From patchwork Fri Apr 9 07:28:40 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dillon Min X-Patchwork-Id: 1464302 X-Patchwork-Delegate: patrice.chotard@st.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=cP2Ml6Xb; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4FGxBl5020z9sW5 for ; Fri, 9 Apr 2021 21:45:03 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id D128580C77; Fri, 9 Apr 2021 13:44:34 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="cP2Ml6Xb"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 1C8EC800D3; Fri, 9 Apr 2021 09:29:07 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.0 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FROM,SPF_HELO_NONE autolearn=ham autolearn_force=no version=3.4.2 Received: from mail-pg1-x532.google.com (mail-pg1-x532.google.com [IPv6:2607:f8b0:4864:20::532]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 1B86F8004F for ; Fri, 9 Apr 2021 09:28:59 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=dillon.minfei@gmail.com Received: by mail-pg1-x532.google.com with SMTP id b17so3233687pgh.7 for ; Fri, 09 Apr 2021 00:28:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=TdUcscY1Pkvyyi6Q4ieyt+lprcxusutD9081mc/brc8=; b=cP2Ml6XbBMsMXvrKhgn1l7zGLXZTbeNhWMACNLz4eZnmaT/ekvqZk4lcGezCbqQ6sB NeybfQ6PnTyS72ikrm9jzP1FOrX1yOSAVGmG5EOGCOhHDny0IHzFCJbiLt6yxxhter5b lYSTWp9I4Jbb65e5U1fyqxA9VyRMuYnks2Dyjgb953yevBf8e2CtLJkUuxvSuRWKVT5F OextWjWIVn3KicG14bs55rvWIYITICsW/vGbyyPW7yIm0UVZDgvEvOW3ADdM/V0vjxvI D7BLx0Q/aBq9inW7xyQQGAjG5BJ3/SAcFYADVULNwQxRlQYVqo5ygfbiJebfmnj0Ik0D su9Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=TdUcscY1Pkvyyi6Q4ieyt+lprcxusutD9081mc/brc8=; b=n2GNVAB2I5w+em8reWP1z+AYc0H2i+ejMk5vtxtqxgNj4E/Bw0qKU82TvvncuCsz1/ A+x/fh4n+RFiZrZOelDbTs015VGzZv2lEKW6ivzlD0vQa+MMx3D9xMaVrRu1e7o82hru MCnDx27jEIuRjdGNKLlAImp/UBWz65NVYrhhsdw30F58SrChiOJEpv7bcUQA5oxpQIMk hz+KyLLiIkeKr+//qHxnmuqNocg6pNEiZ8RLL4urdloUOtsBsDJ58mh5+spiRZCXgThY NA3HrEKNCqdB8CIDVVOlkczGuMsM71//Up5CRfPhJTGRN39Wl+RFkjLMNxBllYZlvBrM /psw== X-Gm-Message-State: AOAM530DXoALRALhLehg2O2LXdfI/dDlPm1fDbZ6hVkxJ6Joh+DtiGDo 7OzEi78QRPgrtVX14CRqTXM= X-Google-Smtp-Source: ABdhPJwxnyu+8mxE6qNQh/K9srgshTY9d9qsSNiQvQvX1cvSIwZvmhcBJUZmIKelWRDPJpaz847t0g== X-Received: by 2002:a63:3ecb:: with SMTP id l194mr11966098pga.146.1617953337437; Fri, 09 Apr 2021 00:28:57 -0700 (PDT) Received: from fmin-OptiPlex-7060.nreal.work ([137.59.103.165]) by smtp.gmail.com with ESMTPSA id j3sm1344432pfc.49.2021.04.09.00.28.53 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Fri, 09 Apr 2021 00:28:56 -0700 (PDT) From: dillon.minfei@gmail.com To: kever.yang@rock-chips.com, andre.przywara@arm.com, priyanka.jain@nxp.com, jagan@amarulasolutions.com, narmstrong@baylibre.com, marex@denx.de, aford173@gmail.com, ioana.ciornei@nxp.com, josip.kelecic@sartura.hr, festevam@gmail.com, hs@denx.de, heiko.stuebner@theobroma-systems.com, u-boot@lists.denx.de, patrice.chotard@foss.st.com, patrick.delaunay@foss.st.com, uboot-stm32@st-md-mailman.stormreply.com, sjg@chromium.org Cc: dillon min Subject: [PATCH v5 1/7] ARM: dts: stm32: split sdram pin & timing parameter into specific board dts Date: Fri, 9 Apr 2021 15:28:40 +0800 Message-Id: <1617953326-3110-2-git-send-email-dillon.minfei@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1617953326-3110-1-git-send-email-dillon.minfei@gmail.com> References: <1617953326-3110-1-git-send-email-dillon.minfei@gmail.com> X-Mailman-Approved-At: Fri, 09 Apr 2021 13:44:19 +0200 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.4 at phobos.denx.de X-Virus-Status: Clean From: dillon min As different boards has their own sdram hw connection, mount different sdram modules, so move sdram timing parameter and pin configuration to their board device tree. Signed-off-by: dillon min Reviewed-by: Patrice Chotard --- v5: no changes arch/arm/dts/stm32h7-u-boot.dtsi | 100 ++---------------------------- arch/arm/dts/stm32h743i-disco-u-boot.dtsi | 98 +++++++++++++++++++++++++++++ arch/arm/dts/stm32h743i-eval-u-boot.dtsi | 98 +++++++++++++++++++++++++++++ 3 files changed, 201 insertions(+), 95 deletions(-) diff --git a/arch/arm/dts/stm32h7-u-boot.dtsi b/arch/arm/dts/stm32h7-u-boot.dtsi index 54dd406..84dc765 100644 --- a/arch/arm/dts/stm32h7-u-boot.dtsi +++ b/arch/arm/dts/stm32h7-u-boot.dtsi @@ -20,6 +20,7 @@ gpio9 = &gpioj; gpio10 = &gpiok; mmc0 = &sdmmc1; + pinctrl0 = &pinctrl; }; soc { @@ -36,30 +37,6 @@ pinctrl-0 = <&fmc_pins>; pinctrl-names = "default"; status = "okay"; - - /* - * Memory configuration from sdram datasheet IS42S32800G-6BLI - * first bank is bank@0 - * second bank is bank@1 - */ - bank1: bank@1 { - st,sdram-control = /bits/ 8 ; - st,sdram-timing = /bits/ 8 ; - st,sdram-refcount = <1539>; - }; }; }; }; @@ -136,77 +113,6 @@ compatible = "st,stm32-gpio"; }; -&pinctrl { - fmc_pins: fmc@0 { - pins { - pinmux = , - , - , - , - , - , - , - - , - , - , - , - , - , - , - , - , - , - , - - , - , - , - , - , - , - , - , - , - , - , - - , - , - , - , - , - , - , - - , - , - , - , - , - , - , - , - , - , - , - - , - , - , - , - , - , - , - , - , - ; - - slew-rate = <3>; - }; - }; -}; - &pwrcfg { u-boot,dm-pre-reloc; }; @@ -222,3 +128,7 @@ &timer5 { u-boot,dm-pre-reloc; }; + +&pinctrl { + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/dts/stm32h743i-disco-u-boot.dtsi b/arch/arm/dts/stm32h743i-disco-u-boot.dtsi index 5965afc..02e28c6 100644 --- a/arch/arm/dts/stm32h743i-disco-u-boot.dtsi +++ b/arch/arm/dts/stm32h743i-disco-u-boot.dtsi @@ -1,3 +1,101 @@ // SPDX-License-Identifier: GPL-2.0+ #include + +&fmc { + + /* + * Memory configuration from sdram datasheet IS42S32800G-6BLI + * first bank is bank@0 + * second bank is bank@1 + */ + bank1: bank@1 { + st,sdram-control = /bits/ 8 ; + st,sdram-timing = /bits/ 8 ; + st,sdram-refcount = <1539>; + }; +}; + +&pinctrl { + fmc_pins: fmc@0 { + pins { + pinmux = , + , + , + , + , + , + , + + , + , + , + , + , + , + , + , + , + , + , + + , + , + , + , + , + , + , + , + , + , + , + + , + , + , + , + , + , + , + + , + , + , + , + , + , + , + , + , + , + , + + , + , + , + , + , + , + , + , + , + ; + + slew-rate = <3>; + }; + }; +}; diff --git a/arch/arm/dts/stm32h743i-eval-u-boot.dtsi b/arch/arm/dts/stm32h743i-eval-u-boot.dtsi index 5965afc..02e28c6 100644 --- a/arch/arm/dts/stm32h743i-eval-u-boot.dtsi +++ b/arch/arm/dts/stm32h743i-eval-u-boot.dtsi @@ -1,3 +1,101 @@ // SPDX-License-Identifier: GPL-2.0+ #include + +&fmc { + + /* + * Memory configuration from sdram datasheet IS42S32800G-6BLI + * first bank is bank@0 + * second bank is bank@1 + */ + bank1: bank@1 { + st,sdram-control = /bits/ 8 ; + st,sdram-timing = /bits/ 8 ; + st,sdram-refcount = <1539>; + }; +}; + +&pinctrl { + fmc_pins: fmc@0 { + pins { + pinmux = , + , + , + , + , + , + , + + , + , + , + , + , + , + , + , + , + , + , + + , + , + , + , + , + , + , + , + , + , + , + + , + , + , + , + , + , + , + + , + , + , + , + , + , + , + , + , + , + , + + , + , + , + , + , + , + , + , + , + ; + + slew-rate = <3>; + }; + }; +}; From patchwork Fri Apr 9 07:28:41 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dillon Min X-Patchwork-Id: 1464303 X-Patchwork-Delegate: patrice.chotard@st.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=SBEoJB5F; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4FGxCB2BcXz9sW1 for ; Fri, 9 Apr 2021 21:45:26 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 8540F81780; Fri, 9 Apr 2021 13:44:42 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="SBEoJB5F"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 64D1F801D4; Fri, 9 Apr 2021 09:29:13 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.0 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FROM,SPF_HELO_NONE autolearn=ham autolearn_force=no version=3.4.2 Received: from mail-pl1-x631.google.com (mail-pl1-x631.google.com [IPv6:2607:f8b0:4864:20::631]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id A9882800D7 for ; Fri, 9 Apr 2021 09:29:03 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=dillon.minfei@gmail.com Received: by mail-pl1-x631.google.com with SMTP id ay2so2324554plb.3 for ; Fri, 09 Apr 2021 00:29:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=q73aZEmo8EMVwAVsr4m8VFBbmZDmV/edr9lpTPbwW5M=; b=SBEoJB5F3MMhmEylq8EqLsi+DlC1FyEQVdTrL1dtZqcUynFlKGUjtm5cymEsfql3XN bD4Bt6bYcIc9myJ+gb9RcZi2mBh2Lp0wAKMKxmxMxXkuIsVXZeHb1kWdVhdQdbuc0A5O +vGBWGTkEKJJLg5YWbziQSmQhBRx98Sle8SCuTsHee4y39RVCSt6fyQ04tDWgy30gC7L 6wuOkWJhtju3eU0vygYnsBrokq7XxyxHfogvlCVccoVJQCv7VEcQir+lS4n1Odhz5BjB FrMVL4sXdFLzVkgEDudpATNi5mbCLtL0lZ5NVSzjZ07kflZFjLU2uKUtXArc2xylZDdT lQPQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=q73aZEmo8EMVwAVsr4m8VFBbmZDmV/edr9lpTPbwW5M=; b=CGSvMa0N4ouznnbg0mkMBvH4OefcPbmPplIYrY7/nLRUBseSiMsqgXvlijoQCxU2Yf SxEIj8/AkxGhHqnEkZWLoUM+iBN8z9EdObVXtgDiniNKRPkRmdfdWoDAqAj6npdC+3Gb CYtBHU6wVTs7ig7cRNhBmxxyHD+JQmexYSVvwEtvCzBBu8GHg519SDF1IwBhTibYidlr kVWLfgxTgGWAsj9FZ+IkkJxO85UFRB7I29zJhpQKt5qaSLLfodCeY6JPUv9YDX0gxtGO bsGz03m4UsP/oowTZf3+lpHN7y/sjgCKTb5DWfiqOQCjYPzRh/iodWr06q4VfTQOzXkW pYhg== X-Gm-Message-State: AOAM53089TF6JUkqfVe83HPhtXOkN6l7eR4m0HXjbhxAOKjZU4R5s1la qkgJc5dDidslXcfp2lqrjfY= X-Google-Smtp-Source: ABdhPJwvKXbEOADFyCqKWB8IjXrgvNG7OXmPWbhCOnD5DUOLENbIGncAb49ZgbQdfNznByaz5LkmOg== X-Received: by 2002:a17:90b:2250:: with SMTP id hk16mr12465905pjb.110.1617953342025; Fri, 09 Apr 2021 00:29:02 -0700 (PDT) Received: from fmin-OptiPlex-7060.nreal.work ([137.59.103.165]) by smtp.gmail.com with ESMTPSA id j3sm1344432pfc.49.2021.04.09.00.28.57 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Fri, 09 Apr 2021 00:29:01 -0700 (PDT) From: dillon.minfei@gmail.com To: kever.yang@rock-chips.com, andre.przywara@arm.com, priyanka.jain@nxp.com, jagan@amarulasolutions.com, narmstrong@baylibre.com, marex@denx.de, aford173@gmail.com, ioana.ciornei@nxp.com, josip.kelecic@sartura.hr, festevam@gmail.com, hs@denx.de, heiko.stuebner@theobroma-systems.com, u-boot@lists.denx.de, patrice.chotard@foss.st.com, patrick.delaunay@foss.st.com, uboot-stm32@st-md-mailman.stormreply.com, sjg@chromium.org Cc: dillon min Subject: [PATCH v5 2/7] ARM: dts: stm32: introduce stm32h7-pinctrl.dtsi to support stm32h750 Date: Fri, 9 Apr 2021 15:28:41 +0800 Message-Id: <1617953326-3110-3-git-send-email-dillon.minfei@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1617953326-3110-1-git-send-email-dillon.minfei@gmail.com> References: <1617953326-3110-1-git-send-email-dillon.minfei@gmail.com> X-Mailman-Approved-At: Fri, 09 Apr 2021 13:44:19 +0200 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.4 at phobos.denx.de X-Virus-Status: Clean From: dillon min This patch is intend to add support stm32h750 value line, just add stm32h7-pinctrl.dtsi for extending, with following changes: - rename stm32h743-pinctrl.dtsi to stm32h7-pinctrl.dtsi - move 'pin-controller' from stm32h7-pinctrl.dtsi to stm32h743.dtsi - update stm32h743i-{disco, eval}.dts to include stm32h7-pinctrl.dtsi Signed-off-by: dillon min Reviewed-by: Patrice Chotard --- v5: no changes arch/arm/dts/stm32h7-pinctrl.dtsi | 185 ++++++++++++++++++++++ arch/arm/dts/stm32h743-pinctrl.dtsi | 306 ------------------------------------ arch/arm/dts/stm32h743.dtsi | 142 +++++++++++++++++ arch/arm/dts/stm32h743i-disco.dts | 2 +- arch/arm/dts/stm32h743i-eval.dts | 2 +- 5 files changed, 329 insertions(+), 308 deletions(-) create mode 100644 arch/arm/dts/stm32h7-pinctrl.dtsi delete mode 100644 arch/arm/dts/stm32h743-pinctrl.dtsi diff --git a/arch/arm/dts/stm32h7-pinctrl.dtsi b/arch/arm/dts/stm32h7-pinctrl.dtsi new file mode 100644 index 0000000..f6968b5 --- /dev/null +++ b/arch/arm/dts/stm32h7-pinctrl.dtsi @@ -0,0 +1,185 @@ +/* + * Copyright 2017 - Alexandre Torgue + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include + +&pinctrl { + + i2c1_pins_a: i2c1-0 { + pins { + pinmux = , /* I2C1_SCL */ + ; /* I2C1_SDA */ + bias-disable; + drive-open-drain; + slew-rate = <0>; + }; + }; + + ethernet_rmii: rmii-0 { + pins { + pinmux = , + , + , + , + , + , + , + , + ; + slew-rate = <2>; + }; + }; + + sdmmc1_b4_pins_a: sdmmc1-b4-0 { + pins { + pinmux = , /* SDMMC1_D0 */ + , /* SDMMC1_D1 */ + , /* SDMMC1_D2 */ + , /* SDMMC1_D3 */ + , /* SDMMC1_CK */ + ; /* SDMMC1_CMD */ + slew-rate = <3>; + drive-push-pull; + bias-disable; + }; + }; + + sdmmc1_b4_od_pins_a: sdmmc1-b4-od-0 { + pins1 { + pinmux = , /* SDMMC1_D0 */ + , /* SDMMC1_D1 */ + , /* SDMMC1_D2 */ + , /* SDMMC1_D3 */ + ; /* SDMMC1_CK */ + slew-rate = <3>; + drive-push-pull; + bias-disable; + }; + pins2{ + pinmux = ; /* SDMMC1_CMD */ + slew-rate = <3>; + drive-open-drain; + bias-disable; + }; + }; + + sdmmc1_b4_sleep_pins_a: sdmmc1-b4-sleep-0 { + pins { + pinmux = , /* SDMMC1_D0 */ + , /* SDMMC1_D1 */ + , /* SDMMC1_D2 */ + , /* SDMMC1_D3 */ + , /* SDMMC1_CK */ + ; /* SDMMC1_CMD */ + }; + }; + + sdmmc1_dir_pins_a: sdmmc1-dir-0 { + pins1 { + pinmux = , /* SDMMC1_D0DIR */ + , /* SDMMC1_D123DIR */ + ; /* SDMMC1_CDIR */ + slew-rate = <3>; + drive-push-pull; + bias-pull-up; + }; + pins2{ + pinmux = ; /* SDMMC1_CKIN */ + bias-pull-up; + }; + }; + + sdmmc1_dir_sleep_pins_a: sdmmc1-dir-sleep-0 { + pins { + pinmux = , /* SDMMC1_D0DIR */ + , /* SDMMC1_D123DIR */ + , /* SDMMC1_CDIR */ + ; /* SDMMC1_CKIN */ + }; + }; + + usart1_pins: usart1-0 { + pins1 { + pinmux = ; /* USART1_TX */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = ; /* USART1_RX */ + bias-disable; + }; + }; + + usart2_pins: usart2-0 { + pins1 { + pinmux = ; /* USART2_TX */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = ; /* USART2_RX */ + bias-disable; + }; + }; + + usbotg_hs_pins_a: usbotg-hs-0 { + pins { + pinmux = , /* ULPI_NXT */ + , /* ULPI_DIR> */ + , /* ULPI_STP> */ + , /* ULPI_CK> */ + , /* ULPI_D0> */ + , /* ULPI_D1> */ + , /* ULPI_D2> */ + , /* ULPI_D3> */ + , /* ULPI_D4> */ + , /* ULPI_D5> */ + , /* ULPI_D6> */ + ; /* ULPI_D7> */ + bias-disable; + drive-push-pull; + slew-rate = <2>; + }; + }; +}; diff --git a/arch/arm/dts/stm32h743-pinctrl.dtsi b/arch/arm/dts/stm32h743-pinctrl.dtsi deleted file mode 100644 index 141083f..0000000 --- a/arch/arm/dts/stm32h743-pinctrl.dtsi +++ /dev/null @@ -1,306 +0,0 @@ -/* - * Copyright 2017 - Alexandre Torgue - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include - -/ { - soc { - pinctrl: pin-controller { - #address-cells = <1>; - #size-cells = <1>; - compatible = "st,stm32h743-pinctrl"; - ranges = <0 0x58020000 0x3000>; - interrupt-parent = <&exti>; - st,syscfg = <&syscfg 0x8>; - pins-are-numbered; - - gpioa: gpio@58020000 { - gpio-controller; - #gpio-cells = <2>; - reg = <0x0 0x400>; - clocks = <&rcc GPIOA_CK>; - st,bank-name = "GPIOA"; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpiob: gpio@58020400 { - gpio-controller; - #gpio-cells = <2>; - reg = <0x400 0x400>; - clocks = <&rcc GPIOB_CK>; - st,bank-name = "GPIOB"; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpioc: gpio@58020800 { - gpio-controller; - #gpio-cells = <2>; - reg = <0x800 0x400>; - clocks = <&rcc GPIOC_CK>; - st,bank-name = "GPIOC"; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpiod: gpio@58020c00 { - gpio-controller; - #gpio-cells = <2>; - reg = <0xc00 0x400>; - clocks = <&rcc GPIOD_CK>; - st,bank-name = "GPIOD"; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpioe: gpio@58021000 { - gpio-controller; - #gpio-cells = <2>; - reg = <0x1000 0x400>; - clocks = <&rcc GPIOE_CK>; - st,bank-name = "GPIOE"; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpiof: gpio@58021400 { - gpio-controller; - #gpio-cells = <2>; - reg = <0x1400 0x400>; - clocks = <&rcc GPIOF_CK>; - st,bank-name = "GPIOF"; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpiog: gpio@58021800 { - gpio-controller; - #gpio-cells = <2>; - reg = <0x1800 0x400>; - clocks = <&rcc GPIOG_CK>; - st,bank-name = "GPIOG"; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpioh: gpio@58021c00 { - gpio-controller; - #gpio-cells = <2>; - reg = <0x1c00 0x400>; - clocks = <&rcc GPIOH_CK>; - st,bank-name = "GPIOH"; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpioi: gpio@58022000 { - gpio-controller; - #gpio-cells = <2>; - reg = <0x2000 0x400>; - clocks = <&rcc GPIOI_CK>; - st,bank-name = "GPIOI"; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpioj: gpio@58022400 { - gpio-controller; - #gpio-cells = <2>; - reg = <0x2400 0x400>; - clocks = <&rcc GPIOJ_CK>; - st,bank-name = "GPIOJ"; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpiok: gpio@58022800 { - gpio-controller; - #gpio-cells = <2>; - reg = <0x2800 0x400>; - clocks = <&rcc GPIOK_CK>; - st,bank-name = "GPIOK"; - interrupt-controller; - #interrupt-cells = <2>; - }; - - i2c1_pins_a: i2c1-0 { - pins { - pinmux = , /* I2C1_SCL */ - ; /* I2C1_SDA */ - bias-disable; - drive-open-drain; - slew-rate = <0>; - }; - }; - - ethernet_rmii: rmii-0 { - pins { - pinmux = , - , - , - , - , - , - , - , - ; - slew-rate = <2>; - }; - }; - - sdmmc1_b4_pins_a: sdmmc1-b4-0 { - pins { - pinmux = , /* SDMMC1_D0 */ - , /* SDMMC1_D1 */ - , /* SDMMC1_D2 */ - , /* SDMMC1_D3 */ - , /* SDMMC1_CK */ - ; /* SDMMC1_CMD */ - slew-rate = <3>; - drive-push-pull; - bias-disable; - }; - }; - - sdmmc1_b4_od_pins_a: sdmmc1-b4-od-0 { - pins1 { - pinmux = , /* SDMMC1_D0 */ - , /* SDMMC1_D1 */ - , /* SDMMC1_D2 */ - , /* SDMMC1_D3 */ - ; /* SDMMC1_CK */ - slew-rate = <3>; - drive-push-pull; - bias-disable; - }; - pins2{ - pinmux = ; /* SDMMC1_CMD */ - slew-rate = <3>; - drive-open-drain; - bias-disable; - }; - }; - - sdmmc1_b4_sleep_pins_a: sdmmc1-b4-sleep-0 { - pins { - pinmux = , /* SDMMC1_D0 */ - , /* SDMMC1_D1 */ - , /* SDMMC1_D2 */ - , /* SDMMC1_D3 */ - , /* SDMMC1_CK */ - ; /* SDMMC1_CMD */ - }; - }; - - sdmmc1_dir_pins_a: sdmmc1-dir-0 { - pins1 { - pinmux = , /* SDMMC1_D0DIR */ - , /* SDMMC1_D123DIR */ - ; /* SDMMC1_CDIR */ - slew-rate = <3>; - drive-push-pull; - bias-pull-up; - }; - pins2{ - pinmux = ; /* SDMMC1_CKIN */ - bias-pull-up; - }; - }; - - sdmmc1_dir_sleep_pins_a: sdmmc1-dir-sleep-0 { - pins { - pinmux = , /* SDMMC1_D0DIR */ - , /* SDMMC1_D123DIR */ - , /* SDMMC1_CDIR */ - ; /* SDMMC1_CKIN */ - }; - }; - - usart1_pins: usart1-0 { - pins1 { - pinmux = ; /* USART1_TX */ - bias-disable; - drive-push-pull; - slew-rate = <0>; - }; - pins2 { - pinmux = ; /* USART1_RX */ - bias-disable; - }; - }; - - usart2_pins: usart2-0 { - pins1 { - pinmux = ; /* USART2_TX */ - bias-disable; - drive-push-pull; - slew-rate = <0>; - }; - pins2 { - pinmux = ; /* USART2_RX */ - bias-disable; - }; - }; - - usbotg_hs_pins_a: usbotg-hs-0 { - pins { - pinmux = , /* ULPI_NXT */ - , /* ULPI_DIR> */ - , /* ULPI_STP> */ - , /* ULPI_CK> */ - , /* ULPI_D0> */ - , /* ULPI_D1> */ - , /* ULPI_D2> */ - , /* ULPI_D3> */ - , /* ULPI_D4> */ - , /* ULPI_D5> */ - , /* ULPI_D6> */ - ; /* ULPI_D7> */ - bias-disable; - drive-push-pull; - slew-rate = <2>; - }; - }; - }; - }; -}; diff --git a/arch/arm/dts/stm32h743.dtsi b/arch/arm/dts/stm32h743.dtsi index e4e4723..8c96698 100644 --- a/arch/arm/dts/stm32h743.dtsi +++ b/arch/arm/dts/stm32h743.dtsi @@ -519,6 +519,148 @@ snps,pbl = <8>; status = "disabled"; }; + + pinctrl: pin-controller@58020000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "st,stm32h743-pinctrl"; + ranges = <0 0x58020000 0x3000>; + interrupt-parent = <&exti>; + st,syscfg = <&syscfg 0x8>; + pins-are-numbered; + + gpioa: gpio@58020000 { + gpio-controller; + #gpio-cells = <2>; + reg = <0x0 0x400>; + clocks = <&rcc GPIOA_CK>; + st,bank-name = "GPIOA"; + interrupt-controller; + #interrupt-cells = <2>; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 0 16>; + }; + + gpiob: gpio@58020400 { + gpio-controller; + #gpio-cells = <2>; + reg = <0x400 0x400>; + clocks = <&rcc GPIOB_CK>; + st,bank-name = "GPIOB"; + interrupt-controller; + #interrupt-cells = <2>; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 16 16>; + }; + + gpioc: gpio@58020800 { + gpio-controller; + #gpio-cells = <2>; + reg = <0x800 0x400>; + clocks = <&rcc GPIOC_CK>; + st,bank-name = "GPIOC"; + interrupt-controller; + #interrupt-cells = <2>; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 32 16>; + }; + + gpiod: gpio@58020c00 { + gpio-controller; + #gpio-cells = <2>; + reg = <0xc00 0x400>; + clocks = <&rcc GPIOD_CK>; + st,bank-name = "GPIOD"; + interrupt-controller; + #interrupt-cells = <2>; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 48 16>; + }; + + gpioe: gpio@58021000 { + gpio-controller; + #gpio-cells = <2>; + reg = <0x1000 0x400>; + clocks = <&rcc GPIOE_CK>; + st,bank-name = "GPIOE"; + interrupt-controller; + #interrupt-cells = <2>; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 64 16>; + }; + + gpiof: gpio@58021400 { + gpio-controller; + #gpio-cells = <2>; + reg = <0x1400 0x400>; + clocks = <&rcc GPIOF_CK>; + st,bank-name = "GPIOF"; + interrupt-controller; + #interrupt-cells = <2>; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 80 16>; + }; + + gpiog: gpio@58021800 { + gpio-controller; + #gpio-cells = <2>; + reg = <0x1800 0x400>; + clocks = <&rcc GPIOG_CK>; + st,bank-name = "GPIOG"; + interrupt-controller; + #interrupt-cells = <2>; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 96 16>; + }; + + gpioh: gpio@58021c00 { + gpio-controller; + #gpio-cells = <2>; + reg = <0x1c00 0x400>; + clocks = <&rcc GPIOH_CK>; + st,bank-name = "GPIOH"; + interrupt-controller; + #interrupt-cells = <2>; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 112 16>; + }; + + gpioi: gpio@58022000 { + gpio-controller; + #gpio-cells = <2>; + reg = <0x2000 0x400>; + clocks = <&rcc GPIOI_CK>; + st,bank-name = "GPIOI"; + interrupt-controller; + #interrupt-cells = <2>; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 128 16>; + }; + + gpioj: gpio@58022400 { + gpio-controller; + #gpio-cells = <2>; + reg = <0x2400 0x400>; + clocks = <&rcc GPIOJ_CK>; + st,bank-name = "GPIOJ"; + interrupt-controller; + #interrupt-cells = <2>; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 144 16>; + }; + + gpiok: gpio@58022800 { + gpio-controller; + #gpio-cells = <2>; + reg = <0x2800 0x400>; + clocks = <&rcc GPIOK_CK>; + st,bank-name = "GPIOK"; + interrupt-controller; + #interrupt-cells = <2>; + ngpios = <8>; + gpio-ranges = <&pinctrl 0 160 8>; + }; + }; }; }; diff --git a/arch/arm/dts/stm32h743i-disco.dts b/arch/arm/dts/stm32h743i-disco.dts index 7927310..3a01ebd 100644 --- a/arch/arm/dts/stm32h743i-disco.dts +++ b/arch/arm/dts/stm32h743i-disco.dts @@ -6,7 +6,7 @@ /dts-v1/; #include "stm32h743.dtsi" -#include "stm32h743-pinctrl.dtsi" +#include "stm32h7-pinctrl.dtsi" / { model = "STMicroelectronics STM32H743i-Discovery board"; diff --git a/arch/arm/dts/stm32h743i-eval.dts b/arch/arm/dts/stm32h743i-eval.dts index 8f39817..38cc7fa 100644 --- a/arch/arm/dts/stm32h743i-eval.dts +++ b/arch/arm/dts/stm32h743i-eval.dts @@ -42,7 +42,7 @@ /dts-v1/; #include "stm32h743.dtsi" -#include "stm32h743-pinctrl.dtsi" +#include "stm32h7-pinctrl.dtsi" / { model = "STMicroelectronics STM32H743i-EVAL board"; From patchwork Fri Apr 9 07:28:42 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dillon Min X-Patchwork-Id: 1464306 X-Patchwork-Delegate: patrice.chotard@st.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=vfEbvT3W; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4FGxGF70b5z9sW1 for ; Fri, 9 Apr 2021 21:48:05 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id EBECB819C3; Fri, 9 Apr 2021 13:47:53 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="vfEbvT3W"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 02896800D3; Fri, 9 Apr 2021 09:29:15 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.0 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FROM,SPF_HELO_NONE autolearn=ham autolearn_force=no version=3.4.2 Received: from mail-pj1-x102b.google.com (mail-pj1-x102b.google.com [IPv6:2607:f8b0:4864:20::102b]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id BA0388004F for ; Fri, 9 Apr 2021 09:29:07 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=dillon.minfei@gmail.com Received: by mail-pj1-x102b.google.com with SMTP id ha17so2455813pjb.2 for ; Fri, 09 Apr 2021 00:29:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=22Yj40BvHmYRX+ww41/Nr1ueDQzAJWYkW3qkeVFuDzo=; b=vfEbvT3WeyFGJ2jGeOemjKyvxDPlWtiv5kt7Kqwy7P/b6mqupK6+RN8ftK0bNYnEnc tl/vLs2BRBsYxxQImeg2IlmhjOfJT4jbSvbpNJo236QpOf+4tnNuBiGSy2f2Vtbj92Fx 8GICcbwwZjdV5R2KHGsvu3KBJfIDQ/r7KBIj++MdY+RJxWC04JOPJuiWnGF6jUx5Qg/b 93i71UIkOufC9pubCnngKhID05CU1ROU+aAsufSRwCe5wnAHM1HfO7rsjrlk98iQSOY6 /DOozW+jk92TkAuswSOStKknx71P487fbvLBdECxvI20SiP2RgW7u+IZTSjbISp8D2pf eQyA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=22Yj40BvHmYRX+ww41/Nr1ueDQzAJWYkW3qkeVFuDzo=; b=R08IqABMTKGB1bWcmPy5Tip7Y5iliuupiiHJBEe01j4jYMOUKuYvCFXLCEiKXpzlh8 zNWodDkC3VaEJu/zFVJ8ZTmp+SyH7q+ZrdssBOA3px4Chpl3BWgob+RJCpyWS+F54ffF IOqMHBXJs42hshwWjNOIpyxx/OTGCnQ8RKRHk0QrzpsyRLWNnA1bU82I328CNLssRR6z oFI3l2VwTfRkJ21XWWzzjTwcJypxqNqOYJF+zth4PEczS6E1yM71I4nC4572HHUMk9Ly QHEXGpyoOkLScuINYV/V+PVOzEFSu9YptIqajBSqsqwjylzmvznx91kwaq25Xr57s46Q 66jw== X-Gm-Message-State: AOAM531PGm3bFDX9un5mFAThfNgxyHKra0rqWY+UkPCw8/aN5mT7kv1y e5Mw1+6Rpnf+QSZKMJxkXsM= X-Google-Smtp-Source: ABdhPJw+liMSGLtmdZKhUx2RDxKdhAyNnd3h4yXeOGaowY3dDJ76ezzxUZ4rJVolnIQS6xas05jKog== X-Received: by 2002:a17:902:c948:b029:e9:8f01:fa8e with SMTP id i8-20020a170902c948b02900e98f01fa8emr6913545pla.37.1617953346213; Fri, 09 Apr 2021 00:29:06 -0700 (PDT) Received: from fmin-OptiPlex-7060.nreal.work ([137.59.103.165]) by smtp.gmail.com with ESMTPSA id j3sm1344432pfc.49.2021.04.09.00.29.02 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Fri, 09 Apr 2021 00:29:05 -0700 (PDT) From: dillon.minfei@gmail.com To: kever.yang@rock-chips.com, andre.przywara@arm.com, priyanka.jain@nxp.com, jagan@amarulasolutions.com, narmstrong@baylibre.com, marex@denx.de, aford173@gmail.com, ioana.ciornei@nxp.com, josip.kelecic@sartura.hr, festevam@gmail.com, hs@denx.de, heiko.stuebner@theobroma-systems.com, u-boot@lists.denx.de, patrice.chotard@foss.st.com, patrick.delaunay@foss.st.com, uboot-stm32@st-md-mailman.stormreply.com, sjg@chromium.org Cc: dillon min Subject: [PATCH v5 3/7] ARM: dts: stm32: add new instances for stm32h743 MCU Date: Fri, 9 Apr 2021 15:28:42 +0800 Message-Id: <1617953326-3110-4-git-send-email-dillon.minfei@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1617953326-3110-1-git-send-email-dillon.minfei@gmail.com> References: <1617953326-3110-1-git-send-email-dillon.minfei@gmail.com> X-Mailman-Approved-At: Fri, 09 Apr 2021 13:44:19 +0200 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.4 at phobos.denx.de X-Virus-Status: Clean From: dillon min Some instances are missing in current support of stm32h743 MCU. This commit adds usart3/uart4 and sdmmc2 support. Signed-off-by: dillon min Reviewed-by: Patrice Chotard --- v5: no changes arch/arm/dts/stm32h743.dtsi | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/arch/arm/dts/stm32h743.dtsi b/arch/arm/dts/stm32h743.dtsi index 8c96698..77a8aef 100644 --- a/arch/arm/dts/stm32h743.dtsi +++ b/arch/arm/dts/stm32h743.dtsi @@ -99,6 +99,22 @@ clocks = <&rcc USART2_CK>; }; + usart3: serial@40004800 { + compatible = "st,stm32h7-uart"; + reg = <0x40004800 0x400>; + interrupts = <39>; + status = "disabled"; + clocks = <&rcc USART3_CK>; + }; + + uart4: serial@40004c00 { + compatible = "st,stm32h7-uart"; + reg = <0x40004c00 0x400>; + interrupts = <52>; + status = "disabled"; + clocks = <&rcc UART4_CK>; + }; + i2c1: i2c@40005400 { compatible = "st,stm32f7-i2c"; #address-cells = <1>; @@ -332,6 +348,20 @@ max-frequency = <120000000>; }; + sdmmc2: sdmmc@48022400 { + compatible = "arm,pl18x", "arm,primecell"; + arm,primecell-periphid = <0x10153180>; + reg = <0x48022400 0x400>; + interrupts = <124>; + interrupt-names = "cmd_irq"; + clocks = <&rcc SDMMC2_CK>; + clock-names = "apb_pclk"; + resets = <&rcc STM32H7_AHB2_RESET(SDMMC2)>; + cap-sd-highspeed; + cap-mmc-highspeed; + max-frequency = <120000000>; + }; + exti: interrupt-controller@58000000 { compatible = "st,stm32h7-exti"; interrupt-controller; From patchwork Fri Apr 9 07:28:43 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dillon Min X-Patchwork-Id: 1464307 X-Patchwork-Delegate: patrice.chotard@st.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=PWpFz/up; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4FGxGf48nnz9sWW for ; Fri, 9 Apr 2021 21:48:26 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 9FC208187F; Fri, 9 Apr 2021 13:48:17 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="PWpFz/up"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id DEE26800D3; Fri, 9 Apr 2021 09:29:18 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.0 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FROM,SPF_HELO_NONE autolearn=ham autolearn_force=no version=3.4.2 Received: from mail-pf1-x433.google.com (mail-pf1-x433.google.com [IPv6:2607:f8b0:4864:20::433]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 277728017D for ; Fri, 9 Apr 2021 09:29:12 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=dillon.minfei@gmail.com Received: by mail-pf1-x433.google.com with SMTP id a85so3227408pfa.0 for ; Fri, 09 Apr 2021 00:29:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=e0gmWoZZ8tS0re+uwOYBXni4qOAl589bJB7kiJzLxmg=; b=PWpFz/up5OW+jCToj/fdCCI7GfwXjH7C6cxfWwi3UwVeIPzt+pyI8x0av7p3uAbsgz k1hkD+ijp1yeyKvBJhNWjOwHKGaD6Ov1tONPfIHBWIkRN5tGe10d8Xy4fb3BpFZDMKFs QLOH6WzsAkoEYuph05hOPB0YwC5RaSanrpTyUNkcXPnkIQg4B+LGpI5RTfFkRXp5N4KJ FZOzUpgtKWl3J9qqSMngts9EWm6i7RVjCzjO3Yg7K5YDAaw16Uo9+I+tQ1kPBOdG482y 1MRPzFKBLpG0lmmA0WVQwyiqncNu6w0/lyXzvJl0f1Jv9ma+11g9RccVmOV26ibt73Rz Q9/A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=e0gmWoZZ8tS0re+uwOYBXni4qOAl589bJB7kiJzLxmg=; b=hFpQHkSC2wBruQlF9WRZP7pz+VktKfMxrOQGsNaOeLuB9j81hT5vFauJduhXg80fl0 nH8vQlsIS7mwXSJT7myTGmVQuX/kMbhw7lo6EHswuF0y6mlPbMwKJAXFUfL+3tp6YTdK 3xUZLtP0v/hclx4VTgjTQCa6rRTL7DODxbKfdLHuu6XY3GIzryOJZofT62EwIqsCPpHo d2d/pK3SY0+C7eZFd0THrUVOtmnmrhtWHNyAxabOHUZUf7ypom0bwJslOdON0zTpC7M3 DfK8GjyHEXcaGSba9GqtA2oPYHMpLHHeOuD7y761s62NhjG78FKEitZpKMvU+rYQofFE 6MdQ== X-Gm-Message-State: AOAM530ohCRujooCiSdWy3ecTzbzDedFIT4Us4cZ0U+IdTkp5gph2c/R eDxnDHjcnJgELiNDf6lOSwI= X-Google-Smtp-Source: ABdhPJz0m8lrR5z+5UKSe6q8AC/cFll7WQAXdIPh0IAmX6OnBrGV+KgK6b1DX1oUYZgKx8S6HVEM5g== X-Received: by 2002:a63:fd44:: with SMTP id m4mr12019144pgj.233.1617953350370; Fri, 09 Apr 2021 00:29:10 -0700 (PDT) Received: from fmin-OptiPlex-7060.nreal.work ([137.59.103.165]) by smtp.gmail.com with ESMTPSA id j3sm1344432pfc.49.2021.04.09.00.29.06 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Fri, 09 Apr 2021 00:29:10 -0700 (PDT) From: dillon.minfei@gmail.com To: kever.yang@rock-chips.com, andre.przywara@arm.com, priyanka.jain@nxp.com, jagan@amarulasolutions.com, narmstrong@baylibre.com, marex@denx.de, aford173@gmail.com, ioana.ciornei@nxp.com, josip.kelecic@sartura.hr, festevam@gmail.com, hs@denx.de, heiko.stuebner@theobroma-systems.com, u-boot@lists.denx.de, patrice.chotard@foss.st.com, patrick.delaunay@foss.st.com, uboot-stm32@st-md-mailman.stormreply.com, sjg@chromium.org Cc: dillon min Subject: [PATCH v5 4/7] ARM: dts: stm32: fix i2c node typo in stm32h743, update dmamux1 register Date: Fri, 9 Apr 2021 15:28:43 +0800 Message-Id: <1617953326-3110-5-git-send-email-dillon.minfei@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1617953326-3110-1-git-send-email-dillon.minfei@gmail.com> References: <1617953326-3110-1-git-send-email-dillon.minfei@gmail.com> X-Mailman-Approved-At: Fri, 09 Apr 2021 13:44:19 +0200 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.4 at phobos.denx.de X-Virus-Status: Clean From: dillon min Replace upper case by lower case in i2c nodes name. update dmamux1 register range. Signed-off-by: dillon min Reviewed-by: Patrice Chotard --- v5: no changes arch/arm/dts/stm32h743.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/dts/stm32h743.dtsi b/arch/arm/dts/stm32h743.dtsi index 77a8aef..ed68575 100644 --- a/arch/arm/dts/stm32h743.dtsi +++ b/arch/arm/dts/stm32h743.dtsi @@ -139,7 +139,7 @@ status = "disabled"; }; - i2c3: i2c@40005C00 { + i2c3: i2c@40005c00 { compatible = "st,stm32f7-i2c"; #address-cells = <1>; #size-cells = <0>; @@ -254,7 +254,7 @@ dmamux1: dma-router@40020800 { compatible = "st,stm32h7-dmamux"; - reg = <0x40020800 0x1c>; + reg = <0x40020800 0x40>; #dma-cells = <3>; dma-channels = <16>; dma-requests = <128>; @@ -386,7 +386,7 @@ status = "disabled"; }; - i2c4: i2c@58001C00 { + i2c4: i2c@58001c00 { compatible = "st,stm32f7-i2c"; #address-cells = <1>; #size-cells = <0>; From patchwork Fri Apr 9 07:28:44 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dillon Min X-Patchwork-Id: 1464308 X-Patchwork-Delegate: patrice.chotard@st.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=V3UBt3ny; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4FGxH76Q9Tz9sW1 for ; Fri, 9 Apr 2021 21:48:51 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 1092881780; Fri, 9 Apr 2021 13:48:39 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="V3UBt3ny"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 69A39800D3; Fri, 9 Apr 2021 09:29:25 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.0 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FROM,SPF_HELO_NONE autolearn=ham autolearn_force=no version=3.4.2 Received: from mail-pf1-x42a.google.com (mail-pf1-x42a.google.com [IPv6:2607:f8b0:4864:20::42a]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id ED0F28004F for ; Fri, 9 Apr 2021 09:29:15 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=dillon.minfei@gmail.com Received: by mail-pf1-x42a.google.com with SMTP id w8so194581pfn.9 for ; Fri, 09 Apr 2021 00:29:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=DGauWPjVZ4QNcdzQNKb7bCcrbIGVaCGyIzjLExWEfkU=; b=V3UBt3nyV4VqPZdnmNk55gaIrTf2v5g9eKgdWRcRN6F0TGLNynpw6qtfcMO9yM+7fy mPg7wOQVNBT/iLkJJ/gjM0EzQyuGJc8TWKhG5o8SRbTVLjAqCjIWZJEF0dY2dCuP9eYy ywX3Y2CPSyJp9n/8a7M9f4nOjXz8SX3lCjh5YYhFjRi2qWhO+zCOJZBo2OlPi65JrABA 1LrwSZ5XY5echn01dF2DXfl+fCyadJ3noiwkHWsbbDgKT1qoWKOPCvMuSXpEs6Bh6Pa+ oGtYJK9D4CZECotyAO/9nS0cnyu+Rp3J8K9ViKHj00H7MV7rzfVHwazBv+sW0QVzZ+5R 7RvA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=DGauWPjVZ4QNcdzQNKb7bCcrbIGVaCGyIzjLExWEfkU=; b=Fi/hPQVXJbdfUwsxIBKSsLAly7beJRXXg/VFaJYznrLr6sKdTbk3qMMGNYWx0z4tpW qM2fs7W7s5hgqfq8K/o96OACH6HoWONZ51T9RUhMnGPfRAhgA3rZPMxv5YqwMNdOtezX /VaoGP1vM9vLWNVxybmbm9rbytru74caJ7yldRWonPnCGVledpp4vWTyptIH28WFZ6Co jEE8hY/8eipgUZZbz2avz8LzDGB8o7MaYXAPvf5NcOZpmOu1e8ICUqyG+ZhIqZ5CEAyI XInUUXtvgusX4VLnXFQ5yTPnrdwHiLF+9tyo0kFo6gsv0m4Mz0UAg5T5vL/SvuVSI3du A9lw== X-Gm-Message-State: AOAM5300YzJv7b1AJB3yVmlVR6ZgcMP60C2IJRDnM6tq02Qm6sDpaVn8 wUpIMlqCh7T8IFBor73MRGM= X-Google-Smtp-Source: ABdhPJz6VL01yxK5URiOyyIwpiXPYEDc8TrpEOEbE+5OspJXf4ejSxuDu3LiT8hE6UnwSdhSGbBOWw== X-Received: by 2002:a05:6a00:1510:b029:221:cd7d:90d8 with SMTP id q16-20020a056a001510b0290221cd7d90d8mr11111607pfu.61.1617953354525; Fri, 09 Apr 2021 00:29:14 -0700 (PDT) Received: from fmin-OptiPlex-7060.nreal.work ([137.59.103.165]) by smtp.gmail.com with ESMTPSA id j3sm1344432pfc.49.2021.04.09.00.29.10 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Fri, 09 Apr 2021 00:29:14 -0700 (PDT) From: dillon.minfei@gmail.com To: kever.yang@rock-chips.com, andre.przywara@arm.com, priyanka.jain@nxp.com, jagan@amarulasolutions.com, narmstrong@baylibre.com, marex@denx.de, aford173@gmail.com, ioana.ciornei@nxp.com, josip.kelecic@sartura.hr, festevam@gmail.com, hs@denx.de, heiko.stuebner@theobroma-systems.com, u-boot@lists.denx.de, patrice.chotard@foss.st.com, patrick.delaunay@foss.st.com, uboot-stm32@st-md-mailman.stormreply.com, sjg@chromium.org Cc: dillon min Subject: [PATCH v5 5/7] ARM: dts: stm32: add support for art-pi board based on stm32h750xbh6 Date: Fri, 9 Apr 2021 15:28:44 +0800 Message-Id: <1617953326-3110-6-git-send-email-dillon.minfei@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1617953326-3110-1-git-send-email-dillon.minfei@gmail.com> References: <1617953326-3110-1-git-send-email-dillon.minfei@gmail.com> X-Mailman-Approved-At: Fri, 09 Apr 2021 13:44:19 +0200 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.4 at phobos.denx.de X-Virus-Status: Clean From: dillon min This patchset has following changes: - introduce stm32h750.dtsi to support stm32h750 value line - add pin groups for usart3/uart4/spi1/sdmmc2 - add stm32h750i-art-pi.dtb (arch/arm/boot/dts/Makefile) - add stm32h750i-art-pi.dts to support art-pi board - add stm32h750i-art-pi-u-boot.dtsi to support art-pi board (u-boot) art-pi board component: - 8MiB qspi flash - 16MiB spi flash - 32MiB sdram - ap6212 wifi&bt&fm the detail board information can be found at: https://art-pi.gitee.io/website/ Signed-off-by: dillon min Reviewed-by: Patrice Chotard --- v5: no changes arch/arm/dts/Makefile | 3 +- arch/arm/dts/stm32h7-pinctrl.dtsi | 89 ++++++++++++++ arch/arm/dts/stm32h750.dtsi | 5 + arch/arm/dts/stm32h750i-art-pi-u-boot.dtsi | 81 +++++++++++++ arch/arm/dts/stm32h750i-art-pi.dts | 188 +++++++++++++++++++++++++++++ include/dt-bindings/memory/stm32-sdram.h | 2 + 6 files changed, 367 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/stm32h750.dtsi create mode 100644 arch/arm/dts/stm32h750i-art-pi-u-boot.dtsi create mode 100644 arch/arm/dts/stm32h750i-art-pi.dts diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index c671082..0f54801 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -454,7 +454,8 @@ dtb-$(CONFIG_STM32F7) += stm32f746-disco.dtb \ stm32f769-disco.dtb \ stm32746g-eval.dtb dtb-$(CONFIG_STM32H7) += stm32h743i-disco.dtb \ - stm32h743i-eval.dtb + stm32h743i-eval.dtb \ + stm32h750i-art-pi.dtb dtb-$(CONFIG_MACH_SUN4I) += \ sun4i-a10-a1000.dtb \ diff --git a/arch/arm/dts/stm32h7-pinctrl.dtsi b/arch/arm/dts/stm32h7-pinctrl.dtsi index f6968b5..aefa324 100644 --- a/arch/arm/dts/stm32h7-pinctrl.dtsi +++ b/arch/arm/dts/stm32h7-pinctrl.dtsi @@ -137,6 +137,80 @@ }; }; + sdmmc2_b4_pins_a: sdmmc2-b4-0 { + pins { + pinmux = , /* SDMMC1_D0 */ + , /* SDMMC1_D1 */ + , /* SDMMC1_D2 */ + , /* SDMMC1_D3 */ + , /* SDMMC1_CK */ + ; /* SDMMC1_CMD */ + slew-rate = <3>; + drive-push-pull; + bias-disable; + }; + }; + + sdmmc2_b4_od_pins_a: sdmmc2-b4-od-0 { + pins1 { + pinmux = , /* SDMMC2_D0 */ + , /* SDMMC1_D1 */ + , /* SDMMC1_D2 */ + , /* SDMMC1_D3 */ + ; /* SDMMC1_CK */ + slew-rate = <3>; + drive-push-pull; + bias-disable; + }; + pins2{ + pinmux = ; /* SDMMC1_CMD */ + slew-rate = <3>; + drive-open-drain; + bias-disable; + }; + }; + + sdmmc2_b4_sleep_pins_a: sdmmc2-b4-sleep-0 { + pins { + pinmux = , /* SDMMC1_D0 */ + , /* SDMMC1_D1 */ + , /* SDMMC1_D2 */ + , /* SDMMC1_D3 */ + , /* SDMMC1_CK */ + ; /* SDMMC1_CMD */ + }; + }; + + spi1_pins: spi1-0 { + pins1 { + pinmux = , + /* SPI1_CLK */ + ; + /* SPI1_MOSI */ + bias-disable; + drive-push-pull; + slew-rate = <2>; + }; + pins2 { + pinmux = ; + /* SPI1_MISO */ + bias-disable; + }; + }; + + uart4_pins: uart4-0 { + pins1 { + pinmux = ; /* UART4_TX */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = ; /* UART4_RX */ + bias-disable; + }; + }; + usart1_pins: usart1-0 { pins1 { pinmux = ; /* USART1_TX */ @@ -163,6 +237,21 @@ }; }; + usart3_pins: usart3-0 { + pins1 { + pinmux = , /* USART3_TX */ + ; /* USART3_RTS_DE */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = , /* USART3_RX */ + ; /* USART3_CTS_NSS */ + bias-disable; + }; + }; + usbotg_hs_pins_a: usbotg-hs-0 { pins { pinmux = , /* ULPI_NXT */ diff --git a/arch/arm/dts/stm32h750.dtsi b/arch/arm/dts/stm32h750.dtsi new file mode 100644 index 0000000..99533f3 --- /dev/null +++ b/arch/arm/dts/stm32h750.dtsi @@ -0,0 +1,5 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* Copyright (C) STMicroelectronics 2021 - All Rights Reserved */ + +#include "stm32h743.dtsi" + diff --git a/arch/arm/dts/stm32h750i-art-pi-u-boot.dtsi b/arch/arm/dts/stm32h750i-art-pi-u-boot.dtsi new file mode 100644 index 0000000..326a553 --- /dev/null +++ b/arch/arm/dts/stm32h750i-art-pi-u-boot.dtsi @@ -0,0 +1,81 @@ +// SPDX-License-Identifier: GPL-2.0+ + +#include + +&fmc { + /* + * Memory configuration from sdram datasheet W9825G6KH + * first bank is bank@0 + * second bank is bank@1 + */ + bank1: bank@0 { + st,sdram-control = /bits/ 8 ; + st,sdram-timing = /bits/ 8 ; + st,sdram-refcount = <677>; + }; +}; + +&pinctrl { + fmc_pins: fmc@0 { + pins { + pinmux = , + , + , + , + , + , + , + + , + , + , + , + , + , + , + , + , + , + , + + , + , + , + , + , + , + , + , + , + , + , + + , + , + , + , + , + , + , + + , + , + ; + + slew-rate = <3>; + }; + }; +}; diff --git a/arch/arm/dts/stm32h750i-art-pi.dts b/arch/arm/dts/stm32h750i-art-pi.dts new file mode 100644 index 0000000..2a4d1cb --- /dev/null +++ b/arch/arm/dts/stm32h750i-art-pi.dts @@ -0,0 +1,188 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * Copyright 2021 - Dillon Min + * + */ + +/dts-v1/; +#include "stm32h750.dtsi" +#include "stm32h7-pinctrl.dtsi" +#include +#include + +/ { + model = "RT-Thread STM32H750i-ART-PI board"; + compatible = "st,stm32h750i-art-pi", "st,stm32h750"; + + chosen { + bootargs = "root=/dev/ram"; + stdout-path = "serial0:2000000n8"; + }; + + memory@c0000000 { + device_type = "memory"; + reg = <0xc0000000 0x2000000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + linux,cma { + compatible = "shared-dma-pool"; + no-map; + size = <0x100000>; + linux,dma-default; + }; + }; + + aliases { + serial0 = &uart4; + serial1 = &usart3; + }; + + leds { + compatible = "gpio-leds"; + led-red { + gpios = <&gpioi 8 0>; + }; + led-green { + gpios = <&gpioc 15 0>; + linux,default-trigger = "heartbeat"; + }; + }; + + v3v3: regulator-v3v3 { + compatible = "regulator-fixed"; + regulator-name = "v3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + wlan_pwr: regulator-wlan { + compatible = "regulator-fixed"; + + regulator-name = "wl-reg"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpios = <&gpioc 13 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; + +&clk_hse { + clock-frequency = <25000000>; +}; + +&dma1 { + status = "okay"; +}; + +&dma2 { + status = "okay"; +}; + +&mac { + status = "disabled"; + pinctrl-0 = <ðernet_rmii>; + pinctrl-names = "default"; + phy-mode = "rmii"; + phy-handle = <&phy0>; + + mdio0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + phy0: ethernet-phy@0 { + reg = <0>; + }; + }; +}; + +&sdmmc1 { + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc1_b4_pins_a>; + pinctrl-1 = <&sdmmc1_b4_od_pins_a>; + pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>; + broken-cd; + st,neg-edge; + bus-width = <4>; + vmmc-supply = <&v3v3>; + status = "okay"; +}; + +&sdmmc2 { + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc2_b4_pins_a>; + pinctrl-1 = <&sdmmc2_b4_od_pins_a>; + pinctrl-2 = <&sdmmc2_b4_sleep_pins_a>; + broken-cd; + non-removable; + st,neg-edge; + bus-width = <4>; + vmmc-supply = <&wlan_pwr>; + status = "okay"; + + #address-cells = <1>; + #size-cells = <0>; + brcmf: bcrmf@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + }; +}; + +&spi1 { + status = "okay"; + pinctrl-0 = <&spi1_pins>; + pinctrl-names = "default"; + cs-gpios = <&gpioa 4 GPIO_ACTIVE_LOW>; + dmas = <&dmamux1 37 0x400 0x05>, + <&dmamux1 38 0x400 0x05>; + dma-names = "rx", "tx"; + + flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "winbond,w25q128", "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <80000000>; + + partition@0 { + label = "root filesystem"; + reg = <0 0x1000000>; + }; + }; +}; + +&usart2 { + pinctrl-0 = <&usart2_pins>; + pinctrl-names = "default"; + status = "disabled"; +}; + +&usart3 { + pinctrl-names = "default"; + pinctrl-0 = <&usart3_pins>; + dmas = <&dmamux1 45 0x400 0x05>, + <&dmamux1 46 0x400 0x05>; + dma-names = "rx", "tx"; + st,hw-flow-ctrl; + status = "okay"; + + bluetooth { + compatible = "brcm,bcm43438-bt"; + host-wakeup-gpios = <&gpioc 0 GPIO_ACTIVE_HIGH>; + device-wakeup-gpios = <&gpioi 10 GPIO_ACTIVE_HIGH>; + shutdown-gpios = <&gpioi 11 GPIO_ACTIVE_HIGH>; + max-speed = <115200>; + }; +}; + +&uart4 { + pinctrl-0 = <&uart4_pins>; + pinctrl-names = "default"; + status = "okay"; +}; diff --git a/include/dt-bindings/memory/stm32-sdram.h b/include/dt-bindings/memory/stm32-sdram.h index ab91d2b..90ef2e1 100644 --- a/include/dt-bindings/memory/stm32-sdram.h +++ b/include/dt-bindings/memory/stm32-sdram.h @@ -34,8 +34,10 @@ #define TXSR_1 (1 - 1) #define TXSR_6 (6 - 1) #define TXSR_7 (7 - 1) +#define TXSR_8 (8 - 1) #define TRAS_1 (1 - 1) #define TRAS_4 (4 - 1) +#define TRAS_6 (6 - 1) #define TRC_6 (6 - 1) #define TWR_1 (1 - 1) #define TWR_2 (2 - 1) From patchwork Fri Apr 9 07:28:45 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dillon Min X-Patchwork-Id: 1464309 X-Patchwork-Delegate: patrice.chotard@st.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=JgxZ0qZv; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4FGxHS6z4xz9sW1 for ; Fri, 9 Apr 2021 21:49:08 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 9C31181C84; Fri, 9 Apr 2021 13:48:56 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="JgxZ0qZv"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 5D09A80050; Fri, 9 Apr 2021 09:29:26 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.0 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FROM,SPF_HELO_NONE autolearn=ham autolearn_force=no version=3.4.2 Received: from mail-pg1-x52c.google.com (mail-pg1-x52c.google.com [IPv6:2607:f8b0:4864:20::52c]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 1EDAA801D4 for ; Fri, 9 Apr 2021 09:29:20 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=dillon.minfei@gmail.com Received: by mail-pg1-x52c.google.com with SMTP id q10so3238842pgj.2 for ; Fri, 09 Apr 2021 00:29:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Y4M11X15i0Bp4xMyiHxKNtu/p+u/Lz6TbAiq1qNsDk8=; b=JgxZ0qZvYIe+zrCR820Ut+5a1k8OWogxkG/xun3jtSxHgdWqJylE+Y1IVxtJ+IPYiM xrJAKfGfR/FPemqlNvE+U8lxTeWZQ0vf0zWC/wFiGTsraFJHqMntuPlduLSDm+YZIUNr Swzbdm1XjeAmK7zoni1YvD3Kb5l4zO3/kl8R9E7h07+ePwUAh2TpkXqItg2XMEhCL4Tu vNOxYCbEwCg+ZHPmonoyyEMEFbj3jQGXKOWE06/C7PErnnXa+yMMNF55JFsBriipo2Ky GJ+K9vbDRyhnuRivC5Vuki/sbZ4kViFsFnBHXFY+KgoiN5wHEMDJtEPAI96KJ/lXoF8H d3CQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Y4M11X15i0Bp4xMyiHxKNtu/p+u/Lz6TbAiq1qNsDk8=; b=irOKzoVJyGdf8LotwdnP7UI125/f6xtftjvAnolYKVVS4/0kHF5Lv1dtRVf+SruvYG M0STu/4f4T5HMPSwR72cHhlhFuS5S3akCAA9jBKkugm7Oqy/GooqCbt++lSjSlO2Ili5 kGaWh/aS9tE11NUsByXYLt8oOb2xIMWN+73jd9nVFy/2zd8LC3KXHs1XK9/N5DLIGxi6 StInwDb/RhPGsgUIYstEwQm8dIlCF65wME00x5tskvNwGOnYKQGE/DMfDspjV1Ip5EA/ R/TkFR7DhXyN0w/LIEaWkF8fDokY0R/YEpIAJX6nP86qNDyDNQM31FJDqegpr0HAdi+q 9+pw== X-Gm-Message-State: AOAM53393IOYDguJKh0U3lS0ResI69uyvPn/Y0K0MpntfxGSlaFBGZSy gd3bgAGd+qH/sUz3L1d9Xxw= X-Google-Smtp-Source: ABdhPJxU7NnkNQ0GHy0G2E2rBsAsdBqT/A8Ztc568+AFRDQITzop6/k9udOHe+FSp7EFyiMmGWc4ag== X-Received: by 2002:a62:8c13:0:b029:241:db2a:11b6 with SMTP id m19-20020a628c130000b0290241db2a11b6mr11437407pfd.74.1617953358724; Fri, 09 Apr 2021 00:29:18 -0700 (PDT) Received: from fmin-OptiPlex-7060.nreal.work ([137.59.103.165]) by smtp.gmail.com with ESMTPSA id j3sm1344432pfc.49.2021.04.09.00.29.14 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Fri, 09 Apr 2021 00:29:18 -0700 (PDT) From: dillon.minfei@gmail.com To: kever.yang@rock-chips.com, andre.przywara@arm.com, priyanka.jain@nxp.com, jagan@amarulasolutions.com, narmstrong@baylibre.com, marex@denx.de, aford173@gmail.com, ioana.ciornei@nxp.com, josip.kelecic@sartura.hr, festevam@gmail.com, hs@denx.de, heiko.stuebner@theobroma-systems.com, u-boot@lists.denx.de, patrice.chotard@foss.st.com, patrick.delaunay@foss.st.com, uboot-stm32@st-md-mailman.stormreply.com, sjg@chromium.org Cc: dillon min Subject: [PATCH v5 6/7] ram: stm32: fix strsep failed on read only memory Date: Fri, 9 Apr 2021 15:28:45 +0800 Message-Id: <1617953326-3110-7-git-send-email-dillon.minfei@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1617953326-3110-1-git-send-email-dillon.minfei@gmail.com> References: <1617953326-3110-1-git-send-email-dillon.minfei@gmail.com> X-Mailman-Approved-At: Fri, 09 Apr 2021 13:44:19 +0200 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.4 at phobos.denx.de X-Virus-Status: Clean From: dillon min strsep will change data from original memory address, in case the memory is in non-sdram/sram place, will run into a bug(hang at SDRAM: ) just add a temporary array to store bank_name[] to fix this bug. Signed-off-by: dillon min Reviewed-by: Patrice Chotard --- v5: no changes drivers/ram/stm32_sdram.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/ram/stm32_sdram.c b/drivers/ram/stm32_sdram.c index 540ad85..3e25cc7 100644 --- a/drivers/ram/stm32_sdram.c +++ b/drivers/ram/stm32_sdram.c @@ -268,6 +268,7 @@ static int stm32_fmc_of_to_plat(struct udevice *dev) u32 swp_fmc; ofnode bank_node; char *bank_name; + char _bank_name[128] = {0}; u8 bank = 0; int ret; @@ -300,6 +301,8 @@ static int stm32_fmc_of_to_plat(struct udevice *dev) dev_for_each_subnode(bank_node, dev) { /* extract the bank index from DT */ bank_name = (char *)ofnode_get_name(bank_node); + strlcpy(_bank_name, bank_name, sizeof(_bank_name)); + bank_name = (char *)_bank_name; strsep(&bank_name, "@"); if (!bank_name) { pr_err("missing sdram bank index"); From patchwork Fri Apr 9 07:28:46 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dillon Min X-Patchwork-Id: 1464310 X-Patchwork-Delegate: patrice.chotard@st.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=i4+l+mfL; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4FGxHs48Szz9sWD for ; Fri, 9 Apr 2021 21:49:29 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 43DB9818C7; Fri, 9 Apr 2021 13:49:19 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="i4+l+mfL"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id DAF7A800D7; Fri, 9 Apr 2021 09:29:30 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.0 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FROM,SPF_HELO_NONE autolearn=ham autolearn_force=no version=3.4.2 Received: from mail-pl1-x634.google.com (mail-pl1-x634.google.com [IPv6:2607:f8b0:4864:20::634]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 42C13801F3 for ; Fri, 9 Apr 2021 09:29:24 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=dillon.minfei@gmail.com Received: by mail-pl1-x634.google.com with SMTP id d8so2307162plh.11 for ; Fri, 09 Apr 2021 00:29:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=39RiiSpYrhJfD/iyTXVMBAk0rH+GfuzVa/eb9MzR/Cw=; b=i4+l+mfL/iVTLW363aElrtf8Jlek0cJMvz2TZbasNVhfVPEj7e1iPxXYNsWIlKpvdT t5WuGoZPzrmioUJGhSzkQDUJ/ej5OLqi06uDRPkV29AyO5NXI29W5WW6bL1kth+F2hZ7 p6xp3CqYh7AdfUgHbVNZsYtOPlGh90/ICCSckJoFwQoT/OKX3adifJ9mOl8parLtmNlF KrEmzBxr84lW5DBrE8BLLrG4Owgg/96WeWqy5gVGoVj49mAHeekq57rNkI1/Z85CN0mu +eMj1OvSjvxsL/Vf+ocrH/hQppPXtIWE8xFiqwaSsyvToiuQmi1c2ZE4CFG9fS0wObM+ rnKQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=39RiiSpYrhJfD/iyTXVMBAk0rH+GfuzVa/eb9MzR/Cw=; b=CD4wT8PrtTjuCWI6ZWGgvgkkHlX7znsiE56ZNYqXWYx863lo8CmNUizLhCsgiXvMP7 WloxeZx1HyKLoSYLoIBpz8Khs7d3ySwwiKzNVNK94PdgGL6s8wtkecJJ4UvRNswSlRht N0m8q4k4sQhhRXRIrpoFv3ADwrsRmiiSuDlBX0EAM3vS55lhIpR5e6pgOp29QQOJsJUA wdMgycm3CADJlrppfsinrRBhEdqF9PI61qyOKTzMyw8CJ/ymxSFwKuGgyfZ10FC4RgQc ru2zNFdDK01DCRxALLyq4P3OqCdZTFs5MmkD4BDS+rEwatcsf98yrVLxL+kW727cgjpz 70PA== X-Gm-Message-State: AOAM533JqLOhRqCoB2Vd7ZuODmxwrNAug5dJSfNdnuAIi2smwmgb05Jh jxlYBehSAvy/tyeaxw9VXUg= X-Google-Smtp-Source: ABdhPJyNd/8z9w5OkmkHw1NoJ0JF02RwP8zojndJrvxo1tnNyw16HLCn/9/pL5mB3fLscGtX5UMsqg== X-Received: by 2002:a17:90b:360c:: with SMTP id ml12mr12269609pjb.40.1617953362862; Fri, 09 Apr 2021 00:29:22 -0700 (PDT) Received: from fmin-OptiPlex-7060.nreal.work ([137.59.103.165]) by smtp.gmail.com with ESMTPSA id j3sm1344432pfc.49.2021.04.09.00.29.18 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Fri, 09 Apr 2021 00:29:22 -0700 (PDT) From: dillon.minfei@gmail.com To: kever.yang@rock-chips.com, andre.przywara@arm.com, priyanka.jain@nxp.com, jagan@amarulasolutions.com, narmstrong@baylibre.com, marex@denx.de, aford173@gmail.com, ioana.ciornei@nxp.com, josip.kelecic@sartura.hr, festevam@gmail.com, hs@denx.de, heiko.stuebner@theobroma-systems.com, u-boot@lists.denx.de, patrice.chotard@foss.st.com, patrick.delaunay@foss.st.com, uboot-stm32@st-md-mailman.stormreply.com, sjg@chromium.org Cc: dillon min Subject: [PATCH v5 7/7] board: Add rt-thread art-pi board support Date: Fri, 9 Apr 2021 15:28:46 +0800 Message-Id: <1617953326-3110-8-git-send-email-dillon.minfei@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1617953326-3110-1-git-send-email-dillon.minfei@gmail.com> References: <1617953326-3110-1-git-send-email-dillon.minfei@gmail.com> X-Mailman-Approved-At: Fri, 09 Apr 2021 13:44:19 +0200 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.4 at phobos.denx.de X-Virus-Status: Clean From: dillon min All these files are add for support rt-thread art-pi board - add board/st/stm32h750-art-pi, defconfig, header support for u-boot for more information about art-pi, please goto: https://art-pi.gitee.io/website/ Signed-off-by: dillon min Reviewed-by: Patrice Chotard --- v5: remove "for STMicroelectronics." from Author(s) description arch/arm/mach-stm32/stm32h7/Kconfig | 4 ++ board/st/stm32h750-art-pi/Kconfig | 19 +++++++++ board/st/stm32h750-art-pi/MAINTAINERS | 7 ++++ board/st/stm32h750-art-pi/Makefile | 6 +++ board/st/stm32h750-art-pi/stm32h750-art-pi.c | 58 ++++++++++++++++++++++++++++ configs/stm32h750-art-pi_defconfig | 51 ++++++++++++++++++++++++ include/configs/stm32h750-art-pi.h | 48 +++++++++++++++++++++++ 7 files changed, 193 insertions(+) create mode 100644 board/st/stm32h750-art-pi/Kconfig create mode 100644 board/st/stm32h750-art-pi/MAINTAINERS create mode 100644 board/st/stm32h750-art-pi/Makefile create mode 100644 board/st/stm32h750-art-pi/stm32h750-art-pi.c create mode 100644 configs/stm32h750-art-pi_defconfig create mode 100644 include/configs/stm32h750-art-pi.h diff --git a/arch/arm/mach-stm32/stm32h7/Kconfig b/arch/arm/mach-stm32/stm32h7/Kconfig index 55e6217..70233a4 100644 --- a/arch/arm/mach-stm32/stm32h7/Kconfig +++ b/arch/arm/mach-stm32/stm32h7/Kconfig @@ -6,7 +6,11 @@ config TARGET_STM32H743_DISCO config TARGET_STM32H743_EVAL bool "STM32H743 Evaluation board" +config TARGET_STM32H750_ART_PI + bool "STM32H750 ART Pi board" + source "board/st/stm32h743-eval/Kconfig" source "board/st/stm32h743-disco/Kconfig" +source "board/st/stm32h750-art-pi/Kconfig" endif diff --git a/board/st/stm32h750-art-pi/Kconfig b/board/st/stm32h750-art-pi/Kconfig new file mode 100644 index 0000000..c31b984 --- /dev/null +++ b/board/st/stm32h750-art-pi/Kconfig @@ -0,0 +1,19 @@ +if TARGET_STM32H750_ART_PI + +config SYS_BOARD + string + default "stm32h750-art-pi" + +config SYS_VENDOR + string + default "st" + +config SYS_SOC + string + default "stm32h7" + +config SYS_CONFIG_NAME + string + default "stm32h750-art-pi" + +endif diff --git a/board/st/stm32h750-art-pi/MAINTAINERS b/board/st/stm32h750-art-pi/MAINTAINERS new file mode 100644 index 0000000..9578833 --- /dev/null +++ b/board/st/stm32h750-art-pi/MAINTAINERS @@ -0,0 +1,7 @@ +STM32H750 ART PI BOARD +M: Dillon Min +S: Maintained +F: board/st/stm32h750-art-pi +F: include/configs/stm32h750-art-pi.h +F: configs/stm32h750-art-pi_defconfig +F: arch/arm/dts/stm32h7* diff --git a/board/st/stm32h750-art-pi/Makefile b/board/st/stm32h750-art-pi/Makefile new file mode 100644 index 0000000..a06de87 --- /dev/null +++ b/board/st/stm32h750-art-pi/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2021, RT-Thread - All Rights Reserved +# Author(s): Dillon Min, for RT-Thread. + +obj-y := stm32h750-art-pi.o diff --git a/board/st/stm32h750-art-pi/stm32h750-art-pi.c b/board/st/stm32h750-art-pi/stm32h750-art-pi.c new file mode 100644 index 0000000..5785b2e --- /dev/null +++ b/board/st/stm32h750-art-pi/stm32h750-art-pi.c @@ -0,0 +1,58 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2021, STMicroelectronics - All Rights Reserved + * Author(s): Dillon Min + */ + +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +int dram_init(void) +{ + struct udevice *dev; + int ret; + + ret = uclass_get_device(UCLASS_RAM, 0, &dev); + if (ret) { + debug("DRAM init failed: %d\n", ret); + return ret; + } + + if (fdtdec_setup_mem_size_base() != 0) + ret = -EINVAL; + + return ret; +} + +int dram_init_banksize(void) +{ + fdtdec_setup_memory_banksize(); + + return 0; +} + +int board_early_init_f(void) +{ + return 0; +} + +u32 get_board_rev(void) +{ + return 0; +} + +int board_late_init(void) +{ + return 0; +} + +int board_init(void) +{ + gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100; + return 0; +} diff --git a/configs/stm32h750-art-pi_defconfig b/configs/stm32h750-art-pi_defconfig new file mode 100644 index 0000000..447af5b --- /dev/null +++ b/configs/stm32h750-art-pi_defconfig @@ -0,0 +1,51 @@ +CONFIG_ARM=y +CONFIG_ARCH_STM32=y +CONFIG_SYS_TEXT_BASE=0x90000000 +CONFIG_SYS_MALLOC_F_LEN=0xF00 +CONFIG_NR_DRAM_BANKS=1 +CONFIG_ENV_SIZE=0x2000 +CONFIG_STM32H7=y +CONFIG_TARGET_STM32H750_ART_PI=y +CONFIG_DEFAULT_DEVICE_TREE="stm32h750i-art-pi" +CONFIG_DISTRO_DEFAULTS=y +CONFIG_BOOTDELAY=3 +CONFIG_AUTOBOOT_KEYED=y +CONFIG_AUTOBOOT_PROMPT="Hit SPACE in %d seconds to stop autoboot.\n" +CONFIG_AUTOBOOT_STOP_STR=" " +# CONFIG_USE_BOOTCOMMAND is not set +CONFIG_DEFAULT_FDT_FILE="stm32h750i-art-pi" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_BOARD_LATE_INIT=y +CONFIG_SYS_PROMPT="U-Boot > " +CONFIG_CMD_GPT=y +CONFIG_CMD_MMC=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIMER=y +CONFIG_CMD_EXT4_WRITE=y +# CONFIG_ISO_PARTITION is not set +CONFIG_OF_CONTROL=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +# CONFIG_NET is not set +CONFIG_DM_MMC=y +CONFIG_STM32_SDMMC2=y +# CONFIG_PINCTRL_FULL is not set +CONFIG_OF_LIBFDT_OVERLAY=y +CONFIG_BAUDRATE=2000000 +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="console=ttySTM0,2000000 root=/dev/ram loglevel=8" +CONFIG_BOOTCOMMAND="bootm 90080000" +CONFIG_REQUIRE_SERIAL_CONSOLE=y +CONFIG_SERIAL_PRESENT=y +CONFIG_DM_SERIAL=y +CONFIG_STM32_SERIAL=y +CONFIG_FIT=y +CONFIG_FIT_EXTERNAL_OFFSET=0x0 +CONFIG_FIT_ENABLE_SHA256_SUPPORT=y +CONFIG_FIT_FULL_CHECK=y +CONFIG_FIT_PRINT=y +CONFIG_LEGACY_IMAGE_FORMAT=y +CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_USE_BOOTCOMMAND=y +CONFIG_DM_DMA=y diff --git a/include/configs/stm32h750-art-pi.h b/include/configs/stm32h750-art-pi.h new file mode 100644 index 0000000..3fd5461 --- /dev/null +++ b/include/configs/stm32h750-art-pi.h @@ -0,0 +1,48 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2021, STMicroelectronics - All Rights Reserved + * Author(s): Dillon Min + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include +#include + +/* For booting Linux, use the first 16MB of memory */ +#define CONFIG_SYS_BOOTMAPSZ (SZ_16M + SZ_8M) + +#define CONFIG_SYS_FLASH_BASE 0x90000000 +#define CONFIG_SYS_INIT_SP_ADDR 0x24040000 + +/* + * Configuration of the external SDRAM memory + */ +#define CONFIG_SYS_LOAD_ADDR 0xC1800000 +#define CONFIG_LOADADDR 0xC1800000 + +#define CONFIG_SYS_HZ_CLOCK 1000000 + +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG +#define CONFIG_REVISION_TAG + +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024) + +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 0) + +#include +#define CONFIG_EXTRA_ENV_SETTINGS \ + "kernel_addr_r=0xC0008000\0" \ + "fdtfile=stm32h750i-art-pi.dtb\0" \ + "fdt_addr_r=0xC0408000\0" \ + "scriptaddr=0xC0418000\0" \ + "pxefile_addr_r=0xC0428000\0" \ + "ramdisk_addr_r=0xC0438000\0" \ + BOOTENV + +#endif /* __CONFIG_H */