From patchwork Fri Mar 26 14:51:30 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 1458837 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=cYq7anr9; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4F6Q1139Xcz9sVm for ; Sat, 27 Mar 2021 01:52:05 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230159AbhCZOvc (ORCPT ); Fri, 26 Mar 2021 10:51:32 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56252 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230051AbhCZOv0 (ORCPT ); Fri, 26 Mar 2021 10:51:26 -0400 Received: from mail-wm1-x32b.google.com (mail-wm1-x32b.google.com [IPv6:2a00:1450:4864:20::32b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 31120C0613AA for ; Fri, 26 Mar 2021 07:51:26 -0700 (PDT) Received: by mail-wm1-x32b.google.com with SMTP id 12so3122569wmf.5 for ; Fri, 26 Mar 2021 07:51:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=1jY8mwnQnAeWLndXGjoVPFOh3LwZ9LMn1afxTK8ioYU=; b=cYq7anr9I5TabG+pA/dIDgs1ukMI/RJ5lyFqfgAVps2FCdtEjfXm1GStbQpi2qXjZS ySsNNfwQApaE20yjFGrODOhPG5agByHc+eadWqk55iEZNZ5wh6XJ7JXXLuI6xEMzortj pcL/O+JETN9SYJgQEbFVXB4K/C2RD0THr8R6PrhRdvLC8X9nZochrfTc3mCZxoXbc4hh mr9ABiBh66SO58+xocwUbq00OB1hPqf5fS6FOYwRjFWdC+TkZRNIDdb5sC9+Buv7byF7 al3ZanAVPb/V6B6jdB+U7FyyNrQqFuJwnc2xTQSwtoIJviE8Y1JeB2u7wIqVunNRVfzk QyqQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=1jY8mwnQnAeWLndXGjoVPFOh3LwZ9LMn1afxTK8ioYU=; b=i4h7usGy7Dedg0eexDh8LTR+zcC4kl/uj5/HcYfZn06Ga5E4i7E8MMJoH/kNlkTa7A NZGd1IuTIwKJtsOKBZq1uI6Vw5BdcY2u3xLSCMb8TEdJd77sqAy0Ye037dHp5uS2zmGP TpmTLVMc8pFYXLDbxwiCdpHIpcrhe9dRG4YqwkXH0hQPh4ZIODV0yHJqK5h4xRHJNBXr 8iipYUdTimna1tUM3w2Ur8Ez8t2kOEOuHMORf/D6IBd1qQEXKTIynB9w25Ct60fyUcaF 0RlgHe0sS8QFbClTBGXeAvxgG8Mk7S0oMGhBUqQ++WRYMK8gXnlMI1C3+Qt4h6r31UJX j0IQ== X-Gm-Message-State: AOAM5333c/00E5Q5erof9Wn8RUfC9en5P4RU2S58MKg5jfRWY1fJr76z 3xMBAXNDACoXjdT4ZMKlHiU= X-Google-Smtp-Source: ABdhPJwLGnx999mXR/dfcnAYVGLYaE5B2HwvvEGVFtaZgHK51cReNLWGwGqZh/E9awvbrmVp/RyPdQ== X-Received: by 2002:a05:600c:290b:: with SMTP id i11mr13888176wmd.129.1616770284982; Fri, 26 Mar 2021 07:51:24 -0700 (PDT) Received: from localhost ([62.96.65.119]) by smtp.gmail.com with ESMTPSA id m11sm13001228wrz.40.2021.03.26.07.51.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Mar 2021 07:51:24 -0700 (PDT) From: Thierry Reding To: Thierry Reding Cc: David Airlie , Daniel Vetter , Maarten Lankhorst , Thomas Zimmermann , Maxime Ripard , James Jones , Dmitry Osipenko , Simon Ser , dri-devel@lists.freedesktop.org, linux-tegra@vger.kernel.org Subject: [PATCH v2 01/10] drm/fourcc: Add macros to determine the modifier vendor Date: Fri, 26 Mar 2021 15:51:30 +0100 Message-Id: <20210326145139.467072-2-thierry.reding@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210326145139.467072-1-thierry.reding@gmail.com> References: <20210326145139.467072-1-thierry.reding@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Thierry Reding When working with framebuffer modifiers, it can be useful to extract the vendor identifier or check a modifier against a given vendor identifier. Add one macro that extracts the vendor identifier and a helper to check a modifier against a given vendor identifier. v2: add macro to extract vendor ID from modifier (Simon) Signed-off-by: Thierry Reding Reviewed-by: Simon Ser --- include/uapi/drm/drm_fourcc.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h index f76de49c768f..64f01bc2624c 100644 --- a/include/uapi/drm/drm_fourcc.h +++ b/include/uapi/drm/drm_fourcc.h @@ -366,6 +366,12 @@ extern "C" { #define DRM_FORMAT_RESERVED ((1ULL << 56) - 1) +#define fourcc_mod_get_vendor(modifier) \ + (((modifier) >> 56) & 0xff) + +#define fourcc_mod_is_vendor(modifier, vendor) \ + (fourcc_mod_get_vendor(modifier) == DRM_FORMAT_MOD_VENDOR_## vendor) + #define fourcc_mod_code(vendor, val) \ ((((__u64)DRM_FORMAT_MOD_VENDOR_## vendor) << 56) | ((val) & 0x00ffffffffffffffULL)) From patchwork Fri Mar 26 14:51:31 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 1458840 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=sy0LpR6C; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4F6Q1b4bLjz9sRR for ; Sat, 27 Mar 2021 01:52:35 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230188AbhCZOwF (ORCPT ); Fri, 26 Mar 2021 10:52:05 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56264 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230170AbhCZOv3 (ORCPT ); Fri, 26 Mar 2021 10:51:29 -0400 Received: from mail-wm1-x32d.google.com (mail-wm1-x32d.google.com [IPv6:2a00:1450:4864:20::32d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 537C4C0613AA for ; Fri, 26 Mar 2021 07:51:28 -0700 (PDT) Received: by mail-wm1-x32d.google.com with SMTP id m20-20020a7bcb940000b029010cab7e5a9fso5059769wmi.3 for ; Fri, 26 Mar 2021 07:51:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=dexBEjYiMkS4XXfyY7Y63BCfCtQuPvt6wAmmNMM9uiU=; b=sy0LpR6CO/+hGOGtblTJwkDRNfJ0OIYrkXpVb7gzm3NNWD+WbbNHcwjYquArjfkiLp 3pqD/CIluuv2EH803a7w+8Zpruec3tTOpAo2v9DrUADG0Q1vvvb6t5KkdWBVl4aszjOs 8WuiMFf8IJtBqfs2rjLhZBYeUQfTVeyUxvSLw2XQ/Q8x3QoT1c5Zb0O/zTD2e59YE3b8 vRYwATWOzwE/06IhBA/Zbcvh1dmygCiWgw5r3tqYHhKd2DJ2O1zNkA77pygVOqb6CQMf Bbhaw4FCKRLPrklpt3UaeOBU5OtLlHNLwHuUVla0NBptfyCpPdwIetjAufT1nb2/0A4/ wBHA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=dexBEjYiMkS4XXfyY7Y63BCfCtQuPvt6wAmmNMM9uiU=; b=OYmExo6A2oF5rVGmXx422tSX/UBUnl/cJ2UYxjIrKvLXJRkZyZClMa5Cu5vJb+xQBq ypgTl4iFRFg55th3wGbntxM6frWUXSHXQ08ftMjTv2nzkeCj8rCvvfcZib32iSGtuha7 OJ5bsd2DqnIgb6n7t4VDYIoB3ezg9UtmTQD8aHasNUrnfEajpTdTvDbxFj7J+jVI7ALb kWM/Z2sTWH0lY9EPQTxE+FTop8ACBR2y1Iss++Cpr9ygEhQRIekpQwJqOn8BpBYKJMkz DKEPwug+ZqGBqoV6K4LBmZgzwZHa3ModtDft+2lK9ow6QcaKF5qHE5mrMxxmzZmpPfHn 22BQ== X-Gm-Message-State: AOAM530saaQdtL/K2DodHteH7rAzeLTeyjLu17IVSu0LKQTVTpoToHL1 CH5d4SSKNR+EDbKGOvaDr5U= X-Google-Smtp-Source: ABdhPJyAMzgOJyXp6zRFVElVkH/XLVwQcbL0T9qq9DXloPusNrJUNrrxtee7Loh7WIWQCUuT5ehcaQ== X-Received: by 2002:a7b:c083:: with SMTP id r3mr13414453wmh.177.1616770287127; Fri, 26 Mar 2021 07:51:27 -0700 (PDT) Received: from localhost ([62.96.65.119]) by smtp.gmail.com with ESMTPSA id r16sm8022566wrx.75.2021.03.26.07.51.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Mar 2021 07:51:26 -0700 (PDT) From: Thierry Reding To: Thierry Reding Cc: David Airlie , Daniel Vetter , Maarten Lankhorst , Thomas Zimmermann , Maxime Ripard , James Jones , Dmitry Osipenko , Simon Ser , dri-devel@lists.freedesktop.org, linux-tegra@vger.kernel.org Subject: [PATCH v2 02/10] drm/arm: malidp: Use fourcc_mod_is_vendor() helper Date: Fri, 26 Mar 2021 15:51:31 +0100 Message-Id: <20210326145139.467072-3-thierry.reding@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210326145139.467072-1-thierry.reding@gmail.com> References: <20210326145139.467072-1-thierry.reding@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Thierry Reding Rather than open-coding the vendor extraction operation, use the newly introduced helper macro. Signed-off-by: Thierry Reding Reviewed-by: Daniel Vetter --- drivers/gpu/drm/arm/malidp_planes.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/arm/malidp_planes.c b/drivers/gpu/drm/arm/malidp_planes.c index ddbba67f0283..cd218883cff8 100644 --- a/drivers/gpu/drm/arm/malidp_planes.c +++ b/drivers/gpu/drm/arm/malidp_planes.c @@ -165,7 +165,7 @@ bool malidp_format_mod_supported(struct drm_device *drm, return !malidp_hw_format_is_afbc_only(format); } - if ((modifier >> 56) != DRM_FORMAT_MOD_VENDOR_ARM) { + if (!fourcc_mod_is_vendor(modifier, ARM)) { DRM_ERROR("Unknown modifier (not Arm)\n"); return false; } From patchwork Fri Mar 26 14:51:32 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 1458838 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=eyC59KwU; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4F6Q1Z4dRXz9sRR for ; Sat, 27 Mar 2021 01:52:34 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230223AbhCZOwD (ORCPT ); Fri, 26 Mar 2021 10:52:03 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56272 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230076AbhCZOvb (ORCPT ); Fri, 26 Mar 2021 10:51:31 -0400 Received: from mail-wm1-x32d.google.com (mail-wm1-x32d.google.com [IPv6:2a00:1450:4864:20::32d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 405C7C0613B1 for ; Fri, 26 Mar 2021 07:51:31 -0700 (PDT) Received: by mail-wm1-x32d.google.com with SMTP id g20so3124792wmk.3 for ; Fri, 26 Mar 2021 07:51:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=mYZHwCwRW4nMunvHncCTe6a/rr8wamJxRARNjK2ntJo=; b=eyC59KwUVdj4wh2qXTUJoBU3hvwj73JNBUYOV5f2GE2l+3SN23gCe08mELuBhiLJE4 GqA9uoVijwFH+qNNoRxiPskJLyzAo1AWVatJSYz3HFw1P1itlX1KqK6Mvr2bLZmmvwLa SfBrKW8/I+yNF5AJWvA+XiMvv99XG6PKOhGcKwCzaFf6nzgMo3/dXPOPCgpo6aKrNxmn 61it3+EqyzN026gBOG1ad5cLyujK120R0ogms9o/4yN4nSwANOffc3vF8207ztuqExD+ LW/iGlNdHdzADGgbDDEzIsAvlEr4X9Owu0z91Q6tRk0I7utQt2aeJEb0MOvAZAnH6l5f A7Qg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=mYZHwCwRW4nMunvHncCTe6a/rr8wamJxRARNjK2ntJo=; b=k6F9D05aLxU0+bO5UzB8ZNOkEYzWgYY4w8zjIk5h5KN3p51LPlR8GqJR+blqb+1c4R MfEPwngboB2sUoUos9hGVkM+CU11XBTGtAFkE8CgP2JSxnwQqnC69prIyNVNvlfC3xE+ gPBg/F6+OjoU8kxYtZ35rcNauTsbqI/l62HQsT5EPsESQ2zAKmyghpLv8L056MGVww6Z u3pRCl0Aig++NpMijJdquO3T0IR3z/1FEWCs3tAJQC8Q4yT8OdgBm7y7RoRSHuZRgveN 0qjhoTiZY6ZV+j5QRrPHYno9OV9WR4e6xlCTxGbyAeYdNcbp+bKpN/aOU/rRUKKc+Jh7 oREQ== X-Gm-Message-State: AOAM532G4+Zwuvmag302HdoafR/ZhiaFO8Wc0RHEv+tkGsYv+BoGXURM DJe3CMH6H01vxVYNPe3fEAo= X-Google-Smtp-Source: ABdhPJylGou6xdZQHDcpDelq2ymSU1tXgTq3g9SINF4tCi4n383YKtC9pWSPljq9f+EY+naLSxSDLg== X-Received: by 2002:a1c:ddc6:: with SMTP id u189mr13752722wmg.171.1616770290034; Fri, 26 Mar 2021 07:51:30 -0700 (PDT) Received: from localhost ([62.96.65.119]) by smtp.gmail.com with ESMTPSA id l8sm13147469wrx.83.2021.03.26.07.51.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Mar 2021 07:51:28 -0700 (PDT) From: Thierry Reding To: Thierry Reding Cc: David Airlie , Daniel Vetter , Maarten Lankhorst , Thomas Zimmermann , Maxime Ripard , James Jones , Dmitry Osipenko , Simon Ser , dri-devel@lists.freedesktop.org, linux-tegra@vger.kernel.org Subject: [PATCH v2 03/10] drm/tegra: dc: Inherit DMA mask Date: Fri, 26 Mar 2021 15:51:32 +0100 Message-Id: <20210326145139.467072-4-thierry.reding@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210326145139.467072-1-thierry.reding@gmail.com> References: <20210326145139.467072-1-thierry.reding@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Thierry Reding Inherit the DMA mask from host1x (on Tegra210 and earlier) or the display hub (on Tegra186 and later). This is necessary in order to properly map buffers without SMMU support and use the maximum IOVA space available with SMMU support. Signed-off-by: Thierry Reding --- drivers/gpu/drm/tegra/dc.c | 7 +++++++ drivers/gpu/drm/tegra/hub.c | 7 +++++++ 2 files changed, 14 insertions(+) diff --git a/drivers/gpu/drm/tegra/dc.c b/drivers/gpu/drm/tegra/dc.c index 40bf8f33a2ae..935717e7410d 100644 --- a/drivers/gpu/drm/tegra/dc.c +++ b/drivers/gpu/drm/tegra/dc.c @@ -2538,9 +2538,16 @@ static int tegra_dc_couple(struct tegra_dc *dc) static int tegra_dc_probe(struct platform_device *pdev) { + u64 dma_mask = dma_get_mask(pdev->dev.parent); struct tegra_dc *dc; int err; + err = dma_coerce_mask_and_coherent(&pdev->dev, dma_mask); + if (err < 0) { + dev_err(&pdev->dev, "failed to set DMA mask: %d\n", err); + return err; + } + dc = devm_kzalloc(&pdev->dev, sizeof(*dc), GFP_KERNEL); if (!dc) return -ENOMEM; diff --git a/drivers/gpu/drm/tegra/hub.c b/drivers/gpu/drm/tegra/hub.c index 8e6d329d062b..617240032c37 100644 --- a/drivers/gpu/drm/tegra/hub.c +++ b/drivers/gpu/drm/tegra/hub.c @@ -848,12 +848,19 @@ static const struct host1x_client_ops tegra_display_hub_ops = { static int tegra_display_hub_probe(struct platform_device *pdev) { + u64 dma_mask = dma_get_mask(pdev->dev.parent); struct device_node *child = NULL; struct tegra_display_hub *hub; struct clk *clk; unsigned int i; int err; + err = dma_coerce_mask_and_coherent(&pdev->dev, dma_mask); + if (err < 0) { + dev_err(&pdev->dev, "failed to set DMA mask: %d\n", err); + return err; + } + hub = devm_kzalloc(&pdev->dev, sizeof(*hub), GFP_KERNEL); if (!hub) return -ENOMEM; From patchwork Fri Mar 26 14:51:33 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 1458839 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=ioyO77vd; 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Fri, 26 Mar 2021 07:51:38 -0700 (PDT) Received: from localhost ([62.96.65.119]) by smtp.gmail.com with ESMTPSA id j136sm12156895wmj.35.2021.03.26.07.51.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Mar 2021 07:51:31 -0700 (PDT) From: Thierry Reding To: Thierry Reding Cc: David Airlie , Daniel Vetter , Maarten Lankhorst , Thomas Zimmermann , Maxime Ripard , James Jones , Dmitry Osipenko , Simon Ser , dri-devel@lists.freedesktop.org, linux-tegra@vger.kernel.org Subject: [PATCH v2 04/10] drm/tegra: dc: Parameterize maximum resolution Date: Fri, 26 Mar 2021 15:51:33 +0100 Message-Id: <20210326145139.467072-5-thierry.reding@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210326145139.467072-1-thierry.reding@gmail.com> References: <20210326145139.467072-1-thierry.reding@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Thierry Reding Tegra186 and later support a higher maximum resolution than earlier chips, so make sure to reflect that in the mode configuration. Signed-off-by: Thierry Reding --- drivers/gpu/drm/tegra/dc.c | 6 ++++++ drivers/gpu/drm/tegra/drm.c | 13 ++++++++++--- drivers/gpu/drm/tegra/drm.h | 1 + 3 files changed, 17 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/tegra/dc.c b/drivers/gpu/drm/tegra/dc.c index 935717e7410d..0541d7b5c841 100644 --- a/drivers/gpu/drm/tegra/dc.c +++ b/drivers/gpu/drm/tegra/dc.c @@ -2117,6 +2117,12 @@ static int tegra_dc_init(struct host1x_client *client) if (dc->soc->pitch_align > tegra->pitch_align) tegra->pitch_align = dc->soc->pitch_align; + /* track maximum resolution */ + if (dc->soc->has_nvdisplay) + drm->mode_config.max_width = drm->mode_config.max_height = 16384; + else + drm->mode_config.max_width = drm->mode_config.max_height = 4096; + err = tegra_dc_rgb_init(drm, dc); if (err < 0 && err != -ENODEV) { dev_err(dc->dev, "failed to initialize RGB output: %d\n", err); diff --git a/drivers/gpu/drm/tegra/drm.c b/drivers/gpu/drm/tegra/drm.c index 6015913fef83..bbc504763bd4 100644 --- a/drivers/gpu/drm/tegra/drm.c +++ b/drivers/gpu/drm/tegra/drm.c @@ -1144,9 +1144,8 @@ static int host1x_drm_probe(struct host1x_device *dev) drm->mode_config.min_width = 0; drm->mode_config.min_height = 0; - - drm->mode_config.max_width = 4096; - drm->mode_config.max_height = 4096; + drm->mode_config.max_width = 0; + drm->mode_config.max_height = 0; drm->mode_config.allow_fb_modifiers = true; @@ -1165,6 +1164,14 @@ static int host1x_drm_probe(struct host1x_device *dev) if (err < 0) goto fbdev; + /* + * Now that all display controller have been initialized, the maximum + * supported resolution is known and the bitmask for horizontal and + * vertical bitfields can be computed. + */ + tegra->hmask = drm->mode_config.max_width - 1; + tegra->vmask = drm->mode_config.max_height - 1; + if (tegra->use_explicit_iommu) { u64 carveout_start, carveout_end, gem_start, gem_end; u64 dma_mask = dma_get_mask(&dev->dev); diff --git a/drivers/gpu/drm/tegra/drm.h b/drivers/gpu/drm/tegra/drm.h index 1af57c2016eb..34fbcd6abf2f 100644 --- a/drivers/gpu/drm/tegra/drm.h +++ b/drivers/gpu/drm/tegra/drm.h @@ -54,6 +54,7 @@ struct tegra_drm { struct tegra_fbdev *fbdev; #endif + unsigned int hmask, vmask; unsigned int pitch_align; struct tegra_display_hub *hub; From patchwork Fri Mar 26 14:51:34 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 1458842 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=OSraSRCg; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4F6Q1c2MsVz9sVm for ; Sat, 27 Mar 2021 01:52:36 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230167AbhCZOwF (ORCPT ); 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Fri, 26 Mar 2021 07:51:39 -0700 (PDT) From: Thierry Reding To: Thierry Reding Cc: David Airlie , Daniel Vetter , Maarten Lankhorst , Thomas Zimmermann , Maxime Ripard , James Jones , Dmitry Osipenko , Simon Ser , dri-devel@lists.freedesktop.org, linux-tegra@vger.kernel.org Subject: [PATCH v2 05/10] drm/tegra: dc: Implement hardware cursor on Tegra186 and later Date: Fri, 26 Mar 2021 15:51:34 +0100 Message-Id: <20210326145139.467072-6-thierry.reding@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210326145139.467072-1-thierry.reding@gmail.com> References: <20210326145139.467072-1-thierry.reding@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Thierry Reding The hardware cursor on Tegra186 differs slightly from the implementation on older SoC generations. In particular the new implementation relies on software for clipping the cursor against the screen. Fortunately, atomic KMS already computes clipped coordinates for (cursor) planes, so this is trivial to implement. The format supported by the hardware cursor is also slightly different. v2: use more drm_rect helpers (Dmitry) Signed-off-by: Thierry Reding Reviewed-by: Dmitry Osipenko --- drivers/gpu/drm/tegra/dc.c | 59 ++++++++++++++++++++++++++++++++------ drivers/gpu/drm/tegra/dc.h | 5 ++++ 2 files changed, 56 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/tegra/dc.c b/drivers/gpu/drm/tegra/dc.c index 0541d7b5c841..7758d64822ae 100644 --- a/drivers/gpu/drm/tegra/dc.c +++ b/drivers/gpu/drm/tegra/dc.c @@ -832,10 +832,14 @@ static struct drm_plane *tegra_primary_plane_create(struct drm_device *drm, return &plane->base; } -static const u32 tegra_cursor_plane_formats[] = { +static const u32 tegra_legacy_cursor_plane_formats[] = { DRM_FORMAT_RGBA8888, }; +static const u32 tegra_cursor_plane_formats[] = { + DRM_FORMAT_ARGB8888, +}; + static int tegra_cursor_atomic_check(struct drm_plane *plane, struct drm_atomic_state *state) { @@ -875,12 +879,22 @@ static void tegra_cursor_atomic_update(struct drm_plane *plane, plane); struct tegra_plane_state *tegra_plane_state = to_tegra_plane_state(new_state); struct tegra_dc *dc = to_tegra_dc(new_state->crtc); - u32 value = CURSOR_CLIP_DISPLAY; + struct tegra_drm *tegra = plane->dev->dev_private; + u64 dma_mask = *dc->dev->dma_mask; + unsigned int x, y; + u32 value = 0; /* rien ne va plus */ if (!new_state->crtc || !new_state->fb) return; + /* + * Legacy display supports hardware clipping of the cursor, but + * nvdisplay relies on software to clip the cursor to the screen. + */ + if (!dc->soc->has_nvdisplay) + value |= CURSOR_CLIP_DISPLAY; + switch (new_state->crtc_w) { case 32: value |= CURSOR_SIZE_32x32; @@ -908,7 +922,7 @@ static void tegra_cursor_atomic_update(struct drm_plane *plane, tegra_dc_writel(dc, value, DC_DISP_CURSOR_START_ADDR); #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT - value = (tegra_plane_state->iova[0] >> 32) & 0x3; + value = (tegra_plane_state->iova[0] >> 32) & (dma_mask >> 32); tegra_dc_writel(dc, value, DC_DISP_CURSOR_START_ADDR_HI); #endif @@ -920,15 +934,39 @@ static void tegra_cursor_atomic_update(struct drm_plane *plane, value = tegra_dc_readl(dc, DC_DISP_BLEND_CURSOR_CONTROL); value &= ~CURSOR_DST_BLEND_MASK; value &= ~CURSOR_SRC_BLEND_MASK; - value |= CURSOR_MODE_NORMAL; + + if (dc->soc->has_nvdisplay) + value &= ~CURSOR_COMPOSITION_MODE_XOR; + else + value |= CURSOR_MODE_NORMAL; + value |= CURSOR_DST_BLEND_NEG_K1_TIMES_SRC; value |= CURSOR_SRC_BLEND_K1_TIMES_SRC; value |= CURSOR_ALPHA; tegra_dc_writel(dc, value, DC_DISP_BLEND_CURSOR_CONTROL); + /* nvdisplay relies on software for clipping */ + if (dc->soc->has_nvdisplay) { + struct drm_rect src; + + x = new_state->dst.x1; + y = new_state->dst.y1; + + drm_rect_fp_to_int(&src, &new_state->src); + + value = (src.y1 & tegra->vmask) << 16 | (src.x1 & tegra->hmask); + tegra_dc_writel(dc, value, DC_DISP_PCALC_HEAD_SET_CROPPED_POINT_IN_CURSOR); + + value = (drm_rect_height(&src) & tegra->vmask) << 16 | + (drm_rect_width(&src) & tegra->hmask); + tegra_dc_writel(dc, value, DC_DISP_PCALC_HEAD_SET_CROPPED_SIZE_IN_CURSOR); + } else { + x = new_state->crtc_x; + y = new_state->crtc_y; + } + /* position the cursor */ - value = (new_state->crtc_y & 0x3fff) << 16 | - (new_state->crtc_x & 0x3fff); + value = ((y & tegra->vmask) << 16) | (x & tegra->hmask); tegra_dc_writel(dc, value, DC_DISP_CURSOR_POSITION); } @@ -982,8 +1020,13 @@ static struct drm_plane *tegra_dc_cursor_plane_create(struct drm_device *drm, plane->index = 6; plane->dc = dc; - num_formats = ARRAY_SIZE(tegra_cursor_plane_formats); - formats = tegra_cursor_plane_formats; + if (!dc->soc->has_nvdisplay) { + num_formats = ARRAY_SIZE(tegra_legacy_cursor_plane_formats); + formats = tegra_legacy_cursor_plane_formats; + } else { + num_formats = ARRAY_SIZE(tegra_cursor_plane_formats); + formats = tegra_cursor_plane_formats; + } err = drm_universal_plane_init(drm, &plane->base, possible_crtcs, &tegra_plane_funcs, formats, diff --git a/drivers/gpu/drm/tegra/dc.h b/drivers/gpu/drm/tegra/dc.h index 051d03dcb9b0..21074cd2ce5e 100644 --- a/drivers/gpu/drm/tegra/dc.h +++ b/drivers/gpu/drm/tegra/dc.h @@ -511,6 +511,8 @@ int tegra_dc_rgb_exit(struct tegra_dc *dc); #define DC_DISP_CURSOR_START_ADDR_HI 0x4ec #define DC_DISP_BLEND_CURSOR_CONTROL 0x4f1 +#define CURSOR_COMPOSITION_MODE_BLEND (0 << 25) +#define CURSOR_COMPOSITION_MODE_XOR (1 << 25) #define CURSOR_MODE_LEGACY (0 << 24) #define CURSOR_MODE_NORMAL (1 << 24) #define CURSOR_DST_BLEND_ZERO (0 << 16) @@ -705,6 +707,9 @@ int tegra_dc_rgb_exit(struct tegra_dc *dc); #define PROTOCOL_MASK (0xf << 8) #define PROTOCOL_SINGLE_TMDS_A (0x1 << 8) +#define DC_DISP_PCALC_HEAD_SET_CROPPED_POINT_IN_CURSOR 0x442 +#define DC_DISP_PCALC_HEAD_SET_CROPPED_SIZE_IN_CURSOR 0x446 + #define DC_WIN_CORE_WINDOWGROUP_SET_CONTROL 0x702 #define OWNER_MASK (0xf << 0) #define OWNER(x) (((x) & 0xf) << 0) From patchwork Fri Mar 26 14:51:35 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 1458841 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=enao8mgc; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4F6Q1b6tccz9sVw for ; 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Fri, 26 Mar 2021 07:51:42 -0700 (PDT) From: Thierry Reding To: Thierry Reding Cc: David Airlie , Daniel Vetter , Maarten Lankhorst , Thomas Zimmermann , Maxime Ripard , James Jones , Dmitry Osipenko , Simon Ser , dri-devel@lists.freedesktop.org, linux-tegra@vger.kernel.org Subject: [PATCH v2 06/10] drm/tegra: fb: Add diagnostics for framebuffer modifiers Date: Fri, 26 Mar 2021 15:51:35 +0100 Message-Id: <20210326145139.467072-7-thierry.reding@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210326145139.467072-1-thierry.reding@gmail.com> References: <20210326145139.467072-1-thierry.reding@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Thierry Reding Add a debug message to let the user know when a framebuffer modifier is not supported. Signed-off-by: Thierry Reding --- drivers/gpu/drm/tegra/fb.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/tegra/fb.c b/drivers/gpu/drm/tegra/fb.c index 01939c57fc74..350f33206076 100644 --- a/drivers/gpu/drm/tegra/fb.c +++ b/drivers/gpu/drm/tegra/fb.c @@ -86,6 +86,7 @@ int tegra_fb_get_tiling(struct drm_framebuffer *framebuffer, break; default: + DRM_DEBUG_KMS("unknown format modifier: %llx\n", modifier); return -EINVAL; } From patchwork Fri Mar 26 14:51:36 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 1458845 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=iEK6+aZl; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4F6Q1d375Yz9sVm for ; Sat, 27 Mar 2021 01:52:37 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230264AbhCZOwH (ORCPT ); Fri, 26 Mar 2021 10:52:07 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56344 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230100AbhCZOvs (ORCPT ); Fri, 26 Mar 2021 10:51:48 -0400 Received: from mail-wr1-x42d.google.com (mail-wr1-x42d.google.com [IPv6:2a00:1450:4864:20::42d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 39DC3C0613AA for ; Fri, 26 Mar 2021 07:51:48 -0700 (PDT) Received: by mail-wr1-x42d.google.com with SMTP id e18so5921935wrt.6 for ; Fri, 26 Mar 2021 07:51:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ReoCKHRk0Yzv54SDAezUoYwx+obEQfebobD2IUY1RHo=; b=iEK6+aZlJrXx8XjCJnAXlLR4InbGYUVx2dt2D4tb6J2ipv7Uq6hWX4QXYtZ/qXIdHT kIYC3R9TlP7L7v4kPpu/1xGzTac4zByImZwVADMw/eHuCr7PIHlWwZ5+Ho5sEM+nuzSI l80ke7Vy7X508jjRY1XAJc0SD6123/gqEo8RgzMsQHAY6akz+z7GH6FHkJ/s0J6RHUEe cMfQLWCpRB1NDb9OmS+wO/vZOGxIcjq1ipUrh6e1tvLO4aklf0uDWcr2dvi//XBkXHNi cWMDvkNT0wZCtHWTNApmN/g0za0pqaAkQFc+GhSziGhj1MhbYSMuMWefrOEsr5f6afLa OsWA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ReoCKHRk0Yzv54SDAezUoYwx+obEQfebobD2IUY1RHo=; b=gHrDmTyRL56uIxFMVNSBVWNevk7Rr325pOAOSn5hHk6aTSDdBTVrRARm6KOCpLefYC iGeNgVlK6lFVYHydCtzvJRXoaP2VtPzMOC5WHQ+QN3bP7rhtNKAQvUSclamT3xEgYk9A Ke7jesnn0F8dvKdwRdYwWgfMhTzn2VJq2d+efnvFkPObzd3Y7V3pSA5CZj+6XCQ5GJt7 ova4SRGD6Hy1L2gXhYAW7YkA5XEcqLSu7X0H7zCsEDA0Apgf87doyxH8tX5JL/ycptw+ RPyInln4skcpvnympmzIDfLp/o1eiHSg5riSleeUKUk/q/oxljddUT7AaBNM913z0ab3 7Gow== X-Gm-Message-State: AOAM531/O3Eh8LAsF3A/9UBMK2Ryqa/uGDdzZEMfOhQj+9Hdaz7QtHAU kr7O6d4waxtpQmVIgjO6hfU= X-Google-Smtp-Source: ABdhPJwlfUjZQv3XsgfKDmclqEDIXzXXcqW+GBTKFrjaojuEtGrfrq6RFk8w1RFXCoMn9hgvOf9zlg== X-Received: by 2002:adf:a59a:: with SMTP id g26mr14938857wrc.271.1616770307017; Fri, 26 Mar 2021 07:51:47 -0700 (PDT) Received: from localhost ([62.96.65.119]) by smtp.gmail.com with ESMTPSA id j123sm10902561wmb.1.2021.03.26.07.51.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Mar 2021 07:51:45 -0700 (PDT) From: Thierry Reding To: Thierry Reding Cc: David Airlie , Daniel Vetter , Maarten Lankhorst , Thomas Zimmermann , Maxime Ripard , James Jones , Dmitry Osipenko , Simon Ser , dri-devel@lists.freedesktop.org, linux-tegra@vger.kernel.org Subject: [PATCH v2 07/10] drm/tegra: gem: Add a clarifying comment Date: Fri, 26 Mar 2021 15:51:36 +0100 Message-Id: <20210326145139.467072-8-thierry.reding@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210326145139.467072-1-thierry.reding@gmail.com> References: <20210326145139.467072-1-thierry.reding@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Thierry Reding Clarify when a fixed IOV address can be used and when a buffer has to be mapped before the IOVA can be used. Signed-off-by: Thierry Reding --- drivers/gpu/drm/tegra/plane.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/gpu/drm/tegra/plane.c b/drivers/gpu/drm/tegra/plane.c index 19e8847a164b..793da5d675d2 100644 --- a/drivers/gpu/drm/tegra/plane.c +++ b/drivers/gpu/drm/tegra/plane.c @@ -119,6 +119,14 @@ static int tegra_dc_pin(struct tegra_dc *dc, struct tegra_plane_state *state) dma_addr_t phys_addr, *phys; struct sg_table *sgt; + /* + * If we're not attached to a domain, we already stored the + * physical address when the buffer was allocated. If we're + * part of a group that's shared between all display + * controllers, we've also already mapped the framebuffer + * through the SMMU. In both cases we can short-circuit the + * code below and retrieve the stored IOV address. + */ if (!domain || dc->client.group) phys = &phys_addr; else From patchwork Fri Mar 26 14:51:37 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 1458844 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=AaLyS3Qe; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4F6Q1d0PTBz9sVw for ; Sat, 27 Mar 2021 01:52:37 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230272AbhCZOwI (ORCPT ); Fri, 26 Mar 2021 10:52:08 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56352 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230046AbhCZOvu (ORCPT ); Fri, 26 Mar 2021 10:51:50 -0400 Received: from mail-wr1-x433.google.com (mail-wr1-x433.google.com [IPv6:2a00:1450:4864:20::433]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 675A7C0613AA for ; Fri, 26 Mar 2021 07:51:50 -0700 (PDT) Received: by mail-wr1-x433.google.com with SMTP id k8so5934513wrc.3 for ; Fri, 26 Mar 2021 07:51:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=3U/NAbihKjPec78yWr69VR7pI5Ujcbfohjar0SwT5eo=; b=AaLyS3Qergrq9129uVi7KloKnhBed8aEvtOSdu1Uwcx6cGMumwd1dkZqNRXHBVlZUe VMzUFkNborSwg7jJFBFwxlQj7cK60QVHVTXdvWJPaol29w/e/x0SuEhkCvcwSkU+M6OP Qa/p/iG3A1Itl+nJkFmVN+i52C3BMpcrE6MzPrjGWvnTYbdP+Db0aA99zbOr1ZwwVI5D hBWlwd93u1hldS2DuQ/Ad8gNf/GBPh0RpwxnVvbQnX7Qg/S7WUx97sYApn+xraGDW/Af a8SxC8s6k38SDRzPqdoEI0cqKcJMLxps2692fgCk1xOHzDNLWJI/19zHIfLLAI+AuyBY PWoA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=3U/NAbihKjPec78yWr69VR7pI5Ujcbfohjar0SwT5eo=; b=YkF/zSyQO5urWTF7t/xeUHQ142lzIq50yhnUeb6Ggtp3pKGHTtagOINzZW5iOh4xDl f+M6PpGnV5UwKEbwcRV1m8cFeyEy6Z621xe2NAMamzasCZxiyzEj+Ah+Tr0RvVmbWdft d8WH8QKZ27SRyZhectv8RcizP1CBNSKCIhmHszcmm9zgHGeYltKaZ9Hg4GbC5gfOr7Ko CjRWG6uSEI4f54fecA+TyizA5rFejMfuV6hRRe92WU9Sw9nAK1RfP1y5W8kCxYdeWHnq egqv1Dydbs59OT64Hg7e0DcOauQzK42+DfUWPof318ftunBiAMj1R7pxaeIrkGUTkbL/ 7tXA== X-Gm-Message-State: AOAM532+4jxYIPlEuOxiSkxrWyB3w934EdT2EAh0mYxQQNCT9EZAzH81 /rqcGlHMu6rASg5bPoOZ+Og= X-Google-Smtp-Source: ABdhPJyNOUsrKleJ3gngSpSoJQRwShk1gTga+j6VbqpxGeASJGdgTyuCBEMJgqLpqvGYd3jBCmSZNA== X-Received: by 2002:adf:8562:: with SMTP id 89mr15015871wrh.101.1616770309209; Fri, 26 Mar 2021 07:51:49 -0700 (PDT) Received: from localhost ([62.96.65.119]) by smtp.gmail.com with ESMTPSA id g5sm13622621wrq.30.2021.03.26.07.51.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Mar 2021 07:51:48 -0700 (PDT) From: Thierry Reding To: Thierry Reding Cc: David Airlie , Daniel Vetter , Maarten Lankhorst , Thomas Zimmermann , Maxime Ripard , James Jones , Dmitry Osipenko , Simon Ser , dri-devel@lists.freedesktop.org, linux-tegra@vger.kernel.org Subject: [PATCH v2 08/10] gpu: host1x: Add early init and late exit callbacks Date: Fri, 26 Mar 2021 15:51:37 +0100 Message-Id: <20210326145139.467072-9-thierry.reding@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210326145139.467072-1-thierry.reding@gmail.com> References: <20210326145139.467072-1-thierry.reding@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Thierry Reding These callbacks can be used by client drivers to run code during early init and during late exit. Early init callbacks are run prior to the regular init callbacks while late exit callbacks run after the regular exit callbacks. Signed-off-by: Thierry Reding --- drivers/gpu/host1x/bus.c | 31 +++++++++++++++++++++++++++++++ include/linux/host1x.h | 2 ++ 2 files changed, 33 insertions(+) diff --git a/drivers/gpu/host1x/bus.c b/drivers/gpu/host1x/bus.c index 4c18874f7c4a..c9077cfbfef9 100644 --- a/drivers/gpu/host1x/bus.c +++ b/drivers/gpu/host1x/bus.c @@ -196,6 +196,17 @@ int host1x_device_init(struct host1x_device *device) mutex_lock(&device->clients_lock); + list_for_each_entry(client, &device->clients, list) { + if (client->ops && client->ops->early_init) { + err = client->ops->early_init(client); + if (err < 0) { + dev_err(&device->dev, "failed to early initialize %s: %d\n", + dev_name(client->dev), err); + goto teardown_late; + } + } + } + list_for_each_entry(client, &device->clients, list) { if (client->ops && client->ops->init) { err = client->ops->init(client); @@ -217,6 +228,14 @@ int host1x_device_init(struct host1x_device *device) if (client->ops->exit) client->ops->exit(client); + /* reset client to end of list for late teardown */ + client = list_entry(&device->clients, struct host1x_client, list); + +teardown_late: + list_for_each_entry_continue_reverse(client, &device->clients, list) + if (client->ops->late_exit) + client->ops->late_exit(client); + mutex_unlock(&device->clients_lock); return err; } @@ -251,6 +270,18 @@ int host1x_device_exit(struct host1x_device *device) } } + list_for_each_entry_reverse(client, &device->clients, list) { + if (client->ops && client->ops->late_exit) { + err = client->ops->late_exit(client); + if (err < 0) { + dev_err(&device->dev, "failed to late cleanup %s: %d\n", + dev_name(client->dev), err); + mutex_unlock(&device->clients_lock); + return err; + } + } + } + mutex_unlock(&device->clients_lock); return 0; diff --git a/include/linux/host1x.h b/include/linux/host1x.h index 5890f91dd286..74970681ecdb 100644 --- a/include/linux/host1x.h +++ b/include/linux/host1x.h @@ -31,8 +31,10 @@ u64 host1x_get_dma_mask(struct host1x *host1x); * @resume: host1x client resume code */ struct host1x_client_ops { + int (*early_init)(struct host1x_client *client); int (*init)(struct host1x_client *client); int (*exit)(struct host1x_client *client); + int (*late_exit)(struct host1x_client *client); int (*suspend)(struct host1x_client *client); int (*resume)(struct host1x_client *client); }; From patchwork Fri Mar 26 14:51:38 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 1458843 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=Eg6shYcr; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4F6Q1c4fxCz9sRR for ; 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Fri, 26 Mar 2021 07:51:50 -0700 (PDT) From: Thierry Reding To: Thierry Reding Cc: David Airlie , Daniel Vetter , Maarten Lankhorst , Thomas Zimmermann , Maxime Ripard , James Jones , Dmitry Osipenko , Simon Ser , dri-devel@lists.freedesktop.org, linux-tegra@vger.kernel.org Subject: [PATCH v2 09/10] drm/tegra: Count number of display controllers at runtime Date: Fri, 26 Mar 2021 15:51:38 +0100 Message-Id: <20210326145139.467072-10-thierry.reding@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210326145139.467072-1-thierry.reding@gmail.com> References: <20210326145139.467072-1-thierry.reding@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Thierry Reding In order to be able to attach planes to all possible display controllers the exact number of CRTCs must be known. Keep track of the number of the display controllers that register during initialization. Signed-off-by: Thierry Reding --- drivers/gpu/drm/tegra/dc.c | 22 ++++++++++++++++++++++ drivers/gpu/drm/tegra/drm.h | 1 + drivers/gpu/drm/tegra/hub.c | 6 ++++-- 3 files changed, 27 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/tegra/dc.c b/drivers/gpu/drm/tegra/dc.c index 7758d64822ae..0c51f0bb17a9 100644 --- a/drivers/gpu/drm/tegra/dc.c +++ b/drivers/gpu/drm/tegra/dc.c @@ -2078,6 +2078,16 @@ static bool tegra_dc_has_window_groups(struct tegra_dc *dc) return false; } +static int tegra_dc_early_init(struct host1x_client *client) +{ + struct drm_device *drm = dev_get_drvdata(client->host); + struct tegra_drm *tegra = drm->dev_private; + + tegra->num_crtcs++; + + return 0; +} + static int tegra_dc_init(struct host1x_client *client) { struct drm_device *drm = dev_get_drvdata(client->host); @@ -2226,6 +2236,16 @@ static int tegra_dc_exit(struct host1x_client *client) return 0; } +static int tegra_dc_late_exit(struct host1x_client *client) +{ + struct drm_device *drm = dev_get_drvdata(client->host); + struct tegra_drm *tegra = drm->dev_private; + + tegra->num_crtcs--; + + return 0; +} + static int tegra_dc_runtime_suspend(struct host1x_client *client) { struct tegra_dc *dc = host1x_client_to_dc(client); @@ -2290,8 +2310,10 @@ static int tegra_dc_runtime_resume(struct host1x_client *client) } static const struct host1x_client_ops dc_client_ops = { + .early_init = tegra_dc_early_init, .init = tegra_dc_init, .exit = tegra_dc_exit, + .late_exit = tegra_dc_late_exit, .suspend = tegra_dc_runtime_suspend, .resume = tegra_dc_runtime_resume, }; diff --git a/drivers/gpu/drm/tegra/drm.h b/drivers/gpu/drm/tegra/drm.h index 34fbcd6abf2f..9a089b93da24 100644 --- a/drivers/gpu/drm/tegra/drm.h +++ b/drivers/gpu/drm/tegra/drm.h @@ -56,6 +56,7 @@ struct tegra_drm { unsigned int hmask, vmask; unsigned int pitch_align; + unsigned int num_crtcs; struct tegra_display_hub *hub; }; diff --git a/drivers/gpu/drm/tegra/hub.c b/drivers/gpu/drm/tegra/hub.c index 617240032c37..500c9d37e654 100644 --- a/drivers/gpu/drm/tegra/hub.c +++ b/drivers/gpu/drm/tegra/hub.c @@ -562,9 +562,8 @@ struct drm_plane *tegra_shared_plane_create(struct drm_device *drm, enum drm_plane_type type = DRM_PLANE_TYPE_OVERLAY; struct tegra_drm *tegra = drm->dev_private; struct tegra_display_hub *hub = tegra->hub; - /* planes can be assigned to arbitrary CRTCs */ - unsigned int possible_crtcs = 0x7; struct tegra_shared_plane *plane; + unsigned int possible_crtcs; unsigned int num_formats; const u64 *modifiers; struct drm_plane *p; @@ -583,6 +582,9 @@ struct drm_plane *tegra_shared_plane_create(struct drm_device *drm, p = &plane->base.base; + /* planes can be assigned to arbitrary CRTCs */ + possible_crtcs = BIT(tegra->num_crtcs) - 1; + num_formats = ARRAY_SIZE(tegra_shared_plane_formats); formats = tegra_shared_plane_formats; modifiers = tegra_shared_plane_modifiers; From patchwork Fri Mar 26 14:51:39 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 1458846 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; 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Fri, 26 Mar 2021 07:51:55 -0700 (PDT) Received: from localhost ([62.96.65.119]) by smtp.gmail.com with ESMTPSA id v18sm13858177wrf.41.2021.03.26.07.51.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Mar 2021 07:51:53 -0700 (PDT) From: Thierry Reding To: Thierry Reding Cc: David Airlie , Daniel Vetter , Maarten Lankhorst , Thomas Zimmermann , Maxime Ripard , James Jones , Dmitry Osipenko , Simon Ser , dri-devel@lists.freedesktop.org, linux-tegra@vger.kernel.org Subject: [PATCH v2 10/10] drm/tegra: Support sector layout on Tegra194 Date: Fri, 26 Mar 2021 15:51:39 +0100 Message-Id: <20210326145139.467072-11-thierry.reding@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210326145139.467072-1-thierry.reding@gmail.com> References: <20210326145139.467072-1-thierry.reding@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Thierry Reding Tegra194 has a special physical address bit that enables some memory swizzling logic to support different sector layouts. Support the bit that selects the sector layout which is passed in the framebuffer modifier. Signed-off-by: Thierry Reding --- drivers/gpu/drm/tegra/dc.c | 7 +++++++ drivers/gpu/drm/tegra/dc.h | 1 + drivers/gpu/drm/tegra/drm.h | 3 +++ drivers/gpu/drm/tegra/fb.c | 9 +++++++++ drivers/gpu/drm/tegra/gem.h | 6 ++++++ drivers/gpu/drm/tegra/hub.c | 28 ++++++++++++++++++++++++++++ drivers/gpu/drm/tegra/plane.c | 24 ++++++++++++++++++++++++ 7 files changed, 78 insertions(+) diff --git a/drivers/gpu/drm/tegra/dc.c b/drivers/gpu/drm/tegra/dc.c index 0c51f0bb17a9..2f6c02bf96e5 100644 --- a/drivers/gpu/drm/tegra/dc.c +++ b/drivers/gpu/drm/tegra/dc.c @@ -2323,6 +2323,7 @@ static const struct tegra_dc_soc_info tegra20_dc_soc_info = { .supports_interlacing = false, .supports_cursor = false, .supports_block_linear = false, + .supports_sector_layout = false, .has_legacy_blending = true, .pitch_align = 8, .has_powergate = false, @@ -2342,6 +2343,7 @@ static const struct tegra_dc_soc_info tegra30_dc_soc_info = { .supports_interlacing = false, .supports_cursor = false, .supports_block_linear = false, + .supports_sector_layout = false, .has_legacy_blending = true, .pitch_align = 8, .has_powergate = false, @@ -2361,6 +2363,7 @@ static const struct tegra_dc_soc_info tegra114_dc_soc_info = { .supports_interlacing = false, .supports_cursor = false, .supports_block_linear = false, + .supports_sector_layout = false, .has_legacy_blending = true, .pitch_align = 64, .has_powergate = true, @@ -2380,6 +2383,7 @@ static const struct tegra_dc_soc_info tegra124_dc_soc_info = { .supports_interlacing = true, .supports_cursor = true, .supports_block_linear = true, + .supports_sector_layout = false, .has_legacy_blending = false, .pitch_align = 64, .has_powergate = true, @@ -2399,6 +2403,7 @@ static const struct tegra_dc_soc_info tegra210_dc_soc_info = { .supports_interlacing = true, .supports_cursor = true, .supports_block_linear = true, + .supports_sector_layout = false, .has_legacy_blending = false, .pitch_align = 64, .has_powergate = true, @@ -2452,6 +2457,7 @@ static const struct tegra_dc_soc_info tegra186_dc_soc_info = { .supports_interlacing = true, .supports_cursor = true, .supports_block_linear = true, + .supports_sector_layout = false, .has_legacy_blending = false, .pitch_align = 64, .has_powergate = false, @@ -2500,6 +2506,7 @@ static const struct tegra_dc_soc_info tegra194_dc_soc_info = { .supports_interlacing = true, .supports_cursor = true, .supports_block_linear = true, + .supports_sector_layout = true, .has_legacy_blending = false, .pitch_align = 64, .has_powergate = false, diff --git a/drivers/gpu/drm/tegra/dc.h b/drivers/gpu/drm/tegra/dc.h index 21074cd2ce5e..29f19c3c6149 100644 --- a/drivers/gpu/drm/tegra/dc.h +++ b/drivers/gpu/drm/tegra/dc.h @@ -52,6 +52,7 @@ struct tegra_dc_soc_info { bool supports_interlacing; bool supports_cursor; bool supports_block_linear; + bool supports_sector_layout; bool has_legacy_blending; unsigned int pitch_align; bool has_powergate; diff --git a/drivers/gpu/drm/tegra/drm.h b/drivers/gpu/drm/tegra/drm.h index 9a089b93da24..fe1a37e95bfa 100644 --- a/drivers/gpu/drm/tegra/drm.h +++ b/drivers/gpu/drm/tegra/drm.h @@ -24,6 +24,9 @@ #include "hub.h" #include "trace.h" +/* XXX move to include/uapi/drm/drm_fourcc.h? */ +#define DRM_FORMAT_MOD_NVIDIA_SECTOR_LAYOUT BIT(22) + struct reset_control; #ifdef CONFIG_DRM_FBDEV_EMULATION diff --git a/drivers/gpu/drm/tegra/fb.c b/drivers/gpu/drm/tegra/fb.c index 350f33206076..c04dda8353fd 100644 --- a/drivers/gpu/drm/tegra/fb.c +++ b/drivers/gpu/drm/tegra/fb.c @@ -44,6 +44,15 @@ int tegra_fb_get_tiling(struct drm_framebuffer *framebuffer, { uint64_t modifier = framebuffer->modifier; + if (fourcc_mod_is_vendor(modifier, NVIDIA)) { + if ((modifier & DRM_FORMAT_MOD_NVIDIA_SECTOR_LAYOUT) == 0) + tiling->sector_layout = TEGRA_BO_SECTOR_LAYOUT_TEGRA; + else + tiling->sector_layout = TEGRA_BO_SECTOR_LAYOUT_GPU; + + modifier &= ~DRM_FORMAT_MOD_NVIDIA_SECTOR_LAYOUT; + } + switch (modifier) { case DRM_FORMAT_MOD_LINEAR: tiling->mode = TEGRA_BO_TILING_MODE_PITCH; diff --git a/drivers/gpu/drm/tegra/gem.h b/drivers/gpu/drm/tegra/gem.h index fafb5724499b..c15fd99d6cb2 100644 --- a/drivers/gpu/drm/tegra/gem.h +++ b/drivers/gpu/drm/tegra/gem.h @@ -21,9 +21,15 @@ enum tegra_bo_tiling_mode { TEGRA_BO_TILING_MODE_BLOCK, }; +enum tegra_bo_sector_layout { + TEGRA_BO_SECTOR_LAYOUT_TEGRA, + TEGRA_BO_SECTOR_LAYOUT_GPU, +}; + struct tegra_bo_tiling { enum tegra_bo_tiling_mode mode; unsigned long value; + enum tegra_bo_sector_layout sector_layout; }; struct tegra_bo { diff --git a/drivers/gpu/drm/tegra/hub.c b/drivers/gpu/drm/tegra/hub.c index 500c9d37e654..79bff8b48271 100644 --- a/drivers/gpu/drm/tegra/hub.c +++ b/drivers/gpu/drm/tegra/hub.c @@ -55,6 +55,18 @@ static const u64 tegra_shared_plane_modifiers[] = { DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(3), DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(4), DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(5), + /* + * The GPU sector layout is only supported on Tegra194, but these will + * be filtered out later on by ->format_mod_supported() on SoCs where + * it isn't supported. + */ + DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(0) | DRM_FORMAT_MOD_NVIDIA_SECTOR_LAYOUT, + DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(1) | DRM_FORMAT_MOD_NVIDIA_SECTOR_LAYOUT, + DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(2) | DRM_FORMAT_MOD_NVIDIA_SECTOR_LAYOUT, + DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(3) | DRM_FORMAT_MOD_NVIDIA_SECTOR_LAYOUT, + DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(4) | DRM_FORMAT_MOD_NVIDIA_SECTOR_LAYOUT, + DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(5) | DRM_FORMAT_MOD_NVIDIA_SECTOR_LAYOUT, + /* sentinel */ DRM_FORMAT_MOD_INVALID }; @@ -366,6 +378,12 @@ static int tegra_shared_plane_atomic_check(struct drm_plane *plane, return -EINVAL; } + if (tiling->sector_layout == TEGRA_BO_SECTOR_LAYOUT_GPU && + !dc->soc->supports_sector_layout) { + DRM_ERROR("hardware doesn't support GPU sector layout\n"); + return -EINVAL; + } + /* * Tegra doesn't support different strides for U and V planes so we * error out if the user tries to display a framebuffer with such a @@ -485,6 +503,16 @@ static void tegra_shared_plane_atomic_update(struct drm_plane *plane, base = tegra_plane_state->iova[0] + fb->offsets[0]; +#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT + /* + * Physical address bit 39 in Tegra194 is used as a switch for special + * logic that swizzles the memory using either the legacy Tegra or the + * dGPU sector layout. + */ + if (tegra_plane_state->tiling.sector_layout == TEGRA_BO_SECTOR_LAYOUT_GPU) + base |= BIT(39); +#endif + tegra_plane_writel(p, tegra_plane_state->format, DC_WIN_COLOR_DEPTH); tegra_plane_writel(p, 0, DC_WIN_PRECOMP_WGRP_PARAMS); diff --git a/drivers/gpu/drm/tegra/plane.c b/drivers/gpu/drm/tegra/plane.c index 793da5d675d2..1e0eae8b4342 100644 --- a/drivers/gpu/drm/tegra/plane.c +++ b/drivers/gpu/drm/tegra/plane.c @@ -83,6 +83,22 @@ static void tegra_plane_atomic_destroy_state(struct drm_plane *plane, kfree(state); } +static bool tegra_plane_supports_sector_layout(struct drm_plane *plane) +{ + struct drm_crtc *crtc; + + drm_for_each_crtc(crtc, plane->dev) { + if (plane->possible_crtcs & drm_crtc_mask(crtc)) { + struct tegra_dc *dc = to_tegra_dc(crtc); + + if (!dc->soc->supports_sector_layout) + return false; + } + } + + return true; +} + static bool tegra_plane_format_mod_supported(struct drm_plane *plane, uint32_t format, uint64_t modifier) @@ -92,6 +108,14 @@ static bool tegra_plane_format_mod_supported(struct drm_plane *plane, if (modifier == DRM_FORMAT_MOD_LINEAR) return true; + /* check for the sector layout bit */ + if (fourcc_mod_is_vendor(modifier, NVIDIA)) { + if (modifier & DRM_FORMAT_MOD_NVIDIA_SECTOR_LAYOUT) { + if (!tegra_plane_supports_sector_layout(plane)) + return false; + } + } + if (info->num_planes == 1) return true;