From patchwork Tue Mar 23 14:03:51 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Sandiford X-Patchwork-Id: 1457224 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=sourceware.org; envelope-from=gcc-patches-bounces@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.a=rsa-sha256 header.s=default header.b=PwhpfABj; dkim-atps=neutral Received: from sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4F4Y4w0jKtz9sTD for ; Wed, 24 Mar 2021 01:03:59 +1100 (AEDT) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 8B82A385BF9E; Tue, 23 Mar 2021 14:03:56 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 8B82A385BF9E DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1616508236; bh=msUZbaP0/Z2CwqbygZTlESNSBpg5vflR8epFFsScwYA=; h=To:Subject:Date:List-Id:List-Unsubscribe:List-Archive:List-Post: List-Help:List-Subscribe:From:Reply-To:From; b=PwhpfABjHoiNguXma4/Dpn+z9+VM18jovlydKifxwMmTXjFda5Jrq4T2ViR5Ogoye ZB2vKdMhhw8kR8xhIZBXTDG6m3MyiITmCsdodlYOuiVAoFlRntyR9U8IueJTg+ABEj 8SDM+X6CS4rVFmuYrbK1jCbYOoYH1HYQ09/Z7hEQ= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by sourceware.org (Postfix) with ESMTP id B807B385701F for ; Tue, 23 Mar 2021 14:03:53 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.3.2 sourceware.org B807B385701F Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 380C3D6E for ; Tue, 23 Mar 2021 07:03:53 -0700 (PDT) Received: from localhost (e121540-lin.manchester.arm.com [10.32.98.126]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id D2E9A3F719 for ; Tue, 23 Mar 2021 07:03:52 -0700 (PDT) To: gcc-patches@gcc.gnu.org Mail-Followup-To: gcc-patches@gcc.gnu.org, richard.sandiford@arm.com Subject: [committed] aarch64: Make aarch64_add_offset work with -ftrapv [PR99540] Date: Tue, 23 Mar 2021 14:03:51 +0000 Message-ID: User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/26.3 (gnu/linux) MIME-Version: 1.0 X-Spam-Status: No, score=-12.6 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Richard Sandiford via Gcc-patches From: Richard Sandiford Reply-To: Richard Sandiford Errors-To: gcc-patches-bounces@gcc.gnu.org Sender: "Gcc-patches" aarch64_add_offset uses expand_mult to multiply the SVE VL by an out-of-range constant. expand_mult takes an argument to indicate whether the multiplication is signed or unsigned, but in this context the multiplication is effectively signless and so the choice seemed arbitrary. However, one of the things that the signedness input does is indicate whether signed overflow should be trapped for -ftrapv. We don't want that here, so we must treat the multiplication as unsigned. Tested on aarch64-linux-gnu (with and without SVE). Pushed to trunk so far. Will backport to GCC 10 tomorrow. Richard gcc/ 2021-03-23 Jakub Jelinek PR target/99540 * config/aarch64/aarch64.c (aarch64_add_offset): Tell expand_mult to perform an unsigned rather than a signed multiplication. gcc/testsuite/ 2021-03-23 Richard Sandiford PR target/99540 * gcc.dg/vect/pr99540.c: New test. --- gcc/config/aarch64/aarch64.c | 2 +- gcc/testsuite/gcc.dg/vect/pr99540.c | 20 ++++++++++++++++++++ 2 files changed, 21 insertions(+), 1 deletion(-) create mode 100644 gcc/testsuite/gcc.dg/vect/pr99540.c diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c index db69e6983d0..c8a87fe858a 100644 --- a/gcc/config/aarch64/aarch64.c +++ b/gcc/config/aarch64/aarch64.c @@ -4639,7 +4639,7 @@ aarch64_add_offset (scalar_int_mode mode, rtx dest, rtx src, if (can_create_pseudo_p ()) { rtx coeff1 = gen_int_mode (factor, mode); - val = expand_mult (mode, val, coeff1, NULL_RTX, false, true); + val = expand_mult (mode, val, coeff1, NULL_RTX, true, true); } else { diff --git a/gcc/testsuite/gcc.dg/vect/pr99540.c b/gcc/testsuite/gcc.dg/vect/pr99540.c new file mode 100644 index 00000000000..9136b099d94 --- /dev/null +++ b/gcc/testsuite/gcc.dg/vect/pr99540.c @@ -0,0 +1,20 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-ftrapv -ffloat-store -march=armv8.2-a+sve" { target aarch64*-*-* } } */ + +float *MSalign2m2m_rec_initverticalw, *MSalign2m2m_rec_currentw; + +void +match_ribosum (int MSalign2m2m_rec_i, int MSalign2m2m_rec_lgth1, + int MSalign2m2m_rec_lgth2) +{ + float **WMMTX; + + while (MSalign2m2m_rec_i < 1) + WMMTX[MSalign2m2m_rec_i++][0] = MSalign2m2m_rec_initverticalw[0]; + + while (MSalign2m2m_rec_i < MSalign2m2m_rec_lgth1) + MSalign2m2m_rec_initverticalw[MSalign2m2m_rec_i++] += 0.1; + + while (MSalign2m2m_rec_i < MSalign2m2m_rec_lgth2) + MSalign2m2m_rec_currentw[MSalign2m2m_rec_i++] += 0.1; +}