From patchwork Tue Mar 16 21:31:03 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dimitri John Ledkov X-Patchwork-Id: 1454504 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.ubuntu.com (client-ip=91.189.94.19; helo=huckleberry.canonical.com; envelope-from=kernel-team-bounces@lists.ubuntu.com; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; secure) header.d=surgut.co.uk header.i=@surgut.co.uk header.a=rsa-sha256 header.s=google header.b=Q13oIZDm; dkim-atps=neutral Received: from huckleberry.canonical.com (huckleberry.canonical.com [91.189.94.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4F0gtc0RRVz9sxS; Wed, 17 Mar 2021 17:56:39 +1100 (AEDT) Received: from localhost ([127.0.0.1] helo=huckleberry.canonical.com) by huckleberry.canonical.com with esmtp (Exim 4.86_2) (envelope-from ) id 1lMQ6Y-0000TU-Ho; Wed, 17 Mar 2021 06:56:30 +0000 Received: from mail-wr1-f44.google.com ([209.85.221.44]) by huckleberry.canonical.com with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.86_2) (envelope-from ) id 1lMHHp-0005n8-UL for kernel-team@lists.ubuntu.com; Tue, 16 Mar 2021 21:31:33 +0000 Received: by mail-wr1-f44.google.com with SMTP id o16so8186154wrn.0 for ; Tue, 16 Mar 2021 14:31:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=surgut.co.uk; s=google; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=lIENocVPzpcn2PD2lQU3E1KIE4AvsbAdgH6qYiqQnhE=; b=Q13oIZDmbN60ihDNW9DOrifFpASIQfpDJ52EWqKuyRZ+wjaqXs4J+DyOLVBIQbuqPF aig0O0+aiN83/e5FgcaLqkvMgQC/Jh9tq1DD75MZPuwP0e5wqxs0mcRsFTIHkR0Kcl40 Gd9iyGvBSI+jH3S102+AB8wxotoW2vmOxmRdU= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=lIENocVPzpcn2PD2lQU3E1KIE4AvsbAdgH6qYiqQnhE=; b=UoGXIVmJ2jmlPZSRSG/8Aynsd6M0EymE9IrYKK/dvjJefNRELo9OdpIcoQOHQCVpq1 4mghwUMqOQFdf873WNmRADOh68Z59qU84oeO9AQGf2XqgzqhdX8EdmZJhravJVUa+zO1 h8giCrIhKisMgc3DqwPeDHSYtpdWipTi04rg0CDjDtLCBD+MYX8/AdjebQs7fVi2IZcr nhw86smMECzJamXZCp1re3lSJRTgPWFJ0k6AJJ+a3QzlauvPSJBR0mECijF8gVRrnrtw Fv1Tde3SwH3nlA078dZdr14As8xcEjFzhwnwdOvwB7vPg2N8eK3M7D8RO17DDekyyiid bKzg== X-Gm-Message-State: AOAM532dMyBMmAkh8xFFunzL9WqVjme1Grnptq4NuNKlLsotc7vVy23T kz88LoO0ue/ItrnDiPh6D8RaJL2UCxjAPg== X-Google-Smtp-Source: ABdhPJwE8+lZbZ9rogVJcVk7Da/n7c7iEHBJo99cX5PieiuM8t90ctGVtyIVg5UivhsktFOl5KTZOA== X-Received: by 2002:a5d:6404:: with SMTP id z4mr1009525wru.109.1615930293266; Tue, 16 Mar 2021 14:31:33 -0700 (PDT) Received: from localhost ([2a01:4b00:85fd:d700:da2f:147e:3a8a:27aa]) by smtp.gmail.com with ESMTPSA id u63sm539822wmg.24.2021.03.16.14.31.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Mar 2021 14:31:32 -0700 (PDT) From: Dimitri John Ledkov To: kernel-team@lists.ubuntu.com Subject: [PATCH 01/15] riscv: dts: fu740: fix cache-controller interrupts Date: Tue, 16 Mar 2021 21:31:03 +0000 Message-Id: <20210316213117.757193-2-xnox@ubuntu.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20210316213117.757193-1-xnox@ubuntu.com> References: <20210316213117.757193-1-xnox@ubuntu.com> MIME-Version: 1.0 X-Mailman-Approved-At: Wed, 17 Mar 2021 06:56:26 +0000 X-BeenThere: kernel-team@lists.ubuntu.com X-Mailman-Version: 2.1.20 Precedence: list List-Id: Kernel team discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: kernel-team-bounces@lists.ubuntu.com Sender: "kernel-team" From: David Abdurachmanov The order of interrupt numbers is incorrect. The order for FU740 is: DirError, DataError, DataFail, DirFail From SiFive FU740-C000 Manual: 19 - L2 Cache DirError 20 - L2 Cache DirFail 21 - L2 Cache DataError 22 - L2 Cache DataFail Signed-off-by: David Abdurachmanov Signed-off-by: Dimitri John Ledkov --- arch/riscv/boot/dts/sifive/fu740-c000.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/riscv/boot/dts/sifive/fu740-c000.dtsi b/arch/riscv/boot/dts/sifive/fu740-c000.dtsi index eeb4f8c3e0e7..d0d206cdb999 100644 --- a/arch/riscv/boot/dts/sifive/fu740-c000.dtsi +++ b/arch/riscv/boot/dts/sifive/fu740-c000.dtsi @@ -272,7 +272,7 @@ ccache: cache-controller@2010000 { cache-size = <2097152>; cache-unified; interrupt-parent = <&plic0>; - interrupts = <19 20 21 22>; + interrupts = <19 21 22 20>; reg = <0x0 0x2010000 0x0 0x1000>; }; gpio: gpio@10060000 { From patchwork Tue Mar 16 21:31:04 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dimitri John Ledkov X-Patchwork-Id: 1454505 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; 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Tue, 16 Mar 2021 14:31:35 -0700 (PDT) Received: from localhost ([2a01:4b00:85fd:d700:da2f:147e:3a8a:27aa]) by smtp.gmail.com with ESMTPSA id x13sm22990650wrt.75.2021.03.16.14.31.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Mar 2021 14:31:34 -0700 (PDT) From: Dimitri John Ledkov To: kernel-team@lists.ubuntu.com Subject: [PATCH 02/15] riscv: sifive: fu740: cpu{1, 2, 3, 4} set compatible to sifive, u74-mc Date: Tue, 16 Mar 2021 21:31:04 +0000 Message-Id: <20210316213117.757193-3-xnox@ubuntu.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20210316213117.757193-1-xnox@ubuntu.com> References: <20210316213117.757193-1-xnox@ubuntu.com> MIME-Version: 1.0 X-Mailman-Approved-At: Wed, 17 Mar 2021 06:56:26 +0000 X-BeenThere: kernel-team@lists.ubuntu.com X-Mailman-Version: 2.1.20 Precedence: list List-Id: Kernel team discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: kernel-team-bounces@lists.ubuntu.com Sender: "kernel-team" From: David Abdurachmanov Signed-off-by: David Abdurachmanov Signed-off-by: Dimitri John Ledkov --- arch/riscv/boot/dts/sifive/fu740-c000.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/riscv/boot/dts/sifive/fu740-c000.dtsi b/arch/riscv/boot/dts/sifive/fu740-c000.dtsi index d0d206cdb999..cd9cc025777d 100644 --- a/arch/riscv/boot/dts/sifive/fu740-c000.dtsi +++ b/arch/riscv/boot/dts/sifive/fu740-c000.dtsi @@ -39,7 +39,7 @@ cpu0_intc: interrupt-controller { }; }; cpu1: cpu@1 { - compatible = "sifive,bullet0", "riscv"; + compatible = "sifive,u74-mc", "sifive,bullet0", "riscv"; d-cache-block-size = <64>; d-cache-sets = <64>; d-cache-size = <32768>; @@ -63,7 +63,7 @@ cpu1_intc: interrupt-controller { }; }; cpu2: cpu@2 { - compatible = "sifive,bullet0", "riscv"; + compatible = "sifive,u74-mc", "sifive,bullet0", "riscv"; d-cache-block-size = <64>; d-cache-sets = <64>; d-cache-size = <32768>; @@ -87,7 +87,7 @@ cpu2_intc: interrupt-controller { }; }; cpu3: cpu@3 { - compatible = "sifive,bullet0", "riscv"; + compatible = "sifive,u74-mc", "sifive,bullet0", "riscv"; d-cache-block-size = <64>; d-cache-sets = <64>; d-cache-size = <32768>; @@ -111,7 +111,7 @@ cpu3_intc: interrupt-controller { }; }; cpu4: cpu@4 { - compatible = "sifive,bullet0", "riscv"; + compatible = "sifive,u74-mc", "sifive,bullet0", "riscv"; d-cache-block-size = <64>; d-cache-sets = <64>; d-cache-size = <32768>; From patchwork Tue Mar 16 21:31:05 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dimitri John Ledkov X-Patchwork-Id: 1454502 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; 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Tue, 16 Mar 2021 14:31:37 -0700 (PDT) Received: from localhost ([2a01:4b00:85fd:d700:da2f:147e:3a8a:27aa]) by smtp.gmail.com with ESMTPSA id x11sm555683wmi.3.2021.03.16.14.31.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Mar 2021 14:31:37 -0700 (PDT) From: Dimitri John Ledkov To: kernel-team@lists.ubuntu.com Subject: [PATCH 03/15] riscv: sifive: unmatched: update for 16GB rev3 Date: Tue, 16 Mar 2021 21:31:05 +0000 Message-Id: <20210316213117.757193-4-xnox@ubuntu.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20210316213117.757193-1-xnox@ubuntu.com> References: <20210316213117.757193-1-xnox@ubuntu.com> MIME-Version: 1.0 X-Mailman-Approved-At: Wed, 17 Mar 2021 06:56:26 +0000 X-BeenThere: kernel-team@lists.ubuntu.com X-Mailman-Version: 2.1.20 Precedence: list List-Id: Kernel team discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: kernel-team-bounces@lists.ubuntu.com Sender: "kernel-team" From: David Abdurachmanov Signed-off-by: David Abdurachmanov Signed-off-by: Dimitri John Ledkov --- .../boot/dts/sifive/hifive-unmatched-a00.dts | 34 +++++++++---------- 1 file changed, 17 insertions(+), 17 deletions(-) diff --git a/arch/riscv/boot/dts/sifive/hifive-unmatched-a00.dts b/arch/riscv/boot/dts/sifive/hifive-unmatched-a00.dts index b1c3c596578f..e026f60af09e 100644 --- a/arch/riscv/boot/dts/sifive/hifive-unmatched-a00.dts +++ b/arch/riscv/boot/dts/sifive/hifive-unmatched-a00.dts @@ -24,7 +24,7 @@ cpus { memory@80000000 { device_type = "memory"; - reg = <0x0 0x80000000 0x2 0x00000000>; + reg = <0x0 0x80000000 0x4 0x00000000>; }; soc { @@ -72,16 +72,16 @@ pmic@58 { regulators { vdd_bcore1: bcore1 { - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <900000>; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; regulator-min-microamp = <5000000>; regulator-max-microamp = <5000000>; regulator-always-on; }; vdd_bcore2: bcore2 { - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <900000>; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; regulator-min-microamp = <5000000>; regulator-max-microamp = <5000000>; regulator-always-on; @@ -136,48 +136,48 @@ vdd_ldo2: ldo2 { }; vdd_ldo3: ldo3 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; regulator-min-microamp = <200000>; regulator-max-microamp = <200000>; regulator-always-on; }; vdd_ldo4: ldo4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; regulator-min-microamp = <200000>; regulator-max-microamp = <200000>; regulator-always-on; }; vdd_ldo5: ldo5 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; regulator-min-microamp = <100000>; regulator-max-microamp = <100000>; regulator-always-on; }; vdd_ldo6: ldo6 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; regulator-min-microamp = <200000>; regulator-max-microamp = <200000>; regulator-always-on; }; vdd_ldo7: ldo7 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; regulator-min-microamp = <200000>; regulator-max-microamp = <200000>; regulator-always-on; }; vdd_ldo8: ldo8 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; regulator-min-microamp = <200000>; regulator-max-microamp = <200000>; regulator-always-on; From patchwork Tue Mar 16 21:31:06 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dimitri John Ledkov X-Patchwork-Id: 1454500 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.ubuntu.com (client-ip=91.189.94.19; helo=huckleberry.canonical.com; envelope-from=kernel-team-bounces@lists.ubuntu.com; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; secure) header.d=surgut.co.uk header.i=@surgut.co.uk header.a=rsa-sha256 header.s=google header.b=Vh5lpDtm; dkim-atps=neutral Received: from huckleberry.canonical.com (huckleberry.canonical.com [91.189.94.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4F0gtc1QwBz9t0J; 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Tue, 16 Mar 2021 14:31:38 -0700 (PDT) From: Dimitri John Ledkov To: kernel-team@lists.ubuntu.com Subject: [PATCH 04/15] riscv: Add 3 SBI wrapper functions to get cpu manufacturer information Date: Tue, 16 Mar 2021 21:31:06 +0000 Message-Id: <20210316213117.757193-5-xnox@ubuntu.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20210316213117.757193-1-xnox@ubuntu.com> References: <20210316213117.757193-1-xnox@ubuntu.com> MIME-Version: 1.0 X-Mailman-Approved-At: Wed, 17 Mar 2021 06:56:26 +0000 X-BeenThere: kernel-team@lists.ubuntu.com X-Mailman-Version: 2.1.20 Precedence: list List-Id: Kernel team discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: kernel-team-bounces@lists.ubuntu.com Sender: "kernel-team" From: Vincent Chen Add 3 wrapper functions to get vendor id, architecture id and implement id from M-mode Signed-off-by: Vincent Chen Signed-off-by: Dimitri John Ledkov --- arch/riscv/include/asm/sbi.h | 3 +++ arch/riscv/kernel/sbi.c | 15 +++++++++++++++ 2 files changed, 18 insertions(+) diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h index 653edb25d495..97eb78d8025f 100644 --- a/arch/riscv/include/asm/sbi.h +++ b/arch/riscv/include/asm/sbi.h @@ -97,6 +97,9 @@ struct sbiret sbi_ecall(int ext, int fid, unsigned long arg0, void sbi_console_putchar(int ch); int sbi_console_getchar(void); +long sbi_get_vendorid(void); +long sbi_get_archid(void); +long sbi_get_impid(void); void sbi_set_timer(uint64_t stime_value); void sbi_shutdown(void); void sbi_clear_ipi(void); diff --git a/arch/riscv/kernel/sbi.c b/arch/riscv/kernel/sbi.c index 226ccce0f9e0..b8f82c73deb7 100644 --- a/arch/riscv/kernel/sbi.c +++ b/arch/riscv/kernel/sbi.c @@ -547,6 +547,21 @@ static inline long sbi_get_firmware_version(void) return __sbi_base_ecall(SBI_EXT_BASE_GET_IMP_VERSION); } +long sbi_get_vendorid(void) +{ + return __sbi_base_ecall(SBI_EXT_BASE_GET_MVENDORID); +} + +long sbi_get_archid(void) +{ + return __sbi_base_ecall(SBI_EXT_BASE_GET_MARCHID); +} + +long sbi_get_impid(void) +{ + return __sbi_base_ecall(SBI_EXT_BASE_GET_MIMPID); +} + static void sbi_send_cpumask_ipi(const struct cpumask *target) { struct cpumask hartid_mask; From patchwork Tue Mar 16 21:31:07 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dimitri John Ledkov X-Patchwork-Id: 1454496 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; 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Tue, 16 Mar 2021 14:31:40 -0700 (PDT) Received: from localhost ([2a01:4b00:85fd:d700:da2f:147e:3a8a:27aa]) by smtp.gmail.com with ESMTPSA id g16sm24643083wrs.76.2021.03.16.14.31.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Mar 2021 14:31:39 -0700 (PDT) From: Dimitri John Ledkov To: kernel-team@lists.ubuntu.com Subject: [PATCH 05/15] riscv: Get CPU manufacturer information Date: Tue, 16 Mar 2021 21:31:07 +0000 Message-Id: <20210316213117.757193-6-xnox@ubuntu.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20210316213117.757193-1-xnox@ubuntu.com> References: <20210316213117.757193-1-xnox@ubuntu.com> MIME-Version: 1.0 X-Mailman-Approved-At: Wed, 17 Mar 2021 06:56:26 +0000 X-BeenThere: kernel-team@lists.ubuntu.com X-Mailman-Version: 2.1.20 Precedence: list List-Id: Kernel team discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: kernel-team-bounces@lists.ubuntu.com Sender: "kernel-team" From: Vincent Chen Issue 3 SBI calls to get the vendor ID, architecture ID and implementation ID early in boot so we only need to take the SBI call overhead once. Signed-off-by: Vincent Chen Signed-off-by: Dimitri John Ledkov --- arch/riscv/include/asm/csr.h | 3 +++ arch/riscv/include/asm/hwcap.h | 6 ++++++ arch/riscv/include/asm/processor.h | 2 ++ arch/riscv/include/asm/soc.h | 1 + arch/riscv/kernel/cpufeature.c | 17 +++++++++++++++++ arch/riscv/kernel/setup.c | 2 ++ arch/riscv/kernel/soc.c | 1 + 7 files changed, 32 insertions(+) diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h index cec462e198ce..076beb9447c1 100644 --- a/arch/riscv/include/asm/csr.h +++ b/arch/riscv/include/asm/csr.h @@ -109,6 +109,9 @@ #define CSR_MIP 0x344 #define CSR_PMPCFG0 0x3a0 #define CSR_PMPADDR0 0x3b0 +#define CSR_MVENDORID 0xf11 +#define CSR_MARCHID 0xf12 +#define CSR_MIMPID 0xf13 #define CSR_MHARTID 0xf14 #ifdef CONFIG_RISCV_M_MODE diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index 5ce50468aff1..b7409487c9d2 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -44,6 +44,12 @@ bool __riscv_isa_extension_available(const unsigned long *isa_bitmap, int bit); #define riscv_isa_extension_available(isa_bitmap, ext) \ __riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_##ext) +struct cpu_manufacturer_info_t { + unsigned long vendor_id; + unsigned long arch_id; + unsigned long imp_id; +}; + #endif #endif /* _ASM_RISCV_HWCAP_H */ diff --git a/arch/riscv/include/asm/processor.h b/arch/riscv/include/asm/processor.h index bdddcd5c1b71..dee4a259bf34 100644 --- a/arch/riscv/include/asm/processor.h +++ b/arch/riscv/include/asm/processor.h @@ -71,6 +71,8 @@ int riscv_of_parent_hartid(struct device_node *node); extern void riscv_fill_hwcap(void); +void riscv_fill_cpu_manufacturer_info(void); + #endif /* __ASSEMBLY__ */ #endif /* _ASM_RISCV_PROCESSOR_H */ diff --git a/arch/riscv/include/asm/soc.h b/arch/riscv/include/asm/soc.h index 6c8363b1f327..bc3044edbef9 100644 --- a/arch/riscv/include/asm/soc.h +++ b/arch/riscv/include/asm/soc.h @@ -10,6 +10,7 @@ #include #include #include +#include #define SOC_EARLY_INIT_DECLARE(name, compat, fn) \ static const struct of_device_id __soc_early_init__##name \ diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index ac202f44a670..389162ee19ea 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -12,6 +12,8 @@ #include #include #include +#include +#include unsigned long elf_hwcap __read_mostly; @@ -22,6 +24,8 @@ static DECLARE_BITMAP(riscv_isa, RISCV_ISA_EXT_MAX) __read_mostly; bool has_fpu __read_mostly; #endif +struct cpu_manufacturer_info_t cpu_mfr_info; + /** * riscv_isa_extension_base() - Get base extension word * @@ -149,3 +153,16 @@ void riscv_fill_hwcap(void) has_fpu = true; #endif } + +void riscv_fill_cpu_manufacturer_info(void) +{ +#ifndef CONFIG_RISCV_M_MODE + cpu_mfr_info.vendor_id = sbi_get_vendorid(); + cpu_mfr_info.arch_id = sbi_get_archid(); + cpu_mfr_info.imp_id = sbi_get_impid(); +#else + cpu_mfr_info.vendor_id = csr_read(CSR_MVENDORID); + cpu_mfr_info.arch_id = csr_read(CSR_MARCHID); + cpu_mfr_info.imp_id = csr_read(CSR_MIMPID); +#endif +} diff --git a/arch/riscv/kernel/setup.c b/arch/riscv/kernel/setup.c index c7c0655dd45b..595d1d8a586b 100644 --- a/arch/riscv/kernel/setup.c +++ b/arch/riscv/kernel/setup.c @@ -271,6 +271,8 @@ void __init setup_arch(char **cmdline_p) #endif riscv_fill_hwcap(); + + riscv_fill_cpu_manufacturer_info(); } static int __init topology_init(void) diff --git a/arch/riscv/kernel/soc.c b/arch/riscv/kernel/soc.c index c7b0a73e382e..284d4af0ccd8 100644 --- a/arch/riscv/kernel/soc.c +++ b/arch/riscv/kernel/soc.c @@ -6,6 +6,7 @@ #include #include #include +#include /* * This is called extremly early, before parse_dtb(), to allow initializing From patchwork Tue Mar 16 21:31:08 2021 Content-Type: text/plain; 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The main purpose of this patch is to provide a framework. Therefore, the implementation is quite basic for now so that some scenarios could not use this schemei, such as patching code to a module, relocating the patching code and heterogeneous CPU topology. Users could use the macro ALTERNATIVE to apply an errata to the existing code flow. In the macro ALTERNATIVE, users need to specify the manufacturer information(vendorid, archid, and impid) for this errata. Therefore, kernel will know this errata is suitable for which CPU core. During the booting procedure, kernel will select the errata required by the CPU core and then patch it. It means that the kernel only applies the errata to the specified CPU core. In this case the vendor's errata does not affect each other at runtime. The above patching procedure only occurs during the booting phase, so we only take the overhead of the "alternative" mechanism once. This "alternative" mechanism is enabled by default to ensure that all required errata will be applied. However, users can disable this feature by the Kconfig "CONFIG_RISCV_ERRATA_ALTERNATIVE". Signed-off-by: Vincent Chen Signed-off-by: Dimitri John Ledkov --- arch/riscv/Kconfig | 1 + arch/riscv/Kconfig.erratas | 12 +++ arch/riscv/Makefile | 1 + arch/riscv/errata/Makefile | 1 + arch/riscv/errata/alternative.c | 69 ++++++++++++ arch/riscv/include/asm/alternative-macros.h | 110 ++++++++++++++++++++ arch/riscv/include/asm/alternative.h | 44 ++++++++ arch/riscv/include/asm/asm.h | 1 + arch/riscv/include/asm/errata_list.h | 8 ++ arch/riscv/include/asm/sections.h | 2 + arch/riscv/include/asm/vendorid_list.h | 6 ++ arch/riscv/kernel/smpboot.c | 4 + arch/riscv/kernel/vmlinux.lds.S | 14 +++ 13 files changed, 273 insertions(+) create mode 100644 arch/riscv/Kconfig.erratas create mode 100644 arch/riscv/errata/Makefile create mode 100644 arch/riscv/errata/alternative.c create mode 100644 arch/riscv/include/asm/alternative-macros.h create mode 100644 arch/riscv/include/asm/alternative.h create mode 100644 arch/riscv/include/asm/errata_list.h create mode 100644 arch/riscv/include/asm/vendorid_list.h diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index e9553583e86f..4fafd1550292 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -195,6 +195,7 @@ config LOCKDEP_SUPPORT def_bool y source "arch/riscv/Kconfig.socs" +source "arch/riscv/Kconfig.erratas" menu "Platform type" diff --git a/arch/riscv/Kconfig.erratas b/arch/riscv/Kconfig.erratas new file mode 100644 index 000000000000..4d0bafc536df --- /dev/null +++ b/arch/riscv/Kconfig.erratas @@ -0,0 +1,12 @@ +menu "CPU errata selection" + +config RISCV_ERRATA_ALTERNATIVE + bool "RISC-V alternative scheme" + default y + help + This Kconfig allows the kernel to automatically patch the + errata required by the execution platform at run time. The + code patching is performed once in the boot stages. It means + that the overhead from this mechanism is just taken once. + +endmenu diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile index 8c29e553ef7f..2bff64c40a57 100644 --- a/arch/riscv/Makefile +++ b/arch/riscv/Makefile @@ -75,6 +75,7 @@ KBUILD_IMAGE := $(boot)/Image.gz head-y := arch/riscv/kernel/head.o core-y += arch/riscv/ +core-$(CONFIG_RISCV_ERRATA_ALTERNATIVE) += arch/riscv/errata/ libs-y += arch/riscv/lib/ libs-$(CONFIG_EFI_STUB) += $(objtree)/drivers/firmware/efi/libstub/lib.a diff --git a/arch/riscv/errata/Makefile b/arch/riscv/errata/Makefile new file mode 100644 index 000000000000..43e6d5424367 --- /dev/null +++ b/arch/riscv/errata/Makefile @@ -0,0 +1 @@ +obj-y += alternative.o diff --git a/arch/riscv/errata/alternative.c b/arch/riscv/errata/alternative.c new file mode 100644 index 000000000000..052affdce6eb --- /dev/null +++ b/arch/riscv/errata/alternative.c @@ -0,0 +1,69 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * alternative runtime patching + * inspired by the ARM64 and x86 version + * + * Copyright (C) 2021 Sifive. + */ + +#include +#include +#include +#include +#include +#include + +struct alt_region { + struct alt_entry *begin; + struct alt_entry *end; +}; + +static bool (*errata_checkfunc)(struct alt_entry *alt); +typedef int (*patch_func_t)(void *addr, const void *insn, size_t size); + +static void __apply_alternatives(void *alt_region, void *alt_patch_func) +{ + struct alt_entry *alt; + struct alt_region *region = alt_region; + + for (alt = region->begin; alt < region->end; alt++) { + if (!errata_checkfunc(alt)) + continue; + ((patch_func_t)alt_patch_func)(alt->old_ptr, alt->alt_ptr, alt->alt_len); + } +} + +static void __init init_alternative(void) +{ + struct errata_checkfunc_id *ptr; + + for (ptr = (struct errata_checkfunc_id *)__alt_checkfunc_table; + ptr < (struct errata_checkfunc_id *)__alt_checkfunc_table_end; + ptr++) { + if (cpu_mfr_info.vendor_id == ptr->vendor_id) + errata_checkfunc = ptr->func; + } +} + +/* + * This is called very early in the boot process (directly after we run + * a feature detect on the boot CPU). No need to worry about other CPUs + * here. + */ +void __init apply_boot_alternatives(void) +{ + struct alt_region region; + + /* If called on non-boot cpu things could go wrong */ + WARN_ON(smp_processor_id() != 0); + + init_alternative(); + + if (!errata_checkfunc) + return; + + region.begin = (struct alt_entry *)__alt_start; + region.end = (struct alt_entry *)__alt_end; + __apply_alternatives(®ion, patch_text_nosync); +} + diff --git a/arch/riscv/include/asm/alternative-macros.h b/arch/riscv/include/asm/alternative-macros.h new file mode 100644 index 000000000000..7b6f0c94b1fb --- /dev/null +++ b/arch/riscv/include/asm/alternative-macros.h @@ -0,0 +1,110 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __ASM_ALTERNATIVE_MACROS_H +#define __ASM_ALTERNATIVE_MACROS_H + +#ifdef CONFIG_RISCV_ERRATA_ALTERNATIVE + +#ifndef __ASSEMBLY__ + +#include +#include + +#define ALT_ENTRY(oldptr, altptr, vendor_id, errata_id, altlen) \ + RISCV_PTR " " oldptr "\n" \ + RISCV_PTR " " altptr "\n" \ + REG_ASM " " vendor_id "\n" \ + REG_ASM " " altlen "\n" \ + ".word " errata_id "\n" + +#define __ALTERNATIVE_CFG(oldinsn, altinsn, vendor_id, errata_id, enable) \ + "886 :\n" \ + oldinsn "\n" \ + ".if " __stringify(enable) " == 1\n" \ + "887 :\n" \ + ".pushsection .alternative, \"a\"\n" \ + ALT_ENTRY("886b", "888f", __stringify(vendor_id), __stringify(errata_id), "889f - 888f") \ + ".popsection\n" \ + ".subsection 1\n" \ + "888 :\n" \ + altinsn "\n" \ + "889 :\n" \ + ".previous\n" \ + ".org . - (887b - 886b) + (889b - 888b)\n" \ + ".org . - (889b - 888b) + (887b - 886b)\n" \ + ".endif\n" + +#define _ALTERNATIVE_CFG(oldinsn, altinsn, vendor_id, errata_id, CONFIG_k) \ + __ALTERNATIVE_CFG(oldinsn, altinsn, vendor_id, errata_id, IS_ENABLED(CONFIG_k)) + +#else /* __ASSEMBLY__ */ + +.macro ALT_ENTRY oldptr altptr vendor_id errata_id alt_len + RISCV_PTR \oldptr + RISCV_PTR \altptr + REG_ASM \vendor_id + REG_ASM \alt_len + .word \errata_id +.endm + +.macro __ALTERNATIVE_CFG insn1 insn2 vendor_id errata_id enable = 1 +886 : + \insn1 + .if \enable +887 : + .pushsection .alternative, "a" + ALT_ENTRY 886b, 888f, \vendor_id, \errata_id, 889f - 888f + .popsection + .subsection 1 +888 : + \insn2 +889 : + .previous + .org . - (889b - 888b) + (887b - 886b) + .org . - (887b - 886b) + (889b - 888b) + .endif +.endm + +#define _ALTERNATIVE_CFG(oldinsn, altinsn, vendor_id, errata_id, CONFIG_k) \ + __ALTERNATIVE_CFG oldinsn, altinsn, vendor_id, errata_id, IS_ENABLED(CONFIG_k) + +#endif /* !__ASSEMBLY__ */ + +#else /* !CONFIG_RISCV_ERRATA_ALTERNATIVE*/ +#ifndef __ASSEMBLY__ + +#define __ALTERNATIVE_CFG(oldinsn) \ + oldinsn "\n" + +#define _ALTERNATIVE_CFG(oldinsn, altinsn, vendor_id, errata_id, CONFIG_k) \ + __ALTERNATIVE_CFG(oldinsn) + +#else /* __ASSEMBLY__ */ + +.macro __ALTERNATIVE_CFG insn1 + \insn1 +.endm + +#define _ALTERNATIVE_CFG(oldinsn, altinsn, vendor_id, errata_id, CONFIG_k) \ + __ALTERNATIVE_CFG oldinsn + +#endif /* !__ASSEMBLY__ */ +#endif /* CONFIG_RISCV_ERRATA_ALTERNATIVE */ + +/* + * Usage: + * ALTERNATIVE(oldinsn, altinsn, vendor_id, errata_id, CONFIG_k) + * in the assembly code. Otherwise, + * asm(ALTERNATIVE(oldinsn, altinsn, vendor_id, errata_id, CONFIG_k)); + * + * oldinsn: The old instruction which will be replaced. + * altinsn: The replacement instruction. + * vendor_id: The CPU vendor ID. + * errata_id: The errata ID. + * CONFIG_k: The Kconfig of this errata. The instructions replacement can + * be disabled by this Kconfig. When Kconfig is disabled, the + * oldinsn will always be executed. + */ +#define ALTERNATIVE(oldinsn, altinsn, vendor_id, errata_id, CONFIG_k) \ + _ALTERNATIVE_CFG(oldinsn, altinsn, vendor_id, errata_id, CONFIG_k) + +#endif diff --git a/arch/riscv/include/asm/alternative.h b/arch/riscv/include/asm/alternative.h new file mode 100644 index 000000000000..98a0ea331a27 --- /dev/null +++ b/arch/riscv/include/asm/alternative.h @@ -0,0 +1,44 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2021 Sifive. + */ + +#ifndef __ASM_ALTERNATIVE_H +#define __ASM_ALTERNATIVE_H + +#define ERRATA_STRING_LENGTH_MAX 32 + +#include + +#ifndef __ASSEMBLY__ + +#include +#include +#include +#include + +void __init apply_boot_alternatives(void); + +struct alt_entry { + void *old_ptr; /* address of original instruciton or data */ + void *alt_ptr; /* address of replacement instruction or data */ + unsigned long vendor_id; /* cpu vendor id */ + unsigned long alt_len; /* The replacement size */ + unsigned int errata_id; /* The errata id */ +} __packed; + +struct errata_checkfunc_id { + unsigned long vendor_id; + bool (*func)(struct alt_entry *alt); +}; + +extern struct cpu_manufacturer_info_t cpu_mfr_info; + +#define REGISTER_ERRATA_CHECKFUNC(checkfunc, vendorid) \ + static const struct errata_checkfunc_id _errata_check_##vendorid \ + __used __section(".alt_checkfunc_table") \ + __aligned(__alignof__(struct errata_checkfunc_id)) = \ + { .vendor_id = vendorid, \ + .func = checkfunc } +#endif +#endif diff --git a/arch/riscv/include/asm/asm.h b/arch/riscv/include/asm/asm.h index 9c992a88d858..618d7c5af1a2 100644 --- a/arch/riscv/include/asm/asm.h +++ b/arch/riscv/include/asm/asm.h @@ -23,6 +23,7 @@ #define REG_L __REG_SEL(ld, lw) #define REG_S __REG_SEL(sd, sw) #define REG_SC __REG_SEL(sc.d, sc.w) +#define REG_ASM __REG_SEL(.dword, .word) #define SZREG __REG_SEL(8, 4) #define LGREG __REG_SEL(3, 2) diff --git a/arch/riscv/include/asm/errata_list.h b/arch/riscv/include/asm/errata_list.h new file mode 100644 index 000000000000..5e5a1fcd90ba --- /dev/null +++ b/arch/riscv/include/asm/errata_list.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2021 Sifive. + */ + +#ifdef CONFIG_SOC_SIFIVE +#define ERRATA_NUMBER 0 +#endif diff --git a/arch/riscv/include/asm/sections.h b/arch/riscv/include/asm/sections.h index 1595c5b60cfd..d13160f46d4e 100644 --- a/arch/riscv/include/asm/sections.h +++ b/arch/riscv/include/asm/sections.h @@ -11,5 +11,7 @@ extern char _start[]; extern char _start_kernel[]; extern char __init_data_begin[], __init_data_end[]; extern char __init_text_begin[], __init_text_end[]; +extern char __alt_checkfunc_table[], __alt_checkfunc_table_end[]; +extern char __alt_start[], __alt_end[]; #endif /* __ASM_SECTIONS_H */ diff --git a/arch/riscv/include/asm/vendorid_list.h b/arch/riscv/include/asm/vendorid_list.h new file mode 100644 index 000000000000..1f3be47decb6 --- /dev/null +++ b/arch/riscv/include/asm/vendorid_list.h @@ -0,0 +1,6 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2021 SiFive + */ + +#define SIFIVE_VENDOR_ID 0x489 diff --git a/arch/riscv/kernel/smpboot.c b/arch/riscv/kernel/smpboot.c index 96167d55ed98..79788d275bbe 100644 --- a/arch/riscv/kernel/smpboot.c +++ b/arch/riscv/kernel/smpboot.c @@ -31,6 +31,7 @@ #include #include #include +#include #include "head.h" @@ -39,6 +40,9 @@ static DECLARE_COMPLETION(cpu_running); void __init smp_prepare_boot_cpu(void) { init_cpu_topology(); +#ifdef CONFIG_RISCV_ERRATA_ALTERNATIVE + apply_boot_alternatives(); +#endif } void __init smp_prepare_cpus(unsigned int max_cpus) diff --git a/arch/riscv/kernel/vmlinux.lds.S b/arch/riscv/kernel/vmlinux.lds.S index de03cb22d0e9..6503dfca65b0 100644 --- a/arch/riscv/kernel/vmlinux.lds.S +++ b/arch/riscv/kernel/vmlinux.lds.S @@ -90,6 +90,20 @@ SECTIONS } __init_data_end = .; + + . = ALIGN(8); + .alt_checkfunc_table : { + __alt_checkfunc_table = .; + *(.alt_checkfunc_table) + __alt_checkfunc_table_end = .; + } + + . = ALIGN(8); + .alternative : { + __alt_start = .; + *(.alternative) + __alt_end = .; + } __init_end = .; /* Start of data section */ From patchwork Tue Mar 16 21:31:09 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dimitri John Ledkov X-Patchwork-Id: 1454507 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.ubuntu.com (client-ip=91.189.94.19; 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Tue, 16 Mar 2021 14:31:42 -0700 (PDT) Received: from localhost ([2a01:4b00:85fd:d700:da2f:147e:3a8a:27aa]) by smtp.gmail.com with ESMTPSA id v9sm23679267wrn.86.2021.03.16.14.31.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Mar 2021 14:31:42 -0700 (PDT) From: Dimitri John Ledkov To: kernel-team@lists.ubuntu.com Subject: [PATCH 07/15] riscv: sifive: apply errata "cip-453" patch Date: Tue, 16 Mar 2021 21:31:09 +0000 Message-Id: <20210316213117.757193-8-xnox@ubuntu.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20210316213117.757193-1-xnox@ubuntu.com> References: <20210316213117.757193-1-xnox@ubuntu.com> MIME-Version: 1.0 X-Mailman-Approved-At: Wed, 17 Mar 2021 06:56:26 +0000 X-BeenThere: kernel-team@lists.ubuntu.com X-Mailman-Version: 2.1.20 Precedence: list List-Id: Kernel team discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: kernel-team-bounces@lists.ubuntu.com Sender: "kernel-team" From: Vincent Chen Add sign extension to the $badaddr before addressing the instruction page fault and instruction access fault to workaround the issue "cip-453". To avoid affecting the existing code sequence, this patch will creates two trampolines to add sign extension to the $badaddr. By the "alternative" mechanism, these two trampolines will replace the original exception handler of instruction page fault and instruction access fault in the excp_vect_table. In this case, only the specific SiFive CPU core jumps to the do_page_fault and do_trap_insn_fault through these two trampolines. Other CPUs are not affected. Signed-off-by: Vincent Chen Signed-off-by: Dimitri John Ledkov --- arch/riscv/Kconfig.erratas | 22 +++++++++ arch/riscv/Kconfig.socs | 1 + arch/riscv/errata/Makefile | 1 + arch/riscv/errata/sifive/Makefile | 2 + arch/riscv/errata/sifive/altern_ops.c | 56 +++++++++++++++++++++++ arch/riscv/errata/sifive/errata_cip_453.S | 34 ++++++++++++++ arch/riscv/include/asm/errata_list.h | 3 +- arch/riscv/kernel/entry.S | 12 ++++- 8 files changed, 128 insertions(+), 3 deletions(-) create mode 100644 arch/riscv/errata/sifive/Makefile create mode 100644 arch/riscv/errata/sifive/altern_ops.c create mode 100644 arch/riscv/errata/sifive/errata_cip_453.S diff --git a/arch/riscv/Kconfig.erratas b/arch/riscv/Kconfig.erratas index 4d0bafc536df..ea36a672064d 100644 --- a/arch/riscv/Kconfig.erratas +++ b/arch/riscv/Kconfig.erratas @@ -9,4 +9,26 @@ config RISCV_ERRATA_ALTERNATIVE code patching is performed once in the boot stages. It means that the overhead from this mechanism is just taken once. +config CPU_SIFIVE + bool "SiFive cores" + help + This enables support for SiFive CPU cores. Currently, It will enable + all the SiFive errata Kconfig. Please say "Y" here if your platform + uses SiFive CPU cores. + + Otherwise, please say "N" here to avoid unnecessary performance + overhead. + +config ERRATA_SIFIVE_CIP_453 + bool "Apply SiFive errata CIP-453" + depends on CPU_SIFIVE + depends on RISCV_ERRATA_ALTERNATIVE + default y + help + This will apply the SiFive CIP-453 errata to add sign extension + to the $badaddr when exception type is instruction page fault + and instruction access fault. + + If you don't know what to do here, say "Y". + endmenu diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs index 3284d5c291be..83630c834e4f 100644 --- a/arch/riscv/Kconfig.socs +++ b/arch/riscv/Kconfig.socs @@ -7,6 +7,7 @@ config SOC_SIFIVE select CLK_SIFIVE select CLK_SIFIVE_PRCI select SIFIVE_PLIC + select CPU_SIFIVE help This enables support for SiFive SoC platform hardware. diff --git a/arch/riscv/errata/Makefile b/arch/riscv/errata/Makefile index 43e6d5424367..a69758bca36a 100644 --- a/arch/riscv/errata/Makefile +++ b/arch/riscv/errata/Makefile @@ -1 +1,2 @@ obj-y += alternative.o +obj-$(CONFIG_CPU_SIFIVE) += sifive/ diff --git a/arch/riscv/errata/sifive/Makefile b/arch/riscv/errata/sifive/Makefile new file mode 100644 index 000000000000..b7f4cd7ee185 --- /dev/null +++ b/arch/riscv/errata/sifive/Makefile @@ -0,0 +1,2 @@ +obj-y += altern_ops.o +obj-y += errata_cip_453.o diff --git a/arch/riscv/errata/sifive/altern_ops.c b/arch/riscv/errata/sifive/altern_ops.c new file mode 100644 index 000000000000..0b0a9af42a55 --- /dev/null +++ b/arch/riscv/errata/sifive/altern_ops.c @@ -0,0 +1,56 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2021 Sifive. + */ + +#include +#include +#include +#include +#include +#include + +#define MAX_ERRATA_IMPID 5 +struct errata_info_t { + char name[ERRATA_STRING_LENGTH_MAX]; + unsigned long arch_id; + unsigned long imp_id[MAX_ERRATA_IMPID]; +} errata_info; + +struct errata_info_t sifive_errata_list[ERRATA_NUMBER] = { + { + .name = "cip-453", + .arch_id = 0x8000000000000007, + .imp_id = { + 0x20181004, 0x00200504 + }, + }, +}; + +static inline bool __init cpu_info_cmp(struct errata_info_t *errata, struct alt_entry *alt) +{ + int i; + + if (errata->arch_id != cpu_mfr_info.arch_id) + return false; + + for (i = 0; i < MAX_ERRATA_IMPID && errata->imp_id[i]; i++) + if (errata->imp_id[i] == cpu_mfr_info.imp_id) + return true; + + return false; +} + +static bool __init sifive_errata_check(struct alt_entry *alt) +{ + if (cpu_mfr_info.vendor_id != alt->vendor_id) + return false; + + if (likely(alt->errata_id < ERRATA_NUMBER)) + return cpu_info_cmp(&sifive_errata_list[alt->errata_id], alt); + + WARN_ON(1); + return false; +} + +REGISTER_ERRATA_CHECKFUNC(sifive_errata_check, SIFIVE_VENDOR_ID); diff --git a/arch/riscv/errata/sifive/errata_cip_453.S b/arch/riscv/errata/sifive/errata_cip_453.S new file mode 100644 index 000000000000..34d0fe26172e --- /dev/null +++ b/arch/riscv/errata/sifive/errata_cip_453.S @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2021 SiFive + */ + +#include +#include +#include +#include + +.macro ADD_SIGN_EXT pt_reg badaddr tmp_reg + REG_L \badaddr, PT_BADADDR(\pt_reg) + li \tmp_reg,1 + slli \tmp_reg,\tmp_reg,0x26 + and \tmp_reg,\tmp_reg,\badaddr + beqz \tmp_reg, 1f + li \tmp_reg,-1 + slli \tmp_reg,\tmp_reg,0x27 + or \badaddr,\tmp_reg,\badaddr + REG_S \badaddr, PT_BADADDR(\pt_reg) +1: +.endm + +ENTRY(do_page_fault_trampoline) + ADD_SIGN_EXT a0, t0, t1 + la t0, do_page_fault + jr t0 +END(do_page_fault_trampoline) + +ENTRY(do_trap_insn_fault_trampoline) + ADD_SIGN_EXT a0, t0, t1 + la t0, do_trap_insn_fault + jr t0 +END(do_trap_insn_fault_trampoline) diff --git a/arch/riscv/include/asm/errata_list.h b/arch/riscv/include/asm/errata_list.h index 5e5a1fcd90ba..d3752c8eff1f 100644 --- a/arch/riscv/include/asm/errata_list.h +++ b/arch/riscv/include/asm/errata_list.h @@ -4,5 +4,6 @@ */ #ifdef CONFIG_SOC_SIFIVE -#define ERRATA_NUMBER 0 +#define ERRATA_CIP_453 0 +#define ERRATA_NUMBER 1 #endif diff --git a/arch/riscv/kernel/entry.S b/arch/riscv/kernel/entry.S index 744f3209c48d..821e86ee67e4 100644 --- a/arch/riscv/kernel/entry.S +++ b/arch/riscv/kernel/entry.S @@ -12,6 +12,9 @@ #include #include #include +#include +#include +#include #if !IS_ENABLED(CONFIG_PREEMPTION) .set resume_kernel, restore_all @@ -450,7 +453,9 @@ ENDPROC(__switch_to) /* Exception vector table */ ENTRY(excp_vect_table) RISCV_PTR do_trap_insn_misaligned - RISCV_PTR do_trap_insn_fault + ALTERNATIVE(__stringify(RISCV_PTR do_trap_insn_fault), + __stringify(RISCV_PTR do_trap_insn_fault_trampoline), + SIFIVE_VENDOR_ID, ERRATA_CIP_453, CONFIG_ERRATA_SIFIVE_CIP_453) RISCV_PTR do_trap_insn_illegal RISCV_PTR do_trap_break RISCV_PTR do_trap_load_misaligned @@ -461,7 +466,10 @@ ENTRY(excp_vect_table) RISCV_PTR do_trap_ecall_s RISCV_PTR do_trap_unknown RISCV_PTR do_trap_ecall_m - RISCV_PTR do_page_fault /* instruction page fault */ + /* instruciton page fault */ + ALTERNATIVE(__stringify(RISCV_PTR do_page_fault), + __stringify(RISCV_PTR do_page_fault_trampoline), + SIFIVE_VENDOR_ID, ERRATA_CIP_453, CONFIG_ERRATA_SIFIVE_CIP_453) RISCV_PTR do_page_fault /* load page fault */ RISCV_PTR do_trap_unknown RISCV_PTR do_page_fault /* store page fault */ From patchwork Tue Mar 16 21:31:10 2021 Content-Type: text/plain; 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Signed-off-by: Greentime Hu Signed-off-by: Dimitri John Ledkov --- drivers/clk/sifive/fu740-prci.c | 11 +++++ drivers/clk/sifive/fu740-prci.h | 2 +- drivers/clk/sifive/sifive-prci.c | 41 +++++++++++++++++++ drivers/clk/sifive/sifive-prci.h | 9 ++++ include/dt-bindings/clock/sifive-fu740-prci.h | 1 + 5 files changed, 63 insertions(+), 1 deletion(-) diff --git a/drivers/clk/sifive/fu740-prci.c b/drivers/clk/sifive/fu740-prci.c index 764d1097aa51..53f6e00a03b9 100644 --- a/drivers/clk/sifive/fu740-prci.c +++ b/drivers/clk/sifive/fu740-prci.c @@ -72,6 +72,12 @@ static const struct clk_ops sifive_fu740_prci_hfpclkplldiv_clk_ops = { .recalc_rate = sifive_prci_hfpclkplldiv_recalc_rate, }; +static const struct clk_ops sifive_fu740_prci_pcie_aux_clk_ops = { + .enable = sifive_prci_pcie_aux_clock_enable, + .disable = sifive_prci_pcie_aux_clock_disable, + .is_enabled = sifive_prci_pcie_aux_clock_is_enabled, +}; + /* List of clock controls provided by the PRCI */ struct __prci_clock __prci_init_clocks_fu740[] = { [PRCI_CLK_COREPLL] = { @@ -120,4 +126,9 @@ struct __prci_clock __prci_init_clocks_fu740[] = { .parent_name = "hfpclkpll", .ops = &sifive_fu740_prci_hfpclkplldiv_clk_ops, }, + [PRCI_CLK_PCIE_AUX] = { + .name = "pcie_aux", + .parent_name = "hfclk", + .ops = &sifive_fu740_prci_pcie_aux_clk_ops, + }, }; diff --git a/drivers/clk/sifive/fu740-prci.h b/drivers/clk/sifive/fu740-prci.h index 13ef971f7764..511a0bf7ba2b 100644 --- a/drivers/clk/sifive/fu740-prci.h +++ b/drivers/clk/sifive/fu740-prci.h @@ -9,7 +9,7 @@ #include "sifive-prci.h" -#define NUM_CLOCK_FU740 8 +#define NUM_CLOCK_FU740 9 extern struct __prci_clock __prci_init_clocks_fu740[NUM_CLOCK_FU740]; diff --git a/drivers/clk/sifive/sifive-prci.c b/drivers/clk/sifive/sifive-prci.c index c78b042750e2..baf7313dac92 100644 --- a/drivers/clk/sifive/sifive-prci.c +++ b/drivers/clk/sifive/sifive-prci.c @@ -448,6 +448,47 @@ void sifive_prci_hfpclkpllsel_use_hfpclkpll(struct __prci_data *pd) r = __prci_readl(pd, PRCI_HFPCLKPLLSEL_OFFSET); /* barrier */ } +/* PCIE AUX clock APIs for enable, disable. */ +int sifive_prci_pcie_aux_clock_is_enabled(struct clk_hw *hw) +{ + struct __prci_clock *pc = clk_hw_to_prci_clock(hw); + struct __prci_data *pd = pc->pd; + u32 r; + + r = __prci_readl(pd, PRCI_PCIE_AUX_OFFSET); + + if (r & PRCI_PCIE_AUX_EN_MASK) + return 1; + else + return 0; +} + +int sifive_prci_pcie_aux_clock_enable(struct clk_hw *hw) +{ + struct __prci_clock *pc = clk_hw_to_prci_clock(hw); + struct __prci_data *pd = pc->pd; + u32 r; + + if (sifive_prci_pcie_aux_clock_is_enabled(hw)) + return 0; + + __prci_writel(1, PRCI_PCIE_AUX_OFFSET, pd); + r = __prci_readl(pd, PRCI_PCIE_AUX_OFFSET); /* barrier */ + + return 0; +} + +void sifive_prci_pcie_aux_clock_disable(struct clk_hw *hw) +{ + struct __prci_clock *pc = clk_hw_to_prci_clock(hw); + struct __prci_data *pd = pc->pd; + u32 r; + + __prci_writel(0, PRCI_PCIE_AUX_OFFSET, pd); + r = __prci_readl(pd, PRCI_PCIE_AUX_OFFSET); /* barrier */ + +} + /** * __prci_register_clocks() - register clock controls in the PRCI * @dev: Linux struct device diff --git a/drivers/clk/sifive/sifive-prci.h b/drivers/clk/sifive/sifive-prci.h index dbdbd1722688..022c67cf053c 100644 --- a/drivers/clk/sifive/sifive-prci.h +++ b/drivers/clk/sifive/sifive-prci.h @@ -67,6 +67,11 @@ #define PRCI_DDRPLLCFG1_CKE_SHIFT 31 #define PRCI_DDRPLLCFG1_CKE_MASK (0x1 << PRCI_DDRPLLCFG1_CKE_SHIFT) +/* PCIEAUX */ +#define PRCI_PCIE_AUX_OFFSET 0x14 +#define PRCI_PCIE_AUX_EN_SHIFT 0 +#define PRCI_PCIE_AUX_EN_MASK (0x1 << PRCI_PCIE_AUX_EN_SHIFT) + /* GEMGXLPLLCFG0 */ #define PRCI_GEMGXLPLLCFG0_OFFSET 0x1c #define PRCI_GEMGXLPLLCFG0_DIVR_SHIFT 0 @@ -296,4 +301,8 @@ unsigned long sifive_prci_tlclksel_recalc_rate(struct clk_hw *hw, unsigned long sifive_prci_hfpclkplldiv_recalc_rate(struct clk_hw *hw, unsigned long parent_rate); +int sifive_prci_pcie_aux_clock_is_enabled(struct clk_hw *hw); +int sifive_prci_pcie_aux_clock_enable(struct clk_hw *hw); +void sifive_prci_pcie_aux_clock_disable(struct clk_hw *hw); + #endif /* __SIFIVE_CLK_SIFIVE_PRCI_H */ diff --git a/include/dt-bindings/clock/sifive-fu740-prci.h b/include/dt-bindings/clock/sifive-fu740-prci.h index cd7706ea5677..7899b7fee7db 100644 --- a/include/dt-bindings/clock/sifive-fu740-prci.h +++ b/include/dt-bindings/clock/sifive-fu740-prci.h @@ -19,5 +19,6 @@ #define PRCI_CLK_CLTXPLL 5 #define PRCI_CLK_TLCLK 6 #define PRCI_CLK_PCLK 7 +#define PRCI_CLK_PCIE_AUX 8 #endif /* __DT_BINDINGS_CLOCK_SIFIVE_FU740_PRCI_H */ From patchwork Tue Mar 16 21:31:11 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dimitri John Ledkov X-Patchwork-Id: 1454508 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.ubuntu.com (client-ip=91.189.94.19; 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Tue, 16 Mar 2021 14:31:45 -0700 (PDT) Received: from localhost ([2a01:4b00:85fd:d700:da2f:147e:3a8a:27aa]) by smtp.gmail.com with ESMTPSA id c2sm531906wmr.22.2021.03.16.14.31.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Mar 2021 14:31:45 -0700 (PDT) From: Dimitri John Ledkov To: kernel-team@lists.ubuntu.com Subject: [PATCH 09/15] clk: sifive: Use reset-simple in prci driver for PCIe driver Date: Tue, 16 Mar 2021 21:31:11 +0000 Message-Id: <20210316213117.757193-10-xnox@ubuntu.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20210316213117.757193-1-xnox@ubuntu.com> References: <20210316213117.757193-1-xnox@ubuntu.com> MIME-Version: 1.0 X-Mailman-Approved-At: Wed, 17 Mar 2021 06:56:26 +0000 X-BeenThere: kernel-team@lists.ubuntu.com X-Mailman-Version: 2.1.20 Precedence: list List-Id: Kernel team discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: kernel-team-bounces@lists.ubuntu.com Sender: "kernel-team" From: Greentime Hu We use reset-simple in this patch so that pcie driver can use devm_reset_control_get() to get this reset data structure and use reset_control_deassert() to deassert pcie_power_up_rst_n. Signed-off-by: Greentime Hu Signed-off-by: Dimitri John Ledkov --- drivers/clk/sifive/Kconfig | 2 ++ drivers/clk/sifive/sifive-prci.c | 14 ++++++++++++++ drivers/clk/sifive/sifive-prci.h | 4 ++++ drivers/reset/Kconfig | 3 ++- 4 files changed, 22 insertions(+), 1 deletion(-) diff --git a/drivers/clk/sifive/Kconfig b/drivers/clk/sifive/Kconfig index 1c14eb20c066..9132c3c4aa86 100644 --- a/drivers/clk/sifive/Kconfig +++ b/drivers/clk/sifive/Kconfig @@ -10,6 +10,8 @@ if CLK_SIFIVE config CLK_SIFIVE_PRCI bool "PRCI driver for SiFive SoCs" + select RESET_CONTROLLER + select RESET_SIMPLE select CLK_ANALOGBITS_WRPLL_CLN28HPC help Supports the Power Reset Clock interface (PRCI) IP block found in diff --git a/drivers/clk/sifive/sifive-prci.c b/drivers/clk/sifive/sifive-prci.c index baf7313dac92..925affc6de55 100644 --- a/drivers/clk/sifive/sifive-prci.c +++ b/drivers/clk/sifive/sifive-prci.c @@ -583,7 +583,21 @@ static int sifive_prci_probe(struct platform_device *pdev) if (IS_ERR(pd->va)) return PTR_ERR(pd->va); + pd->reset.rcdev.owner = THIS_MODULE; + pd->reset.rcdev.nr_resets = PRCI_RST_NR; + pd->reset.rcdev.ops = &reset_simple_ops; + pd->reset.rcdev.of_node = pdev->dev.of_node; + pd->reset.active_low = true; + pd->reset.membase = pd->va + PRCI_DEVICESRESETREG_OFFSET; + spin_lock_init(&pd->reset.lock); + + r = devm_reset_controller_register(&pdev->dev, &pd->reset.rcdev); + if (r) { + dev_err(dev, "could not register reset controller: %d\n", r); + return r; + } r = __prci_register_clocks(dev, pd, desc); + if (r) { dev_err(dev, "could not register clocks: %d\n", r); return r; diff --git a/drivers/clk/sifive/sifive-prci.h b/drivers/clk/sifive/sifive-prci.h index 022c67cf053c..91658a88af4e 100644 --- a/drivers/clk/sifive/sifive-prci.h +++ b/drivers/clk/sifive/sifive-prci.h @@ -11,6 +11,7 @@ #include #include +#include #include /* @@ -121,6 +122,8 @@ #define PRCI_DEVICESRESETREG_CHIPLINK_RST_N_MASK \ (0x1 << PRCI_DEVICESRESETREG_CHIPLINK_RST_N_SHIFT) +#define PRCI_RST_NR 7 + /* CLKMUXSTATUSREG */ #define PRCI_CLKMUXSTATUSREG_OFFSET 0x2c #define PRCI_CLKMUXSTATUSREG_TLCLKSEL_STATUS_SHIFT 1 @@ -221,6 +224,7 @@ */ struct __prci_data { void __iomem *va; + struct reset_simple_data reset; struct clk_hw_onecell_data hw_clks; }; diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig index 71ab75a46491..f094df93d911 100644 --- a/drivers/reset/Kconfig +++ b/drivers/reset/Kconfig @@ -173,7 +173,7 @@ config RESET_SCMI config RESET_SIMPLE bool "Simple Reset Controller Driver" if COMPILE_TEST - default ARCH_AGILEX || ARCH_ASPEED || ARCH_BITMAIN || ARCH_REALTEK || ARCH_STM32 || ARCH_STRATIX10 || ARCH_SUNXI || ARCH_ZX || ARC + default ARCH_AGILEX || ARCH_ASPEED || ARCH_BITMAIN || ARCH_REALTEK || ARCH_STM32 || ARCH_STRATIX10 || ARCH_SUNXI || ARCH_ZX || ARC || RISCV help This enables a simple reset controller driver for reset lines that that can be asserted and deasserted by toggling bits in a contiguous, @@ -187,6 +187,7 @@ config RESET_SIMPLE - RCC reset controller in STM32 MCUs - Allwinner SoCs - ZTE's zx2967 family + - SiFive FU740 SoCs config RESET_STM32MP157 bool "STM32MP157 Reset Driver" if COMPILE_TEST From patchwork Tue Mar 16 21:31:12 2021 Content-Type: text/plain; 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Signed-off-by: Greentime Hu Signed-off-by: Dimitri John Ledkov --- MAINTAINERS | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index cf773a562433..6bc519da58d5 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -13605,6 +13605,14 @@ S: Maintained F: Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt F: drivers/pci/controller/dwc/*imx6* +PCI DRIVER FOR FU740 +M: Paul Walmsley +M: Greentime Hu +L: linux-pci@vger.kernel.org +S: Maintained +F: Documentation/devicetree/bindings/pci/sifive,fu740-pcie.yaml +F: drivers/pci/controller/dwc/pcie-fu740.c + PCI DRIVER FOR INTEL VOLUME MANAGEMENT DEVICE (VMD) M: Jonathan Derrick L: linux-pci@vger.kernel.org From patchwork Tue Mar 16 21:31:13 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dimitri John Ledkov X-Patchwork-Id: 1454498 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.ubuntu.com (client-ip=91.189.94.19; helo=huckleberry.canonical.com; envelope-from=kernel-team-bounces@lists.ubuntu.com; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; secure) header.d=surgut.co.uk header.i=@surgut.co.uk header.a=rsa-sha256 header.s=google header.b=U/GTjwDp; dkim-atps=neutral Received: from huckleberry.canonical.com (huckleberry.canonical.com [91.189.94.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4F0gtb6Xgqz9ssD; Wed, 17 Mar 2021 17:56:39 +1100 (AEDT) Received: from localhost ([127.0.0.1] helo=huckleberry.canonical.com) by huckleberry.canonical.com with esmtp (Exim 4.86_2) (envelope-from ) id 1lMQ6W-0000Sh-3R; Wed, 17 Mar 2021 06:56:28 +0000 Received: from mail-wm1-f49.google.com ([209.85.128.49]) by huckleberry.canonical.com with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.86_2) (envelope-from ) id 1lMHI4-0005oC-G8 for kernel-team@lists.ubuntu.com; Tue, 16 Mar 2021 21:31:48 +0000 Received: by mail-wm1-f49.google.com with SMTP id u5-20020a7bcb050000b029010e9316b9d5so175786wmj.2 for ; Tue, 16 Mar 2021 14:31:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=surgut.co.uk; s=google; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=+p0+ro11fM4mGqUffVI4C4eJWhpuxVLfMgohBXSV4As=; b=U/GTjwDpEB1M88QtFZ6MU4UmGeS9Gp0Y4/aw+wYEhtVpHcZMIOUmJwZhlpgo2cCh5k f3U2uTkVs8oAuVXCxmoY/HRmdoI5/UkfX3EWz64F6lKp52C44VZpm4E3EihwGqmdCAJt 4bFQeEgIJgrzaqXTHLXg+srmfWRi7NbB/od4A= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=+p0+ro11fM4mGqUffVI4C4eJWhpuxVLfMgohBXSV4As=; b=LItl1vL20ZuVz0+H6uLU9t0WAxedkjxYAU6DgeZ22HI6lvTmjU/XxdPss7/XM6PhSI cAlRBckJcNgfKMr08znwk1D1OwQisxW+0dUPpZM35yAwCXVrs20g+rSUdD/U1iE4hb2G H0O+rVh04szBHTLrnbwOxUTVe0tP0Kq38xuKYG50tZJ2Txw2XzAsQzaNXTp2DtF9lJD6 UjRc1rARJ1LfXD1uEZ7kIlHHRAp0kGJeulr9T3k7YhQ81vQIDFCYh/iNZKhWAsci995O S3nS+F148VgnhAb8CL/Adov/EdC/yqW8Cyv+gMjkELOIQ2DvD+IZV0WqgAIHgMlsv4HG nImQ== X-Gm-Message-State: AOAM5325wSAwdYk77gb2qbYJUT5MB3QsNdm4SSBYoDayiaCsechO8q2y 4QOlzPWQHmnXNJzo9NjHdoCczANnK1jgzQ== X-Google-Smtp-Source: ABdhPJwbXEdqx8IsStQuuDXYXG5fWNQ5bWcUoKcUVENwn4Q6Aj+9cHxQXJTquI+/QzazxO0C4W/Xkw== X-Received: by 2002:a1c:7916:: with SMTP id l22mr708363wme.86.1615930307777; Tue, 16 Mar 2021 14:31:47 -0700 (PDT) Received: from localhost ([2a01:4b00:85fd:d700:da2f:147e:3a8a:27aa]) by smtp.gmail.com with ESMTPSA id m132sm492178wmf.45.2021.03.16.14.31.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Mar 2021 14:31:47 -0700 (PDT) From: Dimitri John Ledkov To: kernel-team@lists.ubuntu.com Subject: [PATCH 11/15] dt-bindings: PCI: Add SiFive FU740 PCIe host controller Date: Tue, 16 Mar 2021 21:31:13 +0000 Message-Id: <20210316213117.757193-12-xnox@ubuntu.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20210316213117.757193-1-xnox@ubuntu.com> References: <20210316213117.757193-1-xnox@ubuntu.com> MIME-Version: 1.0 X-Mailman-Approved-At: Wed, 17 Mar 2021 06:56:26 +0000 X-BeenThere: kernel-team@lists.ubuntu.com X-Mailman-Version: 2.1.20 Precedence: list List-Id: Kernel team discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: kernel-team-bounces@lists.ubuntu.com Sender: "kernel-team" From: Greentime Hu Add PCIe host controller DT bindings of SiFive FU740. Signed-off-by: Greentime Hu Signed-off-by: Dimitri John Ledkov --- .../bindings/pci/sifive,fu740-pcie.yaml | 119 ++++++++++++++++++ 1 file changed, 119 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/sifive,fu740-pcie.yaml diff --git a/Documentation/devicetree/bindings/pci/sifive,fu740-pcie.yaml b/Documentation/devicetree/bindings/pci/sifive,fu740-pcie.yaml new file mode 100644 index 000000000000..879ab4f80456 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/sifive,fu740-pcie.yaml @@ -0,0 +1,119 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/sifive,fu740-pcie.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: SiFive fu740 PCIe host controller + +description: | + SiFive fu740 PCIe host controller is based on the Synopsys DesignWare + PCI core. It shares common features with the PCIe DesignWare core and + inherits common properties defined in + Documentation/devicetree/bindings/pci/designware-pcie.txt. + +maintainers: + - Paul Walmsley + - Greentime Hu + +allOf: + - $ref: /schemas/pci/pci-bus.yaml# + +properties: + compatible: + const: sifive,fu740-pcie + + reg: + maxItems: 4 + + reg-names: + items: + - const: dbi + - const: config + - const: mgmt + + device_type: + const: pci + + dma-coherent: + description: Indicates that the PCIe IP block can ensure the coherency + + bus-range: + description: Range of bus numbers associated with this controller. + + num-lanes: true + + msi-parent: true + + interrupt-names: + items: + - const: msi + - const: inta + - const: intb + - const: intc + - const: intd + + resets: + description: A phandle to the PCIe power up reset line + + pwren-gpios: + description: Should specify the GPIO for controlling the PCI bus device power on + + perstn-gpios: + description: Should specify the GPIO for controlling the PCI bus device reset + +required: + - compatible + - reg + - reg-names + - device_type + - dma-coherent + - bus-range + - ranges + - num-lanes + - interrupts + - interrupt-names + - interrupt-parent + - interrupt-map-mask + - interrupt-map + - clock-names + - clocks + - resets + - pwren-gpios + - perstn-gpios + +additionalProperties: false + +examples: + - | + pcie@e00000000 { + #address-cells = <3>; + #interrupt-cells = <1>; + #size-cells = <2>; + compatible = "sifive,fu740-pcie"; + reg = <0xe 0x00000000 0x1 0x0 + 0xd 0xf0000000 0x0 0x10000000 + 0x0 0x100d0000 0x0 0x1000>; + reg-names = "dbi", "config", "mgmt"; + device_type = "pci"; + dma-coherent; + bus-range = <0x0 0xff>; + ranges = <0x81000000 0x0 0x60080000 0x0 0x60080000 0x0 0x10000 /* I/O */ + 0x82000000 0x0 0x60090000 0x0 0x60090000 0x0 0xff70000 /* mem */ + 0x82000000 0x0 0x70000000 0x0 0x70000000 0x0 0x1000000 /* mem */ + 0xc3000000 0x20 0x00000000 0x20 0x00000000 0x20 0x00000000>; /* mem prefetchable */ + num-lanes = <0x8>; + interrupts = <56 57 58 59 60 61 62 63 64>; + interrupt-names = "msi", "inta", "intb", "intc", "intd"; + interrupt-parent = <&plic0>; + interrupt-map-mask = <0x0 0x0 0x0 0x7>; + interrupt-map = <0x0 0x0 0x0 0x1 &plic0 57>, + <0x0 0x0 0x0 0x2 &plic0 58>, + <0x0 0x0 0x0 0x3 &plic0 59>, + <0x0 0x0 0x0 0x4 &plic0 60>; + clock-names = "pcie_aux"; + clocks = <&prci PRCI_CLK_PCIE_AUX>; + resets = <&prci 4>; + pwren-gpios = <&gpio 5 0>; + perstn-gpios = <&gpio 8 0>; + }; From patchwork Tue Mar 16 21:31:14 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dimitri John Ledkov X-Patchwork-Id: 1454503 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.ubuntu.com (client-ip=91.189.94.19; helo=huckleberry.canonical.com; envelope-from=kernel-team-bounces@lists.ubuntu.com; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; secure) header.d=surgut.co.uk header.i=@surgut.co.uk header.a=rsa-sha256 header.s=google header.b=TrxHNbdb; dkim-atps=neutral Received: from huckleberry.canonical.com (huckleberry.canonical.com [91.189.94.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4F0gtb6W54z9srZ; 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Tue, 16 Mar 2021 14:31:48 -0700 (PDT) From: Dimitri John Ledkov To: kernel-team@lists.ubuntu.com Subject: [PATCH 12/15] PCI: designware: Add SiFive FU740 PCIe host controller driver Date: Tue, 16 Mar 2021 21:31:14 +0000 Message-Id: <20210316213117.757193-13-xnox@ubuntu.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20210316213117.757193-1-xnox@ubuntu.com> References: <20210316213117.757193-1-xnox@ubuntu.com> MIME-Version: 1.0 X-Mailman-Approved-At: Wed, 17 Mar 2021 06:56:26 +0000 X-BeenThere: kernel-team@lists.ubuntu.com X-Mailman-Version: 2.1.20 Precedence: list List-Id: Kernel team discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: kernel-team-bounces@lists.ubuntu.com Sender: "kernel-team" From: Paul Walmsley Add driver for the SiFive FU740 PCIe host controller. This controller is based on the DesignWare PCIe core. Co-developed-by: Henry Styles Signed-off-by: Henry Styles Co-developed-by: Erik Danie Signed-off-by: Erik Danie Co-developed-by: Greentime Hu Signed-off-by: Greentime Hu Signed-off-by: Paul Walmsley Signed-off-by: Dimitri John Ledkov --- drivers/pci/controller/dwc/Kconfig | 9 + drivers/pci/controller/dwc/Makefile | 1 + drivers/pci/controller/dwc/pcie-fu740.c | 455 ++++++++++++++++++++++++ 3 files changed, 465 insertions(+) create mode 100644 drivers/pci/controller/dwc/pcie-fu740.c diff --git a/drivers/pci/controller/dwc/Kconfig b/drivers/pci/controller/dwc/Kconfig index 22c5529e9a65..0a37d21ed64e 100644 --- a/drivers/pci/controller/dwc/Kconfig +++ b/drivers/pci/controller/dwc/Kconfig @@ -318,4 +318,13 @@ config PCIE_AL required only for DT-based platforms. ACPI platforms with the Annapurna Labs PCIe controller don't need to enable this. +config PCIE_FU740 + bool "SiFive FU740 PCIe host controller" + depends on PCI_MSI_IRQ_DOMAIN + depends on SOC_SIFIVE || COMPILE_TEST + select PCIE_DW_HOST + help + Say Y here if you want PCIe controller support for the SiFive + FU740. + endmenu diff --git a/drivers/pci/controller/dwc/Makefile b/drivers/pci/controller/dwc/Makefile index a751553fa0db..625f6aaeb5b8 100644 --- a/drivers/pci/controller/dwc/Makefile +++ b/drivers/pci/controller/dwc/Makefile @@ -5,6 +5,7 @@ obj-$(CONFIG_PCIE_DW_EP) += pcie-designware-ep.o obj-$(CONFIG_PCIE_DW_PLAT) += pcie-designware-plat.o obj-$(CONFIG_PCI_DRA7XX) += pci-dra7xx.o obj-$(CONFIG_PCI_EXYNOS) += pci-exynos.o +obj-$(CONFIG_PCIE_FU740) += pcie-fu740.o obj-$(CONFIG_PCI_IMX6) += pci-imx6.o obj-$(CONFIG_PCIE_SPEAR13XX) += pcie-spear13xx.o obj-$(CONFIG_PCI_KEYSTONE) += pci-keystone.o diff --git a/drivers/pci/controller/dwc/pcie-fu740.c b/drivers/pci/controller/dwc/pcie-fu740.c new file mode 100644 index 000000000000..6916eea40ea5 --- /dev/null +++ b/drivers/pci/controller/dwc/pcie-fu740.c @@ -0,0 +1,455 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * FU740 DesignWare PCIe Controller integration + * Copyright (C) 2019-2021 SiFive, Inc. + * Paul Walmsley + * Greentime Hu + * + * Based in part on the i.MX6 PCIe host controller shim which is: + * + * Copyright (C) 2013 Kosagi + * https://www.kosagi.com + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "pcie-designware.h" + +#define to_fu740_pcie(x) dev_get_drvdata((x)->dev) + +struct fu740_pcie { + struct dw_pcie *pci; + void __iomem *mgmt_base; + int perstn_gpio; + int pwren_gpio; + struct clk *pcie_aux; + struct reset_control *rst; +}; + +#define SIFIVE_DEVICESRESETREG 0x28 + +#define PCIEX8MGMT_PERST_N 0x0 +#define PCIEX8MGMT_APP_LTSSM_ENABLE 0x10 +#define PCIEX8MGMT_APP_HOLD_PHY_RST 0x18 +#define PCIEX8MGMT_DEVICE_TYPE 0x708 +#define PCIEX8MGMT_PHY0_CR_PARA_ADDR 0x860 +#define PCIEX8MGMT_PHY0_CR_PARA_RD_EN 0x870 +#define PCIEX8MGMT_PHY0_CR_PARA_RD_DATA 0x878 +#define PCIEX8MGMT_PHY0_CR_PARA_SEL 0x880 +#define PCIEX8MGMT_PHY0_CR_PARA_WR_DATA 0x888 +#define PCIEX8MGMT_PHY0_CR_PARA_WR_EN 0x890 +#define PCIEX8MGMT_PHY0_CR_PARA_ACK 0x898 +#define PCIEX8MGMT_PHY1_CR_PARA_ADDR 0x8a0 +#define PCIEX8MGMT_PHY1_CR_PARA_RD_EN 0x8b0 +#define PCIEX8MGMT_PHY1_CR_PARA_RD_DATA 0x8b8 +#define PCIEX8MGMT_PHY1_CR_PARA_SEL 0x8c0 +#define PCIEX8MGMT_PHY1_CR_PARA_WR_DATA 0x8c8 +#define PCIEX8MGMT_PHY1_CR_PARA_WR_EN 0x8d0 +#define PCIEX8MGMT_PHY1_CR_PARA_ACK 0x8d8 + +/* PCIe Port Logic registers (memory-mapped) */ +#define PL_OFFSET 0x700 +#define PCIE_PL_GEN2_CTRL_OFF (PL_OFFSET + 0x10c) +#define PCIE_PL_DIRECTED_SPEED_CHANGE_OFF 0x20000 + +#define PCIE_PHY_MAX_RETRY_CNT 1000 + +static void fu740_pcie_assert_perstn(struct fu740_pcie *afp) +{ + /* PERST_N GPIO */ + if (gpio_is_valid(afp->perstn_gpio)) + gpio_direction_output(afp->perstn_gpio, 0); + + /* Controller PERST_N */ + __raw_writel(0x0, afp->mgmt_base + PCIEX8MGMT_PERST_N); +} + +static void fu740_pcie_deassert_perstn(struct fu740_pcie *afp) +{ + /* Controller PERST_N */ + __raw_writel(0x1, afp->mgmt_base + PCIEX8MGMT_PERST_N); + /* PERST_N GPIO */ + if (gpio_is_valid(afp->perstn_gpio)) + gpio_direction_output(afp->perstn_gpio, 1); +} + +static void fu740_pcie_power_on(struct fu740_pcie *afp) +{ + if (gpio_is_valid(afp->pwren_gpio)) { + gpio_direction_output(afp->pwren_gpio, 1); + mdelay(100); + } +} + +static void fu740_pcie_drive_perstn(struct fu740_pcie *afp) +{ + fu740_pcie_assert_perstn(afp); + fu740_pcie_power_on(afp); + fu740_pcie_deassert_perstn(afp); +} + +static void fu740_phyregreadwrite(const uint8_t phy, const uint8_t write, + const uint16_t addr, + const uint16_t wrdata, uint16_t *rddata, + struct fu740_pcie *afp) +{ + unsigned char ack = 0; + unsigned int cnt = 0; + struct device *dev = afp->pci->dev; + + /* setup */ + __raw_writel(addr, + afp->mgmt_base + + (phy ? PCIEX8MGMT_PHY1_CR_PARA_ADDR : + PCIEX8MGMT_PHY0_CR_PARA_ADDR)); + if (write) + __raw_writel(wrdata, + afp->mgmt_base + + (phy ? PCIEX8MGMT_PHY1_CR_PARA_WR_DATA : + PCIEX8MGMT_PHY0_CR_PARA_WR_DATA)); + if (write) + __raw_writel(1, + afp->mgmt_base + + (phy ? PCIEX8MGMT_PHY1_CR_PARA_WR_EN : + PCIEX8MGMT_PHY0_CR_PARA_WR_EN)); + else + __raw_writel(1, + afp->mgmt_base + + (phy ? PCIEX8MGMT_PHY1_CR_PARA_RD_EN : + PCIEX8MGMT_PHY0_CR_PARA_RD_EN)); + + /* wait for wait_idle */ + do { + if (__raw_readl + (afp->mgmt_base + + (phy ? PCIEX8MGMT_PHY1_CR_PARA_ACK : + PCIEX8MGMT_PHY0_CR_PARA_ACK))) { + ack = 1; + if (!write) + __raw_readl(afp->mgmt_base + + (phy ? + PCIEX8MGMT_PHY1_CR_PARA_RD_DATA : + PCIEX8MGMT_PHY0_CR_PARA_RD_DATA)); + } + } while (!ack); + + /* clear */ + if (write) + __raw_writel(0, + afp->mgmt_base + + (phy ? PCIEX8MGMT_PHY1_CR_PARA_WR_EN : + PCIEX8MGMT_PHY0_CR_PARA_WR_EN)); + else + __raw_writel(0, + afp->mgmt_base + + (phy ? PCIEX8MGMT_PHY1_CR_PARA_RD_EN : + PCIEX8MGMT_PHY0_CR_PARA_RD_EN)); + + /* wait for ~wait_idle */ + while (__raw_readl + (afp->mgmt_base + + (phy ? PCIEX8MGMT_PHY1_CR_PARA_ACK : + PCIEX8MGMT_PHY0_CR_PARA_ACK))) { + cpu_relax(); + cnt++; + if (cnt > PCIE_PHY_MAX_RETRY_CNT) { + dev_err(dev, "PCIE phy doesn't enter idle state.\n"); + break; + } + } +} + +static void fu740_pcie_init_phy(struct fu740_pcie *afp) +{ + int lane; + + /* enable phy cr_para_sel interfaces */ + __raw_writel(0x1, afp->mgmt_base + PCIEX8MGMT_PHY0_CR_PARA_SEL); + __raw_writel(0x1, afp->mgmt_base + PCIEX8MGMT_PHY1_CR_PARA_SEL); + + /* wait 10 cr_para cycles */ + msleep(1); + + /* set PHY AC termination mode */ + for (lane = 0; lane < 4; lane++) { + fu740_phyregreadwrite(0, 1, + 0x1008 + (0x100 * lane), + 0x0e21, NULL, afp); + fu740_phyregreadwrite(1, 1, + 0x1008 + (0x100 * lane), + 0x0e21, NULL, afp); + } + +} + +static void fu740_pcie_ltssm_enable(struct device *dev) +{ + struct fu740_pcie *afp = dev_get_drvdata(dev); + + /* Enable LTSSM */ + __raw_writel(0x1, afp->mgmt_base + PCIEX8MGMT_APP_LTSSM_ENABLE); +} + +static int fu740_pcie_start_link(struct dw_pcie *pci) +{ + struct device *dev = pci->dev; + u8 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); + u32 tmp; + int ret; + + /* + * Force Gen1 operation when starting the link. In case the link is + * started in Gen2 mode, there is a possibility the devices on the + * bus will not be detected at all. This happens with PCIe switches. + */ + dw_pcie_dbi_ro_wr_en(pci); + tmp = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP); + tmp &= ~PCI_EXP_LNKCAP_SLS; + tmp |= PCI_EXP_LNKCAP_SLS_2_5GB; + dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCAP, tmp); + dw_pcie_dbi_ro_wr_dis(pci); + + /* Start LTSSM. */ + fu740_pcie_ltssm_enable(dev); + + ret = dw_pcie_wait_for_link(pci); + if (ret) + goto err_reset_phy; + + /* Now set it to operate in Gen3 */ + dw_pcie_dbi_ro_wr_en(pci); + tmp = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP); + tmp &= ~PCI_EXP_LNKCAP_SLS; + tmp |= PCI_EXP_LNKCAP_SLS_8_0GB; + dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCAP, tmp); + /* Enable DIRECTED SPEED CHANGE bit of GEN2_CTRL_OFF register */ + tmp = dw_pcie_readl_dbi(pci, PCIE_PL_GEN2_CTRL_OFF); + tmp |= PCIE_PL_DIRECTED_SPEED_CHANGE_OFF; + dw_pcie_writel_dbi(pci, PCIE_PL_GEN2_CTRL_OFF, tmp); + dw_pcie_dbi_ro_wr_dis(pci); + + ret = dw_pcie_wait_for_link(pci); + if (ret) + goto err_reset_phy; + + /* + * Reenable DIRECTED SPEED CHANGE. + * + * You need to set this bit after each speed change, but after + * reaching G1, setting it once doesn't seem to work (it reaches G3 + * equalization states and then times out, falls back to G1). But + * If after that, you set it again, it then reaches G3 perfectly + * fine. + */ + dw_pcie_dbi_ro_wr_en(pci); + tmp = dw_pcie_readl_dbi(pci, PCIE_PL_GEN2_CTRL_OFF); + tmp |= PCIE_PL_DIRECTED_SPEED_CHANGE_OFF; + dw_pcie_writel_dbi(pci, PCIE_PL_GEN2_CTRL_OFF, tmp); + dw_pcie_dbi_ro_wr_dis(pci); + + ret = dw_pcie_wait_for_link(pci); + if (ret) + goto err_reset_phy; + + tmp = dw_pcie_readw_dbi(pci, offset + PCI_EXP_LNKSTA); + dev_info(dev, "Link up, Gen%i\n", tmp & PCI_EXP_LNKSTA_CLS); + return 0; + + err_reset_phy: + dev_err(dev, "Failed to bring link up!\n" + "PHY DEBUG_R0=0x%08x DEBUG_R1=0x%08x\n", + dw_pcie_readl_dbi(pci, PCIE_PORT_DEBUG0), + dw_pcie_readl_dbi(pci, PCIE_PORT_DEBUG1)); + return ret; +} + +static int fu740_pcie_host_init(struct pcie_port *pp) +{ + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); + struct fu740_pcie *afp = to_fu740_pcie(pci); + struct device *dev = pci->dev; + int ret = 0; + + /* power on reset */ + fu740_pcie_drive_perstn(afp); + + /* enable pcieauxclk */ + ret = clk_prepare_enable(afp->pcie_aux); + if (ret) + dev_err(dev, "unable to enable pcie_aux clock\n"); + + /* + * assert hold_phy_rst (hold the controller LTSSM in reset after + * power_up_rst_n + * for register programming with cr_para) + */ + __raw_writel(0x1, afp->mgmt_base + PCIEX8MGMT_APP_HOLD_PHY_RST); + + /* deassert power_up_rst_n */ + ret = reset_control_deassert(afp->rst); + if (ret) + dev_err(dev, "unable to deassert pcie_power_up_rst_n\n"); + + fu740_pcie_init_phy(afp); + + /* disable pcieauxclk */ + clk_disable_unprepare(afp->pcie_aux); + /* clear hold_phy_rst */ + __raw_writel(0x0, afp->mgmt_base + PCIEX8MGMT_APP_HOLD_PHY_RST); + /* enable pcieauxclk */ + ret = clk_prepare_enable(afp->pcie_aux); + /* set RC mode */ + __raw_writel(0x4, afp->mgmt_base + PCIEX8MGMT_DEVICE_TYPE); + + return 0; +} + +static const struct dw_pcie_host_ops fu740_pcie_host_ops = { + .host_init = fu740_pcie_host_init, +}; + +static const struct dw_pcie_ops dw_pcie_ops = { + .start_link = fu740_pcie_start_link, +}; + +static const struct dev_pm_ops fu740_pcie_pm_ops = { + SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(fu740_pcie_suspend_noirq, + fu740_pcie_resume_noirq) +}; + +static int fu740_pcie_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct dw_pcie *pci; + struct fu740_pcie *afp; + struct resource *mgmt_res; + struct device_node *node = dev->of_node; + int ret; + u16 val; + + afp = devm_kzalloc(dev, sizeof(*afp), GFP_KERNEL); + if (!afp) + return -ENOMEM; + + pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL); + if (!pci) + return -ENOMEM; + + pci->dev = dev; + pci->ops = &dw_pcie_ops; + pci->pp.ops = &fu740_pcie_host_ops; + + afp->pci = pci; + + mgmt_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mgmt"); + if (!mgmt_res) { + dev_warn(dev, "missing required mgmt address range"); + return -ENOENT; + } + afp->mgmt_base = devm_ioremap_resource(dev, mgmt_res); + if (IS_ERR(afp->mgmt_base)) + return PTR_ERR(afp->mgmt_base); + + /* Fetch GPIOs */ + afp->perstn_gpio = of_get_named_gpio(node, "perstn-gpios", 0); + if (gpio_is_valid(afp->perstn_gpio)) { + ret = devm_gpio_request_one(dev, afp->perstn_gpio, + GPIOF_OUT_INIT_LOW, "perstn-gpios"); + if (ret) { + dev_err(dev, "unable to get perstn gpio\n"); + return ret; + } + } else if (afp->perstn_gpio == -EPROBE_DEFER) { + dev_err(dev, "perst-gpios EPROBE_DEFER\n"); + return afp->perstn_gpio; + } + + afp->pwren_gpio = of_get_named_gpio(node, "pwren-gpios", 0); + if (gpio_is_valid(afp->pwren_gpio)) { + ret = devm_gpio_request_one(dev, afp->pwren_gpio, + GPIOF_OUT_INIT_LOW, "pwren-gpios"); + if (ret) { + dev_err(dev, "unable to get pwren gpio\n"); + return ret; + } + } else if (afp->pwren_gpio == -EPROBE_DEFER) { + dev_err(dev, "pwren-gpios EPROBE_DEFER\n"); + return afp->pwren_gpio; + } + + /* Fetch clocks */ + afp->pcie_aux = devm_clk_get(dev, "pcie_aux"); + if (IS_ERR(afp->pcie_aux)) + return dev_err_probe(dev, PTR_ERR(afp->pcie_aux), + "pcie_aux clock source missing or invalid\n"); + + /* Fetch reset */ + afp->rst = devm_reset_control_get(dev, NULL); + if (IS_ERR(afp->rst)) + return dev_err_probe(dev, PTR_ERR(afp->rst), "unable to get reset\n"); + + platform_set_drvdata(pdev, afp); + + ret = dw_pcie_host_init(&pci->pp); + if (ret < 0) + return ret; + + if (pci_msi_enabled()) { + u8 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_MSI); + + val = dw_pcie_readw_dbi(pci, offset + PCI_MSI_FLAGS); + val |= PCI_MSI_FLAGS_ENABLE; + dw_pcie_writew_dbi(pci, offset + PCI_MSI_FLAGS, val); + } + + return 0; +} + +static void fu740_pcie_shutdown(struct platform_device *pdev) +{ + struct fu740_pcie *afp = platform_get_drvdata(pdev); + + /* bring down link, so bootloader gets clean state in case of reboot */ + fu740_pcie_assert_perstn(afp); +} + +static const struct of_device_id fu740_pcie_of_match[] = { + {.compatible = "sifive,fu740-pcie"}, + {}, +}; + +static struct platform_driver fu740_pcie_driver = { + .driver = { + .name = "fu740-pcie", + .of_match_table = fu740_pcie_of_match, + .suppress_bind_attrs = true, + .pm = &fu740_pcie_pm_ops, + }, + .probe = fu740_pcie_probe, + .shutdown = fu740_pcie_shutdown, +}; + +static int __init fu740_pcie_init(void) +{ + return platform_driver_register(&fu740_pcie_driver); +} + +device_initcall(fu740_pcie_init); From patchwork Tue Mar 16 21:31:15 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dimitri John Ledkov X-Patchwork-Id: 1454495 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.ubuntu.com (client-ip=91.189.94.19; helo=huckleberry.canonical.com; envelope-from=kernel-team-bounces@lists.ubuntu.com; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; secure) header.d=surgut.co.uk header.i=@surgut.co.uk header.a=rsa-sha256 header.s=google header.b=ZwDEGd6Q; dkim-atps=neutral Received: from huckleberry.canonical.com (huckleberry.canonical.com [91.189.94.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4F0gtY5McKz9sjJ; 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Tue, 16 Mar 2021 14:31:49 -0700 (PDT) From: Dimitri John Ledkov To: kernel-team@lists.ubuntu.com Subject: [PATCH 13/15] riscv: dts: Add PCIe support for the SiFive FU740-C000 SoC Date: Tue, 16 Mar 2021 21:31:15 +0000 Message-Id: <20210316213117.757193-14-xnox@ubuntu.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20210316213117.757193-1-xnox@ubuntu.com> References: <20210316213117.757193-1-xnox@ubuntu.com> MIME-Version: 1.0 X-Mailman-Approved-At: Wed, 17 Mar 2021 06:56:26 +0000 X-BeenThere: kernel-team@lists.ubuntu.com X-Mailman-Version: 2.1.20 Precedence: list List-Id: Kernel team discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: kernel-team-bounces@lists.ubuntu.com Sender: "kernel-team" From: Greentime Hu Signed-off-by: Greentime Hu Signed-off-by: Dimitri John Ledkov --- arch/riscv/boot/dts/sifive/fu740-c000.dtsi | 34 ++++++++++++++++++++++ 1 file changed, 34 insertions(+) diff --git a/arch/riscv/boot/dts/sifive/fu740-c000.dtsi b/arch/riscv/boot/dts/sifive/fu740-c000.dtsi index cd9cc025777d..04fe1b5dad0d 100644 --- a/arch/riscv/boot/dts/sifive/fu740-c000.dtsi +++ b/arch/riscv/boot/dts/sifive/fu740-c000.dtsi @@ -159,6 +159,7 @@ prci: clock-controller@10000000 { reg = <0x0 0x10000000 0x0 0x1000>; clocks = <&hfclk>, <&rtcclk>; #clock-cells = <1>; + #reset-cells = <1>; }; uart0: serial@10010000 { compatible = "sifive,fu740-c000-uart", "sifive,uart0"; @@ -289,5 +290,38 @@ gpio: gpio@10060000 { clocks = <&prci PRCI_CLK_PCLK>; status = "disabled"; }; + pcie@e00000000 { + #address-cells = <3>; + #interrupt-cells = <1>; + #num-lanes = <8>; + #size-cells = <2>; + compatible = "sifive,fu740-pcie"; + reg = <0xe 0x00000000 0x1 0x0 + 0xd 0xf0000000 0x0 0x10000000 + 0x0 0x100d0000 0x0 0x1000>; + reg-names = "dbi", "config", "mgmt"; + device_type = "pci"; + dma-coherent; + bus-range = <0x0 0xff>; + ranges = <0x81000000 0x0 0x60080000 0x0 0x60080000 0x0 0x10000 /* I/O */ + 0x82000000 0x0 0x60090000 0x0 0x60090000 0x0 0xff70000 /* mem */ + 0x82000000 0x0 0x70000000 0x0 0x70000000 0x0 0x1000000 /* mem */ + 0xc3000000 0x20 0x00000000 0x20 0x00000000 0x20 0x00000000>; /* mem prefetchable */ + num-lanes = <0x8>; + interrupts = <56 57 58 59 60 61 62 63 64>; + interrupt-names = "msi", "inta", "intb", "intc", "intd"; + interrupt-parent = <&plic0>; + interrupt-map-mask = <0x0 0x0 0x0 0x7>; + interrupt-map = <0x0 0x0 0x0 0x1 &plic0 57>, + <0x0 0x0 0x0 0x2 &plic0 58>, + <0x0 0x0 0x0 0x3 &plic0 59>, + <0x0 0x0 0x0 0x4 &plic0 60>; + clock-names = "pcie_aux"; + clocks = <&prci PRCI_CLK_PCIE_AUX>; + pwren-gpios = <&gpio 5 0>; + perstn-gpios = <&gpio 8 0>; + resets = <&prci 4>; + status = "okay"; + }; }; }; From patchwork Tue Mar 16 21:31:16 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dimitri John Ledkov X-Patchwork-Id: 1454499 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.ubuntu.com (client-ip=91.189.94.19; helo=huckleberry.canonical.com; envelope-from=kernel-team-bounces@lists.ubuntu.com; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; 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Tue, 16 Mar 2021 14:31:50 -0700 (PDT) Received: from localhost ([2a01:4b00:85fd:d700:da2f:147e:3a8a:27aa]) by smtp.gmail.com with ESMTPSA id u2sm23650490wrp.12.2021.03.16.14.31.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Mar 2021 14:31:50 -0700 (PDT) From: Dimitri John Ledkov To: kernel-team@lists.ubuntu.com Subject: [PATCH 14/15] UBUNTU: [Config] update configs for unmatched Date: Tue, 16 Mar 2021 21:31:16 +0000 Message-Id: <20210316213117.757193-15-xnox@ubuntu.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20210316213117.757193-1-xnox@ubuntu.com> References: <20210316213117.757193-1-xnox@ubuntu.com> MIME-Version: 1.0 X-Mailman-Approved-At: Wed, 17 Mar 2021 06:56:26 +0000 X-BeenThere: kernel-team@lists.ubuntu.com X-Mailman-Version: 2.1.20 Precedence: list List-Id: Kernel team discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: kernel-team-bounces@lists.ubuntu.com Sender: "kernel-team" Signed-off-by: Dimitri John Ledkov --- debian.riscv/config/config.common.ubuntu | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/debian.riscv/config/config.common.ubuntu b/debian.riscv/config/config.common.ubuntu index 1801ee401192..6248ecd67ce5 100644 --- a/debian.riscv/config/config.common.ubuntu +++ b/debian.riscv/config/config.common.ubuntu @@ -1154,6 +1154,7 @@ CONFIG_CPU_IDLE_GOV_MENU=y CONFIG_CPU_IDLE_GOV_TEO=y CONFIG_CPU_ISOLATION=y CONFIG_CPU_RMAP=y +CONFIG_CPU_SIFIVE=y CONFIG_CPU_THERMAL=y CONFIG_CRAMFS=m CONFIG_CRAMFS_BLOCKDEV=y @@ -1952,6 +1953,7 @@ CONFIG_EROFS_FS_POSIX_ACL=y CONFIG_EROFS_FS_SECURITY=y CONFIG_EROFS_FS_XATTR=y CONFIG_EROFS_FS_ZIP=y +CONFIG_ERRATA_SIFIVE_CIP_453=y CONFIG_ET131X=m CONFIG_ETHERNET=y CONFIG_ETHOC=m @@ -4992,6 +4994,7 @@ CONFIG_PCIE_DW_PLAT=y CONFIG_PCIE_DW_PLAT_EP=y CONFIG_PCIE_DW_PLAT_HOST=y # CONFIG_PCIE_ECRC is not set +CONFIG_PCIE_FU740=y CONFIG_PCIE_MICROSEMI=y CONFIG_PCIE_PTM=y CONFIG_PCIE_XILINX=y @@ -5491,6 +5494,7 @@ CONFIG_RESET_ATTACK_MITIGATION=y CONFIG_RESET_BRCMSTB_RESCAL=y CONFIG_RESET_CONTROLLER=y CONFIG_RESET_INTEL_GW=y +CONFIG_RESET_SIMPLE=y CONFIG_RESET_TI_SYSCON=m CONFIG_RETU_WATCHDOG=m CONFIG_RFD77402=m @@ -5509,6 +5513,7 @@ CONFIG_RIONET_RX_SIZE=128 CONFIG_RIONET_TX_SIZE=128 CONFIG_RISCV=y CONFIG_RISCV_BASE_PMU=y +CONFIG_RISCV_ERRATA_ALTERNATIVE=y CONFIG_RISCV_INTC=y CONFIG_RISCV_ISA_C=y CONFIG_RISCV_SBI=y From patchwork Tue Mar 16 21:31:17 2021 Content-Type: text/plain; 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