From patchwork Sun Mar 7 12:08:09 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Mark Cave-Ayland X-Patchwork-Id: 1448634 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4DtgNQ5ym0z9sCD for ; Sun, 7 Mar 2021 23:13:10 +1100 (AEDT) Received: from localhost ([::1]:44216 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lIsHU-0003oK-Pk for incoming@patchwork.ozlabs.org; Sun, 07 Mar 2021 07:13:08 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:41146) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lIsDm-0000J5-DO for qemu-devel@nongnu.org; Sun, 07 Mar 2021 07:09:18 -0500 Received: from mail.ilande.co.uk ([2001:41c9:1:41f::167]:43556 helo=mail.default.ilande.uk0.bigv.io) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lIsDk-0007UF-Os for qemu-devel@nongnu.org; Sun, 07 Mar 2021 07:09:18 -0500 Received: from host86-148-34-47.range86-148.btcentralplus.com ([86.148.34.47] helo=kentang.home) by mail.default.ilande.uk0.bigv.io with esmtpsa (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1lIsDe-0002V5-3s; Sun, 07 Mar 2021 12:09:16 +0000 From: Mark Cave-Ayland To: qemu-devel@nongnu.org, peter.maydell@linaro.org Date: Sun, 7 Mar 2021 12:08:09 +0000 Message-Id: <20210307120850.10418-2-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210307120850.10418-1-mark.cave-ayland@ilande.co.uk> References: <20210307120850.10418-1-mark.cave-ayland@ilande.co.uk> MIME-Version: 1.0 X-SA-Exim-Connect-IP: 86.148.34.47 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk Subject: [PULL 01/42] esp: checkpatch fixes X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on mail.default.ilande.uk0.bigv.io) Received-SPF: pass client-ip=2001:41c9:1:41f::167; envelope-from=mark.cave-ayland@ilande.co.uk; helo=mail.default.ilande.uk0.bigv.io X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Mark Cave-Ayland Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Laurent Vivier Message-Id: <20210304221103.6369-2-mark.cave-ayland@ilande.co.uk> --- hw/scsi/esp.c | 52 ++++++++++++++++++++++++++++++--------------------- 1 file changed, 31 insertions(+), 21 deletions(-) diff --git a/hw/scsi/esp.c b/hw/scsi/esp.c index 93d9c9c7b9..6bb4025d2a 100644 --- a/hw/scsi/esp.c +++ b/hw/scsi/esp.c @@ -241,8 +241,9 @@ static void handle_satn(ESPState *s) } s->pdma_cb = satn_pdma_cb; len = get_cmd(s, buf, sizeof(buf)); - if (len) + if (len) { do_cmd(s, buf); + } } static void s_without_satn_pdma_cb(ESPState *s) @@ -398,8 +399,8 @@ static void esp_do_dma(ESPState *s) * handle_ti_cmd() with do_cmd != NULL (see the assert()) */ trace_esp_do_dma(s->cmdlen, len); - assert (s->cmdlen <= sizeof(s->cmdbuf) && - len <= sizeof(s->cmdbuf) - s->cmdlen); + assert(s->cmdlen <= sizeof(s->cmdbuf) && + len <= sizeof(s->cmdbuf) - s->cmdlen); if (s->dma_memory_read) { s->dma_memory_read(s->dma_opaque, &s->cmdbuf[s->cmdlen], len); } else { @@ -445,15 +446,18 @@ static void esp_do_dma(ESPState *s) s->dma_left -= len; s->async_buf += len; s->async_len -= len; - if (to_device) + if (to_device) { s->ti_size += len; - else + } else { s->ti_size -= len; + } if (s->async_len == 0) { scsi_req_continue(s->current_req); - /* If there is still data to be read from the device then - complete the DMA operation immediately. Otherwise defer - until the scsi layer has completed. */ + /* + * If there is still data to be read from the device then + * complete the DMA operation immediately. Otherwise defer + * until the scsi layer has completed. + */ if (to_device || s->dma_left != 0 || s->ti_size == 0) { return; } @@ -490,7 +494,8 @@ void esp_command_complete(SCSIRequest *req, size_t resid) ESPState *s = req->hba_private; if (s->rregs[ESP_RSTAT] & STAT_INT) { - /* Defer handling command complete until the previous + /* + * Defer handling command complete until the previous * interrupt has been handled. */ trace_esp_command_complete_deferred(); @@ -512,8 +517,10 @@ void esp_transfer_data(SCSIRequest *req, uint32_t len) if (s->dma_left) { esp_do_dma(s); } else if (s->dma_counter != 0 && s->ti_size <= 0) { - /* If this was the last part of a DMA transfer then the - completion interrupt is deferred to here. */ + /* + * If this was the last part of a DMA transfer then the + * completion interrupt is deferred to here. + */ esp_dma_done(s); } } @@ -530,17 +537,18 @@ static void handle_ti(ESPState *s) dmalen = s->rregs[ESP_TCLO]; dmalen |= s->rregs[ESP_TCMID] << 8; dmalen |= s->rregs[ESP_TCHI] << 16; - if (dmalen==0) { - dmalen=0x10000; + if (dmalen == 0) { + dmalen = 0x10000; } s->dma_counter = dmalen; - if (s->do_cmd) + if (s->do_cmd) { minlen = (dmalen < ESP_CMDBUF_SZ) ? dmalen : ESP_CMDBUF_SZ; - else if (s->ti_size < 0) + } else if (s->ti_size < 0) { minlen = (dmalen < -s->ti_size) ? dmalen : -s->ti_size; - else + } else { minlen = (dmalen < s->ti_size) ? dmalen : s->ti_size; + } trace_esp_handle_ti(minlen); if (s->dma) { s->dma_left = minlen; @@ -605,8 +613,10 @@ uint64_t esp_reg_read(ESPState *s, uint32_t saddr) } break; case ESP_RINTR: - /* Clear sequence step, interrupt register and all status bits - except TC */ + /* + * Clear sequence step, interrupt register and all status bits + * except TC + */ old_val = s->rregs[ESP_RINTR]; s->rregs[ESP_RINTR] = 0; s->rregs[ESP_RSTAT] &= ~STAT_TC; @@ -664,13 +674,13 @@ void esp_reg_write(ESPState *s, uint32_t saddr, uint64_t val) } else { s->dma = 0; } - switch(val & CMD_CMD) { + switch (val & CMD_CMD) { case CMD_NOP: trace_esp_mem_writeb_cmd_nop(val); break; case CMD_FLUSH: trace_esp_mem_writeb_cmd_flush(val); - //s->ti_size = 0; + /*s->ti_size = 0;*/ s->rregs[ESP_RINTR] = INTR_FC; s->rregs[ESP_RSEQ] = 0; s->rregs[ESP_RFLAGS] = 0; @@ -786,7 +796,7 @@ static const VMStateDescription vmstate_esp_pdma = { }; const VMStateDescription vmstate_esp = { - .name ="esp", + .name = "esp", .version_id = 4, .minimum_version_id = 3, .fields = (VMStateField[]) { From patchwork Sun Mar 7 12:08:10 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Mark Cave-Ayland X-Patchwork-Id: 1448638 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4DtgT41p7cz9sWb for ; Sun, 7 Mar 2021 23:17:12 +1100 (AEDT) Received: from localhost ([::1]:52848 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lIsLO-0007hT-8q for incoming@patchwork.ozlabs.org; Sun, 07 Mar 2021 07:17:10 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:41186) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lIsDx-0000OP-2H for qemu-devel@nongnu.org; Sun, 07 Mar 2021 07:09:30 -0500 Received: from mail.ilande.co.uk ([2001:41c9:1:41f::167]:43562 helo=mail.default.ilande.uk0.bigv.io) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lIsDp-0007VG-CD for qemu-devel@nongnu.org; Sun, 07 Mar 2021 07:09:27 -0500 Received: from host86-148-34-47.range86-148.btcentralplus.com ([86.148.34.47] helo=kentang.home) by mail.default.ilande.uk0.bigv.io with esmtpsa (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1lIsDk-0002V5-DE; Sun, 07 Mar 2021 12:09:20 +0000 From: Mark Cave-Ayland To: qemu-devel@nongnu.org, peter.maydell@linaro.org Date: Sun, 7 Mar 2021 12:08:10 +0000 Message-Id: <20210307120850.10418-3-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210307120850.10418-1-mark.cave-ayland@ilande.co.uk> References: <20210307120850.10418-1-mark.cave-ayland@ilande.co.uk> MIME-Version: 1.0 X-SA-Exim-Connect-IP: 86.148.34.47 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk Subject: [PULL 02/42] esp: rename existing ESP QOM type to SYSBUS_ESP X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on mail.default.ilande.uk0.bigv.io) Received-SPF: pass client-ip=2001:41c9:1:41f::167; envelope-from=mark.cave-ayland@ilande.co.uk; helo=mail.default.ilande.uk0.bigv.io X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" The existing ESP QOM type currently represents a sysbus device with an embedded ESP state. Rename the type to SYSBUS_ESP accordingly. Signed-off-by: Mark Cave-Ayland Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Laurent Vivier Message-Id: <20210304221103.6369-3-mark.cave-ayland@ilande.co.uk> --- hw/dma/sparc32_dma.c | 4 ++-- hw/m68k/q800.c | 4 ++-- hw/mips/jazz.c | 4 ++-- hw/scsi/esp.c | 8 ++++---- hw/sparc/sun4m.c | 2 +- include/hw/scsi/esp.h | 4 ++-- 6 files changed, 13 insertions(+), 13 deletions(-) diff --git a/hw/dma/sparc32_dma.c b/hw/dma/sparc32_dma.c index b643b413c5..03bc500878 100644 --- a/hw/dma/sparc32_dma.c +++ b/hw/dma/sparc32_dma.c @@ -295,13 +295,13 @@ static void sparc32_espdma_device_init(Object *obj) memory_region_init_io(&s->iomem, OBJECT(s), &dma_mem_ops, s, "espdma-mmio", DMA_SIZE); - object_initialize_child(obj, "esp", &es->esp, TYPE_ESP); + object_initialize_child(obj, "esp", &es->esp, TYPE_SYSBUS_ESP); } static void sparc32_espdma_device_realize(DeviceState *dev, Error **errp) { ESPDMADeviceState *es = SPARC32_ESPDMA_DEVICE(dev); - SysBusESPState *sysbus = ESP(&es->esp); + SysBusESPState *sysbus = SYSBUS_ESP(&es->esp); ESPState *esp = &sysbus->esp; esp->dma_memory_read = espdma_memory_read; diff --git a/hw/m68k/q800.c b/hw/m68k/q800.c index d4eca46767..4d2e866eec 100644 --- a/hw/m68k/q800.c +++ b/hw/m68k/q800.c @@ -350,8 +350,8 @@ static void q800_init(MachineState *machine) /* SCSI */ - dev = qdev_new(TYPE_ESP); - sysbus_esp = ESP(dev); + dev = qdev_new(TYPE_SYSBUS_ESP); + sysbus_esp = SYSBUS_ESP(dev); esp = &sysbus_esp->esp; esp->dma_memory_read = NULL; esp->dma_memory_write = NULL; diff --git a/hw/mips/jazz.c b/hw/mips/jazz.c index 83c8086062..1a0888a0fd 100644 --- a/hw/mips/jazz.c +++ b/hw/mips/jazz.c @@ -328,8 +328,8 @@ static void mips_jazz_init(MachineState *machine, } /* SCSI adapter */ - dev = qdev_new(TYPE_ESP); - sysbus_esp = ESP(dev); + dev = qdev_new(TYPE_SYSBUS_ESP); + sysbus_esp = SYSBUS_ESP(dev); esp = &sysbus_esp->esp; esp->dma_memory_read = rc4030_dma_read; esp->dma_memory_write = rc4030_dma_write; diff --git a/hw/scsi/esp.c b/hw/scsi/esp.c index 6bb4025d2a..93312a68d9 100644 --- a/hw/scsi/esp.c +++ b/hw/scsi/esp.c @@ -938,7 +938,7 @@ static const struct SCSIBusInfo esp_scsi_info = { static void sysbus_esp_gpio_demux(void *opaque, int irq, int level) { - SysBusESPState *sysbus = ESP(opaque); + SysBusESPState *sysbus = SYSBUS_ESP(opaque); ESPState *s = &sysbus->esp; switch (irq) { @@ -954,7 +954,7 @@ static void sysbus_esp_gpio_demux(void *opaque, int irq, int level) static void sysbus_esp_realize(DeviceState *dev, Error **errp) { SysBusDevice *sbd = SYS_BUS_DEVICE(dev); - SysBusESPState *sysbus = ESP(dev); + SysBusESPState *sysbus = SYSBUS_ESP(dev); ESPState *s = &sysbus->esp; sysbus_init_irq(sbd, &s->irq); @@ -976,7 +976,7 @@ static void sysbus_esp_realize(DeviceState *dev, Error **errp) static void sysbus_esp_hard_reset(DeviceState *dev) { - SysBusESPState *sysbus = ESP(dev); + SysBusESPState *sysbus = SYSBUS_ESP(dev); esp_hard_reset(&sysbus->esp); } @@ -1001,7 +1001,7 @@ static void sysbus_esp_class_init(ObjectClass *klass, void *data) } static const TypeInfo sysbus_esp_info = { - .name = TYPE_ESP, + .name = TYPE_SYSBUS_ESP, .parent = TYPE_SYS_BUS_DEVICE, .instance_size = sizeof(SysBusESPState), .class_init = sysbus_esp_class_init, diff --git a/hw/sparc/sun4m.c b/hw/sparc/sun4m.c index 38ca1e33c7..312e2afaf9 100644 --- a/hw/sparc/sun4m.c +++ b/hw/sparc/sun4m.c @@ -334,7 +334,7 @@ static void *sparc32_dma_init(hwaddr dma_base, OBJECT(dma), "espdma")); sysbus_connect_irq(SYS_BUS_DEVICE(espdma), 0, espdma_irq); - esp = ESP(object_resolve_path_component(OBJECT(espdma), "esp")); + esp = SYSBUS_ESP(object_resolve_path_component(OBJECT(espdma), "esp")); ledma = SPARC32_LEDMA_DEVICE(object_resolve_path_component( OBJECT(dma), "ledma")); diff --git a/include/hw/scsi/esp.h b/include/hw/scsi/esp.h index d8a6263c13..8a0740e953 100644 --- a/include/hw/scsi/esp.h +++ b/include/hw/scsi/esp.h @@ -65,8 +65,8 @@ struct ESPState { void (*pdma_cb)(ESPState *s); }; -#define TYPE_ESP "esp" -OBJECT_DECLARE_SIMPLE_TYPE(SysBusESPState, ESP) +#define TYPE_SYSBUS_ESP "sysbus-esp" +OBJECT_DECLARE_SIMPLE_TYPE(SysBusESPState, SYSBUS_ESP) struct SysBusESPState { /*< private >*/ From patchwork Sun Mar 7 12:08:11 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Mark Cave-Ayland X-Patchwork-Id: 1448642 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4DtgZ54MV8z9sRf for ; Sun, 7 Mar 2021 23:21:32 +1100 (AEDT) Received: from localhost ([::1]:33230 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lIsPa-0002rR-0f for incoming@patchwork.ozlabs.org; Sun, 07 Mar 2021 07:21:30 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:41202) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lIsDy-0000Op-Dr for qemu-devel@nongnu.org; Sun, 07 Mar 2021 07:09:30 -0500 Received: from mail.ilande.co.uk ([2001:41c9:1:41f::167]:43568 helo=mail.default.ilande.uk0.bigv.io) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lIsDu-0007Vz-7a for qemu-devel@nongnu.org; Sun, 07 Mar 2021 07:09:30 -0500 Received: from host86-148-34-47.range86-148.btcentralplus.com ([86.148.34.47] helo=kentang.home) by mail.default.ilande.uk0.bigv.io with esmtpsa (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1lIsDo-0002V5-HT; Sun, 07 Mar 2021 12:09:25 +0000 From: Mark Cave-Ayland To: qemu-devel@nongnu.org, peter.maydell@linaro.org Date: Sun, 7 Mar 2021 12:08:11 +0000 Message-Id: <20210307120850.10418-4-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210307120850.10418-1-mark.cave-ayland@ilande.co.uk> References: <20210307120850.10418-1-mark.cave-ayland@ilande.co.uk> MIME-Version: 1.0 X-SA-Exim-Connect-IP: 86.148.34.47 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk Subject: [PULL 03/42] esp: QOMify the internal ESP device state X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on mail.default.ilande.uk0.bigv.io) Received-SPF: pass client-ip=2001:41c9:1:41f::167; envelope-from=mark.cave-ayland@ilande.co.uk; helo=mail.default.ilande.uk0.bigv.io X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Make this new QOM device state a child device of both the sysbus-esp and esp-pci implementations. Signed-off-by: Mark Cave-Ayland Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Laurent Vivier Message-Id: <20210304221103.6369-4-mark.cave-ayland@ilande.co.uk> --- hw/scsi/esp-pci.c | 50 ++++++++++++++++++++++++++++++++----------- hw/scsi/esp.c | 47 ++++++++++++++++++++++++++++++++++------ include/hw/scsi/esp.h | 5 +++++ 3 files changed, 82 insertions(+), 20 deletions(-) diff --git a/hw/scsi/esp-pci.c b/hw/scsi/esp-pci.c index 4d7c2cab56..27a0d36e0b 100644 --- a/hw/scsi/esp-pci.c +++ b/hw/scsi/esp-pci.c @@ -79,8 +79,10 @@ struct PCIESPState { static void esp_pci_handle_idle(PCIESPState *pci, uint32_t val) { + ESPState *s = ESP(&pci->esp); + trace_esp_pci_dma_idle(val); - esp_dma_enable(&pci->esp, 0, 0); + esp_dma_enable(s, 0, 0); } static void esp_pci_handle_blast(PCIESPState *pci, uint32_t val) @@ -91,14 +93,18 @@ static void esp_pci_handle_blast(PCIESPState *pci, uint32_t val) static void esp_pci_handle_abort(PCIESPState *pci, uint32_t val) { + ESPState *s = ESP(&pci->esp); + trace_esp_pci_dma_abort(val); - if (pci->esp.current_req) { - scsi_req_cancel(pci->esp.current_req); + if (s->current_req) { + scsi_req_cancel(s->current_req); } } static void esp_pci_handle_start(PCIESPState *pci, uint32_t val) { + ESPState *s = ESP(&pci->esp); + trace_esp_pci_dma_start(val); pci->dma_regs[DMA_WBC] = pci->dma_regs[DMA_STC]; @@ -109,7 +115,7 @@ static void esp_pci_handle_start(PCIESPState *pci, uint32_t val) | DMA_STAT_DONE | DMA_STAT_ABORT | DMA_STAT_ERROR | DMA_STAT_PWDN); - esp_dma_enable(&pci->esp, 0, 1); + esp_dma_enable(s, 0, 1); } static void esp_pci_dma_write(PCIESPState *pci, uint32_t saddr, uint32_t val) @@ -155,11 +161,12 @@ static void esp_pci_dma_write(PCIESPState *pci, uint32_t saddr, uint32_t val) static uint32_t esp_pci_dma_read(PCIESPState *pci, uint32_t saddr) { + ESPState *s = ESP(&pci->esp); uint32_t val; val = pci->dma_regs[saddr]; if (saddr == DMA_STAT) { - if (pci->esp.rregs[ESP_RSTAT] & STAT_INT) { + if (s->rregs[ESP_RSTAT] & STAT_INT) { val |= DMA_STAT_SCSIINT; } if (!(pci->sbac & SBAC_STATUS)) { @@ -176,6 +183,7 @@ static void esp_pci_io_write(void *opaque, hwaddr addr, uint64_t val, unsigned int size) { PCIESPState *pci = opaque; + ESPState *s = ESP(&pci->esp); if (size < 4 || addr & 3) { /* need to upgrade request: we only support 4-bytes accesses */ @@ -183,7 +191,7 @@ static void esp_pci_io_write(void *opaque, hwaddr addr, int shift; if (addr < 0x40) { - current = pci->esp.wregs[addr >> 2]; + current = s->wregs[addr >> 2]; } else if (addr < 0x60) { current = pci->dma_regs[(addr - 0x40) >> 2]; } else if (addr < 0x74) { @@ -203,7 +211,7 @@ static void esp_pci_io_write(void *opaque, hwaddr addr, if (addr < 0x40) { /* SCSI core reg */ - esp_reg_write(&pci->esp, addr >> 2, val); + esp_reg_write(s, addr >> 2, val); } else if (addr < 0x60) { /* PCI DMA CCB */ esp_pci_dma_write(pci, (addr - 0x40) >> 2, val); @@ -220,11 +228,12 @@ static uint64_t esp_pci_io_read(void *opaque, hwaddr addr, unsigned int size) { PCIESPState *pci = opaque; + ESPState *s = ESP(&pci->esp); uint32_t ret; if (addr < 0x40) { /* SCSI core reg */ - ret = esp_reg_read(&pci->esp, addr >> 2); + ret = esp_reg_read(s, addr >> 2); } else if (addr < 0x60) { /* PCI DMA CCB */ ret = esp_pci_dma_read(pci, (addr - 0x40) >> 2); @@ -306,7 +315,9 @@ static const MemoryRegionOps esp_pci_io_ops = { static void esp_pci_hard_reset(DeviceState *dev) { PCIESPState *pci = PCI_ESP(dev); - esp_hard_reset(&pci->esp); + ESPState *s = ESP(&pci->esp); + + esp_hard_reset(s); pci->dma_regs[DMA_CMD] &= ~(DMA_CMD_DIR | DMA_CMD_INTE_D | DMA_CMD_INTE_P | DMA_CMD_MDL | DMA_CMD_DIAG | DMA_CMD_MASK); pci->dma_regs[DMA_WBC] &= ~0xffff; @@ -353,9 +364,13 @@ static void esp_pci_scsi_realize(PCIDevice *dev, Error **errp) { PCIESPState *pci = PCI_ESP(dev); DeviceState *d = DEVICE(dev); - ESPState *s = &pci->esp; + ESPState *s = ESP(&pci->esp); uint8_t *pci_conf; + if (!qdev_realize(DEVICE(s), NULL, errp)) { + return; + } + pci_conf = dev->config; /* Interrupt pin A */ @@ -374,11 +389,19 @@ static void esp_pci_scsi_realize(PCIDevice *dev, Error **errp) scsi_bus_new(&s->bus, sizeof(s->bus), d, &esp_pci_scsi_info, NULL); } -static void esp_pci_scsi_uninit(PCIDevice *d) +static void esp_pci_scsi_exit(PCIDevice *d) { PCIESPState *pci = PCI_ESP(d); + ESPState *s = ESP(&pci->esp); + + qemu_free_irq(s->irq); +} + +static void esp_pci_init(Object *obj) +{ + PCIESPState *pci = PCI_ESP(obj); - qemu_free_irq(pci->esp.irq); + object_initialize_child(obj, "esp", &pci->esp, TYPE_ESP); } static void esp_pci_class_init(ObjectClass *klass, void *data) @@ -387,7 +410,7 @@ static void esp_pci_class_init(ObjectClass *klass, void *data) PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); k->realize = esp_pci_scsi_realize; - k->exit = esp_pci_scsi_uninit; + k->exit = esp_pci_scsi_exit; k->vendor_id = PCI_VENDOR_ID_AMD; k->device_id = PCI_DEVICE_ID_AMD_SCSI; k->revision = 0x10; @@ -401,6 +424,7 @@ static void esp_pci_class_init(ObjectClass *klass, void *data) static const TypeInfo esp_pci_info = { .name = TYPE_AM53C974_DEVICE, .parent = TYPE_PCI_DEVICE, + .instance_init = esp_pci_init, .instance_size = sizeof(PCIESPState), .class_init = esp_pci_class_init, .interfaces = (InterfaceInfo[]) { diff --git a/hw/scsi/esp.c b/hw/scsi/esp.c index 93312a68d9..6f8a1d1224 100644 --- a/hw/scsi/esp.c +++ b/hw/scsi/esp.c @@ -827,20 +827,22 @@ static void sysbus_esp_mem_write(void *opaque, hwaddr addr, uint64_t val, unsigned int size) { SysBusESPState *sysbus = opaque; + ESPState *s = ESP(&sysbus->esp); uint32_t saddr; saddr = addr >> sysbus->it_shift; - esp_reg_write(&sysbus->esp, saddr, val); + esp_reg_write(s, saddr, val); } static uint64_t sysbus_esp_mem_read(void *opaque, hwaddr addr, unsigned int size) { SysBusESPState *sysbus = opaque; + ESPState *s = ESP(&sysbus->esp); uint32_t saddr; saddr = addr >> sysbus->it_shift; - return esp_reg_read(&sysbus->esp, saddr); + return esp_reg_read(s, saddr); } static const MemoryRegionOps sysbus_esp_mem_ops = { @@ -854,7 +856,7 @@ static void sysbus_esp_pdma_write(void *opaque, hwaddr addr, uint64_t val, unsigned int size) { SysBusESPState *sysbus = opaque; - ESPState *s = &sysbus->esp; + ESPState *s = ESP(&sysbus->esp); uint32_t dmalen; uint8_t *buf = get_pdma_buf(s); @@ -891,7 +893,7 @@ static uint64_t sysbus_esp_pdma_read(void *opaque, hwaddr addr, unsigned int size) { SysBusESPState *sysbus = opaque; - ESPState *s = &sysbus->esp; + ESPState *s = ESP(&sysbus->esp); uint8_t *buf = get_pdma_buf(s); uint64_t val = 0; @@ -939,7 +941,7 @@ static const struct SCSIBusInfo esp_scsi_info = { static void sysbus_esp_gpio_demux(void *opaque, int irq, int level) { SysBusESPState *sysbus = SYSBUS_ESP(opaque); - ESPState *s = &sysbus->esp; + ESPState *s = ESP(&sysbus->esp); switch (irq) { case 0: @@ -955,7 +957,11 @@ static void sysbus_esp_realize(DeviceState *dev, Error **errp) { SysBusDevice *sbd = SYS_BUS_DEVICE(dev); SysBusESPState *sysbus = SYSBUS_ESP(dev); - ESPState *s = &sysbus->esp; + ESPState *s = ESP(&sysbus->esp); + + if (!qdev_realize(DEVICE(s), NULL, errp)) { + return; + } sysbus_init_irq(sbd, &s->irq); sysbus_init_irq(sbd, &s->irq_data); @@ -977,7 +983,16 @@ static void sysbus_esp_realize(DeviceState *dev, Error **errp) static void sysbus_esp_hard_reset(DeviceState *dev) { SysBusESPState *sysbus = SYSBUS_ESP(dev); - esp_hard_reset(&sysbus->esp); + ESPState *s = ESP(&sysbus->esp); + + esp_hard_reset(s); +} + +static void sysbus_esp_init(Object *obj) +{ + SysBusESPState *sysbus = SYSBUS_ESP(obj); + + object_initialize_child(obj, "esp", &sysbus->esp, TYPE_ESP); } static const VMStateDescription vmstate_sysbus_esp_scsi = { @@ -1003,13 +1018,31 @@ static void sysbus_esp_class_init(ObjectClass *klass, void *data) static const TypeInfo sysbus_esp_info = { .name = TYPE_SYSBUS_ESP, .parent = TYPE_SYS_BUS_DEVICE, + .instance_init = sysbus_esp_init, .instance_size = sizeof(SysBusESPState), .class_init = sysbus_esp_class_init, }; +static void esp_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + /* internal device for sysbusesp/pciespscsi, not user-creatable */ + dc->user_creatable = false; + set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); +} + +static const TypeInfo esp_info = { + .name = TYPE_ESP, + .parent = TYPE_DEVICE, + .instance_size = sizeof(ESPState), + .class_init = esp_class_init, +}; + static void esp_register_types(void) { type_register_static(&sysbus_esp_info); + type_register_static(&esp_info); } type_init(esp_register_types) diff --git a/include/hw/scsi/esp.h b/include/hw/scsi/esp.h index 8a0740e953..af23f813cb 100644 --- a/include/hw/scsi/esp.h +++ b/include/hw/scsi/esp.h @@ -22,7 +22,12 @@ enum pdma_origin_id { ASYNC, }; +#define TYPE_ESP "esp" +OBJECT_DECLARE_SIMPLE_TYPE(ESPState, ESP) + struct ESPState { + DeviceState parent_obj; + uint8_t rregs[ESP_REGS]; uint8_t wregs[ESP_REGS]; qemu_irq irq; From patchwork Sun Mar 7 12:08:12 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Mark Cave-Ayland X-Patchwork-Id: 1448631 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4DtgKh3Jg6z9sCD for ; Sun, 7 Mar 2021 23:10:48 +1100 (AEDT) Received: from localhost ([::1]:37034 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lIsFC-0000UD-DD for incoming@patchwork.ozlabs.org; Sun, 07 Mar 2021 07:10:46 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:41226) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lIsE1-0000QQ-0y for qemu-devel@nongnu.org; Sun, 07 Mar 2021 07:09:34 -0500 Received: from mail.ilande.co.uk ([2001:41c9:1:41f::167]:43572 helo=mail.default.ilande.uk0.bigv.io) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lIsDx-0007Xn-Pv for qemu-devel@nongnu.org; Sun, 07 Mar 2021 07:09:31 -0500 Received: from host86-148-34-47.range86-148.btcentralplus.com ([86.148.34.47] helo=kentang.home) by mail.default.ilande.uk0.bigv.io with esmtpsa (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1lIsDt-0002V5-Ds; Sun, 07 Mar 2021 12:09:29 +0000 From: Mark Cave-Ayland To: qemu-devel@nongnu.org, peter.maydell@linaro.org Date: Sun, 7 Mar 2021 12:08:12 +0000 Message-Id: <20210307120850.10418-5-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210307120850.10418-1-mark.cave-ayland@ilande.co.uk> References: <20210307120850.10418-1-mark.cave-ayland@ilande.co.uk> MIME-Version: 1.0 X-SA-Exim-Connect-IP: 86.148.34.47 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk Subject: [PULL 04/42] esp: add vmstate_esp version to embedded ESPState X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on mail.default.ilande.uk0.bigv.io) Received-SPF: pass client-ip=2001:41c9:1:41f::167; envelope-from=mark.cave-ayland@ilande.co.uk; helo=mail.default.ilande.uk0.bigv.io X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" The QOM object representing ESPState is currently embedded within both the SYSBUS_ESP and PCI_ESP devices with migration state handled by embedding vmstate_esp within each device using VMSTATE_STRUCT. Since the vmstate_esp fields are embedded directly within the migration stream, the incoming vmstate_esp version_id is lost. The only version information available is that from vmstate_sysbus_esp_scsi and vmstate_esp_pci_scsi, but those versions represent their respective devices and not that of the underlying ESPState. Resolve this by adding a new version-dependent field in vmstate_sysbus_esp_scsi and vmstate_esp_pci_scsi which stores the vmstate_esp version_id field within ESPState to be used to allow migration from older QEMU versions. Finally bump the vmstate_esp version to 5 to cover the upcoming ESPState changes within this patch series. Signed-off-by: Mark Cave-Ayland Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Laurent Vivier Message-Id: <20210304221103.6369-5-mark.cave-ayland@ilande.co.uk> --- hw/scsi/esp-pci.c | 3 ++- hw/scsi/esp.c | 23 +++++++++++++++++++++-- include/hw/scsi/esp.h | 2 ++ 3 files changed, 25 insertions(+), 3 deletions(-) diff --git a/hw/scsi/esp-pci.c b/hw/scsi/esp-pci.c index 27a0d36e0b..c3d3dab05e 100644 --- a/hw/scsi/esp-pci.c +++ b/hw/scsi/esp-pci.c @@ -330,11 +330,12 @@ static void esp_pci_hard_reset(DeviceState *dev) static const VMStateDescription vmstate_esp_pci_scsi = { .name = "pciespscsi", - .version_id = 1, + .version_id = 2, .minimum_version_id = 1, .fields = (VMStateField[]) { VMSTATE_PCI_DEVICE(parent_obj, PCIESPState), VMSTATE_BUFFER_UNSAFE(dma_regs, PCIESPState, 0, 8 * sizeof(uint32_t)), + VMSTATE_UINT8_V(esp.mig_version_id, PCIESPState, 2), VMSTATE_STRUCT(esp, PCIESPState, 0, vmstate_esp, ESPState), VMSTATE_END_OF_LIST() } diff --git a/hw/scsi/esp.c b/hw/scsi/esp.c index 6f8a1d1224..f65c675872 100644 --- a/hw/scsi/esp.c +++ b/hw/scsi/esp.c @@ -795,10 +795,28 @@ static const VMStateDescription vmstate_esp_pdma = { } }; +static int esp_pre_save(void *opaque) +{ + ESPState *s = ESP(opaque); + + s->mig_version_id = vmstate_esp.version_id; + return 0; +} + +static int esp_post_load(void *opaque, int version_id) +{ + ESPState *s = ESP(opaque); + + s->mig_version_id = vmstate_esp.version_id; + return 0; +} + const VMStateDescription vmstate_esp = { .name = "esp", - .version_id = 4, + .version_id = 5, .minimum_version_id = 3, + .pre_save = esp_pre_save, + .post_load = esp_post_load, .fields = (VMStateField[]) { VMSTATE_BUFFER(rregs, ESPState), VMSTATE_BUFFER(wregs, ESPState), @@ -997,9 +1015,10 @@ static void sysbus_esp_init(Object *obj) static const VMStateDescription vmstate_sysbus_esp_scsi = { .name = "sysbusespscsi", - .version_id = 1, + .version_id = 2, .minimum_version_id = 1, .fields = (VMStateField[]) { + VMSTATE_UINT8_V(esp.mig_version_id, SysBusESPState, 2), VMSTATE_STRUCT(esp, SysBusESPState, 0, vmstate_esp, ESPState), VMSTATE_END_OF_LIST() } diff --git a/include/hw/scsi/esp.h b/include/hw/scsi/esp.h index af23f813cb..9d149cbc9f 100644 --- a/include/hw/scsi/esp.h +++ b/include/hw/scsi/esp.h @@ -68,6 +68,8 @@ struct ESPState { uint32_t pdma_start; uint32_t pdma_cur; void (*pdma_cb)(ESPState *s); + + uint8_t mig_version_id; }; #define TYPE_SYSBUS_ESP "sysbus-esp" From patchwork Sun Mar 7 12:08:13 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Mark Cave-Ayland X-Patchwork-Id: 1448646 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4DtgfS0Xf3z9sWP for ; Sun, 7 Mar 2021 23:25:20 +1100 (AEDT) Received: from localhost ([::1]:41770 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lIsTG-0006Vr-40 for incoming@patchwork.ozlabs.org; Sun, 07 Mar 2021 07:25:18 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:41258) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lIsE4-0000RZ-6J for qemu-devel@nongnu.org; Sun, 07 Mar 2021 07:09:36 -0500 Received: from mail.ilande.co.uk ([2001:41c9:1:41f::167]:43578 helo=mail.default.ilande.uk0.bigv.io) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lIsE2-0007Yn-PZ for qemu-devel@nongnu.org; Sun, 07 Mar 2021 07:09:35 -0500 Received: from host86-148-34-47.range86-148.btcentralplus.com ([86.148.34.47] helo=kentang.home) by mail.default.ilande.uk0.bigv.io with esmtpsa (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1lIsDx-0002V5-Gf; Sun, 07 Mar 2021 12:09:34 +0000 From: Mark Cave-Ayland To: qemu-devel@nongnu.org, peter.maydell@linaro.org Date: Sun, 7 Mar 2021 12:08:13 +0000 Message-Id: <20210307120850.10418-6-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210307120850.10418-1-mark.cave-ayland@ilande.co.uk> References: <20210307120850.10418-1-mark.cave-ayland@ilande.co.uk> MIME-Version: 1.0 X-SA-Exim-Connect-IP: 86.148.34.47 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk Subject: [PULL 05/42] esp: add trace event when receiving a TI command X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on mail.default.ilande.uk0.bigv.io) Received-SPF: pass client-ip=2001:41c9:1:41f::167; envelope-from=mark.cave-ayland@ilande.co.uk; helo=mail.default.ilande.uk0.bigv.io X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" This enables us to determine whether the command being issued is for a DMA or a non-DMA transfer. Signed-off-by: Mark Cave-Ayland Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Laurent Vivier Message-Id: <20210304221103.6369-6-mark.cave-ayland@ilande.co.uk> --- hw/scsi/esp.c | 1 + hw/scsi/trace-events | 1 + 2 files changed, 2 insertions(+) diff --git a/hw/scsi/esp.c b/hw/scsi/esp.c index f65c675872..73700550f2 100644 --- a/hw/scsi/esp.c +++ b/hw/scsi/esp.c @@ -697,6 +697,7 @@ void esp_reg_write(ESPState *s, uint32_t saddr, uint64_t val) } break; case CMD_TI: + trace_esp_mem_writeb_cmd_ti(val); handle_ti(s); break; case CMD_ICCS: diff --git a/hw/scsi/trace-events b/hw/scsi/trace-events index 9788661bfd..6269547266 100644 --- a/hw/scsi/trace-events +++ b/hw/scsi/trace-events @@ -189,6 +189,7 @@ esp_mem_writeb_cmd_selatn(uint32_t val) "Select with ATN (0x%2.2x)" esp_mem_writeb_cmd_selatns(uint32_t val) "Select with ATN & stop (0x%2.2x)" esp_mem_writeb_cmd_ensel(uint32_t val) "Enable selection (0x%2.2x)" esp_mem_writeb_cmd_dissel(uint32_t val) "Disable selection (0x%2.2x)" +esp_mem_writeb_cmd_ti(uint32_t val) "Transfer Information (0x%2.2x)" # esp-pci.c esp_pci_error_invalid_dma_direction(void) "invalid DMA transfer direction" From patchwork Sun Mar 7 12:08:14 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Mark Cave-Ayland X-Patchwork-Id: 1448650 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4Dtglc2z6vz9sWP for ; Sun, 7 Mar 2021 23:29:48 +1100 (AEDT) Received: from localhost ([::1]:50420 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lIsXa-0001pn-Di for incoming@patchwork.ozlabs.org; Sun, 07 Mar 2021 07:29:46 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:41318) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lIsEA-0000au-Gs for qemu-devel@nongnu.org; Sun, 07 Mar 2021 07:09:42 -0500 Received: from mail.ilande.co.uk ([2001:41c9:1:41f::167]:43584 helo=mail.default.ilande.uk0.bigv.io) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lIsE8-0007aX-Uz for qemu-devel@nongnu.org; Sun, 07 Mar 2021 07:09:42 -0500 Received: from host86-148-34-47.range86-148.btcentralplus.com ([86.148.34.47] helo=kentang.home) by mail.default.ilande.uk0.bigv.io with esmtpsa (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1lIsE2-0002V5-Df; Sun, 07 Mar 2021 12:09:40 +0000 From: Mark Cave-Ayland To: qemu-devel@nongnu.org, peter.maydell@linaro.org Date: Sun, 7 Mar 2021 12:08:14 +0000 Message-Id: <20210307120850.10418-7-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210307120850.10418-1-mark.cave-ayland@ilande.co.uk> References: <20210307120850.10418-1-mark.cave-ayland@ilande.co.uk> MIME-Version: 1.0 X-SA-Exim-Connect-IP: 86.148.34.47 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk Subject: [PULL 06/42] esp: fix esp_reg_read() trace event X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on mail.default.ilande.uk0.bigv.io) Received-SPF: pass client-ip=2001:41c9:1:41f::167; envelope-from=mark.cave-ayland@ilande.co.uk; helo=mail.default.ilande.uk0.bigv.io X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Move the trace event to the end of the function so that it correctly reports the returned value if it doesn't come directly from the rregs array. Signed-off-by: Mark Cave-Ayland Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Laurent Vivier Message-Id: <20210304221103.6369-7-mark.cave-ayland@ilande.co.uk> --- hw/scsi/esp.c | 18 ++++++++++++------ 1 file changed, 12 insertions(+), 6 deletions(-) diff --git a/hw/scsi/esp.c b/hw/scsi/esp.c index 73700550f2..16c1853577 100644 --- a/hw/scsi/esp.c +++ b/hw/scsi/esp.c @@ -594,9 +594,8 @@ static void parent_esp_reset(ESPState *s, int irq, int level) uint64_t esp_reg_read(ESPState *s, uint32_t saddr) { - uint32_t old_val; + uint32_t val; - trace_esp_mem_readb(saddr, s->rregs[saddr]); switch (saddr) { case ESP_FIFO: if ((s->rregs[ESP_RSTAT] & STAT_PIO_MASK) == 0) { @@ -611,13 +610,14 @@ uint64_t esp_reg_read(ESPState *s, uint32_t saddr) s->ti_rptr = 0; s->ti_wptr = 0; } + val = s->rregs[ESP_FIFO]; break; case ESP_RINTR: /* * Clear sequence step, interrupt register and all status bits * except TC */ - old_val = s->rregs[ESP_RINTR]; + val = s->rregs[ESP_RINTR]; s->rregs[ESP_RINTR] = 0; s->rregs[ESP_RSTAT] &= ~STAT_TC; s->rregs[ESP_RSEQ] = SEQ_CD; @@ -626,16 +626,22 @@ uint64_t esp_reg_read(ESPState *s, uint32_t saddr) esp_report_command_complete(s, s->deferred_status); s->deferred_complete = false; } - return old_val; + break; case ESP_TCHI: /* Return the unique id if the value has never been written */ if (!s->tchi_written) { - return s->chip_id; + val = s->chip_id; + } else { + val = s->rregs[saddr]; } + break; default: + val = s->rregs[saddr]; break; } - return s->rregs[saddr]; + + trace_esp_mem_readb(saddr, val); + return val; } void esp_reg_write(ESPState *s, uint32_t saddr, uint64_t val) From patchwork Sun Mar 7 12:08:15 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Mark Cave-Ayland X-Patchwork-Id: 1448632 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4DtgNH5YFjz9sCD for ; Sun, 7 Mar 2021 23:13:03 +1100 (AEDT) Received: from localhost ([::1]:43448 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lIsHN-0003V2-Ky for incoming@patchwork.ozlabs.org; Sun, 07 Mar 2021 07:13:01 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:41360) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lIsEL-0000dW-6N for qemu-devel@nongnu.org; Sun, 07 Mar 2021 07:09:54 -0500 Received: from mail.ilande.co.uk ([2001:41c9:1:41f::167]:43592 helo=mail.default.ilande.uk0.bigv.io) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lIsED-0007bQ-TQ for qemu-devel@nongnu.org; Sun, 07 Mar 2021 07:09:52 -0500 Received: from host86-148-34-47.range86-148.btcentralplus.com ([86.148.34.47] helo=kentang.home) by mail.default.ilande.uk0.bigv.io with esmtpsa (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1lIsE8-0002V5-P4; Sun, 07 Mar 2021 12:09:45 +0000 From: Mark Cave-Ayland To: qemu-devel@nongnu.org, peter.maydell@linaro.org Date: Sun, 7 Mar 2021 12:08:15 +0000 Message-Id: <20210307120850.10418-8-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210307120850.10418-1-mark.cave-ayland@ilande.co.uk> References: <20210307120850.10418-1-mark.cave-ayland@ilande.co.uk> MIME-Version: 1.0 X-SA-Exim-Connect-IP: 86.148.34.47 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk Subject: [PULL 07/42] esp: add PDMA trace events X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on mail.default.ilande.uk0.bigv.io) Received-SPF: pass client-ip=2001:41c9:1:41f::167; envelope-from=mark.cave-ayland@ilande.co.uk; helo=mail.default.ilande.uk0.bigv.io X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" This will become more useful later when trying to debug mixed FIFO and PDMA requests. Signed-off-by: Mark Cave-Ayland Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Laurent Vivier Message-Id: <20210304221103.6369-8-mark.cave-ayland@ilande.co.uk> --- hw/scsi/esp.c | 6 ++++++ hw/scsi/trace-events | 4 ++++ 2 files changed, 10 insertions(+) diff --git a/hw/scsi/esp.c b/hw/scsi/esp.c index 16c1853577..e0676ae790 100644 --- a/hw/scsi/esp.c +++ b/hw/scsi/esp.c @@ -63,11 +63,13 @@ static void esp_lower_irq(ESPState *s) static void esp_raise_drq(ESPState *s) { qemu_irq_raise(s->irq_data); + trace_esp_raise_drq(); } static void esp_lower_drq(ESPState *s) { qemu_irq_lower(s->irq_data); + trace_esp_lower_drq(); } void esp_dma_enable(ESPState *s, int irq, int level) @@ -885,6 +887,8 @@ static void sysbus_esp_pdma_write(void *opaque, hwaddr addr, uint32_t dmalen; uint8_t *buf = get_pdma_buf(s); + trace_esp_pdma_write(size); + dmalen = s->rregs[ESP_TCLO]; dmalen |= s->rregs[ESP_TCMID] << 8; dmalen |= s->rregs[ESP_TCHI] << 16; @@ -922,6 +926,8 @@ static uint64_t sysbus_esp_pdma_read(void *opaque, hwaddr addr, uint8_t *buf = get_pdma_buf(s); uint64_t val = 0; + trace_esp_pdma_read(size); + if (s->pdma_len == 0) { return 0; } diff --git a/hw/scsi/trace-events b/hw/scsi/trace-events index 6269547266..1c331fb189 100644 --- a/hw/scsi/trace-events +++ b/hw/scsi/trace-events @@ -159,8 +159,12 @@ esp_error_unhandled_command(uint32_t val) "unhandled command (0x%2.2x)" esp_error_invalid_write(uint32_t val, uint32_t addr) "invalid write of 0x%02x at [0x%x]" esp_raise_irq(void) "Raise IRQ" esp_lower_irq(void) "Lower IRQ" +esp_raise_drq(void) "Raise DREQ" +esp_lower_drq(void) "Lower DREQ" esp_dma_enable(void) "Raise enable" esp_dma_disable(void) "Lower enable" +esp_pdma_read(int size) "pDMA read %u bytes" +esp_pdma_write(int size) "pDMA write %u bytes" esp_get_cmd(uint32_t dmalen, int target) "len %d target %d" esp_do_busid_cmd(uint8_t busid) "busid 0x%x" esp_handle_satn_stop(uint32_t cmdlen) "cmdlen %d" From patchwork Sun Mar 7 12:08:16 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Mark Cave-Ayland X-Patchwork-Id: 1448653 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4Dtgr12P0Mz9sWP for ; Sun, 7 Mar 2021 23:33:37 +1100 (AEDT) Received: from localhost ([::1]:58832 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lIsbH-0005RQ-2A for incoming@patchwork.ozlabs.org; Sun, 07 Mar 2021 07:33:35 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:41378) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lIsEM-0000e4-UX for qemu-devel@nongnu.org; Sun, 07 Mar 2021 07:09:56 -0500 Received: from mail.ilande.co.uk ([2001:41c9:1:41f::167]:43596 helo=mail.default.ilande.uk0.bigv.io) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lIsEK-0007c9-Qt for qemu-devel@nongnu.org; Sun, 07 Mar 2021 07:09:54 -0500 Received: from host86-148-34-47.range86-148.btcentralplus.com ([86.148.34.47] helo=kentang.home) by mail.default.ilande.uk0.bigv.io with esmtpsa (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1lIsED-0002V5-La; Sun, 07 Mar 2021 12:09:50 +0000 From: Mark Cave-Ayland To: qemu-devel@nongnu.org, peter.maydell@linaro.org Date: Sun, 7 Mar 2021 12:08:16 +0000 Message-Id: <20210307120850.10418-9-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210307120850.10418-1-mark.cave-ayland@ilande.co.uk> References: <20210307120850.10418-1-mark.cave-ayland@ilande.co.uk> MIME-Version: 1.0 X-SA-Exim-Connect-IP: 86.148.34.47 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk Subject: [PULL 08/42] esp: determine transfer direction directly from SCSI phase X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on mail.default.ilande.uk0.bigv.io) Received-SPF: pass client-ip=2001:41c9:1:41f::167; envelope-from=mark.cave-ayland@ilande.co.uk; helo=mail.default.ilande.uk0.bigv.io X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" The transfer direction is currently determined by checking the sign of ti_size but as this series progresses ti_size can be zero at the end of the transfer. Use the SCSI phase to determine the transfer direction as used in other SCSI controller implementations. Signed-off-by: Mark Cave-Ayland Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Laurent Vivier Message-Id: <20210304221103.6369-9-mark.cave-ayland@ilande.co.uk> --- hw/scsi/esp.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/hw/scsi/esp.c b/hw/scsi/esp.c index e0676ae790..5365523f6b 100644 --- a/hw/scsi/esp.c +++ b/hw/scsi/esp.c @@ -356,7 +356,7 @@ static void esp_dma_done(ESPState *s) static void do_dma_pdma_cb(ESPState *s) { - int to_device = (s->ti_size < 0); + int to_device = ((s->rregs[ESP_RSTAT] & 7) == STAT_DO); int len = s->pdma_cur - s->pdma_start; if (s->do_cmd) { s->ti_size = 0; @@ -392,7 +392,7 @@ static void do_dma_pdma_cb(ESPState *s) static void esp_do_dma(ESPState *s) { uint32_t len; - int to_device; + int to_device = ((s->rregs[ESP_RSTAT] & 7) == STAT_DO); len = s->dma_left; if (s->do_cmd) { @@ -425,7 +425,6 @@ static void esp_do_dma(ESPState *s) if (len > s->async_len) { len = s->async_len; } - to_device = (s->ti_size < 0); if (to_device) { if (s->dma_memory_read) { s->dma_memory_read(s->dma_opaque, s->async_buf, len); From patchwork Sun Mar 7 12:08:17 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Mark Cave-Ayland X-Patchwork-Id: 1448636 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4DtgSY1lhlz9sWg for ; Sun, 7 Mar 2021 23:16:44 +1100 (AEDT) Received: from localhost ([::1]:52010 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lIsKw-0007Mv-5P for incoming@patchwork.ozlabs.org; Sun, 07 Mar 2021 07:16:42 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:41396) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lIsEP-0000iL-Mt for qemu-devel@nongnu.org; Sun, 07 Mar 2021 07:09:57 -0500 Received: from mail.ilande.co.uk ([2001:41c9:1:41f::167]:43602 helo=mail.default.ilande.uk0.bigv.io) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lIsEN-0007cx-Vy for qemu-devel@nongnu.org; Sun, 07 Mar 2021 07:09:57 -0500 Received: from host86-148-34-47.range86-148.btcentralplus.com ([86.148.34.47] helo=kentang.home) by mail.default.ilande.uk0.bigv.io with esmtpsa (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1lIsEI-0002V5-U2; Sun, 07 Mar 2021 12:09:55 +0000 From: Mark Cave-Ayland To: qemu-devel@nongnu.org, peter.maydell@linaro.org Date: Sun, 7 Mar 2021 12:08:17 +0000 Message-Id: <20210307120850.10418-10-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210307120850.10418-1-mark.cave-ayland@ilande.co.uk> References: <20210307120850.10418-1-mark.cave-ayland@ilande.co.uk> MIME-Version: 1.0 X-SA-Exim-Connect-IP: 86.148.34.47 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk Subject: [PULL 09/42] esp: introduce esp_get_tc() and esp_set_tc() X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on mail.default.ilande.uk0.bigv.io) Received-SPF: pass client-ip=2001:41c9:1:41f::167; envelope-from=mark.cave-ayland@ilande.co.uk; helo=mail.default.ilande.uk0.bigv.io X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" These functions simplify reading and writing the TC register value without having to manually shift each individual 8-bit value. Signed-off-by: Mark Cave-Ayland Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Laurent Vivier Message-Id: <20210304221103.6369-10-mark.cave-ayland@ilande.co.uk> --- hw/scsi/esp.c | 38 +++++++++++++++++++++++--------------- 1 file changed, 23 insertions(+), 15 deletions(-) diff --git a/hw/scsi/esp.c b/hw/scsi/esp.c index 5365523f6b..dd94f7b47b 100644 --- a/hw/scsi/esp.c +++ b/hw/scsi/esp.c @@ -98,6 +98,24 @@ void esp_request_cancelled(SCSIRequest *req) } } +static uint32_t esp_get_tc(ESPState *s) +{ + uint32_t dmalen; + + dmalen = s->rregs[ESP_TCLO]; + dmalen |= s->rregs[ESP_TCMID] << 8; + dmalen |= s->rregs[ESP_TCHI] << 16; + + return dmalen; +} + +static void esp_set_tc(ESPState *s, uint32_t dmalen) +{ + s->rregs[ESP_TCLO] = dmalen; + s->rregs[ESP_TCMID] = dmalen >> 8; + s->rregs[ESP_TCHI] = dmalen >> 16; +} + static void set_pdma(ESPState *s, enum pdma_origin_id origin, uint32_t index, uint32_t len) { @@ -157,9 +175,7 @@ static uint32_t get_cmd(ESPState *s, uint8_t *buf, uint8_t buflen) target = s->wregs[ESP_WBUSID] & BUSID_DID; if (s->dma) { - dmalen = s->rregs[ESP_TCLO]; - dmalen |= s->rregs[ESP_TCMID] << 8; - dmalen |= s->rregs[ESP_TCHI] << 16; + dmalen = esp_get_tc(s); if (dmalen > buflen) { return 0; } @@ -348,9 +364,7 @@ static void esp_dma_done(ESPState *s) s->rregs[ESP_RINTR] = INTR_BS; s->rregs[ESP_RSEQ] = 0; s->rregs[ESP_RFLAGS] = 0; - s->rregs[ESP_TCLO] = 0; - s->rregs[ESP_TCMID] = 0; - s->rregs[ESP_TCHI] = 0; + esp_set_tc(s, 0); esp_raise_irq(s); } @@ -535,9 +549,7 @@ static void handle_ti(ESPState *s) return; } - dmalen = s->rregs[ESP_TCLO]; - dmalen |= s->rregs[ESP_TCMID] << 8; - dmalen |= s->rregs[ESP_TCHI] << 16; + dmalen = esp_get_tc(s); if (dmalen == 0) { dmalen = 0x10000; } @@ -888,9 +900,7 @@ static void sysbus_esp_pdma_write(void *opaque, hwaddr addr, trace_esp_pdma_write(size); - dmalen = s->rregs[ESP_TCLO]; - dmalen |= s->rregs[ESP_TCMID] << 8; - dmalen |= s->rregs[ESP_TCHI] << 16; + dmalen = esp_get_tc(s); if (dmalen == 0 || s->pdma_len == 0) { return; } @@ -907,9 +917,7 @@ static void sysbus_esp_pdma_write(void *opaque, hwaddr addr, dmalen -= 2; break; } - s->rregs[ESP_TCLO] = dmalen & 0xff; - s->rregs[ESP_TCMID] = dmalen >> 8; - s->rregs[ESP_TCHI] = dmalen >> 16; + esp_set_tc(s, dmalen); if (s->pdma_len == 0 && s->pdma_cb) { esp_lower_drq(s); s->pdma_cb(s); From patchwork Sun Mar 7 12:08:18 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Mark Cave-Ayland X-Patchwork-Id: 1448633 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4DtgNK17Scz9sWb for ; Sun, 7 Mar 2021 23:13:05 +1100 (AEDT) Received: from localhost ([::1]:43574 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lIsHP-0003Y7-4b for incoming@patchwork.ozlabs.org; Sun, 07 Mar 2021 07:13:03 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:41420) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lIsEU-0000pI-K2 for qemu-devel@nongnu.org; Sun, 07 Mar 2021 07:10:06 -0500 Received: from mail.ilande.co.uk ([2001:41c9:1:41f::167]:43608 helo=mail.default.ilande.uk0.bigv.io) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lIsES-0007ev-Qs for qemu-devel@nongnu.org; Sun, 07 Mar 2021 07:10:02 -0500 Received: from host86-148-34-47.range86-148.btcentralplus.com ([86.148.34.47] helo=kentang.home) by mail.default.ilande.uk0.bigv.io with esmtpsa (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1lIsEN-0002V5-On; Sun, 07 Mar 2021 12:10:00 +0000 From: Mark Cave-Ayland To: qemu-devel@nongnu.org, peter.maydell@linaro.org Date: Sun, 7 Mar 2021 12:08:18 +0000 Message-Id: <20210307120850.10418-11-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210307120850.10418-1-mark.cave-ayland@ilande.co.uk> References: <20210307120850.10418-1-mark.cave-ayland@ilande.co.uk> MIME-Version: 1.0 X-SA-Exim-Connect-IP: 86.148.34.47 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk Subject: [PULL 10/42] esp: introduce esp_get_stc() X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on mail.default.ilande.uk0.bigv.io) Received-SPF: pass client-ip=2001:41c9:1:41f::167; envelope-from=mark.cave-ayland@ilande.co.uk; helo=mail.default.ilande.uk0.bigv.io X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" This function simplifies reading the STC register value without having to manually shift each individual 8-bit value. Signed-off-by: Mark Cave-Ayland Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Laurent Vivier Message-Id: <20210304221103.6369-11-mark.cave-ayland@ilande.co.uk> --- hw/scsi/esp.c | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-) diff --git a/hw/scsi/esp.c b/hw/scsi/esp.c index dd94f7b47b..125bdea32a 100644 --- a/hw/scsi/esp.c +++ b/hw/scsi/esp.c @@ -116,6 +116,17 @@ static void esp_set_tc(ESPState *s, uint32_t dmalen) s->rregs[ESP_TCHI] = dmalen >> 16; } +static uint32_t esp_get_stc(ESPState *s) +{ + uint32_t dmalen; + + dmalen = s->wregs[ESP_TCLO]; + dmalen |= s->wregs[ESP_TCMID] << 8; + dmalen |= s->wregs[ESP_TCHI] << 16; + + return dmalen; +} + static void set_pdma(ESPState *s, enum pdma_origin_id origin, uint32_t index, uint32_t len) { @@ -687,9 +698,7 @@ void esp_reg_write(ESPState *s, uint32_t saddr, uint64_t val) if (val & CMD_DMA) { s->dma = 1; /* Reload DMA counter. */ - s->rregs[ESP_TCLO] = s->wregs[ESP_TCLO]; - s->rregs[ESP_TCMID] = s->wregs[ESP_TCMID]; - s->rregs[ESP_TCHI] = s->wregs[ESP_TCHI]; + esp_set_tc(s, esp_get_stc(s)); } else { s->dma = 0; } From patchwork Sun Mar 7 12:08:19 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Cave-Ayland X-Patchwork-Id: 1448635 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4DtgNh65bMz9sCD for ; Sun, 7 Mar 2021 23:13:24 +1100 (AEDT) Received: from localhost ([::1]:45406 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lIsHi-0004KD-Qm for incoming@patchwork.ozlabs.org; Sun, 07 Mar 2021 07:13:22 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:41444) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lIsEa-0000sd-8y for qemu-devel@nongnu.org; Sun, 07 Mar 2021 07:10:08 -0500 Received: from mail.ilande.co.uk ([2001:41c9:1:41f::167]:43616 helo=mail.default.ilande.uk0.bigv.io) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lIsEY-0007fo-PB for qemu-devel@nongnu.org; Sun, 07 Mar 2021 07:10:08 -0500 Received: from host86-148-34-47.range86-148.btcentralplus.com ([86.148.34.47] helo=kentang.home) by mail.default.ilande.uk0.bigv.io with esmtpsa (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1lIsES-0002V5-MD; Sun, 07 Mar 2021 12:10:05 +0000 From: Mark Cave-Ayland To: qemu-devel@nongnu.org, peter.maydell@linaro.org Date: Sun, 7 Mar 2021 12:08:19 +0000 Message-Id: <20210307120850.10418-12-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210307120850.10418-1-mark.cave-ayland@ilande.co.uk> References: <20210307120850.10418-1-mark.cave-ayland@ilande.co.uk> MIME-Version: 1.0 X-SA-Exim-Connect-IP: 86.148.34.47 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk Subject: [PULL 11/42] esp: apply transfer length adjustment when STC is zero at TC load time X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on mail.default.ilande.uk0.bigv.io) Received-SPF: pass client-ip=2001:41c9:1:41f::167; envelope-from=mark.cave-ayland@ilande.co.uk; helo=mail.default.ilande.uk0.bigv.io X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Perform the length adjustment whereby a value of 0 in the STC represents a transfer length of 0x10000 at the point where the TC is loaded at the start of a DMA command rather than just when a TI (Transfer Information) command is executed. This better matches the description as given in the datasheet. Signed-off-by: Mark Cave-Ayland Reviewed-by: Laurent Vivier Message-Id: <20210304221103.6369-12-mark.cave-ayland@ilande.co.uk> --- hw/scsi/esp.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/hw/scsi/esp.c b/hw/scsi/esp.c index 125bdea32a..349067eb6a 100644 --- a/hw/scsi/esp.c +++ b/hw/scsi/esp.c @@ -561,9 +561,6 @@ static void handle_ti(ESPState *s) } dmalen = esp_get_tc(s); - if (dmalen == 0) { - dmalen = 0x10000; - } s->dma_counter = dmalen; if (s->do_cmd) { @@ -698,7 +695,11 @@ void esp_reg_write(ESPState *s, uint32_t saddr, uint64_t val) if (val & CMD_DMA) { s->dma = 1; /* Reload DMA counter. */ - esp_set_tc(s, esp_get_stc(s)); + if (esp_get_stc(s) == 0) { + esp_set_tc(s, 0x10000); + } else { + esp_set_tc(s, esp_get_stc(s)); + } } else { s->dma = 0; } From patchwork Sun Mar 7 12:08:20 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Mark Cave-Ayland X-Patchwork-Id: 1448640 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4DtgYs6ndWz9sRf for ; Sun, 7 Mar 2021 23:21:21 +1100 (AEDT) Received: from localhost ([::1]:60460 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lIsPP-0002QZ-Tu for incoming@patchwork.ozlabs.org; Sun, 07 Mar 2021 07:21:19 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:41472) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lIsEe-00011r-KM for qemu-devel@nongnu.org; Sun, 07 Mar 2021 07:10:14 -0500 Received: from mail.ilande.co.uk ([2001:41c9:1:41f::167]:43620 helo=mail.default.ilande.uk0.bigv.io) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lIsEc-0007ga-VC for qemu-devel@nongnu.org; Sun, 07 Mar 2021 07:10:12 -0500 Received: from host86-148-34-47.range86-148.btcentralplus.com ([86.148.34.47] helo=kentang.home) by mail.default.ilande.uk0.bigv.io with esmtpsa (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1lIsEX-0002V5-Hp; Sun, 07 Mar 2021 12:10:10 +0000 From: Mark Cave-Ayland To: qemu-devel@nongnu.org, peter.maydell@linaro.org Date: Sun, 7 Mar 2021 12:08:20 +0000 Message-Id: <20210307120850.10418-13-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210307120850.10418-1-mark.cave-ayland@ilande.co.uk> References: <20210307120850.10418-1-mark.cave-ayland@ilande.co.uk> MIME-Version: 1.0 X-SA-Exim-Connect-IP: 86.148.34.47 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk Subject: [PULL 12/42] esp: remove dma_counter from ESPState X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on mail.default.ilande.uk0.bigv.io) Received-SPF: pass client-ip=2001:41c9:1:41f::167; envelope-from=mark.cave-ayland@ilande.co.uk; helo=mail.default.ilande.uk0.bigv.io X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" The value of dma_counter is set once at the start of the transfer and remains the same until the transfer is complete. This allows the check in esp_transfer_data to be simplified since dma_left will always be non-zero until the transfer is completed. Signed-off-by: Mark Cave-Ayland Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Laurent Vivier Message-Id: <20210304221103.6369-13-mark.cave-ayland@ilande.co.uk> --- hw/scsi/esp.c | 4 +--- include/hw/scsi/esp.h | 3 --- 2 files changed, 1 insertion(+), 6 deletions(-) diff --git a/hw/scsi/esp.c b/hw/scsi/esp.c index 349067eb6a..15c4c33052 100644 --- a/hw/scsi/esp.c +++ b/hw/scsi/esp.c @@ -229,7 +229,6 @@ static void do_busid_cmd(ESPState *s, uint8_t *buf, uint8_t busid) if (datalen != 0) { s->rregs[ESP_RSTAT] = STAT_TC; s->dma_left = 0; - s->dma_counter = 0; if (datalen > 0) { s->rregs[ESP_RSTAT] |= STAT_DI; } else { @@ -542,7 +541,7 @@ void esp_transfer_data(SCSIRequest *req, uint32_t len) s->async_buf = scsi_req_get_buf(req); if (s->dma_left) { esp_do_dma(s); - } else if (s->dma_counter != 0 && s->ti_size <= 0) { + } else if (s->ti_size <= 0) { /* * If this was the last part of a DMA transfer then the * completion interrupt is deferred to here. @@ -561,7 +560,6 @@ static void handle_ti(ESPState *s) } dmalen = esp_get_tc(s); - s->dma_counter = dmalen; if (s->do_cmd) { minlen = (dmalen < ESP_CMDBUF_SZ) ? dmalen : ESP_CMDBUF_SZ; diff --git a/include/hw/scsi/esp.h b/include/hw/scsi/esp.h index 9d149cbc9f..ff1372947b 100644 --- a/include/hw/scsi/esp.h +++ b/include/hw/scsi/esp.h @@ -50,9 +50,6 @@ struct ESPState { /* The amount of data left in the current DMA transfer. */ uint32_t dma_left; - /* The size of the current DMA transfer. Zero if no transfer is in - progress. */ - uint32_t dma_counter; int dma_enabled; uint32_t async_len; From patchwork Sun Mar 7 12:08:21 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Mark Cave-Ayland X-Patchwork-Id: 1448637 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4DtgSY2J0Qz9sWk for ; Sun, 7 Mar 2021 23:16:44 +1100 (AEDT) Received: from localhost ([::1]:52108 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lIsKw-0007P3-UB for incoming@patchwork.ozlabs.org; Sun, 07 Mar 2021 07:16:42 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:41484) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lIsEi-00013X-Hv for qemu-devel@nongnu.org; Sun, 07 Mar 2021 07:10:17 -0500 Received: from mail.ilande.co.uk ([2001:41c9:1:41f::167]:43628 helo=mail.default.ilande.uk0.bigv.io) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lIsEg-0007hf-Fi for qemu-devel@nongnu.org; Sun, 07 Mar 2021 07:10:16 -0500 Received: from host86-148-34-47.range86-148.btcentralplus.com ([86.148.34.47] helo=kentang.home) by mail.default.ilande.uk0.bigv.io with esmtpsa (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1lIsEc-0002V5-Mw; Sun, 07 Mar 2021 12:10:14 +0000 From: Mark Cave-Ayland To: qemu-devel@nongnu.org, peter.maydell@linaro.org Date: Sun, 7 Mar 2021 12:08:21 +0000 Message-Id: <20210307120850.10418-14-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210307120850.10418-1-mark.cave-ayland@ilande.co.uk> References: <20210307120850.10418-1-mark.cave-ayland@ilande.co.uk> MIME-Version: 1.0 X-SA-Exim-Connect-IP: 86.148.34.47 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk Subject: [PULL 13/42] esp: remove dma_left from ESPState X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on mail.default.ilande.uk0.bigv.io) Received-SPF: pass client-ip=2001:41c9:1:41f::167; envelope-from=mark.cave-ayland@ilande.co.uk; helo=mail.default.ilande.uk0.bigv.io X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" The ESP device already keeps track of the remaining bytes left to transfer via its TC (transfer counter) register which is decremented for each byte that is transferred across the SCSI bus. Switch the transfer logic to use the value of TC instead of dma_left and then remove dma_left completely, adding logic to the vmstate_esp post_load() function to transfer the old dma_left value to the TC register during migration from older versions. Signed-off-by: Mark Cave-Ayland Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Laurent Vivier Message-Id: <20210304221103.6369-14-mark.cave-ayland@ilande.co.uk> --- hw/scsi/esp.c | 47 ++++++++++++++++++++++++++++--------------- include/hw/scsi/esp.h | 5 +++-- 2 files changed, 34 insertions(+), 18 deletions(-) diff --git a/hw/scsi/esp.c b/hw/scsi/esp.c index 15c4c33052..92fea6a8c4 100644 --- a/hw/scsi/esp.c +++ b/hw/scsi/esp.c @@ -228,7 +228,7 @@ static void do_busid_cmd(ESPState *s, uint8_t *buf, uint8_t busid) s->ti_size = datalen; if (datalen != 0) { s->rregs[ESP_RSTAT] = STAT_TC; - s->dma_left = 0; + esp_set_tc(s, 0); if (datalen > 0) { s->rregs[ESP_RSTAT] |= STAT_DI; } else { @@ -382,6 +382,7 @@ static void do_dma_pdma_cb(ESPState *s) { int to_device = ((s->rregs[ESP_RSTAT] & 7) == STAT_DO); int len = s->pdma_cur - s->pdma_start; + if (s->do_cmd) { s->ti_size = 0; s->cmdlen = 0; @@ -389,7 +390,6 @@ static void do_dma_pdma_cb(ESPState *s) do_cmd(s, s->cmdbuf); return; } - s->dma_left -= len; s->async_buf += len; s->async_len -= len; if (to_device) { @@ -404,7 +404,7 @@ static void do_dma_pdma_cb(ESPState *s) * complete the DMA operation immediately. Otherwise defer * until the scsi layer has completed. */ - if (to_device || s->dma_left != 0 || s->ti_size == 0) { + if (to_device || esp_get_tc(s) != 0 || s->ti_size == 0) { return; } } @@ -418,7 +418,7 @@ static void esp_do_dma(ESPState *s) uint32_t len; int to_device = ((s->rregs[ESP_RSTAT] & 7) == STAT_DO); - len = s->dma_left; + len = esp_get_tc(s); if (s->do_cmd) { /* * handle_ti_cmd() case: esp_do_dma() is called only from @@ -468,7 +468,7 @@ static void esp_do_dma(ESPState *s) return; } } - s->dma_left -= len; + esp_set_tc(s, esp_get_tc(s) - len); s->async_buf += len; s->async_len -= len; if (to_device) { @@ -483,7 +483,7 @@ static void esp_do_dma(ESPState *s) * complete the DMA operation immediately. Otherwise defer * until the scsi layer has completed. */ - if (to_device || s->dma_left != 0 || s->ti_size == 0) { + if (to_device || esp_get_tc(s) != 0 || s->ti_size == 0) { return; } } @@ -499,7 +499,6 @@ static void esp_report_command_complete(ESPState *s, uint32_t status) trace_esp_command_complete_unexpected(); } s->ti_size = 0; - s->dma_left = 0; s->async_len = 0; if (status) { trace_esp_command_complete_fail(); @@ -534,12 +533,13 @@ void esp_command_complete(SCSIRequest *req, size_t resid) void esp_transfer_data(SCSIRequest *req, uint32_t len) { ESPState *s = req->hba_private; + uint32_t dmalen = esp_get_tc(s); assert(!s->do_cmd); - trace_esp_transfer_data(s->dma_left, s->ti_size); + trace_esp_transfer_data(dmalen, s->ti_size); s->async_len = len; s->async_buf = scsi_req_get_buf(req); - if (s->dma_left) { + if (dmalen) { esp_do_dma(s); } else if (s->ti_size <= 0) { /* @@ -570,7 +570,6 @@ static void handle_ti(ESPState *s) } trace_esp_handle_ti(minlen); if (s->dma) { - s->dma_left = minlen; s->rregs[ESP_RSTAT] &= ~STAT_TC; esp_do_dma(s); } else if (s->do_cmd) { @@ -823,6 +822,14 @@ static const VMStateDescription vmstate_esp_pdma = { } }; +static bool esp_is_before_version_5(void *opaque, int version_id) +{ + ESPState *s = ESP(opaque); + + version_id = MIN(version_id, s->mig_version_id); + return version_id < 5; +} + static int esp_pre_save(void *opaque) { ESPState *s = ESP(opaque); @@ -835,6 +842,12 @@ static int esp_post_load(void *opaque, int version_id) { ESPState *s = ESP(opaque); + version_id = MIN(version_id, s->mig_version_id); + + if (version_id < 5) { + esp_set_tc(s, s->mig_dma_left); + } + s->mig_version_id = vmstate_esp.version_id; return 0; } @@ -860,7 +873,7 @@ const VMStateDescription vmstate_esp = { VMSTATE_BUFFER_START_MIDDLE_V(cmdbuf, ESPState, 16, 4), VMSTATE_UINT32(cmdlen, ESPState), VMSTATE_UINT32(do_cmd, ESPState), - VMSTATE_UINT32(dma_left, ESPState), + VMSTATE_UINT32_TEST(mig_dma_left, ESPState, esp_is_before_version_5), VMSTATE_END_OF_LIST() }, .subsections = (const VMStateDescription * []) { @@ -903,12 +916,11 @@ static void sysbus_esp_pdma_write(void *opaque, hwaddr addr, { SysBusESPState *sysbus = opaque; ESPState *s = ESP(&sysbus->esp); - uint32_t dmalen; + uint32_t dmalen = esp_get_tc(s); uint8_t *buf = get_pdma_buf(s); trace_esp_pdma_write(size); - dmalen = esp_get_tc(s); if (dmalen == 0 || s->pdma_len == 0) { return; } @@ -938,27 +950,30 @@ static uint64_t sysbus_esp_pdma_read(void *opaque, hwaddr addr, { SysBusESPState *sysbus = opaque; ESPState *s = ESP(&sysbus->esp); + uint32_t dmalen = esp_get_tc(s); uint8_t *buf = get_pdma_buf(s); uint64_t val = 0; trace_esp_pdma_read(size); - if (s->pdma_len == 0) { + if (dmalen == 0 || s->pdma_len == 0) { return 0; } switch (size) { case 1: val = buf[s->pdma_cur++]; s->pdma_len--; + dmalen--; break; case 2: val = buf[s->pdma_cur++]; val = (val << 8) | buf[s->pdma_cur++]; s->pdma_len -= 2; + dmalen -= 2; break; } - - if (s->pdma_len == 0 && s->pdma_cb) { + esp_set_tc(s, dmalen); + if (dmalen == 0 || (s->pdma_len == 0 && s->pdma_cb)) { esp_lower_drq(s); s->pdma_cb(s); s->pdma_cb = NULL; diff --git a/include/hw/scsi/esp.h b/include/hw/scsi/esp.h index ff1372947b..ff50c9e7d8 100644 --- a/include/hw/scsi/esp.h +++ b/include/hw/scsi/esp.h @@ -48,8 +48,6 @@ struct ESPState { uint32_t cmdlen; uint32_t do_cmd; - /* The amount of data left in the current DMA transfer. */ - uint32_t dma_left; int dma_enabled; uint32_t async_len; @@ -67,6 +65,9 @@ struct ESPState { void (*pdma_cb)(ESPState *s); uint8_t mig_version_id; + + /* Legacy fields for vmstate_esp version < 5 */ + uint32_t mig_dma_left; }; #define TYPE_SYSBUS_ESP "sysbus-esp" From patchwork Sun Mar 7 12:08:22 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Mark Cave-Ayland X-Patchwork-Id: 1448639 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4DtgTm3JcRz9sWg for ; Sun, 7 Mar 2021 23:17:48 +1100 (AEDT) Received: from localhost ([::1]:53934 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lIsLy-00088Z-GT for incoming@patchwork.ozlabs.org; Sun, 07 Mar 2021 07:17:46 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:41506) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lIsEo-00018Z-Ge for qemu-devel@nongnu.org; Sun, 07 Mar 2021 07:10:22 -0500 Received: from mail.ilande.co.uk ([2001:41c9:1:41f::167]:43632 helo=mail.default.ilande.uk0.bigv.io) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lIsEk-0007jz-Dn for qemu-devel@nongnu.org; Sun, 07 Mar 2021 07:10:22 -0500 Received: from host86-148-34-47.range86-148.btcentralplus.com ([86.148.34.47] helo=kentang.home) by mail.default.ilande.uk0.bigv.io with esmtpsa (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1lIsEg-0002V5-4Z; Sun, 07 Mar 2021 12:10:18 +0000 From: Mark Cave-Ayland To: qemu-devel@nongnu.org, peter.maydell@linaro.org Date: Sun, 7 Mar 2021 12:08:22 +0000 Message-Id: <20210307120850.10418-15-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210307120850.10418-1-mark.cave-ayland@ilande.co.uk> References: <20210307120850.10418-1-mark.cave-ayland@ilande.co.uk> MIME-Version: 1.0 X-SA-Exim-Connect-IP: 86.148.34.47 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk Subject: [PULL 14/42] esp: remove minlen restriction in handle_ti X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on mail.default.ilande.uk0.bigv.io) Received-SPF: pass client-ip=2001:41c9:1:41f::167; envelope-from=mark.cave-ayland@ilande.co.uk; helo=mail.default.ilande.uk0.bigv.io X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" The limiting of DMA transfers to the maximum size of the available data is already handled by esp_do_dma() and do_dma_pdma_cb(). Signed-off-by: Mark Cave-Ayland Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Laurent Vivier Message-Id: <20210304221103.6369-15-mark.cave-ayland@ilande.co.uk> --- hw/scsi/esp.c | 12 ++---------- 1 file changed, 2 insertions(+), 10 deletions(-) diff --git a/hw/scsi/esp.c b/hw/scsi/esp.c index 92fea6a8c4..07d57cb791 100644 --- a/hw/scsi/esp.c +++ b/hw/scsi/esp.c @@ -552,7 +552,7 @@ void esp_transfer_data(SCSIRequest *req, uint32_t len) static void handle_ti(ESPState *s) { - uint32_t dmalen, minlen; + uint32_t dmalen; if (s->dma && !s->dma_enabled) { s->dma_cb = handle_ti; @@ -560,16 +560,8 @@ static void handle_ti(ESPState *s) } dmalen = esp_get_tc(s); - - if (s->do_cmd) { - minlen = (dmalen < ESP_CMDBUF_SZ) ? dmalen : ESP_CMDBUF_SZ; - } else if (s->ti_size < 0) { - minlen = (dmalen < -s->ti_size) ? dmalen : -s->ti_size; - } else { - minlen = (dmalen < s->ti_size) ? dmalen : s->ti_size; - } - trace_esp_handle_ti(minlen); if (s->dma) { + trace_esp_handle_ti(dmalen); s->rregs[ESP_RSTAT] &= ~STAT_TC; esp_do_dma(s); } else if (s->do_cmd) { From patchwork Sun Mar 7 12:08:23 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Cave-Ayland X-Patchwork-Id: 1448657 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4DtgtQ2Rw9z9sWg for ; Sun, 7 Mar 2021 23:35:42 +1100 (AEDT) Received: from localhost ([::1]:39026 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lIsdI-0000OJ-CT for incoming@patchwork.ozlabs.org; Sun, 07 Mar 2021 07:35:40 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:41516) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lIsEp-0001CV-UB for qemu-devel@nongnu.org; Sun, 07 Mar 2021 07:10:23 -0500 Received: from mail.ilande.co.uk ([2001:41c9:1:41f::167]:43638 helo=mail.default.ilande.uk0.bigv.io) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lIsEo-0007lh-6h for qemu-devel@nongnu.org; Sun, 07 Mar 2021 07:10:23 -0500 Received: from host86-148-34-47.range86-148.btcentralplus.com ([86.148.34.47] helo=kentang.home) by mail.default.ilande.uk0.bigv.io with esmtpsa (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1lIsEk-0002V5-8p; Sun, 07 Mar 2021 12:10:19 +0000 From: Mark Cave-Ayland To: qemu-devel@nongnu.org, peter.maydell@linaro.org Date: Sun, 7 Mar 2021 12:08:23 +0000 Message-Id: <20210307120850.10418-16-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210307120850.10418-1-mark.cave-ayland@ilande.co.uk> References: <20210307120850.10418-1-mark.cave-ayland@ilande.co.uk> MIME-Version: 1.0 X-SA-Exim-Connect-IP: 86.148.34.47 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk Subject: [PULL 15/42] esp: introduce esp_pdma_read() and esp_pdma_write() functions X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on mail.default.ilande.uk0.bigv.io) Received-SPF: pass client-ip=2001:41c9:1:41f::167; envelope-from=mark.cave-ayland@ilande.co.uk; helo=mail.default.ilande.uk0.bigv.io X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Mark Cave-Ayland Reviewed-by: Laurent Vivier Message-Id: <20210304221103.6369-16-mark.cave-ayland@ilande.co.uk> --- hw/scsi/esp.c | 28 ++++++++++++++++++++-------- 1 file changed, 20 insertions(+), 8 deletions(-) diff --git a/hw/scsi/esp.c b/hw/scsi/esp.c index 07d57cb791..0fafc866a4 100644 --- a/hw/scsi/esp.c +++ b/hw/scsi/esp.c @@ -151,6 +151,20 @@ static uint8_t *get_pdma_buf(ESPState *s) return NULL; } +static uint8_t esp_pdma_read(ESPState *s) +{ + uint8_t *buf = get_pdma_buf(s); + + return buf[s->pdma_cur++]; +} + +static void esp_pdma_write(ESPState *s, uint8_t val) +{ + uint8_t *buf = get_pdma_buf(s); + + buf[s->pdma_cur++] = val; +} + static int get_cmd_cb(ESPState *s) { int target; @@ -909,7 +923,6 @@ static void sysbus_esp_pdma_write(void *opaque, hwaddr addr, SysBusESPState *sysbus = opaque; ESPState *s = ESP(&sysbus->esp); uint32_t dmalen = esp_get_tc(s); - uint8_t *buf = get_pdma_buf(s); trace_esp_pdma_write(size); @@ -918,13 +931,13 @@ static void sysbus_esp_pdma_write(void *opaque, hwaddr addr, } switch (size) { case 1: - buf[s->pdma_cur++] = val; + esp_pdma_write(s, val); s->pdma_len--; dmalen--; break; case 2: - buf[s->pdma_cur++] = val >> 8; - buf[s->pdma_cur++] = val; + esp_pdma_write(s, val >> 8); + esp_pdma_write(s, val); s->pdma_len -= 2; dmalen -= 2; break; @@ -943,7 +956,6 @@ static uint64_t sysbus_esp_pdma_read(void *opaque, hwaddr addr, SysBusESPState *sysbus = opaque; ESPState *s = ESP(&sysbus->esp); uint32_t dmalen = esp_get_tc(s); - uint8_t *buf = get_pdma_buf(s); uint64_t val = 0; trace_esp_pdma_read(size); @@ -953,13 +965,13 @@ static uint64_t sysbus_esp_pdma_read(void *opaque, hwaddr addr, } switch (size) { case 1: - val = buf[s->pdma_cur++]; + val = esp_pdma_read(s); s->pdma_len--; dmalen--; break; case 2: - val = buf[s->pdma_cur++]; - val = (val << 8) | buf[s->pdma_cur++]; + val = esp_pdma_read(s); + val = (val << 8) | esp_pdma_read(s); s->pdma_len -= 2; dmalen -= 2; break; From patchwork Sun Mar 7 12:08:24 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Mark Cave-Ayland X-Patchwork-Id: 1448645 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4Dtgdw6CMWz9sWP for ; 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Sun, 07 Mar 2021 12:10:23 +0000 From: Mark Cave-Ayland To: qemu-devel@nongnu.org, peter.maydell@linaro.org Date: Sun, 7 Mar 2021 12:08:24 +0000 Message-Id: <20210307120850.10418-17-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210307120850.10418-1-mark.cave-ayland@ilande.co.uk> References: <20210307120850.10418-1-mark.cave-ayland@ilande.co.uk> MIME-Version: 1.0 X-SA-Exim-Connect-IP: 86.148.34.47 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk Subject: [PULL 16/42] esp: use pdma_origin directly in esp_pdma_read()/esp_pdma_write() X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on mail.default.ilande.uk0.bigv.io) Received-SPF: pass client-ip=2001:41c9:1:41f::167; envelope-from=mark.cave-ayland@ilande.co.uk; helo=mail.default.ilande.uk0.bigv.io X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" This is the first step in removing get_pdma_buf() from esp.c. Signed-off-by: Mark Cave-Ayland Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Laurent Vivier Message-Id: <20210304221103.6369-17-mark.cave-ayland@ilande.co.uk> --- hw/scsi/esp.c | 34 ++++++++++++++++++++++++++++------ 1 file changed, 28 insertions(+), 6 deletions(-) diff --git a/hw/scsi/esp.c b/hw/scsi/esp.c index 0fafc866a4..58be98f047 100644 --- a/hw/scsi/esp.c +++ b/hw/scsi/esp.c @@ -153,16 +153,38 @@ static uint8_t *get_pdma_buf(ESPState *s) static uint8_t esp_pdma_read(ESPState *s) { - uint8_t *buf = get_pdma_buf(s); - - return buf[s->pdma_cur++]; + switch (s->pdma_origin) { + case PDMA: + return s->pdma_buf[s->pdma_cur++]; + case TI: + return s->ti_buf[s->pdma_cur++]; + case CMD: + return s->cmdbuf[s->pdma_cur++]; + case ASYNC: + return s->async_buf[s->pdma_cur++]; + default: + g_assert_not_reached(); + } } static void esp_pdma_write(ESPState *s, uint8_t val) { - uint8_t *buf = get_pdma_buf(s); - - buf[s->pdma_cur++] = val; + switch (s->pdma_origin) { + case PDMA: + s->pdma_buf[s->pdma_cur++] = val; + break; + case TI: + s->ti_buf[s->pdma_cur++] = val; + break; + case CMD: + s->cmdbuf[s->pdma_cur++] = val; + break; + case ASYNC: + s->async_buf[s->pdma_cur++] = val; + break; + default: + g_assert_not_reached(); + } } static int get_cmd_cb(ESPState *s) From patchwork Sun Mar 7 12:08:25 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Mark Cave-Ayland X-Patchwork-Id: 1448648 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4DtglL693dz9sWP for ; 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Sun, 07 Mar 2021 12:10:28 +0000 From: Mark Cave-Ayland To: qemu-devel@nongnu.org, peter.maydell@linaro.org Date: Sun, 7 Mar 2021 12:08:25 +0000 Message-Id: <20210307120850.10418-18-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210307120850.10418-1-mark.cave-ayland@ilande.co.uk> References: <20210307120850.10418-1-mark.cave-ayland@ilande.co.uk> MIME-Version: 1.0 X-SA-Exim-Connect-IP: 86.148.34.47 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk Subject: [PULL 17/42] esp: move pdma_len and TC logic into esp_pdma_read()/esp_pdma_write() X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on mail.default.ilande.uk0.bigv.io) Received-SPF: pass client-ip=2001:41c9:1:41f::167; envelope-from=mark.cave-ayland@ilande.co.uk; helo=mail.default.ilande.uk0.bigv.io X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Mark Cave-Ayland Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Laurent Vivier Message-Id: <20210304221103.6369-18-mark.cave-ayland@ilande.co.uk> --- hw/scsi/esp.c | 50 ++++++++++++++++++++++++++++++++------------------ 1 file changed, 32 insertions(+), 18 deletions(-) diff --git a/hw/scsi/esp.c b/hw/scsi/esp.c index 58be98f047..b8d1ec41e9 100644 --- a/hw/scsi/esp.c +++ b/hw/scsi/esp.c @@ -153,22 +153,45 @@ static uint8_t *get_pdma_buf(ESPState *s) static uint8_t esp_pdma_read(ESPState *s) { + uint32_t dmalen = esp_get_tc(s); + uint8_t val; + + if (dmalen == 0 || s->pdma_len == 0) { + return 0; + } + switch (s->pdma_origin) { case PDMA: - return s->pdma_buf[s->pdma_cur++]; + val = s->pdma_buf[s->pdma_cur++]; + break; case TI: - return s->ti_buf[s->pdma_cur++]; + val = s->ti_buf[s->pdma_cur++]; + break; case CMD: - return s->cmdbuf[s->pdma_cur++]; + val = s->cmdbuf[s->pdma_cur++]; + break; case ASYNC: - return s->async_buf[s->pdma_cur++]; + val = s->async_buf[s->pdma_cur++]; + break; default: g_assert_not_reached(); } + + s->pdma_len--; + dmalen--; + esp_set_tc(s, dmalen); + + return val; } static void esp_pdma_write(ESPState *s, uint8_t val) { + uint32_t dmalen = esp_get_tc(s); + + if (dmalen == 0 || s->pdma_len == 0) { + return; + } + switch (s->pdma_origin) { case PDMA: s->pdma_buf[s->pdma_cur++] = val; @@ -185,6 +208,10 @@ static void esp_pdma_write(ESPState *s, uint8_t val) default: g_assert_not_reached(); } + + s->pdma_len--; + dmalen--; + esp_set_tc(s, dmalen); } static int get_cmd_cb(ESPState *s) @@ -944,27 +971,18 @@ static void sysbus_esp_pdma_write(void *opaque, hwaddr addr, { SysBusESPState *sysbus = opaque; ESPState *s = ESP(&sysbus->esp); - uint32_t dmalen = esp_get_tc(s); trace_esp_pdma_write(size); - if (dmalen == 0 || s->pdma_len == 0) { - return; - } switch (size) { case 1: esp_pdma_write(s, val); - s->pdma_len--; - dmalen--; break; case 2: esp_pdma_write(s, val >> 8); esp_pdma_write(s, val); - s->pdma_len -= 2; - dmalen -= 2; break; } - esp_set_tc(s, dmalen); if (s->pdma_len == 0 && s->pdma_cb) { esp_lower_drq(s); s->pdma_cb(s); @@ -988,17 +1006,13 @@ static uint64_t sysbus_esp_pdma_read(void *opaque, hwaddr addr, switch (size) { case 1: val = esp_pdma_read(s); - s->pdma_len--; - dmalen--; break; case 2: val = esp_pdma_read(s); val = (val << 8) | esp_pdma_read(s); - s->pdma_len -= 2; - dmalen -= 2; break; } - esp_set_tc(s, dmalen); + dmalen = esp_get_tc(s); if (dmalen == 0 || (s->pdma_len == 0 && s->pdma_cb)) { esp_lower_drq(s); s->pdma_cb(s); From patchwork Sun Mar 7 12:08:26 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Mark Cave-Ayland X-Patchwork-Id: 1448652 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4DtgqZ0jClz9sWP for ; Sun, 7 Mar 2021 23:33:14 +1100 (AEDT) Received: from localhost ([::1]:57664 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lIsau-0004ye-4q for incoming@patchwork.ozlabs.org; Sun, 07 Mar 2021 07:33:12 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:41566) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lIsFC-0001aw-Gm for qemu-devel@nongnu.org; Sun, 07 Mar 2021 07:10:46 -0500 Received: from mail.ilande.co.uk ([2001:41c9:1:41f::167]:43656 helo=mail.default.ilande.uk0.bigv.io) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lIsFA-0007rE-6r for qemu-devel@nongnu.org; Sun, 07 Mar 2021 07:10:46 -0500 Received: from host86-148-34-47.range86-148.btcentralplus.com ([86.148.34.47] helo=kentang.home) by mail.default.ilande.uk0.bigv.io with esmtpsa (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1lIsEv-0002V5-77; Sun, 07 Mar 2021 12:10:33 +0000 From: Mark Cave-Ayland To: qemu-devel@nongnu.org, peter.maydell@linaro.org Date: Sun, 7 Mar 2021 12:08:26 +0000 Message-Id: <20210307120850.10418-19-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210307120850.10418-1-mark.cave-ayland@ilande.co.uk> References: <20210307120850.10418-1-mark.cave-ayland@ilande.co.uk> MIME-Version: 1.0 X-SA-Exim-Connect-IP: 86.148.34.47 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk Subject: [PULL 18/42] esp: accumulate SCSI commands for PDMA transfers in cmdbuf instead of pdma_buf X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on mail.default.ilande.uk0.bigv.io) Received-SPF: pass client-ip=2001:41c9:1:41f::167; envelope-from=mark.cave-ayland@ilande.co.uk; helo=mail.default.ilande.uk0.bigv.io X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" ESP SCSI commands are already accumulated in cmdbuf and so there is no need to keep a separate pdma_buf buffer. Accumulate SCSI commands for PDMA transfers in cmdbuf instead of pdma_buf so update cmdlen accordingly and change pdma_origin for PDMA transfers to CMD which allows the PDMA origin to be removed. This commit also removes a stray memcpy() from get_cmd() which is a no-op because cmdlen is always zero at the start of a command. Notionally the removal of pdma_buf from vmstate_esp_pdma also breaks migration compatibility for the PDMA subsection until its complete removal by the end of the series. Signed-off-by: Mark Cave-Ayland Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Laurent Vivier Message-Id: <20210304221103.6369-19-mark.cave-ayland@ilande.co.uk> --- hw/scsi/esp.c | 56 +++++++++++++++++++------------------------ include/hw/scsi/esp.h | 2 -- 2 files changed, 25 insertions(+), 33 deletions(-) diff --git a/hw/scsi/esp.c b/hw/scsi/esp.c index b8d1ec41e9..66caa95815 100644 --- a/hw/scsi/esp.c +++ b/hw/scsi/esp.c @@ -139,8 +139,6 @@ static void set_pdma(ESPState *s, enum pdma_origin_id origin, static uint8_t *get_pdma_buf(ESPState *s) { switch (s->pdma_origin) { - case PDMA: - return s->pdma_buf; case TI: return s->ti_buf; case CMD: @@ -161,14 +159,12 @@ static uint8_t esp_pdma_read(ESPState *s) } switch (s->pdma_origin) { - case PDMA: - val = s->pdma_buf[s->pdma_cur++]; - break; case TI: val = s->ti_buf[s->pdma_cur++]; break; case CMD: - val = s->cmdbuf[s->pdma_cur++]; + val = s->cmdbuf[s->cmdlen++]; + s->pdma_cur++; break; case ASYNC: val = s->async_buf[s->pdma_cur++]; @@ -193,14 +189,12 @@ static void esp_pdma_write(ESPState *s, uint8_t val) } switch (s->pdma_origin) { - case PDMA: - s->pdma_buf[s->pdma_cur++] = val; - break; case TI: s->ti_buf[s->pdma_cur++] = val; break; case CMD: - s->cmdbuf[s->pdma_cur++] = val; + s->cmdbuf[s->cmdlen++] = val; + s->pdma_cur++; break; case ASYNC: s->async_buf[s->pdma_cur++] = val; @@ -256,8 +250,7 @@ static uint32_t get_cmd(ESPState *s, uint8_t *buf, uint8_t buflen) if (s->dma_memory_read) { s->dma_memory_read(s->dma_opaque, buf, dmalen); } else { - memcpy(s->pdma_buf, buf, dmalen); - set_pdma(s, PDMA, 0, dmalen); + set_pdma(s, CMD, 0, dmalen); esp_raise_drq(s); return 0; } @@ -316,24 +309,24 @@ static void satn_pdma_cb(ESPState *s) if (get_cmd_cb(s) < 0) { return; } - if (s->pdma_cur != s->pdma_start) { - do_cmd(s, get_pdma_buf(s) + s->pdma_start); + s->do_cmd = 0; + if (s->cmdlen) { + do_cmd(s, s->cmdbuf); } } static void handle_satn(ESPState *s) { - uint8_t buf[32]; - int len; - if (s->dma && !s->dma_enabled) { s->dma_cb = handle_satn; return; } s->pdma_cb = satn_pdma_cb; - len = get_cmd(s, buf, sizeof(buf)); - if (len) { - do_cmd(s, buf); + s->cmdlen = get_cmd(s, s->cmdbuf, sizeof(s->cmdbuf)); + if (s->cmdlen) { + do_cmd(s, s->cmdbuf); + } else { + s->do_cmd = 1; } } @@ -342,24 +335,24 @@ static void s_without_satn_pdma_cb(ESPState *s) if (get_cmd_cb(s) < 0) { return; } - if (s->pdma_cur != s->pdma_start) { + s->do_cmd = 0; + if (s->cmdlen) { do_busid_cmd(s, get_pdma_buf(s) + s->pdma_start, 0); } } static void handle_s_without_atn(ESPState *s) { - uint8_t buf[32]; - int len; - if (s->dma && !s->dma_enabled) { s->dma_cb = handle_s_without_atn; return; } s->pdma_cb = s_without_satn_pdma_cb; - len = get_cmd(s, buf, sizeof(buf)); - if (len) { - do_busid_cmd(s, buf, 0); + s->cmdlen = get_cmd(s, s->cmdbuf, sizeof(s->cmdbuf)); + if (s->cmdlen) { + do_busid_cmd(s, s->cmdbuf, 0); + } else { + s->do_cmd = 1; } } @@ -368,7 +361,7 @@ static void satn_stop_pdma_cb(ESPState *s) if (get_cmd_cb(s) < 0) { return; } - s->cmdlen = s->pdma_cur - s->pdma_start; + s->do_cmd = 0; if (s->cmdlen) { trace_esp_handle_satn_stop(s->cmdlen); s->do_cmd = 1; @@ -394,6 +387,8 @@ static void handle_satn_stop(ESPState *s) s->rregs[ESP_RINTR] = INTR_BS | INTR_FC; s->rregs[ESP_RSEQ] = SEQ_CD; esp_raise_irq(s); + } else { + s->do_cmd = 1; } } @@ -864,11 +859,10 @@ static bool esp_pdma_needed(void *opaque) static const VMStateDescription vmstate_esp_pdma = { .name = "esp/pdma", - .version_id = 1, - .minimum_version_id = 1, + .version_id = 2, + .minimum_version_id = 2, .needed = esp_pdma_needed, .fields = (VMStateField[]) { - VMSTATE_BUFFER(pdma_buf, ESPState), VMSTATE_INT32(pdma_origin, ESPState), VMSTATE_UINT32(pdma_len, ESPState), VMSTATE_UINT32(pdma_start, ESPState), diff --git a/include/hw/scsi/esp.h b/include/hw/scsi/esp.h index ff50c9e7d8..600d0c31ab 100644 --- a/include/hw/scsi/esp.h +++ b/include/hw/scsi/esp.h @@ -16,7 +16,6 @@ typedef void (*ESPDMAMemoryReadWriteFunc)(void *opaque, uint8_t *buf, int len); typedef struct ESPState ESPState; enum pdma_origin_id { - PDMA, TI, CMD, ASYNC, @@ -57,7 +56,6 @@ struct ESPState { ESPDMAMemoryReadWriteFunc dma_memory_write; void *dma_opaque; void (*dma_cb)(ESPState *s); - uint8_t pdma_buf[32]; int pdma_origin; uint32_t pdma_len; uint32_t pdma_start; From patchwork Sun Mar 7 12:08:27 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Mark Cave-Ayland X-Patchwork-Id: 1448643 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4DtgcT5Sl3z9sRf for ; Sun, 7 Mar 2021 23:23:37 +1100 (AEDT) Received: from localhost ([::1]:37372 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lIsRb-0004gt-QP for incoming@patchwork.ozlabs.org; Sun, 07 Mar 2021 07:23:35 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:41606) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lIsFN-0001sX-Ss for qemu-devel@nongnu.org; Sun, 07 Mar 2021 07:10:57 -0500 Received: from mail.ilande.co.uk ([2001:41c9:1:41f::167]:43664 helo=mail.default.ilande.uk0.bigv.io) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lIsFK-0007sU-Ow for qemu-devel@nongnu.org; Sun, 07 Mar 2021 07:10:56 -0500 Received: from host86-148-34-47.range86-148.btcentralplus.com ([86.148.34.47] helo=kentang.home) by mail.default.ilande.uk0.bigv.io with esmtpsa (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1lIsF0-0002V5-2L; Sun, 07 Mar 2021 12:10:39 +0000 From: Mark Cave-Ayland To: qemu-devel@nongnu.org, peter.maydell@linaro.org Date: Sun, 7 Mar 2021 12:08:27 +0000 Message-Id: <20210307120850.10418-20-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210307120850.10418-1-mark.cave-ayland@ilande.co.uk> References: <20210307120850.10418-1-mark.cave-ayland@ilande.co.uk> MIME-Version: 1.0 X-SA-Exim-Connect-IP: 86.148.34.47 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk Subject: [PULL 19/42] esp: remove buf parameter from do_cmd() X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on mail.default.ilande.uk0.bigv.io) Received-SPF: pass client-ip=2001:41c9:1:41f::167; envelope-from=mark.cave-ayland@ilande.co.uk; helo=mail.default.ilande.uk0.bigv.io X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Now that all SCSI commands are accumulated in cmdbuf, remove the buf parameter from do_cmd() since this always points to cmdbuf. Signed-off-by: Mark Cave-Ayland Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Laurent Vivier Message-Id: <20210304221103.6369-20-mark.cave-ayland@ilande.co.uk> --- hw/scsi/esp.c | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/hw/scsi/esp.c b/hw/scsi/esp.c index 66caa95815..8ebf5e8d4b 100644 --- a/hw/scsi/esp.c +++ b/hw/scsi/esp.c @@ -297,8 +297,9 @@ static void do_busid_cmd(ESPState *s, uint8_t *buf, uint8_t busid) esp_raise_irq(s); } -static void do_cmd(ESPState *s, uint8_t *buf) +static void do_cmd(ESPState *s) { + uint8_t *buf = s->cmdbuf; uint8_t busid = buf[0]; do_busid_cmd(s, &buf[1], busid); @@ -311,7 +312,7 @@ static void satn_pdma_cb(ESPState *s) } s->do_cmd = 0; if (s->cmdlen) { - do_cmd(s, s->cmdbuf); + do_cmd(s); } } @@ -324,7 +325,7 @@ static void handle_satn(ESPState *s) s->pdma_cb = satn_pdma_cb; s->cmdlen = get_cmd(s, s->cmdbuf, sizeof(s->cmdbuf)); if (s->cmdlen) { - do_cmd(s, s->cmdbuf); + do_cmd(s); } else { s->do_cmd = 1; } @@ -445,7 +446,7 @@ static void do_dma_pdma_cb(ESPState *s) s->ti_size = 0; s->cmdlen = 0; s->do_cmd = 0; - do_cmd(s, s->cmdbuf); + do_cmd(s); return; } s->async_buf += len; @@ -497,7 +498,7 @@ static void esp_do_dma(ESPState *s) s->ti_size = 0; s->cmdlen = 0; s->do_cmd = 0; - do_cmd(s, s->cmdbuf); + do_cmd(s); return; } if (s->async_len == 0) { @@ -627,7 +628,7 @@ static void handle_ti(ESPState *s) s->ti_size = 0; s->cmdlen = 0; s->do_cmd = 0; - do_cmd(s, s->cmdbuf); + do_cmd(s); } } From patchwork Sun Mar 7 12:08:28 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Mark Cave-Ayland X-Patchwork-Id: 1448647 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4Dtgj43v4cz9sWP for ; Sun, 7 Mar 2021 23:27:36 +1100 (AEDT) Received: from localhost ([::1]:45828 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lIsVS-0008It-J0 for incoming@patchwork.ozlabs.org; Sun, 07 Mar 2021 07:27:34 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:41608) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lIsFO-0001t8-82 for qemu-devel@nongnu.org; Sun, 07 Mar 2021 07:10:58 -0500 Received: from mail.ilande.co.uk ([2001:41c9:1:41f::167]:43668 helo=mail.default.ilande.uk0.bigv.io) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lIsFL-0007si-31 for qemu-devel@nongnu.org; Sun, 07 Mar 2021 07:10:58 -0500 Received: from host86-148-34-47.range86-148.btcentralplus.com ([86.148.34.47] helo=kentang.home) by mail.default.ilande.uk0.bigv.io with esmtpsa (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1lIsF6-0002V5-32; Sun, 07 Mar 2021 12:10:44 +0000 From: Mark Cave-Ayland To: qemu-devel@nongnu.org, peter.maydell@linaro.org Date: Sun, 7 Mar 2021 12:08:28 +0000 Message-Id: <20210307120850.10418-21-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210307120850.10418-1-mark.cave-ayland@ilande.co.uk> References: <20210307120850.10418-1-mark.cave-ayland@ilande.co.uk> MIME-Version: 1.0 X-SA-Exim-Connect-IP: 86.148.34.47 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk Subject: [PULL 20/42] esp: remove the buf and buflen parameters from get_cmd() X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on mail.default.ilande.uk0.bigv.io) Received-SPF: pass client-ip=2001:41c9:1:41f::167; envelope-from=mark.cave-ayland@ilande.co.uk; helo=mail.default.ilande.uk0.bigv.io X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Now that all SCSI commands are accumulated in cmdbuf, remove the buf and buflen parameters from get_cmd() since these always reference cmdbuf and ESP_CMDBUF_SZ respectively. Signed-off-by: Mark Cave-Ayland Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Laurent Vivier Message-Id: <20210304221103.6369-21-mark.cave-ayland@ilande.co.uk> --- hw/scsi/esp.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/hw/scsi/esp.c b/hw/scsi/esp.c index 8ebf5e8d4b..44fddf082c 100644 --- a/hw/scsi/esp.c +++ b/hw/scsi/esp.c @@ -236,15 +236,16 @@ static int get_cmd_cb(ESPState *s) return 0; } -static uint32_t get_cmd(ESPState *s, uint8_t *buf, uint8_t buflen) +static uint32_t get_cmd(ESPState *s) { + uint8_t *buf = s->cmdbuf; uint32_t dmalen; int target; target = s->wregs[ESP_WBUSID] & BUSID_DID; if (s->dma) { dmalen = esp_get_tc(s); - if (dmalen > buflen) { + if (dmalen > ESP_CMDBUF_SZ) { return 0; } if (s->dma_memory_read) { @@ -323,7 +324,7 @@ static void handle_satn(ESPState *s) return; } s->pdma_cb = satn_pdma_cb; - s->cmdlen = get_cmd(s, s->cmdbuf, sizeof(s->cmdbuf)); + s->cmdlen = get_cmd(s); if (s->cmdlen) { do_cmd(s); } else { @@ -349,7 +350,7 @@ static void handle_s_without_atn(ESPState *s) return; } s->pdma_cb = s_without_satn_pdma_cb; - s->cmdlen = get_cmd(s, s->cmdbuf, sizeof(s->cmdbuf)); + s->cmdlen = get_cmd(s); if (s->cmdlen) { do_busid_cmd(s, s->cmdbuf, 0); } else { @@ -380,7 +381,7 @@ static void handle_satn_stop(ESPState *s) return; } s->pdma_cb = satn_stop_pdma_cb; - s->cmdlen = get_cmd(s, s->cmdbuf, sizeof(s->cmdbuf)); + s->cmdlen = get_cmd(s); if (s->cmdlen) { trace_esp_handle_satn_stop(s->cmdlen); s->do_cmd = 1; From patchwork Sun Mar 7 12:08:29 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Cave-Ayland X-Patchwork-Id: 1448656 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4Dtgsj4Y59z9sWP for ; Sun, 7 Mar 2021 23:35:05 +1100 (AEDT) Received: from localhost ([::1]:37914 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lIscg-0008Nv-VK for incoming@patchwork.ozlabs.org; Sun, 07 Mar 2021 07:35:03 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:41622) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lIsFS-00021v-GY for qemu-devel@nongnu.org; Sun, 07 Mar 2021 07:11:02 -0500 Received: from mail.ilande.co.uk ([2001:41c9:1:41f::167]:43674 helo=mail.default.ilande.uk0.bigv.io) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lIsFQ-0007u6-U1 for qemu-devel@nongnu.org; Sun, 07 Mar 2021 07:11:02 -0500 Received: from host86-148-34-47.range86-148.btcentralplus.com ([86.148.34.47] helo=kentang.home) by mail.default.ilande.uk0.bigv.io with esmtpsa (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1lIsFA-0002V5-V4; Sun, 07 Mar 2021 12:10:50 +0000 From: Mark Cave-Ayland To: qemu-devel@nongnu.org, peter.maydell@linaro.org Date: Sun, 7 Mar 2021 12:08:29 +0000 Message-Id: <20210307120850.10418-22-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210307120850.10418-1-mark.cave-ayland@ilande.co.uk> References: <20210307120850.10418-1-mark.cave-ayland@ilande.co.uk> MIME-Version: 1.0 X-SA-Exim-Connect-IP: 86.148.34.47 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk Subject: [PULL 21/42] esp: remove redundant pdma_start from ESPState X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on mail.default.ilande.uk0.bigv.io) Received-SPF: pass client-ip=2001:41c9:1:41f::167; envelope-from=mark.cave-ayland@ilande.co.uk; helo=mail.default.ilande.uk0.bigv.io X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Now that PDMA SCSI commands are accumulated in cmdbuf in the same way as normal commands, the existing logic for locating the start of the SCSI command in cmdbuf via cmdlen can be used. This enables the PDMA-specific pdma_start and also get_pdma_buf() to be removed. Signed-off-by: Mark Cave-Ayland Reviewed-by: Laurent Vivier Message-Id: <20210304221103.6369-22-mark.cave-ayland@ilande.co.uk> --- hw/scsi/esp.c | 19 ++----------------- include/hw/scsi/esp.h | 1 - 2 files changed, 2 insertions(+), 18 deletions(-) diff --git a/hw/scsi/esp.c b/hw/scsi/esp.c index 44fddf082c..38c05e97c3 100644 --- a/hw/scsi/esp.c +++ b/hw/scsi/esp.c @@ -131,24 +131,10 @@ static void set_pdma(ESPState *s, enum pdma_origin_id origin, uint32_t index, uint32_t len) { s->pdma_origin = origin; - s->pdma_start = index; s->pdma_cur = index; s->pdma_len = len; } -static uint8_t *get_pdma_buf(ESPState *s) -{ - switch (s->pdma_origin) { - case TI: - return s->ti_buf; - case CMD: - return s->cmdbuf; - case ASYNC: - return s->async_buf; - } - return NULL; -} - static uint8_t esp_pdma_read(ESPState *s) { uint32_t dmalen = esp_get_tc(s); @@ -339,7 +325,7 @@ static void s_without_satn_pdma_cb(ESPState *s) } s->do_cmd = 0; if (s->cmdlen) { - do_busid_cmd(s, get_pdma_buf(s) + s->pdma_start, 0); + do_busid_cmd(s, s->cmdbuf, 0); } } @@ -441,7 +427,7 @@ static void esp_dma_done(ESPState *s) static void do_dma_pdma_cb(ESPState *s) { int to_device = ((s->rregs[ESP_RSTAT] & 7) == STAT_DO); - int len = s->pdma_cur - s->pdma_start; + int len = s->pdma_cur; if (s->do_cmd) { s->ti_size = 0; @@ -867,7 +853,6 @@ static const VMStateDescription vmstate_esp_pdma = { .fields = (VMStateField[]) { VMSTATE_INT32(pdma_origin, ESPState), VMSTATE_UINT32(pdma_len, ESPState), - VMSTATE_UINT32(pdma_start, ESPState), VMSTATE_UINT32(pdma_cur, ESPState), VMSTATE_END_OF_LIST() } diff --git a/include/hw/scsi/esp.h b/include/hw/scsi/esp.h index 600d0c31ab..55b0aee762 100644 --- a/include/hw/scsi/esp.h +++ b/include/hw/scsi/esp.h @@ -58,7 +58,6 @@ struct ESPState { void (*dma_cb)(ESPState *s); int pdma_origin; uint32_t pdma_len; - uint32_t pdma_start; uint32_t pdma_cur; void (*pdma_cb)(ESPState *s); From patchwork Sun Mar 7 12:08:30 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Cave-Ayland X-Patchwork-Id: 1448660 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4Dtgx35mjpz9sWb for ; Sun, 7 Mar 2021 23:37:59 +1100 (AEDT) Received: from localhost ([::1]:46400 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lIsfV-0003UF-PO for incoming@patchwork.ozlabs.org; Sun, 07 Mar 2021 07:37:57 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:41644) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lIsFY-0002BR-Cr for qemu-devel@nongnu.org; Sun, 07 Mar 2021 07:11:10 -0500 Received: from mail.ilande.co.uk ([2001:41c9:1:41f::167]:43682 helo=mail.default.ilande.uk0.bigv.io) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lIsFV-0007ur-Lx for qemu-devel@nongnu.org; Sun, 07 Mar 2021 07:11:08 -0500 Received: from host86-148-34-47.range86-148.btcentralplus.com ([86.148.34.47] helo=kentang.home) by mail.default.ilande.uk0.bigv.io with esmtpsa (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1lIsFG-0002V5-MD; Sun, 07 Mar 2021 12:10:55 +0000 From: Mark Cave-Ayland To: qemu-devel@nongnu.org, peter.maydell@linaro.org Date: Sun, 7 Mar 2021 12:08:30 +0000 Message-Id: <20210307120850.10418-23-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210307120850.10418-1-mark.cave-ayland@ilande.co.uk> References: <20210307120850.10418-1-mark.cave-ayland@ilande.co.uk> MIME-Version: 1.0 X-SA-Exim-Connect-IP: 86.148.34.47 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk Subject: [PULL 22/42] esp: move PDMA length adjustments into esp_pdma_read()/esp_pdma_write() X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on mail.default.ilande.uk0.bigv.io) Received-SPF: pass client-ip=2001:41c9:1:41f::167; envelope-from=mark.cave-ayland@ilande.co.uk; helo=mail.default.ilande.uk0.bigv.io X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Here the updates to async_len and ti_size are moved into the corresponding esp_pdma_read()/esp_pdma_write() function to eliminate the reference to pdma_cur in do_dma_pdma_cb(). Signed-off-by: Mark Cave-Ayland Reviewed-by: Laurent Vivier Message-Id: <20210304221103.6369-23-mark.cave-ayland@ilande.co.uk> --- hw/scsi/esp.c | 24 ++++++++++++++---------- 1 file changed, 14 insertions(+), 10 deletions(-) diff --git a/hw/scsi/esp.c b/hw/scsi/esp.c index 38c05e97c3..bb3a9cd5e3 100644 --- a/hw/scsi/esp.c +++ b/hw/scsi/esp.c @@ -153,12 +153,18 @@ static uint8_t esp_pdma_read(ESPState *s) s->pdma_cur++; break; case ASYNC: - val = s->async_buf[s->pdma_cur++]; + val = s->async_buf[0]; + if (s->async_len > 0) { + s->async_len--; + s->async_buf++; + } + s->pdma_cur++; break; default: g_assert_not_reached(); } + s->ti_size--; s->pdma_len--; dmalen--; esp_set_tc(s, dmalen); @@ -183,12 +189,18 @@ static void esp_pdma_write(ESPState *s, uint8_t val) s->pdma_cur++; break; case ASYNC: - s->async_buf[s->pdma_cur++] = val; + s->async_buf[0] = val; + if (s->async_len > 0) { + s->async_len--; + s->async_buf++; + } + s->pdma_cur++; break; default: g_assert_not_reached(); } + s->ti_size++; s->pdma_len--; dmalen--; esp_set_tc(s, dmalen); @@ -427,7 +439,6 @@ static void esp_dma_done(ESPState *s) static void do_dma_pdma_cb(ESPState *s) { int to_device = ((s->rregs[ESP_RSTAT] & 7) == STAT_DO); - int len = s->pdma_cur; if (s->do_cmd) { s->ti_size = 0; @@ -436,13 +447,6 @@ static void do_dma_pdma_cb(ESPState *s) do_cmd(s); return; } - s->async_buf += len; - s->async_len -= len; - if (to_device) { - s->ti_size += len; - } else { - s->ti_size -= len; - } if (s->async_len == 0) { scsi_req_continue(s->current_req); /* From patchwork Sun Mar 7 12:08:31 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Mark Cave-Ayland X-Patchwork-Id: 1448651 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4DtgpD47g0z9sWP for ; Sun, 7 Mar 2021 23:32:03 +1100 (AEDT) Received: from localhost ([::1]:54316 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lIsZk-0003RV-Q1 for incoming@patchwork.ozlabs.org; Sun, 07 Mar 2021 07:32:00 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:41712) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lIsFh-0002C1-30 for qemu-devel@nongnu.org; Sun, 07 Mar 2021 07:11:18 -0500 Received: from mail.ilande.co.uk ([2001:41c9:1:41f::167]:43688 helo=mail.default.ilande.uk0.bigv.io) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lIsFa-0007xV-ET for qemu-devel@nongnu.org; Sun, 07 Mar 2021 07:11:16 -0500 Received: from host86-148-34-47.range86-148.btcentralplus.com ([86.148.34.47] helo=kentang.home) by mail.default.ilande.uk0.bigv.io with esmtpsa (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1lIsFL-0002V5-GZ; Sun, 07 Mar 2021 12:11:00 +0000 From: Mark Cave-Ayland To: qemu-devel@nongnu.org, peter.maydell@linaro.org Date: Sun, 7 Mar 2021 12:08:31 +0000 Message-Id: <20210307120850.10418-24-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210307120850.10418-1-mark.cave-ayland@ilande.co.uk> References: <20210307120850.10418-1-mark.cave-ayland@ilande.co.uk> MIME-Version: 1.0 X-SA-Exim-Connect-IP: 86.148.34.47 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk Subject: [PULL 23/42] esp: use ti_wptr/ti_rptr to manage the current FIFO position for PDMA X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on mail.default.ilande.uk0.bigv.io) Received-SPF: pass client-ip=2001:41c9:1:41f::167; envelope-from=mark.cave-ayland@ilande.co.uk; helo=mail.default.ilande.uk0.bigv.io X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" This eliminates the last user of the PDMA-specific pdma_cur variable which can now be removed. Signed-off-by: Mark Cave-Ayland Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Laurent Vivier Message-Id: <20210304221103.6369-24-mark.cave-ayland@ilande.co.uk> --- hw/scsi/esp.c | 23 ++++++++--------------- include/hw/scsi/esp.h | 1 - 2 files changed, 8 insertions(+), 16 deletions(-) diff --git a/hw/scsi/esp.c b/hw/scsi/esp.c index bb3a9cd5e3..7bf2ec9c94 100644 --- a/hw/scsi/esp.c +++ b/hw/scsi/esp.c @@ -127,11 +127,9 @@ static uint32_t esp_get_stc(ESPState *s) return dmalen; } -static void set_pdma(ESPState *s, enum pdma_origin_id origin, - uint32_t index, uint32_t len) +static void set_pdma(ESPState *s, enum pdma_origin_id origin, uint32_t len) { s->pdma_origin = origin; - s->pdma_cur = index; s->pdma_len = len; } @@ -146,11 +144,10 @@ static uint8_t esp_pdma_read(ESPState *s) switch (s->pdma_origin) { case TI: - val = s->ti_buf[s->pdma_cur++]; + val = s->ti_buf[s->ti_rptr++]; break; case CMD: val = s->cmdbuf[s->cmdlen++]; - s->pdma_cur++; break; case ASYNC: val = s->async_buf[0]; @@ -158,7 +155,6 @@ static uint8_t esp_pdma_read(ESPState *s) s->async_len--; s->async_buf++; } - s->pdma_cur++; break; default: g_assert_not_reached(); @@ -182,11 +178,10 @@ static void esp_pdma_write(ESPState *s, uint8_t val) switch (s->pdma_origin) { case TI: - s->ti_buf[s->pdma_cur++] = val; + s->ti_buf[s->ti_wptr++] = val; break; case CMD: s->cmdbuf[s->cmdlen++] = val; - s->pdma_cur++; break; case ASYNC: s->async_buf[0] = val; @@ -194,7 +189,6 @@ static void esp_pdma_write(ESPState *s, uint8_t val) s->async_len--; s->async_buf++; } - s->pdma_cur++; break; default: g_assert_not_reached(); @@ -249,7 +243,7 @@ static uint32_t get_cmd(ESPState *s) if (s->dma_memory_read) { s->dma_memory_read(s->dma_opaque, buf, dmalen); } else { - set_pdma(s, CMD, 0, dmalen); + set_pdma(s, CMD, dmalen); esp_raise_drq(s); return 0; } @@ -412,7 +406,7 @@ static void write_response(ESPState *s) s->rregs[ESP_RINTR] = INTR_BS | INTR_FC; s->rregs[ESP_RSEQ] = SEQ_CD; } else { - set_pdma(s, TI, 0, 2); + set_pdma(s, TI, 2); s->pdma_cb = write_response_pdma_cb; esp_raise_drq(s); return; @@ -480,7 +474,7 @@ static void esp_do_dma(ESPState *s) if (s->dma_memory_read) { s->dma_memory_read(s->dma_opaque, &s->cmdbuf[s->cmdlen], len); } else { - set_pdma(s, CMD, s->cmdlen, len); + set_pdma(s, CMD, len); s->pdma_cb = do_dma_pdma_cb; esp_raise_drq(s); return; @@ -503,7 +497,7 @@ static void esp_do_dma(ESPState *s) if (s->dma_memory_read) { s->dma_memory_read(s->dma_opaque, s->async_buf, len); } else { - set_pdma(s, ASYNC, 0, len); + set_pdma(s, ASYNC, len); s->pdma_cb = do_dma_pdma_cb; esp_raise_drq(s); return; @@ -512,7 +506,7 @@ static void esp_do_dma(ESPState *s) if (s->dma_memory_write) { s->dma_memory_write(s->dma_opaque, s->async_buf, len); } else { - set_pdma(s, ASYNC, 0, len); + set_pdma(s, ASYNC, len); s->pdma_cb = do_dma_pdma_cb; esp_raise_drq(s); return; @@ -857,7 +851,6 @@ static const VMStateDescription vmstate_esp_pdma = { .fields = (VMStateField[]) { VMSTATE_INT32(pdma_origin, ESPState), VMSTATE_UINT32(pdma_len, ESPState), - VMSTATE_UINT32(pdma_cur, ESPState), VMSTATE_END_OF_LIST() } }; diff --git a/include/hw/scsi/esp.h b/include/hw/scsi/esp.h index 55b0aee762..26bd015cf4 100644 --- a/include/hw/scsi/esp.h +++ b/include/hw/scsi/esp.h @@ -58,7 +58,6 @@ struct ESPState { void (*dma_cb)(ESPState *s); int pdma_origin; uint32_t pdma_len; - uint32_t pdma_cur; void (*pdma_cb)(ESPState *s); uint8_t mig_version_id; From patchwork Sun Mar 7 12:08:32 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Mark Cave-Ayland X-Patchwork-Id: 1448661 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4DtgyN2J2Tz9sWP for ; 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Sun, 07 Mar 2021 12:11:05 +0000 From: Mark Cave-Ayland To: qemu-devel@nongnu.org, peter.maydell@linaro.org Date: Sun, 7 Mar 2021 12:08:32 +0000 Message-Id: <20210307120850.10418-25-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210307120850.10418-1-mark.cave-ayland@ilande.co.uk> References: <20210307120850.10418-1-mark.cave-ayland@ilande.co.uk> MIME-Version: 1.0 X-SA-Exim-Connect-IP: 86.148.34.47 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk Subject: [PULL 24/42] esp: use in-built TC to determine PDMA transfer length X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on mail.default.ilande.uk0.bigv.io) Received-SPF: pass client-ip=2001:41c9:1:41f::167; envelope-from=mark.cave-ayland@ilande.co.uk; helo=mail.default.ilande.uk0.bigv.io X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Real hardware simply counts down using the in-built TC to determine when the the PDMA request is complete. Use the TC to determine the PDMA transfer length which then enables us to remove the redundant pdma_len variable. Signed-off-by: Mark Cave-Ayland Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Laurent Vivier Message-Id: <20210304221103.6369-25-mark.cave-ayland@ilande.co.uk> --- hw/scsi/esp.c | 28 +++++++++++++--------------- include/hw/scsi/esp.h | 1 - 2 files changed, 13 insertions(+), 16 deletions(-) diff --git a/hw/scsi/esp.c b/hw/scsi/esp.c index 7bf2ec9c94..c80dc606e8 100644 --- a/hw/scsi/esp.c +++ b/hw/scsi/esp.c @@ -127,10 +127,9 @@ static uint32_t esp_get_stc(ESPState *s) return dmalen; } -static void set_pdma(ESPState *s, enum pdma_origin_id origin, uint32_t len) +static void set_pdma(ESPState *s, enum pdma_origin_id origin) { s->pdma_origin = origin; - s->pdma_len = len; } static uint8_t esp_pdma_read(ESPState *s) @@ -138,7 +137,7 @@ static uint8_t esp_pdma_read(ESPState *s) uint32_t dmalen = esp_get_tc(s); uint8_t val; - if (dmalen == 0 || s->pdma_len == 0) { + if (dmalen == 0) { return 0; } @@ -161,7 +160,6 @@ static uint8_t esp_pdma_read(ESPState *s) } s->ti_size--; - s->pdma_len--; dmalen--; esp_set_tc(s, dmalen); @@ -172,7 +170,7 @@ static void esp_pdma_write(ESPState *s, uint8_t val) { uint32_t dmalen = esp_get_tc(s); - if (dmalen == 0 || s->pdma_len == 0) { + if (dmalen == 0) { return; } @@ -195,7 +193,6 @@ static void esp_pdma_write(ESPState *s, uint8_t val) } s->ti_size++; - s->pdma_len--; dmalen--; esp_set_tc(s, dmalen); } @@ -243,7 +240,7 @@ static uint32_t get_cmd(ESPState *s) if (s->dma_memory_read) { s->dma_memory_read(s->dma_opaque, buf, dmalen); } else { - set_pdma(s, CMD, dmalen); + set_pdma(s, CMD); esp_raise_drq(s); return 0; } @@ -406,7 +403,7 @@ static void write_response(ESPState *s) s->rregs[ESP_RINTR] = INTR_BS | INTR_FC; s->rregs[ESP_RSEQ] = SEQ_CD; } else { - set_pdma(s, TI, 2); + set_pdma(s, TI); s->pdma_cb = write_response_pdma_cb; esp_raise_drq(s); return; @@ -474,7 +471,7 @@ static void esp_do_dma(ESPState *s) if (s->dma_memory_read) { s->dma_memory_read(s->dma_opaque, &s->cmdbuf[s->cmdlen], len); } else { - set_pdma(s, CMD, len); + set_pdma(s, CMD); s->pdma_cb = do_dma_pdma_cb; esp_raise_drq(s); return; @@ -497,7 +494,7 @@ static void esp_do_dma(ESPState *s) if (s->dma_memory_read) { s->dma_memory_read(s->dma_opaque, s->async_buf, len); } else { - set_pdma(s, ASYNC, len); + set_pdma(s, ASYNC); s->pdma_cb = do_dma_pdma_cb; esp_raise_drq(s); return; @@ -506,7 +503,7 @@ static void esp_do_dma(ESPState *s) if (s->dma_memory_write) { s->dma_memory_write(s->dma_opaque, s->async_buf, len); } else { - set_pdma(s, ASYNC, len); + set_pdma(s, ASYNC); s->pdma_cb = do_dma_pdma_cb; esp_raise_drq(s); return; @@ -850,7 +847,6 @@ static const VMStateDescription vmstate_esp_pdma = { .needed = esp_pdma_needed, .fields = (VMStateField[]) { VMSTATE_INT32(pdma_origin, ESPState), - VMSTATE_UINT32(pdma_len, ESPState), VMSTATE_END_OF_LIST() } }; @@ -949,6 +945,7 @@ static void sysbus_esp_pdma_write(void *opaque, hwaddr addr, { SysBusESPState *sysbus = opaque; ESPState *s = ESP(&sysbus->esp); + uint32_t dmalen; trace_esp_pdma_write(size); @@ -961,7 +958,8 @@ static void sysbus_esp_pdma_write(void *opaque, hwaddr addr, esp_pdma_write(s, val); break; } - if (s->pdma_len == 0 && s->pdma_cb) { + dmalen = esp_get_tc(s); + if (dmalen == 0 && s->pdma_cb) { esp_lower_drq(s); s->pdma_cb(s); s->pdma_cb = NULL; @@ -978,7 +976,7 @@ static uint64_t sysbus_esp_pdma_read(void *opaque, hwaddr addr, trace_esp_pdma_read(size); - if (dmalen == 0 || s->pdma_len == 0) { + if (dmalen == 0) { return 0; } switch (size) { @@ -991,7 +989,7 @@ static uint64_t sysbus_esp_pdma_read(void *opaque, hwaddr addr, break; } dmalen = esp_get_tc(s); - if (dmalen == 0 || (s->pdma_len == 0 && s->pdma_cb)) { + if (dmalen == 0 && s->pdma_cb) { esp_lower_drq(s); s->pdma_cb(s); s->pdma_cb = NULL; diff --git a/include/hw/scsi/esp.h b/include/hw/scsi/esp.h index 26bd015cf4..1be4586aff 100644 --- a/include/hw/scsi/esp.h +++ b/include/hw/scsi/esp.h @@ -57,7 +57,6 @@ struct ESPState { void *dma_opaque; void (*dma_cb)(ESPState *s); int pdma_origin; - uint32_t pdma_len; void (*pdma_cb)(ESPState *s); uint8_t mig_version_id; From patchwork Sun Mar 7 12:08:33 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Mark Cave-Ayland X-Patchwork-Id: 1448664 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4Dth4g662cz9sWb for ; Sun, 7 Mar 2021 23:44:35 +1100 (AEDT) Received: from localhost ([::1]:54936 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lIslt-0007Cn-U0 for incoming@patchwork.ozlabs.org; Sun, 07 Mar 2021 07:44:33 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:41756) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lIsFo-0002Mo-Ca for qemu-devel@nongnu.org; Sun, 07 Mar 2021 07:11:24 -0500 Received: from mail.ilande.co.uk ([2001:41c9:1:41f::167]:43702 helo=mail.default.ilande.uk0.bigv.io) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lIsFm-0007zh-Oz for qemu-devel@nongnu.org; Sun, 07 Mar 2021 07:11:24 -0500 Received: from host86-148-34-47.range86-148.btcentralplus.com ([86.148.34.47] helo=kentang.home) by mail.default.ilande.uk0.bigv.io with esmtpsa (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1lIsFV-0002V5-5O; Sun, 07 Mar 2021 12:11:11 +0000 From: Mark Cave-Ayland To: qemu-devel@nongnu.org, peter.maydell@linaro.org Date: Sun, 7 Mar 2021 12:08:33 +0000 Message-Id: <20210307120850.10418-26-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210307120850.10418-1-mark.cave-ayland@ilande.co.uk> References: <20210307120850.10418-1-mark.cave-ayland@ilande.co.uk> MIME-Version: 1.0 X-SA-Exim-Connect-IP: 86.148.34.47 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk Subject: [PULL 25/42] esp: remove CMD pdma_origin X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on mail.default.ilande.uk0.bigv.io) Received-SPF: pass client-ip=2001:41c9:1:41f::167; envelope-from=mark.cave-ayland@ilande.co.uk; helo=mail.default.ilande.uk0.bigv.io X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" The cmdbuf is really just a copy of FIFO data (including extra message phase bytes) so its pdma_origin is effectively TI. Fortunately we already know when we are receiving a SCSI command since do_cmd == 1 which enables us to distinguish between the two cases in esp_pdma_read()/esp_pdma_write(). Signed-off-by: Mark Cave-Ayland Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Laurent Vivier Message-Id: <20210304221103.6369-26-mark.cave-ayland@ilande.co.uk> --- hw/scsi/esp.c | 22 ++++++++++++---------- include/hw/scsi/esp.h | 1 - 2 files changed, 12 insertions(+), 11 deletions(-) diff --git a/hw/scsi/esp.c b/hw/scsi/esp.c index c80dc606e8..d5c03f9697 100644 --- a/hw/scsi/esp.c +++ b/hw/scsi/esp.c @@ -143,10 +143,11 @@ static uint8_t esp_pdma_read(ESPState *s) switch (s->pdma_origin) { case TI: - val = s->ti_buf[s->ti_rptr++]; - break; - case CMD: - val = s->cmdbuf[s->cmdlen++]; + if (s->do_cmd) { + val = s->cmdbuf[s->cmdlen++]; + } else { + val = s->ti_buf[s->ti_rptr++]; + } break; case ASYNC: val = s->async_buf[0]; @@ -176,10 +177,11 @@ static void esp_pdma_write(ESPState *s, uint8_t val) switch (s->pdma_origin) { case TI: - s->ti_buf[s->ti_wptr++] = val; - break; - case CMD: - s->cmdbuf[s->cmdlen++] = val; + if (s->do_cmd) { + s->cmdbuf[s->cmdlen++] = val; + } else { + s->ti_buf[s->ti_wptr++] = val; + } break; case ASYNC: s->async_buf[0] = val; @@ -240,7 +242,7 @@ static uint32_t get_cmd(ESPState *s) if (s->dma_memory_read) { s->dma_memory_read(s->dma_opaque, buf, dmalen); } else { - set_pdma(s, CMD); + set_pdma(s, TI); esp_raise_drq(s); return 0; } @@ -471,7 +473,7 @@ static void esp_do_dma(ESPState *s) if (s->dma_memory_read) { s->dma_memory_read(s->dma_opaque, &s->cmdbuf[s->cmdlen], len); } else { - set_pdma(s, CMD); + set_pdma(s, TI); s->pdma_cb = do_dma_pdma_cb; esp_raise_drq(s); return; diff --git a/include/hw/scsi/esp.h b/include/hw/scsi/esp.h index 1be4586aff..dbbbb3fc52 100644 --- a/include/hw/scsi/esp.h +++ b/include/hw/scsi/esp.h @@ -17,7 +17,6 @@ typedef struct ESPState ESPState; enum pdma_origin_id { TI, - CMD, ASYNC, }; From patchwork Sun Mar 7 12:08:34 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Mark Cave-Ayland X-Patchwork-Id: 1448641 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4DtgYv0XLnz9sWb for ; Sun, 7 Mar 2021 23:21:23 +1100 (AEDT) Received: from localhost ([::1]:60566 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lIsPR-0002T4-2v for incoming@patchwork.ozlabs.org; Sun, 07 Mar 2021 07:21:21 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:41776) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lIsFu-0002P4-Ek for qemu-devel@nongnu.org; Sun, 07 Mar 2021 07:11:31 -0500 Received: from mail.ilande.co.uk ([2001:41c9:1:41f::167]:43706 helo=mail.default.ilande.uk0.bigv.io) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lIsFq-00081I-Af for qemu-devel@nongnu.org; Sun, 07 Mar 2021 07:11:30 -0500 Received: from host86-148-34-47.range86-148.btcentralplus.com ([86.148.34.47] helo=kentang.home) by mail.default.ilande.uk0.bigv.io with esmtpsa (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1lIsFb-0002V5-5U; Sun, 07 Mar 2021 12:11:15 +0000 From: Mark Cave-Ayland To: qemu-devel@nongnu.org, peter.maydell@linaro.org Date: Sun, 7 Mar 2021 12:08:34 +0000 Message-Id: <20210307120850.10418-27-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210307120850.10418-1-mark.cave-ayland@ilande.co.uk> References: <20210307120850.10418-1-mark.cave-ayland@ilande.co.uk> MIME-Version: 1.0 X-SA-Exim-Connect-IP: 86.148.34.47 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk Subject: [PULL 26/42] esp: rename get_cmd_cb() to esp_select() X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on mail.default.ilande.uk0.bigv.io) Received-SPF: pass client-ip=2001:41c9:1:41f::167; envelope-from=mark.cave-ayland@ilande.co.uk; helo=mail.default.ilande.uk0.bigv.io X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" This better describes the purpose of the function. Signed-off-by: Mark Cave-Ayland Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Laurent Vivier Message-Id: <20210304221103.6369-27-mark.cave-ayland@ilande.co.uk> --- hw/scsi/esp.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/hw/scsi/esp.c b/hw/scsi/esp.c index d5c03f9697..d8d7ede00a 100644 --- a/hw/scsi/esp.c +++ b/hw/scsi/esp.c @@ -199,7 +199,7 @@ static void esp_pdma_write(ESPState *s, uint8_t val) esp_set_tc(s, dmalen); } -static int get_cmd_cb(ESPState *s) +static int esp_select(ESPState *s) { int target; @@ -256,7 +256,7 @@ static uint32_t get_cmd(ESPState *s) } trace_esp_get_cmd(dmalen, target); - if (get_cmd_cb(s) < 0) { + if (esp_select(s) < 0) { return 0; } return dmalen; @@ -299,7 +299,7 @@ static void do_cmd(ESPState *s) static void satn_pdma_cb(ESPState *s) { - if (get_cmd_cb(s) < 0) { + if (esp_select(s) < 0) { return; } s->do_cmd = 0; @@ -325,7 +325,7 @@ static void handle_satn(ESPState *s) static void s_without_satn_pdma_cb(ESPState *s) { - if (get_cmd_cb(s) < 0) { + if (esp_select(s) < 0) { return; } s->do_cmd = 0; @@ -351,7 +351,7 @@ static void handle_s_without_atn(ESPState *s) static void satn_stop_pdma_cb(ESPState *s) { - if (get_cmd_cb(s) < 0) { + if (esp_select(s) < 0) { return; } s->do_cmd = 0; From patchwork Sun Mar 7 12:08:35 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Cave-Ayland X-Patchwork-Id: 1448665 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4Dth501Cx0z9sWb for ; Sun, 7 Mar 2021 23:44:52 +1100 (AEDT) Received: from localhost ([::1]:56072 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lIsmA-0007er-5p for incoming@patchwork.ozlabs.org; Sun, 07 Mar 2021 07:44:50 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:41788) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lIsFx-0002Q2-58 for qemu-devel@nongnu.org; Sun, 07 Mar 2021 07:11:34 -0500 Received: from mail.ilande.co.uk ([2001:41c9:1:41f::167]:43712 helo=mail.default.ilande.uk0.bigv.io) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lIsFt-00083y-C7 for qemu-devel@nongnu.org; Sun, 07 Mar 2021 07:11:32 -0500 Received: from host86-148-34-47.range86-148.btcentralplus.com ([86.148.34.47] helo=kentang.home) by mail.default.ilande.uk0.bigv.io with esmtpsa (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1lIsFf-0002V5-KA; Sun, 07 Mar 2021 12:11:19 +0000 From: Mark Cave-Ayland To: qemu-devel@nongnu.org, peter.maydell@linaro.org Date: Sun, 7 Mar 2021 12:08:35 +0000 Message-Id: <20210307120850.10418-28-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210307120850.10418-1-mark.cave-ayland@ilande.co.uk> References: <20210307120850.10418-1-mark.cave-ayland@ilande.co.uk> MIME-Version: 1.0 X-SA-Exim-Connect-IP: 86.148.34.47 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk Subject: [PULL 27/42] esp: fix PDMA target selection X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on mail.default.ilande.uk0.bigv.io) Received-SPF: pass client-ip=2001:41c9:1:41f::167; envelope-from=mark.cave-ayland@ilande.co.uk; helo=mail.default.ilande.uk0.bigv.io X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Currently the target selection for PDMA is done after the SCSI command has been delivered which is not correct. Perform target selection as part of the initial get_cmd() call when the command is submitted: if no target is present, don't raise DRQ. If the target is present then switch to the command phase since the MacOS toolbox ROM checks for this before attempting to submit the SCSI command. Signed-off-by: Mark Cave-Ayland Reviewed-by: Laurent Vivier Message-Id: <20210304221103.6369-28-mark.cave-ayland@ilande.co.uk> --- hw/scsi/esp.c | 53 +++++++++++++++++++++++++++++++++------------------ 1 file changed, 34 insertions(+), 19 deletions(-) diff --git a/hw/scsi/esp.c b/hw/scsi/esp.c index d8d7ede00a..10e63d1f62 100644 --- a/hw/scsi/esp.c +++ b/hw/scsi/esp.c @@ -243,6 +243,9 @@ static uint32_t get_cmd(ESPState *s) s->dma_memory_read(s->dma_opaque, buf, dmalen); } else { set_pdma(s, TI); + if (esp_select(s) < 0) { + return -1; + } esp_raise_drq(s); return 0; } @@ -257,7 +260,7 @@ static uint32_t get_cmd(ESPState *s) trace_esp_get_cmd(dmalen, target); if (esp_select(s) < 0) { - return 0; + return -1; } return dmalen; } @@ -299,9 +302,6 @@ static void do_cmd(ESPState *s) static void satn_pdma_cb(ESPState *s) { - if (esp_select(s) < 0) { - return; - } s->do_cmd = 0; if (s->cmdlen) { do_cmd(s); @@ -310,24 +310,28 @@ static void satn_pdma_cb(ESPState *s) static void handle_satn(ESPState *s) { + int32_t cmdlen; + if (s->dma && !s->dma_enabled) { s->dma_cb = handle_satn; return; } s->pdma_cb = satn_pdma_cb; - s->cmdlen = get_cmd(s); - if (s->cmdlen) { + cmdlen = get_cmd(s); + if (cmdlen > 0) { + s->cmdlen = cmdlen; do_cmd(s); - } else { + } else if (cmdlen == 0) { + s->cmdlen = 0; s->do_cmd = 1; + /* Target present, but no cmd yet - switch to command phase */ + s->rregs[ESP_RSEQ] = SEQ_CD; + s->rregs[ESP_RSTAT] = STAT_CD; } } static void s_without_satn_pdma_cb(ESPState *s) { - if (esp_select(s) < 0) { - return; - } s->do_cmd = 0; if (s->cmdlen) { do_busid_cmd(s, s->cmdbuf, 0); @@ -336,24 +340,28 @@ static void s_without_satn_pdma_cb(ESPState *s) static void handle_s_without_atn(ESPState *s) { + int32_t cmdlen; + if (s->dma && !s->dma_enabled) { s->dma_cb = handle_s_without_atn; return; } s->pdma_cb = s_without_satn_pdma_cb; - s->cmdlen = get_cmd(s); - if (s->cmdlen) { + cmdlen = get_cmd(s); + if (cmdlen > 0) { + s->cmdlen = cmdlen; do_busid_cmd(s, s->cmdbuf, 0); - } else { + } else if (cmdlen == 0) { + s->cmdlen = 0; s->do_cmd = 1; + /* Target present, but no cmd yet - switch to command phase */ + s->rregs[ESP_RSEQ] = SEQ_CD; + s->rregs[ESP_RSTAT] = STAT_CD; } } static void satn_stop_pdma_cb(ESPState *s) { - if (esp_select(s) < 0) { - return; - } s->do_cmd = 0; if (s->cmdlen) { trace_esp_handle_satn_stop(s->cmdlen); @@ -367,21 +375,28 @@ static void satn_stop_pdma_cb(ESPState *s) static void handle_satn_stop(ESPState *s) { + int32_t cmdlen; + if (s->dma && !s->dma_enabled) { s->dma_cb = handle_satn_stop; return; } s->pdma_cb = satn_stop_pdma_cb; - s->cmdlen = get_cmd(s); - if (s->cmdlen) { + cmdlen = get_cmd(s); + if (cmdlen > 0) { trace_esp_handle_satn_stop(s->cmdlen); + s->cmdlen = cmdlen; s->do_cmd = 1; s->rregs[ESP_RSTAT] = STAT_TC | STAT_CD; s->rregs[ESP_RINTR] = INTR_BS | INTR_FC; s->rregs[ESP_RSEQ] = SEQ_CD; esp_raise_irq(s); - } else { + } else if (cmdlen == 0) { + s->cmdlen = 0; s->do_cmd = 1; + /* Target present, but no cmd yet - switch to command phase */ + s->rregs[ESP_RSEQ] = SEQ_CD; + s->rregs[ESP_RSTAT] = STAT_CD; } } From patchwork Sun Mar 7 12:08:36 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Cave-Ayland X-Patchwork-Id: 1448644 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4Dtgdw6YxVz9sWb for ; Sun, 7 Mar 2021 23:24:52 +1100 (AEDT) Received: from localhost ([::1]:40714 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lIsSo-00065r-T2 for incoming@patchwork.ozlabs.org; Sun, 07 Mar 2021 07:24:50 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:41848) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lIsG1-0002Rp-Ue for qemu-devel@nongnu.org; Sun, 07 Mar 2021 07:11:38 -0500 Received: from mail.ilande.co.uk ([2001:41c9:1:41f::167]:43716 helo=mail.default.ilande.uk0.bigv.io) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lIsFy-00086u-8Z for qemu-devel@nongnu.org; Sun, 07 Mar 2021 07:11:37 -0500 Received: from host86-148-34-47.range86-148.btcentralplus.com ([86.148.34.47] helo=kentang.home) by mail.default.ilande.uk0.bigv.io with esmtpsa (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1lIsFj-0002V5-7H; Sun, 07 Mar 2021 12:11:23 +0000 From: Mark Cave-Ayland To: qemu-devel@nongnu.org, peter.maydell@linaro.org Date: Sun, 7 Mar 2021 12:08:36 +0000 Message-Id: <20210307120850.10418-29-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210307120850.10418-1-mark.cave-ayland@ilande.co.uk> References: <20210307120850.10418-1-mark.cave-ayland@ilande.co.uk> MIME-Version: 1.0 X-SA-Exim-Connect-IP: 86.148.34.47 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk Subject: [PULL 28/42] esp: use FIFO for PDMA transfers between initiator and device X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on mail.default.ilande.uk0.bigv.io) Received-SPF: pass client-ip=2001:41c9:1:41f::167; envelope-from=mark.cave-ayland@ilande.co.uk; helo=mail.default.ilande.uk0.bigv.io X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" PDMA as implemented on the Quadra 800 uses DREQ to load data into the FIFO up to a maximum of 16 bytes at a time. The MacOS toolbox ROM requires this because it mixes FIFO and PDMA transfers whilst checking the FIFO status and counter registers to ensure success. Signed-off-by: Mark Cave-Ayland Reviewed-by: Laurent Vivier Message-Id: <20210304221103.6369-29-mark.cave-ayland@ilande.co.uk> --- hw/scsi/esp.c | 109 ++++++++++++++++++++++++++++++++++---------------- 1 file changed, 75 insertions(+), 34 deletions(-) diff --git a/hw/scsi/esp.c b/hw/scsi/esp.c index 10e63d1f62..aa897a4ebd 100644 --- a/hw/scsi/esp.c +++ b/hw/scsi/esp.c @@ -134,13 +134,8 @@ static void set_pdma(ESPState *s, enum pdma_origin_id origin) static uint8_t esp_pdma_read(ESPState *s) { - uint32_t dmalen = esp_get_tc(s); uint8_t val; - if (dmalen == 0) { - return 0; - } - switch (s->pdma_origin) { case TI: if (s->do_cmd) { @@ -160,10 +155,6 @@ static uint8_t esp_pdma_read(ESPState *s) g_assert_not_reached(); } - s->ti_size--; - dmalen--; - esp_set_tc(s, dmalen); - return val; } @@ -194,7 +185,6 @@ static void esp_pdma_write(ESPState *s, uint8_t val) g_assert_not_reached(); } - s->ti_size++; dmalen--; esp_set_tc(s, dmalen); } @@ -290,6 +280,7 @@ static void do_busid_cmd(ESPState *s, uint8_t *buf, uint8_t busid) s->rregs[ESP_RINTR] = INTR_BS | INTR_FC; s->rregs[ESP_RSEQ] = SEQ_CD; esp_raise_irq(s); + esp_lower_drq(s); } static void do_cmd(ESPState *s) @@ -447,28 +438,71 @@ static void esp_dma_done(ESPState *s) static void do_dma_pdma_cb(ESPState *s) { int to_device = ((s->rregs[ESP_RSTAT] & 7) == STAT_DO); + int len; if (s->do_cmd) { s->ti_size = 0; s->cmdlen = 0; s->do_cmd = 0; do_cmd(s); + esp_lower_drq(s); return; } - if (s->async_len == 0) { - scsi_req_continue(s->current_req); - /* - * If there is still data to be read from the device then - * complete the DMA operation immediately. Otherwise defer - * until the scsi layer has completed. - */ - if (to_device || esp_get_tc(s) != 0 || s->ti_size == 0) { + + if (to_device) { + /* Copy FIFO data to device */ + len = MIN(s->ti_wptr, TI_BUFSZ); + memcpy(s->async_buf, s->ti_buf, len); + s->ti_wptr = 0; + s->ti_rptr = 0; + s->async_buf += len; + s->async_len -= len; + s->ti_size += len; + if (s->async_len == 0) { + scsi_req_continue(s->current_req); return; } - } - /* Partially filled a scsi buffer. Complete immediately. */ - esp_dma_done(s); + if (esp_get_tc(s) == 0) { + esp_lower_drq(s); + esp_dma_done(s); + } + + return; + } else { + if (s->async_len == 0) { + if (s->current_req) { + scsi_req_continue(s->current_req); + } + + /* + * If there is still data to be read from the device then + * complete the DMA operation immediately. Otherwise defer + * until the scsi layer has completed. + */ + if (esp_get_tc(s) != 0 || s->ti_size == 0) { + return; + } + } + + if (esp_get_tc(s) != 0) { + /* Copy device data to FIFO */ + s->ti_wptr = 0; + s->ti_rptr = 0; + len = MIN(s->async_len, TI_BUFSZ); + memcpy(s->ti_buf, s->async_buf, len); + s->ti_wptr += len; + s->async_buf += len; + s->async_len -= len; + s->ti_size -= len; + esp_set_tc(s, esp_get_tc(s) - len); + return; + } + + /* Partially filled a scsi buffer. Complete immediately. */ + esp_lower_drq(s); + esp_dma_done(s); + } } static void esp_do_dma(ESPState *s) @@ -511,7 +545,7 @@ static void esp_do_dma(ESPState *s) if (s->dma_memory_read) { s->dma_memory_read(s->dma_opaque, s->async_buf, len); } else { - set_pdma(s, ASYNC); + set_pdma(s, TI); s->pdma_cb = do_dma_pdma_cb; esp_raise_drq(s); return; @@ -520,9 +554,20 @@ static void esp_do_dma(ESPState *s) if (s->dma_memory_write) { s->dma_memory_write(s->dma_opaque, s->async_buf, len); } else { - set_pdma(s, ASYNC); + /* Copy device data to FIFO */ + len = MIN(len, TI_BUFSZ - s->ti_wptr); + memcpy(&s->ti_buf[s->ti_wptr], s->async_buf, len); + s->ti_wptr += len; + s->async_buf += len; + s->async_len -= len; + s->ti_size -= len; + esp_set_tc(s, esp_get_tc(s) - len); + set_pdma(s, TI); s->pdma_cb = do_dma_pdma_cb; esp_raise_drq(s); + + /* Indicate transfer to FIFO is complete */ + s->rregs[ESP_RSTAT] |= STAT_TC; return; } } @@ -548,6 +593,7 @@ static void esp_do_dma(ESPState *s) /* Partially filled a scsi buffer. Complete immediately. */ esp_dma_done(s); + esp_lower_drq(s); } static void esp_report_command_complete(ESPState *s, uint32_t status) @@ -564,6 +610,7 @@ static void esp_report_command_complete(ESPState *s, uint32_t status) s->status = status; s->rregs[ESP_RSTAT] = STAT_ST; esp_dma_done(s); + esp_lower_drq(s); if (s->current_req) { scsi_req_unref(s->current_req); s->current_req = NULL; @@ -605,6 +652,7 @@ void esp_transfer_data(SCSIRequest *req, uint32_t len) * completion interrupt is deferred to here. */ esp_dma_done(s); + esp_lower_drq(s); } } @@ -976,10 +1024,8 @@ static void sysbus_esp_pdma_write(void *opaque, hwaddr addr, break; } dmalen = esp_get_tc(s); - if (dmalen == 0 && s->pdma_cb) { - esp_lower_drq(s); + if (dmalen == 0 || (s->ti_wptr == TI_BUFSZ)) { s->pdma_cb(s); - s->pdma_cb = NULL; } } @@ -988,14 +1034,10 @@ static uint64_t sysbus_esp_pdma_read(void *opaque, hwaddr addr, { SysBusESPState *sysbus = opaque; ESPState *s = ESP(&sysbus->esp); - uint32_t dmalen = esp_get_tc(s); uint64_t val = 0; trace_esp_pdma_read(size); - if (dmalen == 0) { - return 0; - } switch (size) { case 1: val = esp_pdma_read(s); @@ -1005,11 +1047,10 @@ static uint64_t sysbus_esp_pdma_read(void *opaque, hwaddr addr, val = (val << 8) | esp_pdma_read(s); break; } - dmalen = esp_get_tc(s); - if (dmalen == 0 && s->pdma_cb) { - esp_lower_drq(s); + if (s->ti_rptr == s->ti_wptr) { + s->ti_wptr = 0; + s->ti_rptr = 0; s->pdma_cb(s); - s->pdma_cb = NULL; } return val; } From patchwork Sun Mar 7 12:08:37 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Cave-Ayland X-Patchwork-Id: 1448649 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4DtglM615wz9sWb for ; Sun, 7 Mar 2021 23:29:35 +1100 (AEDT) Received: from localhost ([::1]:49252 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lIsXN-0001IU-QK for incoming@patchwork.ozlabs.org; Sun, 07 Mar 2021 07:29:33 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:41862) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lIsG6-0002Y5-Vb for qemu-devel@nongnu.org; Sun, 07 Mar 2021 07:11:43 -0500 Received: from mail.ilande.co.uk ([2001:41c9:1:41f::167]:43722 helo=mail.default.ilande.uk0.bigv.io) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lIsG4-00088v-6n for qemu-devel@nongnu.org; Sun, 07 Mar 2021 07:11:42 -0500 Received: from host86-148-34-47.range86-148.btcentralplus.com ([86.148.34.47] helo=kentang.home) by mail.default.ilande.uk0.bigv.io with esmtpsa (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1lIsFo-0002V5-3t; Sun, 07 Mar 2021 12:11:28 +0000 From: Mark Cave-Ayland To: qemu-devel@nongnu.org, peter.maydell@linaro.org Date: Sun, 7 Mar 2021 12:08:37 +0000 Message-Id: <20210307120850.10418-30-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210307120850.10418-1-mark.cave-ayland@ilande.co.uk> References: <20210307120850.10418-1-mark.cave-ayland@ilande.co.uk> MIME-Version: 1.0 X-SA-Exim-Connect-IP: 86.148.34.47 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk Subject: [PULL 29/42] esp: remove pdma_origin from ESPState X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on mail.default.ilande.uk0.bigv.io) Received-SPF: pass client-ip=2001:41c9:1:41f::167; envelope-from=mark.cave-ayland@ilande.co.uk; helo=mail.default.ilande.uk0.bigv.io X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Now that all data is transferred via the FIFO (ti_buf) there is no need to track the source buffer being used for the data transfer. This also eliminates the need for a separate subsection for PDMA state migration. Signed-off-by: Mark Cave-Ayland Reviewed-by: Laurent Vivier Message-Id: <20210304221103.6369-30-mark.cave-ayland@ilande.co.uk> --- hw/scsi/esp.c | 74 +++++-------------------------------------- include/hw/scsi/esp.h | 6 ---- 2 files changed, 8 insertions(+), 72 deletions(-) diff --git a/hw/scsi/esp.c b/hw/scsi/esp.c index aa897a4ebd..79b84e31d3 100644 --- a/hw/scsi/esp.c +++ b/hw/scsi/esp.c @@ -127,32 +127,14 @@ static uint32_t esp_get_stc(ESPState *s) return dmalen; } -static void set_pdma(ESPState *s, enum pdma_origin_id origin) -{ - s->pdma_origin = origin; -} - static uint8_t esp_pdma_read(ESPState *s) { uint8_t val; - switch (s->pdma_origin) { - case TI: - if (s->do_cmd) { - val = s->cmdbuf[s->cmdlen++]; - } else { - val = s->ti_buf[s->ti_rptr++]; - } - break; - case ASYNC: - val = s->async_buf[0]; - if (s->async_len > 0) { - s->async_len--; - s->async_buf++; - } - break; - default: - g_assert_not_reached(); + if (s->do_cmd) { + val = s->cmdbuf[s->cmdlen++]; + } else { + val = s->ti_buf[s->ti_rptr++]; } return val; @@ -166,23 +148,10 @@ static void esp_pdma_write(ESPState *s, uint8_t val) return; } - switch (s->pdma_origin) { - case TI: - if (s->do_cmd) { - s->cmdbuf[s->cmdlen++] = val; - } else { - s->ti_buf[s->ti_wptr++] = val; - } - break; - case ASYNC: - s->async_buf[0] = val; - if (s->async_len > 0) { - s->async_len--; - s->async_buf++; - } - break; - default: - g_assert_not_reached(); + if (s->do_cmd) { + s->cmdbuf[s->cmdlen++] = val; + } else { + s->ti_buf[s->ti_wptr++] = val; } dmalen--; @@ -232,7 +201,6 @@ static uint32_t get_cmd(ESPState *s) if (s->dma_memory_read) { s->dma_memory_read(s->dma_opaque, buf, dmalen); } else { - set_pdma(s, TI); if (esp_select(s) < 0) { return -1; } @@ -411,7 +379,6 @@ static void write_response(ESPState *s) s->rregs[ESP_RINTR] = INTR_BS | INTR_FC; s->rregs[ESP_RSEQ] = SEQ_CD; } else { - set_pdma(s, TI); s->pdma_cb = write_response_pdma_cb; esp_raise_drq(s); return; @@ -522,7 +489,6 @@ static void esp_do_dma(ESPState *s) if (s->dma_memory_read) { s->dma_memory_read(s->dma_opaque, &s->cmdbuf[s->cmdlen], len); } else { - set_pdma(s, TI); s->pdma_cb = do_dma_pdma_cb; esp_raise_drq(s); return; @@ -545,7 +511,6 @@ static void esp_do_dma(ESPState *s) if (s->dma_memory_read) { s->dma_memory_read(s->dma_opaque, s->async_buf, len); } else { - set_pdma(s, TI); s->pdma_cb = do_dma_pdma_cb; esp_raise_drq(s); return; @@ -562,7 +527,6 @@ static void esp_do_dma(ESPState *s) s->async_len -= len; s->ti_size -= len; esp_set_tc(s, esp_get_tc(s) - len); - set_pdma(s, TI); s->pdma_cb = do_dma_pdma_cb; esp_raise_drq(s); @@ -898,24 +862,6 @@ static bool esp_mem_accepts(void *opaque, hwaddr addr, return (size == 1) || (is_write && size == 4); } -static bool esp_pdma_needed(void *opaque) -{ - ESPState *s = opaque; - return s->dma_memory_read == NULL && s->dma_memory_write == NULL && - s->dma_enabled; -} - -static const VMStateDescription vmstate_esp_pdma = { - .name = "esp/pdma", - .version_id = 2, - .minimum_version_id = 2, - .needed = esp_pdma_needed, - .fields = (VMStateField[]) { - VMSTATE_INT32(pdma_origin, ESPState), - VMSTATE_END_OF_LIST() - } -}; - static bool esp_is_before_version_5(void *opaque, int version_id) { ESPState *s = ESP(opaque); @@ -970,10 +916,6 @@ const VMStateDescription vmstate_esp = { VMSTATE_UINT32_TEST(mig_dma_left, ESPState, esp_is_before_version_5), VMSTATE_END_OF_LIST() }, - .subsections = (const VMStateDescription * []) { - &vmstate_esp_pdma, - NULL - } }; static void sysbus_esp_mem_write(void *opaque, hwaddr addr, diff --git a/include/hw/scsi/esp.h b/include/hw/scsi/esp.h index dbbbb3fc52..91f8ffd6c8 100644 --- a/include/hw/scsi/esp.h +++ b/include/hw/scsi/esp.h @@ -15,11 +15,6 @@ typedef void (*ESPDMAMemoryReadWriteFunc)(void *opaque, uint8_t *buf, int len); typedef struct ESPState ESPState; -enum pdma_origin_id { - TI, - ASYNC, -}; - #define TYPE_ESP "esp" OBJECT_DECLARE_SIMPLE_TYPE(ESPState, ESP) @@ -55,7 +50,6 @@ struct ESPState { ESPDMAMemoryReadWriteFunc dma_memory_write; void *dma_opaque; void (*dma_cb)(ESPState *s); - int pdma_origin; void (*pdma_cb)(ESPState *s); uint8_t mig_version_id; From patchwork Sun Mar 7 12:08:38 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Mark Cave-Ayland X-Patchwork-Id: 1448668 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4DthCk5jsCz9sW5 for ; Sun, 7 Mar 2021 23:50:42 +1100 (AEDT) Received: from localhost ([::1]:36002 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lIsro-0002l1-K5 for incoming@patchwork.ozlabs.org; Sun, 07 Mar 2021 07:50:40 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:41874) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lIsG8-0002cd-VO for qemu-devel@nongnu.org; Sun, 07 Mar 2021 07:11:44 -0500 Received: from mail.ilande.co.uk ([2001:41c9:1:41f::167]:43730 helo=mail.default.ilande.uk0.bigv.io) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lIsG7-0008AL-AO for qemu-devel@nongnu.org; Sun, 07 Mar 2021 07:11:44 -0500 Received: from host86-148-34-47.range86-148.btcentralplus.com ([86.148.34.47] helo=kentang.home) by mail.default.ilande.uk0.bigv.io with esmtpsa (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1lIsFs-0002V5-6R; Sun, 07 Mar 2021 12:11:32 +0000 From: Mark Cave-Ayland To: qemu-devel@nongnu.org, peter.maydell@linaro.org Date: Sun, 7 Mar 2021 12:08:38 +0000 Message-Id: <20210307120850.10418-31-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210307120850.10418-1-mark.cave-ayland@ilande.co.uk> References: <20210307120850.10418-1-mark.cave-ayland@ilande.co.uk> MIME-Version: 1.0 X-SA-Exim-Connect-IP: 86.148.34.47 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk Subject: [PULL 30/42] esp: add 4 byte PDMA read and write transfers X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on mail.default.ilande.uk0.bigv.io) Received-SPF: pass client-ip=2001:41c9:1:41f::167; envelope-from=mark.cave-ayland@ilande.co.uk; helo=mail.default.ilande.uk0.bigv.io X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" The MacOS toolbox ROM performs 4 byte reads/writes when transferring data to and from the target. Since the SCSI bus is 16-bits wide, use the memory API to split a 4 byte access into 2 x 2 byte accesses. Signed-off-by: Mark Cave-Ayland Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Laurent Vivier Message-Id: <20210304221103.6369-31-mark.cave-ayland@ilande.co.uk> --- hw/scsi/esp.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/hw/scsi/esp.c b/hw/scsi/esp.c index 79b84e31d3..2dded90be6 100644 --- a/hw/scsi/esp.c +++ b/hw/scsi/esp.c @@ -1002,7 +1002,9 @@ static const MemoryRegionOps sysbus_esp_pdma_ops = { .write = sysbus_esp_pdma_write, .endianness = DEVICE_NATIVE_ENDIAN, .valid.min_access_size = 1, - .valid.max_access_size = 2, + .valid.max_access_size = 4, + .impl.min_access_size = 1, + .impl.max_access_size = 2, }; static const struct SCSIBusInfo esp_scsi_info = { @@ -1049,7 +1051,7 @@ static void sysbus_esp_realize(DeviceState *dev, Error **errp) sysbus, "esp-regs", ESP_REGS << sysbus->it_shift); sysbus_init_mmio(sbd, &sysbus->iomem); memory_region_init_io(&sysbus->pdma, OBJECT(sysbus), &sysbus_esp_pdma_ops, - sysbus, "esp-pdma", 2); + sysbus, "esp-pdma", 4); sysbus_init_mmio(sbd, &sysbus->pdma); qdev_init_gpio_in(dev, sysbus_esp_gpio_demux, 2); From patchwork Sun Mar 7 12:08:39 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Cave-Ayland X-Patchwork-Id: 1448671 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4DthGV1rGwz9sW5 for ; Sun, 7 Mar 2021 23:53:06 +1100 (AEDT) Received: from localhost ([::1]:42284 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lIsu8-0005VF-AB for incoming@patchwork.ozlabs.org; Sun, 07 Mar 2021 07:53:04 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:41900) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lIsGF-0002uR-7m for qemu-devel@nongnu.org; Sun, 07 Mar 2021 07:11:51 -0500 Received: from mail.ilande.co.uk ([2001:41c9:1:41f::167]:43738 helo=mail.default.ilande.uk0.bigv.io) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lIsGD-0008BX-Jy for qemu-devel@nongnu.org; Sun, 07 Mar 2021 07:11:50 -0500 Received: from host86-148-34-47.range86-148.btcentralplus.com ([86.148.34.47] helo=kentang.home) by mail.default.ilande.uk0.bigv.io with esmtpsa (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1lIsFx-0002V5-0o; Sun, 07 Mar 2021 12:11:39 +0000 From: Mark Cave-Ayland To: qemu-devel@nongnu.org, peter.maydell@linaro.org Date: Sun, 7 Mar 2021 12:08:39 +0000 Message-Id: <20210307120850.10418-32-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210307120850.10418-1-mark.cave-ayland@ilande.co.uk> References: <20210307120850.10418-1-mark.cave-ayland@ilande.co.uk> MIME-Version: 1.0 X-SA-Exim-Connect-IP: 86.148.34.47 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk Subject: [PULL 31/42] esp: implement FIFO flush command X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on mail.default.ilande.uk0.bigv.io) Received-SPF: pass client-ip=2001:41c9:1:41f::167; envelope-from=mark.cave-ayland@ilande.co.uk; helo=mail.default.ilande.uk0.bigv.io X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" At this point it is now possible to properly implement the FIFO flush command without causing guest errors. Signed-off-by: Mark Cave-Ayland Reviewed-by: Laurent Vivier Message-Id: <20210304221103.6369-32-mark.cave-ayland@ilande.co.uk> --- hw/scsi/esp.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/hw/scsi/esp.c b/hw/scsi/esp.c index 2dded90be6..6aae6f91c2 100644 --- a/hw/scsi/esp.c +++ b/hw/scsi/esp.c @@ -769,6 +769,8 @@ void esp_reg_write(ESPState *s, uint32_t saddr, uint64_t val) case CMD_FLUSH: trace_esp_mem_writeb_cmd_flush(val); /*s->ti_size = 0;*/ + s->ti_wptr = 0; + s->ti_rptr = 0; s->rregs[ESP_RINTR] = INTR_FC; s->rregs[ESP_RSEQ] = 0; s->rregs[ESP_RFLAGS] = 0; From patchwork Sun Mar 7 12:08:40 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Cave-Ayland X-Patchwork-Id: 1448654 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4Dtgrr63mXz9sWP for ; Sun, 7 Mar 2021 23:34:20 +1100 (AEDT) Received: from localhost ([::1]:34624 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lIsby-00073z-Sv for incoming@patchwork.ozlabs.org; Sun, 07 Mar 2021 07:34:18 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:41930) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lIsGL-0003C7-NV for qemu-devel@nongnu.org; Sun, 07 Mar 2021 07:11:57 -0500 Received: from mail.ilande.co.uk ([2001:41c9:1:41f::167]:43742 helo=mail.default.ilande.uk0.bigv.io) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lIsGJ-0008Cs-Ro for qemu-devel@nongnu.org; Sun, 07 Mar 2021 07:11:57 -0500 Received: from host86-148-34-47.range86-148.btcentralplus.com ([86.148.34.47] helo=kentang.home) by mail.default.ilande.uk0.bigv.io with esmtpsa (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1lIsG3-0002V5-AF; Sun, 07 Mar 2021 12:11:45 +0000 From: Mark Cave-Ayland To: qemu-devel@nongnu.org, peter.maydell@linaro.org Date: Sun, 7 Mar 2021 12:08:40 +0000 Message-Id: <20210307120850.10418-33-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210307120850.10418-1-mark.cave-ayland@ilande.co.uk> References: <20210307120850.10418-1-mark.cave-ayland@ilande.co.uk> MIME-Version: 1.0 X-SA-Exim-Connect-IP: 86.148.34.47 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk Subject: [PULL 32/42] esp: latch individual bits in ESP_RINTR register X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on mail.default.ilande.uk0.bigv.io) Received-SPF: pass client-ip=2001:41c9:1:41f::167; envelope-from=mark.cave-ayland@ilande.co.uk; helo=mail.default.ilande.uk0.bigv.io X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Currently the ESP_RINTR register is set to a specific value as required within the ESP state machine. In order to implement the upcoming deferred interrupt functionality it is necessary to set individual bits within ESP_RINTR so that a deferred interrupt will not overwrite the value of any other interrupt bits. This also requires fixing up a few locations where the ESP_RINTR and ESP_RSEQ registers are set/reset unexpectedly. Signed-off-by: Mark Cave-Ayland Reviewed-by: Laurent Vivier Message-Id: <20210304221103.6369-33-mark.cave-ayland@ilande.co.uk> --- hw/scsi/esp.c | 29 +++++++++++++---------------- 1 file changed, 13 insertions(+), 16 deletions(-) diff --git a/hw/scsi/esp.c b/hw/scsi/esp.c index 6aae6f91c2..54d008c609 100644 --- a/hw/scsi/esp.c +++ b/hw/scsi/esp.c @@ -178,7 +178,7 @@ static int esp_select(ESPState *s) if (!s->current_dev) { /* No such drive */ s->rregs[ESP_RSTAT] = 0; - s->rregs[ESP_RINTR] = INTR_DC; + s->rregs[ESP_RINTR] |= INTR_DC; s->rregs[ESP_RSEQ] = SEQ_0; esp_raise_irq(s); return -1; @@ -245,7 +245,7 @@ static void do_busid_cmd(ESPState *s, uint8_t *buf, uint8_t busid) } scsi_req_continue(s->current_req); } - s->rregs[ESP_RINTR] = INTR_BS | INTR_FC; + s->rregs[ESP_RINTR] |= INTR_BS | INTR_FC; s->rregs[ESP_RSEQ] = SEQ_CD; esp_raise_irq(s); esp_lower_drq(s); @@ -326,7 +326,7 @@ static void satn_stop_pdma_cb(ESPState *s) trace_esp_handle_satn_stop(s->cmdlen); s->do_cmd = 1; s->rregs[ESP_RSTAT] = STAT_TC | STAT_CD; - s->rregs[ESP_RINTR] = INTR_BS | INTR_FC; + s->rregs[ESP_RINTR] |= INTR_BS | INTR_FC; s->rregs[ESP_RSEQ] = SEQ_CD; esp_raise_irq(s); } @@ -346,8 +346,8 @@ static void handle_satn_stop(ESPState *s) trace_esp_handle_satn_stop(s->cmdlen); s->cmdlen = cmdlen; s->do_cmd = 1; - s->rregs[ESP_RSTAT] = STAT_TC | STAT_CD; - s->rregs[ESP_RINTR] = INTR_BS | INTR_FC; + s->rregs[ESP_RSTAT] = STAT_CD; + s->rregs[ESP_RINTR] |= INTR_BS | INTR_FC; s->rregs[ESP_RSEQ] = SEQ_CD; esp_raise_irq(s); } else if (cmdlen == 0) { @@ -362,7 +362,7 @@ static void handle_satn_stop(ESPState *s) static void write_response_pdma_cb(ESPState *s) { s->rregs[ESP_RSTAT] = STAT_TC | STAT_ST; - s->rregs[ESP_RINTR] = INTR_BS | INTR_FC; + s->rregs[ESP_RINTR] |= INTR_BS | INTR_FC; s->rregs[ESP_RSEQ] = SEQ_CD; esp_raise_irq(s); } @@ -376,7 +376,7 @@ static void write_response(ESPState *s) if (s->dma_memory_write) { s->dma_memory_write(s->dma_opaque, s->ti_buf, 2); s->rregs[ESP_RSTAT] = STAT_TC | STAT_ST; - s->rregs[ESP_RINTR] = INTR_BS | INTR_FC; + s->rregs[ESP_RINTR] |= INTR_BS | INTR_FC; s->rregs[ESP_RSEQ] = SEQ_CD; } else { s->pdma_cb = write_response_pdma_cb; @@ -395,7 +395,7 @@ static void write_response(ESPState *s) static void esp_dma_done(ESPState *s) { s->rregs[ESP_RSTAT] |= STAT_TC; - s->rregs[ESP_RINTR] = INTR_BS; + s->rregs[ESP_RINTR] |= INTR_BS; s->rregs[ESP_RSEQ] = 0; s->rregs[ESP_RFLAGS] = 0; esp_set_tc(s, 0); @@ -700,7 +700,7 @@ uint64_t esp_reg_read(ESPState *s, uint32_t saddr) val = s->rregs[ESP_RINTR]; s->rregs[ESP_RINTR] = 0; s->rregs[ESP_RSTAT] &= ~STAT_TC; - s->rregs[ESP_RSEQ] = SEQ_CD; + s->rregs[ESP_RSEQ] = SEQ_0; esp_lower_irq(s); if (s->deferred_complete) { esp_report_command_complete(s, s->deferred_status); @@ -771,9 +771,6 @@ void esp_reg_write(ESPState *s, uint32_t saddr, uint64_t val) /*s->ti_size = 0;*/ s->ti_wptr = 0; s->ti_rptr = 0; - s->rregs[ESP_RINTR] = INTR_FC; - s->rregs[ESP_RSEQ] = 0; - s->rregs[ESP_RFLAGS] = 0; break; case CMD_RESET: trace_esp_mem_writeb_cmd_reset(val); @@ -781,8 +778,8 @@ void esp_reg_write(ESPState *s, uint32_t saddr, uint64_t val) break; case CMD_BUSRESET: trace_esp_mem_writeb_cmd_bus_reset(val); - s->rregs[ESP_RINTR] = INTR_RST; if (!(s->wregs[ESP_CFG1] & CFG1_RESREPT)) { + s->rregs[ESP_RINTR] |= INTR_RST; esp_raise_irq(s); } break; @@ -793,12 +790,12 @@ void esp_reg_write(ESPState *s, uint32_t saddr, uint64_t val) case CMD_ICCS: trace_esp_mem_writeb_cmd_iccs(val); write_response(s); - s->rregs[ESP_RINTR] = INTR_FC; + s->rregs[ESP_RINTR] |= INTR_FC; s->rregs[ESP_RSTAT] |= STAT_MI; break; case CMD_MSGACC: trace_esp_mem_writeb_cmd_msgacc(val); - s->rregs[ESP_RINTR] = INTR_DC; + s->rregs[ESP_RINTR] |= INTR_DC; s->rregs[ESP_RSEQ] = 0; s->rregs[ESP_RFLAGS] = 0; esp_raise_irq(s); @@ -806,7 +803,7 @@ void esp_reg_write(ESPState *s, uint32_t saddr, uint64_t val) case CMD_PAD: trace_esp_mem_writeb_cmd_pad(val); s->rregs[ESP_RSTAT] = STAT_TC; - s->rregs[ESP_RINTR] = INTR_FC; + s->rregs[ESP_RINTR] |= INTR_FC; s->rregs[ESP_RSEQ] = 0; break; case CMD_SATN: From patchwork Sun Mar 7 12:08:41 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Cave-Ayland X-Patchwork-Id: 1448658 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4DtgwG1rkrz9sWP for ; Sun, 7 Mar 2021 23:37:17 +1100 (AEDT) Received: from localhost ([::1]:43140 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lIsep-00028w-9Y for incoming@patchwork.ozlabs.org; Sun, 07 Mar 2021 07:37:15 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:41942) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lIsGT-0003GJ-8K for qemu-devel@nongnu.org; Sun, 07 Mar 2021 07:12:07 -0500 Received: from mail.ilande.co.uk ([2001:41c9:1:41f::167]:43748 helo=mail.default.ilande.uk0.bigv.io) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lIsGO-0008EK-Ph for qemu-devel@nongnu.org; Sun, 07 Mar 2021 07:12:05 -0500 Received: from host86-148-34-47.range86-148.btcentralplus.com ([86.148.34.47] helo=kentang.home) by mail.default.ilande.uk0.bigv.io with esmtpsa (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1lIsG9-0002V5-MM; Sun, 07 Mar 2021 12:11:50 +0000 From: Mark Cave-Ayland To: qemu-devel@nongnu.org, peter.maydell@linaro.org Date: Sun, 7 Mar 2021 12:08:41 +0000 Message-Id: <20210307120850.10418-34-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210307120850.10418-1-mark.cave-ayland@ilande.co.uk> References: <20210307120850.10418-1-mark.cave-ayland@ilande.co.uk> MIME-Version: 1.0 X-SA-Exim-Connect-IP: 86.148.34.47 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk Subject: [PULL 33/42] esp: defer command completion interrupt on incoming data transfers X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on mail.default.ilande.uk0.bigv.io) Received-SPF: pass client-ip=2001:41c9:1:41f::167; envelope-from=mark.cave-ayland@ilande.co.uk; helo=mail.default.ilande.uk0.bigv.io X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" The MacOS toolbox ROM issues a command to the ESP controller as part of its "FAST" SCSI routines and then proceeds to read the incoming data soon after receiving the command completion interrupt. Unfortunately due to SCSI block transfers being asynchronous the incoming data may not yet be present causing an underflow error. Resolve this by waiting for the SCSI subsystem transfer_data callback before raising the command completion interrupt. Signed-off-by: Mark Cave-Ayland Reviewed-by: Laurent Vivier Message-Id: <20210304221103.6369-34-mark.cave-ayland@ilande.co.uk> --- hw/scsi/esp.c | 66 ++++++++++++++++++++++++++++++++++--------- include/hw/scsi/esp.h | 1 + 2 files changed, 54 insertions(+), 13 deletions(-) diff --git a/hw/scsi/esp.c b/hw/scsi/esp.c index 54d008c609..0eecc1d05c 100644 --- a/hw/scsi/esp.c +++ b/hw/scsi/esp.c @@ -183,6 +183,14 @@ static int esp_select(ESPState *s) esp_raise_irq(s); return -1; } + + /* + * Note that we deliberately don't raise the IRQ here: this will be done + * either in do_busid_cmd() for DATA OUT transfers or by the deferred + * IRQ mechanism in esp_transfer_data() for DATA IN transfers + */ + s->rregs[ESP_RINTR] |= INTR_FC; + s->rregs[ESP_RSEQ] = SEQ_CD; return 0; } @@ -237,18 +245,24 @@ static void do_busid_cmd(ESPState *s, uint8_t *buf, uint8_t busid) s->ti_size = datalen; if (datalen != 0) { s->rregs[ESP_RSTAT] = STAT_TC; + s->rregs[ESP_RSEQ] = SEQ_CD; esp_set_tc(s, 0); if (datalen > 0) { + /* + * Switch to DATA IN phase but wait until initial data xfer is + * complete before raising the command completion interrupt + */ + s->data_in_ready = false; s->rregs[ESP_RSTAT] |= STAT_DI; } else { s->rregs[ESP_RSTAT] |= STAT_DO; + s->rregs[ESP_RINTR] |= INTR_BS | INTR_FC; + esp_raise_irq(s); + esp_lower_drq(s); } scsi_req_continue(s->current_req); + return; } - s->rregs[ESP_RINTR] |= INTR_BS | INTR_FC; - s->rregs[ESP_RSEQ] = SEQ_CD; - esp_raise_irq(s); - esp_lower_drq(s); } static void do_cmd(ESPState *s) @@ -439,17 +453,11 @@ static void do_dma_pdma_cb(ESPState *s) } else { if (s->async_len == 0) { if (s->current_req) { + /* Defer until the scsi layer has completed */ scsi_req_continue(s->current_req); + s->data_in_ready = false; } - - /* - * If there is still data to be read from the device then - * complete the DMA operation immediately. Otherwise defer - * until the scsi layer has completed. - */ - if (esp_get_tc(s) != 0 || s->ti_size == 0) { - return; - } + return; } if (esp_get_tc(s) != 0) { @@ -602,12 +610,35 @@ void esp_command_complete(SCSIRequest *req, size_t resid) void esp_transfer_data(SCSIRequest *req, uint32_t len) { ESPState *s = req->hba_private; + int to_device = ((s->rregs[ESP_RSTAT] & 7) == STAT_DO); uint32_t dmalen = esp_get_tc(s); assert(!s->do_cmd); trace_esp_transfer_data(dmalen, s->ti_size); s->async_len = len; s->async_buf = scsi_req_get_buf(req); + + if (!to_device && !s->data_in_ready) { + /* + * Initial incoming data xfer is complete so raise command + * completion interrupt + */ + s->data_in_ready = true; + s->rregs[ESP_RSTAT] |= STAT_TC; + s->rregs[ESP_RINTR] |= INTR_BS; + esp_raise_irq(s); + + /* + * If data is ready to transfer and the TI command has already + * been executed, start DMA immediately. Otherwise DMA will start + * when host sends the TI command + */ + if (s->ti_size && (s->rregs[ESP_CMD] == (CMD_TI | CMD_DMA))) { + esp_do_dma(s); + } + return; + } + if (dmalen) { esp_do_dma(s); } else if (s->ti_size <= 0) { @@ -869,6 +900,14 @@ static bool esp_is_before_version_5(void *opaque, int version_id) return version_id < 5; } +static bool esp_is_version_5(void *opaque, int version_id) +{ + ESPState *s = ESP(opaque); + + version_id = MIN(version_id, s->mig_version_id); + return version_id == 5; +} + static int esp_pre_save(void *opaque) { ESPState *s = ESP(opaque); @@ -913,6 +952,7 @@ const VMStateDescription vmstate_esp = { VMSTATE_UINT32(cmdlen, ESPState), VMSTATE_UINT32(do_cmd, ESPState), VMSTATE_UINT32_TEST(mig_dma_left, ESPState, esp_is_before_version_5), + VMSTATE_BOOL_TEST(data_in_ready, ESPState, esp_is_version_5), VMSTATE_END_OF_LIST() }, }; diff --git a/include/hw/scsi/esp.h b/include/hw/scsi/esp.h index 91f8ffd6c8..61bc317a4c 100644 --- a/include/hw/scsi/esp.h +++ b/include/hw/scsi/esp.h @@ -41,6 +41,7 @@ struct ESPState { uint32_t cmdlen; uint32_t do_cmd; + bool data_in_ready; int dma_enabled; uint32_t async_len; From patchwork Sun Mar 7 12:08:42 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Cave-Ayland X-Patchwork-Id: 1448655 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4DtgsJ2516z9sWP for ; Sun, 7 Mar 2021 23:34:44 +1100 (AEDT) Received: from localhost ([::1]:35974 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lIscM-0007bu-9T for incoming@patchwork.ozlabs.org; Sun, 07 Mar 2021 07:34:42 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:41956) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lIsGW-0003HV-Oq for qemu-devel@nongnu.org; Sun, 07 Mar 2021 07:12:10 -0500 Received: from mail.ilande.co.uk ([2001:41c9:1:41f::167]:43752 helo=mail.default.ilande.uk0.bigv.io) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lIsGT-0008Fl-V8 for qemu-devel@nongnu.org; Sun, 07 Mar 2021 07:12:08 -0500 Received: from host86-148-34-47.range86-148.btcentralplus.com ([86.148.34.47] helo=kentang.home) by mail.default.ilande.uk0.bigv.io with esmtpsa (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1lIsGE-0002V5-HL; Sun, 07 Mar 2021 12:11:55 +0000 From: Mark Cave-Ayland To: qemu-devel@nongnu.org, peter.maydell@linaro.org Date: Sun, 7 Mar 2021 12:08:42 +0000 Message-Id: <20210307120850.10418-35-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210307120850.10418-1-mark.cave-ayland@ilande.co.uk> References: <20210307120850.10418-1-mark.cave-ayland@ilande.co.uk> MIME-Version: 1.0 X-SA-Exim-Connect-IP: 86.148.34.47 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk Subject: [PULL 34/42] esp: remove old deferred command completion mechanism X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on mail.default.ilande.uk0.bigv.io) Received-SPF: pass client-ip=2001:41c9:1:41f::167; envelope-from=mark.cave-ayland@ilande.co.uk; helo=mail.default.ilande.uk0.bigv.io X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Commit ea84a44250 "scsi: esp: Defer command completion until previous interrupts have been handled" provided a mechanism to delay the command completion interrupt until ESP_RINTR is read after the command has completed. With the previous fixes for latching the ESP_RINTR bits and deferring the setting of the command completion interrupt for incoming data to the SCSI callback, this workaround is no longer required and can be removed. Signed-off-by: Mark Cave-Ayland Reviewed-by: Laurent Vivier Message-Id: <20210304221103.6369-35-mark.cave-ayland@ilande.co.uk> --- hw/scsi/esp.c | 35 +++++++++-------------------------- include/hw/scsi/esp.h | 4 ++-- 2 files changed, 11 insertions(+), 28 deletions(-) diff --git a/hw/scsi/esp.c b/hw/scsi/esp.c index 0eecc1d05c..eb6681ca66 100644 --- a/hw/scsi/esp.c +++ b/hw/scsi/esp.c @@ -568,18 +568,20 @@ static void esp_do_dma(ESPState *s) esp_lower_drq(s); } -static void esp_report_command_complete(ESPState *s, uint32_t status) +void esp_command_complete(SCSIRequest *req, size_t resid) { + ESPState *s = req->hba_private; + trace_esp_command_complete(); if (s->ti_size != 0) { trace_esp_command_complete_unexpected(); } s->ti_size = 0; s->async_len = 0; - if (status) { + if (req->status) { trace_esp_command_complete_fail(); } - s->status = status; + s->status = req->status; s->rregs[ESP_RSTAT] = STAT_ST; esp_dma_done(s); esp_lower_drq(s); @@ -590,23 +592,6 @@ static void esp_report_command_complete(ESPState *s, uint32_t status) } } -void esp_command_complete(SCSIRequest *req, size_t resid) -{ - ESPState *s = req->hba_private; - - if (s->rregs[ESP_RSTAT] & STAT_INT) { - /* - * Defer handling command complete until the previous - * interrupt has been handled. - */ - trace_esp_command_complete_deferred(); - s->deferred_status = req->status; - s->deferred_complete = true; - return; - } - esp_report_command_complete(s, req->status); -} - void esp_transfer_data(SCSIRequest *req, uint32_t len) { ESPState *s = req->hba_private; @@ -733,10 +718,6 @@ uint64_t esp_reg_read(ESPState *s, uint32_t saddr) s->rregs[ESP_RSTAT] &= ~STAT_TC; s->rregs[ESP_RSEQ] = SEQ_0; esp_lower_irq(s); - if (s->deferred_complete) { - esp_report_command_complete(s, s->deferred_status); - s->deferred_complete = false; - } break; case ESP_TCHI: /* Return the unique id if the value has never been written */ @@ -944,8 +925,10 @@ const VMStateDescription vmstate_esp = { VMSTATE_UINT32(ti_wptr, ESPState), VMSTATE_BUFFER(ti_buf, ESPState), VMSTATE_UINT32(status, ESPState), - VMSTATE_UINT32(deferred_status, ESPState), - VMSTATE_BOOL(deferred_complete, ESPState), + VMSTATE_UINT32_TEST(mig_deferred_status, ESPState, + esp_is_before_version_5), + VMSTATE_BOOL_TEST(mig_deferred_complete, ESPState, + esp_is_before_version_5), VMSTATE_UINT32(dma, ESPState), VMSTATE_PARTIAL_BUFFER(cmdbuf, ESPState, 16), VMSTATE_BUFFER_START_MIDDLE_V(cmdbuf, ESPState, 16, 4), diff --git a/include/hw/scsi/esp.h b/include/hw/scsi/esp.h index 61bc317a4c..7d88fa0f92 100644 --- a/include/hw/scsi/esp.h +++ b/include/hw/scsi/esp.h @@ -30,8 +30,6 @@ struct ESPState { int32_t ti_size; uint32_t ti_rptr, ti_wptr; uint32_t status; - uint32_t deferred_status; - bool deferred_complete; uint32_t dma; uint8_t ti_buf[TI_BUFSZ]; SCSIBus bus; @@ -57,6 +55,8 @@ struct ESPState { /* Legacy fields for vmstate_esp version < 5 */ uint32_t mig_dma_left; + uint32_t mig_deferred_status; + bool mig_deferred_complete; }; #define TYPE_SYSBUS_ESP "sysbus-esp" From patchwork Sun Mar 7 12:08:43 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Cave-Ayland X-Patchwork-Id: 1448667 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4DthC96syrz9sW5 for ; Sun, 7 Mar 2021 23:50:10 +1100 (AEDT) Received: from localhost ([::1]:35018 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lIsrH-0002Kz-Ve for incoming@patchwork.ozlabs.org; Sun, 07 Mar 2021 07:50:08 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:41994) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lIsGe-0003NO-VA for qemu-devel@nongnu.org; Sun, 07 Mar 2021 07:12:17 -0500 Received: from mail.ilande.co.uk ([2001:41c9:1:41f::167]:43758 helo=mail.default.ilande.uk0.bigv.io) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lIsGa-0008Hx-2Y for qemu-devel@nongnu.org; Sun, 07 Mar 2021 07:12:15 -0500 Received: from host86-148-34-47.range86-148.btcentralplus.com ([86.148.34.47] helo=kentang.home) by mail.default.ilande.uk0.bigv.io with esmtpsa (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1lIsGJ-0002V5-OA; Sun, 07 Mar 2021 12:12:00 +0000 From: Mark Cave-Ayland To: qemu-devel@nongnu.org, peter.maydell@linaro.org Date: Sun, 7 Mar 2021 12:08:43 +0000 Message-Id: <20210307120850.10418-36-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210307120850.10418-1-mark.cave-ayland@ilande.co.uk> References: <20210307120850.10418-1-mark.cave-ayland@ilande.co.uk> MIME-Version: 1.0 X-SA-Exim-Connect-IP: 86.148.34.47 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk Subject: [PULL 35/42] esp: raise interrupt after every non-DMA byte transferred to the FIFO X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on mail.default.ilande.uk0.bigv.io) Received-SPF: pass client-ip=2001:41c9:1:41f::167; envelope-from=mark.cave-ayland@ilande.co.uk; helo=mail.default.ilande.uk0.bigv.io X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" This matches the description in the datasheet and is required as support for non-DMA transfers is added. Signed-off-by: Mark Cave-Ayland Reviewed-by: Laurent Vivier Message-Id: <20210304221103.6369-36-mark.cave-ayland@ilande.co.uk> --- hw/scsi/esp.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/hw/scsi/esp.c b/hw/scsi/esp.c index eb6681ca66..4ac299651f 100644 --- a/hw/scsi/esp.c +++ b/hw/scsi/esp.c @@ -760,6 +760,12 @@ void esp_reg_write(ESPState *s, uint32_t saddr, uint64_t val) s->ti_size++; s->ti_buf[s->ti_wptr++] = val & 0xff; } + + /* Non-DMA transfers raise an interrupt after every byte */ + if (s->rregs[ESP_CMD] == CMD_TI) { + s->rregs[ESP_RINTR] |= INTR_FC | INTR_BS; + esp_raise_irq(s); + } break; case ESP_CMD: s->rregs[saddr] = val; From patchwork Sun Mar 7 12:08:44 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Mark Cave-Ayland X-Patchwork-Id: 1448662 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4Dth2s6YT6z9sWP for ; Sun, 7 Mar 2021 23:42:58 +1100 (AEDT) Received: from localhost ([::1]:51620 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lIskI-0005iJ-HI for incoming@patchwork.ozlabs.org; Sun, 07 Mar 2021 07:42:54 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:42008) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lIsGk-0003TU-1E for qemu-devel@nongnu.org; Sun, 07 Mar 2021 07:12:22 -0500 Received: from mail.ilande.co.uk ([2001:41c9:1:41f::167]:43766 helo=mail.default.ilande.uk0.bigv.io) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lIsGe-0008Ik-6v for qemu-devel@nongnu.org; Sun, 07 Mar 2021 07:12:21 -0500 Received: from host86-148-34-47.range86-148.btcentralplus.com ([86.148.34.47] helo=kentang.home) by mail.default.ilande.uk0.bigv.io with esmtpsa (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1lIsGO-0002V5-OC; Sun, 07 Mar 2021 12:12:05 +0000 From: Mark Cave-Ayland To: qemu-devel@nongnu.org, peter.maydell@linaro.org Date: Sun, 7 Mar 2021 12:08:44 +0000 Message-Id: <20210307120850.10418-37-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210307120850.10418-1-mark.cave-ayland@ilande.co.uk> References: <20210307120850.10418-1-mark.cave-ayland@ilande.co.uk> MIME-Version: 1.0 X-SA-Exim-Connect-IP: 86.148.34.47 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk Subject: [PULL 36/42] esp: add maxlen parameter to get_cmd() X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on mail.default.ilande.uk0.bigv.io) Received-SPF: pass client-ip=2001:41c9:1:41f::167; envelope-from=mark.cave-ayland@ilande.co.uk; helo=mail.default.ilande.uk0.bigv.io X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Some guests use a mixture of DMA and non-DMA transfers in combination with the SATN and stop command to transfer message out phase and command phase bytes to the target. Prepare for the next commit by adding a maxlen parameter to get_cmd() to allow partial transfers. Signed-off-by: Mark Cave-Ayland Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Laurent Vivier Message-Id: <20210304221103.6369-37-mark.cave-ayland@ilande.co.uk> --- hw/scsi/esp.c | 20 +++++++++++--------- 1 file changed, 11 insertions(+), 9 deletions(-) diff --git a/hw/scsi/esp.c b/hw/scsi/esp.c index 4ac299651f..23fcaa90c1 100644 --- a/hw/scsi/esp.c +++ b/hw/scsi/esp.c @@ -194,7 +194,7 @@ static int esp_select(ESPState *s) return 0; } -static uint32_t get_cmd(ESPState *s) +static uint32_t get_cmd(ESPState *s, uint32_t maxlen) { uint8_t *buf = s->cmdbuf; uint32_t dmalen; @@ -202,8 +202,8 @@ static uint32_t get_cmd(ESPState *s) target = s->wregs[ESP_WBUSID] & BUSID_DID; if (s->dma) { - dmalen = esp_get_tc(s); - if (dmalen > ESP_CMDBUF_SZ) { + dmalen = MIN(esp_get_tc(s), maxlen); + if (dmalen == 0) { return 0; } if (s->dma_memory_read) { @@ -216,12 +216,14 @@ static uint32_t get_cmd(ESPState *s) return 0; } } else { - dmalen = s->ti_size; - if (dmalen > TI_BUFSZ) { + dmalen = MIN(s->ti_size, maxlen); + if (dmalen == 0) { return 0; } memcpy(buf, s->ti_buf, dmalen); - buf[0] = buf[2] >> 5; + if (dmalen >= 3) { + buf[0] = buf[2] >> 5; + } } trace_esp_get_cmd(dmalen, target); @@ -290,7 +292,7 @@ static void handle_satn(ESPState *s) return; } s->pdma_cb = satn_pdma_cb; - cmdlen = get_cmd(s); + cmdlen = get_cmd(s, ESP_CMDBUF_SZ); if (cmdlen > 0) { s->cmdlen = cmdlen; do_cmd(s); @@ -320,7 +322,7 @@ static void handle_s_without_atn(ESPState *s) return; } s->pdma_cb = s_without_satn_pdma_cb; - cmdlen = get_cmd(s); + cmdlen = get_cmd(s, ESP_CMDBUF_SZ); if (cmdlen > 0) { s->cmdlen = cmdlen; do_busid_cmd(s, s->cmdbuf, 0); @@ -355,7 +357,7 @@ static void handle_satn_stop(ESPState *s) return; } s->pdma_cb = satn_stop_pdma_cb; - cmdlen = get_cmd(s); + cmdlen = get_cmd(s, ESP_CMDBUF_SZ); if (cmdlen > 0) { trace_esp_handle_satn_stop(s->cmdlen); s->cmdlen = cmdlen; From patchwork Sun Mar 7 12:08:45 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Cave-Ayland X-Patchwork-Id: 1448659 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4Dtgwn1tzkz9sWb for ; Sun, 7 Mar 2021 23:37:44 +1100 (AEDT) Received: from localhost ([::1]:44582 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lIsfF-0002lh-W5 for incoming@patchwork.ozlabs.org; Sun, 07 Mar 2021 07:37:42 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:42020) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lIsGl-0003XB-Eu for qemu-devel@nongnu.org; Sun, 07 Mar 2021 07:12:23 -0500 Received: from mail.ilande.co.uk ([2001:41c9:1:41f::167]:43772 helo=mail.default.ilande.uk0.bigv.io) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lIsGj-0008K7-F5 for qemu-devel@nongnu.org; Sun, 07 Mar 2021 07:12:23 -0500 Received: from host86-148-34-47.range86-148.btcentralplus.com ([86.148.34.47] helo=kentang.home) by mail.default.ilande.uk0.bigv.io with esmtpsa (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1lIsGU-0002V5-2E; Sun, 07 Mar 2021 12:12:11 +0000 From: Mark Cave-Ayland To: qemu-devel@nongnu.org, peter.maydell@linaro.org Date: Sun, 7 Mar 2021 12:08:45 +0000 Message-Id: <20210307120850.10418-38-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210307120850.10418-1-mark.cave-ayland@ilande.co.uk> References: <20210307120850.10418-1-mark.cave-ayland@ilande.co.uk> MIME-Version: 1.0 X-SA-Exim-Connect-IP: 86.148.34.47 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk Subject: [PULL 37/42] esp: transition to message out phase after SATN and stop command X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on mail.default.ilande.uk0.bigv.io) Received-SPF: pass client-ip=2001:41c9:1:41f::167; envelope-from=mark.cave-ayland@ilande.co.uk; helo=mail.default.ilande.uk0.bigv.io X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" The SCSI bus should remain in the message out phase after the SATN and stop command rather than transitioning to the command phase. A new ESPState variable cmdbuf_cdb_offset is added which stores the offset of the CDB from the start of cmdbuf when accumulating extended message out phase data. Currently any extended message out data is discarded in do_cmd() before the CDB is processed in do_busid_cmd(). Signed-off-by: Mark Cave-Ayland Reviewed-by: Laurent Vivier Message-Id: <20210304221103.6369-38-mark.cave-ayland@ilande.co.uk> --- hw/scsi/esp.c | 72 ++++++++++++++++++++++++++++++++++--------- include/hw/scsi/esp.h | 2 ++ 2 files changed, 60 insertions(+), 14 deletions(-) diff --git a/hw/scsi/esp.c b/hw/scsi/esp.c index 23fcaa90c1..0d5c07e4c1 100644 --- a/hw/scsi/esp.c +++ b/hw/scsi/esp.c @@ -272,13 +272,15 @@ static void do_cmd(ESPState *s) uint8_t *buf = s->cmdbuf; uint8_t busid = buf[0]; - do_busid_cmd(s, &buf[1], busid); + /* Ignore extended messages for now */ + do_busid_cmd(s, &buf[s->cmdbuf_cdb_offset], busid); } static void satn_pdma_cb(ESPState *s) { s->do_cmd = 0; if (s->cmdlen) { + s->cmdbuf_cdb_offset = 1; do_cmd(s); } } @@ -295,6 +297,7 @@ static void handle_satn(ESPState *s) cmdlen = get_cmd(s, ESP_CMDBUF_SZ); if (cmdlen > 0) { s->cmdlen = cmdlen; + s->cmdbuf_cdb_offset = 1; do_cmd(s); } else if (cmdlen == 0) { s->cmdlen = 0; @@ -309,6 +312,7 @@ static void s_without_satn_pdma_cb(ESPState *s) { s->do_cmd = 0; if (s->cmdlen) { + s->cmdbuf_cdb_offset = 0; do_busid_cmd(s, s->cmdbuf, 0); } } @@ -325,6 +329,7 @@ static void handle_s_without_atn(ESPState *s) cmdlen = get_cmd(s, ESP_CMDBUF_SZ); if (cmdlen > 0) { s->cmdlen = cmdlen; + s->cmdbuf_cdb_offset = 0; do_busid_cmd(s, s->cmdbuf, 0); } else if (cmdlen == 0) { s->cmdlen = 0; @@ -341,6 +346,7 @@ static void satn_stop_pdma_cb(ESPState *s) if (s->cmdlen) { trace_esp_handle_satn_stop(s->cmdlen); s->do_cmd = 1; + s->cmdbuf_cdb_offset = 1; s->rregs[ESP_RSTAT] = STAT_TC | STAT_CD; s->rregs[ESP_RINTR] |= INTR_BS | INTR_FC; s->rregs[ESP_RSEQ] = SEQ_CD; @@ -357,21 +363,22 @@ static void handle_satn_stop(ESPState *s) return; } s->pdma_cb = satn_stop_pdma_cb; - cmdlen = get_cmd(s, ESP_CMDBUF_SZ); + cmdlen = get_cmd(s, 1); if (cmdlen > 0) { - trace_esp_handle_satn_stop(s->cmdlen); + trace_esp_handle_satn_stop(cmdlen); s->cmdlen = cmdlen; s->do_cmd = 1; - s->rregs[ESP_RSTAT] = STAT_CD; + s->cmdbuf_cdb_offset = 1; + s->rregs[ESP_RSTAT] = STAT_MO; s->rregs[ESP_RINTR] |= INTR_BS | INTR_FC; - s->rregs[ESP_RSEQ] = SEQ_CD; + s->rregs[ESP_RSEQ] = SEQ_MO; esp_raise_irq(s); } else if (cmdlen == 0) { s->cmdlen = 0; s->do_cmd = 1; - /* Target present, but no cmd yet - switch to command phase */ - s->rregs[ESP_RSEQ] = SEQ_CD; - s->rregs[ESP_RSTAT] = STAT_CD; + /* Target present, switch to message out phase */ + s->rregs[ESP_RSEQ] = SEQ_MO; + s->rregs[ESP_RSTAT] = STAT_MO; } } @@ -505,9 +512,27 @@ static void esp_do_dma(ESPState *s) } trace_esp_handle_ti_cmd(s->cmdlen); s->ti_size = 0; - s->cmdlen = 0; - s->do_cmd = 0; - do_cmd(s); + if ((s->rregs[ESP_RSTAT] & 7) == STAT_CD) { + /* No command received */ + if (s->cmdbuf_cdb_offset == s->cmdlen) { + return; + } + + /* Command has been received */ + s->cmdlen = 0; + s->do_cmd = 0; + do_cmd(s); + } else { + /* + * Extra message out bytes received: update cmdbuf_cdb_offset + * and then switch to commmand phase + */ + s->cmdbuf_cdb_offset = s->cmdlen; + s->rregs[ESP_RSTAT] = STAT_TC | STAT_CD; + s->rregs[ESP_RSEQ] = SEQ_CD; + s->rregs[ESP_RINTR] |= INTR_BS; + esp_raise_irq(s); + } return; } if (s->async_len == 0) { @@ -655,9 +680,27 @@ static void handle_ti(ESPState *s) } else if (s->do_cmd) { trace_esp_handle_ti_cmd(s->cmdlen); s->ti_size = 0; - s->cmdlen = 0; - s->do_cmd = 0; - do_cmd(s); + if ((s->rregs[ESP_RSTAT] & 7) == STAT_CD) { + /* No command received */ + if (s->cmdbuf_cdb_offset == s->cmdlen) { + return; + } + + /* Command has been received */ + s->cmdlen = 0; + s->do_cmd = 0; + do_cmd(s); + } else { + /* + * Extra message out bytes received: update cmdbuf_cdb_offset + * and then switch to commmand phase + */ + s->cmdbuf_cdb_offset = s->cmdlen; + s->rregs[ESP_RSTAT] = STAT_TC | STAT_CD; + s->rregs[ESP_RSEQ] = SEQ_CD; + s->rregs[ESP_RINTR] |= INTR_BS; + esp_raise_irq(s); + } } } @@ -944,6 +987,7 @@ const VMStateDescription vmstate_esp = { VMSTATE_UINT32(do_cmd, ESPState), VMSTATE_UINT32_TEST(mig_dma_left, ESPState, esp_is_before_version_5), VMSTATE_BOOL_TEST(data_in_ready, ESPState, esp_is_version_5), + VMSTATE_UINT8_TEST(cmdbuf_cdb_offset, ESPState, esp_is_version_5), VMSTATE_END_OF_LIST() }, }; diff --git a/include/hw/scsi/esp.h b/include/hw/scsi/esp.h index 7d88fa0f92..f697645c05 100644 --- a/include/hw/scsi/esp.h +++ b/include/hw/scsi/esp.h @@ -37,6 +37,7 @@ struct ESPState { SCSIRequest *current_req; uint8_t cmdbuf[ESP_CMDBUF_SZ]; uint32_t cmdlen; + uint8_t cmdbuf_cdb_offset; uint32_t do_cmd; bool data_in_ready; @@ -136,6 +137,7 @@ struct SysBusESPState { #define INTR_RST 0x80 #define SEQ_0 0x0 +#define SEQ_MO 0x1 #define SEQ_CD 0x4 #define CFG1_RESREPT 0x40 From patchwork Sun Mar 7 12:08:46 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Mark Cave-Ayland X-Patchwork-Id: 1448666 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4Dth8N37qvz9sW5 for ; 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Sun, 07 Mar 2021 12:12:16 +0000 From: Mark Cave-Ayland To: qemu-devel@nongnu.org, peter.maydell@linaro.org Date: Sun, 7 Mar 2021 12:08:46 +0000 Message-Id: <20210307120850.10418-39-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210307120850.10418-1-mark.cave-ayland@ilande.co.uk> References: <20210307120850.10418-1-mark.cave-ayland@ilande.co.uk> MIME-Version: 1.0 X-SA-Exim-Connect-IP: 86.148.34.47 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk Subject: [PULL 38/42] esp: convert ti_buf from array to Fifo8 X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on mail.default.ilande.uk0.bigv.io) Received-SPF: pass client-ip=2001:41c9:1:41f::167; envelope-from=mark.cave-ayland@ilande.co.uk; helo=mail.default.ilande.uk0.bigv.io X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Rename TI_BUFSZ to ESP_FIFO_SZ since this constant is really describing the size of the FIFO and is not directly related to the TI size. Signed-off-by: Mark Cave-Ayland Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Laurent Vivier Message-Id: <20210304221103.6369-39-mark.cave-ayland@ilande.co.uk> --- hw/scsi/esp.c | 118 ++++++++++++++++++++++++++---------------- include/hw/scsi/esp.h | 8 +-- 2 files changed, 79 insertions(+), 47 deletions(-) diff --git a/hw/scsi/esp.c b/hw/scsi/esp.c index 0d5c07e4c1..44e70aa789 100644 --- a/hw/scsi/esp.c +++ b/hw/scsi/esp.c @@ -98,6 +98,25 @@ void esp_request_cancelled(SCSIRequest *req) } } +static void esp_fifo_push(ESPState *s, uint8_t val) +{ + if (fifo8_num_used(&s->fifo) == ESP_FIFO_SZ) { + trace_esp_error_fifo_overrun(); + return; + } + + fifo8_push(&s->fifo, val); +} + +static uint8_t esp_fifo_pop(ESPState *s) +{ + if (fifo8_is_empty(&s->fifo)) { + return 0; + } + + return fifo8_pop(&s->fifo); +} + static uint32_t esp_get_tc(ESPState *s) { uint32_t dmalen; @@ -134,7 +153,7 @@ static uint8_t esp_pdma_read(ESPState *s) if (s->do_cmd) { val = s->cmdbuf[s->cmdlen++]; } else { - val = s->ti_buf[s->ti_rptr++]; + val = esp_fifo_pop(s); } return val; @@ -151,7 +170,7 @@ static void esp_pdma_write(ESPState *s, uint8_t val) if (s->do_cmd) { s->cmdbuf[s->cmdlen++] = val; } else { - s->ti_buf[s->ti_wptr++] = val; + esp_fifo_push(s, val); } dmalen--; @@ -165,8 +184,7 @@ static int esp_select(ESPState *s) target = s->wregs[ESP_WBUSID] & BUSID_DID; s->ti_size = 0; - s->ti_rptr = 0; - s->ti_wptr = 0; + fifo8_reset(&s->fifo); if (s->current_req) { /* Started a new command before the old one finished. Cancel it. */ @@ -197,7 +215,7 @@ static int esp_select(ESPState *s) static uint32_t get_cmd(ESPState *s, uint32_t maxlen) { uint8_t *buf = s->cmdbuf; - uint32_t dmalen; + uint32_t dmalen, n; int target; target = s->wregs[ESP_WBUSID] & BUSID_DID; @@ -220,7 +238,7 @@ static uint32_t get_cmd(ESPState *s, uint32_t maxlen) if (dmalen == 0) { return 0; } - memcpy(buf, s->ti_buf, dmalen); + memcpy(buf, fifo8_pop_buf(&s->fifo, dmalen, &n), dmalen); if (dmalen >= 3) { buf[0] = buf[2] >> 5; } @@ -392,12 +410,18 @@ static void write_response_pdma_cb(ESPState *s) static void write_response(ESPState *s) { + uint32_t n; + trace_esp_write_response(s->status); - s->ti_buf[0] = s->status; - s->ti_buf[1] = 0; + + fifo8_reset(&s->fifo); + esp_fifo_push(s, s->status); + esp_fifo_push(s, 0); + if (s->dma) { if (s->dma_memory_write) { - s->dma_memory_write(s->dma_opaque, s->ti_buf, 2); + s->dma_memory_write(s->dma_opaque, + (uint8_t *)fifo8_pop_buf(&s->fifo, 2, &n), 2); s->rregs[ESP_RSTAT] = STAT_TC | STAT_ST; s->rregs[ESP_RINTR] |= INTR_BS | INTR_FC; s->rregs[ESP_RSEQ] = SEQ_CD; @@ -408,8 +432,6 @@ static void write_response(ESPState *s) } } else { s->ti_size = 2; - s->ti_rptr = 0; - s->ti_wptr = 2; s->rregs[ESP_RFLAGS] = 2; } esp_raise_irq(s); @@ -429,6 +451,7 @@ static void do_dma_pdma_cb(ESPState *s) { int to_device = ((s->rregs[ESP_RSTAT] & 7) == STAT_DO); int len; + uint32_t n; if (s->do_cmd) { s->ti_size = 0; @@ -441,10 +464,8 @@ static void do_dma_pdma_cb(ESPState *s) if (to_device) { /* Copy FIFO data to device */ - len = MIN(s->ti_wptr, TI_BUFSZ); - memcpy(s->async_buf, s->ti_buf, len); - s->ti_wptr = 0; - s->ti_rptr = 0; + len = MIN(fifo8_num_used(&s->fifo), ESP_FIFO_SZ); + memcpy(s->async_buf, fifo8_pop_buf(&s->fifo, len, &n), len); s->async_buf += len; s->async_len -= len; s->ti_size += len; @@ -471,11 +492,8 @@ static void do_dma_pdma_cb(ESPState *s) if (esp_get_tc(s) != 0) { /* Copy device data to FIFO */ - s->ti_wptr = 0; - s->ti_rptr = 0; - len = MIN(s->async_len, TI_BUFSZ); - memcpy(s->ti_buf, s->async_buf, len); - s->ti_wptr += len; + len = MIN(s->async_len, fifo8_num_free(&s->fifo)); + fifo8_push_all(&s->fifo, s->async_buf, len); s->async_buf += len; s->async_len -= len; s->ti_size -= len; @@ -555,9 +573,8 @@ static void esp_do_dma(ESPState *s) s->dma_memory_write(s->dma_opaque, s->async_buf, len); } else { /* Copy device data to FIFO */ - len = MIN(len, TI_BUFSZ - s->ti_wptr); - memcpy(&s->ti_buf[s->ti_wptr], s->async_buf, len); - s->ti_wptr += len; + len = MIN(len, fifo8_num_free(&s->fifo)); + fifo8_push_all(&s->fifo, s->async_buf, len); s->async_buf += len; s->async_len -= len; s->ti_size -= len; @@ -710,8 +727,7 @@ void esp_hard_reset(ESPState *s) memset(s->wregs, 0, ESP_REGS); s->tchi_written = 0; s->ti_size = 0; - s->ti_rptr = 0; - s->ti_wptr = 0; + fifo8_reset(&s->fifo); s->dma = 0; s->do_cmd = 0; s->dma_cb = NULL; @@ -743,13 +759,9 @@ uint64_t esp_reg_read(ESPState *s, uint32_t saddr) /* Data out. */ qemu_log_mask(LOG_UNIMP, "esp: PIO data read not implemented\n"); s->rregs[ESP_FIFO] = 0; - } else if (s->ti_rptr < s->ti_wptr) { + } else { s->ti_size--; - s->rregs[ESP_FIFO] = s->ti_buf[s->ti_rptr++]; - } - if (s->ti_rptr == s->ti_wptr) { - s->ti_rptr = 0; - s->ti_wptr = 0; + s->rregs[ESP_FIFO] = esp_fifo_pop(s); } val = s->rregs[ESP_FIFO]; break; @@ -799,11 +811,9 @@ void esp_reg_write(ESPState *s, uint32_t saddr, uint64_t val) } else { trace_esp_error_fifo_overrun(); } - } else if (s->ti_wptr == TI_BUFSZ - 1) { - trace_esp_error_fifo_overrun(); } else { s->ti_size++; - s->ti_buf[s->ti_wptr++] = val & 0xff; + esp_fifo_push(s, val); } /* Non-DMA transfers raise an interrupt after every byte */ @@ -831,9 +841,7 @@ void esp_reg_write(ESPState *s, uint32_t saddr, uint64_t val) break; case CMD_FLUSH: trace_esp_mem_writeb_cmd_flush(val); - /*s->ti_size = 0;*/ - s->ti_wptr = 0; - s->ti_rptr = 0; + fifo8_reset(&s->fifo); break; case CMD_RESET: trace_esp_mem_writeb_cmd_reset(val); @@ -951,11 +959,18 @@ static int esp_pre_save(void *opaque) static int esp_post_load(void *opaque, int version_id) { ESPState *s = ESP(opaque); + int len, i; version_id = MIN(version_id, s->mig_version_id); if (version_id < 5) { esp_set_tc(s, s->mig_dma_left); + + /* Migrate ti_buf to fifo */ + len = s->mig_ti_wptr - s->mig_ti_rptr; + for (i = 0; i < len; i++) { + fifo8_push(&s->fifo, s->mig_ti_buf[i]); + } } s->mig_version_id = vmstate_esp.version_id; @@ -972,9 +987,9 @@ const VMStateDescription vmstate_esp = { VMSTATE_BUFFER(rregs, ESPState), VMSTATE_BUFFER(wregs, ESPState), VMSTATE_INT32(ti_size, ESPState), - VMSTATE_UINT32(ti_rptr, ESPState), - VMSTATE_UINT32(ti_wptr, ESPState), - VMSTATE_BUFFER(ti_buf, ESPState), + VMSTATE_UINT32_TEST(mig_ti_rptr, ESPState, esp_is_before_version_5), + VMSTATE_UINT32_TEST(mig_ti_wptr, ESPState, esp_is_before_version_5), + VMSTATE_BUFFER_TEST(mig_ti_buf, ESPState, esp_is_before_version_5), VMSTATE_UINT32(status, ESPState), VMSTATE_UINT32_TEST(mig_deferred_status, ESPState, esp_is_before_version_5), @@ -988,6 +1003,7 @@ const VMStateDescription vmstate_esp = { VMSTATE_UINT32_TEST(mig_dma_left, ESPState, esp_is_before_version_5), VMSTATE_BOOL_TEST(data_in_ready, ESPState, esp_is_version_5), VMSTATE_UINT8_TEST(cmdbuf_cdb_offset, ESPState, esp_is_version_5), + VMSTATE_FIFO8_TEST(fifo, ESPState, esp_is_version_5), VMSTATE_END_OF_LIST() }, }; @@ -1040,7 +1056,7 @@ static void sysbus_esp_pdma_write(void *opaque, hwaddr addr, break; } dmalen = esp_get_tc(s); - if (dmalen == 0 || (s->ti_wptr == TI_BUFSZ)) { + if (dmalen == 0 || fifo8_is_full(&s->fifo)) { s->pdma_cb(s); } } @@ -1063,9 +1079,7 @@ static uint64_t sysbus_esp_pdma_read(void *opaque, hwaddr addr, val = (val << 8) | esp_pdma_read(s); break; } - if (s->ti_rptr == s->ti_wptr) { - s->ti_wptr = 0; - s->ti_rptr = 0; + if (fifo8_is_empty(&s->fifo)) { s->pdma_cb(s); } return val; @@ -1177,6 +1191,20 @@ static const TypeInfo sysbus_esp_info = { .class_init = sysbus_esp_class_init, }; +static void esp_finalize(Object *obj) +{ + ESPState *s = ESP(obj); + + fifo8_destroy(&s->fifo); +} + +static void esp_init(Object *obj) +{ + ESPState *s = ESP(obj); + + fifo8_create(&s->fifo, ESP_FIFO_SZ); +} + static void esp_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); @@ -1189,6 +1217,8 @@ static void esp_class_init(ObjectClass *klass, void *data) static const TypeInfo esp_info = { .name = TYPE_ESP, .parent = TYPE_DEVICE, + .instance_init = esp_init, + .instance_finalize = esp_finalize, .instance_size = sizeof(ESPState), .class_init = esp_class_init, }; diff --git a/include/hw/scsi/esp.h b/include/hw/scsi/esp.h index f697645c05..eb4e8ba171 100644 --- a/include/hw/scsi/esp.h +++ b/include/hw/scsi/esp.h @@ -3,6 +3,7 @@ #include "hw/scsi/scsi.h" #include "hw/sysbus.h" +#include "qemu/fifo8.h" #include "qom/object.h" /* esp.c */ @@ -10,7 +11,7 @@ typedef void (*ESPDMAMemoryReadWriteFunc)(void *opaque, uint8_t *buf, int len); #define ESP_REGS 16 -#define TI_BUFSZ 16 +#define ESP_FIFO_SZ 16 #define ESP_CMDBUF_SZ 32 typedef struct ESPState ESPState; @@ -28,10 +29,9 @@ struct ESPState { uint8_t chip_id; bool tchi_written; int32_t ti_size; - uint32_t ti_rptr, ti_wptr; uint32_t status; uint32_t dma; - uint8_t ti_buf[TI_BUFSZ]; + Fifo8 fifo; SCSIBus bus; SCSIDevice *current_dev; SCSIRequest *current_req; @@ -58,6 +58,8 @@ struct ESPState { uint32_t mig_dma_left; uint32_t mig_deferred_status; bool mig_deferred_complete; + uint32_t mig_ti_rptr, mig_ti_wptr; + uint8_t mig_ti_buf[ESP_FIFO_SZ]; }; #define TYPE_SYSBUS_ESP "sysbus-esp" From patchwork Sun Mar 7 12:08:47 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Cave-Ayland X-Patchwork-Id: 1448670 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4DthGJ27bPz9sW5 for ; Sun, 7 Mar 2021 23:52:56 +1100 (AEDT) Received: from localhost ([::1]:41398 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lIsty-000573-8y for incoming@patchwork.ozlabs.org; Sun, 07 Mar 2021 07:52:54 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:42080) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lIsGx-00041Y-8K for qemu-devel@nongnu.org; Sun, 07 Mar 2021 07:12:35 -0500 Received: from mail.ilande.co.uk ([2001:41c9:1:41f::167]:43784 helo=mail.default.ilande.uk0.bigv.io) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lIsGu-0008M8-Qg for qemu-devel@nongnu.org; Sun, 07 Mar 2021 07:12:35 -0500 Received: from host86-148-34-47.range86-148.btcentralplus.com ([86.148.34.47] helo=kentang.home) by mail.default.ilande.uk0.bigv.io with esmtpsa (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1lIsGe-0002V5-6L; Sun, 07 Mar 2021 12:12:22 +0000 From: Mark Cave-Ayland To: qemu-devel@nongnu.org, peter.maydell@linaro.org Date: Sun, 7 Mar 2021 12:08:47 +0000 Message-Id: <20210307120850.10418-40-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210307120850.10418-1-mark.cave-ayland@ilande.co.uk> References: <20210307120850.10418-1-mark.cave-ayland@ilande.co.uk> MIME-Version: 1.0 X-SA-Exim-Connect-IP: 86.148.34.47 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk Subject: [PULL 39/42] esp: convert cmdbuf from array to Fifo8 X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on mail.default.ilande.uk0.bigv.io) Received-SPF: pass client-ip=2001:41c9:1:41f::167; envelope-from=mark.cave-ayland@ilande.co.uk; helo=mail.default.ilande.uk0.bigv.io X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Rename ESP_CMDBUF_SZ to ESP_CMDFIFO_SZ and cmdbuf_cdb_offset to cmdfifo_cdb_offset to indicate that the command buffer type has changed from an array to a Fifo8. This also enables us to remove the ESPState field cmdlen since the command length is now simply the number of elements used in cmdfifo. Signed-off-by: Mark Cave-Ayland Reviewed-by: Laurent Vivier Message-Id: <20210304221103.6369-40-mark.cave-ayland@ilande.co.uk> --- hw/scsi/esp.c | 151 +++++++++++++++++++++++++++--------------- include/hw/scsi/esp.h | 9 +-- 2 files changed, 101 insertions(+), 59 deletions(-) diff --git a/hw/scsi/esp.c b/hw/scsi/esp.c index 44e70aa789..34dc58da58 100644 --- a/hw/scsi/esp.c +++ b/hw/scsi/esp.c @@ -117,6 +117,25 @@ static uint8_t esp_fifo_pop(ESPState *s) return fifo8_pop(&s->fifo); } +static void esp_cmdfifo_push(ESPState *s, uint8_t val) +{ + if (fifo8_num_used(&s->cmdfifo) == ESP_CMDFIFO_SZ) { + trace_esp_error_fifo_overrun(); + return; + } + + fifo8_push(&s->cmdfifo, val); +} + +static uint8_t esp_cmdfifo_pop(ESPState *s) +{ + if (fifo8_is_empty(&s->cmdfifo)) { + return 0; + } + + return fifo8_pop(&s->cmdfifo); +} + static uint32_t esp_get_tc(ESPState *s) { uint32_t dmalen; @@ -151,7 +170,7 @@ static uint8_t esp_pdma_read(ESPState *s) uint8_t val; if (s->do_cmd) { - val = s->cmdbuf[s->cmdlen++]; + val = esp_cmdfifo_pop(s); } else { val = esp_fifo_pop(s); } @@ -168,7 +187,7 @@ static void esp_pdma_write(ESPState *s, uint8_t val) } if (s->do_cmd) { - s->cmdbuf[s->cmdlen++] = val; + esp_cmdfifo_push(s, val); } else { esp_fifo_push(s, val); } @@ -214,7 +233,7 @@ static int esp_select(ESPState *s) static uint32_t get_cmd(ESPState *s, uint32_t maxlen) { - uint8_t *buf = s->cmdbuf; + uint8_t buf[ESP_CMDFIFO_SZ]; uint32_t dmalen, n; int target; @@ -226,15 +245,18 @@ static uint32_t get_cmd(ESPState *s, uint32_t maxlen) } if (s->dma_memory_read) { s->dma_memory_read(s->dma_opaque, buf, dmalen); + fifo8_push_all(&s->cmdfifo, buf, dmalen); } else { if (esp_select(s) < 0) { + fifo8_reset(&s->cmdfifo); return -1; } esp_raise_drq(s); + fifo8_reset(&s->cmdfifo); return 0; } } else { - dmalen = MIN(s->ti_size, maxlen); + dmalen = MIN(fifo8_num_used(&s->fifo), maxlen); if (dmalen == 0) { return 0; } @@ -242,27 +264,35 @@ static uint32_t get_cmd(ESPState *s, uint32_t maxlen) if (dmalen >= 3) { buf[0] = buf[2] >> 5; } + fifo8_push_all(&s->cmdfifo, buf, dmalen); } trace_esp_get_cmd(dmalen, target); if (esp_select(s) < 0) { + fifo8_reset(&s->cmdfifo); return -1; } return dmalen; } -static void do_busid_cmd(ESPState *s, uint8_t *buf, uint8_t busid) +static void do_busid_cmd(ESPState *s, uint8_t busid) { + uint32_t n, cmdlen; int32_t datalen; int lun; SCSIDevice *current_lun; + uint8_t *buf; trace_esp_do_busid_cmd(busid); lun = busid & 7; + cmdlen = fifo8_num_used(&s->cmdfifo); + buf = (uint8_t *)fifo8_pop_buf(&s->cmdfifo, cmdlen, &n); + current_lun = scsi_device_find(&s->bus, 0, s->current_dev->id, lun); s->current_req = scsi_req_new(current_lun, 0, lun, buf, s); datalen = scsi_req_enqueue(s->current_req); s->ti_size = datalen; + fifo8_reset(&s->cmdfifo); if (datalen != 0) { s->rregs[ESP_RSTAT] = STAT_TC; s->rregs[ESP_RSEQ] = SEQ_CD; @@ -287,18 +317,25 @@ static void do_busid_cmd(ESPState *s, uint8_t *buf, uint8_t busid) static void do_cmd(ESPState *s) { - uint8_t *buf = s->cmdbuf; - uint8_t busid = buf[0]; + uint8_t busid = fifo8_pop(&s->cmdfifo); + uint32_t n; + + s->cmdfifo_cdb_offset--; /* Ignore extended messages for now */ - do_busid_cmd(s, &buf[s->cmdbuf_cdb_offset], busid); + if (s->cmdfifo_cdb_offset) { + fifo8_pop_buf(&s->cmdfifo, s->cmdfifo_cdb_offset, &n); + s->cmdfifo_cdb_offset = 0; + } + + do_busid_cmd(s, busid); } static void satn_pdma_cb(ESPState *s) { s->do_cmd = 0; - if (s->cmdlen) { - s->cmdbuf_cdb_offset = 1; + if (!fifo8_is_empty(&s->cmdfifo)) { + s->cmdfifo_cdb_offset = 1; do_cmd(s); } } @@ -312,13 +349,11 @@ static void handle_satn(ESPState *s) return; } s->pdma_cb = satn_pdma_cb; - cmdlen = get_cmd(s, ESP_CMDBUF_SZ); + cmdlen = get_cmd(s, ESP_CMDFIFO_SZ); if (cmdlen > 0) { - s->cmdlen = cmdlen; - s->cmdbuf_cdb_offset = 1; + s->cmdfifo_cdb_offset = 1; do_cmd(s); } else if (cmdlen == 0) { - s->cmdlen = 0; s->do_cmd = 1; /* Target present, but no cmd yet - switch to command phase */ s->rregs[ESP_RSEQ] = SEQ_CD; @@ -328,10 +363,13 @@ static void handle_satn(ESPState *s) static void s_without_satn_pdma_cb(ESPState *s) { + uint32_t len; + s->do_cmd = 0; - if (s->cmdlen) { - s->cmdbuf_cdb_offset = 0; - do_busid_cmd(s, s->cmdbuf, 0); + len = fifo8_num_used(&s->cmdfifo); + if (len) { + s->cmdfifo_cdb_offset = 0; + do_busid_cmd(s, 0); } } @@ -344,13 +382,11 @@ static void handle_s_without_atn(ESPState *s) return; } s->pdma_cb = s_without_satn_pdma_cb; - cmdlen = get_cmd(s, ESP_CMDBUF_SZ); + cmdlen = get_cmd(s, ESP_CMDFIFO_SZ); if (cmdlen > 0) { - s->cmdlen = cmdlen; - s->cmdbuf_cdb_offset = 0; - do_busid_cmd(s, s->cmdbuf, 0); + s->cmdfifo_cdb_offset = 0; + do_busid_cmd(s, 0); } else if (cmdlen == 0) { - s->cmdlen = 0; s->do_cmd = 1; /* Target present, but no cmd yet - switch to command phase */ s->rregs[ESP_RSEQ] = SEQ_CD; @@ -361,10 +397,10 @@ static void handle_s_without_atn(ESPState *s) static void satn_stop_pdma_cb(ESPState *s) { s->do_cmd = 0; - if (s->cmdlen) { - trace_esp_handle_satn_stop(s->cmdlen); + if (!fifo8_is_empty(&s->cmdfifo)) { + trace_esp_handle_satn_stop(fifo8_num_used(&s->cmdfifo)); s->do_cmd = 1; - s->cmdbuf_cdb_offset = 1; + s->cmdfifo_cdb_offset = 1; s->rregs[ESP_RSTAT] = STAT_TC | STAT_CD; s->rregs[ESP_RINTR] |= INTR_BS | INTR_FC; s->rregs[ESP_RSEQ] = SEQ_CD; @@ -383,16 +419,14 @@ static void handle_satn_stop(ESPState *s) s->pdma_cb = satn_stop_pdma_cb; cmdlen = get_cmd(s, 1); if (cmdlen > 0) { - trace_esp_handle_satn_stop(cmdlen); - s->cmdlen = cmdlen; + trace_esp_handle_satn_stop(fifo8_num_used(&s->cmdfifo)); s->do_cmd = 1; - s->cmdbuf_cdb_offset = 1; + s->cmdfifo_cdb_offset = 1; s->rregs[ESP_RSTAT] = STAT_MO; s->rregs[ESP_RINTR] |= INTR_BS | INTR_FC; s->rregs[ESP_RSEQ] = SEQ_MO; esp_raise_irq(s); } else if (cmdlen == 0) { - s->cmdlen = 0; s->do_cmd = 1; /* Target present, switch to message out phase */ s->rregs[ESP_RSEQ] = SEQ_MO; @@ -455,7 +489,6 @@ static void do_dma_pdma_cb(ESPState *s) if (s->do_cmd) { s->ti_size = 0; - s->cmdlen = 0; s->do_cmd = 0; do_cmd(s); esp_lower_drq(s); @@ -509,8 +542,9 @@ static void do_dma_pdma_cb(ESPState *s) static void esp_do_dma(ESPState *s) { - uint32_t len; + uint32_t len, cmdlen; int to_device = ((s->rregs[ESP_RSTAT] & 7) == STAT_DO); + uint8_t buf[ESP_CMDFIFO_SZ]; len = esp_get_tc(s); if (s->do_cmd) { @@ -518,34 +552,33 @@ static void esp_do_dma(ESPState *s) * handle_ti_cmd() case: esp_do_dma() is called only from * handle_ti_cmd() with do_cmd != NULL (see the assert()) */ - trace_esp_do_dma(s->cmdlen, len); - assert(s->cmdlen <= sizeof(s->cmdbuf) && - len <= sizeof(s->cmdbuf) - s->cmdlen); + cmdlen = fifo8_num_used(&s->cmdfifo); + trace_esp_do_dma(cmdlen, len); if (s->dma_memory_read) { - s->dma_memory_read(s->dma_opaque, &s->cmdbuf[s->cmdlen], len); + s->dma_memory_read(s->dma_opaque, buf, len); + fifo8_push_all(&s->cmdfifo, buf, len); } else { s->pdma_cb = do_dma_pdma_cb; esp_raise_drq(s); return; } - trace_esp_handle_ti_cmd(s->cmdlen); + trace_esp_handle_ti_cmd(cmdlen); s->ti_size = 0; if ((s->rregs[ESP_RSTAT] & 7) == STAT_CD) { /* No command received */ - if (s->cmdbuf_cdb_offset == s->cmdlen) { + if (s->cmdfifo_cdb_offset == fifo8_num_used(&s->cmdfifo)) { return; } /* Command has been received */ - s->cmdlen = 0; s->do_cmd = 0; do_cmd(s); } else { /* - * Extra message out bytes received: update cmdbuf_cdb_offset + * Extra message out bytes received: update cmdfifo_cdb_offset * and then switch to commmand phase */ - s->cmdbuf_cdb_offset = s->cmdlen; + s->cmdfifo_cdb_offset = fifo8_num_used(&s->cmdfifo); s->rregs[ESP_RSTAT] = STAT_TC | STAT_CD; s->rregs[ESP_RSEQ] = SEQ_CD; s->rregs[ESP_RINTR] |= INTR_BS; @@ -682,7 +715,7 @@ void esp_transfer_data(SCSIRequest *req, uint32_t len) static void handle_ti(ESPState *s) { - uint32_t dmalen; + uint32_t dmalen, cmdlen; if (s->dma && !s->dma_enabled) { s->dma_cb = handle_ti; @@ -695,24 +728,24 @@ static void handle_ti(ESPState *s) s->rregs[ESP_RSTAT] &= ~STAT_TC; esp_do_dma(s); } else if (s->do_cmd) { - trace_esp_handle_ti_cmd(s->cmdlen); + cmdlen = fifo8_num_used(&s->cmdfifo); + trace_esp_handle_ti_cmd(cmdlen); s->ti_size = 0; if ((s->rregs[ESP_RSTAT] & 7) == STAT_CD) { /* No command received */ - if (s->cmdbuf_cdb_offset == s->cmdlen) { + if (s->cmdfifo_cdb_offset == fifo8_num_used(&s->cmdfifo)) { return; } /* Command has been received */ - s->cmdlen = 0; s->do_cmd = 0; do_cmd(s); } else { /* - * Extra message out bytes received: update cmdbuf_cdb_offset + * Extra message out bytes received: update cmdfifo_cdb_offset * and then switch to commmand phase */ - s->cmdbuf_cdb_offset = s->cmdlen; + s->cmdfifo_cdb_offset = fifo8_num_used(&s->cmdfifo); s->rregs[ESP_RSTAT] = STAT_TC | STAT_CD; s->rregs[ESP_RSEQ] = SEQ_CD; s->rregs[ESP_RINTR] |= INTR_BS; @@ -728,6 +761,7 @@ void esp_hard_reset(ESPState *s) s->tchi_written = 0; s->ti_size = 0; fifo8_reset(&s->fifo); + fifo8_reset(&s->cmdfifo); s->dma = 0; s->do_cmd = 0; s->dma_cb = NULL; @@ -806,11 +840,7 @@ void esp_reg_write(ESPState *s, uint32_t saddr, uint64_t val) break; case ESP_FIFO: if (s->do_cmd) { - if (s->cmdlen < ESP_CMDBUF_SZ) { - s->cmdbuf[s->cmdlen++] = val & 0xff; - } else { - trace_esp_error_fifo_overrun(); - } + esp_cmdfifo_push(s, val); } else { s->ti_size++; esp_fifo_push(s, val); @@ -971,6 +1001,11 @@ static int esp_post_load(void *opaque, int version_id) for (i = 0; i < len; i++) { fifo8_push(&s->fifo, s->mig_ti_buf[i]); } + + /* Migrate cmdbuf to cmdfifo */ + for (i = 0; i < s->mig_cmdlen; i++) { + fifo8_push(&s->cmdfifo, s->mig_cmdbuf[i]); + } } s->mig_version_id = vmstate_esp.version_id; @@ -996,14 +1031,18 @@ const VMStateDescription vmstate_esp = { VMSTATE_BOOL_TEST(mig_deferred_complete, ESPState, esp_is_before_version_5), VMSTATE_UINT32(dma, ESPState), - VMSTATE_PARTIAL_BUFFER(cmdbuf, ESPState, 16), - VMSTATE_BUFFER_START_MIDDLE_V(cmdbuf, ESPState, 16, 4), - VMSTATE_UINT32(cmdlen, ESPState), + VMSTATE_STATIC_BUFFER(mig_cmdbuf, ESPState, 0, + esp_is_before_version_5, 0, 16), + VMSTATE_STATIC_BUFFER(mig_cmdbuf, ESPState, 4, + esp_is_before_version_5, 16, + sizeof(typeof_field(ESPState, mig_cmdbuf))), + VMSTATE_UINT32_TEST(mig_cmdlen, ESPState, esp_is_before_version_5), VMSTATE_UINT32(do_cmd, ESPState), VMSTATE_UINT32_TEST(mig_dma_left, ESPState, esp_is_before_version_5), VMSTATE_BOOL_TEST(data_in_ready, ESPState, esp_is_version_5), - VMSTATE_UINT8_TEST(cmdbuf_cdb_offset, ESPState, esp_is_version_5), + VMSTATE_UINT8_TEST(cmdfifo_cdb_offset, ESPState, esp_is_version_5), VMSTATE_FIFO8_TEST(fifo, ESPState, esp_is_version_5), + VMSTATE_FIFO8_TEST(cmdfifo, ESPState, esp_is_version_5), VMSTATE_END_OF_LIST() }, }; @@ -1196,6 +1235,7 @@ static void esp_finalize(Object *obj) ESPState *s = ESP(obj); fifo8_destroy(&s->fifo); + fifo8_destroy(&s->cmdfifo); } static void esp_init(Object *obj) @@ -1203,6 +1243,7 @@ static void esp_init(Object *obj) ESPState *s = ESP(obj); fifo8_create(&s->fifo, ESP_FIFO_SZ); + fifo8_create(&s->cmdfifo, ESP_CMDFIFO_SZ); } static void esp_class_init(ObjectClass *klass, void *data) diff --git a/include/hw/scsi/esp.h b/include/hw/scsi/esp.h index eb4e8ba171..2fe8d20ab5 100644 --- a/include/hw/scsi/esp.h +++ b/include/hw/scsi/esp.h @@ -12,7 +12,7 @@ typedef void (*ESPDMAMemoryReadWriteFunc)(void *opaque, uint8_t *buf, int len); #define ESP_REGS 16 #define ESP_FIFO_SZ 16 -#define ESP_CMDBUF_SZ 32 +#define ESP_CMDFIFO_SZ 32 typedef struct ESPState ESPState; @@ -35,9 +35,8 @@ struct ESPState { SCSIBus bus; SCSIDevice *current_dev; SCSIRequest *current_req; - uint8_t cmdbuf[ESP_CMDBUF_SZ]; - uint32_t cmdlen; - uint8_t cmdbuf_cdb_offset; + Fifo8 cmdfifo; + uint8_t cmdfifo_cdb_offset; uint32_t do_cmd; bool data_in_ready; @@ -60,6 +59,8 @@ struct ESPState { bool mig_deferred_complete; uint32_t mig_ti_rptr, mig_ti_wptr; uint8_t mig_ti_buf[ESP_FIFO_SZ]; + uint8_t mig_cmdbuf[ESP_CMDFIFO_SZ]; + uint32_t mig_cmdlen; }; #define TYPE_SYSBUS_ESP "sysbus-esp" From patchwork Sun Mar 7 12:08:48 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Mark Cave-Ayland X-Patchwork-Id: 1448673 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4DthLP3nKmz9sW5 for ; Sun, 7 Mar 2021 23:56:29 +1100 (AEDT) Received: from localhost ([::1]:49874 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lIsxP-0000FP-2S for incoming@patchwork.ozlabs.org; Sun, 07 Mar 2021 07:56:27 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:42100) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lIsH0-00043d-NC for qemu-devel@nongnu.org; Sun, 07 Mar 2021 07:12:38 -0500 Received: from mail.ilande.co.uk ([2001:41c9:1:41f::167]:43792 helo=mail.default.ilande.uk0.bigv.io) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lIsGz-0008N4-AX for qemu-devel@nongnu.org; Sun, 07 Mar 2021 07:12:38 -0500 Received: from host86-148-34-47.range86-148.btcentralplus.com ([86.148.34.47] helo=kentang.home) by mail.default.ilande.uk0.bigv.io with esmtpsa (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1lIsGk-0002V5-Je; Sun, 07 Mar 2021 12:12:27 +0000 From: Mark Cave-Ayland To: qemu-devel@nongnu.org, peter.maydell@linaro.org Date: Sun, 7 Mar 2021 12:08:48 +0000 Message-Id: <20210307120850.10418-41-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210307120850.10418-1-mark.cave-ayland@ilande.co.uk> References: <20210307120850.10418-1-mark.cave-ayland@ilande.co.uk> MIME-Version: 1.0 X-SA-Exim-Connect-IP: 86.148.34.47 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk Subject: [PULL 40/42] esp: add trivial implementation of the ESP_RFLAGS register X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on mail.default.ilande.uk0.bigv.io) Received-SPF: pass client-ip=2001:41c9:1:41f::167; envelope-from=mark.cave-ayland@ilande.co.uk; helo=mail.default.ilande.uk0.bigv.io X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" The bottom 5 bits contain the number of bytes remaining in the FIFO which is trivial to implement with Fifo8 (the remaining bits are unimplemented and left as 0 for now). Signed-off-by: Mark Cave-Ayland Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Laurent Vivier Message-Id: <20210304221103.6369-41-mark.cave-ayland@ilande.co.uk> --- hw/scsi/esp.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/hw/scsi/esp.c b/hw/scsi/esp.c index 34dc58da58..8a9b1500de 100644 --- a/hw/scsi/esp.c +++ b/hw/scsi/esp.c @@ -818,6 +818,10 @@ uint64_t esp_reg_read(ESPState *s, uint32_t saddr) val = s->rregs[saddr]; } break; + case ESP_RFLAGS: + /* Bottom 5 bits indicate number of bytes in FIFO */ + val = fifo8_num_used(&s->fifo); + break; default: val = s->rregs[saddr]; break; From patchwork Sun Mar 7 12:08:49 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Cave-Ayland X-Patchwork-Id: 1448663 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4Dth3h1qZLz9sWP for ; Sun, 7 Mar 2021 23:43:44 +1100 (AEDT) Received: from localhost ([::1]:53136 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lIsl4-0006SE-8o for incoming@patchwork.ozlabs.org; Sun, 07 Mar 2021 07:43:42 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:42114) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lIsH5-00049j-HB for qemu-devel@nongnu.org; Sun, 07 Mar 2021 07:12:43 -0500 Received: from mail.ilande.co.uk ([2001:41c9:1:41f::167]:43798 helo=mail.default.ilande.uk0.bigv.io) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lIsH3-0008Ox-5X for qemu-devel@nongnu.org; Sun, 07 Mar 2021 07:12:43 -0500 Received: from host86-148-34-47.range86-148.btcentralplus.com ([86.148.34.47] helo=kentang.home) by mail.default.ilande.uk0.bigv.io with esmtpsa (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1lIsGp-0002V5-2Q; Sun, 07 Mar 2021 12:12:30 +0000 From: Mark Cave-Ayland To: qemu-devel@nongnu.org, peter.maydell@linaro.org Date: Sun, 7 Mar 2021 12:08:49 +0000 Message-Id: <20210307120850.10418-42-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210307120850.10418-1-mark.cave-ayland@ilande.co.uk> References: <20210307120850.10418-1-mark.cave-ayland@ilande.co.uk> MIME-Version: 1.0 X-SA-Exim-Connect-IP: 86.148.34.47 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk Subject: [PULL 41/42] esp: implement non-DMA transfers in PDMA mode X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on mail.default.ilande.uk0.bigv.io) Received-SPF: pass client-ip=2001:41c9:1:41f::167; envelope-from=mark.cave-ayland@ilande.co.uk; helo=mail.default.ilande.uk0.bigv.io X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" The MacOS toolbox ROM uses non-DMA TI commands to handle the first/last byte of an unaligned 16-bit transfer to memory. Signed-off-by: Mark Cave-Ayland Reviewed-by: Laurent Vivier Message-Id: <20210304221103.6369-42-mark.cave-ayland@ilande.co.uk> --- hw/scsi/esp.c | 133 ++++++++++++++++++++++++++++++------------ include/hw/scsi/esp.h | 1 + 2 files changed, 98 insertions(+), 36 deletions(-) diff --git a/hw/scsi/esp.c b/hw/scsi/esp.c index 8a9b1500de..f828e70865 100644 --- a/hw/scsi/esp.c +++ b/hw/scsi/esp.c @@ -296,6 +296,7 @@ static void do_busid_cmd(ESPState *s, uint8_t busid) if (datalen != 0) { s->rregs[ESP_RSTAT] = STAT_TC; s->rregs[ESP_RSEQ] = SEQ_CD; + s->ti_cmd = 0; esp_set_tc(s, 0); if (datalen > 0) { /* @@ -645,6 +646,71 @@ static void esp_do_dma(ESPState *s) esp_lower_drq(s); } +static void esp_do_nodma(ESPState *s) +{ + int to_device = ((s->rregs[ESP_RSTAT] & 7) == STAT_DO); + uint32_t cmdlen, n; + int len; + + if (s->do_cmd) { + cmdlen = fifo8_num_used(&s->cmdfifo); + trace_esp_handle_ti_cmd(cmdlen); + s->ti_size = 0; + if ((s->rregs[ESP_RSTAT] & 7) == STAT_CD) { + /* No command received */ + if (s->cmdfifo_cdb_offset == fifo8_num_used(&s->cmdfifo)) { + return; + } + + /* Command has been received */ + s->do_cmd = 0; + do_cmd(s); + } else { + /* + * Extra message out bytes received: update cmdfifo_cdb_offset + * and then switch to commmand phase + */ + s->cmdfifo_cdb_offset = fifo8_num_used(&s->cmdfifo); + s->rregs[ESP_RSTAT] = STAT_TC | STAT_CD; + s->rregs[ESP_RSEQ] = SEQ_CD; + s->rregs[ESP_RINTR] |= INTR_BS; + esp_raise_irq(s); + } + return; + } + + if (s->async_len == 0) { + /* Defer until data is available. */ + return; + } + + if (to_device) { + len = MIN(fifo8_num_used(&s->fifo), ESP_FIFO_SZ); + memcpy(s->async_buf, fifo8_pop_buf(&s->fifo, len, &n), len); + s->async_buf += len; + s->async_len -= len; + s->ti_size += len; + } else { + len = MIN(s->ti_size, s->async_len); + len = MIN(len, fifo8_num_free(&s->fifo)); + fifo8_push_all(&s->fifo, s->async_buf, len); + s->async_buf += len; + s->async_len -= len; + s->ti_size -= len; + } + + if (s->async_len == 0) { + scsi_req_continue(s->current_req); + + if (to_device || s->ti_size == 0) { + return; + } + } + + s->rregs[ESP_RINTR] |= INTR_BS; + esp_raise_irq(s); +} + void esp_command_complete(SCSIRequest *req, size_t resid) { ESPState *s = req->hba_private; @@ -701,56 +767,51 @@ void esp_transfer_data(SCSIRequest *req, uint32_t len) return; } - if (dmalen) { - esp_do_dma(s); - } else if (s->ti_size <= 0) { + if (s->ti_cmd == 0) { /* - * If this was the last part of a DMA transfer then the - * completion interrupt is deferred to here. + * Always perform the initial transfer upon reception of the next TI + * command to ensure the DMA/non-DMA status of the command is correct. + * It is not possible to use s->dma directly in the section below as + * some OSs send non-DMA NOP commands after a DMA transfer. Hence if the + * async data transfer is delayed then s->dma is set incorrectly. */ - esp_dma_done(s); - esp_lower_drq(s); + return; + } + + if (s->ti_cmd & CMD_DMA) { + if (dmalen) { + esp_do_dma(s); + } else if (s->ti_size <= 0) { + /* + * If this was the last part of a DMA transfer then the + * completion interrupt is deferred to here. + */ + esp_dma_done(s); + esp_lower_drq(s); + } + } else { + esp_do_nodma(s); } } static void handle_ti(ESPState *s) { - uint32_t dmalen, cmdlen; + uint32_t dmalen; if (s->dma && !s->dma_enabled) { s->dma_cb = handle_ti; return; } - dmalen = esp_get_tc(s); + s->ti_cmd = s->rregs[ESP_CMD]; if (s->dma) { + dmalen = esp_get_tc(s); trace_esp_handle_ti(dmalen); s->rregs[ESP_RSTAT] &= ~STAT_TC; esp_do_dma(s); - } else if (s->do_cmd) { - cmdlen = fifo8_num_used(&s->cmdfifo); - trace_esp_handle_ti_cmd(cmdlen); - s->ti_size = 0; - if ((s->rregs[ESP_RSTAT] & 7) == STAT_CD) { - /* No command received */ - if (s->cmdfifo_cdb_offset == fifo8_num_used(&s->cmdfifo)) { - return; - } - - /* Command has been received */ - s->do_cmd = 0; - do_cmd(s); - } else { - /* - * Extra message out bytes received: update cmdfifo_cdb_offset - * and then switch to commmand phase - */ - s->cmdfifo_cdb_offset = fifo8_num_used(&s->cmdfifo); - s->rregs[ESP_RSTAT] = STAT_TC | STAT_CD; - s->rregs[ESP_RSEQ] = SEQ_CD; - s->rregs[ESP_RINTR] |= INTR_BS; - esp_raise_irq(s); - } + } else { + trace_esp_handle_ti(s->ti_size); + esp_do_nodma(s); } } @@ -789,12 +850,12 @@ uint64_t esp_reg_read(ESPState *s, uint32_t saddr) switch (saddr) { case ESP_FIFO: - if ((s->rregs[ESP_RSTAT] & STAT_PIO_MASK) == 0) { + if (s->dma_memory_read && s->dma_memory_write && + (s->rregs[ESP_RSTAT] & STAT_PIO_MASK) == 0) { /* Data out. */ qemu_log_mask(LOG_UNIMP, "esp: PIO data read not implemented\n"); s->rregs[ESP_FIFO] = 0; } else { - s->ti_size--; s->rregs[ESP_FIFO] = esp_fifo_pop(s); } val = s->rregs[ESP_FIFO]; @@ -846,7 +907,6 @@ void esp_reg_write(ESPState *s, uint32_t saddr, uint64_t val) if (s->do_cmd) { esp_cmdfifo_push(s, val); } else { - s->ti_size++; esp_fifo_push(s, val); } @@ -1047,6 +1107,7 @@ const VMStateDescription vmstate_esp = { VMSTATE_UINT8_TEST(cmdfifo_cdb_offset, ESPState, esp_is_version_5), VMSTATE_FIFO8_TEST(fifo, ESPState, esp_is_version_5), VMSTATE_FIFO8_TEST(cmdfifo, ESPState, esp_is_version_5), + VMSTATE_UINT8_TEST(ti_cmd, ESPState, esp_is_version_5), VMSTATE_END_OF_LIST() }, }; diff --git a/include/hw/scsi/esp.h b/include/hw/scsi/esp.h index 2fe8d20ab5..95088490aa 100644 --- a/include/hw/scsi/esp.h +++ b/include/hw/scsi/esp.h @@ -40,6 +40,7 @@ struct ESPState { uint32_t do_cmd; bool data_in_ready; + uint8_t ti_cmd; int dma_enabled; uint32_t async_len; From patchwork Sun Mar 7 12:08:50 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Cave-Ayland X-Patchwork-Id: 1448672 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4DthJk0PM8z9sW5 for ; Sun, 7 Mar 2021 23:55:01 +1100 (AEDT) Received: from localhost ([::1]:46968 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lIsvy-0007VF-St for incoming@patchwork.ozlabs.org; Sun, 07 Mar 2021 07:54:58 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:42126) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lIsH9-0004GK-Sn for qemu-devel@nongnu.org; Sun, 07 Mar 2021 07:12:48 -0500 Received: from mail.ilande.co.uk ([2001:41c9:1:41f::167]:43806 helo=mail.default.ilande.uk0.bigv.io) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lIsH7-0008QE-Vh for qemu-devel@nongnu.org; Sun, 07 Mar 2021 07:12:47 -0500 Received: from host86-148-34-47.range86-148.btcentralplus.com ([86.148.34.47] helo=kentang.home) by mail.default.ilande.uk0.bigv.io with esmtpsa (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1lIsGt-0002V5-0A; Sun, 07 Mar 2021 12:12:35 +0000 From: Mark Cave-Ayland To: qemu-devel@nongnu.org, peter.maydell@linaro.org Date: Sun, 7 Mar 2021 12:08:50 +0000 Message-Id: <20210307120850.10418-43-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210307120850.10418-1-mark.cave-ayland@ilande.co.uk> References: <20210307120850.10418-1-mark.cave-ayland@ilande.co.uk> MIME-Version: 1.0 X-SA-Exim-Connect-IP: 86.148.34.47 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk Subject: [PULL 42/42] esp: add support for unaligned accesses X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on mail.default.ilande.uk0.bigv.io) Received-SPF: pass client-ip=2001:41c9:1:41f::167; envelope-from=mark.cave-ayland@ilande.co.uk; helo=mail.default.ilande.uk0.bigv.io X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" When the MacOS toolbox ROM transfers data from a target device to an unaligned memory address, the first/last byte of a 16-bit transfer needs to be handled separately. This means that the first byte is preloaded into the FIFO before the transfer, or the last byte remains in the FIFO after the transfer. The result of this is that the PDMA routines must be updated so that the FIFO is loaded/unloaded if the last 16-bit word is used (rather than the last byte) and any remaining byte from a FIFO wraparound is handled correctly. Signed-off-by: Mark Cave-Ayland Reviewed-by: Laurent Vivier Message-Id: <20210304221103.6369-43-mark.cave-ayland@ilande.co.uk> --- hw/scsi/esp.c | 48 +++++++++++++++++++++++++++++++++++++++++------- 1 file changed, 41 insertions(+), 7 deletions(-) diff --git a/hw/scsi/esp.c b/hw/scsi/esp.c index f828e70865..507ab363bc 100644 --- a/hw/scsi/esp.c +++ b/hw/scsi/esp.c @@ -498,11 +498,22 @@ static void do_dma_pdma_cb(ESPState *s) if (to_device) { /* Copy FIFO data to device */ - len = MIN(fifo8_num_used(&s->fifo), ESP_FIFO_SZ); + len = MIN(s->async_len, ESP_FIFO_SZ); + len = MIN(len, fifo8_num_used(&s->fifo)); memcpy(s->async_buf, fifo8_pop_buf(&s->fifo, len, &n), len); - s->async_buf += len; - s->async_len -= len; - s->ti_size += len; + s->async_buf += n; + s->async_len -= n; + s->ti_size += n; + + if (n < len) { + /* Unaligned accesses can cause FIFO wraparound */ + len = len - n; + memcpy(s->async_buf, fifo8_pop_buf(&s->fifo, len, &n), len); + s->async_buf += n; + s->async_len -= n; + s->ti_size += n; + } + if (s->async_len == 0) { scsi_req_continue(s->current_req); return; @@ -526,12 +537,18 @@ static void do_dma_pdma_cb(ESPState *s) if (esp_get_tc(s) != 0) { /* Copy device data to FIFO */ - len = MIN(s->async_len, fifo8_num_free(&s->fifo)); + len = MIN(s->async_len, esp_get_tc(s)); + len = MIN(len, fifo8_num_free(&s->fifo)); fifo8_push_all(&s->fifo, s->async_buf, len); s->async_buf += len; s->async_len -= len; s->ti_size -= len; esp_set_tc(s, esp_get_tc(s) - len); + + if (esp_get_tc(s) == 0) { + /* Indicate transfer to FIFO is complete */ + s->rregs[ESP_RSTAT] |= STAT_TC; + } return; } @@ -606,12 +623,29 @@ static void esp_do_dma(ESPState *s) if (s->dma_memory_write) { s->dma_memory_write(s->dma_opaque, s->async_buf, len); } else { + /* Adjust TC for any leftover data in the FIFO */ + if (!fifo8_is_empty(&s->fifo)) { + esp_set_tc(s, esp_get_tc(s) - fifo8_num_used(&s->fifo)); + } + /* Copy device data to FIFO */ len = MIN(len, fifo8_num_free(&s->fifo)); fifo8_push_all(&s->fifo, s->async_buf, len); s->async_buf += len; s->async_len -= len; s->ti_size -= len; + + /* + * MacOS toolbox uses a TI length of 16 bytes for all commands, so + * commands shorter than this must be padded accordingly + */ + if (len < esp_get_tc(s) && esp_get_tc(s) <= ESP_FIFO_SZ) { + while (fifo8_num_used(&s->fifo) < ESP_FIFO_SZ) { + esp_fifo_push(s, 0); + len++; + } + } + esp_set_tc(s, esp_get_tc(s) - len); s->pdma_cb = do_dma_pdma_cb; esp_raise_drq(s); @@ -1160,7 +1194,7 @@ static void sysbus_esp_pdma_write(void *opaque, hwaddr addr, break; } dmalen = esp_get_tc(s); - if (dmalen == 0 || fifo8_is_full(&s->fifo)) { + if (dmalen == 0 || fifo8_num_free(&s->fifo) < 2) { s->pdma_cb(s); } } @@ -1183,7 +1217,7 @@ static uint64_t sysbus_esp_pdma_read(void *opaque, hwaddr addr, val = (val << 8) | esp_pdma_read(s); break; } - if (fifo8_is_empty(&s->fifo)) { + if (fifo8_num_used(&s->fifo) < 2) { s->pdma_cb(s); } return val;