From patchwork Sun Feb 28 14:12:30 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dario Binacchi X-Patchwork-Id: 1445250 X-Patchwork-Delegate: lokeshvutla@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=libero.it header.i=@libero.it header.a=rsa-sha256 header.s=s2021 header.b=UKChxZQj; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4DpQNQ4bBPz9sS8 for ; Mon, 1 Mar 2021 01:13:25 +1100 (AEDT) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 9D6B281F9C; Sun, 28 Feb 2021 15:13:08 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=quarantine dis=none) header.from=libero.it Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=libero.it header.i=@libero.it header.b="UKChxZQj"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id AD93181454; Sun, 28 Feb 2021 15:13:01 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=0.5 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FORGED_SPF_HELO,FREEMAIL_FROM, RCVD_IN_SORBS_WEB,SPF_HELO_PASS autolearn=no autolearn_force=no version=3.4.2 Received: from libero.it (smtp-17.italiaonline.it [213.209.10.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id C39D780505 for ; Sun, 28 Feb 2021 15:12:58 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=quarantine dis=none) header.from=libero.it Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=dariobin@libero.it Received: from passgat-Modern-14-A10M.homenet.telecomitalia.it ([87.20.116.197]) by smtp-17.iol.local with ESMTPA id GMoXljE45lChfGMoclwAEQ; Sun, 28 Feb 2021 15:12:58 +0100 x-libjamoibt: 1601 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=libero.it; s=s2021; t=1614521578; bh=zdUDFhnoPEU01b4unN3IUHVAFPWb5bpEn06dc+Buhq0=; h=From; b=UKChxZQjNQGg2u33aCYAq9kOOisM5o6cC4B1/Bttn+7BVdUQ7OzGf3KS+Anx6WfQ0 EahDSJoTVwEnNJ1cYWjFYECwUys8JU/skNzmYgfyUxNS+hO0ObPeXXUzGeaUw6nciY D8q8cyp0+/21VyPn0JsF07zDkEkJ3ZHTgpmfADjHG5CSuy9sp8mmfUEbafUQw4k2l+ 7s8xYjmowtpCneVwcGiGy7Oo9BRzkqwnVEQKJsG4+VGjNuR2baRCvGJ8OmhtneTIYU AOF7Aedwt1O7CDQxuRJM4+3Ifv/KGYolKdZ3dfp3mOYPCrO6Ro9uSIWyEuB/kFpOCN +Nnxh9dsN0ckg== X-CNFS-Analysis: v=2.4 cv=S6McfKgP c=1 sm=1 tr=0 ts=603ba4ea cx=a_exe a=AVqmXbCQpuNSdJmApS5GbQ==:117 a=AVqmXbCQpuNSdJmApS5GbQ==:17 a=cm27Pg_UAAAA:8 a=CNNU2WlDxd8r9xRg_hQA:9 a=xmb-EsYY8bH0VWELuYED:22 a=pHzHmUro8NiASowvMSCR:22 a=n87TN5wuljxrRezIQYnT:22 From: Dario Binacchi To: u-boot@lists.denx.de Cc: Lokesh Vutla , Dario Binacchi , Patrick Delaunay , Pratyush Yadav , Simon Glass Subject: [PATCH v3 01/12] pinctrl: single: fix format of structure documentation Date: Sun, 28 Feb 2021 15:12:30 +0100 Message-Id: <20210228141241.15931-2-dariobin@libero.it> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210228141241.15931-1-dariobin@libero.it> References: <20210228141241.15931-1-dariobin@libero.it> X-CMAE-Envelope: MS4xfLbTggMsQtVuGWm4YQf3jX0OsFxOJrzkCN4kmFz3rI9rOMEZtpu0qtDwEAxUjdZ5Q42m849qY1WxGMyn4qKDSt1Na2QTZx+E94jm37270uQMvcwq/LHW JkZ/dJcg5B+lTcWDGFU9AfZHXB5fW0Cp1rAB4hwSDztree7SPVZftvJAxhM1UuNGAh/hEW0sZ2xVPbsf7aop8OV0PQmMTuRuzwBFQ5aozLJtTo1QVf/57O+Z AMvVQkT78LfmtV4Hh/k3a9NvUaCxQFhhKd+QckrLQIZjhsAn1f9CcWmfZhOE+WcJRpzE3zRGQB6sib/cfJ8XF5p4UptR34zpHy7Ab+Wy02IZ46/xDm1b1ooI K9Hn97JO5xytGoxRngfmD0T7XQMYmg== X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.4 at phobos.denx.de X-Virus-Status: Clean U-Boot adopted the kernel-doc annotation style. Signed-off-by: Dario Binacchi Reviewed-by: Simon Glass --- (no changes since v2) Changes in v2: - Added Simon Glass review tag. drivers/pinctrl/pinctrl-single.c | 45 +++++++++++++++++++++++++------- 1 file changed, 36 insertions(+), 9 deletions(-) diff --git a/drivers/pinctrl/pinctrl-single.c b/drivers/pinctrl/pinctrl-single.c index 20c3c82aa9..c9a6c272bf 100644 --- a/drivers/pinctrl/pinctrl-single.c +++ b/drivers/pinctrl/pinctrl-single.c @@ -10,23 +10,50 @@ #include #include +/** + * struct single_pdata - platform data + * @base: first configuration register + * @offset: index of last configuration register + * @mask: configuration-value mask bits + * @width: configuration register bit width + * @bits_per_mux: true if one register controls more than one pin + */ struct single_pdata { - fdt_addr_t base; /* first configuration register */ - int offset; /* index of last configuration register */ - u32 mask; /* configuration-value mask bits */ - int width; /* configuration register bit width */ + fdt_addr_t base; + int offset; + u32 mask; + int width; bool bits_per_mux; }; +/** + * struct single_fdt_pin_cfg - pin configuration + * + * This structure is used for the pin configuration parameters in case + * the register controls only one pin. + * + * @reg: configuration register offset + * @val: configuration register value + */ struct single_fdt_pin_cfg { - fdt32_t reg; /* configuration register offset */ - fdt32_t val; /* configuration register value */ + fdt32_t reg; + fdt32_t val; }; +/** + * struct single_fdt_bits_cfg - pin configuration + * + * This structure is used for the pin configuration parameters in case + * the register controls more than one pin. + * + * @reg: configuration register offset + * @val: configuration register value + * @mask: configuration register mask + */ struct single_fdt_bits_cfg { - fdt32_t reg; /* configuration register offset */ - fdt32_t val; /* configuration register value */ - fdt32_t mask; /* configuration register mask */ + fdt32_t reg; + fdt32_t val; + fdt32_t mask; }; /** From patchwork Sun Feb 28 14:12:31 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dario Binacchi X-Patchwork-Id: 1445253 X-Patchwork-Delegate: lokeshvutla@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=libero.it header.i=@libero.it header.a=rsa-sha256 header.s=s2021 header.b=opt8iRJu; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4DpQNs2hRcz9rx6 for ; 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Sun, 28 Feb 2021 15:12:59 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=quarantine dis=none) header.from=libero.it Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=dariobin@libero.it Received: from passgat-Modern-14-A10M.homenet.telecomitalia.it ([87.20.116.197]) by smtp-17.iol.local with ESMTPA id GMoXljE45lChfGModlwAEY; Sun, 28 Feb 2021 15:12:59 +0100 x-libjamoibt: 1601 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=libero.it; s=s2021; t=1614521579; bh=ASlkKTD37pqtbvwGTkPuC4gLO/4NXIHhrW2xKH8S/20=; h=From; b=opt8iRJuYp/5zqzV7QNoiOVIecaons17MOzgjC8VmEoGqJFTCOKdBOiQulapLOVDw 4PGuLTUZC3Eew7HsC7QUOSgmBdpR/wExECoIRZn7fyV1VfR4kb8txe/qlI0WNzDNXd a5FkKRKvbC99opVA2goesOehta0P0nYhhMvPF7Go8iGzP4JDeoekpA1d/6N9nYAAxZ mOjiqm8oyKIxfKRyOXLzeZ4nafaVv3YXFlDG5xpoIW9KgsxpN6OSpaTwBpnSh/K4xh yRu4RDm0U4Vcy2nZn7lsnefXodaBKVFqxC/ghppuSQUDExBi7TMr0IIXcJ4WDn6Ulm H/ZaGvmMrrsfA== X-CNFS-Analysis: v=2.4 cv=S6McfKgP c=1 sm=1 tr=0 ts=603ba4eb cx=a_exe a=AVqmXbCQpuNSdJmApS5GbQ==:117 a=AVqmXbCQpuNSdJmApS5GbQ==:17 a=cm27Pg_UAAAA:8 a=sozttTNsAAAA:8 a=v0YLU9JjO2Y4mDxuVjMA:9 a=xmb-EsYY8bH0VWELuYED:22 a=aeg5Gbbo78KNqacMgKqU:22 From: Dario Binacchi To: u-boot@lists.denx.de Cc: Lokesh Vutla , Dario Binacchi , Andy Shevchenko , Patrick Delaunay , Pratyush Yadav , Simon Glass Subject: [PATCH v3 02/12] pinctrl: single: fix the loop counter variable type Date: Sun, 28 Feb 2021 15:12:31 +0100 Message-Id: <20210228141241.15931-3-dariobin@libero.it> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210228141241.15931-1-dariobin@libero.it> References: <20210228141241.15931-1-dariobin@libero.it> X-CMAE-Envelope: MS4xfFnMY2sSEw+ezUkgRQs/nEVHtxt9azOz3t1Jt3SbYyXHyRN5G9xa3xLWIsLWHzbaagD7NE/+n4SJ0IB21znSp357F5WQm3Z8aoCB3W5zYHWf/KtYLSbI YmiHsq9x+x5IGG7/F9TwCDJenm/+kZjkO9H+XpOjQfm2SzfWIp9sxq7hSASdVUULuyBmL1BC05CZgTGc3Gb4p26UjBUUH2W+KdooJPMolRijcOTnnao42CjC nneFKmqzaT+rvhuqP8kNfd2Sv0E/9y34+Ju3EmUFJrtmcYLUZixzmdhJO3Li8eNiJZao0KS18wiX0quRjMkON4gCdmZ/IeADpCh85U1S+oQGV5bjyEmDfGPA gmXVIvEJd4LziQZiaaYwWMgEXThAQnRfiMBPSqOCzfCBGF8o+JS6NyMkwqGkp6je35WaKRVZSw7R5syCjBn0ibBK1FgUZA== X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.4 at phobos.denx.de X-Virus-Status: Clean The 'n' variable is used as a loop counter, not as a physical address, and is used in a comparison with an int. So it makes sense to change its type from phys_addr_t to int. Signed-off-by: Dario Binacchi Reviewed-by: Simon Glass Reviewed-by: Pratyush Yadav --- (no changes since v2) Changes in v2: - Updated commit message. - Added Simon Glass review tag. - Added Pratyush Yadav review tag. drivers/pinctrl/pinctrl-single.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/pinctrl/pinctrl-single.c b/drivers/pinctrl/pinctrl-single.c index c9a6c272bf..49ed15211d 100644 --- a/drivers/pinctrl/pinctrl-single.c +++ b/drivers/pinctrl/pinctrl-single.c @@ -75,8 +75,8 @@ static int single_configure_pins(struct udevice *dev, int size) { struct single_pdata *pdata = dev_get_plat(dev); - int count = size / sizeof(struct single_fdt_pin_cfg); - phys_addr_t n, reg; + int n, count = size / sizeof(struct single_fdt_pin_cfg); + phys_addr_t reg; u32 val; for (n = 0; n < count; n++, pins++) { @@ -109,8 +109,8 @@ static int single_configure_bits(struct udevice *dev, int size) { struct single_pdata *pdata = dev_get_plat(dev); - int count = size / sizeof(struct single_fdt_bits_cfg); - phys_addr_t n, reg; + int n, count = size / sizeof(struct single_fdt_bits_cfg); + phys_addr_t reg; u32 val, mask; for (n = 0; n < count; n++, pins++) { From patchwork Sun Feb 28 14:12:32 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dario Binacchi X-Patchwork-Id: 1445254 X-Patchwork-Delegate: lokeshvutla@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=libero.it header.i=@libero.it header.a=rsa-sha256 header.s=s2021 header.b=ZNhnUThA; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4DpQP33kR2z9rx6 for ; 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Sun, 28 Feb 2021 15:12:59 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=quarantine dis=none) header.from=libero.it Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=dariobin@libero.it Received: from passgat-Modern-14-A10M.homenet.telecomitalia.it ([87.20.116.197]) by smtp-17.iol.local with ESMTPA id GMoXljE45lChfGModlwAEn; Sun, 28 Feb 2021 15:12:59 +0100 x-libjamoibt: 1601 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=libero.it; s=s2021; t=1614521579; bh=eW2qBIhkdzzQtc+UD6U5OB1Fs/AiA/h2JEsjsJES/eY=; h=From; b=ZNhnUThAas0ZED2t64WlqQIMxGWnqkov8lgsHqhu45hQSVeZBr0dpYiRxGh5CoHoy ei3RefBRW36iLWeI7J0yg1H8rqU2YAwD8a8Xk6sxzX4xKgjJs+W9j9KClyLZg0sBdM Q4uxpcLwo7XxLwS+7/C9051WhHFsktJk+QIPhpH55LjsgX0gutjGuQ73i/YyKi7pKJ Snf5hd93mth/nQHxh0NbCh5qYOt6v97FcWELTzDhZ8HADtvDcCEQruAYn38MJAS9QP QaKbZTCUHSNwT+xFlvDOaFqBxVJvAHvjHtNxIMOh9Aut033o5SMaiHdl3A3spFnyx2 K4q2/zQAOuq5g== X-CNFS-Analysis: v=2.4 cv=S6McfKgP c=1 sm=1 tr=0 ts=603ba4eb cx=a_exe a=AVqmXbCQpuNSdJmApS5GbQ==:117 a=AVqmXbCQpuNSdJmApS5GbQ==:17 a=sozttTNsAAAA:8 a=wv_ar1DUYrJP48xX2MwA:9 a=aeg5Gbbo78KNqacMgKqU:22 From: Dario Binacchi To: u-boot@lists.denx.de Cc: Lokesh Vutla , Dario Binacchi , Patrick Delaunay , Pratyush Yadav , Simon Glass Subject: [PATCH v3 03/12] pinctrl: single: fix offset management Date: Sun, 28 Feb 2021 15:12:32 +0100 Message-Id: <20210228141241.15931-4-dariobin@libero.it> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210228141241.15931-1-dariobin@libero.it> References: <20210228141241.15931-1-dariobin@libero.it> X-CMAE-Envelope: MS4xfFnMY2sSEw+ezUkgRQs/nEVHtxt9azOz3t1Jt3SbYyXHyRN5G9xa3xLWIsLWHzbaagD7NE/+n4SJ0IB21znSp357F5WQm3Z8aoCB3W5zYHWf/KtYLSbI YmiHsq9x+x5IGG7/F9TwCDJenm/+kZjkO9H+XpOjQfm2SzfWIp9sxq7hVXPcZcLgaJXkWT2XWRc5XtE3B7O1gG19H0lEajhBH8r2kTpY5aIS8C1csbfcZKyg X2206Bde8U/vjugZuRWUmSSd1WfB2rh3VFudGGK7JbfsS1Xp57pvm17R/Qx6GSjUsDkDL9MqmpNofwupyIahybMy97iQDZ9dckOWxLfI/n5wpfcnXiwlqome iL+AaC4EFv9b4a1ScpyBCQpjagXmNQ== X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.4 at phobos.denx.de X-Virus-Status: Clean The pinmux configuration DT node of a peripheral does not define a physical address but an offset. Only by adding it to the base address of the controller it is possible to calculate the physical address of the register to be configured. Printing an offset also requires a different formatting option than a physical address. Signed-off-by: Dario Binacchi Reviewed-by: Pratyush Yadav --- Changes in v3: - Added Pratyush Yadav review tag. drivers/pinctrl/pinctrl-single.c | 24 ++++++++++++++---------- 1 file changed, 14 insertions(+), 10 deletions(-) diff --git a/drivers/pinctrl/pinctrl-single.c b/drivers/pinctrl/pinctrl-single.c index 49ed15211d..935b5e920d 100644 --- a/drivers/pinctrl/pinctrl-single.c +++ b/drivers/pinctrl/pinctrl-single.c @@ -77,15 +77,17 @@ static int single_configure_pins(struct udevice *dev, struct single_pdata *pdata = dev_get_plat(dev); int n, count = size / sizeof(struct single_fdt_pin_cfg); phys_addr_t reg; - u32 val; + u32 offset, val; for (n = 0; n < count; n++, pins++) { - reg = fdt32_to_cpu(pins->reg); - if ((reg < 0) || (reg > pdata->offset)) { - dev_dbg(dev, " invalid register offset 0x%pa\n", ®); + offset = fdt32_to_cpu(pins->reg); + if (offset < 0 || offset > pdata->offset) { + dev_dbg(dev, " invalid register offset 0x%x\n", + offset); continue; } - reg += pdata->base; + + reg = pdata->base + offset; val = fdt32_to_cpu(pins->val) & pdata->mask; switch (pdata->width) { case 16: @@ -111,15 +113,17 @@ static int single_configure_bits(struct udevice *dev, struct single_pdata *pdata = dev_get_plat(dev); int n, count = size / sizeof(struct single_fdt_bits_cfg); phys_addr_t reg; - u32 val, mask; + u32 offset, val, mask; for (n = 0; n < count; n++, pins++) { - reg = fdt32_to_cpu(pins->reg); - if ((reg < 0) || (reg > pdata->offset)) { - dev_dbg(dev, " invalid register offset 0x%pa\n", ®); + offset = fdt32_to_cpu(pins->reg); + if (offset < 0 || offset > pdata->offset) { + dev_dbg(dev, " invalid register offset 0x%x\n", + offset); continue; } - reg += pdata->base; + + reg = pdata->base + offset; mask = fdt32_to_cpu(pins->mask); val = fdt32_to_cpu(pins->val) & mask; From patchwork Sun Feb 28 14:12:33 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dario Binacchi X-Patchwork-Id: 1445255 X-Patchwork-Delegate: lokeshvutla@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; 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spf=pass smtp.mailfrom=dariobin@libero.it Received: from passgat-Modern-14-A10M.homenet.telecomitalia.it ([87.20.116.197]) by smtp-17.iol.local with ESMTPA id GMoXljE45lChfGMoelwAF3; Sun, 28 Feb 2021 15:13:00 +0100 x-libjamoibt: 1601 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=libero.it; s=s2021; t=1614521580; bh=gWaLurHHcgaZ/hHTCOIdnLTz209gy4uemp+FlfeFZKE=; h=From; b=A7YAd2Xy7cMM4tl86fssqzMzWZOHKmIqD8nlBAEsErYioGlEdOesb50cgf8t+cQnS +mG97nnum3dDawmUNuwJd9XZsDTzGhAX862G5NUqO7mb7exAyzUldvBTRwOcHMRbvv r4dXMNaQzUdnFsvIR6j5rDisYi7gzytHjR/IS+5JXnCOW0HNRFKHOqzZq+p86VY1pX mwKzBTeoB18DNnT1CEeWdO3nLZYTLJwbk+Uwt5+UM1JoYyGcNXuvjnHnLL3mM7VC0L SRkdPk618Nyx7dviri+BS2wf2JJveb+5BK5wxnVO+/9yGDD1dZfF0pkEl8hyjOT2SZ 98IFK+W5b5wMA== X-CNFS-Analysis: v=2.4 cv=S6McfKgP c=1 sm=1 tr=0 ts=603ba4ec cx=a_exe a=AVqmXbCQpuNSdJmApS5GbQ==:117 a=AVqmXbCQpuNSdJmApS5GbQ==:17 a=sozttTNsAAAA:8 a=u5BIsiXaYWSDGc_4nFgA:9 a=aeg5Gbbo78KNqacMgKqU:22 From: Dario Binacchi To: u-boot@lists.denx.de Cc: Lokesh Vutla , Dario Binacchi , Patrick Delaunay , Pratyush Yadav , Simon Glass Subject: [PATCH v3 04/12] pinctrl: single: fix debug messages formatting Date: Sun, 28 Feb 2021 15:12:33 +0100 Message-Id: <20210228141241.15931-5-dariobin@libero.it> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210228141241.15931-1-dariobin@libero.it> References: <20210228141241.15931-1-dariobin@libero.it> X-CMAE-Envelope: MS4xfL8eiwZaH6CEcOGR37WazBixH2tbppefJIfJFAiahE55g09Ic3J5V3bBnHkldazQ8hZyfrC9SuEly6ZziLyC37/PojCpzpmkb2wJrZzKsl5V0uadWgFV yg698kTAiuMkJ5MH25qRwjnCdmh9vpet3jgpmjMNswalcInG2nn2TDtxPDZdcGPxLApMHafZIhvmXLIqNZXRVnp4tJNLr20bopaoosW954XmmEaR5UErY9o+ wh4w5Y7/gAHamneeXri8RsuGVtRJqyIC8fx0f4QGHiSLOMJILE5KMb7fqYeUOvTiJfT0UG+JZhmxVbMuSbQnl9p2e0GDVHqCMo8Wskvm/xIFbOT5cckfGsbN awiDY3FzqXOTvIJsdCur+Yr70bWv6w== X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.4 at phobos.denx.de X-Virus-Status: Clean The dev_dbg(dev, " reg/val 0x%pa/0x%08x\n", ®, val); prints the 'reg' address preceded by the prefix 0x0x instead of 0x. This because the printf '%pa' format specifier already prepends the prefix '0x' to the address displayed. Signed-off-by: Dario Binacchi Reviewed-by: Pratyush Yadav --- Changes in v3: - Updated commit message. - Added Pratyush Yadav review tag. Changes in v2: - Updated commit message - Split in 2 commits drivers/pinctrl/pinctrl-single.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/pinctrl-single.c b/drivers/pinctrl/pinctrl-single.c index 935b5e920d..cec00e289c 100644 --- a/drivers/pinctrl/pinctrl-single.c +++ b/drivers/pinctrl/pinctrl-single.c @@ -101,7 +101,7 @@ static int single_configure_pins(struct udevice *dev, pdata->width); continue; } - dev_dbg(dev, " reg/val 0x%pa/0x%08x\n", ®, val); + dev_dbg(dev, " reg/val %pa/0x%08x\n", ®, val); } return 0; } @@ -140,7 +140,7 @@ static int single_configure_bits(struct udevice *dev, pdata->width); continue; } - dev_dbg(dev, " reg/val 0x%pa/0x%08x\n", ®, val); + dev_dbg(dev, " reg/val %pa/0x%08x\n", ®, val); } return 0; } From patchwork Sun Feb 28 14:12:34 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dario Binacchi X-Patchwork-Id: 1445256 X-Patchwork-Delegate: lokeshvutla@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; 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Signed-off-by: Dario Binacchi Reviewed-by: Pratyush Yadav --- Changes in v3: - Added Pratyush Yadav review tag. Changes in v2: - Check dev_read_addr_size return value. drivers/pinctrl/pinctrl-single.c | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/drivers/pinctrl/pinctrl-single.c b/drivers/pinctrl/pinctrl-single.c index cec00e289c..d5656de8e8 100644 --- a/drivers/pinctrl/pinctrl-single.c +++ b/drivers/pinctrl/pinctrl-single.c @@ -182,17 +182,19 @@ static int single_set_state(struct udevice *dev, static int single_of_to_plat(struct udevice *dev) { fdt_addr_t addr; - u32 of_reg[2]; - int res; + fdt_size_t size; struct single_pdata *pdata = dev_get_plat(dev); pdata->width = dev_read_u32_default(dev, "pinctrl-single,register-width", 0); - res = dev_read_u32_array(dev, "reg", of_reg, 2); - if (res) - return res; - pdata->offset = of_reg[1] - pdata->width / 8; + addr = dev_read_addr_size(dev, "reg", &size); + if (addr == FDT_ADDR_T_NONE) { + dev_err(dev, "failed to get base register size\n"); + return -EINVAL; + } + + pdata->offset = size - pdata->width / BITS_PER_BYTE; addr = dev_read_addr(dev); if (addr == FDT_ADDR_T_NONE) { From patchwork Sun Feb 28 14:12:35 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dario Binacchi X-Patchwork-Id: 1445252 X-Patchwork-Delegate: lokeshvutla@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=libero.it header.i=@libero.it header.a=rsa-sha256 header.s=s2021 header.b=wm7DYGDS; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4DpQNd1vdsz9rx6 for ; Mon, 1 Mar 2021 01:13:37 +1100 (AEDT) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id E74F981A26; Sun, 28 Feb 2021 15:13:16 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=quarantine dis=none) header.from=libero.it Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=libero.it header.i=@libero.it header.b="wm7DYGDS"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 7AACF806C5; Sun, 28 Feb 2021 15:13:07 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=0.5 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FORGED_SPF_HELO,FREEMAIL_FROM, RCVD_IN_MSPIKE_H4,RCVD_IN_MSPIKE_WL,RCVD_IN_SORBS_WEB,SPF_HELO_PASS autolearn=no autolearn_force=no version=3.4.2 Received: from libero.it (smtp-17-i2.italiaonline.it [213.209.12.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id E4F87804E7 for ; Sun, 28 Feb 2021 15:13:01 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=quarantine dis=none) header.from=libero.it Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=dariobin@libero.it Received: from passgat-Modern-14-A10M.homenet.telecomitalia.it ([87.20.116.197]) by smtp-17.iol.local with ESMTPA id GMoXljE45lChfGMoflwAFT; Sun, 28 Feb 2021 15:13:01 +0100 x-libjamoibt: 1601 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=libero.it; s=s2021; t=1614521581; bh=aYjTb4RaEaxpnwVlZ2u6DCLNXArLtyQH9ZkaBTUDByM=; h=From; b=wm7DYGDSSxgQGbTuLBN+Aig2hqGydVOMmjAg/bkejuV/m9pNS2QuoUOf3ZLtL3r9h l8kWPjeGTuqJm5JkK+LIMi7CVfskvevqlHNAza7jeBK9uo3b32q5yg+xlQDVPCfj2e UZerAoLKaC1+/hb2r8ubkbx6720RyWQRTuGSd8gluxtSI6Yn9mF/huxjBR5Nfqw+Sr wJiCD644DGeN41Cx2S08eJycCrxKPo5eptdaJKWJkZeZdIpLksFmfDaTSxaGJeSyQn piCLg92rbboxj+DwhVmUefAtvCu6cp0UXbQvu2tNFGWwx/PcErJkaoMm8iAPWLoYoR 3LlESKjlt4LHw== X-CNFS-Analysis: v=2.4 cv=S6McfKgP c=1 sm=1 tr=0 ts=603ba4ed cx=a_exe a=AVqmXbCQpuNSdJmApS5GbQ==:117 a=AVqmXbCQpuNSdJmApS5GbQ==:17 a=cm27Pg_UAAAA:8 a=AewqRzli-FD5yDso3x8A:9 a=xmb-EsYY8bH0VWELuYED:22 From: Dario Binacchi To: u-boot@lists.denx.de Cc: Lokesh Vutla , Dario Binacchi , Patrick Delaunay , Pratyush Yadav , Simon Glass Subject: [PATCH v3 06/12] pinctrl: single: check "register-width" DT property Date: Sun, 28 Feb 2021 15:12:35 +0100 Message-Id: <20210228141241.15931-7-dariobin@libero.it> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210228141241.15931-1-dariobin@libero.it> References: <20210228141241.15931-1-dariobin@libero.it> X-CMAE-Envelope: MS4xfM8RWVc3l9xy6e1y7fCsExnd+zkGMm750wJjO4eiqTpZynmcLFjRmz3/cHOQo8vZ383kZPLUUNmLrIST7yaDdfkm8pPn3vApS/7/TZgBFiCqjLgxDYy1 W9rzIWOVhCEGU5eqi/A32anZz7zNki2KW3FLFVkK74xOzt7Jw4MsG6i8Gq2k45dUc3KHc+N2in+16vEBsP4gcXycybkxWFZ7FGuQNM/fqPYS1TYVMk/XBlEV txxhWB6+QyheRCB0voLJdBDL4xOETYFRbyacT9soEhCtM8ARjaGtp1O6fnZLU1wVZXGSqWL93/XlCBiim0hzyWbViUUCnoEiGEgIfpleJ+UGuQIPftQloKF6 cqHzwO/tavTTD9Ve70g7xUuDfmXYsg== X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.4 at phobos.denx.de X-Virus-Status: Clean In more recent versions of the Linux kernel the driver's probe function returns an error if the "pinctrl-single,register-width" DT property is missing. The lack of this information, in fact, does not allow to know whether to access the registers of the controller at 8, 16, ... bits. Signed-off-by: Dario Binacchi Reviewed-by: Simon Glass --- (no changes since v2) Changes in v2: - Updated commit message. - Added Simon Glass review tag. drivers/pinctrl/pinctrl-single.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/drivers/pinctrl/pinctrl-single.c b/drivers/pinctrl/pinctrl-single.c index d5656de8e8..5ade108875 100644 --- a/drivers/pinctrl/pinctrl-single.c +++ b/drivers/pinctrl/pinctrl-single.c @@ -22,7 +22,7 @@ struct single_pdata { fdt_addr_t base; int offset; u32 mask; - int width; + u32 width; bool bits_per_mux; }; @@ -184,9 +184,13 @@ static int single_of_to_plat(struct udevice *dev) fdt_addr_t addr; fdt_size_t size; struct single_pdata *pdata = dev_get_plat(dev); + int ret; - pdata->width = - dev_read_u32_default(dev, "pinctrl-single,register-width", 0); + ret = dev_read_u32(dev, "pinctrl-single,register-width", &pdata->width); + if (ret) { + dev_err(dev, "missing register width\n"); + return ret; + } addr = dev_read_addr_size(dev, "reg", &size); if (addr == FDT_ADDR_T_NONE) { From patchwork Sun Feb 28 14:12:36 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dario Binacchi X-Patchwork-Id: 1445258 X-Patchwork-Delegate: lokeshvutla@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=libero.it header.i=@libero.it header.a=rsa-sha256 header.s=s2021 header.b=D1p7lmYT; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4DpQPy6sDPz9rx6 for ; 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Sun, 28 Feb 2021 15:13:02 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=quarantine dis=none) header.from=libero.it Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=dariobin@libero.it Received: from passgat-Modern-14-A10M.homenet.telecomitalia.it ([87.20.116.197]) by smtp-17.iol.local with ESMTPA id GMoXljE45lChfGMoflwAFj; Sun, 28 Feb 2021 15:13:01 +0100 x-libjamoibt: 1601 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=libero.it; s=s2021; t=1614521582; bh=Na5XFmX9JT5N2CgmW1i0/A+Qxjqhnqy290T+H3/3E8k=; h=From; b=D1p7lmYTOgeJnKvoFxfqW3xliY45TD7I0o4RPvQ95CGz0AyHK3bY7QqjgTXiwHqC+ gmc/yXyFCROiBPKlqyGIG9Ix/t4ZgDgRhq8OyfZr93NjrN8LHrRX8T/rsoz5wBkxru ypnfravN5QtZN4hAossKUb1VTLaBEsplJDqCpAkFiJt7MeSh3osmOjuRW7ib0a/ydD Evvha6/BklURrBWTO1DUKFoiccrjvn6Io83tqunhp8OdPqFyE6yN3BjY34SQW88CII ThkR9ekTQbc+mutu4/Px6wEcWix32xccTsEA04kui/Ia01BG+GZcULSC7GJzEhGapZ Ryg6neMVC6jEQ== X-CNFS-Analysis: v=2.4 cv=S6McfKgP c=1 sm=1 tr=0 ts=603ba4ee cx=a_exe a=AVqmXbCQpuNSdJmApS5GbQ==:117 a=AVqmXbCQpuNSdJmApS5GbQ==:17 a=cm27Pg_UAAAA:8 a=9az6cxj04SzJwZhvl5UA:9 a=xmb-EsYY8bH0VWELuYED:22 From: Dario Binacchi To: u-boot@lists.denx.de Cc: Lokesh Vutla , Dario Binacchi , Patrick Delaunay , Pratyush Yadav , Simon Glass Subject: [PATCH v3 07/12] pinctrl: single: change function mask default value Date: Sun, 28 Feb 2021 15:12:36 +0100 Message-Id: <20210228141241.15931-8-dariobin@libero.it> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210228141241.15931-1-dariobin@libero.it> References: <20210228141241.15931-1-dariobin@libero.it> X-CMAE-Envelope: MS4xfO6X1T1djz9LsJX3nuWPuMVWTiaFGk/kdFh+GlgBe1aHPpEk39G1GviyiKhmncXa8BmIB0grYsNlW7o1IYPv1p90rI4waD4DJhxwrVXkXxbqkiTpulJb MjZYD82ekEGqGKDfI9UEPvyKrvQlwEhHvccVB7iB2enpS+1+RBgkRc4nXhHWIeuXkcCBRM5/p2lehAFiiOhE5cQ1FulqrrV8Gll6AO6CsE3JcR3BvNMtFS1W 9tkhopSj9m9e26yREfJHld1MIooCm3LtjwUnyKHUNo3fSx1BxhbWbUcvCO0evRaV/P6bhvKksNXDvWiKvDxBmMRUf32joZTBiB4VaFBpdUJ5JtvgFsx2djae rwhOB+jJZG9zujgKlLpZUF402KST1Q== X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.4 at phobos.denx.de X-Virus-Status: Clean The patch is inspired by more recent versions of the Linux driver. Replacing the default value 0xffffffff of the function mask with 0 is certainly more conservative in case the "pinctrl-single,function-mask" DT property is missing. Signed-off-by: Dario Binacchi Reviewed-by: Simon Glass --- Changes in v3: - Added Simon Glass review tag. drivers/pinctrl/pinctrl-single.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/pinctrl-single.c b/drivers/pinctrl/pinctrl-single.c index 5ade108875..630a6c08b8 100644 --- a/drivers/pinctrl/pinctrl-single.c +++ b/drivers/pinctrl/pinctrl-single.c @@ -79,6 +79,10 @@ static int single_configure_pins(struct udevice *dev, phys_addr_t reg; u32 offset, val; + /* If function mask is null, needn't enable it. */ + if (!pdata->mask) + return 0; + for (n = 0; n < count; n++, pins++) { offset = fdt32_to_cpu(pins->reg); if (offset < 0 || offset > pdata->offset) { @@ -207,8 +211,12 @@ static int single_of_to_plat(struct udevice *dev) } pdata->base = addr; - pdata->mask = dev_read_u32_default(dev, "pinctrl-single,function-mask", - 0xffffffff); + ret = dev_read_u32(dev, "pinctrl-single,function-mask", &pdata->mask); + if (ret) { + pdata->mask = 0; + dev_warn(dev, "missing function register mask\n"); + } + pdata->bits_per_mux = dev_read_bool(dev, "pinctrl-single,bit-per-mux"); return 0; From patchwork Sun Feb 28 14:12:37 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dario Binacchi X-Patchwork-Id: 1445260 X-Patchwork-Delegate: lokeshvutla@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=libero.it header.i=@libero.it header.a=rsa-sha256 header.s=s2021 header.b=AlxtTnAx; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4DpQQP5mS6z9rx6 for ; Mon, 1 Mar 2021 01:15:09 +1100 (AEDT) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 83BF082748; Sun, 28 Feb 2021 15:14:05 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=quarantine dis=none) header.from=libero.it Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=libero.it header.i=@libero.it header.b="AlxtTnAx"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 15B6781A26; Sun, 28 Feb 2021 15:13:12 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=0.5 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FORGED_SPF_HELO,FREEMAIL_FROM, RCVD_IN_MSPIKE_H4,RCVD_IN_MSPIKE_WL,RCVD_IN_SORBS_WEB,SPF_HELO_PASS autolearn=no autolearn_force=no version=3.4.2 Received: from libero.it (smtp-17-i2.italiaonline.it [213.209.12.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id A119E81015 for ; Sun, 28 Feb 2021 15:13:02 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=quarantine dis=none) header.from=libero.it Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=dariobin@libero.it Received: from passgat-Modern-14-A10M.homenet.telecomitalia.it ([87.20.116.197]) by smtp-17.iol.local with ESMTPA id GMoXljE45lChfGMoglwAFv; Sun, 28 Feb 2021 15:13:02 +0100 x-libjamoibt: 1601 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=libero.it; s=s2021; t=1614521582; bh=BxW940qeHGSwEVoibefkVuxvvzmT0f9WRS8ROUrr3tg=; h=From; b=AlxtTnAxc7GbjwajTGC0mITIVQCQM1Es0sl6i1/UMLep30/EsYzVeTSjEPFNUs0gm DZW6TGHoK5Tt+ca4VxtOFaVwAVFL007hrguSWtunaHVTW07dF836+T2xDmLwWRq4MK NXLKTqZaXXCKsvrU5xD5N6P1qNNxorKH/P4ownO4f35wNkV5j+zFvuH10ec68kl+OZ VpNH/Vm410+HVMr0IB3KAhVd64RWB38HlEAd084wuOHQpdfyPjsofeq+0VXgD2Mv1V yZ5/HtEEzCNzt4aqUyjZNEUcngINqc4lwxZzXgAh1eTf0A29tmOwEez1LwCDV1GlIY Q/busxOfwD8Vg== X-CNFS-Analysis: v=2.4 cv=S6McfKgP c=1 sm=1 tr=0 ts=603ba4ee cx=a_exe a=AVqmXbCQpuNSdJmApS5GbQ==:117 a=AVqmXbCQpuNSdJmApS5GbQ==:17 a=cm27Pg_UAAAA:8 a=SHmA3wKN3BWJ4-rrrCYA:9 a=xmb-EsYY8bH0VWELuYED:22 From: Dario Binacchi To: u-boot@lists.denx.de Cc: Lokesh Vutla , Dario Binacchi , Andy Shevchenko , Patrick Delaunay , Pratyush Yadav , Simon Glass Subject: [PATCH v3 08/12] pinctrl: single: add register access functions Date: Sun, 28 Feb 2021 15:12:37 +0100 Message-Id: <20210228141241.15931-9-dariobin@libero.it> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210228141241.15931-1-dariobin@libero.it> References: <20210228141241.15931-1-dariobin@libero.it> X-CMAE-Envelope: MS4xfO6X1T1djz9LsJX3nuWPuMVWTiaFGk/kdFh+GlgBe1aHPpEk39G1GviyiKhmncXa8BmIB0grYsNlW7o1IYPv1p90rI4waD4DJhxwrVXkXxbqkiTpulJb MjZYD82ekEGqGKDfI9UEPvyKrvQlwEhHvccVB7iB2enpS+1+RBgkRc4nvkLAYDpjErMn0d/W6pYvIkDG2UTf5jnapmMbN9FlsCRUYzoqtnQc0DeTbplu0cvv nSwKUJrh1Cp1T8IepJnryRxOpnKyf2MCrLeuNLbmf1KbAfCu5eSxtUCbf8jHbcWyvQD6Av5Jtrr08SxbH9eBKTn0InkOsnNQm/yjen3yUr6Z6u+tyHzTfzVy 1VlH+YqHcY3U7Iih5hgrh4H4IFEWCEHezKD7WkVNZV8vmAbYtnNsm3pqFA6KmNAgRXan/4HeM/LwRBe/j4liKs6fnDkZwA== X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.4 at phobos.denx.de X-Virus-Status: Clean The configuration of pinmux registers was implemented with duplicate code which can be removed by adding two functions for read/write access. Access to 8-bit registers has also been added. Signed-off-by: Dario Binacchi Reviewed-by: Simon Glass --- Changes in v3: - Added Simon Glass review tag. Changes in v2: - Updated commit message. - Remove pointer to access functions. drivers/pinctrl/pinctrl-single.c | 71 +++++++++++++++++++++----------- 1 file changed, 46 insertions(+), 25 deletions(-) diff --git a/drivers/pinctrl/pinctrl-single.c b/drivers/pinctrl/pinctrl-single.c index 630a6c08b8..5b3ccc2281 100644 --- a/drivers/pinctrl/pinctrl-single.c +++ b/drivers/pinctrl/pinctrl-single.c @@ -56,6 +56,38 @@ struct single_fdt_bits_cfg { fdt32_t mask; }; +static unsigned int single_read(struct udevice *dev, fdt_addr_t reg) +{ + struct single_pdata *pdata = dev_get_plat(dev); + + switch (pdata->width) { + case 8: + return readb(reg); + case 16: + return readw(reg); + default: /* 32 bits */ + return readl(reg); + } + + return readb(reg); +} + +static void single_write(struct udevice *dev, unsigned int val, fdt_addr_t reg) +{ + struct single_pdata *pdata = dev_get_plat(dev); + + switch (pdata->width) { + case 8: + writeb(val, reg); + break; + case 16: + writew(val, reg); + break; + default: /* 32 bits */ + writel(val, reg); + } +} + /** * single_configure_pins() - Configure pins based on FDT data * @@ -93,19 +125,10 @@ static int single_configure_pins(struct udevice *dev, reg = pdata->base + offset; val = fdt32_to_cpu(pins->val) & pdata->mask; - switch (pdata->width) { - case 16: - writew((readw(reg) & ~pdata->mask) | val, reg); - break; - case 32: - writel((readl(reg) & ~pdata->mask) | val, reg); - break; - default: - dev_warn(dev, "unsupported register width %i\n", - pdata->width); - continue; - } + single_write(dev, (single_read(dev, reg) & ~pdata->mask) | val, + reg); dev_dbg(dev, " reg/val %pa/0x%08x\n", ®, val); + } return 0; } @@ -131,19 +154,7 @@ static int single_configure_bits(struct udevice *dev, mask = fdt32_to_cpu(pins->mask); val = fdt32_to_cpu(pins->val) & mask; - - switch (pdata->width) { - case 16: - writew((readw(reg) & ~mask) | val, reg); - break; - case 32: - writel((readl(reg) & ~mask) | val, reg); - break; - default: - dev_warn(dev, "unsupported register width %i\n", - pdata->width); - continue; - } + single_write(dev, (single_read(dev, reg) & ~mask) | val, reg); dev_dbg(dev, " reg/val %pa/0x%08x\n", ®, val); } return 0; @@ -196,6 +207,16 @@ static int single_of_to_plat(struct udevice *dev) return ret; } + switch (pdata->width) { + case 8: + case 16: + case 32: + break; + default: + dev_err(dev, "wrong register width\n"); + return -EINVAL; + } + addr = dev_read_addr_size(dev, "reg", &size); if (addr == FDT_ADDR_T_NONE) { dev_err(dev, "failed to get base register size\n"); From patchwork Sun Feb 28 14:12:38 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dario Binacchi X-Patchwork-Id: 1445259 X-Patchwork-Delegate: lokeshvutla@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; 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Signed-off-by: Dario Binacchi Reviewed-by: Simon Glass --- (no changes since v2) Changes in v2: - Added Simon Glass review tag. drivers/pinctrl/pinctrl-single.c | 37 ++++++++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/drivers/pinctrl/pinctrl-single.c b/drivers/pinctrl/pinctrl-single.c index 5b3ccc2281..e99eb552f5 100644 --- a/drivers/pinctrl/pinctrl-single.c +++ b/drivers/pinctrl/pinctrl-single.c @@ -26,6 +26,16 @@ struct single_pdata { bool bits_per_mux; }; +/** + * struct single_priv - private data + * @bits_per_pin: number of bits per pin + * @npins: number of selectable pins + */ +struct single_priv { + unsigned int bits_per_pin; + unsigned int npins; +}; + /** * struct single_fdt_pin_cfg - pin configuration * @@ -194,6 +204,30 @@ static int single_set_state(struct udevice *dev, return len; } +static int single_get_pins_count(struct udevice *dev) +{ + struct single_priv *priv = dev_get_priv(dev); + + return priv->npins; +} + +static int single_probe(struct udevice *dev) +{ + struct single_pdata *pdata = dev_get_plat(dev); + struct single_priv *priv = dev_get_priv(dev); + u32 size; + + size = pdata->offset + pdata->width / BITS_PER_BYTE; + priv->npins = size / (pdata->width / BITS_PER_BYTE); + if (pdata->bits_per_mux) { + priv->bits_per_pin = fls(pdata->mask); + priv->npins *= (pdata->width / priv->bits_per_pin); + } + + dev_dbg(dev, "%d pins\n", priv->npins); + return 0; +} + static int single_of_to_plat(struct udevice *dev) { fdt_addr_t addr; @@ -244,6 +278,7 @@ static int single_of_to_plat(struct udevice *dev) } const struct pinctrl_ops single_pinctrl_ops = { + .get_pins_count = single_get_pins_count, .set_state = single_set_state, }; @@ -258,5 +293,7 @@ U_BOOT_DRIVER(single_pinctrl) = { .of_match = single_pinctrl_match, .ops = &single_pinctrl_ops, .plat_auto = sizeof(struct single_pdata), + .priv_auto = sizeof(struct single_priv), .of_to_plat = single_of_to_plat, + .probe = single_probe, }; From patchwork Sun Feb 28 14:12:39 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dario Binacchi X-Patchwork-Id: 1445257 X-Patchwork-Delegate: lokeshvutla@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; 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Signed-off-by: Dario Binacchi Reviewed-by: Simon Glass --- (no changes since v2) Changes in v2: - Added Simon Glass review tag. drivers/pinctrl/pinctrl-single.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/drivers/pinctrl/pinctrl-single.c b/drivers/pinctrl/pinctrl-single.c index e99eb552f5..cdb5040852 100644 --- a/drivers/pinctrl/pinctrl-single.c +++ b/drivers/pinctrl/pinctrl-single.c @@ -30,10 +30,12 @@ struct single_pdata { * struct single_priv - private data * @bits_per_pin: number of bits per pin * @npins: number of selectable pins + * @pin_name: temporary buffer to store the pin name */ struct single_priv { unsigned int bits_per_pin; unsigned int npins; + char pin_name[PINNAME_SIZE]; }; /** @@ -204,6 +206,19 @@ static int single_set_state(struct udevice *dev, return len; } +static const char *single_get_pin_name(struct udevice *dev, + unsigned int selector) +{ + struct single_priv *priv = dev_get_priv(dev); + + if (selector >= priv->npins) + snprintf(priv->pin_name, PINNAME_SIZE, "Error"); + else + snprintf(priv->pin_name, PINNAME_SIZE, "PIN%u", selector); + + return priv->pin_name; +} + static int single_get_pins_count(struct udevice *dev) { struct single_priv *priv = dev_get_priv(dev); @@ -279,6 +294,7 @@ static int single_of_to_plat(struct udevice *dev) const struct pinctrl_ops single_pinctrl_ops = { .get_pins_count = single_get_pins_count, + .get_pin_name = single_get_pin_name, .set_state = single_set_state, }; From patchwork Sun Feb 28 14:12:40 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dario Binacchi X-Patchwork-Id: 1445261 X-Patchwork-Delegate: lokeshvutla@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; 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a=rsa-sha256; c=relaxed/relaxed; d=libero.it; s=s2021; t=1614521584; bh=jBrvYS+nEVgjcO40g5EBZzpwWXpkCtujkPVTIivyFrQ=; h=From; b=PJ1L9bcdiyp0rSOc2G7tqEwBR48b1UbspHTZiGKrAQxw5hKfBC9wIbVYftkF5enVt dlTxBBI+um4xKtSNRLQ4P19AXFkEV0Vur7KEnubzoZEUK8o+rhMSfTbU/ha+VczzyV 3pmI6tgVC6Sx6iWaTS63jc65kY79JUAzmQBkUvgNmQHR7QtgIMCrrQCUcWD707x22J AwvAPUdU39L+KIPBqFqgjHVdeEGuB0hTvH/8V2zMyM7zH+V9Rq8uYaqft+IXkmaVqe XmhfuD+9GAbSvwfR7BMaUv/8xSCuvh2OyOyWZLLYiglZnw58MMnOB0vzNeLSqlZlAT 4R0FOLI0z4iTg== X-CNFS-Analysis: v=2.4 cv=S6McfKgP c=1 sm=1 tr=0 ts=603ba4f0 cx=a_exe a=AVqmXbCQpuNSdJmApS5GbQ==:117 a=AVqmXbCQpuNSdJmApS5GbQ==:17 a=cm27Pg_UAAAA:8 a=d069haIMVjMWh2nAXtgA:9 a=gJQk6zD7_MtXv87T:21 a=61HPYePdjOItKzTt:21 a=xmb-EsYY8bH0VWELuYED:22 From: Dario Binacchi To: u-boot@lists.denx.de Cc: Lokesh Vutla , Dario Binacchi , Andy Shevchenko , Patrick Delaunay , Pratyush Yadav , Simon Glass Subject: [PATCH v3 11/12] pinctrl: single: add get_pin_muxing operation Date: Sun, 28 Feb 2021 15:12:40 +0100 Message-Id: <20210228141241.15931-12-dariobin@libero.it> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210228141241.15931-1-dariobin@libero.it> References: <20210228141241.15931-1-dariobin@libero.it> X-CMAE-Envelope: MS4xfLwq49I5MZ9WZdfwpTuNuOmpnIGOCHAEekSn6LKfqLx7uuil+VaogdLZUeE5WKledhJrIdhDb64FbpwCZHpa8Ddp+FQyHhbNxBxH+xBTdtLaY88qNgsC GWRwjRfrlL4qkYeX+x2d93DJuCo0uNYTxqsyCdNqJiJiZDmdTb4vGP0S9zT/uLb58mgMiIjlwm1EBeR8ezk1n6TGt5x8W53Ru7n9VpgvVlavJwVvOFY6iTbf 9dGdaNuEkao25YCIhiBwyvbehkpOLMslnB6KP3rDri9jdW3EWvtRDOYn/AGhhz7xPe3u7bGWmFJ/VE90jH31cdcQVuXbUjyuks7PlwkbgHhLE6G1RQovLxqy LboGSIuX4ywtsNNjJLD4E0LzVWJLKpBKpZuOL49ZQBdFeiO6qY7g6UCxJZINpLu1vepGrWCyXRdJ6IcAptmiKN1evNewiQ== X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.4 at phobos.denx.de X-Virus-Status: Clean It allows to display the muxing of a given pin. Inspired by more recent versions of the Linux driver, in addition to the address and the value of the configuration register I added the pin function retrieved from the DT. In doing so, the information displayed does not depend on the platform, being a generic type driver, and it can be useful for debug purposes. Signed-off-by: Dario Binacchi Reviewed-by: Simon Glass --- Changes in v3: - Added Simon Glass review tag. drivers/pinctrl/pinctrl-single.c | 222 +++++++++++++++++++++++++++++-- 1 file changed, 213 insertions(+), 9 deletions(-) diff --git a/drivers/pinctrl/pinctrl-single.c b/drivers/pinctrl/pinctrl-single.c index cdb5040852..3ddb637ab7 100644 --- a/drivers/pinctrl/pinctrl-single.c +++ b/drivers/pinctrl/pinctrl-single.c @@ -1,14 +1,18 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) EETS GmbH, 2017, Felix Brack + * Copyright (C) 2021 Dario Binacchi */ #include #include #include +#include #include #include +#include #include +#include /** * struct single_pdata - platform data @@ -26,6 +30,20 @@ struct single_pdata { bool bits_per_mux; }; +/** + * struct single_func - pinctrl function + * @node: list node + * @name: pinctrl function name + * @npins: number of entries in pins array + * @pins: pins array + */ +struct single_func { + struct list_head node; + const char *name; + unsigned int npins; + unsigned int *pins; +}; + /** * struct single_priv - private data * @bits_per_pin: number of bits per pin @@ -36,6 +54,7 @@ struct single_priv { unsigned int bits_per_pin; unsigned int npins; char pin_name[PINNAME_SIZE]; + struct list_head functions; }; /** @@ -100,6 +119,121 @@ static void single_write(struct udevice *dev, unsigned int val, fdt_addr_t reg) } } +/** + * single_get_pin_by_offset() - get a pin based on the register offset + * @dev: single driver instance + * @offset: register offset from the base + */ +static int single_get_pin_by_offset(struct udevice *dev, unsigned int offset) +{ + struct single_pdata *pdata = dev_get_plat(dev); + struct single_priv *priv = dev_get_priv(dev); + + if (offset > pdata->offset) { + dev_err(dev, "mux offset out of range: 0x%x (0x%x)\n", + offset, pdata->offset); + return -EINVAL; + } + + if (pdata->bits_per_mux) + return (offset * BITS_PER_BYTE) / priv->bits_per_pin; + + return offset / (pdata->width / BITS_PER_BYTE); +} + +static int single_get_offset_by_pin(struct udevice *dev, unsigned int pin) +{ + struct single_pdata *pdata = dev_get_plat(dev); + struct single_priv *priv = dev_get_priv(dev); + unsigned int mux_bytes; + + if (pin >= priv->npins) + return -EINVAL; + + mux_bytes = pdata->width / BITS_PER_BYTE; + if (pdata->bits_per_mux) { + int byte_num; + + byte_num = (priv->bits_per_pin * pin) / BITS_PER_BYTE; + return (byte_num / mux_bytes) * mux_bytes; + } + + return pin * mux_bytes; +} + +static const char *single_get_pin_function(struct udevice *dev, + unsigned int pin) +{ + struct single_priv *priv = dev_get_priv(dev); + struct single_func *func; + int i; + + list_for_each_entry(func, &priv->functions, node) { + for (i = 0; i < func->npins; i++) { + if (pin == func->pins[i]) + return func->name; + + if (pin < func->pins[i]) + break; + } + } + + return NULL; +} + +static int single_get_pin_muxing(struct udevice *dev, unsigned int pin, + char *buf, int size) +{ + struct single_pdata *pdata = dev_get_plat(dev); + struct single_priv *priv = dev_get_priv(dev); + fdt_addr_t reg; + const char *fname; + unsigned int val; + int offset, pin_shift = 0; + + offset = single_get_offset_by_pin(dev, pin); + if (offset < 0) + return offset; + + reg = pdata->base + offset; + val = single_read(dev, reg); + + if (pdata->bits_per_mux) + pin_shift = pin % (pdata->width / priv->bits_per_pin) * + priv->bits_per_pin; + + val &= (pdata->mask << pin_shift); + fname = single_get_pin_function(dev, pin); + snprintf(buf, size, "%pa 0x%08x %s", ®, val, + fname ? fname : "UNCLAIMED"); + return 0; +} + +static struct single_func *single_allocate_function(struct udevice *dev, + unsigned int group_pins) +{ + struct single_func *func; + + func = devm_kmalloc(dev, sizeof(*func), GFP_KERNEL); + if (!func) + return ERR_PTR(-ENOMEM); + + func->pins = devm_kmalloc(dev, sizeof(unsigned int) * group_pins, + GFP_KERNEL); + if (!func->pins) + return ERR_PTR(-ENOMEM); + + return func; +} + +static int single_pin_compare(const void *s1, const void *s2) +{ + int pin1 = *(const unsigned int *)s1; + int pin2 = *(const unsigned int *)s2; + + return pin1 - pin2; +} + /** * single_configure_pins() - Configure pins based on FDT data * @@ -113,13 +247,16 @@ static void single_write(struct udevice *dev, unsigned int val, fdt_addr_t reg) * @size: Size of the 'pins' array in bytes. * The number of register/value pairs in the 'pins' array therefore * equals to 'size / sizeof(struct single_fdt_pin_cfg)'. + * @fname: Function name. */ static int single_configure_pins(struct udevice *dev, const struct single_fdt_pin_cfg *pins, - int size) + int size, const char *fname) { struct single_pdata *pdata = dev_get_plat(dev); - int n, count = size / sizeof(struct single_fdt_pin_cfg); + struct single_priv *priv = dev_get_priv(dev); + int n, pin, count = size / sizeof(struct single_fdt_pin_cfg); + struct single_func *func; phys_addr_t reg; u32 offset, val; @@ -127,33 +264,61 @@ static int single_configure_pins(struct udevice *dev, if (!pdata->mask) return 0; + func = single_allocate_function(dev, count); + if (IS_ERR(func)) + return PTR_ERR(func); + + func->name = fname; + func->npins = 0; for (n = 0; n < count; n++, pins++) { offset = fdt32_to_cpu(pins->reg); if (offset < 0 || offset > pdata->offset) { - dev_dbg(dev, " invalid register offset 0x%x\n", + dev_err(dev, " invalid register offset 0x%x\n", offset); continue; } reg = pdata->base + offset; val = fdt32_to_cpu(pins->val) & pdata->mask; + pin = single_get_pin_by_offset(dev, offset); + if (pin < 0) { + dev_err(dev, " failed to get pin by offset %x\n", + offset); + continue; + } + single_write(dev, (single_read(dev, reg) & ~pdata->mask) | val, reg); dev_dbg(dev, " reg/val %pa/0x%08x\n", ®, val); - + func->pins[func->npins] = pin; + func->npins++; } + + qsort(func->pins, func->npins, sizeof(func->pins[0]), + single_pin_compare); + list_add(&func->node, &priv->functions); return 0; } static int single_configure_bits(struct udevice *dev, const struct single_fdt_bits_cfg *pins, - int size) + int size, const char *fname) { struct single_pdata *pdata = dev_get_plat(dev); - int n, count = size / sizeof(struct single_fdt_bits_cfg); + struct single_priv *priv = dev_get_priv(dev); + int n, pin, count = size / sizeof(struct single_fdt_bits_cfg); + int npins_in_reg, pin_num_from_lsb; + struct single_func *func; phys_addr_t reg; - u32 offset, val, mask; + u32 offset, val, mask, bit_pos, val_pos, mask_pos, submask; + + npins_in_reg = pdata->width / priv->bits_per_pin; + func = single_allocate_function(dev, count * npins_in_reg); + if (IS_ERR(func)) + return PTR_ERR(func); + func->name = fname; + func->npins = 0; for (n = 0; n < count; n++, pins++) { offset = fdt32_to_cpu(pins->reg); if (offset < 0 || offset > pdata->offset) { @@ -164,11 +329,47 @@ static int single_configure_bits(struct udevice *dev, reg = pdata->base + offset; + pin = single_get_pin_by_offset(dev, offset); + if (pin < 0) { + dev_err(dev, " failed to get pin by offset 0x%pa\n", + ®); + continue; + } + mask = fdt32_to_cpu(pins->mask); val = fdt32_to_cpu(pins->val) & mask; single_write(dev, (single_read(dev, reg) & ~mask) | val, reg); dev_dbg(dev, " reg/val %pa/0x%08x\n", ®, val); + + while (mask) { + bit_pos = __ffs(mask); + pin_num_from_lsb = bit_pos / priv->bits_per_pin; + mask_pos = pdata->mask << bit_pos; + val_pos = val & mask_pos; + submask = mask & mask_pos; + + if ((mask & mask_pos) == 0) { + dev_err(dev, "Invalid mask at 0x%x\n", offset); + break; + } + + mask &= ~mask_pos; + + if (submask != mask_pos) { + dev_warn(dev, + "Invalid submask 0x%x at 0x%x\n", + submask, offset); + continue; + } + + func->pins[func->npins] = pin + pin_num_from_lsb; + func->npins++; + } } + + qsort(func->pins, func->npins, sizeof(func->pins[0]), + single_pin_compare); + list_add(&func->node, &priv->functions); return 0; } static int single_set_state(struct udevice *dev, @@ -186,7 +387,7 @@ static int single_set_state(struct udevice *dev, dev_dbg(dev, " invalid pin configuration in fdt\n"); return -FDT_ERR_BADSTRUCTURE; } - single_configure_pins(dev, prop, len); + single_configure_pins(dev, prop, len, config->name); return 0; } @@ -198,7 +399,7 @@ static int single_set_state(struct udevice *dev, dev_dbg(dev, " invalid bits configuration in fdt\n"); return -FDT_ERR_BADSTRUCTURE; } - single_configure_bits(dev, prop_bits, len); + single_configure_bits(dev, prop_bits, len, config->name); return 0; } @@ -232,6 +433,8 @@ static int single_probe(struct udevice *dev) struct single_priv *priv = dev_get_priv(dev); u32 size; + INIT_LIST_HEAD(&priv->functions); + size = pdata->offset + pdata->width / BITS_PER_BYTE; priv->npins = size / (pdata->width / BITS_PER_BYTE); if (pdata->bits_per_mux) { @@ -296,6 +499,7 @@ const struct pinctrl_ops single_pinctrl_ops = { .get_pins_count = single_get_pins_count, .get_pin_name = single_get_pin_name, .set_state = single_set_state, + .get_pin_muxing = single_get_pin_muxing, }; static const struct udevice_id single_pinctrl_match[] = { From patchwork Sun Feb 28 14:12:41 2021 Content-Type: text/plain; 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Sun, 28 Feb 2021 15:13:05 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=quarantine dis=none) header.from=libero.it Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=dariobin@libero.it Received: from passgat-Modern-14-A10M.homenet.telecomitalia.it ([87.20.116.197]) by smtp-17.iol.local with ESMTPA id GMoXljE45lChfGMoilwAGb; Sun, 28 Feb 2021 15:13:04 +0100 x-libjamoibt: 1601 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=libero.it; s=s2021; t=1614521585; bh=JX+XmfYm1Gx9BpzDOEzXuZZqccgOxu/AnE3gj7QDP+w=; h=From; b=H5hAf6KIA1rL4jVMQnJdgvp0tBMsb0yDZ5VA/lbvhVw3yKpEzSk5KaQ5gYKFYLPCy /DFaJ+DM+DSxV7aqKryIM76PBb5Gw6mqqWR+fYwdLbTO50sVUtrghMREMyspm0/HiG Rdwex6JV5FE7Lso8HeC875bN0gyJ2to9w3s8n8EyhLv62j1gWUCyILSfugitGukhhk ij/cNgJrk1xDnUwmimczrqYomTWL9I4Cqh17Z0ZAH6PATOVra5L36tICMHUXFlI9cp /3kq7T48AmGV9vYIJpW/DfCcp1M11l5agJTfYrQy5jHU2oKLx3htwbhrIirGyKe88q WI74EeoK5Mhpg== X-CNFS-Analysis: v=2.4 cv=S6McfKgP c=1 sm=1 tr=0 ts=603ba4f1 cx=a_exe a=AVqmXbCQpuNSdJmApS5GbQ==:117 a=AVqmXbCQpuNSdJmApS5GbQ==:17 a=cm27Pg_UAAAA:8 a=eFUcvzSUtRLMO_gTjDcA:9 a=xmb-EsYY8bH0VWELuYED:22 From: Dario Binacchi To: u-boot@lists.denx.de Cc: Lokesh Vutla , Dario Binacchi , Andy Shevchenko , Bin Meng , Etienne Carriere , Jean-Jacques Hiblot , Patrick Delaunay , Philippe Reynes , Pratyush Yadav , Sean Anderson , Simon Glass , Wolfgang Wallner Subject: [PATCH v3 12/12] test: pinmux: add test for 'pinctrl-single' driver Date: Sun, 28 Feb 2021 15:12:41 +0100 Message-Id: <20210228141241.15931-13-dariobin@libero.it> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210228141241.15931-1-dariobin@libero.it> References: <20210228141241.15931-1-dariobin@libero.it> X-CMAE-Envelope: MS4xfL2ZHTxDVIzLQBoRCyNb8vwu56BKVJ+m3jq/GV5H+Yts9nhDVhQ4ZbFuEi0OhsOHo58gul4p07GxeXfXuDTZAEO6/pzrSPJH8ZGY2nbs/6wl5RZ1q6eT qnMjXLRyC5jwL9Tk2Su+SZ8Z/YQrNUSyjsRoZq37KuepmytVjHdTH3QiT9n3QZEmaLF6jv9zSaNN/W9kdiXD5WgYh9b4qLSLT4cy5hG6KNq0Ct1M5WH4H+nz 1By7ZVHZA+THt4EUcuKIuTieik2eWUvdJaYWw8SDM51Z4iG18CZ/FBpmoCzhnEAVAOP257Th1W+Gckqu7u1kJJ4p7HGuR7E3JKX9qFg/y8/dc9FUmDdF90+Y F/o9lMzkhEEJ3CdN61pM+eduQYgKGZ8hxUzqPYdLLtVe27LFBuGl2UoPWBu9WXnlqS/PXnvgNrQeMHBOzf7QcGzUeF5P7PA6aITCCXZu9QUWsmoaIIQy4dwR CGzkiYpaOi0eeLCboEVRH1UwcX6KVDvvaC2qwSocxc/QLAcBbuZzdEaDuTpKInLyaymAoaM1BzXMZT6Fb5jEBdPQJPNk0PqJB8NasirAgwZakBdk0CYXz66o DW5mDY6nT4k3PmMjsH/fwhNUUT/vFGuVfUo1cp9r24tR5yUD2T02t9u2Ln5c6W+OsPQ= X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.4 at phobos.denx.de X-Virus-Status: Clean The test adds two pinmux nodes to the device tree, one to test when a register changes only one pin's mux (pinctrl-single,pins), and the other to test when more than one pin's mux is changed (pinctrl-single,bits). This required replacing the controller's register access functions when the driver is used on sandbox. Signed-off-by: Dario Binacchi Reviewed-by: Simon Glass --- (no changes since v2) Changes in v2: - Added Simon Glass review tag. - Added error checking when the 'width' property is missing. - Fix coding style. arch/sandbox/dts/test.dts | 72 +++++++++++++++++++++++++ configs/sandbox_defconfig | 1 + drivers/pinctrl/pinctrl-single.c | 31 +++++++++++ test/dm/pinmux.c | 91 ++++++++++++++++++++++++++++++-- 4 files changed, 190 insertions(+), 5 deletions(-) diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts index 2600360224..b09342ed2c 100644 --- a/arch/sandbox/dts/test.dts +++ b/arch/sandbox/dts/test.dts @@ -569,6 +569,9 @@ reg = <0 1>; compatible = "sandbox,i2c"; clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinmux_i2c0_pins>; + eeprom@2c { reg = <0x2c>; compatible = "i2c-eeprom"; @@ -649,6 +652,8 @@ lcd { u-boot,dm-pre-reloc; compatible = "sandbox,lcd-sdl"; + pinctrl-names = "default"; + pinctrl-0 = <&pinmux_lcd_pins>; xres = <1366>; yres = <768>; }; @@ -899,6 +904,8 @@ pwm: pwm { compatible = "sandbox,pwm"; #pwm-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinmux_pwm_pins>; }; pwm2 { @@ -970,6 +977,9 @@ reg = <0 1>; compatible = "sandbox,spi"; cs-gpios = <0>, <0>, <&gpio_a 0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinmux_spi0_pins>; + spi.bin@0 { reg = <0>; compatible = "spansion,m25p16", "jedec,spi-nor"; @@ -1059,6 +1069,8 @@ uart0: serial { compatible = "sandbox,serial"; u-boot,dm-pre-reloc; + pinctrl-names = "default"; + pinctrl-0 = <&pinmux_uart0_pins>; }; usb_0: usb@0 { @@ -1325,6 +1337,66 @@ }; }; + pinctrl-single-no-width { + compatible = "pinctrl-single"; + reg = <0x0000 0x238>; + #pinctrl-cells = <1>; + pinctrl-single,function-mask = <0x7f>; + }; + + pinctrl-single-pins { + compatible = "pinctrl-single"; + reg = <0x0000 0x238>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0x7f>; + + pinmux_pwm_pins: pinmux_pwm_pins { + pinctrl-single,pins = < 0x48 0x06 >; + }; + + pinmux_spi0_pins: pinmux_spi0_pins { + pinctrl-single,pins = < + 0x190 0x0c + 0x194 0x0c + 0x198 0x23 + 0x19c 0x0c + >; + }; + + pinmux_uart0_pins: pinmux_uart0_pins { + pinctrl-single,pins = < + 0x70 0x30 + 0x74 0x00 + >; + }; + }; + + pinctrl-single-bits { + compatible = "pinctrl-single"; + reg = <0x0000 0x50>; + #pinctrl-cells = <2>; + pinctrl-single,bit-per-mux; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0xf>; + + pinmux_i2c0_pins: pinmux_i2c0_pins { + pinctrl-single,bits = < + 0x10 0x00002200 0x0000ff00 + >; + }; + + pinmux_lcd_pins: pinmux_lcd_pins { + pinctrl-single,bits = < + 0x40 0x22222200 0xffffff00 + 0x44 0x22222222 0xffffffff + 0x48 0x00000022 0x000000ff + 0x48 0x02000000 0x0f000000 + 0x4c 0x02000022 0x0f0000ff + >; + }; + }; + hwspinlock@0 { compatible = "sandbox,hwspinlock"; }; diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig index 5bc90d09a8..3a09f37804 100644 --- a/configs/sandbox_defconfig +++ b/configs/sandbox_defconfig @@ -197,6 +197,7 @@ CONFIG_PHY_SANDBOX=y CONFIG_PINCTRL=y CONFIG_PINCONF=y CONFIG_PINCTRL_SANDBOX=y +CONFIG_PINCTRL_SINGLE=y CONFIG_POWER_DOMAIN=y CONFIG_SANDBOX_POWER_DOMAIN=y CONFIG_DM_PMIC=y diff --git a/drivers/pinctrl/pinctrl-single.c b/drivers/pinctrl/pinctrl-single.c index 3ddb637ab7..48bdd0f6f5 100644 --- a/drivers/pinctrl/pinctrl-single.c +++ b/drivers/pinctrl/pinctrl-single.c @@ -51,6 +51,9 @@ struct single_func { * @pin_name: temporary buffer to store the pin name */ struct single_priv { +#if (IS_ENABLED(CONFIG_SANDBOX)) + u32 *sandbox_regs; +#endif unsigned int bits_per_pin; unsigned int npins; char pin_name[PINNAME_SIZE]; @@ -87,6 +90,8 @@ struct single_fdt_bits_cfg { fdt32_t mask; }; +#if (!IS_ENABLED(CONFIG_SANDBOX)) + static unsigned int single_read(struct udevice *dev, fdt_addr_t reg) { struct single_pdata *pdata = dev_get_plat(dev); @@ -119,6 +124,24 @@ static void single_write(struct udevice *dev, unsigned int val, fdt_addr_t reg) } } +#else /* CONFIG_SANDBOX */ + +static unsigned int single_read(struct udevice *dev, fdt_addr_t reg) +{ + struct single_priv *priv = dev_get_priv(dev); + + return priv->sandbox_regs[reg]; +} + +static void single_write(struct udevice *dev, unsigned int val, fdt_addr_t reg) +{ + struct single_priv *priv = dev_get_priv(dev); + + priv->sandbox_regs[reg] = val; +} + +#endif /* CONFIG_SANDBOX */ + /** * single_get_pin_by_offset() - get a pin based on the register offset * @dev: single driver instance @@ -436,6 +459,14 @@ static int single_probe(struct udevice *dev) INIT_LIST_HEAD(&priv->functions); size = pdata->offset + pdata->width / BITS_PER_BYTE; + #if (CONFIG_IS_ENABLED(SANDBOX)) + priv->sandbox_regs = + devm_kzalloc(dev, size * sizeof(*priv->sandbox_regs), + GFP_KERNEL); + if (!priv->sandbox_regs) + return -ENOMEM; + #endif + priv->npins = size / (pdata->width / BITS_PER_BYTE); if (pdata->bits_per_mux) { priv->bits_per_pin = fls(pdata->mask); diff --git a/test/dm/pinmux.c b/test/dm/pinmux.c index 047184d4bc..265df4ccb9 100644 --- a/test/dm/pinmux.c +++ b/test/dm/pinmux.c @@ -9,16 +9,21 @@ #include #include -static int dm_test_pinmux(struct unit_test_state *uts) -{ - char buf[64]; - struct udevice *dev; - +static char buf[64]; #define test_muxing(selector, expected) do { \ ut_assertok(pinctrl_get_pin_muxing(dev, selector, buf, sizeof(buf))); \ ut_asserteq_str(expected, (char *)&buf); \ } while (0) +#define test_name(selector, expected) do { \ + ut_assertok(pinctrl_get_pin_name(dev, selector, buf, sizeof(buf))); \ + ut_asserteq_str(expected, (char *)&buf); \ +} while (0) + +static int dm_test_pinmux(struct unit_test_state *uts) +{ + struct udevice *dev; + ut_assertok(uclass_get_device_by_name(UCLASS_PINCTRL, "pinctrl", &dev)); test_muxing(0, "UART TX."); test_muxing(1, "UART RX."); @@ -54,4 +59,80 @@ static int dm_test_pinmux(struct unit_test_state *uts) return 0; } + DM_TEST(dm_test_pinmux, UT_TESTF_SCAN_FDT); + +static int dm_test_pinctrl_single(struct unit_test_state *uts) +{ + struct udevice *dev; + int ret; + + ret = uclass_get_device_by_name(UCLASS_PINCTRL, + "pinctrl-single-no-width", &dev); + ut_asserteq(-EINVAL, ret); + ut_assertok(uclass_get_device_by_name(UCLASS_PWM, "pwm", &dev)); + ut_assertok(uclass_get_device_by_name(UCLASS_SERIAL, "serial", &dev)); + ut_assertok(uclass_get_device_by_name(UCLASS_SPI, "spi@0", &dev)); + ut_assertok(uclass_get_device_by_name(UCLASS_PINCTRL, + "pinctrl-single-pins", &dev)); + ut_asserteq(142, pinctrl_get_pins_count(dev)); + test_name(0, "PIN0"); + test_name(141, "PIN141"); + test_name(142, "Error"); + test_muxing(0, "0x00000000 0x00000000 UNCLAIMED"); + test_muxing(18, "0x00000048 0x00000006 pinmux_pwm_pins"); + test_muxing(28, "0x00000070 0x00000030 pinmux_uart0_pins"); + test_muxing(29, "0x00000074 0x00000000 pinmux_uart0_pins"); + test_muxing(100, "0x00000190 0x0000000c pinmux_spi0_pins"); + test_muxing(101, "0x00000194 0x0000000c pinmux_spi0_pins"); + test_muxing(102, "0x00000198 0x00000023 pinmux_spi0_pins"); + test_muxing(103, "0x0000019c 0x0000000c pinmux_spi0_pins"); + ret = pinctrl_get_pin_muxing(dev, 142, buf, sizeof(buf)); + ut_asserteq(-EINVAL, ret); + ut_assertok(uclass_get_device_by_name(UCLASS_I2C, "i2c@0", &dev)); + ut_assertok(uclass_get_device_by_name(UCLASS_VIDEO, "lcd", &dev)); + ut_assertok(uclass_get_device_by_name(UCLASS_PINCTRL, + "pinctrl-single-bits", &dev)); + ut_asserteq(160, pinctrl_get_pins_count(dev)); + test_name(0, "PIN0"); + test_name(159, "PIN159"); + test_name(160, "Error"); + test_muxing(0, "0x00000000 0x00000000 UNCLAIMED"); + test_muxing(34, "0x00000010 0x00000200 pinmux_i2c0_pins"); + test_muxing(35, "0x00000010 0x00002000 pinmux_i2c0_pins"); + test_muxing(130, "0x00000040 0x00000200 pinmux_lcd_pins"); + test_muxing(131, "0x00000040 0x00002000 pinmux_lcd_pins"); + test_muxing(132, "0x00000040 0x00020000 pinmux_lcd_pins"); + test_muxing(133, "0x00000040 0x00200000 pinmux_lcd_pins"); + test_muxing(134, "0x00000040 0x02000000 pinmux_lcd_pins"); + test_muxing(135, "0x00000040 0x20000000 pinmux_lcd_pins"); + test_muxing(136, "0x00000044 0x00000002 pinmux_lcd_pins"); + test_muxing(137, "0x00000044 0x00000020 pinmux_lcd_pins"); + test_muxing(138, "0x00000044 0x00000200 pinmux_lcd_pins"); + test_muxing(139, "0x00000044 0x00002000 pinmux_lcd_pins"); + test_muxing(140, "0x00000044 0x00020000 pinmux_lcd_pins"); + test_muxing(141, "0x00000044 0x00200000 pinmux_lcd_pins"); + test_muxing(142, "0x00000044 0x02000000 pinmux_lcd_pins"); + test_muxing(143, "0x00000044 0x20000000 pinmux_lcd_pins"); + test_muxing(144, "0x00000048 0x00000002 pinmux_lcd_pins"); + test_muxing(145, "0x00000048 0x00000020 pinmux_lcd_pins"); + test_muxing(146, "0x00000048 0x00000000 UNCLAIMED"); + test_muxing(147, "0x00000048 0x00000000 UNCLAIMED"); + test_muxing(148, "0x00000048 0x00000000 UNCLAIMED"); + test_muxing(149, "0x00000048 0x00000000 UNCLAIMED"); + test_muxing(150, "0x00000048 0x02000000 pinmux_lcd_pins"); + test_muxing(151, "0x00000048 0x00000000 UNCLAIMED"); + test_muxing(152, "0x0000004c 0x00000002 pinmux_lcd_pins"); + test_muxing(153, "0x0000004c 0x00000020 pinmux_lcd_pins"); + test_muxing(154, "0x0000004c 0x00000000 UNCLAIMED"); + test_muxing(155, "0x0000004c 0x00000000 UNCLAIMED"); + test_muxing(156, "0x0000004c 0x00000000 UNCLAIMED"); + test_muxing(157, "0x0000004c 0x00000000 UNCLAIMED"); + test_muxing(158, "0x0000004c 0x02000000 pinmux_lcd_pins"); + test_muxing(159, "0x0000004c 0x00000000 UNCLAIMED"); + ret = pinctrl_get_pin_muxing(dev, 160, buf, sizeof(buf)); + ut_asserteq(-EINVAL, ret); + return 0; +} + +DM_TEST(dm_test_pinctrl_single, UT_TESTF_SCAN_FDT);