From patchwork Fri Jan 12 17:41:16 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Bodireddy, Bhanuprakash" X-Patchwork-Id: 860108 X-Patchwork-Delegate: ian.stokes@intel.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=openvswitch.org (client-ip=140.211.169.12; helo=mail.linuxfoundation.org; envelope-from=ovs-dev-bounces@openvswitch.org; receiver=) Received: from mail.linuxfoundation.org (mail.linuxfoundation.org [140.211.169.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3zJ9Lx1CRsz9sBd for ; Sat, 13 Jan 2018 04:52:41 +1100 (AEDT) Received: from mail.linux-foundation.org (localhost [127.0.0.1]) by mail.linuxfoundation.org (Postfix) with ESMTP id 552F3EA2; Fri, 12 Jan 2018 17:52:39 +0000 (UTC) X-Original-To: dev@openvswitch.org Delivered-To: ovs-dev@mail.linuxfoundation.org Received: from smtp1.linuxfoundation.org (smtp1.linux-foundation.org [172.17.192.35]) by mail.linuxfoundation.org (Postfix) with ESMTPS id DAF07E18 for ; Fri, 12 Jan 2018 17:52:38 +0000 (UTC) X-Greylist: domain auto-whitelisted by SQLgrey-1.7.6 Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by smtp1.linuxfoundation.org (Postfix) with ESMTPS id 3AC1918A for ; Fri, 12 Jan 2018 17:52:38 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga101.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 12 Jan 2018 09:52:37 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.46,350,1511856000"; d="scan'208";a="19631340" Received: from silpixa00393942.ir.intel.com (HELO silpixa00393942.ger.corp.intel.com) ([10.237.223.42]) by orsmga003.jf.intel.com with ESMTP; 12 Jan 2018 09:52:36 -0800 From: Bhanuprakash Bodireddy To: dev@openvswitch.org Date: Fri, 12 Jan 2018 17:41:16 +0000 Message-Id: <1515778879-60075-1-git-send-email-bhanuprakash.bodireddy@intel.com> X-Mailer: git-send-email 2.4.11 X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, T_RP_MATCHES_RCVD autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on smtp1.linux-foundation.org Subject: [ovs-dev] [PATCH 1/4] compiler: Introduce OVS_PREFETCH variants. X-BeenThere: ovs-dev@openvswitch.org X-Mailman-Version: 2.1.12 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: ovs-dev-bounces@openvswitch.org Errors-To: ovs-dev-bounces@openvswitch.org This commit introduces prefetch variants by using the GCC built-in prefetch function. The prefetch variants gives the user better control on designing data caching strategy in order to increase cache efficiency and minimize cache pollution. Data reference patterns here can be classified in to - Non-temporal(NT) - Data that is referenced once and not reused in immediate future. - Temporal - Data will be used again soon. The Macro variants can be used where there are - Predictable memory access patterns. - Execution pipeline can stall if data isn't available. - Time consuming loops. For example: OVS_PREFETCH_CACHE(addr, OPCH_LTR) - OPCH_LTR : OVS PREFETCH CACHE HINT-LOW TEMPORAL READ. - __builtin_prefetch(addr, 0, 1) - Prefetch data in to L3 cache for readonly purpose. OVS_PREFETCH_CACHE(addr, OPCH_HTW) - OPCH_HTW : OVS PREFETCH CACHE HINT-HIGH TEMPORAL WRITE. - __builtin_prefetch(addr, 1, 3) - Prefetch data in to all caches in anticipation of write. In doing so it invalidates other cached copies so as to gain 'exclusive' access. OVS_PREFETCH(addr) - OPCH_HTR : OVS PREFETCH CACHE HINT-HIGH TEMPORAL READ. - __builtin_prefetch(addr, 0, 3) - Prefetch data in to all caches in anticipation of read and that data will be used again soon (HTR - High Temporal Read). Signed-off-by: Bhanuprakash Bodireddy --- include/openvswitch/compiler.h | 147 ++++++++++++++++++++++++++++++++++++++--- 1 file changed, 139 insertions(+), 8 deletions(-) diff --git a/include/openvswitch/compiler.h b/include/openvswitch/compiler.h index c7cb930..94bb24d 100644 --- a/include/openvswitch/compiler.h +++ b/include/openvswitch/compiler.h @@ -222,18 +222,149 @@ static void f(void) #endif -/* OVS_PREFETCH() can be used to instruct the CPU to fetch the cache - * line containing the given address to a CPU cache. - * OVS_PREFETCH_WRITE() should be used when the memory is going to be - * written to. Depending on the target CPU, this can generate the same - * instruction as OVS_PREFETCH(), or bring the data into the cache in an - * exclusive state. */ #if __GNUC__ -#define OVS_PREFETCH(addr) __builtin_prefetch((addr)) -#define OVS_PREFETCH_WRITE(addr) __builtin_prefetch((addr), 1) +enum cache_locality { + NON_TEMPORAL_LOCALITY, + LOW_TEMPORAL_LOCALITY, + MODERATE_TEMPORAL_LOCALITY, + HIGH_TEMPORAL_LOCALITY +}; + +enum cache_rw { + PREFETCH_READ, + PREFETCH_WRITE +}; + +/* The prefetch variants gives the user better control on designing data + * caching strategy in order to increase cache efficiency and minimize + * cache pollution. Data reference patterns here can be classified in to + * + * Non-temporal(NT) - Data that is referenced once and not reused in + * immediate future. + * Temporal - Data will be used again soon. + * + * The Macro variants can be used where there are + * o Predictable memory access patterns. + * o Execution pipeline can stall if data isn't available. + * o Time consuming loops. + * + * OVS_PREFETCH_CACHE() can be used to instruct the CPU to fetch the cache + * line containing the given address to a CPU cache. The second argument + * OPCH_XXR (or) OPCH_XXW is used to hint if the prefetched data is going + * to be read or written to by core. + * + * Example Usage: + * + * OVS_PREFETCH_CACHE(addr, OPCH_LTR) + * - OPCH_LTR : OVS PREFETCH CACHE HINT-LOW TEMPORAL READ. + * - __builtin_prefetch(addr, 0, 1) + * - Prefetch data in to L3 cache for readonly purpose. + * + * OVS_PREFETCH_CACHE(addr, OPCH_HTW) + * - OPCH_HTW : OVS PREFETCH CACHE HINT-HIGH TEMPORAL WRITE. + * - __builtin_prefetch(addr, 1, 3) + * - Prefetch data in to all caches in anticipation of write. In doing + * so it invalidates other cached copies so as to gain 'exclusive' + * access. + * + * OVS_PREFETCH(addr) + * - OPCH_HTR : OVS PREFETCH CACHE HINT-HIGH TEMPORAL READ. + * - __builtin_prefetch(addr, 0, 3) + * - Prefetch data in to all caches in anticipation of read and that + * data will be used again soon (HTR - High Temporal Read). + * + * Implementation details of prefetch hint instructions may vary across + * different processors and microarchitectures. + * + * OPCH_NTW, OPCH_LTW, OPCH_MTW uses prefetchwt1 instruction and OPCH_HTW + * uses prefetchw instruction when available. Refer Documentation on how + * to enable prefetchwt1 instruction. + * + * PREFETCH HINT Instruction GCC builtin function + * ------------------------------------------------------- + * OPCH_NTR prefetchnta __builtin_prefetch(a, 0, 0) + * OPCH_LTR prefetcht2 __builtin_prefetch(a, 0, 1) + * OPCH_MTR prefetcht1 __builtin_prefetch(a, 0, 2) + * OPCH_HTR prefetcht0 __builtin_prefetch(a, 0, 3) + * + * OPCH_NTW prefetchwt1 __builtin_prefetch(a, 1, 0) + * OPCH_LTW prefetchwt1 __builtin_prefetch(a, 1, 1) + * OPCH_MTW prefetchwt1 __builtin_prefetch(a, 1, 2) + * OPCH_HTW prefetchw __builtin_prefetch(a, 1, 3) + * + * */ +#define OVS_PREFETCH_CACHE_HINT \ + OPCH(OPCH_NTR, PREFETCH_READ, NON_TEMPORAL_LOCALITY, \ + "Fetch data to non-temporal cache close to processor" \ + "to minimize cache pollution") \ + OPCH(OPCH_LTR, PREFETCH_READ, LOW_TEMPORAL_LOCALITY, \ + "Fetch data to L2 and L3 cache") \ + OPCH(OPCH_MTR, PREFETCH_READ, MODERATE_TEMPORAL_LOCALITY, \ + "Fetch data to L2 and L3 caches, same as LTR on" \ + "Nehalem, Westmere, Sandy Bridge and newer microarchitectures") \ + OPCH(OPCH_HTR, PREFETCH_READ, HIGH_TEMPORAL_LOCALITY, \ + "Fetch data in to all cache levels L1, L2 and L3") \ + OPCH(OPCH_NTW, PREFETCH_WRITE, NON_TEMPORAL_LOCALITY, \ + "Fetch data to L2 and L3 cache in exclusive state" \ + "in anticipation of write") \ + OPCH(OPCH_LTW, PREFETCH_WRITE, LOW_TEMPORAL_LOCALITY, \ + "Fetch data to L2 and L3 cache in exclusive state") \ + OPCH(OPCH_MTW, PREFETCH_WRITE, MODERATE_TEMPORAL_LOCALITY, \ + "Fetch data in to L2 and L3 caches in exclusive state") \ + OPCH(OPCH_HTW, PREFETCH_WRITE, HIGH_TEMPORAL_LOCALITY, \ + "Fetch data in to all cache levels in exclusive state") + +/* Indexes for cache prefetch types. */ +enum { +#define OPCH(ENUM, RW, LOCALITY, EXPLANATION) ENUM##_INDEX, + OVS_PREFETCH_CACHE_HINT +#undef OPCH +}; + +/* Cache prefetch types. */ +enum ovs_prefetch_type { +#define OPCH(ENUM, RW, LOCALITY, EXPLANATION) ENUM = 1 << ENUM##_INDEX, + OVS_PREFETCH_CACHE_HINT +#undef OPCH +}; + +#define OVS_PREFETCH_CACHE(addr, TYPE) switch(TYPE) \ +{ \ + case OPCH_NTR: \ + __builtin_prefetch((addr), PREFETCH_READ, NON_TEMPORAL_LOCALITY); \ + break; \ + case OPCH_LTR: \ + __builtin_prefetch((addr), PREFETCH_READ, LOW_TEMPORAL_LOCALITY); \ + break; \ + case OPCH_MTR: \ + __builtin_prefetch((addr), PREFETCH_READ, \ + MODERATE_TEMPORAL_LOCALITY); \ + break; \ + case OPCH_HTR: \ + __builtin_prefetch((addr), PREFETCH_READ, HIGH_TEMPORAL_LOCALITY); \ + break; \ + case OPCH_NTW: \ + __builtin_prefetch((addr), PREFETCH_WRITE, NON_TEMPORAL_LOCALITY); \ + break; \ + case OPCH_LTW: \ + __builtin_prefetch((addr), PREFETCH_WRITE, LOW_TEMPORAL_LOCALITY); \ + break; \ + case OPCH_MTW: \ + __builtin_prefetch((addr), PREFETCH_WRITE, \ + MODERATE_TEMPORAL_LOCALITY); \ + break; \ + case OPCH_HTW: \ + __builtin_prefetch((addr), PREFETCH_WRITE, HIGH_TEMPORAL_LOCALITY); \ + break; \ +} + +/* Retain this for backward compatibility. */ +#define OVS_PREFETCH(addr) OVS_PREFETCH_CACHE(addr, OPCH_HTR) +#define OVS_PREFETCH_WRITE(addr) OVS_PREFETCH_CACHE(addr, OPCH_HTW) #else #define OVS_PREFETCH(addr) #define OVS_PREFETCH_WRITE(addr) +#define OVS_PREFETCH_CACHE(addr, OP) #endif /* Build assertions. From patchwork Fri Jan 12 17:41:17 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Bodireddy, Bhanuprakash" X-Patchwork-Id: 860110 X-Patchwork-Delegate: ian.stokes@intel.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=openvswitch.org (client-ip=140.211.169.12; helo=mail.linuxfoundation.org; envelope-from=ovs-dev-bounces@openvswitch.org; receiver=) Received: from mail.linuxfoundation.org (mail.linuxfoundation.org [140.211.169.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3zJ9MX0PQ8z9sBd for ; Sat, 13 Jan 2018 04:53:12 +1100 (AEDT) Received: from mail.linux-foundation.org (localhost [127.0.0.1]) by mail.linuxfoundation.org (Postfix) with ESMTP id 431A2F6A; Fri, 12 Jan 2018 17:52:42 +0000 (UTC) X-Original-To: dev@openvswitch.org Delivered-To: ovs-dev@mail.linuxfoundation.org Received: from smtp1.linuxfoundation.org (smtp1.linux-foundation.org [172.17.192.35]) by mail.linuxfoundation.org (Postfix) with ESMTPS id 8F8ECF00 for ; Fri, 12 Jan 2018 17:52:39 +0000 (UTC) X-Greylist: domain auto-whitelisted by SQLgrey-1.7.6 Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by smtp1.linuxfoundation.org (Postfix) with ESMTPS id 3C12D18A for ; Fri, 12 Jan 2018 17:52:39 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga101.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 12 Jan 2018 09:52:38 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.46,350,1511856000"; d="scan'208";a="19631345" Received: from silpixa00393942.ir.intel.com (HELO silpixa00393942.ger.corp.intel.com) ([10.237.223.42]) by orsmga003.jf.intel.com with ESMTP; 12 Jan 2018 09:52:37 -0800 From: Bhanuprakash Bodireddy To: dev@openvswitch.org Date: Fri, 12 Jan 2018 17:41:17 +0000 Message-Id: <1515778879-60075-2-git-send-email-bhanuprakash.bodireddy@intel.com> X-Mailer: git-send-email 2.4.11 In-Reply-To: <1515778879-60075-1-git-send-email-bhanuprakash.bodireddy@intel.com> References: <1515778879-60075-1-git-send-email-bhanuprakash.bodireddy@intel.com> X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, T_RP_MATCHES_RCVD autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on smtp1.linux-foundation.org Subject: [ovs-dev] [PATCH 2/4] util: Extend ovs_prefetch_range to include prefetch type. X-BeenThere: ovs-dev@openvswitch.org X-Mailman-Version: 2.1.12 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: ovs-dev-bounces@openvswitch.org Errors-To: ovs-dev-bounces@openvswitch.org With ovs_prefetch_range(), large amounts of data can be prefetched in to caches. Prefetch type gives better control over data caching strategy; Meaning where the data should be prefetched(L1/L2/L3) and if the data reference is temporal or non-temporal. Signed-off-by: Bhanuprakash Bodireddy --- lib/pvector.h | 6 ++++-- lib/util.h | 4 ++-- 2 files changed, 6 insertions(+), 4 deletions(-) diff --git a/lib/pvector.h b/lib/pvector.h index b175b21..d5655f0 100644 --- a/lib/pvector.h +++ b/lib/pvector.h @@ -177,7 +177,8 @@ pvector_cursor_init(const struct pvector *pvec, impl = ovsrcu_get(struct pvector_impl *, &pvec->impl); - ovs_prefetch_range(impl->vector, impl->size * sizeof impl->vector[0]); + ovs_prefetch_range(impl->vector, impl->size * sizeof impl->vector[0], + OPCH_HTR); cursor.size = impl->size; cursor.vector = impl->vector; @@ -208,7 +209,8 @@ static inline void pvector_cursor_lookahead(const struct pvector_cursor *cursor, int n, size_t size) { if (cursor->entry_idx + n < cursor->size) { - ovs_prefetch_range(cursor->vector[cursor->entry_idx + n].ptr, size); + ovs_prefetch_range(cursor->vector[cursor->entry_idx + n].ptr, size, + OPCH_HTR); } } diff --git a/lib/util.h b/lib/util.h index b6639b8..0a8ae23 100644 --- a/lib/util.h +++ b/lib/util.h @@ -73,13 +73,13 @@ BUILD_ASSERT_DECL(IS_POW2(CACHE_LINE_SIZE)); typedef uint8_t OVS_CACHE_LINE_MARKER[1]; static inline void -ovs_prefetch_range(const void *start, size_t size) +ovs_prefetch_range(const void *start, size_t size, enum ovs_prefetch_type type) { const char *addr = (const char *)start; size_t ofs; for (ofs = 0; ofs < size; ofs += CACHE_LINE_SIZE) { - OVS_PREFETCH(addr + ofs); + OVS_PREFETCH_CACHE(addr + ofs, type); } } From patchwork Fri Jan 12 17:41:18 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Bodireddy, Bhanuprakash" X-Patchwork-Id: 860111 X-Patchwork-Delegate: ian.stokes@intel.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=openvswitch.org (client-ip=140.211.169.12; helo=mail.linuxfoundation.org; envelope-from=ovs-dev-bounces@openvswitch.org; receiver=) Received: from mail.linuxfoundation.org (mail.linuxfoundation.org [140.211.169.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3zJ9N44ckVz9sNc for ; Sat, 13 Jan 2018 04:53:40 +1100 (AEDT) Received: from mail.linux-foundation.org (localhost [127.0.0.1]) by mail.linuxfoundation.org (Postfix) with ESMTP id 3FDCCF85; Fri, 12 Jan 2018 17:52:43 +0000 (UTC) X-Original-To: dev@openvswitch.org Delivered-To: ovs-dev@mail.linuxfoundation.org Received: from smtp1.linuxfoundation.org (smtp1.linux-foundation.org [172.17.192.35]) by mail.linuxfoundation.org (Postfix) with ESMTPS id EE1A2F00 for ; Fri, 12 Jan 2018 17:52:39 +0000 (UTC) X-Greylist: domain auto-whitelisted by SQLgrey-1.7.6 Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by smtp1.linuxfoundation.org (Postfix) with ESMTPS id 9A2D718A for ; Fri, 12 Jan 2018 17:52:39 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga101.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 12 Jan 2018 09:52:39 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.46,350,1511856000"; d="scan'208";a="19631349" Received: from silpixa00393942.ir.intel.com (HELO silpixa00393942.ger.corp.intel.com) ([10.237.223.42]) by orsmga003.jf.intel.com with ESMTP; 12 Jan 2018 09:52:38 -0800 From: Bhanuprakash Bodireddy To: dev@openvswitch.org Date: Fri, 12 Jan 2018 17:41:18 +0000 Message-Id: <1515778879-60075-3-git-send-email-bhanuprakash.bodireddy@intel.com> X-Mailer: git-send-email 2.4.11 In-Reply-To: <1515778879-60075-1-git-send-email-bhanuprakash.bodireddy@intel.com> References: <1515778879-60075-1-git-send-email-bhanuprakash.bodireddy@intel.com> X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, T_RP_MATCHES_RCVD autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on smtp1.linux-foundation.org Subject: [ovs-dev] [PATCH 3/4] util: Use OPCH_NTR type while prefetching packet metadata. X-BeenThere: ovs-dev@openvswitch.org X-Mailman-Version: 2.1.12 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: ovs-dev-bounces@openvswitch.org Errors-To: ovs-dev-bounces@openvswitch.org OVS_PREFETCH by default uses OPCH_HTR(High Temporal Read), meaning the prefetch is in preparation for a future read and the prefetched data is made available in all levels of caches. However the pkt_metadata_prefetch_init() prefetches the metadata so that the data is readily available when pkt_metadata_init() zeroes out the same. So a 'write' operation is actually performed instead of anticipated 'read' on the prefetched data. Doing a 'write' isn't a problem as the metadata isn't shared between the threads and doesn't need invalidation across other cores and so read prefetch is enough with *non-temporal* reference so not to pollute the cache. This change seems to positively affect performance. Signed-off-by: Bhanuprakash Bodireddy --- lib/packets.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/lib/packets.h b/lib/packets.h index 9a71aa3..5f50fe2 100644 --- a/lib/packets.h +++ b/lib/packets.h @@ -166,14 +166,14 @@ pkt_metadata_prefetch_init(struct pkt_metadata *md) { /* Prefetch cacheline0 as members till ct_state and odp_port will * be initialized later in pkt_metadata_init(). */ - OVS_PREFETCH(md->cacheline0); + OVS_PREFETCH_CACHE(md->cacheline0, OPCH_NTR); /* Prefetch cacheline1 as members of this cacheline will be zeroed out * in pkt_metadata_init_tnl(). */ - OVS_PREFETCH(md->cacheline1); + OVS_PREFETCH_CACHE(md->cacheline1, OPCH_NTR); /* Prefetch cachline2 as ip_dst & ipv6_dst fields will be initialized. */ - OVS_PREFETCH(md->cacheline2); + OVS_PREFETCH_CACHE(md->cacheline2, OPCH_NTR); } bool dpid_from_string(const char *s, uint64_t *dpidp); From patchwork Fri Jan 12 17:41:19 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Bodireddy, Bhanuprakash" X-Patchwork-Id: 860112 X-Patchwork-Delegate: ian.stokes@intel.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=openvswitch.org (client-ip=140.211.169.12; helo=mail.linuxfoundation.org; envelope-from=ovs-dev-bounces@openvswitch.org; receiver=) Received: from mail.linuxfoundation.org (mail.linuxfoundation.org [140.211.169.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3zJ9Ng0h5Cz9sNV for ; Sat, 13 Jan 2018 04:54:11 +1100 (AEDT) Received: from mail.linux-foundation.org (localhost [127.0.0.1]) by mail.linuxfoundation.org (Postfix) with ESMTP id 34276F0D; Fri, 12 Jan 2018 17:52:44 +0000 (UTC) X-Original-To: dev@openvswitch.org Delivered-To: ovs-dev@mail.linuxfoundation.org Received: from smtp1.linuxfoundation.org (smtp1.linux-foundation.org [172.17.192.35]) by mail.linuxfoundation.org (Postfix) with ESMTPS id 19662ED4 for ; Fri, 12 Jan 2018 17:52:41 +0000 (UTC) X-Greylist: domain auto-whitelisted by SQLgrey-1.7.6 Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by smtp1.linuxfoundation.org (Postfix) with ESMTPS id 9919E44D for ; Fri, 12 Jan 2018 17:52:40 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga101.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 12 Jan 2018 09:52:40 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.46,350,1511856000"; d="scan'208";a="19631350" Received: from silpixa00393942.ir.intel.com (HELO silpixa00393942.ger.corp.intel.com) ([10.237.223.42]) by orsmga003.jf.intel.com with ESMTP; 12 Jan 2018 09:52:39 -0800 From: Bhanuprakash Bodireddy To: dev@openvswitch.org Date: Fri, 12 Jan 2018 17:41:19 +0000 Message-Id: <1515778879-60075-4-git-send-email-bhanuprakash.bodireddy@intel.com> X-Mailer: git-send-email 2.4.11 In-Reply-To: <1515778879-60075-1-git-send-email-bhanuprakash.bodireddy@intel.com> References: <1515778879-60075-1-git-send-email-bhanuprakash.bodireddy@intel.com> X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, T_RP_MATCHES_RCVD autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on smtp1.linux-foundation.org Subject: [ovs-dev] [PATCH 4/4] doc: Update configure section with prefetchwt1 details. X-BeenThere: ovs-dev@openvswitch.org X-Mailman-Version: 2.1.12 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: ovs-dev-bounces@openvswitch.org Errors-To: ovs-dev-bounces@openvswitch.org Inspite of specifying -march=native when using Low Temporal Write(OPCH_LTW), the compiler generates 'prefetchw' instruction instead of 'prefetchwt1' instruction available on processor as in 'Case B'. To make the compiler emit prefetchwt1 instruction, -mprefetchwt1 needs to be passed to configure explicitly. [Problem] Case A: OVS_PREFETCH_CACHE(addr, OPCH_HTW) [__builtin_prefetch(addr, 1, 3)] [Assembly] leaq -112(%rbp), %rax prefetchw (%rax) Case B: OVS_PREFETCH_CACHE(addr, OPCH_LTW) [__builtin_prefetch(addr, 1, 1)] [Assembly] leaq -112(%rbp), %rax prefetchw (%rax) <***problem***> [Solution] ./configure CFLAGS="-g -O2 -mprefetchwt1" Case B: OVS_PREFETCH_CACHE(addr, OPCH_LTW) [__builtin_prefetch(addr, 1, 1)] [Assembly] leaq -112(%rbp), %rax prefetchwt1 (%rax) See also: https://mail.openvswitch.org/pipermail/ovs-dev/2017-December/341591.html Signed-off-by: Bhanuprakash Bodireddy --- Documentation/intro/install/general.rst | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/Documentation/intro/install/general.rst b/Documentation/intro/install/general.rst index 718e5c2..4d2db45 100644 --- a/Documentation/intro/install/general.rst +++ b/Documentation/intro/install/general.rst @@ -280,6 +280,19 @@ With this, GCC will detect the processor and automatically set appropriate flags for it. This should not be used if you are compiling OVS outside the target machine. +Compilers(gcc) won't emit prefetchwt1 instruction even with '-march=native' +specified. In such case, -mprefetchwt1 needs to be explicitly passed during +configuration. + +For example inspite of specifying -march=native when using Low Temporal Write +i.e OVS_PREFETCH_CACHE(addr, OPCH_LTW), the compiler generates 'prefetchw' +instruction instead of 'prefetchwt1' instruction available on processor. + +To make the compiler generate the appropriate instruction, it is recommended +to pass ``-mprefetchwt1`` settings:: + + $ ./configure CFLAGS="-g -O2 -march=native -mprefetchwt1" + .. note:: CFLAGS are not applied when building the Linux kernel module. Custom CFLAGS for the kernel module are supplied using the ``EXTRA_CFLAGS`` variable when