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[44.242.66.180]) by smtp.gmail.com with ESMTPSA id b17sm154405edv.56.2021.02.09.18.45.57 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Tue, 09 Feb 2021 18:46:00 -0800 (PST) From: Bin Meng To: David Gibson , Greg Kurz Subject: [PATCH v2] target/ppc: Add E500 L2CSR0 write helper Date: Wed, 10 Feb 2021 10:45:52 +0800 Message-Id: <1612925152-20913-1-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.7.4 Received-SPF: pass client-ip=2a00:1450:4864:20::62a; envelope-from=bmeng.cn@gmail.com; helo=mail-ej1-x62a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bin Meng , qemu-ppc@nongnu.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Bin Meng Per EREF 2.0 [1] chapter 3.11.2: The following bits in L2CSR0 (exists in the e500mc/e5500/e6500 core): - L2FI (L2 cache flash invalidate) - L2FL (L2 cache flush) - L2LFC (L2 cache lock flash clear) when set, a cache operation is initiated by hardware, and these bits will be cleared when the operation is complete. Since we don't model cache in QEMU, let's add a write helper to emulate the cache operations completing instantly. [1] https://www.nxp.com/files-static/32bit/doc/ref_manual/EREFRM.pdf Signed-off-by: Bin Meng --- Changes in v2: - Add Freescale manual link and clarifications in the commit message target/ppc/cpu.h | 6 ++++++ target/ppc/translate_init.c.inc | 16 ++++++++++++++++ 2 files changed, 22 insertions(+) diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 2609e40..e77911a 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -1919,6 +1919,7 @@ typedef PowerPCCPU ArchCPU; #define SPR_750FX_HID2 (0x3F8) #define SPR_Exxx_L1FINV0 (0x3F8) #define SPR_L2CR (0x3F9) +#define SPR_Exxx_L2CSR0 (0x3F9) #define SPR_L3CR (0x3FA) #define SPR_750_TDCH (0x3FA) #define SPR_IABR2 (0x3FA) @@ -1974,6 +1975,11 @@ typedef PowerPCCPU ArchCPU; #define L1CSR1_ICFI 0x00000002 /* Instruction Cache Flash Invalidate */ #define L1CSR1_ICE 0x00000001 /* Instruction Cache Enable */ +/* E500 L2CSR0 */ +#define E500_L2CSR0_L2FI (1 << 21) /* L2 cache flash invalidate */ +#define E500_L2CSR0_L2FL (1 << 11) /* L2 cache flush */ +#define E500_L2CSR0_L2LFC (1 << 10) /* L2 cache lock flash clear */ + /* HID0 bits */ #define HID0_DEEPNAP (1 << 24) /* pre-2.06 */ #define HID0_DOZE (1 << 23) /* pre-2.06 */ diff --git a/target/ppc/translate_init.c.inc b/target/ppc/translate_init.c.inc index 9867d0a..3ec45cb 100644 --- a/target/ppc/translate_init.c.inc +++ b/target/ppc/translate_init.c.inc @@ -1735,6 +1735,16 @@ static void spr_write_e500_l1csr1(DisasContext *ctx, int sprn, int gprn) tcg_temp_free(t0); } +static void spr_write_e500_l2csr0(DisasContext *ctx, int sprn, int gprn) +{ + TCGv t0 = tcg_temp_new(); + + tcg_gen_andi_tl(t0, cpu_gpr[gprn], + ~(E500_L2CSR0_L2FI | E500_L2CSR0_L2FL | E500_L2CSR0_L2LFC)); + gen_store_spr(sprn, t0); + tcg_temp_free(t0); +} + static void spr_write_booke206_mmucsr0(DisasContext *ctx, int sprn, int gprn) { gen_helper_booke206_tlbflush(cpu_env, cpu_gpr[gprn]); @@ -5029,6 +5039,12 @@ static void init_proc_e500(CPUPPCState *env, int version) SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_e500_l1csr1, 0x00000000); + if (version != fsl_e500v1 && version != fsl_e500v2) { + spr_register(env, SPR_Exxx_L2CSR0, "L2CSR0", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_e500_l2csr0, + 0x00000000); + } spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0", SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic,