From patchwork Fri Feb 5 23:47:20 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Leo Li X-Patchwork-Id: 1436940 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4DXc6x5blQz9sWV for ; Sat, 6 Feb 2021 13:43:53 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231491AbhBFCnC (ORCPT ); Fri, 5 Feb 2021 21:43:02 -0500 Received: from inva020.nxp.com ([92.121.34.13]:45672 "EHLO inva020.nxp.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230029AbhBFCil (ORCPT ); Fri, 5 Feb 2021 21:38:41 -0500 Received: from inva020.nxp.com (localhost [127.0.0.1]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 43C2A1A17D5; Sat, 6 Feb 2021 00:50:48 +0100 (CET) Received: from smtp.na-rdc02.nxp.com (usphx01srsp001v.us-phx01.nxp.com [134.27.49.11]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 51A6A1A17C1; Sat, 6 Feb 2021 00:50:47 +0100 (CET) Received: from right.am.freescale.net (right.am.freescale.net [10.81.116.70]) by usphx01srsp001v.us-phx01.nxp.com (Postfix) with ESMTP id 18FB740A63; Fri, 5 Feb 2021 16:50:43 -0700 (MST) From: Li Yang To: Shawn Guo , Rob Herring , devicetree@vger.kernel.org, Oleksij Rempel , Krzysztof Kozlowski , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Li Yang Subject: [PATCH 01/15] dt-bindings: arm: fsl: add ls1021a-tsn board Date: Fri, 5 Feb 2021 17:47:20 -0600 Message-Id: <20210205234734.3397-2-leoyang.li@nxp.com> X-Mailer: git-send-email 2.25.1.377.g2d2118b In-Reply-To: <20210205234734.3397-1-leoyang.li@nxp.com> References: <20210205234734.3397-1-leoyang.li@nxp.com> MIME-Version: 1.0 X-Virus-Scanned: ClamAV using ClamSMTP Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add the missing board in the binding docuemnt. Signed-off-by: Li Yang Acked-by: Rob Herring --- Documentation/devicetree/bindings/arm/fsl.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index 297c87f45db8..85277c8045fe 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -834,6 +834,7 @@ properties: - enum: - fsl,ls1021a-moxa-uc-8410a - fsl,ls1021a-qds + - fsl,ls1021a-tsn - fsl,ls1021a-twr - const: fsl,ls1021a From patchwork Fri Feb 5 23:47:21 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Leo Li X-Patchwork-Id: 1436961 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4DXdBy6cG9z9sVb for ; Sat, 6 Feb 2021 14:32:26 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231574AbhBFDau (ORCPT ); Fri, 5 Feb 2021 22:30:50 -0500 Received: from inva020.nxp.com ([92.121.34.13]:58666 "EHLO inva020.nxp.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230334AbhBFD2d (ORCPT ); Fri, 5 Feb 2021 22:28:33 -0500 Received: from inva020.nxp.com (localhost [127.0.0.1]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 994841A0BED; Sat, 6 Feb 2021 00:50:50 +0100 (CET) Received: from smtp.na-rdc02.nxp.com (usphx01srsp001v.us-phx01.nxp.com [134.27.49.11]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 529E61A025F; Sat, 6 Feb 2021 00:50:50 +0100 (CET) Received: from right.am.freescale.net (right.am.freescale.net [10.81.116.70]) by usphx01srsp001v.us-phx01.nxp.com (Postfix) with ESMTP id 2D82540BCF; Fri, 5 Feb 2021 16:50:46 -0700 (MST) From: Li Yang To: Shawn Guo , Rob Herring , devicetree@vger.kernel.org, Oleksij Rempel , Krzysztof Kozlowski , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Li Yang Subject: [PATCH 02/15] dt-bindings: i2c: imx: update schema to align with original binding Date: Fri, 5 Feb 2021 17:47:21 -0600 Message-Id: <20210205234734.3397-3-leoyang.li@nxp.com> X-Mailer: git-send-email 2.25.1.377.g2d2118b In-Reply-To: <20210205234734.3397-1-leoyang.li@nxp.com> References: <20210205234734.3397-1-leoyang.li@nxp.com> MIME-Version: 1.0 X-Virus-Scanned: ClamAV using ClamSMTP Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Layerscape SoCs doesn't use ipg as clock name. Remove the clock name requirement in the schema. Also the original binding doesn't enforce the order of "tx" and "rx" in dma-names. Both orders are used extensively in existing dtses, update the schema to allow both. Signed-off-by: Li Yang --- Documentation/devicetree/bindings/i2c/i2c-imx.yaml | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a/Documentation/devicetree/bindings/i2c/i2c-imx.yaml b/Documentation/devicetree/bindings/i2c/i2c-imx.yaml index f23966b0d6c6..57237b0b7d89 100644 --- a/Documentation/devicetree/bindings/i2c/i2c-imx.yaml +++ b/Documentation/devicetree/bindings/i2c/i2c-imx.yaml @@ -54,20 +54,19 @@ properties: maxItems: 1 clock-names: - const: ipg + maxItems: 1 clock-frequency: enum: [ 100000, 400000 ] dmas: - items: - - description: DMA controller phandle and request line for RX - - description: DMA controller phandle and request line for TX + minItems: 2 + maxItems: 2 dma-names: items: - - const: rx - - const: tx + - enum: [ "rx", "tx" ] + - enum: [ "tx", "rx" ] sda-gpios: maxItems: 1 From patchwork Fri Feb 5 23:47:22 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Leo Li X-Patchwork-Id: 1436960 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4DXdBx4HD6z9sVb for ; Sat, 6 Feb 2021 14:32:25 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230249AbhBFDao (ORCPT ); Fri, 5 Feb 2021 22:30:44 -0500 Received: from inva021.nxp.com ([92.121.34.21]:60526 "EHLO inva021.nxp.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230252AbhBFD22 (ORCPT ); Fri, 5 Feb 2021 22:28:28 -0500 Received: from inva021.nxp.com (localhost [127.0.0.1]) by inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id 1C9C120014B; Sat, 6 Feb 2021 00:50:51 +0100 (CET) Received: from smtp.na-rdc02.nxp.com (usphx01srsp001v.us-phx01.nxp.com [134.27.49.11]) by inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id B1D2120016E; Sat, 6 Feb 2021 00:50:50 +0100 (CET) Received: from right.am.freescale.net (right.am.freescale.net [10.81.116.70]) by usphx01srsp001v.us-phx01.nxp.com (Postfix) with ESMTP id CF96640011; Fri, 5 Feb 2021 16:50:49 -0700 (MST) From: Li Yang To: Shawn Guo , Rob Herring , devicetree@vger.kernel.org, Oleksij Rempel , Krzysztof Kozlowski , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Li Yang Subject: [PATCH 03/15] dt-bindings: memory: fsl: convert ifc binding to yaml schema Date: Fri, 5 Feb 2021 17:47:22 -0600 Message-Id: <20210205234734.3397-4-leoyang.li@nxp.com> X-Mailer: git-send-email 2.25.1.377.g2d2118b In-Reply-To: <20210205234734.3397-1-leoyang.li@nxp.com> References: <20210205234734.3397-1-leoyang.li@nxp.com> MIME-Version: 1.0 X-Virus-Scanned: ClamAV using ClamSMTP Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Convert the txt binding to yaml format and add description. Also updated the recommended node name to ifc-bus to align with the simple-bus node name requirements. Signed-off-by: Li Yang --- .../bindings/memory-controllers/fsl/ifc.txt | 82 ---------- .../bindings/memory-controllers/fsl/ifc.yaml | 140 ++++++++++++++++++ 2 files changed, 140 insertions(+), 82 deletions(-) delete mode 100644 Documentation/devicetree/bindings/memory-controllers/fsl/ifc.txt create mode 100644 Documentation/devicetree/bindings/memory-controllers/fsl/ifc.yaml diff --git a/Documentation/devicetree/bindings/memory-controllers/fsl/ifc.txt b/Documentation/devicetree/bindings/memory-controllers/fsl/ifc.txt deleted file mode 100644 index 89427b018ba7..000000000000 --- a/Documentation/devicetree/bindings/memory-controllers/fsl/ifc.txt +++ /dev/null @@ -1,82 +0,0 @@ -Integrated Flash Controller - -Properties: -- name : Should be ifc -- compatible : should contain "fsl,ifc". The version of the integrated - flash controller can be found in the IFC_REV register at - offset zero. - -- #address-cells : Should be either two or three. The first cell is the - chipselect number, and the remaining cells are the - offset into the chipselect. -- #size-cells : Either one or two, depending on how large each chipselect - can be. -- reg : Offset and length of the register set for the device -- interrupts: IFC may have one or two interrupts. If two interrupt - specifiers are present, the first is the "common" - interrupt (CM_EVTER_STAT), and the second is the NAND - interrupt (NAND_EVTER_STAT). If there is only one, - that interrupt reports both types of event. - -- little-endian : If this property is absent, the big-endian mode will - be in use as default for registers. - -- ranges : Each range corresponds to a single chipselect, and covers - the entire access window as configured. - -Child device nodes describe the devices connected to IFC such as NOR (e.g. -cfi-flash) and NAND (fsl,ifc-nand). There might be board specific devices -like FPGAs, CPLDs, etc. - -Example: - - ifc@ffe1e000 { - compatible = "fsl,ifc", "simple-bus"; - #address-cells = <2>; - #size-cells = <1>; - reg = <0x0 0xffe1e000 0 0x2000>; - interrupts = <16 2 19 2>; - little-endian; - - /* NOR, NAND Flashes and CPLD on board */ - ranges = <0x0 0x0 0x0 0xee000000 0x02000000 - 0x1 0x0 0x0 0xffa00000 0x00010000 - 0x3 0x0 0x0 0xffb00000 0x00020000>; - - flash@0,0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "cfi-flash"; - reg = <0x0 0x0 0x2000000>; - bank-width = <2>; - device-width = <1>; - - partition@0 { - /* 32MB for user data */ - reg = <0x0 0x02000000>; - label = "NOR Data"; - }; - }; - - flash@1,0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "fsl,ifc-nand"; - reg = <0x1 0x0 0x10000>; - - partition@0 { - /* This location must not be altered */ - /* 1MB for u-boot Bootloader Image */ - reg = <0x0 0x00100000>; - label = "NAND U-Boot Image"; - read-only; - }; - }; - - cpld@3,0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "fsl,p1010rdb-cpld"; - reg = <0x3 0x0 0x000001f>; - }; - }; diff --git a/Documentation/devicetree/bindings/memory-controllers/fsl/ifc.yaml b/Documentation/devicetree/bindings/memory-controllers/fsl/ifc.yaml new file mode 100644 index 000000000000..d37cae66b027 --- /dev/null +++ b/Documentation/devicetree/bindings/memory-controllers/fsl/ifc.yaml @@ -0,0 +1,140 @@ +# SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/memory-controllers/fsl/ifc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: FSL/NXP Integrated Flash Controller + +maintainers: + - Li Yang + +description: | + NXP's integrated flash controller (IFC) is an advanced version of the + enhanced local bus controller which includes similar programming and signal + interfaces with an extended feature set. The IFC provides access to multiple + external memory types, such as NAND flash (SLC and MLC), NOR flash, EPROM, + SRAM and other memories where address and data are shared on a bus. + +allOf: + - $ref: /schemas/simple-bus.yaml# + +properties: + $nodename: + pattern: "^ifc-bus@[0-9a-f]+$" + + compatible: + contains: + const: fsl,ifc + + "#address-cells": + enum: [2, 3] + description: | + Should be either two or three. The first cell is the chipselect + number, and the remaining cells are the offset into the chipselect. + + "#size-cells": + enum: [1, 2] + description: | + Either one or two, depending on how large each chipselect can be. + + reg: + maxItems: 1 + description: | + Offset and length of the register set for the device. + + interrupts: + minItems: 1 + maxItems: 2 + description: | + IFC may have one or two interrupts. If two interrupt specifiers are + present, the first is the "common" interrupt (CM_EVTER_STAT), and the + second is the NAND interrupt (NAND_EVTER_STAT). If there is only one, + that interrupt reports both types of event. + + little-endian: + description: | + If this property is absent, the big-endian mode will be in use as default + for registers. + + ranges: + description: | + Each range corresponds to a single chipselect, and covers the entire + access window as configured. + +patternProperties: + "^.*@[a-f0-9]+(,[a-f0-9]+)+$": + type: object + description: | + Child device nodes describe the devices connected to IFC such as NOR (e.g. + cfi-flash) and NAND (fsl,ifc-nand). There might be board specific devices + like FPGAs, CPLDs, etc. + + required: + - compatible + - reg + +required: + - compatible + - reg + - interrupts + +additionalProperties: false + +examples: + - | + soc { + #address-cells = <2>; + #size-cells = <2>; + + ifc-bus@ffe1e000 { + compatible = "fsl,ifc", "simple-bus"; + #address-cells = <2>; + #size-cells = <1>; + reg = <0x0 0xffe1e000 0 0x2000>; + interrupts = <16 2 19 2>; + little-endian; + + /* NOR, NAND Flashes and CPLD on board */ + ranges = <0x0 0x0 0x0 0xee000000 0x02000000>, + <0x1 0x0 0x0 0xffa00000 0x00010000>, + <0x3 0x0 0x0 0xffb00000 0x00020000>; + + flash@0,0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "cfi-flash"; + reg = <0x0 0x0 0x2000000>; + bank-width = <2>; + device-width = <1>; + + partition@0 { + /* 32MB for user data */ + reg = <0x0 0x02000000>; + label = "NOR Data"; + }; + }; + + flash@1,0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,ifc-nand"; + reg = <0x1 0x0 0x10000>; + + partition@0 { + /* This location must not be altered */ + /* 1MB for u-boot Bootloader Image */ + reg = <0x0 0x00100000>; + label = "NAND U-Boot Image"; + read-only; + }; + }; + + cpld@3,0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,p1010rdb-cpld"; + reg = <0x3 0x0 0x000001f>; + }; + }; + };