From patchwork Fri Jan 29 13:23:14 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 1433307 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=eqEG4lbq; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4DRyk83Tt2z9sW1 for ; Sat, 30 Jan 2021 00:24:46 +1100 (AEDT) Received: from localhost ([::1]:52650 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l5TlS-0003bb-OT for incoming@patchwork.ozlabs.org; Fri, 29 Jan 2021 08:24:42 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:59688) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l5Tkg-0003ZY-Te; Fri, 29 Jan 2021 08:23:54 -0500 Received: from mail-pf1-x42a.google.com ([2607:f8b0:4864:20::42a]:46423) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l5Tkf-0007sb-Cb; Fri, 29 Jan 2021 08:23:54 -0500 Received: by mail-pf1-x42a.google.com with SMTP id f63so6209806pfa.13; Fri, 29 Jan 2021 05:23:52 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=kkLTOezkfKdPVe5VTO0yLce91pnJrqvoONkhLftQoZk=; b=eqEG4lbqJhLaCZLhPB91Aun/2c7Ahu1Agy2+z9p4cSbVDMViJJBZyR0BU9MsExrKwS v9n8skX2ZvtNqDMOWxMoN9iMbo1TwL1PQy3wt1d4ODxQjzo3Rn3V1Rf+7Qsgn0OtDJbR wt+FdK9K5B83+NOMFArOHh26vLPEOrr7e1JgX5iYGkR3qgfslsFORW8XeMzU2x8pGQZa 7xjSkimBdIfc4ncU0aDB7MV7Uld2dtR/1lz99KByhHEkGRlPdetOqme0k256W4w3LOB/ YXYfOYe6zgAoEhdNxH+sYIAZsCbnGEV+p6lOOsO6Y53WMQ7D39UByr2ZWo90K+MasIP2 I1HA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=kkLTOezkfKdPVe5VTO0yLce91pnJrqvoONkhLftQoZk=; b=fTpQNCBxipFagb/GmD5ROe3otdz1qfmlBLq8/Mi0MJ/9pGgSYvjeruXEVYzXMXUNvE qyN0Fy0X7UQug3UCw93fAWGhnEtyeAuuCjUYyykfdHvHh0mKvl72up/uloQS7THDbPjo THdFfQbRFPaGdsW5tJXTaoev9sNK3j41pavAvCcg8Yx1hVRKWoo5Y5fYZ3eq/0SvsvhD d96zKeAIBj0Mn1tSCRP5Wv4MttGxQ5TBF3pKI1SLzCxi6RS+Hzi5pYy2p6EGT0oRokVr bQ43qRBarRIQEAxzoLvb+WI3Vk3XNwJiyoHfkNQHUVgisZAaN1UVvdEm1CzWxYYMPfmO lbiA== X-Gm-Message-State: AOAM530gwPR4r27IYkqqW8Nk7W+RW3BN+wZ/c0jUwTOk7Z/wuAqZyuU6 2/NUIKBABKl21xeNpzioLpY= X-Google-Smtp-Source: ABdhPJy9NgTS3aaFYc2HlE0ft0ekaDM77VB+t9udjad8wE+2HXMq+woALq+JHIzrf7yi26OV9LoqhA== X-Received: by 2002:a05:6a00:16c7:b029:1bc:6eb9:ee47 with SMTP id l7-20020a056a0016c7b02901bc6eb9ee47mr4539608pfc.0.1611926631946; Fri, 29 Jan 2021 05:23:51 -0800 (PST) Received: from i9-aorus-gtx1080.localdomain (144.168.56.201.16clouds.com. [144.168.56.201]) by smtp.gmail.com with ESMTPSA id j6sm8857259pfg.159.2021.01.29.05.23.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 29 Jan 2021 05:23:51 -0800 (PST) From: Bin Meng To: Peter Maydell , Jean-Christophe Dubois , =?utf-8?q?Philippe_Mathieu-Da?= =?utf-8?q?ud=C3=A9?= , Alistair Francis , qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v9 01/10] hw/ssi: imx_spi: Use a macro for number of chip selects supported Date: Fri, 29 Jan 2021 21:23:14 +0800 Message-Id: <20210129132323.30946-2-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210129132323.30946-1-bmeng.cn@gmail.com> References: <20210129132323.30946-1-bmeng.cn@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42a; envelope-from=bmeng.cn@gmail.com; helo=mail-pf1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bin Meng , Juan Quintela Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Bin Meng Avoid using a magic number (4) everywhere for the number of chip selects supported. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Juan Quintela --- (no changes since v1) include/hw/ssi/imx_spi.h | 5 ++++- hw/ssi/imx_spi.c | 4 ++-- 2 files changed, 6 insertions(+), 3 deletions(-) diff --git a/include/hw/ssi/imx_spi.h b/include/hw/ssi/imx_spi.h index b82b17f364..eeaf49bbac 100644 --- a/include/hw/ssi/imx_spi.h +++ b/include/hw/ssi/imx_spi.h @@ -77,6 +77,9 @@ #define EXTRACT(value, name) extract32(value, name##_SHIFT, name##_LENGTH) +/* number of chip selects supported */ +#define ECSPI_NUM_CS 4 + #define TYPE_IMX_SPI "imx.spi" OBJECT_DECLARE_SIMPLE_TYPE(IMXSPIState, IMX_SPI) @@ -89,7 +92,7 @@ struct IMXSPIState { qemu_irq irq; - qemu_irq cs_lines[4]; + qemu_irq cs_lines[ECSPI_NUM_CS]; SSIBus *bus; diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c index d8885ae454..e605049a21 100644 --- a/hw/ssi/imx_spi.c +++ b/hw/ssi/imx_spi.c @@ -361,7 +361,7 @@ static void imx_spi_write(void *opaque, hwaddr offset, uint64_t value, /* We are in master mode */ - for (i = 0; i < 4; i++) { + for (i = 0; i < ECSPI_NUM_CS; i++) { qemu_set_irq(s->cs_lines[i], i == imx_spi_selected_channel(s) ? 0 : 1); } @@ -424,7 +424,7 @@ static void imx_spi_realize(DeviceState *dev, Error **errp) sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem); sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq); - for (i = 0; i < 4; ++i) { + for (i = 0; i < ECSPI_NUM_CS; ++i) { sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->cs_lines[i]); } From patchwork Fri Jan 29 13:23:15 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 1433308 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=qIvbNySf; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4DRyk82GLhz9sSC for ; Sat, 30 Jan 2021 00:24:48 +1100 (AEDT) Received: from localhost ([::1]:52978 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l5TlW-0003kt-7S for incoming@patchwork.ozlabs.org; Fri, 29 Jan 2021 08:24:46 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:59738) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l5Tku-0003ib-Rw; Fri, 29 Jan 2021 08:24:10 -0500 Received: from mail-pf1-x435.google.com ([2607:f8b0:4864:20::435]:37752) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l5Tkl-0007vi-NZ; Fri, 29 Jan 2021 08:24:03 -0500 Received: by mail-pf1-x435.google.com with SMTP id 11so6229918pfu.4; Fri, 29 Jan 2021 05:23:59 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Ja59qADvqfh/2q+KQY+LSk2zC5zuDWA+c5NUnArnusQ=; b=qIvbNySfjDas6JHaKn94Jzi284Ig8lyM4svVDtouJWOz0XRyzOeMBbXFn/n6Q4kqln eWxbFcmc9JqUXhiRTm0xFRswFsDTIwvKTs4UnXszcC0VLfPsJq7Eiy9EoOkiJObmdHJs S9IM4xFxb0tBrsckaY/x2FRQzAWZjJCMljV9fPAcpS42A+IOIk4v3sYTbnfVRYhjmS2J oBDMOmh/0WUFRl/TW7EMvxRxoJFNX/3X05n+WKG286GYpoQVghx/cy6mDzCG+CtO29K/ ZQu3YMLibD70fQIcgmYcea+AIf9kJx/yE3A7DJeWm1yMJTCfEiIxNxtvCtgtlw0LNHEm Eh+g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Ja59qADvqfh/2q+KQY+LSk2zC5zuDWA+c5NUnArnusQ=; b=L6Bw4N25zy0jvrIIJlnPgNxqw3OlokaSaT+9ZFfjEhnvDFIJexzQlGSn+GCiqUsLdS FxAQFeRJ4vVvRzYbq5RKK5nF08Pyp/3dPSVQ9RKrHnt2SCRPSVk4d8mEPi4ARwVCj4/o lKEVlRrC9tWTSJArRzIwFjKo4J+oPVVL17NnlXKkXyeDh7ly4n+QOVerV4tkFGvqPI26 ieYiWLb53H0WAK19uSRnFG+4Pk3dgt6qcRW/zxMVeaOa8aBq5eFztCI5VRb9XAWjtIoi RltYYqAk11lek4YVIoUdUnKsKKGuxA88IsN2XUijANV8YDjvQhDL6u3eZPRlHyrPHotk CsDw== X-Gm-Message-State: AOAM532d77fsNzW30fTpv7Kn1jCdwSscjvA6ckQUSXjPUhHgf7WxUC48 IexlRhNWOecrBj6ai58Qjxg= X-Google-Smtp-Source: ABdhPJyP0TXEaXYrtGfOVrtXdfAkWzyJqSHsZvoGjPrBhpiYvfwcQft87rmH0gJO/8No+xbZWNBxHg== X-Received: by 2002:a63:171d:: with SMTP id x29mr4779341pgl.168.1611926638249; Fri, 29 Jan 2021 05:23:58 -0800 (PST) Received: from i9-aorus-gtx1080.localdomain (144.168.56.201.16clouds.com. [144.168.56.201]) by smtp.gmail.com with ESMTPSA id j6sm8857259pfg.159.2021.01.29.05.23.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 29 Jan 2021 05:23:57 -0800 (PST) From: Bin Meng To: Peter Maydell , Jean-Christophe Dubois , =?utf-8?q?Philippe_Mathieu-Da?= =?utf-8?q?ud=C3=A9?= , Alistair Francis , qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v9 02/10] hw/ssi: imx_spi: Remove imx_spi_update_irq() in imx_spi_reset() Date: Fri, 29 Jan 2021 21:23:15 +0800 Message-Id: <20210129132323.30946-3-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210129132323.30946-1-bmeng.cn@gmail.com> References: <20210129132323.30946-1-bmeng.cn@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::435; envelope-from=bmeng.cn@gmail.com; helo=mail-pf1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bin Meng Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Bin Meng Usually the approach is that the device on the other end of the line is going to reset its state anyway, so there's no need to actively signal an irq line change during the reset hook. Move imx_spi_update_irq() out of imx_spi_reset(), to a new function imx_spi_soft_reset() that is called when the controller is disabled. Signed-off-by: Bin Meng Reviewed-by: Peter Maydell --- (no changes since v5) Changes in v5: - rename imx_spi_hard_reset() to imx_spi_soft_reset() Changes in v4: - adujst the patch 2,3 order - rename imx_spi_soft_reset() to imx_spi_hard_reset() to avoid confusion Changes in v3: - new patch: remove imx_spi_update_irq() in imx_spi_reset() hw/ssi/imx_spi.c | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c index e605049a21..4d488b159a 100644 --- a/hw/ssi/imx_spi.c +++ b/hw/ssi/imx_spi.c @@ -241,11 +241,16 @@ static void imx_spi_reset(DeviceState *dev) imx_spi_rxfifo_reset(s); imx_spi_txfifo_reset(s); - imx_spi_update_irq(s); - s->burst_length = 0; } +static void imx_spi_soft_reset(IMXSPIState *s) +{ + imx_spi_reset(DEVICE(s)); + + imx_spi_update_irq(s); +} + static uint64_t imx_spi_read(void *opaque, hwaddr offset, unsigned size) { uint32_t value = 0; @@ -351,8 +356,9 @@ static void imx_spi_write(void *opaque, hwaddr offset, uint64_t value, s->regs[ECSPI_CONREG] = value; if (!imx_spi_is_enabled(s)) { - /* device is disabled, so this is a reset */ - imx_spi_reset(DEVICE(s)); + /* device is disabled, so this is a soft reset */ + imx_spi_soft_reset(s); + return; } From patchwork Fri Jan 29 13:23:16 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 1433310 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=Jsdz9+/f; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4DRym52B6sz9sWC for ; Sat, 30 Jan 2021 00:26:29 +1100 (AEDT) Received: from localhost ([::1]:54744 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l5Tn9-0004W9-8X for incoming@patchwork.ozlabs.org; Fri, 29 Jan 2021 08:26:27 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:59752) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l5Tky-0003je-LC; Fri, 29 Jan 2021 08:24:15 -0500 Received: from mail-pj1-x1031.google.com ([2607:f8b0:4864:20::1031]:33962) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l5Tku-0007xw-Ew; Fri, 29 Jan 2021 08:24:11 -0500 Received: by mail-pj1-x1031.google.com with SMTP id my11so6461217pjb.1; Fri, 29 Jan 2021 05:24:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=3jrYO5yz/J2x1yetvpXGtvLlgKXHVau4sRG7K210isU=; b=Jsdz9+/f/5wZFbrhXlxddOR3acr3mlGNT9rupY8Zl7SRBzvlgJMLKLEdvV8NY340ip bZHy0JFACntK7/mqWYLmyna29/oXiMNgr44k5kmmqX0LY9tEMiGNahoaA39TP/LZioWj nWRre2JvyEATHPrOMNEyBFqUf5nBENN4SRik/g9B6iMyKngy1zJNsOfhGdmm/gZeSltI Hx24nBjx3LxSmX3xLLgmvPXCOxBk4Vv5Dcktqf0KctWjP1OwQHq8MeYPWQXYGK6P3VGU 7MP3Ga1yypb38NC9FOByRoBmrdNXq5+OctlWta6+Lb3HdXZ+o2F5JdypevovXGrflknV L9dw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=3jrYO5yz/J2x1yetvpXGtvLlgKXHVau4sRG7K210isU=; b=gdUSVpxcPLVRT7NYVdgIqVli/LpjhnKLGipDOLS2kWBiV/2WV0Cwq9Jrd4ZbR6vqiZ C7lRZXYimcf6O9Xl4L0elCvuXKxGyja0PXDvwzCnoskaAHZc6/2KqL9lj+glSaLDD21E 93viJp6YV+AFfO9MZEkCCroHyRREmQhYfmdeOduWtrnk4AWvGZ3UKIcxwNddLXQK4OtE QQWhHv1wOCgqzEx2X/f2ItMu68qypfgbXSY8x+xWvjUuj0mx+uV99ME4f3R1TssFFhbD zCZwXeRkvq3gQHPMTqtVcHtnTVsyj3cgazoKnsy5g1sZNk2eBh+dSndAdr5EC7wy3AiL fDkA== X-Gm-Message-State: AOAM533TeTf894JP/5Cq9cXQC05SzbUixFazbgHn56CQKrJz29M2ypmr il0PMgrwJKFCbRawCI68AXc= X-Google-Smtp-Source: ABdhPJxwmX9NVkeIvUbjKBU3la09esY60T104AFAGjfoht4KeQ02bm3yVXzmYUjUsbvruLB5c43xdw== X-Received: by 2002:a17:902:9044:b029:df:fa69:1ed1 with SMTP id w4-20020a1709029044b02900dffa691ed1mr4204665plz.11.1611926645606; Fri, 29 Jan 2021 05:24:05 -0800 (PST) Received: from i9-aorus-gtx1080.localdomain (144.168.56.201.16clouds.com. [144.168.56.201]) by smtp.gmail.com with ESMTPSA id j6sm8857259pfg.159.2021.01.29.05.23.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 29 Jan 2021 05:24:05 -0800 (PST) From: Bin Meng To: Peter Maydell , Jean-Christophe Dubois , =?utf-8?q?Philippe_Mathieu-Da?= =?utf-8?q?ud=C3=A9?= , Alistair Francis , qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v9 03/10] hw/ssi: imx_spi: Remove pointless variable initialization Date: Fri, 29 Jan 2021 21:23:16 +0800 Message-Id: <20210129132323.30946-4-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210129132323.30946-1-bmeng.cn@gmail.com> References: <20210129132323.30946-1-bmeng.cn@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1031; envelope-from=bmeng.cn@gmail.com; helo=mail-pj1-x1031.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bin Meng , Juan Quintela Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Philippe Mathieu-Daudé 'burst_length' is cleared in imx_spi_reset(), which is called after imx_spi_realize(). Remove the initialization to simplify. Reviewed-by: Juan Quintela Signed-off-by: Philippe Mathieu-Daudé Message-Id: <20210115153049.3353008-3-f4bug@amsat.org> Reviewed-by: Bin Meng Signed-off-by: Bin Meng --- (no changes since v7) Changes in v7: - remove the RFC tag Changes in v6: - new patch: [RFC] remove pointless variable initialization hw/ssi/imx_spi.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c index 4d488b159a..8fb3c9b6d1 100644 --- a/hw/ssi/imx_spi.c +++ b/hw/ssi/imx_spi.c @@ -434,8 +434,6 @@ static void imx_spi_realize(DeviceState *dev, Error **errp) sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->cs_lines[i]); } - s->burst_length = 0; - fifo32_create(&s->tx_fifo, ECSPI_FIFO_SIZE); fifo32_create(&s->rx_fifo, ECSPI_FIFO_SIZE); } From patchwork Fri Jan 29 13:23:17 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 1433312 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=b0+Ihryo; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4DRypt6y0jz9sSC for ; Sat, 30 Jan 2021 00:28:54 +1100 (AEDT) Received: from localhost ([::1]:33234 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l5TpU-0007Iv-LR for incoming@patchwork.ozlabs.org; Fri, 29 Jan 2021 08:28:52 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:59790) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l5Tl8-0003oz-Bq; Fri, 29 Jan 2021 08:24:22 -0500 Received: from mail-pf1-x42e.google.com ([2607:f8b0:4864:20::42e]:39375) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l5Tl6-00082F-Nl; Fri, 29 Jan 2021 08:24:22 -0500 Received: by mail-pf1-x42e.google.com with SMTP id e19so6221381pfh.6; Fri, 29 Jan 2021 05:24:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=5mXXyyknt34UXruqKVI1mRb9uaGtIfcaWSlxoOQ+8iA=; b=b0+IhryofXgzeqY/ClfgBYRj1BGdTbR0F00TslTqkjyhVRlWYmUStnxQEK9GO622UB nanKSaSp2uKzgTVTHq1GIE2ey2agSRhilKZX7WbN4AMuOAOJun6amrLbiIPfmfDNeH7M K1y/IFD4sOKXVZsVsQ1Dit27HEn4zvcsJf/zgiuFJoBEOQxF8rTOV3IJzCi0IdZ3+qPO oATD6Fsy98GVAgQJSghr8ycrtBH/cUNrr9il8BBnn8YYqYwMxd8aMM6QVA9vCLB2E95Q OD6ht5ioOnDFnelWfXetB2o8gnnmFxHdyQCjei7aSiLZppjYLFXNzLkMq2vrV80ZEh2d Nb8A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=5mXXyyknt34UXruqKVI1mRb9uaGtIfcaWSlxoOQ+8iA=; b=CxJ1k75yi+2mvDUjqdVDVyMbd5ULklldt+7iNgHjwuhuEQP6ahnpkye0N7GZwfDZNh 0QXo1GRe4RsxjnvdmvfoU2SUdO2mF/l9aPp84nEFFJwR0vcRNOzDW+J3JuSBuWsBy5aF qDPfIvyYKu4HOl3VHm5fNMIRwuezd4bS/IuqUKkdtwmReQn4784sQ73YsnjTiBMYVQfZ 6UHLV85H1aUzYUX6WiunUlZ19JLXb045uDQ0XCOSNCvEh2oZJUOWvrbbYpIkzXboYrYC 2GWu5wYPqC24lPRfKUdSQmJ/MUT4BemYUg/lcrAPtuK/9k9M9ArymKkeukyzHCNZbPe8 PDOQ== X-Gm-Message-State: AOAM532tEna3Gzd+vPClS42xbvUXun1TyA631UoVc3Lai5xfcNOaQsMi DMWxvxfC8We2pWA66UxiM8Y= X-Google-Smtp-Source: ABdhPJw+kj3ROHXFi8kQDZQTvlZ8HNyZPrzfnTnDsfJf/0ERhh6HxaEW/hWlxWsOXRq2rvVQtepx7g== X-Received: by 2002:a63:c64:: with SMTP id 36mr4751076pgm.282.1611926659235; Fri, 29 Jan 2021 05:24:19 -0800 (PST) Received: from i9-aorus-gtx1080.localdomain (144.168.56.201.16clouds.com. [144.168.56.201]) by smtp.gmail.com with ESMTPSA id j6sm8857259pfg.159.2021.01.29.05.24.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 29 Jan 2021 05:24:18 -0800 (PST) From: Bin Meng To: Peter Maydell , Jean-Christophe Dubois , =?utf-8?q?Philippe_Mathieu-Da?= =?utf-8?q?ud=C3=A9?= , Alistair Francis , qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v9 04/10] hw/ssi: imx_spi: Rework imx_spi_reset() to keep CONREG register value Date: Fri, 29 Jan 2021 21:23:17 +0800 Message-Id: <20210129132323.30946-5-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210129132323.30946-1-bmeng.cn@gmail.com> References: <20210129132323.30946-1-bmeng.cn@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42e; envelope-from=bmeng.cn@gmail.com; helo=mail-pf1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bin Meng Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Philippe Mathieu-Daudé When the block is disabled, all registers are reset with the exception of the ECSPI_CONREG. It is initialized to zero when the instance is created. Ref: i.MX 6DQ Applications Processor Reference Manual (IMX6DQRM), chapter 21.7.3: Control Register (ECSPIx_CONREG) Signed-off-by: Philippe Mathieu-Daudé [bmeng: add a 'common_reset' function that does most of reset operation] Signed-off-by: Bin Meng Reviewed-by: Philippe Mathieu-Daudé --- Changes in v9: - Add a 'common_reset' function that does most of reset operation, leaving ECSPI_CONREG clear in imx_spi_reset(). Changes in v7: - remove the RFC tag Changes in v6: - new patch: [RFC] rework imx_spi_reset() to keep CONREG register value hw/ssi/imx_spi.c | 32 ++++++++++++++++++++++++-------- 1 file changed, 24 insertions(+), 8 deletions(-) diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c index 8fb3c9b6d1..e85be6ae60 100644 --- a/hw/ssi/imx_spi.c +++ b/hw/ssi/imx_spi.c @@ -228,15 +228,23 @@ static void imx_spi_flush_txfifo(IMXSPIState *s) fifo32_num_used(&s->tx_fifo), fifo32_num_used(&s->rx_fifo)); } -static void imx_spi_reset(DeviceState *dev) +static void imx_spi_common_reset(IMXSPIState *s) { - IMXSPIState *s = IMX_SPI(dev); - - DPRINTF("\n"); - - memset(s->regs, 0, sizeof(s->regs)); + int i; - s->regs[ECSPI_STATREG] = 0x00000003; + for (i = 0; i < ARRAY_SIZE(s->regs); i++) { + switch (i) { + case ECSPI_CONREG: + /* CONREG is not updated on soft reset */ + break; + case ECSPI_STATREG: + s->regs[i] = 0x00000003; + break; + default: + s->regs[i] = 0; + break; + } + } imx_spi_rxfifo_reset(s); imx_spi_txfifo_reset(s); @@ -246,11 +254,19 @@ static void imx_spi_reset(DeviceState *dev) static void imx_spi_soft_reset(IMXSPIState *s) { - imx_spi_reset(DEVICE(s)); + imx_spi_common_reset(s); imx_spi_update_irq(s); } +static void imx_spi_reset(DeviceState *dev) +{ + IMXSPIState *s = IMX_SPI(dev); + + imx_spi_common_reset(s); + s->regs[ECSPI_CONREG] = 0; +} + static uint64_t imx_spi_read(void *opaque, hwaddr offset, unsigned size) { uint32_t value = 0; From patchwork Fri Jan 29 13:23:18 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 1433313 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=hZjiIhA6; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4DRyrq69WHz9sSC for ; Sat, 30 Jan 2021 00:30:35 +1100 (AEDT) Received: from localhost ([::1]:35454 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l5Tr7-0008DP-Nd for incoming@patchwork.ozlabs.org; Fri, 29 Jan 2021 08:30:33 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:59804) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l5TlE-00042c-S6; Fri, 29 Jan 2021 08:24:28 -0500 Received: from mail-pl1-x62c.google.com ([2607:f8b0:4864:20::62c]:44029) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l5TlD-00084l-35; Fri, 29 Jan 2021 08:24:28 -0500 Received: by mail-pl1-x62c.google.com with SMTP id 31so5212870plb.10; Fri, 29 Jan 2021 05:24:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=SXP/QcpeVzooZtaZF1E9k2db9E1DHz3DCHI+nO8tjBw=; b=hZjiIhA6dPA+zXViVBMDAzzdbf0phBVB0mp9AJGWUtJELzLciuzF08A7GDSrfRoM0i keYO8x+FmtiFdWjEnmHPrtFmi2kMXGWRlDISpwv9fCjYkWBhwR754+K1DLzPKw3u5c6v WTVshjqoGu3RPM2DDaBJwExM39uemw7EHPt/azYaZDHLeyz2EOcTu+xS3Xplu+QSVLHK opIZSKHnXlTp20xYPdlNstnAaPxGBVY/5TuvqVzPjppyHo/gXLSDO5ax/fPgJTK3U112 6f3eCNPUH85xYkxS7yyfYXW0DxCC3YbxpVfspCWJdWYra3Q7odD4HQryE6ViSEWKjwi0 Yl9g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=SXP/QcpeVzooZtaZF1E9k2db9E1DHz3DCHI+nO8tjBw=; b=MaQFkOgWL2twO8iFi9YpsJmaBVwuzpbuZ3ZYd1dUaKUgE9A5/zEL1CQfgguXj8mNYG 7mUuDKlw6RPnQuFIvV7YKCqVqAyMdNdculdLspzGFfLUn8ZaZOWy/4x2Jo2G4pIwtVj5 s4PsC5+oCwpDfL1sHHtaUBnDwfyg0febMb3OW5/kE2duDjw9OE/Z520sF4lasAvzYA8h fBTeDYhtS0tqYNvvlTYkmrIdo5OytfCmbe0nGuC1YEmQWzgliehPmoGvoMYEu5v0CrFY xq2JT5BwMqDJE6BdgWMejYNm7RAzQjKwdfCnnkUSnH3Twnb5UaOTBZx4nb/KQGNgyw3C +hzg== X-Gm-Message-State: AOAM5301PYjx5XK8BQpWZy+9Ji6Sm2YrXD5cAnXgxSQR3BkvIyMTBTuR Ol0+Ur4rBt9zc3MYmLroYAaibYVGx/PK2g== X-Google-Smtp-Source: ABdhPJxiM7yYKjosSrFZBr1PDdObFsKr1Q0N0TZ26Tc+VoY12rCpr0QMou5VdAAfEb3bOP9gyo4zIQ== X-Received: by 2002:a17:903:248f:b029:de:c703:9839 with SMTP id p15-20020a170903248fb02900dec7039839mr4318910plw.42.1611926665489; Fri, 29 Jan 2021 05:24:25 -0800 (PST) Received: from i9-aorus-gtx1080.localdomain (144.168.56.201.16clouds.com. [144.168.56.201]) by smtp.gmail.com with ESMTPSA id j6sm8857259pfg.159.2021.01.29.05.24.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 29 Jan 2021 05:24:24 -0800 (PST) From: Bin Meng To: Peter Maydell , Jean-Christophe Dubois , =?utf-8?q?Philippe_Mathieu-Da?= =?utf-8?q?ud=C3=A9?= , Alistair Francis , qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v9 05/10] hw/ssi: imx_spi: Rework imx_spi_read() to handle block disabled Date: Fri, 29 Jan 2021 21:23:18 +0800 Message-Id: <20210129132323.30946-6-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210129132323.30946-1-bmeng.cn@gmail.com> References: <20210129132323.30946-1-bmeng.cn@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62c; envelope-from=bmeng.cn@gmail.com; helo=mail-pl1-x62c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bin Meng , Juan Quintela Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Philippe Mathieu-Daudé When the block is disabled, it stay it is 'internal reset logic' (internal clocks are gated off). Reading any register returns its reset value. Only update this value if the device is enabled. Ref: i.MX 6DQ Applications Processor Reference Manual (IMX6DQRM), chapter 21.7.3: Control Register (ECSPIx_CONREG) Reviewed-by: Juan Quintela Signed-off-by: Philippe Mathieu-Daudé Message-Id: <20210115153049.3353008-5-f4bug@amsat.org> Reviewed-by: Bin Meng Signed-off-by: Bin Meng --- (no changes since v7) Changes in v7: - remove the RFC tag Changes in v6: - new patch: [RFC] rework imx_spi_read() to handle block disabled hw/ssi/imx_spi.c | 60 +++++++++++++++++++++++------------------------- 1 file changed, 29 insertions(+), 31 deletions(-) diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c index e85be6ae60..21e2c9dea3 100644 --- a/hw/ssi/imx_spi.c +++ b/hw/ssi/imx_spi.c @@ -279,42 +279,40 @@ static uint64_t imx_spi_read(void *opaque, hwaddr offset, unsigned size) return 0; } - switch (index) { - case ECSPI_RXDATA: - if (!imx_spi_is_enabled(s)) { - value = 0; - } else if (fifo32_is_empty(&s->rx_fifo)) { - /* value is undefined */ - value = 0xdeadbeef; - } else { - /* read from the RX FIFO */ - value = fifo32_pop(&s->rx_fifo); - } - - break; - case ECSPI_TXDATA: - qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Trying to read from TX FIFO\n", - TYPE_IMX_SPI, __func__); - - /* Reading from TXDATA gives 0 */ - - break; - case ECSPI_MSGDATA: - qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Trying to read from MSG FIFO\n", - TYPE_IMX_SPI, __func__); + value = s->regs[index]; + + if (imx_spi_is_enabled(s)) { + switch (index) { + case ECSPI_RXDATA: + if (fifo32_is_empty(&s->rx_fifo)) { + /* value is undefined */ + value = 0xdeadbeef; + } else { + /* read from the RX FIFO */ + value = fifo32_pop(&s->rx_fifo); + } + break; + case ECSPI_TXDATA: + qemu_log_mask(LOG_GUEST_ERROR, + "[%s]%s: Trying to read from TX FIFO\n", + TYPE_IMX_SPI, __func__); - /* Reading from MSGDATA gives 0 */ + /* Reading from TXDATA gives 0 */ + break; + case ECSPI_MSGDATA: + qemu_log_mask(LOG_GUEST_ERROR, + "[%s]%s: Trying to read from MSG FIFO\n", + TYPE_IMX_SPI, __func__); + /* Reading from MSGDATA gives 0 */ + break; + default: + break; + } - break; - default: - value = s->regs[index]; - break; + imx_spi_update_irq(s); } - DPRINTF("reg[%s] => 0x%" PRIx32 "\n", imx_spi_reg_name(index), value); - imx_spi_update_irq(s); - return (uint64_t)value; } From patchwork Fri Jan 29 13:23:19 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 1433315 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=PMe3wFhD; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4DRyx61WTHz9sVF for ; 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[144.168.56.201]) by smtp.gmail.com with ESMTPSA id j6sm8857259pfg.159.2021.01.29.05.24.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 29 Jan 2021 05:24:32 -0800 (PST) From: Bin Meng To: Peter Maydell , Jean-Christophe Dubois , =?utf-8?q?Philippe_Mathieu-Da?= =?utf-8?q?ud=C3=A9?= , Alistair Francis , qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v9 06/10] hw/ssi: imx_spi: Rework imx_spi_write() to handle block disabled Date: Fri, 29 Jan 2021 21:23:19 +0800 Message-Id: <20210129132323.30946-7-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210129132323.30946-1-bmeng.cn@gmail.com> References: <20210129132323.30946-1-bmeng.cn@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102c; envelope-from=bmeng.cn@gmail.com; helo=mail-pj1-x102c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bin Meng Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Philippe Mathieu-Daudé When the block is disabled, only the ECSPI_CONREG register can be modified. Setting the EN bit enabled the device, clearing it "disables the block and resets the internal logic with the exception of the ECSPI_CONREG" register. Ignore all other registers write except ECSPI_CONREG when the block is disabled. Ref: i.MX 6DQ Applications Processor Reference Manual (IMX6DQRM), chapter 21.7.3: Control Register (ECSPIx_CONREG) Signed-off-by: Philippe Mathieu-Daudé Message-Id: <20210115153049.3353008-6-f4bug@amsat.org> Signed-off-by: Bin Meng Reviewed-by: Peter Maydell --- (no changes since v8) Changes in v8: - keep the controller disable logic in the ECSPI_CONREG case in imx_spi_write() Changes in v7: - remove the RFC tag Changes in v6: - new patch: [RFC] rework imx_spi_write() to handle block disabled hw/ssi/imx_spi.c | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c index 21e2c9dea3..4cfbb73e35 100644 --- a/hw/ssi/imx_spi.c +++ b/hw/ssi/imx_spi.c @@ -332,6 +332,14 @@ static void imx_spi_write(void *opaque, hwaddr offset, uint64_t value, DPRINTF("reg[%s] <= 0x%" PRIx32 "\n", imx_spi_reg_name(index), (uint32_t)value); + if (!imx_spi_is_enabled(s)) { + /* Block is disabled */ + if (index != ECSPI_CONREG) { + /* Ignore access */ + return; + } + } + change_mask = s->regs[index] ^ value; switch (index) { @@ -340,10 +348,7 @@ static void imx_spi_write(void *opaque, hwaddr offset, uint64_t value, TYPE_IMX_SPI, __func__); break; case ECSPI_TXDATA: - if (!imx_spi_is_enabled(s)) { - /* Ignore writes if device is disabled */ - break; - } else if (fifo32_is_full(&s->tx_fifo)) { + if (fifo32_is_full(&s->tx_fifo)) { /* Ignore writes if queue is full */ break; } From patchwork Fri Jan 29 13:23:20 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 1433318 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=dXXRH7+H; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4DRz124dXMz9sSC for ; Sat, 30 Jan 2021 00:37:42 +1100 (AEDT) Received: from localhost ([::1]:52558 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l5Ty0-0006yc-Jp for incoming@patchwork.ozlabs.org; Fri, 29 Jan 2021 08:37:40 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:59840) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l5TlU-0004fw-0o; Fri, 29 Jan 2021 08:24:44 -0500 Received: from mail-pf1-x434.google.com ([2607:f8b0:4864:20::434]:34096) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l5TlS-0008BS-Ar; Fri, 29 Jan 2021 08:24:43 -0500 Received: by mail-pf1-x434.google.com with SMTP id m6so6233925pfk.1; Fri, 29 Jan 2021 05:24:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=arRlN344IEUt++/WHKWnko22ZyvawohyzOe7fEOUZng=; b=dXXRH7+HALphmZwtowWgWVoD9g01u3ZkMMwybZiPR0dEB5gWsNBn7AbfpA4j4rrKhn JiCYNFZOVRZpiw+gOdUH+woomiEB/lrac5V3bPm1dQCQFtXuAAVnvgaesGJAKUsbh4V3 ukI/2cRrBXJZmbRMJkRtK7jIOdhmPCm0VYKlCWy1NzLZFj09pN6o3nGvqiJ3QEgYU+nZ 6ao3CRdiiCl5VmGFVbvGzBBBiLNu7727JYDc1uJP6Bi+XQIXzAwTWzHdvRpQccZMzeTC +YhJlbiVVKrX06Br7cMtGQMimjzY+ld+jt6Q/pOHw7KXkduLniVlvzGsZCMP27kC14Ur LDmw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=arRlN344IEUt++/WHKWnko22ZyvawohyzOe7fEOUZng=; b=a1XcS6MyJiZSyIwQnWNB7lLqlYYtTA6MicFY3ecQDZHJbdrG2+yG+miBYDdw1Or7sH SQlsJhtyOQ11U0/oXE5KkODHnJTkc3c7qTsxZvH3u/BXjXTf5r8/1mEaaGZ9YA4+qEqq ygIgqtr1j3ijFvfOt2DdLkZZGO/yxHfLo9qdv7FYJjHMqYc7pgGAW7qk01Cl/LsHal3t jlFp3B/mK67YvHeauqeW0oeaxLEUlbSpBYhpjIj2zkU3bgrcRalqmfMTN4fqNBe8ETXO t5cbjG3OBgOU4Jb3HjQ5D0MqT/SlXTzb40/DSWOtNx0psESh/BaQaelbRQycmtL9Ijf8 FZCQ== X-Gm-Message-State: AOAM533jHyog9E59QokXA/ZOzj/Y5PkYj9y1i4Oj70nzwoTM67QTInb5 PhbIwdy2tbBPROGlDi9lzwqJ7yHEnRTJ3Q== X-Google-Smtp-Source: ABdhPJyeDaszL+aAJHwbf4bAc976WnzFYmUiUnOfHZu9EnsUjO6o3Mq4JHdwUdQjLJ2dmVQfffTZBQ== X-Received: by 2002:a63:c441:: with SMTP id m1mr4659328pgg.353.1611926680772; Fri, 29 Jan 2021 05:24:40 -0800 (PST) Received: from i9-aorus-gtx1080.localdomain (144.168.56.201.16clouds.com. [144.168.56.201]) by smtp.gmail.com with ESMTPSA id j6sm8857259pfg.159.2021.01.29.05.24.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 29 Jan 2021 05:24:40 -0800 (PST) From: Bin Meng To: Peter Maydell , Jean-Christophe Dubois , =?utf-8?q?Philippe_Mathieu-Da?= =?utf-8?q?ud=C3=A9?= , Alistair Francis , qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v9 07/10] hw/ssi: imx_spi: Disable chip selects when controller is disabled Date: Fri, 29 Jan 2021 21:23:20 +0800 Message-Id: <20210129132323.30946-8-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210129132323.30946-1-bmeng.cn@gmail.com> References: <20210129132323.30946-1-bmeng.cn@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::434; envelope-from=bmeng.cn@gmail.com; helo=mail-pf1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Xuzhou Cheng , Bin Meng Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Xuzhou Cheng When a write to ECSPI_CONREG register to disable the SPI controller, imx_spi_soft_reset() is called to reset the controller, but chip select lines should have been disabled, otherwise the state machine of any devices (e.g.: SPI flashes) connected to the SPI master is stuck to its last state and responds incorrectly to any follow-up commands. Fixes: c906a3a01582 ("i.MX: Add the Freescale SPI Controller") Signed-off-by: Xuzhou Cheng Signed-off-by: Bin Meng Reviewed-by: Philippe Mathieu-Daudé --- (no changes since v3) Changes in v3: - Move the chip selects disable out of imx_spi_reset() Changes in v2: - Fix the "Fixes" tag in the commit message hw/ssi/imx_spi.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c index 4cfbb73e35..2fb65498c3 100644 --- a/hw/ssi/imx_spi.c +++ b/hw/ssi/imx_spi.c @@ -254,9 +254,15 @@ static void imx_spi_common_reset(IMXSPIState *s) static void imx_spi_soft_reset(IMXSPIState *s) { + int i; + imx_spi_common_reset(s); imx_spi_update_irq(s); + + for (i = 0; i < ECSPI_NUM_CS; i++) { + qemu_set_irq(s->cs_lines[i], 1); + } } static void imx_spi_reset(DeviceState *dev) From patchwork Fri Jan 29 13:23:21 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 1433314 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=KlXJxjm7; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4DRyt52BJsz9sW0 for ; Sat, 30 Jan 2021 00:31:41 +1100 (AEDT) Received: from localhost ([::1]:37278 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l5TsB-0000Xc-6b for incoming@patchwork.ozlabs.org; Fri, 29 Jan 2021 08:31:39 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:59866) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l5Tla-0004vE-92; Fri, 29 Jan 2021 08:24:50 -0500 Received: from mail-pg1-x52a.google.com ([2607:f8b0:4864:20::52a]:39898) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l5TlY-0008EE-Jo; Fri, 29 Jan 2021 08:24:50 -0500 Received: by mail-pg1-x52a.google.com with SMTP id o63so6649561pgo.6; Fri, 29 Jan 2021 05:24:47 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=LFsuI0BABtR2qo+SroCf7kUB6qpaMqblWl0znWx3WO8=; b=KlXJxjm7esUMyRKo6adtW3JPyDDQb0UuMcWWb/KUNRlRNzaxQ10p0IM+Y6MaBZNjrZ Ic3e5wmhGrLVSv5BOhDW9z68GTYz3Ttdf//JEZnqSBXjxaMvUIN0u95V0eEwL8N+zZ+e huVJWOosgVOqExr6rY7XNnYeu+9u5ogZ8vZWuJSiDX0XqPVsr8jgB3PCK7nGWbwOvxeB G6Gr20976+FLPBVDZnUcdw403nD3UNH+GJ6CiX7aRDphPkLbdd9lEhxRPMZl8zz+zhs3 eYXxVMfEL0X77wgRT3xOu2e3/EwS4BJ6hTiT/kxZYwhuPoUO6UvaswDCNr8pysy5UsZh mkDw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=LFsuI0BABtR2qo+SroCf7kUB6qpaMqblWl0znWx3WO8=; b=GzMJtvrKCY/vcjs3kntBVUU4mbnfee1WQWv5sq0fIbL+g2SKJnhiyavBNz/GcAnk9v mViuL9syCkECo+kcM4vGf7Z06VpgScBo18O3X2EdI6YqQCvwjD0PineROfgiqY+8oD9C JeskOIp/oFlMWBT/5QBmu5FmxUFVRg9DoeoJJPOSbvTfAsVB7mV/hDG1NaLE5aTbWmrZ 1WggfcCuTsLnC6E7EuhOWc+9ryW2UyTtCQoRYeoick+CvG4um3fMwzfeEp5Gq4q17yyM 6lsD+aPo2aTpyiw0o6x4ibwCreYUJZ3Ktzcgtu2nseeBQyrZg9sPaNIqdiBKmSaCyHcN OG0Q== X-Gm-Message-State: AOAM530mTvOoeAMJ2bdGMY92mzbSeeUdw4zkyqs04upXhZJzseFu6Eke 5ngWVD5KXrpjWGBw54NpSgMjOy9NgwGV7Q== X-Google-Smtp-Source: ABdhPJyramRlfvvjxqOVjQnQmZ3mTD0h+BvuhHA5Rzk02dtUIs82J8hxnVWMNa2DWgdmSDLCtkX38A== X-Received: by 2002:aa7:99db:0:b029:1ba:5263:63c4 with SMTP id v27-20020aa799db0000b02901ba526363c4mr4272972pfi.53.1611926687117; Fri, 29 Jan 2021 05:24:47 -0800 (PST) Received: from i9-aorus-gtx1080.localdomain (144.168.56.201.16clouds.com. [144.168.56.201]) by smtp.gmail.com with ESMTPSA id j6sm8857259pfg.159.2021.01.29.05.24.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 29 Jan 2021 05:24:46 -0800 (PST) From: Bin Meng To: Peter Maydell , Jean-Christophe Dubois , =?utf-8?q?Philippe_Mathieu-Da?= =?utf-8?q?ud=C3=A9?= , Alistair Francis , qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v9 08/10] hw/ssi: imx_spi: Round up the burst length to be multiple of 8 Date: Fri, 29 Jan 2021 21:23:21 +0800 Message-Id: <20210129132323.30946-9-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210129132323.30946-1-bmeng.cn@gmail.com> References: <20210129132323.30946-1-bmeng.cn@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::52a; envelope-from=bmeng.cn@gmail.com; helo=mail-pg1-x52a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bin Meng Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Bin Meng Current implementation of the imx spi controller expects the burst length to be multiple of 8, which is the most common use case. In case the burst length is not what we expect, log it to give user a chance to notice it, and round it up to be multiple of 8. Signed-off-by: Bin Meng --- Changes in v9: - Do the LOG_UNIMP when the unsupported burst length value is written, rather than where it is used. - Squash the 2 LOG_UNIMP warnings down into one line Changes in v5: - round up the burst length to be multiple of 8 Changes in v4: - s/normal/common/ in the commit message - log the burst length value in the log message Changes in v3: - new patch: log unimplemented burst length hw/ssi/imx_spi.c | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-) diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c index 2fb65498c3..41fe199c9f 100644 --- a/hw/ssi/imx_spi.c +++ b/hw/ssi/imx_spi.c @@ -128,7 +128,14 @@ static uint8_t imx_spi_selected_channel(IMXSPIState *s) static uint32_t imx_spi_burst_length(IMXSPIState *s) { - return EXTRACT(s->regs[ECSPI_CONREG], ECSPI_CONREG_BURST_LENGTH) + 1; + uint32_t burst; + + burst = EXTRACT(s->regs[ECSPI_CONREG], ECSPI_CONREG_BURST_LENGTH) + 1; + if (burst % 8) { + burst = ROUND_UP(burst, 8); + } + + return burst; } static bool imx_spi_is_enabled(IMXSPIState *s) @@ -328,6 +335,7 @@ static void imx_spi_write(void *opaque, hwaddr offset, uint64_t value, IMXSPIState *s = opaque; uint32_t index = offset >> 2; uint32_t change_mask; + uint32_t burst; if (index >= ECSPI_MAX) { qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%" @@ -380,6 +388,13 @@ static void imx_spi_write(void *opaque, hwaddr offset, uint64_t value, case ECSPI_CONREG: s->regs[ECSPI_CONREG] = value; + burst = EXTRACT(s->regs[ECSPI_CONREG], ECSPI_CONREG_BURST_LENGTH) + 1; + if (burst % 8) { + qemu_log_mask(LOG_UNIMP, + "[%s]%s: burst length %d not supported: rounding up to next multiple of 8\n", + TYPE_IMX_SPI, __func__, burst); + } + if (!imx_spi_is_enabled(s)) { /* device is disabled, so this is a soft reset */ imx_spi_soft_reset(s); From patchwork Fri Jan 29 13:23:22 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 1433311 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; 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[144.168.56.201]) by smtp.gmail.com with ESMTPSA id j6sm8857259pfg.159.2021.01.29.05.24.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 29 Jan 2021 05:24:52 -0800 (PST) From: Bin Meng To: Peter Maydell , Jean-Christophe Dubois , =?utf-8?q?Philippe_Mathieu-Da?= =?utf-8?q?ud=C3=A9?= , Alistair Francis , qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v9 09/10] hw/ssi: imx_spi: Correct the burst length > 32 bit transfer logic Date: Fri, 29 Jan 2021 21:23:22 +0800 Message-Id: <20210129132323.30946-10-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210129132323.30946-1-bmeng.cn@gmail.com> References: <20210129132323.30946-1-bmeng.cn@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1036; envelope-from=bmeng.cn@gmail.com; helo=mail-pj1-x1036.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bin Meng Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Bin Meng For the ECSPIx_CONREG register BURST_LENGTH field, the manual says: 0x020 A SPI burst contains the 1 LSB in first word and all 32 bits in second word. 0x021 A SPI burst contains the 2 LSB in first word and all 32 bits in second word. Current logic uses either s->burst_length or 32, whichever smaller, to determine how many bits it should read from the tx fifo each time. For example, for a 48 bit burst length, current logic transfers the first 32 bit from the first word in the tx fifo, followed by a 16 bit from the second word in the tx fifo, which is wrong. The correct logic should be: transfer the first 16 bit from the first word in the tx fifo, followed by a 32 bit from the second word in the tx fifo. With this change, SPI flash can be successfully probed by U-Boot on imx6 sabrelite board. => sf probe SF: Detected sst25vf016b with page size 256 Bytes, erase size 4 KiB, total 2 MiB Fixes: c906a3a01582 ("i.MX: Add the Freescale SPI Controller") Signed-off-by: Bin Meng Reviewed-by: Philippe Mathieu-Daudé --- (no changes since v2) Changes in v2: - Use ternary operator as Philippe suggested hw/ssi/imx_spi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c index 41fe199c9f..a34194c1b0 100644 --- a/hw/ssi/imx_spi.c +++ b/hw/ssi/imx_spi.c @@ -185,7 +185,7 @@ static void imx_spi_flush_txfifo(IMXSPIState *s) DPRINTF("data tx:0x%08x\n", tx); - tx_burst = MIN(s->burst_length, 32); + tx_burst = (s->burst_length % 32) ? : 32; rx = 0; From patchwork Fri Jan 29 13:23:23 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 1433316 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=Ye19j0Hc; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4DRyzW4F6Mz9sSC for ; Sat, 30 Jan 2021 00:36:23 +1100 (AEDT) Received: from localhost ([::1]:47968 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l5Twj-00054U-Hl for incoming@patchwork.ozlabs.org; Fri, 29 Jan 2021 08:36:21 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:59928) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l5Tlq-0004zC-L0; Fri, 29 Jan 2021 08:25:09 -0500 Received: from mail-pj1-x102c.google.com ([2607:f8b0:4864:20::102c]:39118) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l5Tlk-0008KT-JL; Fri, 29 Jan 2021 08:25:06 -0500 Received: by mail-pj1-x102c.google.com with SMTP id d2so350031pjs.4; Fri, 29 Jan 2021 05:24:59 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=m0BdiYb2aO99L/y+s2LkY0AUaYKp2VRWJME7aRkjESk=; b=Ye19j0Hcekw+MArdFXSXZqQ0YaD/Pu6ySTpe1zmcgYsZs949nH3W/fQHgIc8uUEgdI zXk7SJeUn+re+yGURTkWdJTM7OirSioegfaWipkgraR/NpW5fbXtNmr/vSzLzRDYTWxN +po9w8ZLkwVvM4ZDpaDLWKEFVE2OXh1wHx3UPEzXRY0SToc5GAykajZn75HzXNLAlybu 836fQ4bON+dpsF6c3w9y34ZYjGqgJHLk3LqJo83RBuXjffKtYw1UhdxtaKDAUTaLD0dN QZx41Hmy5mv+/VSBnYXAScbdHuMoAHVjaKds6VakFhPCHwPtAtrFy/R1iJtWpjEhiDzo JplQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=m0BdiYb2aO99L/y+s2LkY0AUaYKp2VRWJME7aRkjESk=; b=SmSvChea63SizAq34q2Z8db3MYwaYAyRXFpOxXhwWcG3m2YNHyWIXFSuuYG2uzgFtB Nk+Tuz+/Hy4+2ubk456rRii/8vwIUehYSZWys974y9nIVsTbDmBnSsaMsg6RRORFRDf9 GyIf3tziY+mw51I/kJ6iXNqhWY+dAgbui1CLpATIRZGfH2WJs0aTY0kp7zTsTdpk2vba ciqbOCKaHlRXEcb9qUdpzFNB6DkKzqFite+H8xaqYltuXjw2OhTBH0+xo0Zh5xsWFvOX 1pIDn6v5f3gQXL9fZO0up1O840/lawT8Rf3OPQA/RbIKNNqGYDc9XKwo2YiffvzQt1kM wvUQ== X-Gm-Message-State: AOAM531I0iRUUlUoguAG7s82GUbp1pKhi4q3CT0F+5/5WMZ/YuCkxipf kXwko0pBbULoybjuO1r4QP4= X-Google-Smtp-Source: ABdhPJwAFrc6RveqiX+PcFtbEz0D6jtRlGRjLinj3n0u+YF9grcRCW/ujnYWI5VlfaH26z8BxLuU7g== X-Received: by 2002:a17:90a:8006:: with SMTP id b6mr4577952pjn.108.1611926699170; Fri, 29 Jan 2021 05:24:59 -0800 (PST) Received: from i9-aorus-gtx1080.localdomain (144.168.56.201.16clouds.com. [144.168.56.201]) by smtp.gmail.com with ESMTPSA id j6sm8857259pfg.159.2021.01.29.05.24.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 29 Jan 2021 05:24:58 -0800 (PST) From: Bin Meng To: Peter Maydell , Jean-Christophe Dubois , =?utf-8?q?Philippe_Mathieu-Da?= =?utf-8?q?ud=C3=A9?= , Alistair Francis , qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v9 10/10] hw/ssi: imx_spi: Correct tx and rx fifo endianness Date: Fri, 29 Jan 2021 21:23:23 +0800 Message-Id: <20210129132323.30946-11-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210129132323.30946-1-bmeng.cn@gmail.com> References: <20210129132323.30946-1-bmeng.cn@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102c; envelope-from=bmeng.cn@gmail.com; helo=mail-pj1-x102c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bin Meng Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Bin Meng The endianness of data exchange between tx and rx fifo is incorrect. Earlier bytes are supposed to show up on MSB and later bytes on LSB, ie: in big endian. The manual does not explicitly say this, but the U-Boot and Linux driver codes have a swap on the data transferred to tx fifo and from rx fifo. With this change, U-Boot read from / write to SPI flash tests pass. => sf test 1ff000 1000 SPI flash test: 0 erase: 0 ticks, 4096000 KiB/s 32768.000 Mbps 1 check: 3 ticks, 1333 KiB/s 10.664 Mbps 2 write: 235 ticks, 17 KiB/s 0.136 Mbps 3 read: 2 ticks, 2000 KiB/s 16.000 Mbps Test passed 0 erase: 0 ticks, 4096000 KiB/s 32768.000 Mbps 1 check: 3 ticks, 1333 KiB/s 10.664 Mbps 2 write: 235 ticks, 17 KiB/s 0.136 Mbps 3 read: 2 ticks, 2000 KiB/s 16.000 Mbps Fixes: c906a3a01582 ("i.MX: Add the Freescale SPI Controller") Signed-off-by: Bin Meng Reviewed-by: Peter Maydell --- (no changes since v3) Changes in v3: - Simplify the tx fifo endianness handling hw/ssi/imx_spi.c | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c index a34194c1b0..189423bb3a 100644 --- a/hw/ssi/imx_spi.c +++ b/hw/ssi/imx_spi.c @@ -169,7 +169,6 @@ static void imx_spi_flush_txfifo(IMXSPIState *s) while (!fifo32_is_empty(&s->tx_fifo)) { int tx_burst = 0; - int index = 0; if (s->burst_length <= 0) { s->burst_length = imx_spi_burst_length(s); @@ -190,7 +189,7 @@ static void imx_spi_flush_txfifo(IMXSPIState *s) rx = 0; while (tx_burst > 0) { - uint8_t byte = tx & 0xff; + uint8_t byte = tx >> (tx_burst - 8); DPRINTF("writing 0x%02x\n", (uint32_t)byte); @@ -199,13 +198,11 @@ static void imx_spi_flush_txfifo(IMXSPIState *s) DPRINTF("0x%02x read\n", (uint32_t)byte); - tx = tx >> 8; - rx |= (byte << (index * 8)); + rx = (rx << 8) | byte; /* Remove 8 bits from the actual burst */ tx_burst -= 8; s->burst_length -= 8; - index++; } DPRINTF("data rx:0x%08x\n", rx);