From patchwork Tue Jan 26 05:40:06 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: mark gross X-Patchwork-Id: 1432166 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4DQh916091z9s2g for ; Wed, 27 Jan 2021 22:25:09 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S313712AbhAZW6H (ORCPT ); Tue, 26 Jan 2021 17:58:07 -0500 Received: from mga12.intel.com ([192.55.52.136]:36176 "EHLO mga12.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2388333AbhAZFmg (ORCPT ); Tue, 26 Jan 2021 00:42:36 -0500 IronPort-SDR: /xu2OpLgAuDur+7K+A2D2Aq9QfNREKKF3dz+CXW+Vuk0GbHblqdgjyvjWm8qL8cm2KJNEXpGmv TU8KKohrpjaQ== X-IronPort-AV: E=McAfee;i="6000,8403,9875"; a="159028886" X-IronPort-AV: E=Sophos;i="5.79,375,1602572400"; d="scan'208";a="159028886" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Jan 2021 21:40:42 -0800 IronPort-SDR: tcScTWdAP7qZEACFRmSHHhY7/yMzCkqsbW155suT35MCpG8iSBGpbhtbJT/oiOddoyJsm7Q/5W iQtsOrddIg/Q== X-IronPort-AV: E=Sophos;i="5.79,375,1602572400"; d="scan'208";a="353335758" Received: from smtp.ostc.intel.com ([10.54.29.231]) by orsmga003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Jan 2021 21:40:42 -0800 Received: from mtg-dev.jf.intel.com (mtg-dev.jf.intel.com [10.54.74.10]) by smtp.ostc.intel.com (Postfix) with ESMTP id 6065B6365; Mon, 25 Jan 2021 21:40:40 -0800 (PST) Received: by mtg-dev.jf.intel.com (Postfix, from userid 1000) id 53FE8362FAE; Mon, 25 Jan 2021 21:40:40 -0800 (PST) From: mgross@linux.intel.com To: markgross@kernel.org, mgross@linux.intel.com, arnd@arndb.de, bp@suse.de, damien.lemoal@wdc.com, dragan.cvetic@xilinx.com, gregkh@linuxfoundation.org, corbet@lwn.net, palmerdabbelt@google.com, paul.walmsley@sifive.com, peng.fan@nxp.com, robh+dt@kernel.org, shawnguo@kernel.org, jassisinghbrar@gmail.com Cc: linux-kernel@vger.kernel.org, Daniele Alessandrelli , devicetree@vger.kernel.org Subject: [PATCH v3 04/34] dt-bindings: Add bindings for Keem Bay IPC driver Date: Mon, 25 Jan 2021 21:40:06 -0800 Message-Id: <20210126054036.61587-5-mgross@linux.intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210126054036.61587-1-mgross@linux.intel.com> References: <20210126054036.61587-1-mgross@linux.intel.com> Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Daniele Alessandrelli Add DT binding documentation for the Intel Keem Bay IPC driver, which enables communication between the Computing Sub-System (CSS) and the Multimedia Sub-System (MSS) of the Intel Movidius SoC code named Keem Bay. Cc: Rob Herring Cc: devicetree@vger.kernel.org Reviewed-by: Mark Gross Signed-off-by: Daniele Alessandrelli --- .../bindings/soc/intel/intel,keembay-ipc.yaml | 45 +++++++++++++++++++ 1 file changed, 45 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/intel/intel,keembay-ipc.yaml diff --git a/Documentation/devicetree/bindings/soc/intel/intel,keembay-ipc.yaml b/Documentation/devicetree/bindings/soc/intel/intel,keembay-ipc.yaml new file mode 100644 index 000000000000..586fe73f4cd4 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/intel/intel,keembay-ipc.yaml @@ -0,0 +1,45 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) 2020 Intel Corporation +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/soc/intel/intel,keembay-ipc.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Keem Bay IPC + +maintainers: + - Daniele Alessandrelli + +description: + The Keem Bay IPC driver enables Inter-Processor Communication (IPC) with the + Visual Processor Unit (VPU) embedded in the Intel Movidius SoC code named + Keem Bay. + +properties: + compatible: + const: intel,keembay-ipc + + memory-region: + items: + - description: + Reserved memory region used by the CPU to allocate IPC packets. + - description: + Reserved memory region used by the VPU to allocate IPC packets. + + mboxes: + description: VPU IPC Mailbox. + +required: + - compatible + - memory-region + - mboxes + +additionalProperties: false + +examples: + - | + ipc { + compatible = "intel,keembay-ipc"; + memory-region = <&ipc_cpu_reserved>, <&ipc_vpu_reserved>; + mboxes = <&vpu_ipc_mbox 0>; + }; From patchwork Tue Jan 26 05:40:08 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: mark gross X-Patchwork-Id: 1432168 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4DQh941py3z9s2g for ; Wed, 27 Jan 2021 22:25:12 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S313238AbhAZW6K (ORCPT ); Tue, 26 Jan 2021 17:58:10 -0500 Received: from mga12.intel.com ([192.55.52.136]:35936 "EHLO mga12.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731514AbhAZFm4 (ORCPT ); Tue, 26 Jan 2021 00:42:56 -0500 IronPort-SDR: 752K8DAOUdqO1kX6fkS0nvPK84kubdqNOBdz2MV+gdPLQGlfqqwe4ryJBKKj4PkkW9L0aXCQ8n s0B7Nk+9RbKg== X-IronPort-AV: E=McAfee;i="6000,8403,9875"; a="159028891" X-IronPort-AV: E=Sophos;i="5.79,375,1602572400"; d="scan'208";a="159028891" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Jan 2021 21:40:42 -0800 IronPort-SDR: Y9tkK5+B0CL7QYue7slilr0b5XXZWR99ojjw0BPz0tkutaNsd+7sPmIb0/gmimHiINiuMSZzU8 VADccHM8t7gA== X-IronPort-AV: E=Sophos;i="5.79,375,1602572400"; d="scan'208";a="353335762" Received: from smtp.ostc.intel.com ([10.54.29.231]) by orsmga003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Jan 2021 21:40:42 -0800 Received: from mtg-dev.jf.intel.com (mtg-dev.jf.intel.com [10.54.74.10]) by smtp.ostc.intel.com (Postfix) with ESMTP id 77390636E; Mon, 25 Jan 2021 21:40:40 -0800 (PST) Received: by mtg-dev.jf.intel.com (Postfix, from userid 1000) id 6AB733630A2; Mon, 25 Jan 2021 21:40:40 -0800 (PST) From: mgross@linux.intel.com To: markgross@kernel.org, mgross@linux.intel.com, arnd@arndb.de, bp@suse.de, damien.lemoal@wdc.com, dragan.cvetic@xilinx.com, gregkh@linuxfoundation.org, corbet@lwn.net, palmerdabbelt@google.com, paul.walmsley@sifive.com, peng.fan@nxp.com, robh+dt@kernel.org, shawnguo@kernel.org, jassisinghbrar@gmail.com Cc: linux-kernel@vger.kernel.org, Paul Murphy , devicetree@vger.kernel.org, Daniele Alessandrelli Subject: [PATCH v3 06/34] dt-bindings: Add bindings for Keem Bay VPU IPC driver Date: Mon, 25 Jan 2021 21:40:08 -0800 Message-Id: <20210126054036.61587-7-mgross@linux.intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210126054036.61587-1-mgross@linux.intel.com> References: <20210126054036.61587-1-mgross@linux.intel.com> Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Paul Murphy Add DT bindings documentation for the Keem Bay VPU IPC driver. Cc: Rob Herring Cc: devicetree@vger.kernel.org Reviewed-by: Mark Gross Signed-off-by: Paul Murphy Co-developed-by: Daniele Alessandrelli Signed-off-by: Daniele Alessandrelli --- .../soc/intel/intel,keembay-vpu-ipc.yaml | 153 ++++++++++++++++++ 1 file changed, 153 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/intel/intel,keembay-vpu-ipc.yaml diff --git a/Documentation/devicetree/bindings/soc/intel/intel,keembay-vpu-ipc.yaml b/Documentation/devicetree/bindings/soc/intel/intel,keembay-vpu-ipc.yaml new file mode 100644 index 000000000000..cd1c4abe8bc9 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/intel/intel,keembay-vpu-ipc.yaml @@ -0,0 +1,153 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +# Copyright (c) Intel Corporation. All rights reserved. +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/soc/intel/intel,keembay-vpu-ipc.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Intel Keem Bay VPU IPC + +maintainers: + - Paul Murphy + +description: + The VPU IPC driver facilitates loading of firmware, control, and communication + with the VPU over the IPC FIFO in the Intel Keem Bay SoC. + +properties: + compatible: + oneOf: + - items: + - const: intel,keembay-vpu-ipc + + reg: + items: + - description: NCE WDT registers + - description: NCE TIM_GEN_CONFIG registers + - description: MSS WDT registers + - description: MSS TIM_GEN_CONFIG registers + + reg-names: + items: + - const: nce_wdt + - const: nce_tim_cfg + - const: mss_wdt + - const: mss_tim_cfg + + memory-region: + items: + - description: reference to the VPU reserved memory region + - description: reference to the X509 reserved memory region + - description: reference to the MSS IPC area + + clocks: + items: + - description: cpu clock + - description: pll 0 out 0 rate + - description: pll 0 out 1 rate + - description: pll 0 out 2 rate + - description: pll 0 out 3 rate + - description: pll 1 out 0 rate + - description: pll 1 out 1 rate + - description: pll 1 out 2 rate + - description: pll 1 out 3 rate + - description: pll 2 out 0 rate + - description: pll 2 out 1 rate + - description: pll 2 out 2 rate + - description: pll 2 out 3 rate + + clock-names: + items: + - const: cpu_clock + - const: pll_0_out_0 + - const: pll_0_out_1 + - const: pll_0_out_2 + - const: pll_0_out_3 + - const: pll_1_out_0 + - const: pll_1_out_1 + - const: pll_1_out_2 + - const: pll_1_out_3 + - const: pll_2_out_0 + - const: pll_2_out_1 + - const: pll_2_out_2 + - const: pll_2_out_3 + + interrupts: + items: + - description: number of NCE sub-system WDT timeout IRQ + - description: number of MSS sub-system WDT timeout IRQ + + interrupt-names: + items: + - const: nce_wdt + - const: mss_wdt + + intel,keembay-vpu-ipc-nce-wdt-redirect: + $ref: "/schemas/types.yaml#/definitions/uint32" + description: + Number to which we will request that the NCE sub-system + re-directs it's WDT timeout IRQ + + intel,keembay-vpu-ipc-mss-wdt-redirect: + $ref: "/schemas/types.yaml#/definitions/uint32" + description: + Number to which we will request that the MSS sub-system + re-directs it's WDT timeout IRQ + + intel,keembay-vpu-ipc-imr: + $ref: "/schemas/types.yaml#/definitions/uint32" + description: + IMR (isolated memory region) number which we will request + the runtime service uses to protect the VPU memory region + before authentication + + intel,keembay-vpu-ipc-id: + $ref: "/schemas/types.yaml#/definitions/uint32" + description: The VPU ID to be passed to the VPU firmware. + +additionalProperties: False + +examples: + - | + #include + vpu-ipc@3f00209c { + compatible = "intel,keembay-vpu-ipc"; + reg = <0x3f00209c 0x10>, + <0x3f003008 0x4>, + <0x2082009c 0x10>, + <0x20821008 0x4>; + reg-names = "nce_wdt", + "nce_tim_cfg", + "mss_wdt", + "mss_tim_cfg"; + memory-region = <&vpu_reserved>, + <&vpu_x509_reserved>, + <&mss_ipc_reserved>; + clocks = <&scmi_clk 0>, + <&scmi_clk 0>, + <&scmi_clk 1>, + <&scmi_clk 2>, + <&scmi_clk 3>, + <&scmi_clk 4>, + <&scmi_clk 5>, + <&scmi_clk 6>, + <&scmi_clk 7>, + <&scmi_clk 8>, + <&scmi_clk 9>, + <&scmi_clk 10>, + <&scmi_clk 11>; + clock-names = "cpu_clock", + "pll_0_out_0", "pll_0_out_1", + "pll_0_out_2", "pll_0_out_3", + "pll_1_out_0", "pll_1_out_1", + "pll_1_out_2", "pll_1_out_3", + "pll_2_out_0", "pll_2_out_1", + "pll_2_out_2", "pll_2_out_3"; + interrupts = , + ; + interrupt-names = "nce_wdt", "mss_wdt"; + intel,keembay-vpu-ipc-nce-wdt-redirect = <63>; + intel,keembay-vpu-ipc-mss-wdt-redirect = <47>; + intel,keembay-vpu-ipc-imr = <9>; + intel,keembay-vpu-ipc-id = <0>; + }; From patchwork Tue Jan 26 05:40:19 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: mark gross X-Patchwork-Id: 1432167 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4DQh922Kv9z9sVX for ; Wed, 27 Jan 2021 22:25:10 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S313787AbhAZW6I (ORCPT ); Tue, 26 Jan 2021 17:58:08 -0500 Received: from mga05.intel.com ([192.55.52.43]:33188 "EHLO mga05.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2388335AbhAZFmg (ORCPT ); Tue, 26 Jan 2021 00:42:36 -0500 IronPort-SDR: Tt8sEtsT6JXD81tyfqmNrhomE6W1xx4xwHgj6Lci3D77BNVEOCI8Kc7ZOXC1CRXyQC1Kt9zizr OghmW+sDhDxQ== X-IronPort-AV: E=McAfee;i="6000,8403,9875"; a="264675334" X-IronPort-AV: E=Sophos;i="5.79,375,1602572400"; d="scan'208";a="264675334" Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Jan 2021 21:40:41 -0800 IronPort-SDR: oe4gAPvj2+32iyxAyHwDLWPD7MnwV0ovrYybMXl5FQDxIOfT2DCAvNeRP/pP0cJ+y08/+E41kq Wt625D1tzdYA== X-IronPort-AV: E=Sophos;i="5.79,375,1602572400"; d="scan'208";a="350563118" Received: from smtp.ostc.intel.com ([10.54.29.231]) by fmsmga007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Jan 2021 21:40:41 -0800 Received: from mtg-dev.jf.intel.com (mtg-dev.jf.intel.com [10.54.74.10]) by smtp.ostc.intel.com (Postfix) with ESMTP id 08A60636B; Mon, 25 Jan 2021 21:40:41 -0800 (PST) Received: by mtg-dev.jf.intel.com (Postfix, from userid 1000) id F097F363332; Mon, 25 Jan 2021 21:40:40 -0800 (PST) From: mgross@linux.intel.com To: markgross@kernel.org, mgross@linux.intel.com, arnd@arndb.de, bp@suse.de, damien.lemoal@wdc.com, dragan.cvetic@xilinx.com, gregkh@linuxfoundation.org, corbet@lwn.net, palmerdabbelt@google.com, paul.walmsley@sifive.com, peng.fan@nxp.com, robh+dt@kernel.org, shawnguo@kernel.org, jassisinghbrar@gmail.com Cc: linux-kernel@vger.kernel.org, Seamus Kelly , devicetree@vger.kernel.org, Ryan Carnaghi Subject: [PATCH v3 17/34] xlink-ipc: Add xlink ipc device tree bindings Date: Mon, 25 Jan 2021 21:40:19 -0800 Message-Id: <20210126054036.61587-18-mgross@linux.intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210126054036.61587-1-mgross@linux.intel.com> References: <20210126054036.61587-1-mgross@linux.intel.com> Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Seamus Kelly Add device tree bindings for the xLink IPC driver which enables xLink to control and communicate with the VPU IP present on the Intel Keem Bay SoC. Cc: Rob Herring Cc: devicetree@vger.kernel.org Reviewed-by: Mark Gross Signed-off-by: Seamus Kelly Signed-off-by: Ryan Carnaghi --- .../misc/intel,keembay-xlink-ipc.yaml | 49 +++++++++++++++++++ 1 file changed, 49 insertions(+) create mode 100644 Documentation/devicetree/bindings/misc/intel,keembay-xlink-ipc.yaml diff --git a/Documentation/devicetree/bindings/misc/intel,keembay-xlink-ipc.yaml b/Documentation/devicetree/bindings/misc/intel,keembay-xlink-ipc.yaml new file mode 100644 index 000000000000..699e43c4cd40 --- /dev/null +++ b/Documentation/devicetree/bindings/misc/intel,keembay-xlink-ipc.yaml @@ -0,0 +1,49 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +# Copyright (c) Intel Corporation. All rights reserved. +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/misc/intel,keembay-xlink-ipc.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Intel Keem Bay xlink IPC + +maintainers: + - Kelly Seamus + +description: | + The Keem Bay xlink IPC driver enables the communication/control sub-system + for internal IPC communications within the Intel Keem Bay SoC. + +properties: + compatible: + oneOf: + - items: + - const: intel,keembay-xlink-ipc + + memory-region: + items: + - description: reference to the CSS xlink IPC reserved memory region. + - description: reference to the MSS xlink IPC reserved memory region. + + intel,keembay-vpu-ipc-id: + $ref: "/schemas/types.yaml#/definitions/uint32" + description: The numeric ID identifying the VPU within the xLink stack. + + intel,keembay-vpu-ipc-name: + $ref: "/schemas/types.yaml#/definitions/string" + description: User-friendly name for the VPU within the xLink stack. + + intel,keembay-vpu-ipc: + $ref: "/schemas/types.yaml#/definitions/phandle" + description: reference to the corresponding intel,keembay-vpu-ipc node. + +examples: + - | + xlink-ipc { + compatible = "intel,keembay-xlink-ipc"; + memory-region = <&css_xlink_reserved>, + <&mss_xlink_reserved>; + intel,keembay-vpu-ipc-id = <0x0>; + intel,keembay-vpu-ipc-name = "vpu-slice-0"; + intel,keembay-vpu-ipc = <&vpuipc>; + }; From patchwork Tue Jan 26 05:40:21 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: mark gross X-Patchwork-Id: 1432165 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4DQh7w5M44z9s2g for ; Wed, 27 Jan 2021 22:24:12 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S313827AbhAZW6O (ORCPT ); Tue, 26 Jan 2021 17:58:14 -0500 Received: from mga14.intel.com ([192.55.52.115]:15182 "EHLO mga14.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726869AbhAZFqO (ORCPT ); Tue, 26 Jan 2021 00:46:14 -0500 IronPort-SDR: 9gNEcyW9PeVR83g2BNd3tXEn7zWHjh649F6vIuk6q4cIh30HMji+kUSPcJfwYqahk3Uc6BWJKf 4A7tB67PmLug== X-IronPort-AV: E=McAfee;i="6000,8403,9875"; a="179073452" X-IronPort-AV: E=Sophos;i="5.79,375,1602572400"; d="scan'208";a="179073452" Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Jan 2021 21:40:41 -0800 IronPort-SDR: qtYIzYHE5eS55PwzNGuvReJRdpi/ubm4Sny+fcUmkAt0ilM/PQvAHhxP/zBnfm9KGeI4J/fNKg c6c+MIXFrTLQ== X-IronPort-AV: E=Sophos;i="5.79,375,1602572400"; d="scan'208";a="573946853" Received: from smtp.ostc.intel.com ([10.54.29.231]) by fmsmga006-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Jan 2021 21:40:41 -0800 Received: from mtg-dev.jf.intel.com (mtg-dev.jf.intel.com [10.54.74.10]) by smtp.ostc.intel.com (Postfix) with ESMTP id 223306375; Mon, 25 Jan 2021 21:40:41 -0800 (PST) Received: by mtg-dev.jf.intel.com (Postfix, from userid 1000) id 160CA3633CC; Mon, 25 Jan 2021 21:40:41 -0800 (PST) From: mgross@linux.intel.com To: markgross@kernel.org, mgross@linux.intel.com, arnd@arndb.de, bp@suse.de, damien.lemoal@wdc.com, dragan.cvetic@xilinx.com, gregkh@linuxfoundation.org, corbet@lwn.net, palmerdabbelt@google.com, paul.walmsley@sifive.com, peng.fan@nxp.com, robh+dt@kernel.org, shawnguo@kernel.org, jassisinghbrar@gmail.com Cc: linux-kernel@vger.kernel.org, Seamus Kelly , devicetree@vger.kernel.org, Ryan Carnaghi Subject: [PATCH v3 19/34] xlink-core: Add xlink core device tree bindings Date: Mon, 25 Jan 2021 21:40:21 -0800 Message-Id: <20210126054036.61587-20-mgross@linux.intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210126054036.61587-1-mgross@linux.intel.com> References: <20210126054036.61587-1-mgross@linux.intel.com> Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Seamus Kelly Add device tree bindings for keembay-xlink. Cc: Rob Herring Cc: devicetree@vger.kernel.org Reviewed-by: Mark Gross Signed-off-by: Seamus Kelly Signed-off-by: Ryan Carnaghi --- .../bindings/misc/intel,keembay-xlink.yaml | 27 +++++++++++++++++++ 1 file changed, 27 insertions(+) create mode 100644 Documentation/devicetree/bindings/misc/intel,keembay-xlink.yaml diff --git a/Documentation/devicetree/bindings/misc/intel,keembay-xlink.yaml b/Documentation/devicetree/bindings/misc/intel,keembay-xlink.yaml new file mode 100644 index 000000000000..89c34018fa04 --- /dev/null +++ b/Documentation/devicetree/bindings/misc/intel,keembay-xlink.yaml @@ -0,0 +1,27 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +# Copyright (c) Intel Corporation. All rights reserved. +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/misc/intel,keembay-xlink.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Intel Keem Bay xlink + +maintainers: + - Seamus Kelly + +description: | + The Keem Bay xlink driver enables the communication/control sub-system + for internal and external communications to the Intel Keem Bay SoC. + +properties: + compatible: + oneOf: + - items: + - const: intel,keembay-xlink + +examples: + - | + xlink { + compatible = "intel,keembay-xlink"; + };