From patchwork Mon Jan 25 10:19:12 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 1431136 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=microchip.com header.i=@microchip.com header.a=rsa-sha256 header.s=mchp header.b=aGJd+h8+; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4DPQwx3bZsz9s2g for ; Mon, 25 Jan 2021 21:25:21 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727372AbhAYKYt (ORCPT ); Mon, 25 Jan 2021 05:24:49 -0500 Received: from esa.microchip.iphmx.com ([68.232.153.233]:63942 "EHLO esa.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727483AbhAYKWY (ORCPT ); Mon, 25 Jan 2021 05:22:24 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1611570144; x=1643106144; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=Jaf5ap+iRlOkRyLK7k0c5JvNu7KlWsQcAxQtQYo01tc=; b=aGJd+h8+0Owe0neCTCaabz+DqXWI4Ucb7djpKxWdQPVltjeztuil/anu rwPIeZfGFjIYLfPxUkYY0Fz/TSayNvYHzUJ5wjjSm49Dw1PEsFJf4VOY8 JXvEGqJYPDLqyoTLd5SACz151TLklHSCWfSwot23Plx8E3OZR0DeG6EJV wEGqks6OwcR0AsRCH6iJzF5bELjg2IIJYJFdeMfUTHVlY2gqVppjtyI2j W5Ntsu54bg3UWgV5Ym2+wHWkZJxgCh0X2zUHymvq7ZUnV+90Sf6sce/UR TgyTMk/JsV7OdKI1/DJVDqoBZ42qn64rs83lYorEZQ95c0Tu2n6/7uVPf Q==; IronPort-SDR: auLMmQbeDPZdalqB8hS/UqSVzeM4BRKpKA7JIztoIeE5szefrpMWTYy6fhnnOVnieEAkNyMHmx EtJhqrj92HMS6eV77nMpNNvQCM3LAykk2XUtRCrF54+xI7cZuQ6AMCg84G5Da2x9SLBB7oVHNX lb7kk12CK+U0dcasoQmuXWyEc6dpqipjN16+MjWQsvdg6REE+lCoO2HovSZdNT4OVui55xjVQa fBGUFr3dWDG7vXY/vvo9ig4IPuIEp2gZsUaOH65ROGcNXkaEpiKq1dLgHy67ZWAIHdclni0A2l jzg= X-IronPort-AV: E=Sophos;i="5.79,373,1602572400"; d="scan'208";a="107162032" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa3.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 25 Jan 2021 03:19:26 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1979.3; Mon, 25 Jan 2021 03:19:26 -0700 Received: from m18063-ThinkPad-T460p.microchip.com (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.1979.3 via Frontend Transport; Mon, 25 Jan 2021 03:19:21 -0700 From: Claudiu Beznea To: , , , , CC: , , , , Claudiu Beznea Subject: [PATCH 1/3] dt-bindings: pinctrl: at91-pio4: add slew-rate Date: Mon, 25 Jan 2021 12:19:12 +0200 Message-ID: <1611569954-23279-2-git-send-email-claudiu.beznea@microchip.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1611569954-23279-1-git-send-email-claudiu.beznea@microchip.com> References: <1611569954-23279-1-git-send-email-claudiu.beznea@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Document slew-rate DT binding for SAMA7G5. Signed-off-by: Claudiu Beznea Acked-by: Ludovic Desroches --- .../devicetree/bindings/pinctrl/atmel,at91-pio4-pinctrl.txt | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/pinctrl/atmel,at91-pio4-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/atmel,at91-pio4-pinctrl.txt index 265015bc0603..e2b861ce16d8 100644 --- a/Documentation/devicetree/bindings/pinctrl/atmel,at91-pio4-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/atmel,at91-pio4-pinctrl.txt @@ -35,9 +35,11 @@ ioset settings. Use the macros from boot/dts/-pinfunc.h file to get the right representation of the pin. Optional properties: -- GENERIC_PINCONFIG: generic pinconfig options to use, bias-disable, -bias-pull-down, bias-pull-up, drive-open-drain, input-schmitt-enable, -input-debounce, output-low, output-high. +- GENERIC_PINCONFIG: generic pinconfig options to use: + - bias-disable, bias-pull-down, bias-pull-up, drive-open-drain, + input-schmitt-enable, input-debounce, output-low, output-high. + - for microchip,sama7g5-pinctrl only: + - slew-rate: 0 - disabled, 1 - enabled (default) - atmel,drive-strength: 0 or 1 for low drive, 2 for medium drive and 3 for high drive. The default value is low drive. From patchwork Mon Jan 25 10:19:13 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 1431900 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=microchip.com header.i=@microchip.com header.a=rsa-sha256 header.s=mchp header.b=wvRJt7Cy; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4DQHsj0MXHz9sT6 for ; Wed, 27 Jan 2021 07:10:33 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730438AbhAZFZ7 (ORCPT ); Tue, 26 Jan 2021 00:25:59 -0500 Received: from esa.microchip.iphmx.com ([68.232.153.233]:63942 "EHLO esa.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727302AbhAYKYN (ORCPT ); Mon, 25 Jan 2021 05:24:13 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1611570253; x=1643106253; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=dx9KjAGiGtK/LMcFDbDzEuO+ImpTBzyX/HPCxMAtXdo=; b=wvRJt7CyNoTCJmc4fUm27aCoBp0gKpOjMe1ETiDGGMqv0B7Pr2s5wDOK 0ak/iuerWmAyY43hqDVVRtYrD9PBG2tL7ayJZx4bxhbcTViuPf9csrqNY MyFEVmlyBzk2ZI0e3Ig9F8CGHlWvJiAeembdoRZyooaJLBdN9OFz03Ohz cXVLLzreQFakroMUAz+3IthtDYkmJ7zTa62yann3gdHr5flntE6y7jKL3 gFnAjzC4ePXGfL8Y4Ll65t+y4ujjfCjP5GTqoBJdbq3nik5hyhjG1HC01 NSRGcc+xTn/g+wo6wnvAnydCInnBt+yiPuTY/1KjTxZxEJOzX2wm2IlH0 w==; IronPort-SDR: Q1u/PcW2f8t1diKTRJfilnQjlUZ7OrIaBOu+DPRh1CIiCbILfkZptyhNoounBw86tzocgTVYbE HhHHdZryjhX8hBJpfGBXu/e+HIK1VWqcMup0UGuvL3wTyh/DvHq3uFt/+AaoywU45CSlxVazRU 4IVGNBxX0zbds1yUEU1shZR38gZOxXlEs74mWj8CSTZY8YxrTOkX6BcS2g5KmJwVwaE6K6nCn5 Y4rRRhpVAIdZTim7GAEnVdoAVA5FV6U+D3WMGNCv55EcpAnM9B8qbrnElLMiKXiP4oxP7AOdKf DhI= X-IronPort-AV: E=Sophos;i="5.79,373,1602572400"; d="scan'208";a="107162041" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa3.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 25 Jan 2021 03:19:29 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1979.3; Mon, 25 Jan 2021 03:19:29 -0700 Received: from m18063-ThinkPad-T460p.microchip.com (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.1979.3 via Frontend Transport; Mon, 25 Jan 2021 03:19:26 -0700 From: Claudiu Beznea To: , , , , CC: , , , , Claudiu Beznea Subject: [PATCH 2/3] pinctrl: at91-pio4: add support for slew-rate Date: Mon, 25 Jan 2021 12:19:13 +0200 Message-ID: <1611569954-23279-3-git-send-email-claudiu.beznea@microchip.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1611569954-23279-1-git-send-email-claudiu.beznea@microchip.com> References: <1611569954-23279-1-git-send-email-claudiu.beznea@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org SAMA7G5 supports slew rate configuration. Adapt the driver for this. For switching frequencies lower than 50MHz the slew rate needs to be enabled. Since most of the pins on SAMA7G5 fall into this category enabled the slew rate by default. Signed-off-by: Claudiu Beznea Acked-by: Ludovic Desroches --- drivers/pinctrl/pinctrl-at91-pio4.c | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/drivers/pinctrl/pinctrl-at91-pio4.c b/drivers/pinctrl/pinctrl-at91-pio4.c index d267367d94b9..c59ab0bfb945 100644 --- a/drivers/pinctrl/pinctrl-at91-pio4.c +++ b/drivers/pinctrl/pinctrl-at91-pio4.c @@ -36,6 +36,7 @@ #define ATMEL_PIO_DIR_MASK BIT(8) #define ATMEL_PIO_PUEN_MASK BIT(9) #define ATMEL_PIO_PDEN_MASK BIT(10) +#define ATMEL_PIO_SR_MASK BIT(11) #define ATMEL_PIO_IFEN_MASK BIT(12) #define ATMEL_PIO_IFSCEN_MASK BIT(13) #define ATMEL_PIO_OPD_MASK BIT(14) @@ -76,10 +77,12 @@ * @nbanks: number of PIO banks * @last_bank_count: number of lines in the last bank (can be less than * the rest of the banks). + * @sr: slew rate support */ struct atmel_pioctrl_data { unsigned nbanks; unsigned last_bank_count; + unsigned int sr; }; struct atmel_group { @@ -117,6 +120,7 @@ struct atmel_pin { * @pm_suspend_backup: backup/restore register values on suspend/resume * @dev: device entry for the Atmel PIO controller. * @node: node of the Atmel PIO controller. + * @sr: slew rate support */ struct atmel_pioctrl { void __iomem *reg_base; @@ -138,6 +142,7 @@ struct atmel_pioctrl { } *pm_suspend_backup; struct device *dev; struct device_node *node; + unsigned int sr; }; static const char * const atmel_functions[] = { @@ -760,6 +765,13 @@ static int atmel_conf_pin_config_group_get(struct pinctrl_dev *pctldev, return -EINVAL; arg = 1; break; + case PIN_CONFIG_SLEW_RATE: + if (!atmel_pioctrl->sr) + return -EOPNOTSUPP; + if (!(res & ATMEL_PIO_SR_MASK)) + return -EINVAL; + arg = 1; + break; case ATMEL_PIN_CONFIG_DRIVE_STRENGTH: if (!(res & ATMEL_PIO_DRVSTR_MASK)) return -EINVAL; @@ -793,6 +805,10 @@ static int atmel_conf_pin_config_group_set(struct pinctrl_dev *pctldev, dev_dbg(pctldev->dev, "%s: pin=%u, config=0x%lx\n", __func__, pin_id, configs[i]); + /* Keep slew rate enabled by default. */ + if (atmel_pioctrl->sr) + conf |= ATMEL_PIO_SR_MASK; + switch (param) { case PIN_CONFIG_BIAS_DISABLE: conf &= (~ATMEL_PIO_PUEN_MASK); @@ -850,6 +866,13 @@ static int atmel_conf_pin_config_group_set(struct pinctrl_dev *pctldev, ATMEL_PIO_SODR); } break; + case PIN_CONFIG_SLEW_RATE: + if (!atmel_pioctrl->sr) + break; + /* And remove it if explicitly requested. */ + if (arg == 0) + conf &= ~ATMEL_PIO_SR_MASK; + break; case ATMEL_PIN_CONFIG_DRIVE_STRENGTH: switch (arg) { case ATMEL_PIO_DRVSTR_LO: @@ -901,6 +924,8 @@ static void atmel_conf_pin_config_dbg_show(struct pinctrl_dev *pctldev, seq_printf(s, "%s ", "open-drain"); if (conf & ATMEL_PIO_SCHMITT_MASK) seq_printf(s, "%s ", "schmitt"); + if (atmel_pioctrl->sr && (conf & ATMEL_PIO_SR_MASK)) + seq_printf(s, "%s ", "slew-rate"); if (conf & ATMEL_PIO_DRVSTR_MASK) { switch ((conf & ATMEL_PIO_DRVSTR_MASK) >> ATMEL_PIO_DRVSTR_OFFSET) { case ATMEL_PIO_DRVSTR_ME: @@ -994,6 +1019,7 @@ static const struct atmel_pioctrl_data atmel_sama5d2_pioctrl_data = { static const struct atmel_pioctrl_data microchip_sama7g5_pioctrl_data = { .nbanks = 5, .last_bank_count = 8, /* sama7g5 has only PE0 to PE7 */ + .sr = 1, }; static const struct of_device_id atmel_pctrl_of_match[] = { @@ -1039,6 +1065,7 @@ static int atmel_pinctrl_probe(struct platform_device *pdev) atmel_pioctrl->npins -= ATMEL_PIO_NPINS_PER_BANK; atmel_pioctrl->npins += atmel_pioctrl_data->last_bank_count; } + atmel_pioctrl->sr = atmel_pioctrl_data->sr; atmel_pioctrl->reg_base = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(atmel_pioctrl->reg_base)) From patchwork Mon Jan 25 10:19:14 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 1431470 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=microchip.com header.i=@microchip.com header.a=rsa-sha256 header.s=mchp header.b=WsUg71in; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4DPsFj2x5dz9sVw for ; Tue, 26 Jan 2021 14:11:21 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727241AbhAYKXB (ORCPT ); Mon, 25 Jan 2021 05:23:01 -0500 Received: from esa.microchip.iphmx.com ([68.232.154.123]:58955 "EHLO esa.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727485AbhAYKWZ (ORCPT ); Mon, 25 Jan 2021 05:22:25 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1611570144; x=1643106144; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=kkT0NZx3YoFEjlue/xzoaJqbpzoBMo3HlBOmQaSEfDA=; b=WsUg71inPlf/O/9vNz8Uj9gOykOkStLA5XhB5TsWZKn/OEWkhGXON3+a pp1xJKWfyaNV+uNzRkLQeiy6RkGcQF1TjybmmQnSyVLnJzOH0/H2+DqMR 7Ri8YThPevtUm6lT2/IqwxFSBmzdfJpUApc240/k/SneabtK0vbQMOmx8 O5MM4W+zx2xcmV1BaSacJm6WECtQ15GDK6D7AbDGJy930hTZJgwDI1Iis kfWe20+rvmgwmPPM38my3ag8x7kl1Aew2Q/lxvpJPnFgephDSCR5T32fM DceyZKhr6tl8DoiGju/6786RAEkF2/w9amKTVmCdHCrdzExUP5D9UFZ+K Q==; IronPort-SDR: Cl8CGlCfq4URIJjCJ4pIX8APq72ffop3a0Z5pS3y9tLhG5c7fJPvdu3VaUSEZT4nhYZvWfGkDc JnMblR2K+bqnl5MWpBhcqSfQhDDbJTOhoFB2bXsYyiaUstl33qZWlcYaY9+Cu506OgyufUsRKP 85jDhTfc9vSjIRv6OkHuOCDURcY4UIV2+Efzf4ELdTZmu9xvUKVsTWvMSwtCUZWQlXcl52Xu7l 4okiKGdRURrttt1TUQ4lnq4ur9Rq7k5d4vMwqz6IXHoFJaJd8rOZuGFErddeVR+0oDNK01ly7y sOE= X-IronPort-AV: E=Sophos;i="5.79,373,1602572400"; d="scan'208";a="41611506" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa6.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 25 Jan 2021 03:19:34 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1979.3; Mon, 25 Jan 2021 03:19:34 -0700 Received: from m18063-ThinkPad-T460p.microchip.com (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.1979.3 via Frontend Transport; Mon, 25 Jan 2021 03:19:30 -0700 From: Claudiu Beznea To: , , , , CC: , , , , Claudiu Beznea Subject: [PATCH 3/3] pinctrl: at91-pio4: fix "Prefer 'unsigned int' to bare use of 'unsigned'" Date: Mon, 25 Jan 2021 12:19:14 +0200 Message-ID: <1611569954-23279-4-git-send-email-claudiu.beznea@microchip.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1611569954-23279-1-git-send-email-claudiu.beznea@microchip.com> References: <1611569954-23279-1-git-send-email-claudiu.beznea@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Fix "Prefer 'unsigned int' to bare use of 'unsigned'" checkpatch.pl warning. Signed-off-by: Claudiu Beznea Acked-by: Ludovic Desroches --- drivers/pinctrl/pinctrl-at91-pio4.c | 110 +++++++++++++++++++----------------- 1 file changed, 57 insertions(+), 53 deletions(-) diff --git a/drivers/pinctrl/pinctrl-at91-pio4.c b/drivers/pinctrl/pinctrl-at91-pio4.c index c59ab0bfb945..0206cbfcbebb 100644 --- a/drivers/pinctrl/pinctrl-at91-pio4.c +++ b/drivers/pinctrl/pinctrl-at91-pio4.c @@ -80,8 +80,8 @@ * @sr: slew rate support */ struct atmel_pioctrl_data { - unsigned nbanks; - unsigned last_bank_count; + unsigned int nbanks; + unsigned int last_bank_count; unsigned int sr; }; @@ -91,11 +91,11 @@ struct atmel_group { }; struct atmel_pin { - unsigned pin_id; - unsigned mux; - unsigned ioset; - unsigned bank; - unsigned line; + unsigned int pin_id; + unsigned int mux; + unsigned int ioset; + unsigned int bank; + unsigned int line; const char *device; }; @@ -125,16 +125,16 @@ struct atmel_pin { struct atmel_pioctrl { void __iomem *reg_base; struct clk *clk; - unsigned nbanks; + unsigned int nbanks; struct pinctrl_dev *pinctrl_dev; struct atmel_group *groups; const char * const *group_names; struct atmel_pin **pins; - unsigned npins; + unsigned int npins; struct gpio_chip *gpio_chip; struct irq_domain *irq_domain; int *irqs; - unsigned *pm_wakeup_sources; + unsigned int *pm_wakeup_sources; struct { u32 imr; u32 odsr; @@ -177,11 +177,11 @@ static void atmel_gpio_irq_ack(struct irq_data *d) */ } -static int atmel_gpio_irq_set_type(struct irq_data *d, unsigned type) +static int atmel_gpio_irq_set_type(struct irq_data *d, unsigned int type) { struct atmel_pioctrl *atmel_pioctrl = irq_data_get_irq_chip_data(d); struct atmel_pin *pin = atmel_pioctrl->pins[d->hwirq]; - unsigned reg; + unsigned int reg; atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_MSKR, BIT(pin->line)); @@ -268,7 +268,7 @@ static struct irq_chip atmel_gpio_irq_chip = { .irq_set_wake = atmel_gpio_irq_set_wake, }; -static int atmel_gpio_to_irq(struct gpio_chip *chip, unsigned offset) +static int atmel_gpio_to_irq(struct gpio_chip *chip, unsigned int offset) { struct atmel_pioctrl *atmel_pioctrl = gpiochip_get_data(chip); @@ -316,11 +316,12 @@ static void atmel_gpio_irq_handler(struct irq_desc *desc) chained_irq_exit(chip, desc); } -static int atmel_gpio_direction_input(struct gpio_chip *chip, unsigned offset) +static int atmel_gpio_direction_input(struct gpio_chip *chip, + unsigned int offset) { struct atmel_pioctrl *atmel_pioctrl = gpiochip_get_data(chip); struct atmel_pin *pin = atmel_pioctrl->pins[offset]; - unsigned reg; + unsigned int reg; atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_MSKR, BIT(pin->line)); @@ -331,11 +332,11 @@ static int atmel_gpio_direction_input(struct gpio_chip *chip, unsigned offset) return 0; } -static int atmel_gpio_get(struct gpio_chip *chip, unsigned offset) +static int atmel_gpio_get(struct gpio_chip *chip, unsigned int offset) { struct atmel_pioctrl *atmel_pioctrl = gpiochip_get_data(chip); struct atmel_pin *pin = atmel_pioctrl->pins[offset]; - unsigned reg; + unsigned int reg; reg = atmel_gpio_read(atmel_pioctrl, pin->bank, ATMEL_PIO_PDSR); @@ -369,12 +370,13 @@ static int atmel_gpio_get_multiple(struct gpio_chip *chip, unsigned long *mask, return 0; } -static int atmel_gpio_direction_output(struct gpio_chip *chip, unsigned offset, +static int atmel_gpio_direction_output(struct gpio_chip *chip, + unsigned int offset, int value) { struct atmel_pioctrl *atmel_pioctrl = gpiochip_get_data(chip); struct atmel_pin *pin = atmel_pioctrl->pins[offset]; - unsigned reg; + unsigned int reg; atmel_gpio_write(atmel_pioctrl, pin->bank, value ? ATMEL_PIO_SODR : ATMEL_PIO_CODR, @@ -389,7 +391,7 @@ static int atmel_gpio_direction_output(struct gpio_chip *chip, unsigned offset, return 0; } -static void atmel_gpio_set(struct gpio_chip *chip, unsigned offset, int val) +static void atmel_gpio_set(struct gpio_chip *chip, unsigned int offset, int val) { struct atmel_pioctrl *atmel_pioctrl = gpiochip_get_data(chip); struct atmel_pin *pin = atmel_pioctrl->pins[offset]; @@ -445,11 +447,11 @@ static struct gpio_chip atmel_gpio_chip = { /* --- PINCTRL --- */ static unsigned int atmel_pin_config_read(struct pinctrl_dev *pctldev, - unsigned pin_id) + unsigned int pin_id) { struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev); - unsigned bank = atmel_pioctrl->pins[pin_id]->bank; - unsigned line = atmel_pioctrl->pins[pin_id]->line; + unsigned int bank = atmel_pioctrl->pins[pin_id]->bank; + unsigned int line = atmel_pioctrl->pins[pin_id]->line; void __iomem *addr = atmel_pioctrl->reg_base + bank * ATMEL_PIO_BANK_OFFSET; @@ -461,11 +463,11 @@ static unsigned int atmel_pin_config_read(struct pinctrl_dev *pctldev, } static void atmel_pin_config_write(struct pinctrl_dev *pctldev, - unsigned pin_id, u32 conf) + unsigned int pin_id, u32 conf) { struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev); - unsigned bank = atmel_pioctrl->pins[pin_id]->bank; - unsigned line = atmel_pioctrl->pins[pin_id]->line; + unsigned int bank = atmel_pioctrl->pins[pin_id]->bank; + unsigned int line = atmel_pioctrl->pins[pin_id]->line; void __iomem *addr = atmel_pioctrl->reg_base + bank * ATMEL_PIO_BANK_OFFSET; @@ -483,7 +485,7 @@ static int atmel_pctl_get_groups_count(struct pinctrl_dev *pctldev) } static const char *atmel_pctl_get_group_name(struct pinctrl_dev *pctldev, - unsigned selector) + unsigned int selector) { struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev); @@ -491,19 +493,20 @@ static const char *atmel_pctl_get_group_name(struct pinctrl_dev *pctldev, } static int atmel_pctl_get_group_pins(struct pinctrl_dev *pctldev, - unsigned selector, const unsigned **pins, - unsigned *num_pins) + unsigned int selector, + const unsigned int **pins, + unsigned int *num_pins) { struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev); - *pins = (unsigned *)&atmel_pioctrl->groups[selector].pin; + *pins = (unsigned int *)&atmel_pioctrl->groups[selector].pin; *num_pins = 1; return 0; } static struct atmel_group * -atmel_pctl_find_group_by_pin(struct pinctrl_dev *pctldev, unsigned pin) +atmel_pctl_find_group_by_pin(struct pinctrl_dev *pctldev, unsigned int pin) { struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev); int i; @@ -524,7 +527,7 @@ static int atmel_pctl_xlate_pinfunc(struct pinctrl_dev *pctldev, const char **func_name) { struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev); - unsigned pin_id, func_id; + unsigned int pin_id, func_id; struct atmel_group *grp; pin_id = ATMEL_GET_PIN_NO(pinfunc); @@ -554,10 +557,10 @@ static int atmel_pctl_xlate_pinfunc(struct pinctrl_dev *pctldev, static int atmel_pctl_dt_subnode_to_map(struct pinctrl_dev *pctldev, struct device_node *np, struct pinctrl_map **map, - unsigned *reserved_maps, - unsigned *num_maps) + unsigned int *reserved_maps, + unsigned int *num_maps) { - unsigned num_pins, num_configs, reserve; + unsigned int num_pins, num_configs, reserve; unsigned long *configs; struct property *pins; u32 pinfunc; @@ -628,10 +631,10 @@ static int atmel_pctl_dt_subnode_to_map(struct pinctrl_dev *pctldev, static int atmel_pctl_dt_node_to_map(struct pinctrl_dev *pctldev, struct device_node *np_config, struct pinctrl_map **map, - unsigned *num_maps) + unsigned int *num_maps) { struct device_node *np; - unsigned reserved_maps; + unsigned int reserved_maps; int ret; *map = NULL; @@ -679,13 +682,13 @@ static int atmel_pmx_get_functions_count(struct pinctrl_dev *pctldev) } static const char *atmel_pmx_get_function_name(struct pinctrl_dev *pctldev, - unsigned selector) + unsigned int selector) { return atmel_functions[selector]; } static int atmel_pmx_get_function_groups(struct pinctrl_dev *pctldev, - unsigned selector, + unsigned int selector, const char * const **groups, unsigned * const num_groups) { @@ -698,11 +701,11 @@ static int atmel_pmx_get_function_groups(struct pinctrl_dev *pctldev, } static int atmel_pmx_set_mux(struct pinctrl_dev *pctldev, - unsigned function, - unsigned group) + unsigned int function, + unsigned int group) { struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev); - unsigned pin; + unsigned int pin; u32 conf; dev_dbg(pctldev->dev, "enable function %s group %s\n", @@ -726,13 +729,13 @@ static const struct pinmux_ops atmel_pmxops = { }; static int atmel_conf_pin_config_group_get(struct pinctrl_dev *pctldev, - unsigned group, + unsigned int group, unsigned long *config) { struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev); - unsigned param = pinconf_to_config_param(*config), arg = 0; + unsigned int param = pinconf_to_config_param(*config), arg = 0; struct atmel_group *grp = atmel_pioctrl->groups + group; - unsigned pin_id = grp->pin; + unsigned int pin_id = grp->pin; u32 res; res = atmel_pin_config_read(pctldev, pin_id); @@ -786,21 +789,21 @@ static int atmel_conf_pin_config_group_get(struct pinctrl_dev *pctldev, } static int atmel_conf_pin_config_group_set(struct pinctrl_dev *pctldev, - unsigned group, + unsigned int group, unsigned long *configs, - unsigned num_configs) + unsigned int num_configs) { struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev); struct atmel_group *grp = atmel_pioctrl->groups + group; - unsigned bank, pin, pin_id = grp->pin; + unsigned int bank, pin, pin_id = grp->pin; u32 mask, conf = 0; int i; conf = atmel_pin_config_read(pctldev, pin_id); for (i = 0; i < num_configs; i++) { - unsigned param = pinconf_to_config_param(configs[i]); - unsigned arg = pinconf_to_config_argument(configs[i]); + unsigned int param = pinconf_to_config_param(configs[i]); + unsigned int arg = pinconf_to_config_argument(configs[i]); dev_dbg(pctldev->dev, "%s: pin=%u, config=0x%lx\n", __func__, pin_id, configs[i]); @@ -900,7 +903,8 @@ static int atmel_conf_pin_config_group_set(struct pinctrl_dev *pctldev, } static void atmel_conf_pin_config_dbg_show(struct pinctrl_dev *pctldev, - struct seq_file *s, unsigned pin_id) + struct seq_file *s, + unsigned int pin_id) { struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev); u32 conf; @@ -1108,8 +1112,8 @@ static int atmel_pinctrl_probe(struct platform_device *pdev) return -ENOMEM; for (i = 0 ; i < atmel_pioctrl->npins; i++) { struct atmel_group *group = atmel_pioctrl->groups + i; - unsigned bank = ATMEL_PIO_BANK(i); - unsigned line = ATMEL_PIO_LINE(i); + unsigned int bank = ATMEL_PIO_BANK(i); + unsigned int line = ATMEL_PIO_LINE(i); atmel_pioctrl->pins[i] = devm_kzalloc(dev, sizeof(**atmel_pioctrl->pins), GFP_KERNEL);