From patchwork Sat Jan 23 18:27:01 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dario Binacchi X-Patchwork-Id: 1430801 X-Patchwork-Delegate: lokeshvutla@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=libero.it header.i=@libero.it header.a=rsa-sha256 header.s=s2014 header.b=YSsoz1nf; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4DNPkV3vTDz9sVm for ; Sun, 24 Jan 2021 05:27:46 +1100 (AEDT) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 3276382A08; Sat, 23 Jan 2021 19:27:40 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=quarantine dis=none) header.from=libero.it Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=libero.it header.i=@libero.it header.b="YSsoz1nf"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id D45AF82A28; Sat, 23 Jan 2021 19:27:27 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=0.5 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FORGED_SPF_HELO,FREEMAIL_FROM, RCVD_IN_DNSWL_NONE,RCVD_IN_SORBS_WEB,SPF_HELO_PASS autolearn=no autolearn_force=no version=3.4.2 Received: from libero.it (smtp-17.italiaonline.it [213.209.10.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 144FC829E6 for ; Sat, 23 Jan 2021 19:27:24 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=quarantine dis=none) header.from=libero.it Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=dariobin@libero.it Received: from passgat-Modern-14-A10M.homenet.telecomitalia.it ([87.20.116.197]) by smtp-17.iol.local with ESMTPA id 3NczlVbAHbMHl3Nd5ljPVm; Sat, 23 Jan 2021 19:27:23 +0100 x-libjamoibt: 1601 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=libero.it; s=s2014; t=1611426443; bh=VC6/Ke2B0dWsbAKspdlCON8rXtX1DriqWS299ydMFwI=; h=From; b=YSsoz1nfsJ4d+i3BYS01u+B/TBa/UYONM3MtttYoHA97+zxP9n3v8YcuCC0mLbkhB LMns7cmrocnZ35DLIeQwOAGsaCMfHwkJQ8yhjBftqCgvmJ8NnUQ9KqDYTq04XBTVlW cGu2YCJAa0cp5PLqfV/YF8mQzpKVn1V2PQ/s/q5R7bULhMXkDeauXuFaIRJFWSXaVm e9QHbwai9JjzoR7whouFe868+WnveRi8xKfYEjazTpIgs22A+NBJJKwDRNXCJCuNrR nhKqyRyTTfv7xa4Day4EvMTeMNe7/z7F7+heTJE8vI0YNbXZxVB8iwtbzulTqDpP/3 OfkZcmHkCdoRQ== X-CNFS-Analysis: v=2.4 cv=Sb8yytdu c=1 sm=1 tr=0 ts=600c6a8b cx=a_exe a=AVqmXbCQpuNSdJmApS5GbQ==:117 a=AVqmXbCQpuNSdJmApS5GbQ==:17 a=CNNU2WlDxd8r9xRg_hQA:9 a=pHzHmUro8NiASowvMSCR:22 a=6VlIyEUom7LUIeUMNQJH:22 From: Dario Binacchi To: u-boot@lists.denx.de Cc: Lokesh Vutla , Dario Binacchi , Andy Shevchenko , Patrick Delaunay , Simon Glass Subject: [PATCH 01/11] pinctrl: single: fix format of structure documentation Date: Sat, 23 Jan 2021 19:27:01 +0100 Message-Id: <20210123182711.7177-2-dariobin@libero.it> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210123182711.7177-1-dariobin@libero.it> References: <20210123182711.7177-1-dariobin@libero.it> X-CMAE-Envelope: MS4xfFotGkNhqIDA+cdZzBgXhLAhqpM3CUj4ajzxbJuIV72iEXSOCclEoU7TDhWzpm3RTCdiRQV48SLByJEgUzyF+fbHvNEZNYAieXpVcpvQZHS7NDzaD9zM pJtbw525Leyad1A3TXfFrc3OmskHiUKMSjPMndnkWbTDMpyhuR8V211shhvPboMIWKnmvv53Ep3hOfZ9xdr9b/Ul6XC+ksv9tAeLPZ9YDarbc5XZNiuIvqzT Bs1+HOJjqoPZFP4YzMbjhLOFs1WC/+bWq7yve05gPbyXIeUY0L8KiMd01giebkKi+kQvoouFDuSugprkPIIRQHE+HTQi5RYUIoYZUTqLAynr4fVItIyEJG6x GCXYBkqJibliOvfMKNwQ5u4Rf/zj5O3BhAgnqYDyt0HUPBTphFDPJPtwosrc1LvXylAn60J0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.3 at phobos.denx.de X-Virus-Status: Clean U-Boot adopted the kernel-doc annotation style. Signed-off-by: Dario Binacchi Reviewed-by: Simon Glass --- drivers/pinctrl/pinctrl-single.c | 45 +++++++++++++++++++++++++------- 1 file changed, 36 insertions(+), 9 deletions(-) diff --git a/drivers/pinctrl/pinctrl-single.c b/drivers/pinctrl/pinctrl-single.c index 20c3c82aa9..c9a6c272bf 100644 --- a/drivers/pinctrl/pinctrl-single.c +++ b/drivers/pinctrl/pinctrl-single.c @@ -10,23 +10,50 @@ #include #include +/** + * struct single_pdata - platform data + * @base: first configuration register + * @offset: index of last configuration register + * @mask: configuration-value mask bits + * @width: configuration register bit width + * @bits_per_mux: true if one register controls more than one pin + */ struct single_pdata { - fdt_addr_t base; /* first configuration register */ - int offset; /* index of last configuration register */ - u32 mask; /* configuration-value mask bits */ - int width; /* configuration register bit width */ + fdt_addr_t base; + int offset; + u32 mask; + int width; bool bits_per_mux; }; +/** + * struct single_fdt_pin_cfg - pin configuration + * + * This structure is used for the pin configuration parameters in case + * the register controls only one pin. + * + * @reg: configuration register offset + * @val: configuration register value + */ struct single_fdt_pin_cfg { - fdt32_t reg; /* configuration register offset */ - fdt32_t val; /* configuration register value */ + fdt32_t reg; + fdt32_t val; }; +/** + * struct single_fdt_bits_cfg - pin configuration + * + * This structure is used for the pin configuration parameters in case + * the register controls more than one pin. + * + * @reg: configuration register offset + * @val: configuration register value + * @mask: configuration register mask + */ struct single_fdt_bits_cfg { - fdt32_t reg; /* configuration register offset */ - fdt32_t val; /* configuration register value */ - fdt32_t mask; /* configuration register mask */ + fdt32_t reg; + fdt32_t val; + fdt32_t mask; }; /** From patchwork Sat Jan 23 18:27:02 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dario Binacchi X-Patchwork-Id: 1430802 X-Patchwork-Delegate: lokeshvutla@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=libero.it header.i=@libero.it header.a=rsa-sha256 header.s=s2014 header.b=rDthY/GT; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4DNPkh1TsWz9sVm for ; Sun, 24 Jan 2021 05:27:56 +1100 (AEDT) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id F0AA882A15; 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Sat, 23 Jan 2021 19:27:24 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=quarantine dis=none) header.from=libero.it Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=dariobin@libero.it Received: from passgat-Modern-14-A10M.homenet.telecomitalia.it ([87.20.116.197]) by smtp-17.iol.local with ESMTPA id 3NczlVbAHbMHl3Nd5ljPVv; Sat, 23 Jan 2021 19:27:24 +0100 x-libjamoibt: 1601 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=libero.it; s=s2014; t=1611426444; bh=RfGk0B6KGft3VM9M758kXLirtFmI+ixG3UBciSWcMqU=; h=From; b=rDthY/GTTmffLxj28N7pRZUQCbWrAz0p3T3vBvQg5uP76cm255/qPQQQe5uJKfHHe m/1o5yVTVeQYYeCKV+zytUndILYFogw+is74ZNS7XyGD+KpPVQI4QX4bDP6hK19frA kQUOBptL8gHOueiPIxh1uyNPR5b+21Rju9VSV+EypSHPTQHuCj811AVixzOJxCve/X L7YKm0DSDuU1zHBHFW+5W+YVQcCSGicSHFqyCuSgUpVkR6+ZIQfWWwEg3UtXnWfAg4 5G8xbZ+ZeoQekMXTkanfbVM1ubl3qoXapujNqP3MLhaLGoAUfMIMl3v2/L1pBXDNuu qN9RUJNk337EA== X-CNFS-Analysis: v=2.4 cv=Sb8yytdu c=1 sm=1 tr=0 ts=600c6a8c cx=a_exe a=AVqmXbCQpuNSdJmApS5GbQ==:117 a=AVqmXbCQpuNSdJmApS5GbQ==:17 a=G1j61PheYO25n_gpadAA:9 From: Dario Binacchi To: u-boot@lists.denx.de Cc: Lokesh Vutla , Dario Binacchi , Andy Shevchenko , Patrick Delaunay , Pratyush Yadav , Simon Glass Subject: [PATCH 02/11] pinctrl: single: fix the loop counter variable type Date: Sat, 23 Jan 2021 19:27:02 +0100 Message-Id: <20210123182711.7177-3-dariobin@libero.it> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210123182711.7177-1-dariobin@libero.it> References: <20210123182711.7177-1-dariobin@libero.it> X-CMAE-Envelope: MS4xfLPv3b/VN8oM6IctG6QyBtLPWixnBhXtnwL7mPTrfN8BEMDgRAY3asJl2HaCge6Z/OLxEIp5yK3SpiVd4Vmd/hsEJ76qL56B54P2yiEjWsTNUxepQ669 xsndvl21M8DjEcN1ZgaAiZ/LSTp30IZ4VSt1MgJDL8VLhj4qkYikw531jU7byIqzA1u/b2rOXDYVi13R2UfiDR5GLoRoNM9fAdr8P379ZgDwvLr1tKi7rS2T T1fu/5VWkycA8qz/tMTlFpg8TyQ3/w5W/EKqQRkxisKC+3WkoqzyH3ztB39JOIqEvPN+gb73M6FA2jXt3+5xsYp2m/1/yZdKtSvrnZ6FI1ygBo1i4uwOCTMp NZvpfSIr3pPSM2d0MmKXfmUSLG0fZCvVC0D42zkU/3glRlF5coKWFmKcOkXCA+MM63pqCEll6d0nzAxdYqiuVQxZBsRs7g== X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.3 at phobos.denx.de X-Virus-Status: Clean The patch changes the variable 'n' type from phys_addr_t to int. Signed-off-by: Dario Binacchi Reviewed-by: Simon Glass Reviewed-by: Pratyush Yadav --- drivers/pinctrl/pinctrl-single.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/pinctrl/pinctrl-single.c b/drivers/pinctrl/pinctrl-single.c index c9a6c272bf..49ed15211d 100644 --- a/drivers/pinctrl/pinctrl-single.c +++ b/drivers/pinctrl/pinctrl-single.c @@ -75,8 +75,8 @@ static int single_configure_pins(struct udevice *dev, int size) { struct single_pdata *pdata = dev_get_plat(dev); - int count = size / sizeof(struct single_fdt_pin_cfg); - phys_addr_t n, reg; + int n, count = size / sizeof(struct single_fdt_pin_cfg); + phys_addr_t reg; u32 val; for (n = 0; n < count; n++, pins++) { @@ -109,8 +109,8 @@ static int single_configure_bits(struct udevice *dev, int size) { struct single_pdata *pdata = dev_get_plat(dev); - int count = size / sizeof(struct single_fdt_bits_cfg); - phys_addr_t n, reg; + int n, count = size / sizeof(struct single_fdt_bits_cfg); + phys_addr_t reg; u32 val, mask; for (n = 0; n < count; n++, pins++) { From patchwork Sat Jan 23 18:27:03 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dario Binacchi X-Patchwork-Id: 1430803 X-Patchwork-Delegate: lokeshvutla@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=libero.it header.i=@libero.it header.a=rsa-sha256 header.s=s2014 header.b=DzuqjR4l; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4DNPkt6JHBz9sW4 for ; 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Furthermore, the offset variable is displayed with the '%x' format specifier instead of '%pa'. Signed-off-by: Dario Binacchi --- drivers/pinctrl/pinctrl-single.c | 28 ++++++++++++++++------------ 1 file changed, 16 insertions(+), 12 deletions(-) diff --git a/drivers/pinctrl/pinctrl-single.c b/drivers/pinctrl/pinctrl-single.c index 49ed15211d..cec00e289c 100644 --- a/drivers/pinctrl/pinctrl-single.c +++ b/drivers/pinctrl/pinctrl-single.c @@ -77,15 +77,17 @@ static int single_configure_pins(struct udevice *dev, struct single_pdata *pdata = dev_get_plat(dev); int n, count = size / sizeof(struct single_fdt_pin_cfg); phys_addr_t reg; - u32 val; + u32 offset, val; for (n = 0; n < count; n++, pins++) { - reg = fdt32_to_cpu(pins->reg); - if ((reg < 0) || (reg > pdata->offset)) { - dev_dbg(dev, " invalid register offset 0x%pa\n", ®); + offset = fdt32_to_cpu(pins->reg); + if (offset < 0 || offset > pdata->offset) { + dev_dbg(dev, " invalid register offset 0x%x\n", + offset); continue; } - reg += pdata->base; + + reg = pdata->base + offset; val = fdt32_to_cpu(pins->val) & pdata->mask; switch (pdata->width) { case 16: @@ -99,7 +101,7 @@ static int single_configure_pins(struct udevice *dev, pdata->width); continue; } - dev_dbg(dev, " reg/val 0x%pa/0x%08x\n", ®, val); + dev_dbg(dev, " reg/val %pa/0x%08x\n", ®, val); } return 0; } @@ -111,15 +113,17 @@ static int single_configure_bits(struct udevice *dev, struct single_pdata *pdata = dev_get_plat(dev); int n, count = size / sizeof(struct single_fdt_bits_cfg); phys_addr_t reg; - u32 val, mask; + u32 offset, val, mask; for (n = 0; n < count; n++, pins++) { - reg = fdt32_to_cpu(pins->reg); - if ((reg < 0) || (reg > pdata->offset)) { - dev_dbg(dev, " invalid register offset 0x%pa\n", ®); + offset = fdt32_to_cpu(pins->reg); + if (offset < 0 || offset > pdata->offset) { + dev_dbg(dev, " invalid register offset 0x%x\n", + offset); continue; } - reg += pdata->base; + + reg = pdata->base + offset; mask = fdt32_to_cpu(pins->mask); val = fdt32_to_cpu(pins->val) & mask; @@ -136,7 +140,7 @@ static int single_configure_bits(struct udevice *dev, pdata->width); continue; } - dev_dbg(dev, " reg/val 0x%pa/0x%08x\n", ®, val); + dev_dbg(dev, " reg/val %pa/0x%08x\n", ®, val); } return 0; } From patchwork Sat Jan 23 18:27:04 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dario Binacchi X-Patchwork-Id: 1430804 X-Patchwork-Delegate: lokeshvutla@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=libero.it header.i=@libero.it header.a=rsa-sha256 header.s=s2014 header.b=YjQVa/z2; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4DNPl50Z9tz9sVm for ; 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Sat, 23 Jan 2021 19:27:25 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=quarantine dis=none) header.from=libero.it Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=dariobin@libero.it Received: from passgat-Modern-14-A10M.homenet.telecomitalia.it ([87.20.116.197]) by smtp-17.iol.local with ESMTPA id 3NczlVbAHbMHl3Nd6ljPWH; Sat, 23 Jan 2021 19:27:24 +0100 x-libjamoibt: 1601 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=libero.it; s=s2014; t=1611426445; bh=WvluIYUpcoNiZ3p+zCeGk4pE1lykoHYTSKFx6BjKCoA=; h=From; b=YjQVa/z2kY/GKSuYSRo02ZgEoBAzxTswB5pA8bqeZeKAuBD3w0cxMdgm807X1A6WG e8XyIc5rufFurfQL6KzJnciz6xLcPhbbNjzXDe6J+M19NBcTlKCSmBm+cU0Uu9/uCm OUI9GB4BpuSmenSZX/EOFqQStcfS2KowKlFU6A5HWHiBJXJIxlTZnWdhW7BWe915b1 UAuCg3vceWX0nGeVsy5zmkfB4UU2rx57x/A6uN3gEg59XFTIlsZwKxiHjppe6M88dt qS/P+htqiSfLg8PN//ilpgspUuwCOedMx/ElPxXzjbJYVS0btYC1k79M4bCz+JLD22 bA+dKvQbIORDA== X-CNFS-Analysis: v=2.4 cv=Sb8yytdu c=1 sm=1 tr=0 ts=600c6a8d cx=a_exe a=AVqmXbCQpuNSdJmApS5GbQ==:117 a=AVqmXbCQpuNSdJmApS5GbQ==:17 a=9xPrUc1F4XSQNxcLXUMA:9 From: Dario Binacchi To: u-boot@lists.denx.de Cc: Lokesh Vutla , Dario Binacchi , Andy Shevchenko , Patrick Delaunay , Simon Glass Subject: [PATCH 04/11] pinctrl: single: get register area size by device API Date: Sat, 23 Jan 2021 19:27:04 +0100 Message-Id: <20210123182711.7177-5-dariobin@libero.it> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210123182711.7177-1-dariobin@libero.it> References: <20210123182711.7177-1-dariobin@libero.it> X-CMAE-Envelope: MS4xfGw63TT+1kGRhQ7eJcn6nFfndut2VL81Ql3+Sd7FkaNILoVmxp5wM7HV0Ewepq7yrITMFQqgutGvs6L4j6gxmTB5RAHoifO3IhfmjGoilBowT27yQHwt Yxro5ftoM9clLFtVHeH7jRZo/M+S/7N2qGtUHPyCTLRJd6KWYekUuv1LavfHy+pTZKVpDR/hAODd24EkQIoyVs/+P2/gBFtcwZpyfBu/2oI8/vSXlF4EAIuk GW9nINlPj/+dFjpDMMDg+exEQNVIaIGTmY+CYC3XgkChJZhj1HEEDpOWqDAKFMqjJoSvG6R9SPrOWtoPeI7pnJO4+64l0X2WK7C2ZCSGAAPfABMCqOLaJP6t 5uMzGEucEl/gIi30mzpvRGWYP5oCpWeJeigje+ixIlir/GL2bd0m65EktiJeC6+haUP18zKV X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.3 at phobos.denx.de X-Virus-Status: Clean Use dev_read_addr_size to get size of the controller's register area. Signed-off-by: Dario Binacchi --- drivers/pinctrl/pinctrl-single.c | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) diff --git a/drivers/pinctrl/pinctrl-single.c b/drivers/pinctrl/pinctrl-single.c index cec00e289c..c80a42a193 100644 --- a/drivers/pinctrl/pinctrl-single.c +++ b/drivers/pinctrl/pinctrl-single.c @@ -182,17 +182,14 @@ static int single_set_state(struct udevice *dev, static int single_of_to_plat(struct udevice *dev) { fdt_addr_t addr; - u32 of_reg[2]; - int res; + fdt_size_t size; struct single_pdata *pdata = dev_get_plat(dev); pdata->width = dev_read_u32_default(dev, "pinctrl-single,register-width", 0); - res = dev_read_u32_array(dev, "reg", of_reg, 2); - if (res) - return res; - pdata->offset = of_reg[1] - pdata->width / 8; + dev_read_addr_size(dev, "reg", &size); + pdata->offset = size - pdata->width / BITS_PER_BYTE; addr = dev_read_addr(dev); if (addr == FDT_ADDR_T_NONE) { From patchwork Sat Jan 23 18:27:05 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dario Binacchi X-Patchwork-Id: 1430806 X-Patchwork-Delegate: lokeshvutla@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; 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Sat, 23 Jan 2021 19:27:25 +0100 x-libjamoibt: 1601 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=libero.it; s=s2014; t=1611426445; bh=d/a2wunrJqJkYHdA82rkF0PmvbZqcR5cMc11YlwEH7w=; h=From; b=VKXfaIFEX6HT0FlWK8Q4gmLGQ+q1cgF5OGpx2fJhjPHv2LrSiLcdyU8sXIsf71Sf6 u7cPKilxXlNEkdiRG0AMKV3EGsrhHpFJwOr9ifxi4qNzek4BurR+n+n0ZDnTGUPb0p ys62gkRs1Bl7NnpUhYZ48QlLD7cwoDNDSOXJmMffulK+/MXzUoO7yf0o2KNBi8BPwq i9+/RkumeQ/wbFksMw0Y6NrCQh3YLDD3JfIphgpEvzXn5Xti+trmX7+0hK8EsfJfvw ipsGy6aeSxCLgD1VPc+wvAAWl+qOy8yfUKzuXiBPE09xcnY365l8nyfJnkBBAye0ER p3tczOE2yzcwA== X-CNFS-Analysis: v=2.4 cv=Sb8yytdu c=1 sm=1 tr=0 ts=600c6a8d cx=a_exe a=AVqmXbCQpuNSdJmApS5GbQ==:117 a=AVqmXbCQpuNSdJmApS5GbQ==:17 a=tcWXsHbFgC2EDmNsvL4A:9 From: Dario Binacchi To: u-boot@lists.denx.de Cc: Lokesh Vutla , Dario Binacchi , Patrick Delaunay , Pratyush Yadav , Simon Glass Subject: [PATCH 05/11] pinctrl: single: check "register-width" DT property Date: Sat, 23 Jan 2021 19:27:05 +0100 Message-Id: <20210123182711.7177-6-dariobin@libero.it> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210123182711.7177-1-dariobin@libero.it> References: <20210123182711.7177-1-dariobin@libero.it> X-CMAE-Envelope: MS4xfGw63TT+1kGRhQ7eJcn6nFfndut2VL81Ql3+Sd7FkaNILoVmxp5wM7HV0Ewepq7yrITMFQqgutGvs6L4j6gxmTB5RAHoifO3IhfmjGoilBowT27yQHwt Yxro5ftoM9clLFtVHeH7jRZo/M+S/7N2qGtUHPyCTLRJd6KWYekUuv1LavfHy+pTZKVpDR/hAODd24EkQIoyVs/+P2/gBFtcwZpyfBu/2oI8/vSXlF4EAIuk GW9nINlPj/+dFjpDMMDg+YgB8P6kvVXxbxbnBtyJNP2bxM/qlXDKb3rUeUo0/psTdURZS4CFQx5RzuYoJukI96TQt2Sn//WRisXR9kfodIEk15RZmnXC0tuO PO81OC3zmQHwJJmOhaXnSWo/o1soZA== X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.3 at phobos.denx.de X-Virus-Status: Clean In more recent versions of the Linux kernel the driver's probe function returns an error if the "pinctrl-single,register-width" DT property is missing. The lack of this information, in fact, does not allow to know whether to access the registers of the controller at 8, 16 or 32 bits. Signed-off-by: Dario Binacchi Reviewed-by: Simon Glass --- drivers/pinctrl/pinctrl-single.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/drivers/pinctrl/pinctrl-single.c b/drivers/pinctrl/pinctrl-single.c index c80a42a193..8fd3bf66de 100644 --- a/drivers/pinctrl/pinctrl-single.c +++ b/drivers/pinctrl/pinctrl-single.c @@ -22,7 +22,7 @@ struct single_pdata { fdt_addr_t base; int offset; u32 mask; - int width; + u32 width; bool bits_per_mux; }; @@ -184,9 +184,13 @@ static int single_of_to_plat(struct udevice *dev) fdt_addr_t addr; fdt_size_t size; struct single_pdata *pdata = dev_get_plat(dev); + int ret; - pdata->width = - dev_read_u32_default(dev, "pinctrl-single,register-width", 0); + ret = dev_read_u32(dev, "pinctrl-single,register-width", &pdata->width); + if (ret) { + dev_err(dev, "missing register width\n"); + return ret; + } dev_read_addr_size(dev, "reg", &size); pdata->offset = size - pdata->width / BITS_PER_BYTE; From patchwork Sat Jan 23 18:27:06 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dario Binacchi X-Patchwork-Id: 1430805 X-Patchwork-Delegate: lokeshvutla@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=libero.it header.i=@libero.it header.a=rsa-sha256 header.s=s2014 header.b=lgmMjiZC; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4DNPlJ6WGvz9sVm for ; Sun, 24 Jan 2021 05:28:28 +1100 (AEDT) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id CE29682A29; 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Sat, 23 Jan 2021 19:27:26 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=quarantine dis=none) header.from=libero.it Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=dariobin@libero.it Received: from passgat-Modern-14-A10M.homenet.telecomitalia.it ([87.20.116.197]) by smtp-17.iol.local with ESMTPA id 3NczlVbAHbMHl3Nd7ljPWc; Sat, 23 Jan 2021 19:27:25 +0100 x-libjamoibt: 1601 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=libero.it; s=s2014; t=1611426445; bh=ILZAMo7mGBDphT3Wbg5j4sD1eFnytMXM7Edw27avi9s=; h=From; b=lgmMjiZCXsVOL4wBZIodep5o2PNbOVbeGcoFy6g9PppYwTdvX43xOTcRcKkX8JmT/ 5aVCHgnbP6bFtt7B2AbXkzZb4fe0gCRCvl/zyA2iTqnqjCha524ksoycgcm7UfluGW 9Km/ld5mzIPdV1rXvMjsuLaGjn7xFZ4wfNS4GmyCLpOe0IStljrK7GoF5ydNdDbNPR 48UqSlGGxd+Y7c/IQqLfVeC5U7xQm0MeJBAH4Aq9kEF6Br3PM65XQ6AtloqXs7YOXe ulFjKShAcu/bxdxFJ/LS4g1EWbIDmzEyeHcPJkfiK3M+9tkfKR0ceoUMx8ZoBqy69o JfDDtSoe8VbYg== X-CNFS-Analysis: v=2.4 cv=Sb8yytdu c=1 sm=1 tr=0 ts=600c6a8d cx=a_exe a=AVqmXbCQpuNSdJmApS5GbQ==:117 a=AVqmXbCQpuNSdJmApS5GbQ==:17 a=9az6cxj04SzJwZhvl5UA:9 From: Dario Binacchi To: u-boot@lists.denx.de Cc: Lokesh Vutla , Dario Binacchi , Andy Shevchenko , Patrick Delaunay , Pratyush Yadav , Simon Glass Subject: [PATCH 06/11] pinctrl: single: change function mask default value Date: Sat, 23 Jan 2021 19:27:06 +0100 Message-Id: <20210123182711.7177-7-dariobin@libero.it> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210123182711.7177-1-dariobin@libero.it> References: <20210123182711.7177-1-dariobin@libero.it> X-CMAE-Envelope: MS4xfGw63TT+1kGRhQ7eJcn6nFfndut2VL81Ql3+Sd7FkaNILoVmxp5wM7HV0Ewepq7yrITMFQqgutGvs6L4j6gxmTB5RAHoifO3IhfmjGoilBowT27yQHwt Yxro5ftoM9clLFtVHeH7jRZo/M+S/7N2qGtUHPyCTLRJd6KWYekUuv1L40urnJnu4CBsFwCXPDyUziPOJesAf2q+2H0fPlX7DJWeW10HVCpnjhWaDjVRT1A4 DS0nk9qjGt2KJz4b1IsKjpzkxKU177wgGtlvgWIsKiIJVNEWuNPN3nESH97wzdD58mWH7/RIB5wsd/W0a90V7lheLXOO3yH7O4qwFuUbfy/W8IamCZU+5ipk Ywd/jXvaWWEPad0dVxwYTst0meAIiXaoyK5YFZT4pBr+ibnGi8jg2ao4uaGe3f7TrUQABhTMjdRrCZNjkgiLXOuqdmwTOQ== X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.3 at phobos.denx.de X-Virus-Status: Clean The patch is inspired by more recent versions of the Linux driver. Replacing the default value 0xffffffff of the function mask with 0 is certainly more conservative in case the "pinctrl-single,function-mask" DT property is missing. Signed-off-by: Dario Binacchi --- drivers/pinctrl/pinctrl-single.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/pinctrl-single.c b/drivers/pinctrl/pinctrl-single.c index 8fd3bf66de..09bb883041 100644 --- a/drivers/pinctrl/pinctrl-single.c +++ b/drivers/pinctrl/pinctrl-single.c @@ -79,6 +79,10 @@ static int single_configure_pins(struct udevice *dev, phys_addr_t reg; u32 offset, val; + /* If function mask is null, needn't enable it. */ + if (!pdata->mask) + return 0; + for (n = 0; n < count; n++, pins++) { offset = fdt32_to_cpu(pins->reg); if (offset < 0 || offset > pdata->offset) { @@ -202,8 +206,12 @@ static int single_of_to_plat(struct udevice *dev) } pdata->base = addr; - pdata->mask = dev_read_u32_default(dev, "pinctrl-single,function-mask", - 0xffffffff); + ret = dev_read_u32(dev, "pinctrl-single,function-mask", &pdata->mask); + if (ret) { + pdata->mask = 0; + dev_warn(dev, "missing function register mask\n"); + } + pdata->bits_per_mux = dev_read_bool(dev, "pinctrl-single,bit-per-mux"); return 0; From patchwork Sat Jan 23 18:27:07 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dario Binacchi X-Patchwork-Id: 1430807 X-Patchwork-Delegate: lokeshvutla@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=libero.it header.i=@libero.it header.a=rsa-sha256 header.s=s2014 header.b=ojckBQgB; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4DNPll2pnnz9sVm for ; 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Sat, 23 Jan 2021 19:27:26 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=quarantine dis=none) header.from=libero.it Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=dariobin@libero.it Received: from passgat-Modern-14-A10M.homenet.telecomitalia.it ([87.20.116.197]) by smtp-17.iol.local with ESMTPA id 3NczlVbAHbMHl3Nd8ljPWk; Sat, 23 Jan 2021 19:27:26 +0100 x-libjamoibt: 1601 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=libero.it; s=s2014; t=1611426446; bh=esF1Zrk9CLkmKfrCbR0mZBc+6W1i73NyYmp+4i8OtKI=; h=From; b=ojckBQgB6C0ioBenNqFESTH4FhThgRhGvDDU3Wa02d7UBaoE7OfTyAPZof8FAiNGB ruIyvQ9BgIO9xc4u2CzYczT4LIn6II1gNa15zkuCwUO/ErzBqXpCCEnJBmoicFAMO6 TdU5TjBTyT7SYHD5eixb8mkCaV1IHCl5bhB8uHUNWgcB2WK7xnPEJbd9tMiwZqBldt bmDI30Z5mCQb2lIYXDXLjlb9SYjGk/bceWVDoPdY4pVk91on33ptUzcpFKg9TJ5Hpq 0jDgu9C7ZA4F9a02HPHBikpoqQ0GM3DHRfNSJEBNchIPJZJCaAZHZubCFBqpc/7kHn 8mlBIKNCl+/cw== X-CNFS-Analysis: v=2.4 cv=Sb8yytdu c=1 sm=1 tr=0 ts=600c6a8e cx=a_exe a=AVqmXbCQpuNSdJmApS5GbQ==:117 a=AVqmXbCQpuNSdJmApS5GbQ==:17 a=ymIbYRRC1ugnpXGtFfEA:9 From: Dario Binacchi To: u-boot@lists.denx.de Cc: Lokesh Vutla , Dario Binacchi , Andy Shevchenko , Patrick Delaunay , Simon Glass Subject: [PATCH 07/11] pinctrl: single: use function pointer for register access Date: Sat, 23 Jan 2021 19:27:07 +0100 Message-Id: <20210123182711.7177-8-dariobin@libero.it> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210123182711.7177-1-dariobin@libero.it> References: <20210123182711.7177-1-dariobin@libero.it> X-CMAE-Envelope: MS4xfGHz4e6Cbm4/cUdFsQoOq4v5qP6tgYoFjSSyWMh35ih815v5H52DNTcYe9KIcMHMIgDjknwPjZJTLDQrYpD/5Vnx/ZvMydf+A8gdMdoeZz7tripASvSH VZBqbi48JJCTZo+OIN5Qqv4NJwZ29fbZWD58q/C8kXmr7Ol7IRsQjRzCRiM1kBH5dspoZWP279tIn4ztECThCfsp8zUKiPX2JkXxYcneMCu3uYNXpaGCShpI S+1yFmP+dSSDCmZcaP4+vGTkBSenbSQrHtkFS9jm5WCzSlgxEoEcQB4MXcTEcQFSSHeVRMhL/8iV97Cgnlb8vGNiUmfT5v07Ilmg4hwWK3NcyD1EVvnJfGuP VWZxM+muN7+TGGpNhNyexqiZPOrbI70SQWt52S28zp6a1AzMLhQ/AaeqEYYhNzMjUvNVBm9P X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.3 at phobos.denx.de X-Virus-Status: Clean The patch allows you to call the read/write functions set during probing without having to check the type of access at runtime. It also adds functions for 8-bit registers access. Signed-off-by: Dario Binacchi --- drivers/pinctrl/pinctrl-single.c | 98 ++++++++++++++++++++++++-------- 1 file changed, 73 insertions(+), 25 deletions(-) diff --git a/drivers/pinctrl/pinctrl-single.c b/drivers/pinctrl/pinctrl-single.c index 09bb883041..eb69e53096 100644 --- a/drivers/pinctrl/pinctrl-single.c +++ b/drivers/pinctrl/pinctrl-single.c @@ -26,6 +26,16 @@ struct single_pdata { bool bits_per_mux; }; +/** + * struct single_priv - private data + * @read: function to read from a configuration register + * @write: function to write to a configuration register + */ +struct single_priv { + unsigned int (*read)(fdt_addr_t reg); + void (*write)(unsigned int val, fdt_addr_t reg); +}; + /** * struct single_fdt_pin_cfg - pin configuration * @@ -56,6 +66,36 @@ struct single_fdt_bits_cfg { fdt32_t mask; }; +static unsigned int single_readb(fdt_addr_t reg) +{ + return readb(reg); +} + +static unsigned int single_readw(fdt_addr_t reg) +{ + return readw(reg); +} + +static unsigned int single_readl(fdt_addr_t reg) +{ + return readl(reg); +} + +static void single_writeb(unsigned int val, fdt_addr_t reg) +{ + writeb(val, reg); +} + +static void single_writew(unsigned int val, fdt_addr_t reg) +{ + writew(val, reg); +} + +static void single_writel(unsigned int val, fdt_addr_t reg) +{ + writel(val, reg); +} + /** * single_configure_pins() - Configure pins based on FDT data * @@ -75,6 +115,7 @@ static int single_configure_pins(struct udevice *dev, int size) { struct single_pdata *pdata = dev_get_plat(dev); + struct single_priv *priv = dev_get_priv(dev); int n, count = size / sizeof(struct single_fdt_pin_cfg); phys_addr_t reg; u32 offset, val; @@ -93,19 +134,9 @@ static int single_configure_pins(struct udevice *dev, reg = pdata->base + offset; val = fdt32_to_cpu(pins->val) & pdata->mask; - switch (pdata->width) { - case 16: - writew((readw(reg) & ~pdata->mask) | val, reg); - break; - case 32: - writel((readl(reg) & ~pdata->mask) | val, reg); - break; - default: - dev_warn(dev, "unsupported register width %i\n", - pdata->width); - continue; - } + priv->write((priv->read(reg) & ~pdata->mask) | val, reg); dev_dbg(dev, " reg/val %pa/0x%08x\n", ®, val); + } return 0; } @@ -115,6 +146,7 @@ static int single_configure_bits(struct udevice *dev, int size) { struct single_pdata *pdata = dev_get_plat(dev); + struct single_priv *priv = dev_get_priv(dev); int n, count = size / sizeof(struct single_fdt_bits_cfg); phys_addr_t reg; u32 offset, val, mask; @@ -131,19 +163,7 @@ static int single_configure_bits(struct udevice *dev, mask = fdt32_to_cpu(pins->mask); val = fdt32_to_cpu(pins->val) & mask; - - switch (pdata->width) { - case 16: - writew((readw(reg) & ~mask) | val, reg); - break; - case 32: - writel((readl(reg) & ~mask) | val, reg); - break; - default: - dev_warn(dev, "unsupported register width %i\n", - pdata->width); - continue; - } + priv->write((priv->read(reg) & ~mask) | val, reg); dev_dbg(dev, " reg/val %pa/0x%08x\n", ®, val); } return 0; @@ -183,6 +203,32 @@ static int single_set_state(struct udevice *dev, return len; } +static int single_probe(struct udevice *dev) +{ + struct single_pdata *pdata = dev_get_plat(dev); + struct single_priv *priv = dev_get_priv(dev); + + switch (pdata->width) { + case 8: + priv->read = single_readb; + priv->write = single_writeb; + break; + case 16: + priv->read = single_readw; + priv->write = single_writew; + break; + case 32: + priv->read = single_readl; + priv->write = single_writel; + break; + default: + dev_err(dev, "wrong register width\n"); + return -EINVAL; + } + + return 0; +} + static int single_of_to_plat(struct udevice *dev) { fdt_addr_t addr; @@ -232,5 +278,7 @@ U_BOOT_DRIVER(single_pinctrl) = { .of_match = single_pinctrl_match, .ops = &single_pinctrl_ops, .plat_auto = sizeof(struct single_pdata), + .priv_auto = sizeof(struct single_priv), .of_to_plat = single_of_to_plat, + .probe = single_probe, }; From patchwork Sat Jan 23 18:27:08 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dario Binacchi X-Patchwork-Id: 1430809 X-Patchwork-Delegate: lokeshvutla@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; 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spf=pass smtp.mailfrom=dariobin@libero.it Received: from passgat-Modern-14-A10M.homenet.telecomitalia.it ([87.20.116.197]) by smtp-17.iol.local with ESMTPA id 3NczlVbAHbMHl3Nd8ljPWu; Sat, 23 Jan 2021 19:27:27 +0100 x-libjamoibt: 1601 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=libero.it; s=s2014; t=1611426447; bh=gOJ63NuOvYGXGdk6zDT+O1bzwnQ3/8qjAAukS8ITGeQ=; h=From; b=O2uC2tkyH34v0TUzCV4FSr//e2oY1k759AUP9sM260hfJPud2ef16enoZbPeP3RE4 sU0kjHDwaETJuXWi2dLN9kiBCwwXJy0Guc3y7936z7NQipuEVHtS8fUUFXq1J6SNAW l/ym4rgPL12fmyTGuSUmH12VG3JQqzHNmzzYnI7wmuROwDSnh+DojMaj7bH1pPqlOq jtkhSHvevB6EewLHZOfXEujplCZAJeZvyH5PiQ9RaHfRU8y+s74bV1OCfpdX2JC436 r7aLBfPjPHF3zhkuHo7AYUnCg7qkJgOU4J8BmsbeuhdyIj3ETZ6KRqNdlAvwSQhGMw tBJMeMbF6Mf7w== X-CNFS-Analysis: v=2.4 cv=Sb8yytdu c=1 sm=1 tr=0 ts=600c6a8f cx=a_exe a=AVqmXbCQpuNSdJmApS5GbQ==:117 a=AVqmXbCQpuNSdJmApS5GbQ==:17 a=fFcNCuBO12MhUEXPA5YA:9 From: Dario Binacchi To: u-boot@lists.denx.de Cc: Lokesh Vutla , Dario Binacchi , Patrick Delaunay , Pratyush Yadav , Simon Glass Subject: [PATCH 08/11] pinctrl: single: add get_pins_count operation Date: Sat, 23 Jan 2021 19:27:08 +0100 Message-Id: <20210123182711.7177-9-dariobin@libero.it> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210123182711.7177-1-dariobin@libero.it> References: <20210123182711.7177-1-dariobin@libero.it> X-CMAE-Envelope: MS4xfFhf0LWvHjV+wZA3ZC+83PKPirki8FeExzkiEH/OkILq+bKRaP6P6H+xbl+dfLJcTjgVGQmmXaPTp3dlinKFATdb+dK64OPj7VMqeQhtN7CTcwSeN5H8 u6E81WqW2gV8YqxjcpZ0FvsggyovvRLrAJY6lFwYUdQvHN3/rAn0IyB/LoWClgDaCWEf7NZjs+SApIfctPNMejUj5e6SODzn0cmvExxlg3bqCm4NIAdqEwdG 3RgUN3JbIXEJxCsk9iZBbUygfEl9LV/EIA/y+x0GFxSAhLjGFX78V2CuwxY2ikt0Yh7ktQ3R3RHXLPqokLz6ECFLW1+7CetMtsBhYsZfAHqLMbsNL7U1SaVS kjLz8VWoB4OQrxgFS5m05AxdYZMJzA== X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.3 at phobos.denx.de X-Virus-Status: Clean It returns the number of selectable pins. Signed-off-by: Dario Binacchi Reviewed-by: Simon Glass --- drivers/pinctrl/pinctrl-single.c | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/drivers/pinctrl/pinctrl-single.c b/drivers/pinctrl/pinctrl-single.c index eb69e53096..21a3bbaaa7 100644 --- a/drivers/pinctrl/pinctrl-single.c +++ b/drivers/pinctrl/pinctrl-single.c @@ -28,10 +28,14 @@ struct single_pdata { /** * struct single_priv - private data + * @bits_per_pin: number of bits per pin + * @npins: number of selectable pins * @read: function to read from a configuration register * @write: function to write to a configuration register */ struct single_priv { + unsigned int bits_per_pin; + unsigned int npins; unsigned int (*read)(fdt_addr_t reg); void (*write)(unsigned int val, fdt_addr_t reg); }; @@ -203,10 +207,27 @@ static int single_set_state(struct udevice *dev, return len; } +static int single_get_pins_count(struct udevice *dev) +{ + struct single_priv *priv = dev_get_priv(dev); + + return priv->npins; +} + static int single_probe(struct udevice *dev) { struct single_pdata *pdata = dev_get_plat(dev); struct single_priv *priv = dev_get_priv(dev); + u32 size; + + size = pdata->offset + pdata->width / BITS_PER_BYTE; + priv->npins = size / (pdata->width / BITS_PER_BYTE); + if (pdata->bits_per_mux) { + priv->bits_per_pin = fls(pdata->mask); + priv->npins *= (pdata->width / priv->bits_per_pin); + } + + dev_dbg(dev, "%d pins\n", priv->npins); switch (pdata->width) { case 8: @@ -264,6 +285,7 @@ static int single_of_to_plat(struct udevice *dev) } const struct pinctrl_ops single_pinctrl_ops = { + .get_pins_count = single_get_pins_count, .set_state = single_set_state, }; From patchwork Sat Jan 23 18:27:09 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dario Binacchi X-Patchwork-Id: 1430808 X-Patchwork-Delegate: lokeshvutla@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; 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Sat, 23 Jan 2021 19:27:27 +0100 x-libjamoibt: 1601 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=libero.it; s=s2014; t=1611426447; bh=8As9hfJN8QE168rnkJKMCIXtttRT8D2ElPR8uN80jtk=; h=From; b=qSHn+1pPW2HWJY6cnALgHp57OXUBVEGe9cc62luztv4fdNjGKY3N8rnjon+6SFXLy Km2/nlGTfhpE8dP5O5j9VrUcwV+c7Qb9uDMQcd5JPzzMDozWEpSdkDrSwAE6HzVN7x +V6iDRv5o2MZj7l2dAxOcckldIHL2ZEVtFxWJxQUeUegY86HFRuT+n42spcoX7ilRa CEtg8BAWt8Df7jxPGeXjMiSLiYCZadRzzH+0q/CZn379v0n6fTUL+CzQTLxdhugElJ 5R8a8Voa88M3Mc27T75CkWjbjW9tquwk4qdQksuz0EfpbJpuGD1CITCIWmhZGe9prK 6zryi7iE/ULrQ== X-CNFS-Analysis: v=2.4 cv=Sb8yytdu c=1 sm=1 tr=0 ts=600c6a8f cx=a_exe a=AVqmXbCQpuNSdJmApS5GbQ==:117 a=AVqmXbCQpuNSdJmApS5GbQ==:17 a=KdpinQ9mxdWR9Mpdyl0A:9 From: Dario Binacchi To: u-boot@lists.denx.de Cc: Lokesh Vutla , Dario Binacchi , Andy Shevchenko , Patrick Delaunay , Pratyush Yadav , Simon Glass Subject: [PATCH 09/11] pinctrl: single: add get_pin_name operation Date: Sat, 23 Jan 2021 19:27:09 +0100 Message-Id: <20210123182711.7177-10-dariobin@libero.it> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210123182711.7177-1-dariobin@libero.it> References: <20210123182711.7177-1-dariobin@libero.it> X-CMAE-Envelope: MS4xfFhf0LWvHjV+wZA3ZC+83PKPirki8FeExzkiEH/OkILq+bKRaP6P6H+xbl+dfLJcTjgVGQmmXaPTp3dlinKFATdb+dK64OPj7VMqeQhtN7CTcwSeN5H8 u6E81WqW2gV8YqxjcpZ0FvsggyovvRLrAJY6lFwYUdQvHN3/rAn0IyB/8NWh5rvzknLYI5YOGXeHPNVSXhBi7qgNOQimWaMUVLxf+gnDGVR08bmzr7jUqBW+ YgpaRqD9aec3HzwVONuy3U3k98vWoxVmYIsh4DpM3llRCqskIVjmlkYP0GFX1WUiXDhxYNKb25aoN4z3aJH+Z/+dK6vZBdBipvAGJ2A2uah7IFU6Qo/hpBCs lKhBAIyYdmjdeP0X7eclG4HDJLgHYSWoH1MgI1A3Sm/Nl5g+NNlIrWWpFmkKBdVrkBW2cko9DS2WaWmDeowN9cFwMsb68g== X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.3 at phobos.denx.de X-Virus-Status: Clean It returns the name of the requested pin. Signed-off-by: Dario Binacchi Reviewed-by: Simon Glass --- drivers/pinctrl/pinctrl-single.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/drivers/pinctrl/pinctrl-single.c b/drivers/pinctrl/pinctrl-single.c index 21a3bbaaa7..04e2b00f7e 100644 --- a/drivers/pinctrl/pinctrl-single.c +++ b/drivers/pinctrl/pinctrl-single.c @@ -30,12 +30,14 @@ struct single_pdata { * struct single_priv - private data * @bits_per_pin: number of bits per pin * @npins: number of selectable pins + * @pin_name: temporary buffer to store the pin name * @read: function to read from a configuration register * @write: function to write to a configuration register */ struct single_priv { unsigned int bits_per_pin; unsigned int npins; + char pin_name[PINNAME_SIZE]; unsigned int (*read)(fdt_addr_t reg); void (*write)(unsigned int val, fdt_addr_t reg); }; @@ -207,6 +209,19 @@ static int single_set_state(struct udevice *dev, return len; } +static const char *single_get_pin_name(struct udevice *dev, + unsigned int selector) +{ + struct single_priv *priv = dev_get_priv(dev); + + if (selector >= priv->npins) + snprintf(priv->pin_name, PINNAME_SIZE, "Error"); + else + snprintf(priv->pin_name, PINNAME_SIZE, "PIN%u", selector); + + return priv->pin_name; +} + static int single_get_pins_count(struct udevice *dev) { struct single_priv *priv = dev_get_priv(dev); @@ -286,6 +301,7 @@ static int single_of_to_plat(struct udevice *dev) const struct pinctrl_ops single_pinctrl_ops = { .get_pins_count = single_get_pins_count, + .get_pin_name = single_get_pin_name, .set_state = single_set_state, }; From patchwork Sat Jan 23 18:27:10 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dario Binacchi X-Patchwork-Id: 1430810 X-Patchwork-Delegate: lokeshvutla@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; 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Sat, 23 Jan 2021 19:27:28 +0100 x-libjamoibt: 1601 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=libero.it; s=s2014; t=1611426448; bh=q1MoLnNmzBP0DZEHAdkoZVpGkBaBgqswtPDyVqKq6JU=; h=From; b=YtzmtYLGPFhkjCSoT04D9UwTM917uxkkXIx0+fPKbhZ8LPisgB0aN9yHRg+rVhLy6 EwtrG/q7u7ieDbupqSL+eQWUfSdAUJ2LVKBRQPOl/6xS823KNydSAFDKZXvahki2Iu Lyjv/EF3ZplyHbXPnnnB6HM7gS7JW4UecclNPcGJotGkfpvEQMuMRtdqD/H1sRF0ny oQl/MBX8QGRtPyUUZTVQ37q+ENZpQ0QjnJvhZKBF2G5e092m+5Uru1dLvXVWMN/Paa 8DKC0kB09dn34SmYDk0b0kbanv8/7YbHLxDHZCfVuRegc6HesIew9gwzfDIbgr8nR0 j1v8gJT1pfVWQ== X-CNFS-Analysis: v=2.4 cv=Sb8yytdu c=1 sm=1 tr=0 ts=600c6a90 cx=a_exe a=AVqmXbCQpuNSdJmApS5GbQ==:117 a=AVqmXbCQpuNSdJmApS5GbQ==:17 a=QVZZ7hor8bNjwIJKmhkA:9 a=LTHJsFfI4P5cbJCj:21 a=UCNFcMhjJNiVEGkg:21 From: Dario Binacchi To: u-boot@lists.denx.de Cc: Lokesh Vutla , Dario Binacchi , Andy Shevchenko , Patrick Delaunay , Simon Glass Subject: [PATCH 10/11] pinctrl: single: add get_pin_muxing operation Date: Sat, 23 Jan 2021 19:27:10 +0100 Message-Id: <20210123182711.7177-11-dariobin@libero.it> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210123182711.7177-1-dariobin@libero.it> References: <20210123182711.7177-1-dariobin@libero.it> X-CMAE-Envelope: MS4xfGVveZSdhwvmIA4GN3ri/F2l4v95+DoANV8lVjTFl4l7S1UlQjaAECJkR5lO9tG6CyW5HeNv23FdHVYetk3ntKuQgy4ymO56RbMR3JBbPZT2IqAj1ZrG gupRoLcTcjnpZInSfooDwQZxmEM92P3xzMGxHOqDF9JV9MoTo99SRLRua/eM4XPYOMFh4ky7uZVYjYQM+eZP2j6WY33M5RmPVTgwlEZrAZwGStbUp6XNWrAh WbsJoRKKK+vpIzh0ZFp1lNgy7iiGeMlmT7OQPMdaTzjPJLr8zv9hNCsXeKOHlpLM/0rp7qNonGbzeuqL+KF6U6N3ZQm/XH524lNVdpVvZG+vbxdPQlx+2fgM C1B6sCEfRKt8ffYC65fG3A2imUfG36DfSWtPu0/253IBaPyqeQmvqLyLWvmYQJ96ho979rVE X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.3 at phobos.denx.de X-Virus-Status: Clean It allows to display the muxing of a given pin. Inspired by more recent versions of the Linux driver, in addition to the address and the value of the configuration register I added the pin function retrieved from the DT. In doing so, the information displayed does not depend on the platform, being a generic type driver, and it can be useful for debug purposes. Signed-off-by: Dario Binacchi Reviewed-by: Simon Glass --- drivers/pinctrl/pinctrl-single.c | 220 +++++++++++++++++++++++++++++-- 1 file changed, 211 insertions(+), 9 deletions(-) diff --git a/drivers/pinctrl/pinctrl-single.c b/drivers/pinctrl/pinctrl-single.c index 04e2b00f7e..8db0d9e3d1 100644 --- a/drivers/pinctrl/pinctrl-single.c +++ b/drivers/pinctrl/pinctrl-single.c @@ -1,14 +1,18 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) EETS GmbH, 2017, Felix Brack + * Copyright (C) 2021 Dario Binacchi */ #include #include #include +#include #include #include +#include #include +#include /** * struct single_pdata - platform data @@ -26,6 +30,20 @@ struct single_pdata { bool bits_per_mux; }; +/** + * struct single_func - pinctrl function + * @node: list node + * @name: pinctrl function name + * @npins: number of entries in pins array + * @pins: pins array + */ +struct single_func { + struct list_head node; + const char *name; + unsigned int npins; + unsigned int *pins; +}; + /** * struct single_priv - private data * @bits_per_pin: number of bits per pin @@ -38,6 +56,7 @@ struct single_priv { unsigned int bits_per_pin; unsigned int npins; char pin_name[PINNAME_SIZE]; + struct list_head functions; unsigned int (*read)(fdt_addr_t reg); void (*write)(unsigned int val, fdt_addr_t reg); }; @@ -102,6 +121,121 @@ static void single_writel(unsigned int val, fdt_addr_t reg) writel(val, reg); } +/** + * single_get_pin_by_offset() - get a pin based on the register offset + * @dev: single driver instance + * @offset: register offset from the base + */ +static int single_get_pin_by_offset(struct udevice *dev, unsigned int offset) +{ + struct single_pdata *pdata = dev_get_plat(dev); + struct single_priv *priv = dev_get_priv(dev); + + if (offset > pdata->offset) { + dev_err(dev, "mux offset out of range: 0x%x (0x%x)\n", + offset, pdata->offset); + return -EINVAL; + } + + if (pdata->bits_per_mux) + return (offset * BITS_PER_BYTE) / priv->bits_per_pin; + + return offset / (pdata->width / BITS_PER_BYTE); +} + +static int single_get_offset_by_pin(struct udevice *dev, unsigned int pin) +{ + struct single_pdata *pdata = dev_get_plat(dev); + struct single_priv *priv = dev_get_priv(dev); + unsigned int mux_bytes; + + if (pin >= priv->npins) + return -EINVAL; + + mux_bytes = pdata->width / BITS_PER_BYTE; + if (pdata->bits_per_mux) { + int byte_num; + + byte_num = (priv->bits_per_pin * pin) / BITS_PER_BYTE; + return (byte_num / mux_bytes) * mux_bytes; + } + + return pin * mux_bytes; +} + +static const char *single_get_pin_function(struct udevice *dev, + unsigned int pin) +{ + struct single_priv *priv = dev_get_priv(dev); + struct single_func *func; + int i; + + list_for_each_entry(func, &priv->functions, node) { + for (i = 0; i < func->npins; i++) { + if (pin == func->pins[i]) + return func->name; + + if (pin < func->pins[i]) + break; + } + } + + return NULL; +} + +static int single_get_pin_muxing(struct udevice *dev, unsigned int pin, + char *buf, int size) +{ + struct single_pdata *pdata = dev_get_plat(dev); + struct single_priv *priv = dev_get_priv(dev); + fdt_addr_t reg; + const char *fname; + unsigned int val; + int offset, pin_shift = 0; + + offset = single_get_offset_by_pin(dev, pin); + if (offset < 0) + return offset; + + reg = pdata->base + offset; + val = priv->read(reg); + + if (pdata->bits_per_mux) + pin_shift = pin % (pdata->width / priv->bits_per_pin) * + priv->bits_per_pin; + + val &= (pdata->mask << pin_shift); + fname = single_get_pin_function(dev, pin); + snprintf(buf, size, "%pa 0x%08x %s", ®, val, + fname ? fname : "UNCLAIMED"); + return 0; +} + +static struct single_func *single_allocate_function(struct udevice *dev, + unsigned int group_pins) +{ + struct single_func *func; + + func = devm_kmalloc(dev, sizeof(*func), GFP_KERNEL); + if (!func) + return ERR_PTR(-ENOMEM); + + func->pins = devm_kmalloc(dev, sizeof(unsigned int) * group_pins, + GFP_KERNEL); + if (!func->pins) + return ERR_PTR(-ENOMEM); + + return func; +} + +static int single_pin_compare(const void *s1, const void *s2) +{ + int pin1 = *(const unsigned int *)s1; + int pin2 = *(const unsigned int *)s2; + + return pin1 - pin2; +} + /** * single_configure_pins() - Configure pins based on FDT data * @@ -115,14 +249,16 @@ static void single_writel(unsigned int val, fdt_addr_t reg) * @size: Size of the 'pins' array in bytes. * The number of register/value pairs in the 'pins' array therefore * equals to 'size / sizeof(struct single_fdt_pin_cfg)'. + * @fname: Function name. */ static int single_configure_pins(struct udevice *dev, const struct single_fdt_pin_cfg *pins, - int size) + int size, const char *fname) { struct single_pdata *pdata = dev_get_plat(dev); struct single_priv *priv = dev_get_priv(dev); - int n, count = size / sizeof(struct single_fdt_pin_cfg); + int n, pin, count = size / sizeof(struct single_fdt_pin_cfg); + struct single_func *func; phys_addr_t reg; u32 offset, val; @@ -130,33 +266,60 @@ static int single_configure_pins(struct udevice *dev, if (!pdata->mask) return 0; + func = single_allocate_function(dev, count); + if (IS_ERR(func)) + return PTR_ERR(func); + + func->name = fname; + func->npins = 0; for (n = 0; n < count; n++, pins++) { offset = fdt32_to_cpu(pins->reg); if (offset < 0 || offset > pdata->offset) { - dev_dbg(dev, " invalid register offset 0x%x\n", + dev_err(dev, " invalid register offset 0x%x\n", offset); continue; } reg = pdata->base + offset; val = fdt32_to_cpu(pins->val) & pdata->mask; + pin = single_get_pin_by_offset(dev, offset); + if (pin < 0) { + dev_err(dev, " failed to get pin by offset %x\n", + offset); + continue; + } + priv->write((priv->read(reg) & ~pdata->mask) | val, reg); dev_dbg(dev, " reg/val %pa/0x%08x\n", ®, val); - + func->pins[func->npins] = pin; + func->npins++; } + + qsort(func->pins, func->npins, sizeof(func->pins[0]), + single_pin_compare); + list_add(&func->node, &priv->functions); return 0; } static int single_configure_bits(struct udevice *dev, const struct single_fdt_bits_cfg *pins, - int size) + int size, const char *fname) { struct single_pdata *pdata = dev_get_plat(dev); struct single_priv *priv = dev_get_priv(dev); - int n, count = size / sizeof(struct single_fdt_bits_cfg); + int n, pin, count = size / sizeof(struct single_fdt_bits_cfg); + int npins_in_reg, pin_num_from_lsb; + struct single_func *func; phys_addr_t reg; - u32 offset, val, mask; + u32 offset, val, mask, bit_pos, val_pos, mask_pos, submask; + npins_in_reg = pdata->width / priv->bits_per_pin; + func = single_allocate_function(dev, count * npins_in_reg); + if (IS_ERR(func)) + return PTR_ERR(func); + + func->name = fname; + func->npins = 0; for (n = 0; n < count; n++, pins++) { offset = fdt32_to_cpu(pins->reg); if (offset < 0 || offset > pdata->offset) { @@ -167,11 +330,47 @@ static int single_configure_bits(struct udevice *dev, reg = pdata->base + offset; + pin = single_get_pin_by_offset(dev, offset); + if (pin < 0) { + dev_err(dev, " failed to get pin by offset 0x%pa\n", + ®); + continue; + } + mask = fdt32_to_cpu(pins->mask); val = fdt32_to_cpu(pins->val) & mask; priv->write((priv->read(reg) & ~mask) | val, reg); dev_dbg(dev, " reg/val %pa/0x%08x\n", ®, val); + + while (mask) { + bit_pos = __ffs(mask); + pin_num_from_lsb = bit_pos / priv->bits_per_pin; + mask_pos = pdata->mask << bit_pos; + val_pos = val & mask_pos; + submask = mask & mask_pos; + + if ((mask & mask_pos) == 0) { + dev_err(dev, "Invalid mask at 0x%x\n", offset); + break; + } + + mask &= ~mask_pos; + + if (submask != mask_pos) { + dev_warn(dev, + "Invalid submask 0x%x at 0x%x\n", + submask, offset); + continue; + } + + func->pins[func->npins] = pin + pin_num_from_lsb; + func->npins++; + } } + + qsort(func->pins, func->npins, sizeof(func->pins[0]), + single_pin_compare); + list_add(&func->node, &priv->functions); return 0; } static int single_set_state(struct udevice *dev, @@ -189,7 +388,7 @@ static int single_set_state(struct udevice *dev, dev_dbg(dev, " invalid pin configuration in fdt\n"); return -FDT_ERR_BADSTRUCTURE; } - single_configure_pins(dev, prop, len); + single_configure_pins(dev, prop, len, config->name); return 0; } @@ -201,7 +400,7 @@ static int single_set_state(struct udevice *dev, dev_dbg(dev, " invalid bits configuration in fdt\n"); return -FDT_ERR_BADSTRUCTURE; } - single_configure_bits(dev, prop_bits, len); + single_configure_bits(dev, prop_bits, len, config->name); return 0; } @@ -235,6 +434,8 @@ static int single_probe(struct udevice *dev) struct single_priv *priv = dev_get_priv(dev); u32 size; + INIT_LIST_HEAD(&priv->functions); + size = pdata->offset + pdata->width / BITS_PER_BYTE; priv->npins = size / (pdata->width / BITS_PER_BYTE); if (pdata->bits_per_mux) { @@ -303,6 +504,7 @@ const struct pinctrl_ops single_pinctrl_ops = { .get_pins_count = single_get_pins_count, .get_pin_name = single_get_pin_name, .set_state = single_set_state, + .get_pin_muxing = single_get_pin_muxing, }; static const struct udevice_id single_pinctrl_match[] = { From patchwork Sat Jan 23 18:27:11 2021 Content-Type: text/plain; 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Sat, 23 Jan 2021 19:27:28 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=quarantine dis=none) header.from=libero.it Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=dariobin@libero.it Received: from passgat-Modern-14-A10M.homenet.telecomitalia.it ([87.20.116.197]) by smtp-17.iol.local with ESMTPA id 3NczlVbAHbMHl3NdAljPXT; Sat, 23 Jan 2021 19:27:28 +0100 x-libjamoibt: 1601 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=libero.it; s=s2014; t=1611426448; bh=SBwpnGeNvnB7A39EcfWrz9IbVZ9ei+ENLsbG4jRtF/0=; h=From; b=rgZ0nMN8xiiNy9RTIoH3iFzIIDPLQ4q29Wj5hmF5V/IA//CT87iTYObkj8eoRFNTM /N4Evp7wY5eGl2Lu8HJYyvtJRdreMh1GaBQW1YA+H8xcQRT7cHYTMytDsF/JzrEpWg A+s3qVkVGhhmO2fqzbElaODIUoq29mne8j5z/gOCl8WipZozuIYbMd9U4OvUfg1OwZ rgN4f7UpV0JiCl9xUGIE6IDKLoPVB7qGSSokAAX/STVdjBlPu4kLGdpa2X5D9yhT+/ RtdGsuCJ9TGSbLLIEa5Zez1jlTXbaFDlYugiJPATkrVYW57Z8ug4tqC7VhKQrgVvjB tMy75majLJblA== X-CNFS-Analysis: v=2.4 cv=Sb8yytdu c=1 sm=1 tr=0 ts=600c6a90 cx=a_exe a=AVqmXbCQpuNSdJmApS5GbQ==:117 a=AVqmXbCQpuNSdJmApS5GbQ==:17 a=rRxypoqzFcKL7TVElnEA:9 From: Dario Binacchi To: u-boot@lists.denx.de Cc: Lokesh Vutla , Dario Binacchi , Andy Shevchenko , Bin Meng , Jean-Jacques Hiblot , Patrick Delaunay , Philippe Reynes , Sean Anderson , Simon Glass , Wolfgang Wallner Subject: [PATCH 11/11] test: pinmux: add test for 'pinctrl-single' driver Date: Sat, 23 Jan 2021 19:27:11 +0100 Message-Id: <20210123182711.7177-12-dariobin@libero.it> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210123182711.7177-1-dariobin@libero.it> References: <20210123182711.7177-1-dariobin@libero.it> X-CMAE-Envelope: MS4xfGVveZSdhwvmIA4GN3ri/F2l4v95+DoANV8lVjTFl4l7S1UlQjaAECJkR5lO9tG6CyW5HeNv23FdHVYetk3ntKuQgy4ymO56RbMR3JBbPZT2IqAj1ZrG gupRoLcTcjnpZInSfooDwQZxmEM92P3xzMGxHOqDF9JV9MoTo99SRLRu58+3UPEfeMK1sSoX/S6jLoSKCnIthHbgc0PnV5uQGIorPeYmYKDS6THqHE/x6pMf WNAuDDwhqDYz0tsLbZyNGQ1UAoRJnrPp56/xW0TbOKivWFTfes4WlHIXDbhl6m5RSgTobuBSH3MWwXIhyVHwChhxLvuskGGiEc54VLT5bjtY+IbcUoqFVesN DNLQw8HV7D2RCh1rF9iHiR9vHyyh9k5I2w6f4nqgUp3r/L07BLirJs/i4xwVdalYNS75ug/Ywznd517y4bJ/4GaIXLGLMbzj9eGHUTMYVS51JbhTyvuffLMW uH9S+d9/LJS2WcK3b//2hX4UOWbs8+DKYMOmhfuwJ+yNCKvjAxjZvdUDd8FrWCWDxUpr9BzdZrOZb6NHbEyPfnssggEBHCH7B2dLna6SVN2s49lLEKefvo6G zR8= X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.3 at phobos.denx.de X-Virus-Status: Clean The test adds two pinmux nodes to the device tree, one to test when a register changes only one pin's mux (pinctrl-single,pins), and the other to test when more than one pin's mux is changed (pinctrl-single,bits). This required replacing the controller's register access functions when the driver is used on sandbox. Signed-off-by: Dario Binacchi Reviewed-by: Simon Glass --- arch/sandbox/dts/test.dts | 65 +++++++++++++++++++++++++ configs/sandbox_defconfig | 1 + drivers/pinctrl/pinctrl-single.c | 62 +++++++++++++++++++----- test/dm/pinmux.c | 81 ++++++++++++++++++++++++++++++-- 4 files changed, 193 insertions(+), 16 deletions(-) diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts index f86cd0d3b2..e00a163641 100644 --- a/arch/sandbox/dts/test.dts +++ b/arch/sandbox/dts/test.dts @@ -513,6 +513,9 @@ reg = <0 1>; compatible = "sandbox,i2c"; clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinmux_i2c0_pins>; + eeprom@2c { reg = <0x2c>; compatible = "i2c-eeprom"; @@ -592,6 +595,8 @@ lcd { u-boot,dm-pre-reloc; compatible = "sandbox,lcd-sdl"; + pinctrl-names = "default"; + pinctrl-0 = <&pinmux_lcd_pins>; xres = <1366>; yres = <768>; }; @@ -842,6 +847,8 @@ pwm: pwm { compatible = "sandbox,pwm"; #pwm-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinmux_pwm_pins>; }; pwm2 { @@ -913,6 +920,9 @@ reg = <0 1>; compatible = "sandbox,spi"; cs-gpios = <0>, <0>, <&gpio_a 0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinmux_spi0_pins>; + spi.bin@0 { reg = <0>; compatible = "spansion,m25p16", "jedec,spi-nor"; @@ -1002,6 +1012,8 @@ uart0: serial { compatible = "sandbox,serial"; u-boot,dm-pre-reloc; + pinctrl-names = "default"; + pinctrl-0 = <&pinmux_uart0_pins>; }; usb_0: usb@0 { @@ -1268,6 +1280,59 @@ }; }; + pinctrl-single-pins { + compatible = "pinctrl-single"; + reg = <0x0000 0x238>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0x7f>; + + pinmux_pwm_pins: pinmux_pwm_pins { + pinctrl-single,pins = < 0x48 0x06 >; + }; + + pinmux_spi0_pins: pinmux_spi0_pins { + pinctrl-single,pins = < + 0x190 0x0c + 0x194 0x0c + 0x198 0x23 + 0x19c 0x0c + >; + }; + + pinmux_uart0_pins: pinmux_uart0_pins { + pinctrl-single,pins = < + 0x70 0x30 + 0x74 0x00 + >; + }; + }; + + pinctrl-single-bits { + compatible = "pinctrl-single"; + reg = <0x0000 0x50>; + #pinctrl-cells = <2>; + pinctrl-single,bit-per-mux; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0xf>; + + pinmux_i2c0_pins: pinmux_i2c0_pins { + pinctrl-single,bits = < + 0x10 0x00002200 0x0000ff00 + >; + }; + + pinmux_lcd_pins: pinmux_lcd_pins { + pinctrl-single,bits = < + 0x40 0x22222200 0xffffff00 + 0x44 0x22222222 0xffffffff + 0x48 0x00000022 0x000000ff + 0x48 0x02000000 0x0f000000 + 0x4c 0x02000022 0x0f0000ff + >; + }; + }; + hwspinlock@0 { compatible = "sandbox,hwspinlock"; }; diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig index 86dc603667..1c7d49f073 100644 --- a/configs/sandbox_defconfig +++ b/configs/sandbox_defconfig @@ -193,6 +193,7 @@ CONFIG_PHY_SANDBOX=y CONFIG_PINCTRL=y CONFIG_PINCONF=y CONFIG_PINCTRL_SANDBOX=y +CONFIG_PINCTRL_SINGLE=y CONFIG_POWER_DOMAIN=y CONFIG_SANDBOX_POWER_DOMAIN=y CONFIG_DM_PMIC=y diff --git a/drivers/pinctrl/pinctrl-single.c b/drivers/pinctrl/pinctrl-single.c index 8db0d9e3d1..0efffd48e7 100644 --- a/drivers/pinctrl/pinctrl-single.c +++ b/drivers/pinctrl/pinctrl-single.c @@ -53,12 +53,15 @@ struct single_func { * @write: function to write to a configuration register */ struct single_priv { +#if (IS_ENABLED(CONFIG_SANDBOX)) + u32 *sandbox_regs; +#endif unsigned int bits_per_pin; unsigned int npins; char pin_name[PINNAME_SIZE]; struct list_head functions; - unsigned int (*read)(fdt_addr_t reg); - void (*write)(unsigned int val, fdt_addr_t reg); + unsigned int (*read)(struct udevice *dev, fdt_addr_t reg); + void (*write)(struct udevice *dev, unsigned int val, fdt_addr_t reg); }; /** @@ -91,36 +94,64 @@ struct single_fdt_bits_cfg { fdt32_t mask; }; -static unsigned int single_readb(fdt_addr_t reg) +#if (!IS_ENABLED(CONFIG_SANDBOX)) + +static unsigned int single_readb(struct udevice *dev, fdt_addr_t reg) { return readb(reg); } -static unsigned int single_readw(fdt_addr_t reg) +static unsigned int single_readw(struct udevice *dev, fdt_addr_t reg) { return readw(reg); } -static unsigned int single_readl(fdt_addr_t reg) +static unsigned int single_readl(struct udevice *dev, fdt_addr_t reg) { return readl(reg); } -static void single_writeb(unsigned int val, fdt_addr_t reg) +static void single_writeb(struct udevice *dev, unsigned int val, fdt_addr_t reg) { writeb(val, reg); } -static void single_writew(unsigned int val, fdt_addr_t reg) +static void single_writew(struct udevice *dev, unsigned int val, fdt_addr_t reg) { writew(val, reg); } -static void single_writel(unsigned int val, fdt_addr_t reg) +static void single_writel(struct udevice *dev, unsigned int val, fdt_addr_t reg) { writel(val, reg); } +#else /* CONFIG_SANDBOX */ + +#define single_readb single_sandbox_read +#define single_readw single_sandbox_read +#define single_readl single_sandbox_read +#define single_writeb single_sandbox_write +#define single_writew single_sandbox_write +#define single_writel single_sandbox_write + +static unsigned int single_sandbox_read(struct udevice *dev, fdt_addr_t reg) +{ + struct single_priv *priv = dev_get_priv(dev); + + return priv->sandbox_regs[reg]; +} + +static void single_sandbox_write(struct udevice *dev, unsigned int val, + fdt_addr_t reg) +{ + struct single_priv *priv = dev_get_priv(dev); + + priv->sandbox_regs[reg] = val; +} + +#endif /* CONFIG_SANDBOX */ + /** * single_get_pin_by_offset() - get a pin based on the register offset * @dev: single driver instance @@ -198,7 +229,7 @@ static int single_get_pin_muxing(struct udevice *dev, unsigned int pin, return offset; reg = pdata->base + offset; - val = priv->read(reg); + val = priv->read(dev, reg); if (pdata->bits_per_mux) pin_shift = pin % (pdata->width / priv->bits_per_pin) * @@ -289,7 +320,8 @@ static int single_configure_pins(struct udevice *dev, continue; } - priv->write((priv->read(reg) & ~pdata->mask) | val, reg); + priv->write(dev, (priv->read(dev, reg) & ~pdata->mask) | val, + reg); dev_dbg(dev, " reg/val %pa/0x%08x\n", ®, val); func->pins[func->npins] = pin; func->npins++; @@ -339,7 +371,7 @@ static int single_configure_bits(struct udevice *dev, mask = fdt32_to_cpu(pins->mask); val = fdt32_to_cpu(pins->val) & mask; - priv->write((priv->read(reg) & ~mask) | val, reg); + priv->write(dev, (priv->read(dev, reg) & ~mask) | val, reg); dev_dbg(dev, " reg/val %pa/0x%08x\n", ®, val); while (mask) { @@ -437,6 +469,14 @@ static int single_probe(struct udevice *dev) INIT_LIST_HEAD(&priv->functions); size = pdata->offset + pdata->width / BITS_PER_BYTE; + #if (CONFIG_IS_ENABLED(SANDBOX)) + priv->sandbox_regs = + devm_kzalloc(dev, size * sizeof(*priv->sandbox_regs), + GFP_KERNEL); + if (!priv->sandbox_regs) + return -ENOMEM; + #endif + priv->npins = size / (pdata->width / BITS_PER_BYTE); if (pdata->bits_per_mux) { priv->bits_per_pin = fls(pdata->mask); diff --git a/test/dm/pinmux.c b/test/dm/pinmux.c index 047184d4bc..db3f14bf7d 100644 --- a/test/dm/pinmux.c +++ b/test/dm/pinmux.c @@ -9,16 +9,21 @@ #include #include -static int dm_test_pinmux(struct unit_test_state *uts) -{ - char buf[64]; - struct udevice *dev; - +static char buf[64]; #define test_muxing(selector, expected) do { \ ut_assertok(pinctrl_get_pin_muxing(dev, selector, buf, sizeof(buf))); \ ut_asserteq_str(expected, (char *)&buf); \ } while (0) +#define test_name(selector, expected) do { \ + ut_assertok(pinctrl_get_pin_name(dev, selector, buf, sizeof(buf))); \ + ut_asserteq_str(expected, (char *)&buf); \ +} while (0) + +static int dm_test_pinmux(struct unit_test_state *uts) +{ + struct udevice *dev; + ut_assertok(uclass_get_device_by_name(UCLASS_PINCTRL, "pinctrl", &dev)); test_muxing(0, "UART TX."); test_muxing(1, "UART RX."); @@ -55,3 +60,69 @@ static int dm_test_pinmux(struct unit_test_state *uts) return 0; } DM_TEST(dm_test_pinmux, UT_TESTF_SCAN_FDT); + +static int dm_test_pinctrl_single(struct unit_test_state *uts) +{ + struct udevice *dev; + + ut_assertok(uclass_get_device_by_name(UCLASS_PWM, "pwm", &dev)); + ut_assertok(uclass_get_device_by_name(UCLASS_SERIAL, "serial", &dev)); + ut_assertok(uclass_get_device_by_name(UCLASS_SPI, "spi@0", &dev)); + ut_assertok(uclass_get_device_by_name(UCLASS_PINCTRL, "pinctrl-single-pins", &dev)); + ut_asserteq(142, pinctrl_get_pins_count(dev)); + test_name(0, "PIN0"); + test_name(141, "PIN141"); + test_name(142, "Error"); + test_muxing(0, "0x00000000 0x00000000 UNCLAIMED"); + test_muxing(18, "0x00000048 0x00000006 pinmux_pwm_pins"); + test_muxing(28, "0x00000070 0x00000030 pinmux_uart0_pins"); + test_muxing(29, "0x00000074 0x00000000 pinmux_uart0_pins"); + test_muxing(100, "0x00000190 0x0000000c pinmux_spi0_pins"); + test_muxing(101, "0x00000194 0x0000000c pinmux_spi0_pins"); + test_muxing(102, "0x00000198 0x00000023 pinmux_spi0_pins"); + test_muxing(103, "0x0000019c 0x0000000c pinmux_spi0_pins"); + ut_asserteq(-EINVAL, pinctrl_get_pin_muxing(dev, 142, buf, sizeof(buf))); + ut_assertok(uclass_get_device_by_name(UCLASS_I2C, "i2c@0", &dev)); + ut_assertok(uclass_get_device_by_name(UCLASS_VIDEO, "lcd", &dev)); + ut_assertok(uclass_get_device_by_name(UCLASS_PINCTRL, "pinctrl-single-bits", &dev)); + ut_asserteq(160, pinctrl_get_pins_count(dev)); + test_name(0, "PIN0"); + test_name(159, "PIN159"); + test_name(160, "Error"); + test_muxing(0, "0x00000000 0x00000000 UNCLAIMED"); + test_muxing(34, "0x00000010 0x00000200 pinmux_i2c0_pins"); + test_muxing(35, "0x00000010 0x00002000 pinmux_i2c0_pins"); + test_muxing(130, "0x00000040 0x00000200 pinmux_lcd_pins"); + test_muxing(131, "0x00000040 0x00002000 pinmux_lcd_pins"); + test_muxing(132, "0x00000040 0x00020000 pinmux_lcd_pins"); + test_muxing(133, "0x00000040 0x00200000 pinmux_lcd_pins"); + test_muxing(134, "0x00000040 0x02000000 pinmux_lcd_pins"); + test_muxing(135, "0x00000040 0x20000000 pinmux_lcd_pins"); + test_muxing(136, "0x00000044 0x00000002 pinmux_lcd_pins"); + test_muxing(137, "0x00000044 0x00000020 pinmux_lcd_pins"); + test_muxing(138, "0x00000044 0x00000200 pinmux_lcd_pins"); + test_muxing(139, "0x00000044 0x00002000 pinmux_lcd_pins"); + test_muxing(140, "0x00000044 0x00020000 pinmux_lcd_pins"); + test_muxing(141, "0x00000044 0x00200000 pinmux_lcd_pins"); + test_muxing(142, "0x00000044 0x02000000 pinmux_lcd_pins"); + test_muxing(143, "0x00000044 0x20000000 pinmux_lcd_pins"); + test_muxing(144, "0x00000048 0x00000002 pinmux_lcd_pins"); + test_muxing(145, "0x00000048 0x00000020 pinmux_lcd_pins"); + test_muxing(146, "0x00000048 0x00000000 UNCLAIMED"); + test_muxing(147, "0x00000048 0x00000000 UNCLAIMED"); + test_muxing(148, "0x00000048 0x00000000 UNCLAIMED"); + test_muxing(149, "0x00000048 0x00000000 UNCLAIMED"); + test_muxing(150, "0x00000048 0x02000000 pinmux_lcd_pins"); + test_muxing(151, "0x00000048 0x00000000 UNCLAIMED"); + test_muxing(152, "0x0000004c 0x00000002 pinmux_lcd_pins"); + test_muxing(153, "0x0000004c 0x00000020 pinmux_lcd_pins"); + test_muxing(154, "0x0000004c 0x00000000 UNCLAIMED"); + test_muxing(155, "0x0000004c 0x00000000 UNCLAIMED"); + test_muxing(156, "0x0000004c 0x00000000 UNCLAIMED"); + test_muxing(157, "0x0000004c 0x00000000 UNCLAIMED"); + test_muxing(158, "0x0000004c 0x02000000 pinmux_lcd_pins"); + test_muxing(159, "0x0000004c 0x00000000 UNCLAIMED"); + ut_asserteq(-EINVAL, pinctrl_get_pin_muxing(dev, 160, buf, sizeof(buf))); + return 0; +} +DM_TEST(dm_test_pinctrl_single, UT_TESTF_SCAN_FDT);