From patchwork Wed Jan 20 22:21:12 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bjorn Andersson X-Patchwork-Id: 1429499 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=XWv6Iag9; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4DLj0V05Vnz9sW4 for ; Thu, 21 Jan 2021 10:48:58 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731609AbhATXoI (ORCPT ); Wed, 20 Jan 2021 18:44:08 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41840 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730364AbhATWWU (ORCPT ); Wed, 20 Jan 2021 17:22:20 -0500 Received: from mail-ot1-x336.google.com (mail-ot1-x336.google.com [IPv6:2607:f8b0:4864:20::336]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A28FFC0613D6 for ; Wed, 20 Jan 2021 14:21:08 -0800 (PST) Received: by mail-ot1-x336.google.com with SMTP id a109so24985695otc.1 for ; Wed, 20 Jan 2021 14:21:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=iGiVMVVOzcL1tqI/hMjmyV8ceU57PJkL6kjCCyeH1xE=; b=XWv6Iag94foa1dmPlkoCqDaw9gmEnR7Ck55r+HVYDApfgkIObozUqohfmHNX7wQdPU vYXhrBi2bxJGaVQDFJC/cE5zXRI9+O+LudgWwdjXHsEiTaLAVHwhj63I5XfQXfVMZZzS 6eV/ruq8WBPKMLYgE9jm+pPSBNpvJEhss2qqgTaD9rZwjt1ixkaVSyyCuvUuz8vN2/wr bimDt4NyzKk6Kr2df0LnL/4TejnnMRC5ve5TO3rIGLZbDWiVkeTsDYnJij18Mcv8MZhg KBGGH9d+KZkZQWbyn4Wq+9WCCOKDKllfokM3+fP8D5uZdVOo6ymE62XWdss/qDqA5lL4 6IGw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=iGiVMVVOzcL1tqI/hMjmyV8ceU57PJkL6kjCCyeH1xE=; b=ZVUMlWvt5yK6u6T6nA4YiHUCTXjEZl1mPUn867HbFeR40sGBdxO7hWi0CL4OaSE2LK z1gsSDC6F5e5PBgD6rbAbQirro8rN0mlmg7GCfB6fCJxD4tVsRyfc4xDPDdx/tfZ7rKS CvNIYcTbVTWLlTXnC54h4X/lb6QYODvXkNNnd8NM9JktXuFkQaltp84gAtQX9cnJn95E mvixCzXJX+YVYi+HHw/sl4tsoFv6hEbBmCireEKPSbzHb2gYs6ARpZFqG1eM8RCfeCax SFLwgTPuFXGmJ5tuq2zhngtILRheXtug1RQAHovQLN59XtS1BfWIWzumHkcQ6ZztHJm6 XcYg== X-Gm-Message-State: AOAM531lYVFxxiWExiEF+Os55tCFFcPupIlNWowBIsECeujBN3v84Ymf vf3Q3HqU8SSIC03fmzcgxwqTNw== X-Google-Smtp-Source: ABdhPJyjvxKOOptk4pp2hK+PLHBw1zlg2wlJ8ZB7MoqFmFyKPHpQb8T3LD/Q3a9FAgdHt5MpfBuTDA== X-Received: by 2002:a9d:7b5a:: with SMTP id f26mr3679252oto.95.1611181268071; Wed, 20 Jan 2021 14:21:08 -0800 (PST) Received: from localhost.localdomain (104-57-184-186.lightspeed.austtx.sbcglobal.net. [104.57.184.186]) by smtp.gmail.com with ESMTPSA id h127sm660819oia.28.2021.01.20.14.21.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 20 Jan 2021 14:21:07 -0800 (PST) From: Bjorn Andersson To: Andy Gross , Bjorn Andersson , Linus Walleij , Rob Herring Cc: linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 1/3] dt-bindings: pinctrl: qcom: Define common TLMM binding Date: Wed, 20 Jan 2021 14:21:12 -0800 Message-Id: <20210120222114.1609779-2-bjorn.andersson@linaro.org> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20210120222114.1609779-1-bjorn.andersson@linaro.org> References: <20210120222114.1609779-1-bjorn.andersson@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Several properties are shared between all TLMM bindings. By providing a common binding to define these properties each platform's binding can be reduced to just listing which of these properties should be checked for - or further specified. Signed-off-by: Bjorn Andersson Reviewed-by: Vinod Koul --- .../bindings/pinctrl/qcom,tlmm-common.yaml | 85 +++++++++++++++++++ 1 file changed, 85 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,tlmm-common.yaml diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,tlmm-common.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,tlmm-common.yaml new file mode 100644 index 000000000000..ab44952418ad --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,tlmm-common.yaml @@ -0,0 +1,85 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,tlmm-common.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. TLMM definitions + +maintainers: + - Bjorn Andersson + +description: + This defines the common properties used to describe all Qualcomm TLMM + bindings and pinconf/pinmux states for these. + +properties: + interrupts: + description: Specifies the TLMM summary IRQ + maxItems: 1 + + interrupt-controller: true + + '#interrupt-cells': + description: + Specifies the PIN numbers and Flags, as defined in defined in + include/dt-bindings/interrupt-controller/irq.h + const: 2 + + gpio-controller: true + + '#gpio-cells': + description: + Specifying the pin number and flags, as defined in + include/dt-bindings/gpio/gpio.h + const: 2 + + gpio-ranges: + maxItems: 1 + + wakeup-parent: + description: + Specifying the interrupt-controller used to wake up the system when the + TLMM block has been powered down. + maxItems: 1 + + gpio-reserved-ranges: + description: + Pins can be reserved for trusted applications and thereby unaccessible + from the OS. This property can be used to mark the pins which resources + should not be accessed by the OS. Please see the ../gpio/gpio.txt for more + information. + +required: + - interrupts + - interrupt-controller + - '#interrupt-cells' + - gpio-controller + - '#gpio-cells' + - gpio-ranges + +additionalProperties: true + +$defs: + qcom-tlmm-state: + allOf: + - $ref: pincfg-node.yaml# + - $ref: pinmux-node.yaml# + + properties: + drive-strength: + enum: [2, 4, 6, 8, 10, 12, 14, 16] + default: 2 + description: + Selects the drive strength for the specified pins, in mA. + + bias-pull-down: true + bias-pull-up: true + bias-disable: true + input-enable: true + output-high: true + output-low: true + phandle: true + + additionalProperties: true +... From patchwork Wed Jan 20 22:21:13 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bjorn Andersson X-Patchwork-Id: 1429500 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=t6XidKWo; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4DLj0V36h6z9sWH for ; Thu, 21 Jan 2021 10:48:58 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731793AbhATXoJ (ORCPT ); Wed, 20 Jan 2021 18:44:09 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42076 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726434AbhATWW5 (ORCPT ); Wed, 20 Jan 2021 17:22:57 -0500 Received: from mail-ot1-x332.google.com (mail-ot1-x332.google.com [IPv6:2607:f8b0:4864:20::332]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9F30CC061795 for ; Wed, 20 Jan 2021 14:21:09 -0800 (PST) Received: by mail-ot1-x332.google.com with SMTP id v1so6884252ott.10 for ; Wed, 20 Jan 2021 14:21:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=oRh0PxU8b8ysGIIUNHDmW91h/XAgNGs+a5fdScr/DTM=; b=t6XidKWolVA6VdtfCDkGh3VaLFoMaR6Djkj98JkDM3kb+JtjJxot7mCsy/iBeDJ70i +V7xZiDCNCDZzgtCMu0/PZ9tGG/NsmA7ne9Ss1YiG8hv2tymcqeYXSJnx/8mbdfZ5l5e 1b/nr7uVPSE4IiFelg/NiJDoIcwbqc8OwaRsi1KEgfJ+fy327C41KwDG74angztOBBLR FYqIDszkD8cO/TNq/n6T3iOc6CjoTF47BnFjNgsVfy6dFgjX+63Xpt8lRVcP0WSnYBZ9 kVJl/Vwx4JOmTnbCRIONYxYpoQZuvscUa7qpc9fx/TrZDv1LuDuFm7IyPBn0hclXQPpN mFsQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=oRh0PxU8b8ysGIIUNHDmW91h/XAgNGs+a5fdScr/DTM=; b=QZ733GTN8ymxWV38kTmHypynYIgM43z/pSwmi7Fo/HbtSy7pOpYQUkEn8fMtMtvBjG 4gMjtv//YtAc5gNxFpBM8x/rHyOwA6LEGVFgoBKOBPoiD5yW2GMjgXYdOtdl8ifMaBNm Xn4mwXJ4tJ2wFCSAx2kcWCxVW4dRLurJmi4Z3D5BC9wKakSbUcxUspKuCn/SI+W1yIWU aZSF3R0TvrHujKZ8a+6+m65LPkid+6cnQS8rvLvkPlsrwuXSWgXCw2/yRQl1q31Sjgc9 sZi6yOqIEPNz2ZC08+GTtvjANewth67Rbdkr5rWBgZ0pl/EUtf7QNtObhdSPn0ivaO1k KTXQ== X-Gm-Message-State: AOAM530hgFlqGZ2OVHuMg+U9ql5MMd/t3SBi44/tyWWYer4uhf7zBE+M I1T5WVhmbKvnmo0KnkvAELRmXg== X-Google-Smtp-Source: ABdhPJyFtCDUZuUcImZe1lWNyJqA1h17kOdei4Bt/44CVSXEHQv4BYGduR9JV5yPf6J6NhC0c4uc6Q== X-Received: by 2002:a9d:4c8b:: with SMTP id m11mr8591060otf.319.1611181269007; Wed, 20 Jan 2021 14:21:09 -0800 (PST) Received: from localhost.localdomain (104-57-184-186.lightspeed.austtx.sbcglobal.net. [104.57.184.186]) by smtp.gmail.com with ESMTPSA id h127sm660819oia.28.2021.01.20.14.21.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 20 Jan 2021 14:21:08 -0800 (PST) From: Bjorn Andersson To: Andy Gross , Bjorn Andersson , Linus Walleij , Rob Herring Cc: linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 2/3] dt-bindings: pinctrl: qcom: Add sc8180x binding Date: Wed, 20 Jan 2021 14:21:13 -0800 Message-Id: <20210120222114.1609779-3-bjorn.andersson@linaro.org> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20210120222114.1609779-1-bjorn.andersson@linaro.org> References: <20210120222114.1609779-1-bjorn.andersson@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add binding for the TLMM block in the Qualcomm SC8180X platform. Signed-off-by: Bjorn Andersson --- .../pinctrl/qcom,sc8180x-pinctrl.yaml | 153 ++++++++++++++++++ 1 file changed, 153 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,sc8180x-pinctrl.yaml diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sc8180x-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sc8180x-pinctrl.yaml new file mode 100644 index 000000000000..3ebd80d3ca2e --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sc8180x-pinctrl.yaml @@ -0,0 +1,153 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,sc8180x-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. SC8180X TLMM block + +maintainers: + - Bjorn Andersson + +description: | + This binding describes the Top Level Mode Multiplexer block found in the + SC8180X platform. + +allOf: + - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml# + +properties: + compatible: + const: qcom,sc8180x-tlmm + + reg: + maxItems: 3 + + reg-names: + items: + - const: "west" + - const: "east" + - const: "south" + + interrupts: true + interrupt-controller: true + '#interrupt-cells': true + gpio-controller: true + gpio-reserved-ranges: true + '#gpio-cells': true + gpio-ranges: true + wakeup-parent: true + +required: + - compatible + - reg + - reg-names + +additionalProperties: false + +patternProperties: + '-state$': + oneOf: + - $ref: "#/$defs/qcom-sc8180x-tlmm-state" + - patternProperties: + ".*": + $ref: "#/$defs/qcom-sc8180x-tlmm-state" + +'$defs': + qcom-sc8180x-tlmm-state: + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + $ref: "qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state" + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode. + items: + oneOf: + - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-8][0-9])$" + - enum: [ sdc2_clk, sdc2_cmd, sdc2_data, ufs_reset ] + minItems: 1 + maxItems: 16 + + function: + description: + Specify the alternative function to be configured for the specified + pins. + + enum: [ adsp_ext, agera_pll, aoss_cti, atest_char, atest_tsens, + atest_tsens2, atest_usb0, atest_usb1, atest_usb2, atest_usb3, + atest_usb4, audio_ref, btfm_slimbus, cam_mclk, cci_async, + cci_i2c, cci_timer0, cci_timer1, cci_timer2, cci_timer3, + cci_timer4, cci_timer5, cci_timer6, cci_timer7, cci_timer8, + cci_timer9, cri_trng, dbg_out, ddr_bist, ddr_pxi, debug_hot, + dp_hot, edp_hot, edp_lcd, emac_phy, emac_pps, gcc_gp1, gcc_gp2, + gcc_gp3, gcc_gp4, gcc_gp5, gpio, gps, grfc, hs1_mi2s, hs2_mi2s, + hs3_mi2s, jitter_bist, lpass_slimbus, m_voc, mdp_vsync, + mdp_vsync0, mdp_vsync1, mdp_vsync2, mdp_vsync3, mdp_vsync4, + mdp_vsync5, mss_lte, nav_pps, pa_indicator, pci_e0, pci_e1, + pci_e2, pci_e3, phase_flag, pll_bist, pll_bypassnl, pll_reset, + pri_mi2s, pri_mi2s_ws, prng_rosc, qdss_cti, qdss_gpio, qlink, + qspi0, qspi0_clk, qspi0_cs, qspi1, qspi1_clk, qspi1_cs, + qua_mi2s, qup0, qup1, qup2, qup3, qup4, qup5, qup6, qup7, qup8, + qup9, qup10, qup11, qup12, qup13, qup14, qup15, qup16, qup17, + qup18, qup19, qup_l4, qup_l5, qup_l6, rgmii, sd_write, sdc4, + sdc4_clk, sdc4_cmd, sec_mi2s, sp_cmu, spkr_i2s, ter_mi2s, tgu, + tsense_pwm1, tsense_pwm2, tsif1, tsif2, uim1, uim2, uim_batt, + usb0_phy, usb1_phy, usb2phy_ac, vfr_1, vsense_trigger, + wlan1_adc, wlan2_adc, wmss_reset ] + + bias-disable: true + bias-pull-down: true + bias-pull-up: true + drive-strength: true + input-enable: true + output-high: true + output-low: true + phandle: true + + required: + - pins + - function + + additionalProperties: false + +examples: + - | + #include + pinctrl@3100000 { + compatible = "qcom,sc8180x-tlmm"; + reg = <0x03100000 0x300000>, + <0x03500000 0x700000>, + <0x03d00000 0x300000>; + reg-names = "west", "east", "south"; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&tlmm 0 0 190>; + + gpio-wo-subnode-state { + pins = "gpio1"; + function = "gpio"; + }; + + uart-w-subnodes-state { + rx { + pins = "gpio4"; + function = "qup6"; + bias-pull-up; + }; + + tx { + pins = "gpio5"; + function = "qup6"; + bias-disable; + }; + }; + }; +...