From patchwork Wed Jan 20 01:23:53 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 1428958 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=cwmxZcEP; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4DL79z3JrWz9sW8 for ; Wed, 20 Jan 2021 12:25:11 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727219AbhATBYy (ORCPT ); Tue, 19 Jan 2021 20:24:54 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53358 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726317AbhATBYw (ORCPT ); Tue, 19 Jan 2021 20:24:52 -0500 Received: from mail-lj1-x22e.google.com (mail-lj1-x22e.google.com [IPv6:2a00:1450:4864:20::22e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BAE86C061757; Tue, 19 Jan 2021 17:24:11 -0800 (PST) Received: by mail-lj1-x22e.google.com with SMTP id n11so24166160lji.5; Tue, 19 Jan 2021 17:24:11 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=uj7BT9C+f28xNkznwoNGgGBjdluidQQjv9Qul4Tcuu0=; b=cwmxZcEPvwLv/kyqRMBkARFDLnbvaOMuwQ1Ad6KQtMs35OMqAoCEnblKyZ+A/eKgyA N864A//qe/1OnirT+gVqN4ehdhJI+oXEdxjrYJQTTEK82X8pwEhNfKJGPbuU3hJNNyYw VUPX9tFD6CEygMswsa6GzYw0QLuc55Pgo5LJiLdx3col24gaQRyfmJ/gTHyC8SV1xQMN 8yedXesZcL/vdZ9YdJli8BqLtNde1bhecLfDpmJzk/91/d+uEbNKx10ZJLYglDqzLe6C NB8M5g82kJUitIKF4AwsPorUgOV5kjD+nCSTh+rGzcds+O753ZgMpb38xs32TTXucurg GATg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=uj7BT9C+f28xNkznwoNGgGBjdluidQQjv9Qul4Tcuu0=; b=K2ZkOj7NPRhj9U9KH3UjYutxGj7wS+fRRE1XhZNxnSdJXMePcjsN5pI0zu4yo+K+PR prT1jOFKBCL3EdyQWBV3Gb+AlB9O0TFjndlyDYtnItynzV64pC+s3/GgEk0ZtWv2qADq 0uPvU6nlT0cEuzTUh5n7dv7v69RwfIZ2imlrZhZR2S913GbYq8d38DdjCXgzGyf3L/vw I7SXX+sZlDj8uwuRB7F8y0HB01X+OtbeOLuhWY4n+3o5m1Tj2qD83QaCNzcRPeqb4agn jMASx5U3kbNUVChi5b1RWafheFr1MDOYED6syrQygAOywfRFiX3iUIuDBCReGEXrdlqG 6s6A== X-Gm-Message-State: AOAM533rZ3/7/vFTShK7MNkOcEvHqLf+douIZ3oPXqSN3HVxPIcyX6n1 bi85+hEHiYsqIFgiiA9t9M4= X-Google-Smtp-Source: ABdhPJw3T0wyb4OJ46VKz6CKlnDUcY6hkqNPg84d5mL9Fge6xXAVcdpa6b1G+0Rwh4H+H0CcHMHQDA== X-Received: by 2002:a2e:58f:: with SMTP id 137mr3174423ljf.469.1611105850276; Tue, 19 Jan 2021 17:24:10 -0800 (PST) Received: from localhost.localdomain (109-252-192-57.dynamic.spd-mgts.ru. [109.252.192.57]) by smtp.gmail.com with ESMTPSA id c8sm28416lja.80.2021.01.19.17.24.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Jan 2021 17:24:09 -0800 (PST) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Peter Geis , Nicolas Chauvet , Matt Merhar Cc: linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 1/5] soc/tegra: pmc: Fix imbalanced clock disabling in error code path Date: Wed, 20 Jan 2021 04:23:53 +0300 Message-Id: <20210120012357.11038-2-digetx@gmail.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20210120012357.11038-1-digetx@gmail.com> References: <20210120012357.11038-1-digetx@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org The tegra_powergate_power_up() has a typo in the error code path where it will try to disable clocks twice, fix it. In practice that error never happens, so this is a minor correction. Tested-by: Peter Geis # Ouya T30 Tested-by: Nicolas Chauvet # PAZ00 T20 and TK1 T124 Tested-by: Matt Merhar # Ouya T30 Tested-by: Dmitry Osipenko # A500 T20 and Nexus7 T30 [this patch was also boot-tested on some other T20/30/114 devices] Signed-off-by: Dmitry Osipenko --- drivers/soc/tegra/pmc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c index df9a5ca8c99c..fd2ba3c59178 100644 --- a/drivers/soc/tegra/pmc.c +++ b/drivers/soc/tegra/pmc.c @@ -638,7 +638,7 @@ static int tegra_powergate_power_up(struct tegra_powergate *pg, err = tegra_powergate_enable_clocks(pg); if (err) - goto disable_clks; + goto powergate_off; usleep_range(10, 20); From patchwork Wed Jan 20 01:23:54 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 1428960 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=E3r1teUs; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4DL7B207jNz9sW8 for ; Wed, 20 Jan 2021 12:25:14 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727354AbhATBYy (ORCPT ); Tue, 19 Jan 2021 20:24:54 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53364 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726843AbhATBYx (ORCPT ); Tue, 19 Jan 2021 20:24:53 -0500 Received: from mail-lj1-x236.google.com (mail-lj1-x236.google.com [IPv6:2a00:1450:4864:20::236]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 780ABC0613C1; Tue, 19 Jan 2021 17:24:12 -0800 (PST) Received: by mail-lj1-x236.google.com with SMTP id m13so24116039ljo.11; Tue, 19 Jan 2021 17:24:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=uBnKxkMoWgBmADz8vMOGbpC2I6RNnJynTQ74usheb0k=; b=E3r1teUsHqwMDlgns9e18aIexe465SdW1E8s+/2B0eF9nfSYHVYwdvd8G5kQL5L92z hfjqKQoC55a7WdobuCHy7kcRHY7D4HuE6atYoQDrhowE8VqFQGk3KqESnb9BwAik1QzB 0aF8zvGv3OjNhLv48icELUXxbGX/S+kuDSJaQS4hgS9tTYwcYfq0nR81SkQZxW7cM7ST oS8KF3tVejK19guV7I4lGMd5iSnkY+pni7/iidMz8lZAzQH4Q58A7T3kFuefhPl45MGh 0Ppx42ef6c9A7JwMATZU0Alp8Tb5XC6c8zEbRjM5G0XVOeb4M80IAsDyIPgz1rc6wOTF SaOg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=uBnKxkMoWgBmADz8vMOGbpC2I6RNnJynTQ74usheb0k=; b=TRqWmDOHqEggaK0RUmj/ZER8wCLO/K4JvXeW2/OWRZ3HI83Uf9Kr6lTX0kAREWUcqD JlAQAuSVSy2BYoCSz9MLuYyRRVnMRjMCi5AEAEi+FwQWbY1Vxr7cf2/TVhXbmU1C0PMF vbkmLv1EzeqfxplPM55oTJP0G3MAIPEKbD5Zsr4f+fZavfpEQ/0qvdHn78OQdodx27q0 M7HJFk+U9xY13df+ySpF32kY0QBwMhymrE/oU48eHGfdv/kqgiBRKY00741+G3hamu6S ghgIJiJLhctHb3K6D5Msd4wRMVI7fT5K6KFrfKi+FICi5noeH/HrENquOBIUf4owP4O7 bCRA== X-Gm-Message-State: AOAM533yPkbRZC/xpPN6Apd20AUeH+Sluz/DpJ4llhmMA7z5Uv8mpZjH kClf43yvtHjfrJ5pblYGg60= X-Google-Smtp-Source: ABdhPJw+t9t4TC9wAX/mFIXOhdtNSFjt0AB+iKgwQbTTOlR7I83rHV2BXua5Sfun3DbEykce/wWtGg== X-Received: by 2002:a2e:7508:: with SMTP id q8mr3150470ljc.35.1611105851031; Tue, 19 Jan 2021 17:24:11 -0800 (PST) Received: from localhost.localdomain (109-252-192-57.dynamic.spd-mgts.ru. [109.252.192.57]) by smtp.gmail.com with ESMTPSA id c8sm28416lja.80.2021.01.19.17.24.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Jan 2021 17:24:10 -0800 (PST) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Peter Geis , Nicolas Chauvet , Matt Merhar Cc: linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 2/5] soc/tegra: pmc: Fix completion of power-gate toggling Date: Wed, 20 Jan 2021 04:23:54 +0300 Message-Id: <20210120012357.11038-3-digetx@gmail.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20210120012357.11038-1-digetx@gmail.com> References: <20210120012357.11038-1-digetx@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org The SW-initiated power gate toggling is dropped by PMC if there is contention with a HW-initiated toggling, i.e. when one of CPU cores is gated by cpuidle driver. Software should retry the toggling after 10 microseconds on Tegra20/30 SoCs, hence add the retrying. On Tegra114+ the toggling method was changed in hardware, the TOGGLE_START bit indicates whether PMC is busy or could accept the command to toggle, hence handle that bit properly. The problem pops up after enabling dynamic power gating of 3d hardware, where 3d power domain fails to turn on/off "randomly". The programming sequence and quirks are documented in TRMs, but PMC driver obliviously re-used the Tegra20 logic for Tegra30+, which strikes back now. The 10 microseconds and other timeouts aren't documented in TRM, they are taken from downstream kernel. Link: https://nv-tegra.nvidia.com/gitweb/?p=linux-2.6.git;a=commit;h=311dd1c318b70e93bcefec15456a10ff2b9eb0ff Link: https://nv-tegra.nvidia.com/gitweb/?p=linux-3.10.git;a=commit;h=7f36693c47cb23730a6b2822e0975be65fb0c51d Tested-by: Peter Geis # Ouya T30 Tested-by: Nicolas Chauvet # PAZ00 T20 and TK1 T124 Tested-by: Matt Merhar # Ouya T30 Tested-by: Dmitry Osipenko # A500 T20 and Nexus7 T30 [this patch was also boot-tested on some other T20/30/114 devices] Signed-off-by: Dmitry Osipenko --- drivers/soc/tegra/pmc.c | 70 ++++++++++++++++++++++++++++++++++++++--- 1 file changed, 65 insertions(+), 5 deletions(-) diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c index fd2ba3c59178..f970b615ee27 100644 --- a/drivers/soc/tegra/pmc.c +++ b/drivers/soc/tegra/pmc.c @@ -317,6 +317,8 @@ struct tegra_pmc_soc { bool invert); int (*irq_set_wake)(struct irq_data *data, unsigned int on); int (*irq_set_type)(struct irq_data *data, unsigned int type); + int (*powergate_set)(struct tegra_pmc *pmc, unsigned int id, + bool new_state); const char * const *reset_sources; unsigned int num_reset_sources; @@ -517,6 +519,63 @@ static int tegra_powergate_lookup(struct tegra_pmc *pmc, const char *name) return -ENODEV; } +static int tegra20_powergate_set(struct tegra_pmc *pmc, unsigned int id, + bool new_state) +{ + unsigned int retries = 100; + bool status; + int ret; + + /* + * As per TRM documentation, the toggle command will be dropped by PMC + * if there is contention with a HW-initiated toggling (i.e. CPU core + * power-gated), the command should be retried in that case. + */ + do { + tegra_pmc_writel(pmc, PWRGATE_TOGGLE_START | id, PWRGATE_TOGGLE); + + /* wait for PMC to execute the command */ + ret = readx_poll_timeout(tegra_powergate_state, id, status, + status == new_state, 1, 10); + } while (ret == -ETIMEDOUT && retries--); + + return ret; +} + +static inline bool tegra_powergate_toggle_ready(struct tegra_pmc *pmc) +{ + return !(tegra_pmc_readl(pmc, PWRGATE_TOGGLE) & PWRGATE_TOGGLE_START); +} + +static int tegra114_powergate_set(struct tegra_pmc *pmc, unsigned int id, + bool new_state) +{ + bool status; + int err; + + /* wait while PMC power gating is contented */ + err = readx_poll_timeout(tegra_powergate_toggle_ready, pmc, status, + status == true, 1, 100); + if (err) + return err; + + tegra_pmc_writel(pmc, PWRGATE_TOGGLE_START | id, PWRGATE_TOGGLE); + + /* wait for PMC to accept the command */ + err = readx_poll_timeout(tegra_powergate_toggle_ready, pmc, status, + status == true, 1, 100); + if (err) + return err; + + /* wait for PMC to execute the command */ + err = readx_poll_timeout(tegra_powergate_state, id, status, + status == new_state, 10, 100000); + if (err) + return err; + + return 0; +} + /** * tegra_powergate_set() - set the state of a partition * @pmc: power management controller @@ -526,7 +585,6 @@ static int tegra_powergate_lookup(struct tegra_pmc *pmc, const char *name) static int tegra_powergate_set(struct tegra_pmc *pmc, unsigned int id, bool new_state) { - bool status; int err; if (id == TEGRA_POWERGATE_3D && pmc->soc->has_gpu_clamps) @@ -539,10 +597,7 @@ static int tegra_powergate_set(struct tegra_pmc *pmc, unsigned int id, return 0; } - tegra_pmc_writel(pmc, PWRGATE_TOGGLE_START | id, PWRGATE_TOGGLE); - - err = readx_poll_timeout(tegra_powergate_state, id, status, - status == new_state, 10, 100000); + err = pmc->soc->powergate_set(pmc, id, new_state); mutex_unlock(&pmc->powergates_lock); @@ -2699,6 +2754,7 @@ static const struct tegra_pmc_soc tegra20_pmc_soc = { .regs = &tegra20_pmc_regs, .init = tegra20_pmc_init, .setup_irq_polarity = tegra20_pmc_setup_irq_polarity, + .powergate_set = tegra20_powergate_set, .reset_sources = NULL, .num_reset_sources = 0, .reset_levels = NULL, @@ -2757,6 +2813,7 @@ static const struct tegra_pmc_soc tegra30_pmc_soc = { .regs = &tegra20_pmc_regs, .init = tegra20_pmc_init, .setup_irq_polarity = tegra20_pmc_setup_irq_polarity, + .powergate_set = tegra20_powergate_set, .reset_sources = tegra30_reset_sources, .num_reset_sources = ARRAY_SIZE(tegra30_reset_sources), .reset_levels = NULL, @@ -2811,6 +2868,7 @@ static const struct tegra_pmc_soc tegra114_pmc_soc = { .regs = &tegra20_pmc_regs, .init = tegra20_pmc_init, .setup_irq_polarity = tegra20_pmc_setup_irq_polarity, + .powergate_set = tegra114_powergate_set, .reset_sources = tegra30_reset_sources, .num_reset_sources = ARRAY_SIZE(tegra30_reset_sources), .reset_levels = NULL, @@ -2925,6 +2983,7 @@ static const struct tegra_pmc_soc tegra124_pmc_soc = { .regs = &tegra20_pmc_regs, .init = tegra20_pmc_init, .setup_irq_polarity = tegra20_pmc_setup_irq_polarity, + .powergate_set = tegra114_powergate_set, .reset_sources = tegra30_reset_sources, .num_reset_sources = ARRAY_SIZE(tegra30_reset_sources), .reset_levels = NULL, @@ -3048,6 +3107,7 @@ static const struct tegra_pmc_soc tegra210_pmc_soc = { .regs = &tegra20_pmc_regs, .init = tegra20_pmc_init, .setup_irq_polarity = tegra20_pmc_setup_irq_polarity, + .powergate_set = tegra114_powergate_set, .irq_set_wake = tegra210_pmc_irq_set_wake, .irq_set_type = tegra210_pmc_irq_set_type, .reset_sources = tegra210_reset_sources, From patchwork Wed Jan 20 01:23:55 2021 Content-Type: text/plain; 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[109.252.192.57]) by smtp.gmail.com with ESMTPSA id c8sm28416lja.80.2021.01.19.17.24.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Jan 2021 17:24:11 -0800 (PST) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Peter Geis , Nicolas Chauvet , Matt Merhar Cc: linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 3/5] soc/tegra: pmc: Ensure that clock rates aren't too high Date: Wed, 20 Jan 2021 04:23:55 +0300 Message-Id: <20210120012357.11038-4-digetx@gmail.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20210120012357.11038-1-digetx@gmail.com> References: <20210120012357.11038-1-digetx@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Switch all clocks of a power domain to a safe rate which is suitable for all possible voltages in order to ensure that hardware constraints aren't violated when power domain state toggles. Tested-by: Peter Geis # Ouya T30 Tested-by: Nicolas Chauvet # PAZ00 T20 and TK1 T124 Tested-by: Matt Merhar # Ouya T30 Tested-by: Dmitry Osipenko # A500 T20 and Nexus7 T30 [this patch was also boot-tested on some other T20/30/114 devices] Signed-off-by: Dmitry Osipenko --- drivers/soc/tegra/pmc.c | 92 ++++++++++++++++++++++++++++++++++++++++- 1 file changed, 90 insertions(+), 2 deletions(-) diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c index f970b615ee27..a87645fac735 100644 --- a/drivers/soc/tegra/pmc.c +++ b/drivers/soc/tegra/pmc.c @@ -237,6 +237,7 @@ struct tegra_powergate { unsigned int id; struct clk **clks; unsigned int num_clks; + unsigned long *clk_rates; struct reset_control *reset; }; @@ -641,6 +642,57 @@ static int __tegra_powergate_remove_clamping(struct tegra_pmc *pmc, return 0; } +static int tegra_powergate_prepare_clocks(struct tegra_powergate *pg) +{ + unsigned long safe_rate = 100 * 1000 * 1000; + unsigned int i; + int err; + + for (i = 0; i < pg->num_clks; i++) { + pg->clk_rates[i] = clk_get_rate(pg->clks[i]); + + if (!pg->clk_rates[i]) { + err = -EINVAL; + goto out; + } + + if (pg->clk_rates[i] <= safe_rate) + continue; + + /* + * We don't know whether voltage state is okay for the + * current clock rate, hence it's better to temporally + * switch clock to a safe rate which is suitable for + * all voltages, before enabling the clock. + */ + err = clk_set_rate(pg->clks[i], safe_rate); + if (err) + goto out; + } + + return 0; + +out: + while (i--) + clk_set_rate(pg->clks[i], pg->clk_rates[i]); + + return err; +} + +static int tegra_powergate_unprepare_clocks(struct tegra_powergate *pg) +{ + unsigned int i; + int err; + + for (i = 0; i < pg->num_clks; i++) { + err = clk_set_rate(pg->clks[i], pg->clk_rates[i]); + if (err) + return err; + } + + return 0; +} + static void tegra_powergate_disable_clocks(struct tegra_powergate *pg) { unsigned int i; @@ -691,10 +743,14 @@ static int tegra_powergate_power_up(struct tegra_powergate *pg, usleep_range(10, 20); - err = tegra_powergate_enable_clocks(pg); + err = tegra_powergate_prepare_clocks(pg); if (err) goto powergate_off; + err = tegra_powergate_enable_clocks(pg); + if (err) + goto unprepare_clks; + usleep_range(10, 20); err = __tegra_powergate_remove_clamping(pg->pmc, pg->id); @@ -717,12 +773,19 @@ static int tegra_powergate_power_up(struct tegra_powergate *pg, if (disable_clocks) tegra_powergate_disable_clocks(pg); + err = tegra_powergate_unprepare_clocks(pg); + if (err) + return err; + return 0; disable_clks: tegra_powergate_disable_clocks(pg); usleep_range(10, 20); +unprepare_clks: + tegra_powergate_unprepare_clocks(pg); + powergate_off: tegra_powergate_set(pg->pmc, pg->id, false); @@ -733,10 +796,14 @@ static int tegra_powergate_power_down(struct tegra_powergate *pg) { int err; - err = tegra_powergate_enable_clocks(pg); + err = tegra_powergate_prepare_clocks(pg); if (err) return err; + err = tegra_powergate_enable_clocks(pg); + if (err) + goto unprepare_clks; + usleep_range(10, 20); err = reset_control_assert(pg->reset); @@ -753,6 +820,10 @@ static int tegra_powergate_power_down(struct tegra_powergate *pg) if (err) goto assert_resets; + err = tegra_powergate_unprepare_clocks(pg); + if (err) + return err; + return 0; assert_resets: @@ -764,6 +835,9 @@ static int tegra_powergate_power_down(struct tegra_powergate *pg) disable_clks: tegra_powergate_disable_clocks(pg); +unprepare_clks: + tegra_powergate_unprepare_clocks(pg); + return err; } @@ -881,6 +955,12 @@ int tegra_powergate_sequence_power_up(unsigned int id, struct clk *clk, if (!pg) return -ENOMEM; + pg->clk_rates = kzalloc(sizeof(*pg->clk_rates), GFP_KERNEL); + if (!pg->clk_rates) { + kfree(pg->clks); + return -ENOMEM; + } + pg->id = id; pg->clks = &clk; pg->num_clks = 1; @@ -892,6 +972,7 @@ int tegra_powergate_sequence_power_up(unsigned int id, struct clk *clk, dev_err(pmc->dev, "failed to turn on partition %d: %d\n", id, err); + kfree(pg->clk_rates); kfree(pg); return err; @@ -1042,6 +1123,12 @@ static int tegra_powergate_of_get_clks(struct tegra_powergate *pg, if (!pg->clks) return -ENOMEM; + pg->clk_rates = kcalloc(count, sizeof(*pg->clk_rates), GFP_KERNEL); + if (!pg->clk_rates) { + kfree(pg->clks); + return -ENOMEM; + } + for (i = 0; i < count; i++) { pg->clks[i] = of_clk_get(np, i); if (IS_ERR(pg->clks[i])) { @@ -1058,6 +1145,7 @@ static int tegra_powergate_of_get_clks(struct tegra_powergate *pg, while (i--) clk_put(pg->clks[i]); + kfree(pg->clk_rates); kfree(pg->clks); return err; From patchwork Wed Jan 20 01:23:56 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 1428978 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=IaLQMXGH; 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[109.252.192.57]) by smtp.gmail.com with ESMTPSA id c8sm28416lja.80.2021.01.19.17.24.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Jan 2021 17:24:12 -0800 (PST) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Peter Geis , Nicolas Chauvet , Matt Merhar Cc: linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 4/5] soc/tegra: pmc: Print out domain name when reset fails to acquire Date: Wed, 20 Jan 2021 04:23:56 +0300 Message-Id: <20210120012357.11038-5-digetx@gmail.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20210120012357.11038-1-digetx@gmail.com> References: <20210120012357.11038-1-digetx@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Print out domain name when reset fails to acquire for debugging purposes and to make formatting of GENPD errors consistent in the driver. Tested-by: Peter Geis # Ouya T30 Tested-by: Nicolas Chauvet # PAZ00 T20 and TK1 T124 Tested-by: Matt Merhar # Ouya T30 Tested-by: Dmitry Osipenko # A500 T20 and Nexus7 T30 [this patch was also boot-tested on some other T20/30/114 devices] Signed-off-by: Dmitry Osipenko --- drivers/soc/tegra/pmc.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c index a87645fac735..bf29ea22480a 100644 --- a/drivers/soc/tegra/pmc.c +++ b/drivers/soc/tegra/pmc.c @@ -868,7 +868,8 @@ static int tegra_genpd_power_off(struct generic_pm_domain *domain) err = reset_control_acquire(pg->reset); if (err < 0) { - pr_err("failed to acquire resets: %d\n", err); + dev_err(dev, "failed to acquire resets for PM domain %s: %d\n", + pg->genpd.name, err); return err; } From patchwork Wed Jan 20 01:23:57 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 1428977 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=ESX4j9gI; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4DL8bW2dK5z9sB4 for ; Wed, 20 Jan 2021 13:28:55 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728340AbhATC2L (ORCPT ); Tue, 19 Jan 2021 21:28:11 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53442 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728104AbhATBZO (ORCPT ); Tue, 19 Jan 2021 20:25:14 -0500 Received: from mail-lf1-x135.google.com (mail-lf1-x135.google.com [IPv6:2a00:1450:4864:20::135]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D8D56C0613D6; Tue, 19 Jan 2021 17:24:14 -0800 (PST) Received: by mail-lf1-x135.google.com with SMTP id m25so31847594lfc.11; Tue, 19 Jan 2021 17:24:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=IeBFJJDe4VVelYzs6REAIbkz4wri3N29ZGU+KneB1Xc=; b=ESX4j9gI2nLxK46A9naHobZGuKbDQ5OgI8vz2xzSPdkL68xQW3w5642CUchzJevAbI JsSpXyq2BeAuOQM283OXACmBWSv0OM9BOdfbhELE1CLcWbIYn97nx/ZTUtlJKnbTs8hP yJeMqOgUL+jLFP3/OzNuPM1/gz+CUmcTK//BSRFKH7Lz/JxNuQxo5pttsCsBaGC1U7C3 Z4XC1PAO4ykhD7XW9zsFsvMP3GFn5D2hyxZnlgnfJK7sk05gVDEVDN+lEhziN/5s08nS FoJbnNi8Y+cu6wj9d+kRaG5dxdNRzoMkhVd/m1dSiY0N5k2P4edUMdwYYd7GpqQ0EGL5 xW1w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=IeBFJJDe4VVelYzs6REAIbkz4wri3N29ZGU+KneB1Xc=; b=J8+PJXTZVnB+WrbQM3F9xoeKR6FgPcveBncYjH52sxK8oKi5dH78LnLOPuohyLywZd 7w/3WPXN40grxXSzKaOhvaacxpmTA7aQjgI7g+pptVp0wnOeJ/1HbeTUk3ajb1uKd0MG oAIg/Z9N+ldw4/8RMYdSrMTCo3Ju/YYmDoMEQWWWWqXO0rj8knzmBWMHNDVerqFw8Xjd 4MRyAfSymBLNhIhCpX2nQiXf9J4p/srF7PpcR6SdJzekck7m33FJ0MraWyIaJptCYD// j7/AOElT1M4KWCSGQg1BFnQpH2kvaajFGK4TljlOcJMOaL42z5iyYlS+ciDr2czI43zL FAzA== X-Gm-Message-State: AOAM530snVjNxyxOE9+h24zMft08XaqeAqefmIwxcZDmtVY8Bmc1D/gL TJgh3+xP9m1Pv+zaXS5h+Gw= X-Google-Smtp-Source: ABdhPJxnbQDG0JUGI3IE6Lvzxbrmp+MbulTddr0Z2K/Ifu+puMZWHVhee91No3GdlvKYK7wAMNciZg== X-Received: by 2002:a19:ac2:: with SMTP id 185mr543710lfk.99.1611105853456; Tue, 19 Jan 2021 17:24:13 -0800 (PST) Received: from localhost.localdomain (109-252-192-57.dynamic.spd-mgts.ru. [109.252.192.57]) by smtp.gmail.com with ESMTPSA id c8sm28416lja.80.2021.01.19.17.24.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Jan 2021 17:24:13 -0800 (PST) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Peter Geis , Nicolas Chauvet , Matt Merhar Cc: linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 5/5] soc/tegra: pmc: Link power domains to the parent Core domain Date: Wed, 20 Jan 2021 04:23:57 +0300 Message-Id: <20210120012357.11038-6-digetx@gmail.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20210120012357.11038-1-digetx@gmail.com> References: <20210120012357.11038-1-digetx@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org The Core domain is a parent of PMC power domains, hence PMC domains should be set up as a sub-domains of the parent (Core) domain if "power-domains" phandle presents in a device-tree node of PMC domain. This allows to propagate GENPD performance changes to the parent Core domain if performance change is applied to PMC domain. Tested-by: Peter Geis # Ouya T30 Tested-by: Nicolas Chauvet # PAZ00 T20 and TK1 T124 Tested-by: Matt Merhar # Ouya T30 Tested-by: Dmitry Osipenko # A500 T20 and Nexus7 T30 [this patch was also boot-tested on some other T20/30/114 devices] Signed-off-by: Dmitry Osipenko --- drivers/soc/tegra/pmc.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c index bf29ea22480a..de66092c3d61 100644 --- a/drivers/soc/tegra/pmc.c +++ b/drivers/soc/tegra/pmc.c @@ -1283,6 +1283,7 @@ static int tegra_powergate_add(struct tegra_pmc *pmc, struct device_node *np) static int tegra_powergate_init(struct tegra_pmc *pmc, struct device_node *parent) { + struct of_phandle_args child_args, parent_args; struct device_node *np, *child; int err = 0; @@ -1296,6 +1297,21 @@ static int tegra_powergate_init(struct tegra_pmc *pmc, of_node_put(child); break; } + + if (of_parse_phandle_with_args(child, "power-domains", + "#power-domain-cells", + 0, &parent_args)) + continue; + + child_args.np = child; + child_args.args_count = 0; + + err = of_genpd_add_subdomain(&parent_args, &child_args); + of_node_put(parent_args.np); + if (err) { + of_node_put(child); + break; + } } of_node_put(np);