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Mon, 18 Jan 2021 04:33:13 -0800 Envelope-to: git@xilinx.com, jagan@amarulasolutions.com, tgorochowik@antmicro.com, wtatarski@antmicro.com, ashok.409@gmail.com, u-boot@lists.denx.de, monstr@monstr.eu Received: from [172.23.64.106] (port=48315 helo=xhdvnc125.xilinx.com) by smtp.xilinx.com with esmtp (Exim 4.90) (envelope-from ) id 1l1Tia-0004rV-G6; Mon, 18 Jan 2021 04:33:12 -0800 Received: by xhdvnc125.xilinx.com (Postfix, from userid 2896) id 528421222C0; Mon, 18 Jan 2021 18:02:31 +0530 (IST) From: Ashok Reddy Soma To: CC: , , , , Wojciech Tatarski , "Tomasz Gorochowik" , Ashok Reddy Soma Subject: [PATCH 1/7] spi: zynqmp_gqspi: do not round immediate_data field Date: Mon, 18 Jan 2021 18:02:22 +0530 Message-ID: <1610973148-22465-2-git-send-email-ashok.reddy.soma@xilinx.com> X-Mailer: git-send-email 2.1.1 In-Reply-To: <1610973148-22465-1-git-send-email-ashok.reddy.soma@xilinx.com> References: <1610973148-22465-1-git-send-email-ashok.reddy.soma@xilinx.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-Office365-Filtering-HT: Tenant X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: d9ca59ed-9c96-450a-4c22-08d8bbad3a37 X-MS-TrafficTypeDiagnostic: DM6PR02MB6458: X-LD-Processed: 657af505-d5df-48d0-8300-c31994686c5c,ExtAddr X-Microsoft-Antispam-PRVS: X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-Oob-TLC-OOBClassifiers: OLM:7219; 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DIR:OUT; SFP:1101; X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Jan 2021 12:33:15.2724 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d9ca59ed-9c96-450a-4c22-08d8bbad3a37 X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c; Ip=[149.199.62.198]; Helo=[xsj-pvapexch02.xlnx.xilinx.com] X-MS-Exchange-CrossTenant-AuthSource: CY1NAM02FT038.eop-nam02.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR02MB6458 X-Mailman-Approved-At: Mon, 18 Jan 2021 13:34:57 +0100 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.3 at phobos.denx.de X-Virus-Status: Clean From: Wojciech Tatarski Immediate_data is 8 bit value in generic FIFO command. When fields data_xfer=1 and exponent=0 this field specifies the absolute number of data bytes to read into the RXFIFO. Values from range 0xfd to 0xff are rounded up to 0x100. It causes overwriting the next bit field which is data_xfer. According to Zynq Ultrascale TRM only DMA transfers should be word aligned. So there is no reason to round up the immediate_data field. Signed-off-by: Wojciech Tatarski Signed-off-by: Tomasz Gorochowik Tested-by: Siva Durga Prasad Paladugu Signed-off-by: Ashok Reddy Soma --- drivers/spi/zynqmp_gqspi.c | 9 ++------- 1 file changed, 2 insertions(+), 7 deletions(-) -- 2.17.1 This email and any attachments are intended for the sole use of the named recipient(s) and contain(s) confidential information that may be proprietary, privileged or copyrighted under applicable law. If you are not the intended recipient, do not read, copy, or forward this email message or any attachments. Delete this email message and any attachments immediately. diff --git a/drivers/spi/zynqmp_gqspi.c b/drivers/spi/zynqmp_gqspi.c index efcbd0557f..3e0dbb2c7b 100644 --- a/drivers/spi/zynqmp_gqspi.c +++ b/drivers/spi/zynqmp_gqspi.c @@ -524,7 +524,7 @@ static int zynqmp_qspi_start_dma(struct zynqmp_qspi_priv *priv, u32 gen_fifo_cmd, u32 *buf) { u32 addr; - u32 size, len; + u32 size; u32 actuallen = priv->len; int ret = 0; struct zynqmp_qspi_dma_regs *dma_regs = priv->dma_regs; @@ -537,12 +537,7 @@ static int zynqmp_qspi_start_dma(struct zynqmp_qspi_priv *priv, flush_dcache_range(addr, addr + size); while (priv->len) { - len = zynqmp_qspi_calc_exp(priv, &gen_fifo_cmd); - if (!(gen_fifo_cmd & GQSPI_GFIFO_EXP_MASK) && - (len % ARCH_DMA_MINALIGN)) { - gen_fifo_cmd &= ~GENMASK(7, 0); - gen_fifo_cmd |= roundup(len, ARCH_DMA_MINALIGN); - } + zynqmp_qspi_calc_exp(priv, &gen_fifo_cmd); zynqmp_qspi_fill_gen_fifo(priv, gen_fifo_cmd); debug("GFIFO_CMD_RX:0x%x\n", gen_fifo_cmd); From patchwork Mon Jan 18 12:32:23 2021 Content-Type: text/plain; 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Mon, 18 Jan 2021 04:32:46 -0800 Envelope-to: git@xilinx.com, jagan@amarulasolutions.com, tgorochowik@antmicro.com, wtatarski@antmicro.com, ashok.409@gmail.com, u-boot@lists.denx.de, monstr@monstr.eu Received: from [172.23.64.106] (port=48300 helo=xhdvnc125.xilinx.com) by smtp.xilinx.com with esmtp (Exim 4.90) (envelope-from ) id 1l1Ti9-0004mz-Ib; Mon, 18 Jan 2021 04:32:45 -0800 Received: by xhdvnc125.xilinx.com (Postfix, from userid 2896) id 50FC41210A5; Mon, 18 Jan 2021 18:02:31 +0530 (IST) From: Ashok Reddy Soma To: CC: , , , , Wojciech Tatarski , "Tomasz Gorochowik" , Ashok Reddy Soma Subject: [PATCH 2/7] spi: zynqmp_gqspi: DMA transfers should be word aligned Date: Mon, 18 Jan 2021 18:02:23 +0530 Message-ID: <1610973148-22465-3-git-send-email-ashok.reddy.soma@xilinx.com> X-Mailer: git-send-email 2.1.1 In-Reply-To: <1610973148-22465-1-git-send-email-ashok.reddy.soma@xilinx.com> References: <1610973148-22465-1-git-send-email-ashok.reddy.soma@xilinx.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-Office365-Filtering-HT: Tenant X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: e233415b-e078-4573-41b5-08d8bbad2ad9 X-MS-TrafficTypeDiagnostic: SN6PR02MB5487: X-LD-Processed: 657af505-d5df-48d0-8300-c31994686c5c,ExtAddr X-Microsoft-Antispam-PRVS: X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-Oob-TLC-OOBClassifiers: OLM:1002; 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So there is no reason to round up size of DMA transfer to ARCH_DMA_MINALIGN (0x40) Signed-off-by: Wojciech Tatarski Signed-off-by: Tomasz Gorochowik Tested-by: Siva Durga Prasad Paladugu Signed-off-by: Ashok Reddy Soma --- drivers/spi/zynqmp_gqspi.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) -- 2.17.1 This email and any attachments are intended for the sole use of the named recipient(s) and contain(s) confidential information that may be proprietary, privileged or copyrighted under applicable law. If you are not the intended recipient, do not read, copy, or forward this email message or any attachments. Delete this email message and any attachments immediately. diff --git a/drivers/spi/zynqmp_gqspi.c b/drivers/spi/zynqmp_gqspi.c index 3e0dbb2c7b..81c5e2b22f 100644 --- a/drivers/spi/zynqmp_gqspi.c +++ b/drivers/spi/zynqmp_gqspi.c @@ -530,10 +530,10 @@ static int zynqmp_qspi_start_dma(struct zynqmp_qspi_priv *priv, struct zynqmp_qspi_dma_regs *dma_regs = priv->dma_regs; writel((unsigned long)buf, &dma_regs->dmadst); - writel(roundup(priv->len, ARCH_DMA_MINALIGN), &dma_regs->dmasize); + writel(roundup(priv->len, GQSPI_DMA_ALIGN), &dma_regs->dmasize); writel(GQSPI_DMA_DST_I_STS_MASK, &dma_regs->dmaier); addr = (unsigned long)buf; - size = roundup(priv->len, ARCH_DMA_MINALIGN); + size = roundup(priv->len, GQSPI_DMA_ALIGN); flush_dcache_range(addr, addr + size); while (priv->len) { From patchwork Mon Jan 18 12:32:24 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ashok Reddy Soma X-Patchwork-Id: 1428118 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; 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The driver will be in IO mode when "has-io-mode" is passed from device tree instead of DMA. Signed-off-by: Ashok Reddy Soma --- drivers/spi/zynqmp_gqspi.c | 140 ++++++++++++++++++++++++++++++++----- 1 file changed, 123 insertions(+), 17 deletions(-) -- 2.17.1 This email and any attachments are intended for the sole use of the named recipient(s) and contain(s) confidential information that may be proprietary, privileged or copyrighted under applicable law. If you are not the intended recipient, do not read, copy, or forward this email message or any attachments. Delete this email message and any attachments immediately. diff --git a/drivers/spi/zynqmp_gqspi.c b/drivers/spi/zynqmp_gqspi.c index 81c5e2b22f..ae7b70aa57 100644 --- a/drivers/spi/zynqmp_gqspi.c +++ b/drivers/spi/zynqmp_gqspi.c @@ -16,11 +16,13 @@ #include #include #include +#include #include #include #include -#include -#include +#include +#include "../mtd/spi/sf_internal.h" +#include #define GQSPI_GFIFO_STRT_MODE_MASK BIT(29) #define GQSPI_CONFIG_MODE_EN_MASK (3 << 30) @@ -38,6 +40,7 @@ #define GQSPI_IXR_TXFULL_MASK 0x00000008 /* QSPI TX FIFO is full */ #define GQSPI_IXR_RXNEMTY_MASK 0x00000010 /* QSPI RX FIFO Not Empty */ #define GQSPI_IXR_GFEMTY_MASK 0x00000080 /* QSPI Generic FIFO Empty */ +#define GQSPI_IXR_GFNFULL_MASK 0x00000200 /* QSPI GENFIFO not full */ #define GQSPI_IXR_ALL_MASK (GQSPI_IXR_TXNFULL_MASK | \ GQSPI_IXR_RXNEMTY_MASK) @@ -75,6 +78,7 @@ #define GQSPI_GFIFO_SELECT BIT(0) #define GQSPI_FIFO_THRESHOLD 1 +#define GQSPI_GENFIFO_THRESHOLD 31 #define SPI_XFER_ON_BOTH 0 #define SPI_XFER_ON_LOWER 1 @@ -161,6 +165,7 @@ struct zynqmp_qspi_plat { struct zynqmp_qspi_dma_regs *dma_regs; u32 frequency; u32 speed_hz; + unsigned int io_mode; }; struct zynqmp_qspi_priv { @@ -173,8 +178,11 @@ struct zynqmp_qspi_priv { int bytes_to_receive; unsigned int is_inst; unsigned int cs_change:1; + unsigned int io_mode; }; +static u8 last_cmd; + static int zynqmp_qspi_of_to_plat(struct udevice *bus) { struct zynqmp_qspi_plat *plat = dev_get_plat(bus); @@ -186,6 +194,7 @@ static int zynqmp_qspi_of_to_plat(struct udevice *bus) plat->dma_regs = (struct zynqmp_qspi_dma_regs *) (dev_read_addr(bus) + GQSPI_DMA_REG_OFFSET); + plat->io_mode = dev_read_bool(bus, "has-io-mode"); return 0; } @@ -198,14 +207,20 @@ static void zynqmp_qspi_init_hw(struct zynqmp_qspi_priv *priv) writel(GQSPI_GFIFO_ALL_INT_MASK, ®s->idisr); writel(GQSPI_FIFO_THRESHOLD, ®s->txftr); writel(GQSPI_FIFO_THRESHOLD, ®s->rxftr); + writel(GQSPI_GENFIFO_THRESHOLD, ®s->gqfthr); writel(GQSPI_GFIFO_ALL_INT_MASK, ®s->isr); + writel(0x0, ®s->enbr); config_reg = readl(®s->confr); - config_reg &= ~(GQSPI_GFIFO_STRT_MODE_MASK | - GQSPI_CONFIG_MODE_EN_MASK); - config_reg |= GQSPI_CONFIG_DMA_MODE | - GQSPI_GFIFO_WP_HOLD | - GQSPI_DFLT_BAUD_RATE_DIV; + config_reg &= ~(GQSPI_CONFIG_MODE_EN_MASK); + config_reg |= GQSPI_GFIFO_WP_HOLD | GQSPI_DFLT_BAUD_RATE_DIV; + if (priv->io_mode) { + config_reg |= GQSPI_GFIFO_STRT_MODE_MASK; + } else { + config_reg &= ~(GQSPI_GFIFO_STRT_MODE_MASK); + config_reg |= GQSPI_CONFIG_DMA_MODE; + } + writel(config_reg, ®s->confr); writel(GQSPI_ENABLE_ENABLE_MASK, ®s->enbr); @@ -215,8 +230,7 @@ static u32 zynqmp_qspi_bus_select(struct zynqmp_qspi_priv *priv) { u32 gqspi_fifo_reg = 0; - gqspi_fifo_reg = GQSPI_GFIFO_LOW_BUS | - GQSPI_GFIFO_CS_LOWER; + gqspi_fifo_reg = GQSPI_GFIFO_LOW_BUS | GQSPI_GFIFO_CS_LOWER; return gqspi_fifo_reg; } @@ -227,6 +241,7 @@ static void zynqmp_qspi_fill_gen_fifo(struct zynqmp_qspi_priv *priv, struct zynqmp_qspi_regs *regs = priv->regs; int ret = 0; + /* Wait until the fifo is not full to write the new command */ ret = wait_for_bit_le32(®s->isr, GQSPI_IXR_GFEMTY_MASK, 1, GQSPI_TIMEOUT, 1); if (ret) @@ -343,6 +358,7 @@ static int zynqmp_qspi_probe(struct udevice *bus) priv->regs = plat->regs; priv->dma_regs = plat->dma_regs; + priv->io_mode = plat->io_mode; ret = clk_get_by_index(bus, 0, &clk); if (ret < 0) { @@ -363,7 +379,7 @@ static int zynqmp_qspi_probe(struct udevice *bus) return ret; } plat->frequency = clock; - plat->speed_hz = plat->frequency / 2; + plat->speed_hz = plat->frequency; /* init the zynq spi hw */ zynqmp_qspi_init_hw(priv); @@ -395,7 +411,7 @@ static int zynqmp_qspi_set_mode(struct udevice *bus, uint mode) static int zynqmp_qspi_fill_tx_fifo(struct zynqmp_qspi_priv *priv, u32 size) { - u32 data; + u32 data, config_reg, ier; int ret = 0; struct zynqmp_qspi_regs *regs = priv->regs; u32 *buf = (u32 *)priv->tx_buf; @@ -404,6 +420,17 @@ static int zynqmp_qspi_fill_tx_fifo(struct zynqmp_qspi_priv *priv, u32 size) debug("TxFIFO: 0x%x, size: 0x%x\n", readl(®s->isr), size); + config_reg = readl(®s->confr); + /* Manual start if needed */ + if (config_reg & GQSPI_GEN_FIFO_STRT_MOD) { + config_reg |= GQSPI_STRT_GEN_FIFO; + writel(config_reg, ®s->confr); + /* Enable interrupts */ + ier = readl(®s->ier); + ier |= GQSPI_IXR_ALL_MASK; + writel(ier, ®s->ier); + } + while (size) { ret = wait_for_bit_le32(®s->isr, GQSPI_IXR_TXNFULL_MASK, 1, GQSPI_TIMEOUT, 1); @@ -445,12 +472,20 @@ static int zynqmp_qspi_fill_tx_fifo(struct zynqmp_qspi_priv *priv, u32 size) static void zynqmp_qspi_genfifo_cmd(struct zynqmp_qspi_priv *priv) { + u8 command = 1; u32 gen_fifo_cmd; u32 bytecount = 0; while (priv->len) { gen_fifo_cmd = zynqmp_qspi_bus_select(priv); - gen_fifo_cmd |= GQSPI_GFIFO_TX | GQSPI_SPI_MODE_SPI; + gen_fifo_cmd |= GQSPI_GFIFO_TX; + + if (command) { + command = 0; + last_cmd = *(u8 *)priv->tx_buf; + } + + gen_fifo_cmd |= GQSPI_SPI_MODE_SPI; gen_fifo_cmd |= *(u8 *)priv->tx_buf; bytecount++; priv->len--; @@ -499,7 +534,10 @@ static int zynqmp_qspi_genfifo_fill_tx(struct zynqmp_qspi_priv *priv) gen_fifo_cmd |= GQSPI_GFIFO_TX | GQSPI_GFIFO_DATA_XFR_MASK; - gen_fifo_cmd |= GQSPI_SPI_MODE_SPI; + if (last_cmd == SPINOR_OP_PP_1_1_4) + gen_fifo_cmd |= GQSPI_SPI_MODE_QSPI; + else + gen_fifo_cmd |= GQSPI_SPI_MODE_SPI; while (priv->len) { len = zynqmp_qspi_calc_exp(priv, &gen_fifo_cmd); @@ -520,6 +558,66 @@ static int zynqmp_qspi_genfifo_fill_tx(struct zynqmp_qspi_priv *priv) return ret; } +static int zynqmp_qspi_start_io(struct zynqmp_qspi_priv *priv, + u32 gen_fifo_cmd, u32 *buf) +{ + u32 len; + u32 actuallen = priv->len; + u32 config_reg, ier, isr; + u32 timeout = GQSPI_TIMEOUT; + struct zynqmp_qspi_regs *regs = priv->regs; + u32 last_bits; + u32 *traverse = buf; + + while (priv->len) { + len = zynqmp_qspi_calc_exp(priv, &gen_fifo_cmd); + /* If exponent bit is set, reset immediate to be 2^len */ + if (gen_fifo_cmd & GQSPI_GFIFO_EXP_MASK) + priv->bytes_to_receive = (1 << len); + else + priv->bytes_to_receive = len; + zynqmp_qspi_fill_gen_fifo(priv, gen_fifo_cmd); + debug("GFIFO_CMD_RX:0x%x\n", gen_fifo_cmd); + /* Manual start */ + config_reg = readl(®s->confr); + config_reg |= GQSPI_STRT_GEN_FIFO; + writel(config_reg, ®s->confr); + /* Enable RX interrupts for IO mode */ + ier = readl(®s->ier); + ier |= GQSPI_IXR_ALL_MASK; + writel(ier, ®s->ier); + while (priv->bytes_to_receive && timeout) { + isr = readl(®s->isr); + if (isr & GQSPI_IXR_RXNEMTY_MASK) { + if (priv->bytes_to_receive >= 4) { + *traverse = readl(®s->drxr); + traverse++; + priv->bytes_to_receive -= 4; + } else { + last_bits = readl(®s->drxr); + memcpy(traverse, &last_bits, + priv->bytes_to_receive); + priv->bytes_to_receive = 0; + } + timeout = GQSPI_TIMEOUT; + } else { + udelay(1); + timeout--; + } + } + + debug("buf:0x%lx, rxbuf:0x%lx, *buf:0x%x len: 0x%x\n", + (unsigned long)buf, (unsigned long)priv->rx_buf, + *buf, actuallen); + if (!timeout) { + printf("IO timeout: %d\n", readl(®s->isr)); + return -1; + } + } + + return 0; +} + static int zynqmp_qspi_start_dma(struct zynqmp_qspi_priv *priv, u32 gen_fifo_cmd, u32 *buf) { @@ -572,16 +670,24 @@ static int zynqmp_qspi_genfifo_fill_rx(struct zynqmp_qspi_priv *priv) gen_fifo_cmd |= GQSPI_GFIFO_RX | GQSPI_GFIFO_DATA_XFR_MASK; - gen_fifo_cmd |= GQSPI_SPI_MODE_SPI; + if (last_cmd == SPINOR_OP_READ_1_1_4) + gen_fifo_cmd |= GQSPI_SPI_MODE_QSPI; + else if (last_cmd == SPINOR_OP_READ_1_1_2) + gen_fifo_cmd |= GQSPI_SPI_MODE_DUAL_SPI; + else + gen_fifo_cmd |= GQSPI_SPI_MODE_SPI; /* * Check if receive buffer is aligned to 4 byte and length * is multiples of four byte as we are using dma to receive. */ - if (!((unsigned long)priv->rx_buf & (GQSPI_DMA_ALIGN - 1)) && - !(actuallen % GQSPI_DMA_ALIGN)) { + if ((!((unsigned long)priv->rx_buf & (GQSPI_DMA_ALIGN - 1)) && + !(actuallen % GQSPI_DMA_ALIGN)) || priv->io_mode) { buf = (u32 *)priv->rx_buf; - return zynqmp_qspi_start_dma(priv, gen_fifo_cmd, buf); + if (priv->io_mode) + return zynqmp_qspi_start_io(priv, gen_fifo_cmd, buf); + else + return zynqmp_qspi_start_dma(priv, gen_fifo_cmd, buf); } ALLOC_CACHE_ALIGN_BUFFER(u8, tmp, roundup(priv->len, From patchwork Mon Jan 18 12:32:25 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ashok Reddy Soma X-Patchwork-Id: 1428121 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; 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DIR:OUT; SFP:1101; X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Jan 2021 12:33:31.7078 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b7fd26d1-00b5-41f9-25cd-08d8bbad4403 X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c; Ip=[149.199.62.198]; Helo=[xsj-pvapexch02.xlnx.xilinx.com] X-MS-Exchange-CrossTenant-AuthSource: CY1NAM02FT058.eop-nam02.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY4PR02MB2311 X-Mailman-Approved-At: Mon, 18 Jan 2021 13:34:57 +0100 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.3 at phobos.denx.de X-Virus-Status: Clean From: Siva Durga Prasad Paladugu There is no need of read modify write for tapdelay settings ans hence remove the read operations while setting tapdelays. Also, correct tapdelay value settings at 40MHZ by modifying the if check to <= instead of <. Signed-off-by: Siva Durga Prasad Paladugu Signed-off-by: Ashok Reddy Soma --- drivers/spi/zynqmp_gqspi.c | 27 +++++++++++---------------- 1 file changed, 11 insertions(+), 16 deletions(-) -- 2.17.1 This email and any attachments are intended for the sole use of the named recipient(s) and contain(s) confidential information that may be proprietary, privileged or copyrighted under applicable law. If you are not the intended recipient, do not read, copy, or forward this email message or any attachments. Delete this email message and any attachments immediately. diff --git a/drivers/spi/zynqmp_gqspi.c b/drivers/spi/zynqmp_gqspi.c index ae7b70aa57..136c20f09e 100644 --- a/drivers/spi/zynqmp_gqspi.c +++ b/drivers/spi/zynqmp_gqspi.c @@ -282,24 +282,19 @@ void zynqmp_qspi_set_tapdelay(struct udevice *bus, u32 baudrateval) debug("%s, req_hz:%d, clk_rate:%d, baudrateval:%d\n", __func__, reqhz, clk_rate, baudrateval); - if (reqhz < GQSPI_FREQ_40MHZ) { - zynqmp_mmio_read(IOU_TAPDLY_BYPASS_OFST, &tapdlybypass); - tapdlybypass |= (TAP_DLY_BYPASS_LQSPI_RX_VALUE << - TAP_DLY_BYPASS_LQSPI_RX_SHIFT); + if (reqhz <= GQSPI_FREQ_40MHZ) { + tapdlybypass = TAP_DLY_BYPASS_LQSPI_RX_VALUE << + TAP_DLY_BYPASS_LQSPI_RX_SHIFT; } else if (reqhz <= GQSPI_FREQ_100MHZ) { - zynqmp_mmio_read(IOU_TAPDLY_BYPASS_OFST, &tapdlybypass); - tapdlybypass |= (TAP_DLY_BYPASS_LQSPI_RX_VALUE << - TAP_DLY_BYPASS_LQSPI_RX_SHIFT); - lpbkdlyadj = readl(®s->lpbkdly); - lpbkdlyadj |= (GQSPI_LPBK_DLY_ADJ_LPBK_MASK); - datadlyadj = readl(®s->gqspidlyadj); - datadlyadj |= ((GQSPI_USE_DATA_DLY << GQSPI_USE_DATA_DLY_SHIFT) - | (GQSPI_DATA_DLY_ADJ_VALUE << - GQSPI_DATA_DLY_ADJ_SHIFT)); + tapdlybypass = TAP_DLY_BYPASS_LQSPI_RX_VALUE << + TAP_DLY_BYPASS_LQSPI_RX_SHIFT; + lpbkdlyadj = GQSPI_LPBK_DLY_ADJ_LPBK_MASK; + datadlyadj = (GQSPI_USE_DATA_DLY << GQSPI_USE_DATA_DLY_SHIFT) | + (GQSPI_DATA_DLY_ADJ_VALUE << + GQSPI_DATA_DLY_ADJ_SHIFT); } else if (reqhz <= GQSPI_FREQ_150MHZ) { - lpbkdlyadj = readl(®s->lpbkdly); - lpbkdlyadj |= ((GQSPI_LPBK_DLY_ADJ_LPBK_MASK) | - GQSPI_LPBK_DLY_ADJ_DLY_0); + lpbkdlyadj = GQSPI_LPBK_DLY_ADJ_LPBK_MASK | + GQSPI_LPBK_DLY_ADJ_DLY_0; } zynqmp_mmio_write(IOU_TAPDLY_BYPASS_OFST, IOU_TAPDLY_BYPASS_MASK, From patchwork Mon Jan 18 12:32:26 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ashok Reddy Soma X-Patchwork-Id: 1428122 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; 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Mon, 18 Jan 2021 04:33:39 -0800 Envelope-to: git@xilinx.com, jagan@amarulasolutions.com, ashok.409@gmail.com, u-boot@lists.denx.de, monstr@monstr.eu Received: from [172.23.64.106] (port=48331 helo=xhdvnc125.xilinx.com) by smtp.xilinx.com with esmtp (Exim 4.90) (envelope-from ) id 1l1Tj0-0004tw-V4; Mon, 18 Jan 2021 04:33:39 -0800 Received: by xhdvnc125.xilinx.com (Postfix, from userid 2896) id 62E8C1222D6; Mon, 18 Jan 2021 18:02:31 +0530 (IST) From: Ashok Reddy Soma To: CC: , , , , Ashok Reddy Soma Subject: [PATCH 5/7] spi: zynqmp_gqspi: Fix write issues in single mode Date: Mon, 18 Jan 2021 18:02:26 +0530 Message-ID: <1610973148-22465-6-git-send-email-ashok.reddy.soma@xilinx.com> X-Mailer: git-send-email 2.1.1 In-Reply-To: <1610973148-22465-1-git-send-email-ashok.reddy.soma@xilinx.com> References: <1610973148-22465-1-git-send-email-ashok.reddy.soma@xilinx.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-Office365-Filtering-HT: Tenant X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 95245c22-6d1b-4dbf-2397-08d8bbad4dae X-MS-TrafficTypeDiagnostic: BY5PR02MB6657: X-LD-Processed: 657af505-d5df-48d0-8300-c31994686c5c,ExtAddr X-Microsoft-Antispam-PRVS: X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-Oob-TLC-OOBClassifiers: OLM:6790; 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Enable manual start in zynqmp_qspi_fill_gen_fifo(). Also enable GQSPI_IXR_GFNFULL_MASK and check for it instead of GQSPI_IXR_GFEMTY_MASK. Signed-off-by: Ashok Reddy Soma --- drivers/spi/zynqmp_gqspi.c | 16 +++++++++++++++- 1 file changed, 15 insertions(+), 1 deletion(-) -- 2.17.1 This email and any attachments are intended for the sole use of the named recipient(s) and contain(s) confidential information that may be proprietary, privileged or copyrighted under applicable law. If you are not the intended recipient, do not read, copy, or forward this email message or any attachments. Delete this email message and any attachments immediately. diff --git a/drivers/spi/zynqmp_gqspi.c b/drivers/spi/zynqmp_gqspi.c index 136c20f09e..f50a7304ea 100644 --- a/drivers/spi/zynqmp_gqspi.c +++ b/drivers/spi/zynqmp_gqspi.c @@ -239,10 +239,21 @@ static void zynqmp_qspi_fill_gen_fifo(struct zynqmp_qspi_priv *priv, u32 gqspi_fifo_reg) { struct zynqmp_qspi_regs *regs = priv->regs; + u32 config_reg, ier; int ret = 0; + config_reg = readl(®s->confr); + /* Manual start if needed */ + config_reg |= GQSPI_STRT_GEN_FIFO; + writel(config_reg, ®s->confr); + + /* Enable interrupts */ + ier = readl(®s->ier); + ier |= GQSPI_IXR_GFNFULL_MASK; + writel(ier, ®s->ier); + /* Wait until the fifo is not full to write the new command */ - ret = wait_for_bit_le32(®s->isr, GQSPI_IXR_GFEMTY_MASK, 1, + ret = wait_for_bit_le32(®s->isr, GQSPI_IXR_GFNFULL_MASK, 1, GQSPI_TIMEOUT, 1); if (ret) printf("%s Timeout\n", __func__); @@ -265,6 +276,9 @@ static void zynqmp_qspi_chipselect(struct zynqmp_qspi_priv *priv, int is_on) debug("GFIFO_CMD_CS: 0x%x\n", gqspi_fifo_reg); + /* Dummy generic FIFO entry */ + zynqmp_qspi_fill_gen_fifo(priv, 0); + zynqmp_qspi_fill_gen_fifo(priv, gqspi_fifo_reg); } From patchwork Mon Jan 18 12:32:27 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ashok Reddy Soma X-Patchwork-Id: 1428123 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=xilinx.onmicrosoft.com header.i=@xilinx.onmicrosoft.com header.a=rsa-sha256 header.s=selector2-xilinx-onmicrosoft-com header.b=aP6rGnhf; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4DKB9C25YFz9sP7 for ; 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Mon, 18 Jan 2021 04:33:53 -0800 Envelope-to: git@xilinx.com, jagan@amarulasolutions.com, ashok.409@gmail.com, u-boot@lists.denx.de, monstr@monstr.eu Received: from [172.23.64.106] (port=48348 helo=xhdvnc125.xilinx.com) by smtp.xilinx.com with esmtp (Exim 4.90) (envelope-from ) id 1l1TjE-000071-1l; Mon, 18 Jan 2021 04:33:52 -0800 Received: by xhdvnc125.xilinx.com (Postfix, from userid 2896) id 6D9DB1222D7; Mon, 18 Jan 2021 18:02:31 +0530 (IST) From: Ashok Reddy Soma To: CC: , , , , Ashok Reddy Soma Subject: [PATCH 6/7] spi: zynqmp_gqspi: Add tap delays for Versal qspi Date: Mon, 18 Jan 2021 18:02:27 +0530 Message-ID: <1610973148-22465-7-git-send-email-ashok.reddy.soma@xilinx.com> X-Mailer: git-send-email 2.1.1 In-Reply-To: <1610973148-22465-1-git-send-email-ashok.reddy.soma@xilinx.com> References: <1610973148-22465-1-git-send-email-ashok.reddy.soma@xilinx.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-Office365-Filtering-HT: Tenant X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 98fa0607-f879-4834-603b-08d8bbad5250 X-MS-TrafficTypeDiagnostic: DM6PR02MB4425: X-LD-Processed: 657af505-d5df-48d0-8300-c31994686c5c,ExtAddr X-Microsoft-Antispam-PRVS: X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-Oob-TLC-OOBClassifiers: OLM:6108; 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DIR:OUT; SFP:1101; X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Jan 2021 12:33:55.7021 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 98fa0607-f879-4834-603b-08d8bbad5250 X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c; Ip=[149.199.62.198]; Helo=[xsj-pvapexch02.xlnx.xilinx.com] X-MS-Exchange-CrossTenant-AuthSource: CY1NAM02FT044.eop-nam02.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR02MB4425 X-Mailman-Approved-At: Mon, 18 Jan 2021 13:34:57 +0100 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.3 at phobos.denx.de X-Virus-Status: Clean This patch adds tap delays for qspi in Versal platform. Use IS_ENABLED() to address for ZynqMP and Versal and re-align the tapdelays code. Signed-off-by: Ashok Reddy Soma --- drivers/spi/zynqmp_gqspi.c | 54 ++++++++++++++++++++++++++------------ 1 file changed, 37 insertions(+), 17 deletions(-) -- 2.17.1 This email and any attachments are intended for the sole use of the named recipient(s) and contain(s) confidential information that may be proprietary, privileged or copyrighted under applicable law. If you are not the intended recipient, do not read, copy, or forward this email message or any attachments. Delete this email message and any attachments immediately. diff --git a/drivers/spi/zynqmp_gqspi.c b/drivers/spi/zynqmp_gqspi.c index f50a7304ea..e9726912b7 100644 --- a/drivers/spi/zynqmp_gqspi.c +++ b/drivers/spi/zynqmp_gqspi.c @@ -102,8 +102,10 @@ #define TAP_DLY_BYPASS_LQSPI_RX_VALUE 0x1 #define TAP_DLY_BYPASS_LQSPI_RX_SHIFT 2 #define GQSPI_DATA_DLY_ADJ_OFST 0x000001F8 -#define IOU_TAPDLY_BYPASS_OFST 0xFF180390 +#define IOU_TAPDLY_BYPASS_OFST !IS_ENABLED(CONFIG_ARCH_VERSAL) ? \ + 0xFF180390 : 0xF103003C #define GQSPI_LPBK_DLY_ADJ_LPBK_MASK 0x00000020 +#define GQSPI_FREQ_37_5MHZ 37500000 #define GQSPI_FREQ_40MHZ 40000000 #define GQSPI_FREQ_100MHZ 100000000 #define GQSPI_FREQ_150MHZ 150000000 @@ -296,23 +298,41 @@ void zynqmp_qspi_set_tapdelay(struct udevice *bus, u32 baudrateval) debug("%s, req_hz:%d, clk_rate:%d, baudrateval:%d\n", __func__, reqhz, clk_rate, baudrateval); - if (reqhz <= GQSPI_FREQ_40MHZ) { - tapdlybypass = TAP_DLY_BYPASS_LQSPI_RX_VALUE << - TAP_DLY_BYPASS_LQSPI_RX_SHIFT; - } else if (reqhz <= GQSPI_FREQ_100MHZ) { - tapdlybypass = TAP_DLY_BYPASS_LQSPI_RX_VALUE << - TAP_DLY_BYPASS_LQSPI_RX_SHIFT; - lpbkdlyadj = GQSPI_LPBK_DLY_ADJ_LPBK_MASK; - datadlyadj = (GQSPI_USE_DATA_DLY << GQSPI_USE_DATA_DLY_SHIFT) | - (GQSPI_DATA_DLY_ADJ_VALUE << - GQSPI_DATA_DLY_ADJ_SHIFT); - } else if (reqhz <= GQSPI_FREQ_150MHZ) { - lpbkdlyadj = GQSPI_LPBK_DLY_ADJ_LPBK_MASK | - GQSPI_LPBK_DLY_ADJ_DLY_0; + if (!IS_ENABLED(CONFIG_ARCH_VERSAL)) { + if (reqhz <= GQSPI_FREQ_40MHZ) { + tapdlybypass = TAP_DLY_BYPASS_LQSPI_RX_VALUE << + TAP_DLY_BYPASS_LQSPI_RX_SHIFT; + } else if (reqhz <= GQSPI_FREQ_100MHZ) { + tapdlybypass = TAP_DLY_BYPASS_LQSPI_RX_VALUE << + TAP_DLY_BYPASS_LQSPI_RX_SHIFT; + lpbkdlyadj = GQSPI_LPBK_DLY_ADJ_LPBK_MASK; + datadlyadj = (GQSPI_USE_DATA_DLY << + GQSPI_USE_DATA_DLY_SHIFT) | + (GQSPI_DATA_DLY_ADJ_VALUE << + GQSPI_DATA_DLY_ADJ_SHIFT); + } else if (reqhz <= GQSPI_FREQ_150MHZ) { + lpbkdlyadj = GQSPI_LPBK_DLY_ADJ_LPBK_MASK | + GQSPI_LPBK_DLY_ADJ_DLY_0; + } + zynqmp_mmio_write(IOU_TAPDLY_BYPASS_OFST, + IOU_TAPDLY_BYPASS_MASK, tapdlybypass); + } else { + if (reqhz <= GQSPI_FREQ_37_5MHZ) { + tapdlybypass = TAP_DLY_BYPASS_LQSPI_RX_VALUE << + TAP_DLY_BYPASS_LQSPI_RX_SHIFT; + } else if (reqhz <= GQSPI_FREQ_100MHZ) { + tapdlybypass = TAP_DLY_BYPASS_LQSPI_RX_VALUE << + TAP_DLY_BYPASS_LQSPI_RX_SHIFT; + lpbkdlyadj = GQSPI_LPBK_DLY_ADJ_LPBK_MASK; + datadlyadj = GQSPI_USE_DATA_DLY << + GQSPI_USE_DATA_DLY_SHIFT; + } else if (reqhz <= GQSPI_FREQ_150MHZ) { + lpbkdlyadj = GQSPI_LPBK_DLY_ADJ_LPBK_MASK | + (GQSPI_LPBK_DLY_ADJ_DLY_1 << + GQSPI_LPBK_DLY_ADJ_DLY_1_SHIFT); + } + writel(tapdlybypass, IOU_TAPDLY_BYPASS_OFST); } - - zynqmp_mmio_write(IOU_TAPDLY_BYPASS_OFST, IOU_TAPDLY_BYPASS_MASK, - tapdlybypass); writel(lpbkdlyadj, ®s->lpbkdly); writel(datadlyadj, ®s->gqspidlyadj); } From patchwork Mon Jan 18 12:32:28 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ashok Reddy Soma X-Patchwork-Id: 1428124 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; 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Mon, 18 Jan 2021 04:34:06 -0800 Envelope-to: git@xilinx.com, jagan@amarulasolutions.com, ashok.409@gmail.com, u-boot@lists.denx.de, monstr@monstr.eu Received: from [172.23.64.106] (port=48351 helo=xhdvnc125.xilinx.com) by smtp.xilinx.com with esmtp (Exim 4.90) (envelope-from ) id 1l1TjR-0004wX-L9; Mon, 18 Jan 2021 04:34:05 -0800 Received: by xhdvnc125.xilinx.com (Postfix, from userid 2896) id 7993A1222D8; Mon, 18 Jan 2021 18:02:31 +0530 (IST) From: Ashok Reddy Soma To: CC: , , , , T Karthik Reddy , "Ashok Reddy Soma" Subject: [PATCH 7/7] spi: zynqmp_gqspi: Update tapdelay value Date: Mon, 18 Jan 2021 18:02:28 +0530 Message-ID: <1610973148-22465-8-git-send-email-ashok.reddy.soma@xilinx.com> X-Mailer: git-send-email 2.1.1 In-Reply-To: <1610973148-22465-1-git-send-email-ashok.reddy.soma@xilinx.com> References: <1610973148-22465-1-git-send-email-ashok.reddy.soma@xilinx.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-Office365-Filtering-HT: Tenant X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: dc821a6d-8b3e-46cb-e8b2-08d8bbad5f88 X-MS-TrafficTypeDiagnostic: SJ0PR02MB7807: X-LD-Processed: 657af505-d5df-48d0-8300-c31994686c5c,ExtAddr X-Microsoft-Antispam-PRVS: X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-Oob-TLC-OOBClassifiers: OLM:4125; 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DIR:OUT; SFP:1101; X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Jan 2021 12:34:17.8835 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: dc821a6d-8b3e-46cb-e8b2-08d8bbad5f88 X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c; Ip=[149.199.62.198]; Helo=[xsj-pvapexch01.xlnx.xilinx.com] X-MS-Exchange-CrossTenant-AuthSource: CY1NAM02FT044.eop-nam02.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ0PR02MB7807 X-Mailman-Approved-At: Mon, 18 Jan 2021 13:34:57 +0100 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.3 at phobos.denx.de X-Virus-Status: Clean From: T Karthik Reddy Update GQSPI_LPBK_DLY_ADJ_DLY_1 tapdelay value for Versal for frequencies above 100MHz. Signed-off-by: T Karthik Reddy Signed-off-by: Ashok Reddy Soma --- drivers/spi/zynqmp_gqspi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.17.1 This email and any attachments are intended for the sole use of the named recipient(s) and contain(s) confidential information that may be proprietary, privileged or copyrighted under applicable law. If you are not the intended recipient, do not read, copy, or forward this email message or any attachments. Delete this email message and any attachments immediately. diff --git a/drivers/spi/zynqmp_gqspi.c b/drivers/spi/zynqmp_gqspi.c index e9726912b7..0771541e12 100644 --- a/drivers/spi/zynqmp_gqspi.c +++ b/drivers/spi/zynqmp_gqspi.c @@ -92,7 +92,7 @@ #define GQSPI_BAUD_DIV_SHIFT 2 #define GQSPI_LPBK_DLY_ADJ_LPBK_SHIFT 5 -#define GQSPI_LPBK_DLY_ADJ_DLY_1 0x2 +#define GQSPI_LPBK_DLY_ADJ_DLY_1 0x1 #define GQSPI_LPBK_DLY_ADJ_DLY_1_SHIFT 3 #define GQSPI_LPBK_DLY_ADJ_DLY_0 0x3 #define GQSPI_USE_DATA_DLY 0x1