From patchwork Tue Jan 9 14:46:21 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sebastian Perta X-Patchwork-Id: 857567 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-470552-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="p49m3OG1"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3zGFMc67Mdz9s7g for ; Wed, 10 Jan 2018 01:46:36 +1100 (AEDT) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:subject:date:message-id:mime-version:content-type :content-transfer-encoding; q=dns; s=default; b=WnxSyS9FtpQvdn29 LXZKDqOcJZmlrxrXfjRNZCaUjAsyE0aos5TcajTeViJlRSDeyP6eial+IeMfYflb kXqFw1uWNO6ZhULnrRWB7FyfWibreHAcVeppvdLFRMBGnqpKWOmBbiucqgXss4P2 7PXsCYO7YmTVu14qxvquX2S5oWo= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:subject:date:message-id:mime-version:content-type :content-transfer-encoding; s=default; bh=Y5hDuxOuYmz75nwSLbC3QS 0hvXk=; b=p49m3OG1VhS55lHsBMhkO0FfOchVJF2aexS3scW0+QlGZXGXLOs5hZ B69R3awjDk5VDsBKdLBXIjDfBG6HUQ3iKwD1g6N5Qyk+J7CsZLXR1MazzbQr3I7L P6EWnOoYNvZToAAgEz23QggaJAgPpct7egqCn8ic79PZlAhTfXWbI= Received: (qmail 59987 invoked by alias); 9 Jan 2018 14:46:29 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 59968 invoked by uid 89); 9 Jan 2018 14:46:28 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-11.1 required=5.0 tests=BAYES_00, GIT_PATCH_2, GIT_PATCH_3, KAM_ASCII_DIVIDERS, RCVD_IN_DNSWL_NONE, SPF_PASS, T_RP_MATCHES_RCVD autolearn=ham version=3.3.2 spammy=loop8c, loop-8.c, UD:loop-8.c, Hx-languages-length:4211 X-HELO: relmlie1.idc.renesas.com Received: from relmlor2.renesas.com (HELO relmlie1.idc.renesas.com) (210.160.252.172) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Tue, 09 Jan 2018 14:46:25 +0000 Received: from unknown (HELO relmlir3.idc.renesas.com) ([10.200.68.153]) by relmlie1.idc.renesas.com with ESMTP; 09 Jan 2018 23:46:22 +0900 Received: from relmlii2.idc.renesas.com (relmlii2.idc.renesas.com [10.200.68.66]) by relmlir3.idc.renesas.com (Postfix) with ESMTP id 375387AD00 for ; Tue, 9 Jan 2018 23:46:23 +0900 (JST) Received: from unknown (HELO REEBED03978) ([10.226.37.54]) by relmlii2.idc.renesas.com with ESMTP; 09 Jan 2018 23:46:22 +0900 From: "Sebastian Perta" To: Subject: [PATCH] RX movsicc degrade fix Date: Tue, 9 Jan 2018 14:46:21 -0000 Message-ID: <000301d38958$9e390260$daab0720$@renesas.com> MIME-Version: 1.0 Hello, In recent versions of GCC the define_expand "movsicc" has stopped being used by GCC (approx. 4.7.x/4.8.x onwards) The reason for this is that the first operand of if_then_else has SI mode and it shouldn't have. If we take a look at movsicc for all other targets we see this is true. The fix in rx.md is basically a copy paste from v850.md The patch also adds a testcase in gcc.target/rx to make sure this degrade does not occur again. Regression test is OK with one observation (see below), tested with the following command: make -k check-gcc RUNTESTFLAGS=--target_board=rx-sim I have the following fail (which was not present before): FAIL: gcc.dg/loop-8.c scan-rtl-dump-times loop2_invariant "Decided" 1 (found 0 times) This is because the patch is effective in this test case and the dump is not the same, I checked the asm code manually and it is OK. Is it possible to disable parts of a test case, not the whole test case (* { dg-final { scan-rtl-dump-times "Decided" 1 "loop2_invariant" } } */ from loop-8.c in this example) for a particular target? The total numbers of failures remains the same because the following FAIL is not present anymore with this patch: FAIL: gcc.dg/ifcvt-4.c scan-rtl-dump ce1 "2 true changes made" Please let me know if this is OK. Thank you! Best Regards, Sebastian Index: ChangeLog =================================================================== --- ChangeLog (revision 256382) +++ ChangeLog (working copy) @@ -1,3 +1,8 @@ +2018-01-09 Sebastian Perta + + *config/rx.md: updated "movsicc" expand to be matched by GCC + *testsuite/gcc.target/rx/movsicc.c: new test case + 2018-01-09 Richard Biener PR tree-optimization/83668 Index: config/rx/rx.md =================================================================== --- config/rx/rx.md (revision 256382) +++ config/rx/rx.md (working copy) @@ -733,12 +733,17 @@ (define_expand "movsicc" [(parallel [(set (match_operand:SI 0 "register_operand") - (if_then_else:SI (match_operand:SI 1 "comparison_operator") + (if_then_else:SI (match_operand 1 "comparison_operator") (match_operand:SI 2 "nonmemory_operand") (match_operand:SI 3 "nonmemory_operand"))) (clobber (reg:CC CC_REG))])] "" { + /* Make sure that we have an integer comparison... */ + if (GET_MODE (XEXP (operands[1], 0)) != CCmode + && GET_MODE (XEXP (operands[1], 0)) != SImode) + FAIL; + /* One operand must be a constant or a register, the other must be a register. */ if ( ! CONSTANT_P (operands[2]) && ! CONSTANT_P (operands[3]) Index: testsuite/gcc.target/rx/movsicc.c =================================================================== --- testsuite/gcc.target/rx/movsicc.c (nonexistent) +++ testsuite/gcc.target/rx/movsicc.c (working copy) @@ -0,0 +1,94 @@ +/* { dg-do compile } */ +/* { dg-options "-Os" } */ + +typedef unsigned char u8; +typedef unsigned short u16; +signed int Xa, Xb; + +signed int stzreg_beq(int i, int a, int b) +{ + signed int x; + x = a; + if (i) + x = b; + return x; +} + +/* { dg-final { scan-assembler "bne 1f" } } */ + +signed int stzreg_bge(int i, int a, int b, int c) +{ + signed int x; + x = a; + if (i0) + x = b; + return x; +} + +/* { dg-final { scan-assembler "bgt 1f" } } */ + +signed int stzreg_blt(int i, int a, int b) +{ + signed int x; + x = a; + if (i<0) + x = b; + return x; +} + +/* { dg-final { scan-assembler "blt 1f" } } */ + +signed int stzreg_bne(int i, int a, int b) +{ + signed int x; + x = a; + if (!i) + x = b; + return x; +} + +/* { dg-final { scan-assembler "beq 1f" } } */ + +signed int stzimm_le( int i, int a ) +{ + signed int x; + x = a; + if (i>0) + x = 5; + return x; +} + +/* { dg-final { scan-assembler "ble 1f" } } */ + +signed int stzimm_le_r( int i, int a ) +{ + signed int x; + x = a; + if (i<0) + x = 5; + return x; +} + +/* { dg-final { scan-assembler "bge 1f" } } */