From patchwork Fri Dec 11 21:54:25 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kun Yi X-Patchwork-Id: 1415284 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [203.11.71.2]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4Ct4Ns2wNsz9sVJ for ; Sat, 12 Dec 2020 08:56:13 +1100 (AEDT) Authentication-Results: ozlabs.org; dmarc=fail (p=reject dis=none) header.from=google.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=google.com header.i=@google.com header.a=rsa-sha256 header.s=20161025 header.b=qm2v6cfq; dkim-atps=neutral Received: from bilbo.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 4Ct4Ns0BvVzDqx4 for ; Sat, 12 Dec 2020 08:56:13 +1100 (AEDT) X-Original-To: openbmc@lists.ozlabs.org Delivered-To: openbmc@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=flex--kunyi.bounces.google.com (client-ip=2607:f8b0:4864:20::749; helo=mail-qk1-x749.google.com; envelope-from=3nertxwukb8yw6zaus00sxq.o0y01qznyoxu454.0bxmn4.03s@flex--kunyi.bounces.google.com; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=pass (p=reject dis=none) header.from=google.com Authentication-Results: lists.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=google.com header.i=@google.com header.a=rsa-sha256 header.s=20161025 header.b=qm2v6cfq; dkim-atps=neutral Received: from mail-qk1-x749.google.com (mail-qk1-x749.google.com [IPv6:2607:f8b0:4864:20::749]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 4Ct4M84t3PzDqxB for ; Sat, 12 Dec 2020 08:54:40 +1100 (AEDT) Received: by mail-qk1-x749.google.com with SMTP id 198so7606192qkj.7 for ; Fri, 11 Dec 2020 13:54:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20161025; h=sender:date:in-reply-to:message-id:mime-version:references:subject :from:to:cc; bh=azmHzao3wgetMgbO3ArvMbnmF5zPZ91D/Nr3cEx209E=; b=qm2v6cfqU3Muvk3jYMjn9k9VoOyLkwbmnsZrh42mICnoNAo34l+/Hp4sfoqrBe2qIT 4JAxYzGHaJIw1I/hkYHtEEVotNPkm7I2fivmj6y/hMbDwP4M1CRoe5YUGWmZOlDcgya7 H5Be4c5xOySR81joyYiP2sUJTD2ZbWi+Rzu35EcQRMn/XCcc1ciGdOGB/1gYRaW4qC5e dHOuiNKzeaoXR+fBXEkUehC2Z24QGE5li9/P3FSyzQ8rmYAjKqFz4sKRYRKojAxdNW1n U5t0dDYAaLv/huGPfP60shoBwHqhOAOh5JKWFPGJa3EdoLO6/wca33nF9pfMgICIde0R jtRA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:date:in-reply-to:message-id:mime-version :references:subject:from:to:cc; bh=azmHzao3wgetMgbO3ArvMbnmF5zPZ91D/Nr3cEx209E=; b=uUSks2DOKT6jSnfCXHzHpN97900YGq23gJ8g9aWBQ7knF3nzcj9atFgNd75omJu40q WgsBcbpdtP6IbJMqGyj5Bp4hJYCju9s4PyUdvS+IZcwXs8234Wu21gwVjOzlEpTYZXN/ DUZEgYlu549UBlfLlUaYRdECWcWG4A50EnmDH2INGDRf4hrP9gTolHAGJwgkUSpA+TiO 9rCnAngbTqumkEyV+/vEHC3q4ihK0XWdH/BJZL9FfAOO+1TdGNGQq8qtHxiYPwf7m8fl qTqtgcitemRxcypq25pOC+8szFLq+ZShw7rcOnx+cMhPxoYzB20q7E2HDXT97OBUAlDT KT/w== X-Gm-Message-State: AOAM532D7FygadtPFHLYpxDt4PmZloglm77uCqiq6kLVbjxXMJ3y5FMe v9S8AMTlqFdC7vNc51OLsLLeR6QJCQ== X-Google-Smtp-Source: ABdhPJyek/ka7dtWEUljaiwnn+TTYfv1T2Dgvd2YsdagY/nGVxVPUiXaKj0VJcikfz3Atzm2GBppEAMgLA== X-Received: from kunyi0.svl.corp.google.com ([2620:15c:2c5:3:9657:a5ff:fef2:53bd]) (user=kunyi job=sendgmr) by 2002:a0c:8601:: with SMTP id p1mr9257861qva.22.1607723677330; Fri, 11 Dec 2020 13:54:37 -0800 (PST) Date: Fri, 11 Dec 2020 13:54:25 -0800 In-Reply-To: <20201211215427.3281681-1-kunyi@google.com> Message-Id: <20201211215427.3281681-2-kunyi@google.com> Mime-Version: 1.0 References: <20201211215427.3281681-1-kunyi@google.com> X-Mailer: git-send-email 2.29.2.684.gfbc64c5ab5-goog Subject: [PATCH linux hwmon-next v5 1/3] hwmon: (sbtsi) Add basic support for SB-TSI sensors From: Kun Yi To: jdelvare@suse.com, linux@roeck-us.net, robh+dt@kernel.org, mark.rutland@arm.com, supreeth.venkatesh@amd.com X-BeenThere: openbmc@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Development list for OpenBMC List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-hwmon@vger.kernel.org, devicetree@vger.kernel.org, openbmc@lists.ozlabs.org, linux-kernel@vger.kernel.org Errors-To: openbmc-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "openbmc" SB Temperature Sensor Interface (SB-TSI) is an SMBus compatible interface that reports AMD SoC's Ttcl (normalized temperature), and resembles a typical 8-pin remote temperature sensor's I2C interface to BMC. This commit adds basic support using this interface to read CPU temperature, and read/write high/low CPU temp thresholds. To instantiate this driver on an AMD CPU with SB-TSI support, the i2c bus number would be the bus connected from the board management controller (BMC) to the CPU. The i2c address is specified in Section 6.3.1 of the spec [1]: The SB-TSI address is normally 98h for socket 0 and 90h for socket 1, but it could vary based on hardware address select pins. [1]: https://www.amd.com/system/files/TechDocs/56255_OSRR.pdf Test status: tested reading temp1_input, and reading/writing temp1_max/min. Signed-off-by: Kun Yi --- drivers/hwmon/Kconfig | 10 ++ drivers/hwmon/Makefile | 1 + drivers/hwmon/sbtsi_temp.c | 250 +++++++++++++++++++++++++++++++++++++ 3 files changed, 261 insertions(+) create mode 100644 drivers/hwmon/sbtsi_temp.c diff --git a/drivers/hwmon/Kconfig b/drivers/hwmon/Kconfig index 3c059fc23cd6..3d6a809700ae 100644 --- a/drivers/hwmon/Kconfig +++ b/drivers/hwmon/Kconfig @@ -1522,6 +1522,16 @@ config SENSORS_SL28CPLD This driver can also be built as a module. If so, the module will be called sl28cpld-hwmon. +config SENSORS_SBTSI + tristate "Emulated SB-TSI temperature sensor" + depends on I2C + help + If you say yes here you get support for emulated temperature + sensors on AMD SoCs with SB-TSI interface connected to a BMC device. + + This driver can also be built as a module. If so, the module will + be called sbtsi_temp. + config SENSORS_SHT15 tristate "Sensiron humidity and temperature sensors. SHT15 and compat." depends on GPIOLIB || COMPILE_TEST diff --git a/drivers/hwmon/Makefile b/drivers/hwmon/Makefile index 01ca5d3fbad4..ee8c037919da 100644 --- a/drivers/hwmon/Makefile +++ b/drivers/hwmon/Makefile @@ -160,6 +160,7 @@ obj-$(CONFIG_SENSORS_POWR1220) += powr1220.o obj-$(CONFIG_SENSORS_PWM_FAN) += pwm-fan.o obj-$(CONFIG_SENSORS_RASPBERRYPI_HWMON) += raspberrypi-hwmon.o obj-$(CONFIG_SENSORS_S3C) += s3c-hwmon.o +obj-$(CONFIG_SENSORS_SBTSI) += sbtsi_temp.o obj-$(CONFIG_SENSORS_SCH56XX_COMMON)+= sch56xx-common.o obj-$(CONFIG_SENSORS_SCH5627) += sch5627.o obj-$(CONFIG_SENSORS_SCH5636) += sch5636.o diff --git a/drivers/hwmon/sbtsi_temp.c b/drivers/hwmon/sbtsi_temp.c new file mode 100644 index 000000000000..e35357c48b8e --- /dev/null +++ b/drivers/hwmon/sbtsi_temp.c @@ -0,0 +1,250 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * sbtsi_temp.c - hwmon driver for a SBI Temperature Sensor Interface (SB-TSI) + * compliant AMD SoC temperature device. + * + * Copyright (c) 2020, Google Inc. + * Copyright (c) 2020, Kun Yi + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +/* + * SB-TSI registers only support SMBus byte data access. "_INT" registers are + * the integer part of a temperature value or limit, and "_DEC" registers are + * corresponding decimal parts. + */ +#define SBTSI_REG_TEMP_INT 0x01 /* RO */ +#define SBTSI_REG_STATUS 0x02 /* RO */ +#define SBTSI_REG_CONFIG 0x03 /* RO */ +#define SBTSI_REG_TEMP_HIGH_INT 0x07 /* RW */ +#define SBTSI_REG_TEMP_LOW_INT 0x08 /* RW */ +#define SBTSI_REG_TEMP_DEC 0x10 /* RW */ +#define SBTSI_REG_TEMP_HIGH_DEC 0x13 /* RW */ +#define SBTSI_REG_TEMP_LOW_DEC 0x14 /* RW */ + +#define SBTSI_CONFIG_READ_ORDER_SHIFT 5 + +#define SBTSI_TEMP_MIN 0 +#define SBTSI_TEMP_MAX 255875 + +/* Each client has this additional data */ +struct sbtsi_data { + struct i2c_client *client; + struct mutex lock; +}; + +/* + * From SB-TSI spec: CPU temperature readings and limit registers encode the + * temperature in increments of 0.125 from 0 to 255.875. The "high byte" + * register encodes the base-2 of the integer portion, and the upper 3 bits of + * the "low byte" encode in base-2 the decimal portion. + * + * e.g. INT=0x19, DEC=0x20 represents 25.125 degrees Celsius + * + * Therefore temperature in millidegree Celsius = + * (INT + DEC / 256) * 1000 = (INT * 8 + DEC / 32) * 125 + */ +static inline int sbtsi_reg_to_mc(s32 integer, s32 decimal) +{ + return ((integer << 3) + (decimal >> 5)) * 125; +} + +/* + * Inversely, given temperature in millidegree Celsius + * INT = (TEMP / 125) / 8 + * DEC = ((TEMP / 125) % 8) * 32 + * Caller have to make sure temp doesn't exceed 255875, the max valid value. + */ +static inline void sbtsi_mc_to_reg(s32 temp, u8 *integer, u8 *decimal) +{ + temp /= 125; + *integer = temp >> 3; + *decimal = (temp & 0x7) << 5; +} + +static int sbtsi_read(struct device *dev, enum hwmon_sensor_types type, + u32 attr, int channel, long *val) +{ + struct sbtsi_data *data = dev_get_drvdata(dev); + s32 temp_int, temp_dec; + int err; + + switch (attr) { + case hwmon_temp_input: + /* + * ReadOrder bit specifies the reading order of integer and + * decimal part of CPU temp for atomic reads. If bit == 0, + * reading integer part triggers latching of the decimal part, + * so integer part should be read first. If bit == 1, read + * order should be reversed. + */ + err = i2c_smbus_read_byte_data(data->client, SBTSI_REG_CONFIG); + if (err < 0) + return err; + + mutex_lock(&data->lock); + if (err & BIT(SBTSI_CONFIG_READ_ORDER_SHIFT)) { + temp_dec = i2c_smbus_read_byte_data(data->client, SBTSI_REG_TEMP_DEC); + temp_int = i2c_smbus_read_byte_data(data->client, SBTSI_REG_TEMP_INT); + } else { + temp_int = i2c_smbus_read_byte_data(data->client, SBTSI_REG_TEMP_INT); + temp_dec = i2c_smbus_read_byte_data(data->client, SBTSI_REG_TEMP_DEC); + } + mutex_unlock(&data->lock); + break; + case hwmon_temp_max: + mutex_lock(&data->lock); + temp_int = i2c_smbus_read_byte_data(data->client, SBTSI_REG_TEMP_HIGH_INT); + temp_dec = i2c_smbus_read_byte_data(data->client, SBTSI_REG_TEMP_HIGH_DEC); + mutex_unlock(&data->lock); + break; + case hwmon_temp_min: + mutex_lock(&data->lock); + temp_int = i2c_smbus_read_byte_data(data->client, SBTSI_REG_TEMP_LOW_INT); + temp_dec = i2c_smbus_read_byte_data(data->client, SBTSI_REG_TEMP_LOW_DEC); + mutex_unlock(&data->lock); + break; + default: + return -EINVAL; + } + + + if (temp_int < 0) + return temp_int; + if (temp_dec < 0) + return temp_dec; + + *val = sbtsi_reg_to_mc(temp_int, temp_dec); + + return 0; +} + +static int sbtsi_write(struct device *dev, enum hwmon_sensor_types type, + u32 attr, int channel, long val) +{ + struct sbtsi_data *data = dev_get_drvdata(dev); + int reg_int, reg_dec, err; + u8 temp_int, temp_dec; + + switch (attr) { + case hwmon_temp_max: + reg_int = SBTSI_REG_TEMP_HIGH_INT; + reg_dec = SBTSI_REG_TEMP_HIGH_DEC; + break; + case hwmon_temp_min: + reg_int = SBTSI_REG_TEMP_LOW_INT; + reg_dec = SBTSI_REG_TEMP_LOW_DEC; + break; + default: + return -EINVAL; + } + + val = clamp_val(val, SBTSI_TEMP_MIN, SBTSI_TEMP_MAX); + sbtsi_mc_to_reg(val, &temp_int, &temp_dec); + + mutex_lock(&data->lock); + err = i2c_smbus_write_byte_data(data->client, reg_int, temp_int); + if (err) + goto exit; + + err = i2c_smbus_write_byte_data(data->client, reg_dec, temp_dec); +exit: + mutex_unlock(&data->lock); + return err; +} + +static umode_t sbtsi_is_visible(const void *data, + enum hwmon_sensor_types type, + u32 attr, int channel) +{ + switch (type) { + case hwmon_temp: + switch (attr) { + case hwmon_temp_input: + return 0444; + case hwmon_temp_min: + return 0644; + case hwmon_temp_max: + return 0644; + } + break; + default: + break; + } + return 0; +} + +static const struct hwmon_channel_info *sbtsi_info[] = { + HWMON_CHANNEL_INFO(chip, HWMON_C_REGISTER_TZ), + HWMON_CHANNEL_INFO(temp, HWMON_T_INPUT | HWMON_T_MIN | HWMON_T_MAX), + NULL +}; + +static const struct hwmon_ops sbtsi_hwmon_ops = { + .is_visible = sbtsi_is_visible, + .read = sbtsi_read, + .write = sbtsi_write, +}; + +static const struct hwmon_chip_info sbtsi_chip_info = { + .ops = &sbtsi_hwmon_ops, + .info = sbtsi_info, +}; + +static int sbtsi_probe(struct i2c_client *client, + const struct i2c_device_id *id) +{ + struct device *dev = &client->dev; + struct device *hwmon_dev; + struct sbtsi_data *data; + + data = devm_kzalloc(dev, sizeof(struct sbtsi_data), GFP_KERNEL); + if (!data) + return -ENOMEM; + + data->client = client; + mutex_init(&data->lock); + + hwmon_dev = devm_hwmon_device_register_with_info(dev, client->name, data, &sbtsi_chip_info, + NULL); + + return PTR_ERR_OR_ZERO(hwmon_dev); +} + +static const struct i2c_device_id sbtsi_id[] = { + {"sbtsi", 0}, + {} +}; +MODULE_DEVICE_TABLE(i2c, sbtsi_id); + +static const struct of_device_id __maybe_unused sbtsi_of_match[] = { + { + .compatible = "amd,sbtsi", + }, + { }, +}; +MODULE_DEVICE_TABLE(of, sbtsi_of_match); + +static struct i2c_driver sbtsi_driver = { + .class = I2C_CLASS_HWMON, + .driver = { + .name = "sbtsi", + .of_match_table = of_match_ptr(sbtsi_of_match), + }, + .probe = sbtsi_probe, + .id_table = sbtsi_id, +}; + +module_i2c_driver(sbtsi_driver); + +MODULE_AUTHOR("Kun Yi "); +MODULE_DESCRIPTION("Hwmon driver for AMD SB-TSI emulated sensor"); +MODULE_LICENSE("GPL"); From patchwork Fri Dec 11 21:54:26 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kun Yi X-Patchwork-Id: 1415286 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4Ct4Pr2dSsz9sVJ for ; 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a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:date:in-reply-to:message-id:mime-version :references:subject:from:to:cc; bh=NTgAB1mD14VMd3H1Bqnr5TwzQles0E7KUIMRK7pxIo4=; b=rmQGN7E0Mj+QSsXSWDAn820Ey+cHQSqYSWZJbu8cMwVAkDmvd+9AQC/1Jcm/4ue/eu rhHOCs0dnqII7vGWahgISEAnEUSes/msRaPLtn1GJaMb7hvZKPQezT80GWlR3lAfnPZY 0tOEFKO6Y6+hg7C6YLI1VJG4/HC/u29q4uoOxZZmgkZssCNZ1b9/4XA3CX51kPwHIRb1 alXFyFl6Yl8U06TQdQChveFhjs5ry9dZpUSkkfKsj4RczEVlWd+nYSI2Uvjj12Dx/xP4 2S3WHMcIVKTc0qWz2apzIuj9Oa2+ecUmkyhAm2+20fJ/NYWf1bx33GK5O1NT8Iusw8Tj b9wg== X-Gm-Message-State: AOAM532j8Z6gbwBRnjpdc3j0um4bfSwT6sCRrnKM+FmvNZbfEpwHcDbo jF2R+om2kTOQO+w7DwQWqegxo93bsw== X-Google-Smtp-Source: ABdhPJyVa+Y3FutrLWi8X1KGlRYrBlVNq40nJupQDbBYEPgST1GAmYH1QW4XMUiAfDuET0G/NH3iztLh+Q== X-Received: from kunyi0.svl.corp.google.com ([2620:15c:2c5:3:9657:a5ff:fef2:53bd]) (user=kunyi job=sendgmr) by 2002:a0c:bd2b:: with SMTP id m43mr17844211qvg.32.1607723679283; Fri, 11 Dec 2020 13:54:39 -0800 (PST) Date: Fri, 11 Dec 2020 13:54:26 -0800 In-Reply-To: <20201211215427.3281681-1-kunyi@google.com> Message-Id: <20201211215427.3281681-3-kunyi@google.com> Mime-Version: 1.0 References: <20201211215427.3281681-1-kunyi@google.com> X-Mailer: git-send-email 2.29.2.684.gfbc64c5ab5-goog Subject: [PATCH linux hwmon-next v5 2/3] hwmon: (sbtsi) Add documentation From: Kun Yi To: jdelvare@suse.com, linux@roeck-us.net, robh+dt@kernel.org, mark.rutland@arm.com, supreeth.venkatesh@amd.com X-BeenThere: openbmc@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Development list for OpenBMC List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-hwmon@vger.kernel.org, devicetree@vger.kernel.org, openbmc@lists.ozlabs.org, linux-kernel@vger.kernel.org Errors-To: openbmc-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "openbmc" Document the SB-TSI sensor interface driver. Signed-off-by: Kun Yi --- Documentation/hwmon/index.rst | 1 + Documentation/hwmon/sbtsi_temp.rst | 40 ++++++++++++++++++++++++++++++ 2 files changed, 41 insertions(+) create mode 100644 Documentation/hwmon/sbtsi_temp.rst diff --git a/Documentation/hwmon/index.rst b/Documentation/hwmon/index.rst index fd6fae46b99c..509fb3bcafb2 100644 --- a/Documentation/hwmon/index.rst +++ b/Documentation/hwmon/index.rst @@ -151,6 +151,7 @@ Hardware Monitoring Kernel Drivers pxe1610 pwm-fan raspberrypi-hwmon + sbtsi_temp sch5627 sch5636 scpi-hwmon diff --git a/Documentation/hwmon/sbtsi_temp.rst b/Documentation/hwmon/sbtsi_temp.rst new file mode 100644 index 000000000000..9f0f197c8aa2 --- /dev/null +++ b/Documentation/hwmon/sbtsi_temp.rst @@ -0,0 +1,40 @@ +Kernel driver sbtsi_temp +================== + +Supported hardware: + + * Sideband interface (SBI) Temperature Sensor Interface (SB-TSI) + compliant AMD SoC temperature device. + + Prefix: 'sbtsi_temp' + + Addresses scanned: This driver doesn't support address scanning. + + To instantiate this driver on an AMD CPU with SB-TSI + support, the i2c bus number would be the bus connected from the board + management controller (BMC) to the CPU. The i2c address is specified in + Section 6.3.1 of the SoC register reference: The SB-TSI address is normally + 98h for socket 0 and 90h for socket 1, but it could vary based on hardware + address select pins. + + Datasheet: The SB-TSI interface and protocol is available as part of + the open source SoC register reference at: + + https://www.amd.com/system/files/TechDocs/56255_OSRR.pdf + + The Advanced Platform Management Link (APML) Specification is + available at: + + http://developer.amd.com/wordpress/media/2012/10/41918.pdf + +Author: Kun Yi + +Description +----------- + +The SBI temperature sensor interface (SB-TSI) is an emulation of the software +and physical interface of a typical 8-pin remote temperature sensor (RTS) on +AMD SoCs. It implements one temperature sensor with readings and limit +registers encode the temperature in increments of 0.125 from 0 to 255.875. +Limits can be set through the writable thresholds, and if reached will trigger +corresponding alert signals. From patchwork Fri Dec 11 21:54:27 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kun Yi X-Patchwork-Id: 1415293 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [203.11.71.2]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4Ct4TW2TMGz9sTL for ; Sat, 12 Dec 2020 09:00:15 +1100 (AEDT) Authentication-Results: ozlabs.org; dmarc=fail (p=reject dis=none) header.from=google.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=google.com header.i=@google.com header.a=rsa-sha256 header.s=20161025 header.b=gcJ3yqiJ; dkim-atps=neutral Received: from bilbo.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 4Ct4TW1Z6pzDqxD for ; Sat, 12 Dec 2020 09:00:15 +1100 (AEDT) X-Original-To: openbmc@lists.ozlabs.org Delivered-To: openbmc@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=flex--kunyi.bounces.google.com (client-ip=2607:f8b0:4864:20::549; helo=mail-pg1-x549.google.com; envelope-from=3oertxwukb8o0a3eyw44w1u.s4245u3r2s1y898.4f1qr8.47w@flex--kunyi.bounces.google.com; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=pass (p=reject dis=none) header.from=google.com Authentication-Results: lists.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=google.com header.i=@google.com header.a=rsa-sha256 header.s=20161025 header.b=gcJ3yqiJ; dkim-atps=neutral Received: from mail-pg1-x549.google.com (mail-pg1-x549.google.com [IPv6:2607:f8b0:4864:20::549]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 4Ct4MG48m6zDqwt for ; Sat, 12 Dec 2020 08:54:44 +1100 (AEDT) Received: by mail-pg1-x549.google.com with SMTP id 139so4241312pgd.11 for ; Fri, 11 Dec 2020 13:54:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20161025; h=sender:date:in-reply-to:message-id:mime-version:references:subject :from:to:cc; bh=Rd2S5ERIdpxDDi+uhK9cbjd0vF+3SVBwWriC0JcpU0w=; b=gcJ3yqiJW+gv6J7pXNellIYo6U1XVjhUnAoDf0KYKfq8Z48dh+sC5vdboDhaA2v7dc TKPgf+FFKcXPFTbfqrq3TZp01YbZ147AAU0vwFHu8SfF2JhCRMLpGdxGICdULZXprzIq IMZL836rPQhkRoipkuUo31PvlOYVa8pUzX+n9sl6YngFpIAVx79gvPRp4Lx5FSu5AJmG sCq5Ip77METDR0YTxE6GT9fvcLTLai4M7/mZdFkFyMW1SD+19yBv+BYHks232/kn5p9D SMKLWXUc3ZgueHEpv2jAFW16BYFIAtV2wa0G1NykSQM9veoT26ODprUixchAnkEjKgEj j/ow== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:date:in-reply-to:message-id:mime-version :references:subject:from:to:cc; bh=Rd2S5ERIdpxDDi+uhK9cbjd0vF+3SVBwWriC0JcpU0w=; b=lky+hDC8IOvg7Irdx2DWioQOeuAguf/e+15T9B8JyUdcp7WqYlJBCfoZH1iX8god3i ur8TYOFKA7uhtbH23314RkuQRlAkUvKlkwsCYSixwc3i0totHSdM+GPg4p2KZh7tYlGL LxYeARk5OMRZCJhPAJTuEzkUzhC1XJsCbetiSLDYf+/qjHa0iiDlfbNQOdzEAVFNR/nI jqoOtwDt/8wS2JkKUtWk5qZ82FoqL8wwIBPT1Sy4U28E6ILWnVNxx7QWY/kaZb/Zc2r2 G7XLMeIX/smx8YGHV+jdV2avWHfEMf44YtJM/+FwLOUJUL/tmqv2u12B5e6NSqmE3aXd 7w3Q== X-Gm-Message-State: AOAM532aqqv5f5m4dato8rToYFXM46fSn44A/glqwVLusWqAOhVnUJh+ PE5p0wBOVtytoQ5jW7pstUqf5fKUng== X-Google-Smtp-Source: ABdhPJxUhEx4SmtYdScxsFigf7h0fO4fVDEuEiEtJX/93EAJekijNmsU2fzEHRMav02QofkK1LRhvKb0Gw== X-Received: from kunyi0.svl.corp.google.com ([2620:15c:2c5:3:9657:a5ff:fef2:53bd]) (user=kunyi job=sendgmr) by 2002:a17:90a:4dcd:: with SMTP id r13mr14803802pjl.74.1607723681302; Fri, 11 Dec 2020 13:54:41 -0800 (PST) Date: Fri, 11 Dec 2020 13:54:27 -0800 In-Reply-To: <20201211215427.3281681-1-kunyi@google.com> Message-Id: <20201211215427.3281681-4-kunyi@google.com> Mime-Version: 1.0 References: <20201211215427.3281681-1-kunyi@google.com> X-Mailer: git-send-email 2.29.2.684.gfbc64c5ab5-goog Subject: [PATCH linux hwmon-next v5 3/3] dt-bindings: (hwmon/sbtsi_tmep) Add SB-TSI hwmon driver bindings From: Kun Yi To: jdelvare@suse.com, linux@roeck-us.net, robh+dt@kernel.org, mark.rutland@arm.com, supreeth.venkatesh@amd.com X-BeenThere: openbmc@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Development list for OpenBMC List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-hwmon@vger.kernel.org, devicetree@vger.kernel.org, openbmc@lists.ozlabs.org, linux-kernel@vger.kernel.org Errors-To: openbmc-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "openbmc" Document device tree bindings for AMD SB-TSI emulated temperature sensor. Signed-off-by: Kun Yi --- .../devicetree/bindings/hwmon/amd,sbtsi.yaml | 54 +++++++++++++++++++ 1 file changed, 54 insertions(+) create mode 100644 Documentation/devicetree/bindings/hwmon/amd,sbtsi.yaml diff --git a/Documentation/devicetree/bindings/hwmon/amd,sbtsi.yaml b/Documentation/devicetree/bindings/hwmon/amd,sbtsi.yaml new file mode 100644 index 000000000000..446b09f1ce94 --- /dev/null +++ b/Documentation/devicetree/bindings/hwmon/amd,sbtsi.yaml @@ -0,0 +1,54 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/hwmon/amd,sbtsi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: > + Sideband interface Temperature Sensor Interface (SB-TSI) compliant + AMD SoC temperature device + +maintainers: + - Kun Yi + - Supreeth Venkatesh + +description: | + SB Temperature Sensor Interface (SB-TSI) is an SMBus compatible + interface that reports AMD SoC's Ttcl (normalized temperature), + and resembles a typical 8-pin remote temperature sensor's I2C interface + to BMC. The emulated thermal sensor can report temperatures in increments + of 0.125 degrees, ranging from 0 to 255.875. + +properties: + compatible: + enum: + - amd,sbtsi + + reg: + maxItems: 1 + description: | + I2C bus address of the device as specified in Section 6.3.1 of the + SoC register reference. The SB-TSI address is normally 98h for socket + 0 and 90h for socket 1, but it could vary based on hardware address + select pins. + \[open source SoC register reference\] + https://www.amd.com/system/files/TechDocs/56255_OSRR.pdf + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + i2c0 { + #address-cells = <1>; + #size-cells = <0>; + + sbtsi@4c { + compatible = "amd,sbtsi"; + reg = <0x4c>; + }; + }; +...