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bh=cReaVm9fYOWRrc4duWcmr2k4Q2XdMR8IUxaxdvGTBSE=; b=mW0ogY7NHbCZv9I0fnJhOanCl/N1Qr22+pX0NC2EkMB8zpsqi6AHH9p1b9aeM9spFl Ivr/d+jxgBMYVgR+Ul8tqEMjTL762bRZ77icGcAJ5sw1kTePWm/uDdaKgO0dIRZsv45Q SSV2TgPnYiLJPmOK4h4zFLTur0udf13afuZBu+wQp3dlnkPQun0/9nhprpnrrT5jLjL6 CGBUguGZUyFiClDsly7YqY7P6dhM4IhfEmwz1gZZeRaFVFyCqQKBqVBNPotJvDmZ3k1S FL+phaOe+ZAlgB0/YWSGQacSUEnWLgidwGcWNv8sbvv1VIj/UDSD72106PvtITEIQE2T gJMg== X-Gm-Message-State: AOAM530A5wsBqN60ChhqbBxxgfV/hjKBcCt7Y3M03j5BRX2MAsCgXDKM 6Hu9gNyy3csQJcyKHDA4pq2AW6C/Kf/f+hvMsTEgPql8Yfg= X-Google-Smtp-Source: ABdhPJwTYH7K1GmVx60rEXvfPJMkPvmXgaDNuB1hgagP1BviCmxWsaIR9Jj04mc8kbq3KrMreto+fQUl9JO0m44J5Mo= X-Received: by 2002:ab0:4381:: with SMTP id l1mr3087157ual.116.1607387558031; Mon, 07 Dec 2020 16:32:38 -0800 (PST) MIME-Version: 1.0 From: Alessandro Temil Date: Mon, 7 Dec 2020 16:32:26 -0800 Message-ID: Subject: [PATCH] drivers/net: Add support for 10G Base-R IP core version to xilinx_axi_enet driver To: u-boot@lists.denx.de Cc: joe.hershberger@ni.com, michal.simek@xilinx.com, ashok.reddy.soma@xilinx.com, rfried.dev@gmail.com X-Mailman-Approved-At: Tue, 08 Dec 2020 01:53:34 +0100 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: atemil@waymo.com Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.3 at phobos.denx.de X-Virus-Status: Clean @@ -217,6 +244,8 @@ static u32 phyread(struct axidma_priv *priv, u32 phyaddress, u32 registernum, static u32 phywrite(struct axidma_priv *priv, u32 phyaddress, u32 registernum, u32 data) { + if (priv->mactype == EMAC_10G_25G) return 0; + struct axi_regs *regs = priv->iobase; u32 mdioctrlreg = 0; @@ -374,6 +403,29 @@ static void axiemac_stop(struct udevice *dev) debug("axiemac: Halted\n"); } +static int xxv_axi_ethernet_init(struct axidma_priv *priv) +{ + struct xxv_axi_regs *regs = priv->iobase; + + int val = readl(®s->rcw1) & ~XXV_RCW1_FCS_MASK; + val |= XXV_RCW1_FCS_MASK; + writel(val, ®s->rcw1); + + val = readl(®s->tc) & ~XXV_TC_FCS_MASK; + val |= XXV_TC_FCS_MASK; + writel(val, ®s->tc); + + val = readl(®s->tc) & ~XXV_TC_TX_MASK; + val |= XXV_TC_TX_MASK; + writel(val, ®s->tc); + + val = readl(®s->rcw1) & ~XXV_RCW1_RX_MASK; + val |= XXV_RCW1_RX_MASK; + writel(val, ®s->rcw1); + + return 0; +} + static int axi_ethernet_init(struct axidma_priv *priv) { struct axi_regs *regs = priv->iobase; @@ -427,6 +479,9 @@ static int axiemac_write_hwaddr(struct udevice *dev) { struct eth_pdata *pdata = dev_get_platdata(dev); struct axidma_priv *priv = dev_get_priv(dev); + + if (priv->mactype == EMAC_10G_25G) return 0; + struct axi_regs *regs = priv->iobase; /* Set the MAC address */ @@ -466,7 +521,6 @@ static void axi_dma_init(struct axidma_priv *priv) static int axiemac_start(struct udevice *dev) { struct axidma_priv *priv = dev_get_priv(dev); - struct axi_regs *regs = priv->iobase; u32 temp; debug("axiemac: Init started\n"); @@ -479,8 +533,13 @@ static int axiemac_start(struct udevice *dev) axi_dma_init(priv); /* Initialize AxiEthernet hardware. */ - if (axi_ethernet_init(priv)) - return -1; + if (priv->mactype == EMAC_1G) { + if (axi_ethernet_init(priv)) + return -1; + } else { + if (xxv_axi_ethernet_init(priv)) + return -1; + } /* Disable all RX interrupts before RxBD space setup */ temp = readl(&priv->dmarx->control); @@ -514,15 +573,29 @@ static int axiemac_start(struct udevice *dev) /* Rx BD is ready - start */ axienet_dma_write(&rx_bd, &priv->dmarx->tail); - /* Enable TX */ - writel(XAE_TC_TX_MASK, ®s->tc); - /* Enable RX */ - writel(XAE_RCW1_RX_MASK, ®s->rcw1); - - /* PHY setup */ - if (!setup_phy(dev)) { - axiemac_stop(dev); - return -1; + if (priv->mactype == EMAC_1G) { + struct axi_regs *regs = priv->iobase; + /* Enable TX */ + writel(XAE_TC_TX_MASK, ®s->tc); + /* Enable RX */ + writel(XAE_RCW1_RX_MASK, ®s->rcw1); + + /* PHY setup */ + if (!setup_phy(dev)) { + axiemac_stop(dev); + return -1; + } + } else { + struct xxv_axi_regs *regs = priv->iobase; + /* Enable TX */ + temp = readl(®s->tc) & ~XXV_TC_TX_MASK; + temp |= XXV_TC_TX_MASK; + writel(temp, ®s->tc); + + /* Enable RX */ + temp = readl(®s->rcw1) & ~XXV_RCW1_RX_MASK; + temp |= XXV_RCW1_RX_MASK; + writel(temp, ®s->rcw1); } debug("axiemac: Init complete\n"); @@ -537,6 +610,15 @@ static int axiemac_send(struct udevice *dev, void *ptr, int len) if (len > PKTSIZE_ALIGN) len = PKTSIZE_ALIGN; + /* If size is less than min packet size, pad to min size */ + if (priv->mactype == EMAC_10G_25G + && len < XXV_MIN_PKT_SIZE) { + memset(txminframe, 0, XXV_MIN_PKT_SIZE); + memcpy(txminframe, ptr, len); + len = XXV_MIN_PKT_SIZE; + ptr = txminframe; + } + /* Flush packet to main memory to be trasfered by DMA */ flush_cache((phys_addr_t)ptr, len); @@ -621,7 +703,7 @@ static int axiemac_recv(struct udevice *dev, int flags, uchar **packetp) temp = readl(&priv->dmarx->control); temp &= ~XAXIDMA_IRQ_ALL_MASK; writel(temp, &priv->dmarx->control); - if (!priv->eth_hasnobuf) + if ((!priv->eth_hasnobuf) && priv->mactype == EMAC_1G) length = rx_bd.app4 & 0xFFFF; /* max length mask */ else length = rx_bd.status & XAXIDMA_BD_STS_ACTUAL_LEN_MASK; @@ -701,7 +783,8 @@ static int axi_emac_probe(struct udevice *dev) if (ret) return ret; - axiemac_phy_init(dev); + if (priv->mactype == EMAC_1G) + axiemac_phy_init(dev); return 0; } @@ -736,6 +819,7 @@ static int axi_emac_ofdata_to_platdata(struct udevice *dev) pdata->iobase = dev_read_addr(dev); priv->iobase = (struct axi_regs *)pdata->iobase; + priv->mactype = dev_get_driver_data(dev); offset = fdtdec_lookup_phandle(gd->fdt_blob, node, "axistream-connected"); @@ -760,7 +844,11 @@ static int axi_emac_ofdata_to_platdata(struct udevice *dev) priv->phy_of_handle = offset; } - phy_mode = fdt_getprop(gd->fdt_blob, node, "phy-mode", NULL); + if (priv->mactype == EMAC_1G) + phy_mode = fdt_getprop(gd->fdt_blob, node, "phy-mode", NULL); + else + phy_mode = ""; + if (phy_mode) pdata->phy_interface = phy_get_interface_by_name(phy_mode); if (pdata->phy_interface == -1) { @@ -779,7 +867,8 @@ static int axi_emac_ofdata_to_platdata(struct udevice *dev) } static const struct udevice_id axi_emac_ids[] = { - { .compatible = "xlnx,axi-ethernet-1.00.a" }, + { .compatible = "xlnx,axi-ethernet-1.00.a", .data = (uintptr_t)EMAC_1G }, + { .compatible = "xlnx,xxv-ethernet-1.0", .data = (uintptr_t)EMAC_10G_25G }, { } }; diff --git a/drivers/net/xilinx_axi_emac.c b/drivers/net/xilinx_axi_emac.c index 8af3711204..3b739bd407 100644 --- a/drivers/net/xilinx_axi_emac.c +++ b/drivers/net/xilinx_axi_emac.c @@ -1,5 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* + * Copyright (C) 2020 Waymo LLC * Copyright (C) 2011 Michal Simek * Copyright (C) 2011 PetaLogix * Copyright (C) 2010 Xilinx, Inc. All rights reserved. @@ -72,10 +73,25 @@ DECLARE_GLOBAL_DATA_PTR; #define XAXIDMA_BD_CTRL_TXSOF_MASK 0x08000000 /* First tx packet */ #define XAXIDMA_BD_CTRL_TXEOF_MASK 0x04000000 /* Last tx packet */ +/* Bitmasks for the XXV Ethernet MAC */ +#define XXV_TC_TX_MASK 0x00000001 +#define XXV_TC_FCS_MASK 0x00000002 +#define XXV_RCW1_RX_MASK 0x00000001 +#define XXV_RCW1_FCS_MASK 0x00000002 + #define DMAALIGN 128 +#define XXV_MIN_PKT_SIZE 60 + static u8 rxframe[PKTSIZE_ALIGN] __attribute((aligned(DMAALIGN))); +static u8 txminframe[XXV_MIN_PKT_SIZE] __attribute((aligned(DMAALIGN))); + +enum emac_variant { + EMAC_1G = 0, + EMAC_10G_25G, +}; + /* Reflect dma offsets */ struct axidma_reg { u32 control; /* DMACR */ @@ -97,6 +113,7 @@ struct axidma_priv { struct mii_dev *bus; u8 eth_hasnobuf; int phy_of_handle; + enum emac_variant mactype; }; /* BD descriptors */ @@ -143,6 +160,14 @@ struct axi_regs { u32 uaw1; /* 0x704: Unicast address word 1 */ }; +struct xxv_axi_regs { + u32 gt_reset; /* 0x0 */ + u32 reserved[2]; + u32 tc; /* 0xC: Tx Configuration */ + u32 reserved2; + u32 rcw1; /* 0x14: Rx Configuration Word 1 */ +}; + /* Use MII register 1 (MII status register) to detect PHY */ #define PHY_DETECT_REG 1 @@ -191,6 +216,8 @@ static inline void axienet_dma_write(struct axidma_bd *bd, u32 *desc) static u32 phyread(struct axidma_priv *priv, u32 phyaddress, u32 registernum, u16 *val) { + if (priv->mactype == EMAC_10G_25G) return 0; + struct axi_regs *regs = priv->iobase; u32 mdioctrlreg = 0;