From patchwork Thu Nov 5 16:15:35 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?C=C3=A9dric_Le_Goater?= X-Patchwork-Id: 1395107 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [203.11.71.2]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4CRpdB69Lbz9sSs for ; Fri, 6 Nov 2020 03:19:42 +1100 (AEDT) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=kaod.org Received: from bilbo.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 4CRpdB3H1TzDr2g for ; Fri, 6 Nov 2020 03:19:42 +1100 (AEDT) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; 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Thu, 5 Nov 2020 16:15:46 +0000 (GMT) Received: from d06av24.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id C57974204C; Thu, 5 Nov 2020 16:15:45 +0000 (GMT) Received: from smtp.tlslab.ibm.com (unknown [9.101.4.1]) by d06av24.portsmouth.uk.ibm.com (Postfix) with SMTP; Thu, 5 Nov 2020 16:15:45 +0000 (GMT) Received: from yukon.ibmuc.com (sig-9-145-56-135.uk.ibm.com [9.145.56.135]) by smtp.tlslab.ibm.com (Postfix) with ESMTP id 2E3372201D0; Thu, 5 Nov 2020 17:15:45 +0100 (CET) From: =?utf-8?q?C=C3=A9dric_Le_Goater?= To: skiboot@lists.ozlabs.org Date: Thu, 5 Nov 2020 17:15:35 +0100 Message-Id: <20201105161542.670165-2-clg@kaod.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201105161542.670165-1-clg@kaod.org> References: <20201105161542.670165-1-clg@kaod.org> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.312, 18.0.737 definitions=2020-11-05_09:2020-11-05, 2020-11-05 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 bulkscore=0 mlxlogscore=999 spamscore=0 mlxscore=0 lowpriorityscore=0 priorityscore=1501 impostorscore=0 clxscore=1034 phishscore=0 adultscore=0 suspectscore=1 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2009150000 definitions=main-2011050106 Subject: [Skiboot] [PATCH 1/4] core: Add debugfs framework X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?C=C3=A9dric_Le_Goater?= Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" This is a very simplistic framework adding a read/write interface to opal drivers. Drivers should define a set of 'opal_debug' handlers, each with custom read/write operations. The device tree is then populated with nodes such as : debug@0 { ibm,chip-id = <0x00>; label = "xive-ivt"; compatible = "ibm,opal-debug"; reg = <0x00>; phandle = <0x805e>; }; which can be freely extended by the driver if needed. The Linux driver can choose to expose the contents of each 'opal_debug' handler through debugfs using the OPAL_DEBUG_READ call. It is relatively easy to implement a simple command interface with the OPAL_DEBUG_WRITE call, to set some values or reset some counters. Signed-off-by: Cédric Le Goater --- include/opal-api.h | 4 +- include/opal-debug.h | 27 ++++++++++++ core/opal-debug.c | 97 ++++++++++++++++++++++++++++++++++++++++++++ core/Makefile.inc | 1 + 4 files changed, 128 insertions(+), 1 deletion(-) create mode 100644 include/opal-debug.h create mode 100644 core/opal-debug.c diff --git a/include/opal-api.h b/include/opal-api.h index e90cab1e9f65..03c414946651 100644 --- a/include/opal-api.h +++ b/include/opal-api.h @@ -227,7 +227,9 @@ #define OPAL_SECVAR_ENQUEUE_UPDATE 178 #define OPAL_PHB_SET_OPTION 179 #define OPAL_PHB_GET_OPTION 180 -#define OPAL_LAST 180 +#define OPAL_DEBUG_READ 181 +#define OPAL_DEBUG_WRITE 182 +#define OPAL_LAST 182 #define QUIESCE_HOLD 1 /* Spin all calls at entry */ #define QUIESCE_REJECT 2 /* Fail all calls with OPAL_BUSY */ diff --git a/include/opal-debug.h b/include/opal-debug.h new file mode 100644 index 000000000000..fc8e3980f8a6 --- /dev/null +++ b/include/opal-debug.h @@ -0,0 +1,27 @@ +// SPDX-License-Identifier: Apache-2.0 +/* Copyright 2020 IBM Corp. */ + +#ifndef __OPAL_DEBUG_H +#define __OPAL_DEBUG_H + +struct opal_debug; + +struct opal_debug_ops { + const char *compat; + int (*read)(struct opal_debug *d, void *buf, uint64_t size); + int (*write)(struct opal_debug *d, void *buf, uint64_t size); +}; + +struct opal_debug { + struct list_node link; + uint64_t id; + struct dt_node *node; + const char *name; + void *private; + const struct opal_debug_ops *ops; +}; + +struct opal_debug *opal_debug_create(const char *name, struct dt_node *node, + void* private, const struct opal_debug_ops *ops); + +#endif diff --git a/core/opal-debug.c b/core/opal-debug.c new file mode 100644 index 000000000000..a9ed2552e908 --- /dev/null +++ b/core/opal-debug.c @@ -0,0 +1,97 @@ +// SPDX-License-Identifier: Apache-2.0 +/* Copyright 2020 IBM Corp. */ + +#define pr_fmt(fmt) "DEBUG: " fmt + +#include +#include +#include + +static LIST_HEAD(opal_debug_handlers); +static uint64_t opal_debug_index; + +/* This would need some locking */ +struct opal_debug *opal_debug_create(const char *name, struct dt_node *node, + void* private, const struct opal_debug_ops *ops) +{ + const char *compat = ops->compat ? ops->compat : "ibm,opal-debug"; + struct opal_debug *d; + + d = zalloc(sizeof(*d)); + if (!d) { + prlog(PR_ERR, "Failed to allocate debug handler!\n"); + return NULL; + } + + d->id = opal_debug_index; + d->name = name; + d->private = private; + d->ops = ops; + + d->node = dt_new_addr(node, "debug", opal_debug_index); + dt_add_property_cells(d->node, "reg", opal_debug_index); + dt_add_property_string(d->node, "compatible", compat); + dt_add_property_string(d->node, "label", d->name); + + list_add_tail(&opal_debug_handlers, &d->link); + + opal_debug_index++; + + return d; +} + +static struct opal_debug *opal_debug_find(uint64_t id) +{ + struct opal_debug *d; + + list_for_each(&opal_debug_handlers, d, link) { + if (d->id == id) + return d; + } + return NULL; +} +static int64_t opal_debug_read(uint64_t id, uint64_t buf, uint64_t size) +{ + struct opal_debug *d; + + if (id >= opal_debug_index) + return OPAL_PARAMETER; + + if (!opal_addr_valid((void *)buf) || !size) + return OPAL_PARAMETER; + + d = opal_debug_find(id); + if (!d) { + prlog(PR_ERR, "No debug handler %lld!\n", id); + return OPAL_INTERNAL_ERROR; + } + + if (!d->ops->read) + return OPAL_UNSUPPORTED; + + return d->ops->read(d, (void *)buf, size); +} +opal_call(OPAL_DEBUG_READ, opal_debug_read, 3); + +static int64_t opal_debug_write(uint64_t id, uint64_t buf, uint64_t size) +{ + struct opal_debug *d; + + if (id >= opal_debug_index) + return OPAL_PARAMETER; + + if (!opal_addr_valid((void *)buf) || !size) + return OPAL_PARAMETER; + + d = opal_debug_find(id); + if (!d) { + prlog(PR_ERR, "No debug handler %lld!\n", id); + return OPAL_INTERNAL_ERROR; + } + + if (!d->ops->write) + return OPAL_UNSUPPORTED; + + return d->ops->write(d, (void *)buf, size); +} +opal_call(OPAL_DEBUG_WRITE, opal_debug_write, 3); diff --git a/core/Makefile.inc b/core/Makefile.inc index 829800e5b27f..ed7003ed7a7a 100644 --- a/core/Makefile.inc +++ b/core/Makefile.inc @@ -13,6 +13,7 @@ CORE_OBJS += timer.o i2c.o rtc.o flash.o sensor.o ipmi-opal.o CORE_OBJS += flash-subpartition.o bitmap.o buddy.o pci-quirk.o powercap.o psr.o CORE_OBJS += pci-dt-slot.o direct-controls.o cpufeatures.o CORE_OBJS += flash-firmware-versions.o opal-dump.o +CORE_OBJS += opal-debug.o ifeq ($(SKIBOOT_GCOV),1) CORE_OBJS += gcov-profiling.o From patchwork Thu Nov 5 16:15:36 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?C=C3=A9dric_Le_Goater?= X-Patchwork-Id: 1395086 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4CRpY5165zz9sSs for ; Fri, 6 Nov 2020 03:16:09 +1100 (AEDT) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=kaod.org Received: from bilbo.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 4CRpY4247kzDr13 for ; Fri, 6 Nov 2020 03:16:08 +1100 (AEDT) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=softfail (domain owner discourages use of this host) smtp.mailfrom=kaod.org (client-ip=148.163.156.1; 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Thu, 5 Nov 2020 16:15:46 +0000 (GMT) Received: from yukon.ibmuc.com (sig-9-145-56-135.uk.ibm.com [9.145.56.135]) by smtp.tlslab.ibm.com (Postfix) with ESMTP id B209A2201F0; Thu, 5 Nov 2020 17:15:45 +0100 (CET) From: =?utf-8?q?C=C3=A9dric_Le_Goater?= To: skiboot@lists.ozlabs.org Date: Thu, 5 Nov 2020 17:15:36 +0100 Message-Id: <20201105161542.670165-3-clg@kaod.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201105161542.670165-1-clg@kaod.org> References: <20201105161542.670165-1-clg@kaod.org> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.312, 18.0.737 definitions=2020-11-05_10:2020-11-05, 2020-11-05 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 suspectscore=1 priorityscore=1501 malwarescore=0 bulkscore=0 mlxlogscore=999 lowpriorityscore=0 phishscore=0 impostorscore=0 adultscore=0 clxscore=1034 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2009150000 definitions=main-2011050107 Subject: [Skiboot] [PATCH 2/4] phb4: Add debugfs entries for internal tables X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?C=C3=A9dric_Le_Goater?= Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" Signed-off-by: Cédric Le Goater --- hw/phb4.c | 118 +++++++++++++++++++++++++----------------------------- 1 file changed, 55 insertions(+), 63 deletions(-) diff --git a/hw/phb4.c b/hw/phb4.c index f5bef9643c04..8353abcad2f7 100644 --- a/hw/phb4.c +++ b/hw/phb4.c @@ -112,6 +112,7 @@ #include #include #include +#include /* Enable this to disable error interrupts for debug purposes */ #undef DISABLE_ERR_INTS @@ -2003,95 +2004,79 @@ static void __unused phb4_dump_peltv(struct phb4 *p) } } -static void __unused phb4_dump_ioda_table(struct phb4 *p, int table) -{ +static struct phb4_ioda_table { + int index; const char *name; - int entries, i; + int entries; +} phb4_ioda_tables[] = { + { IODA3_TBL_LIST, "LIST", 8 }, + { IODA3_TBL_MIST, "MIST", 1024 }, + { IODA3_TBL_RCAM, "RCAM", 128 }, + { IODA3_TBL_MRT, "MRT", 16 }, + { IODA3_TBL_PESTA, "PESTA", 512 }, + { IODA3_TBL_PESTB, "PESTB", 512 }, + { IODA3_TBL_TVT, "TVT", 512 }, + { IODA3_TBL_TCAM, "TCAM", 1024 }, + { IODA3_TBL_TDR, "TDR", 1024 }, + { IODA3_TBL_MBT, "MBT", 64 }, /* special case */ + { IODA3_TBL_MDT, "MDT", 512 }, + { IODA3_TBL_PEEV, "PEEV", 8 }, +}; - switch (table) { - case IODA3_TBL_LIST: - name = "LIST"; - entries = 8; - break; - case IODA3_TBL_MIST: - name = "MIST"; - entries = 1024; - break; - case IODA3_TBL_RCAM: - name = "RCAM"; - entries = 128; - break; - case IODA3_TBL_MRT: - name = "MRT"; - entries = 16; - break; - case IODA3_TBL_PESTA: - name = "PESTA"; - entries = 512; - break; - case IODA3_TBL_PESTB: - name = "PESTB"; - entries = 512; - break; - case IODA3_TBL_TVT: - name = "TVT"; - entries = 512; - break; - case IODA3_TBL_TCAM: - name = "TCAM"; - entries = 1024; - break; - case IODA3_TBL_TDR: - name = "TDR"; - entries = 1024; - break; - case IODA3_TBL_MBT: /* special case, see below */ - name = "MBT"; - entries = 64; - break; - case IODA3_TBL_MDT: - name = "MDT"; - entries = 512; - break; - case IODA3_TBL_PEEV: - name = "PEEV"; - entries = 8; - break; - default: - PHBERR(p, "Invalid IODA table %d!\n", table); - return; +static struct phb4_ioda_table *phb4_ioda_table_find(const char *name) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(phb4_ioda_tables); i++) { + if (!strcmp(phb4_ioda_tables[i].name, name)) + return &phb4_ioda_tables[i]; } - PHBERR(p, "Start %s dump (only non-zero entries are printed):\n", name); + return NULL; +} - phb4_ioda_sel(p, table, 0, true); +static int phb4_ioda_read(struct opal_debug *d, void *buf, uint64_t size) +{ + struct phb4 *p = d->private; + struct phb4_ioda_table *table = phb4_ioda_table_find(d->name); + int i; + int n = 0; + + assert(table); + + phb4_ioda_sel(p, table->index, 0, true); /* * Each entry in the MBT is 16 bytes. Every other table has 8 byte * entries so we special case the MDT to keep the output readable. */ - if (table == IODA3_TBL_MBT) { + if (table->index == IODA3_TBL_MBT) { for (i = 0; i < 32; i++) { uint64_t v1 = phb4_read_reg_asb(p, PHB_IODA_DATA0); uint64_t v2 = phb4_read_reg_asb(p, PHB_IODA_DATA0); if (!v1 && !v2) continue; - PHBERR(p, "MBT[%03x] = %016llx %016llx\n", i, v1, v2); + n += snprintf(buf + n, size - n, + "MBT[%03x] = %016llx %016llx\n", i, v1, v2); } } else { - for (i = 0; i < entries; i++) { + for (i = 0; i < table->entries; i++) { uint64_t v = phb4_read_reg_asb(p, PHB_IODA_DATA0); if (!v) continue; - PHBERR(p, "%s[%03x] = %016llx\n", name, i, v); + n += snprintf(buf + n, size - n, "%s[%03x] = %016llx\n", + table->name, i, v); } } - - PHBERR(p, "End %s dump\n", name); + return n; } +static const struct opal_debug_ops phb4_ioda_ops = { + .read = phb4_ioda_read, +}; + static void phb4_eeh_dump_regs(struct phb4 *p) { struct OpalIoPhb4ErrorData *s; @@ -5895,6 +5880,13 @@ static void phb4_create(struct dt_node *np) dt_add_property_string(np, "status", "okay"); + /* Add debug nodes for real PHBs */ + if (p->phb.phb_type != phb_type_npu_v2 && + p->phb.phb_type != phb_type_npu_v2_opencapi && + p->phb.phb_type != phb_type_npu_v3) + for (i = 0; i < ARRAY_SIZE(phb4_ioda_tables); i++) + opal_debug_create(phb4_ioda_tables[i].name, + np, p, &phb4_ioda_ops); return; failed: From patchwork Thu Nov 5 16:15:37 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?C=C3=A9dric_Le_Goater?= X-Patchwork-Id: 1395088 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [203.11.71.2]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4CRpZ06CnJz9sSs for ; Fri, 6 Nov 2020 03:16:56 +1100 (AEDT) Authentication-Results: ozlabs.org; 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Thu, 05 Nov 2020 16:15:49 +0000 Received: from d06av23.portsmouth.uk.ibm.com (d06av23.portsmouth.uk.ibm.com [9.149.105.59]) by b06avi18626390.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 0A5GFlLJ49938818 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Thu, 5 Nov 2020 16:15:47 GMT Received: from d06av23.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 1837CA404D; Thu, 5 Nov 2020 16:15:47 +0000 (GMT) Received: from d06av23.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id D636EA4059; Thu, 5 Nov 2020 16:15:46 +0000 (GMT) Received: from smtp.tlslab.ibm.com (unknown [9.101.4.1]) by d06av23.portsmouth.uk.ibm.com (Postfix) with SMTP; Thu, 5 Nov 2020 16:15:46 +0000 (GMT) Received: from yukon.ibmuc.com (sig-9-145-56-135.uk.ibm.com [9.145.56.135]) by smtp.tlslab.ibm.com (Postfix) with ESMTP id 4371022006B; Thu, 5 Nov 2020 17:15:46 +0100 (CET) From: =?utf-8?q?C=C3=A9dric_Le_Goater?= To: skiboot@lists.ozlabs.org Date: Thu, 5 Nov 2020 17:15:37 +0100 Message-Id: <20201105161542.670165-4-clg@kaod.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201105161542.670165-1-clg@kaod.org> References: <20201105161542.670165-1-clg@kaod.org> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.312, 18.0.737 definitions=2020-11-05_10:2020-11-05, 2020-11-05 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1034 mlxscore=0 lowpriorityscore=0 adultscore=0 impostorscore=0 suspectscore=1 phishscore=0 bulkscore=0 malwarescore=0 spamscore=0 mlxlogscore=974 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2009150000 definitions=main-2011050107 Subject: [Skiboot] [PATCH 3/4] xive/p9: Add debugfs entries for internal tables X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?C=C3=A9dric_Le_Goater?= Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" The XIVE interrupt controller relies on a set of tables to configure the routing of interrupts from source to target. The IVT associates a source number to an event queue, the EQDT associates an event queue to a notification virtual target (NVT) and the NVTT holds the NVT configuration and serves as memory back store for the interrupt thread context registers. Each table contains valuable information which is interesting to expose. Signed-off-by: Cédric Le Goater --- hw/xive.c | 173 ++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 173 insertions(+) diff --git a/hw/xive.c b/hw/xive.c index 7e1bcebf7ece..9942d62a7808 100644 --- a/hw/xive.c +++ b/hw/xive.c @@ -19,6 +19,7 @@ #include #include #include +#include /* Always notify from EQ to VP (no EOI on EQs). Will speed up * EOIs at the expense of potentially higher powerbus traffic. @@ -5153,6 +5154,8 @@ static void xive_init_globals(void) xive_block_to_chip[i] = XIVE_INVALID_CHIP; } +static void xive_init_debug(struct xive *x); + void init_xive(void) { struct dt_node *np; @@ -5232,5 +5235,175 @@ void init_xive(void) opal_register(OPAL_XIVE_GET_QUEUE_STATE, opal_xive_get_queue_state, 4); opal_register(OPAL_XIVE_SET_QUEUE_STATE, opal_xive_set_queue_state, 4); opal_register(OPAL_XIVE_GET_VP_STATE, opal_xive_get_vp_state, 2); + + for_each_chip(chip) { + if (chip->xive) + xive_init_debug(chip->xive); + } +} + +static int xive_ivt_read(struct opal_debug *d, void *buf, uint64_t size) +{ + struct xive *x = d->private; + struct xive_ive *ivt = x->ivt_base; + int i; + int n = 0; + + n += snprintf(buf + n, size - n, "IVT[%d]\n", x->block_id); + for (i = 0; i < XIVE_INT_COUNT; i++) { + struct xive_ive *ive = &ivt[i]; + uint32_t eq_blk, eq_idx, eq_data; + /* TODO: get ESB mmio */ + + if (xive_get_field64(IVE_MASKED, ive->w) || + !xive_get_field64(IVE_VALID, ive->w)) + continue; + n += snprintf(buf + n, size - n, "%08x ", + BLKIDX_TO_GIRQ(x->block_id, i)); + lock(&x->lock); + eq_blk = xive_get_field64(IVE_EQ_BLOCK, ive->w); + eq_idx = xive_get_field64(IVE_EQ_INDEX, ive->w); + eq_data = xive_get_field64(IVE_EQ_DATA, ive->w); + unlock(&x->lock); + + n += snprintf(buf + n, size - n, "eq=%x/%x data=%x\n", + eq_blk, eq_idx, eq_data); + } + + return n; +} + +static int xive_eqt_read(struct opal_debug *d, void *buf, uint64_t size) +{ + struct xive *x = d->private; + int i, j; + int n = 0; + + n += snprintf(buf + n, size - n, "EQT[%d]\n", x->block_id); + bitmap_for_each_one(*x->eq_map, XIVE_EQ_COUNT >> 3, i) { + for (j = 0; j < NUM_INT_PRIORITIES; j++) { + struct xive_eq *eq; + uint32_t idx = (i << 3) | j; + + eq = xive_get_eq(x, idx); + if (!eq || !xive_get_field32(EQ_W0_VALID, eq->w0)) + continue; + + lock(&x->lock); + xive_eqc_scrub(x, x->block_id, idx); + unlock(&x->lock); + + n += snprintf(buf + n, size - n, + "%08x %08x %08x %08x %08x %08x %08x %08x %08x\n", + idx, + eq->w0, eq->w1, eq->w2, eq->w3, + eq->w4, eq->w5, eq->w6, eq->w7); + } + } + return n; +} + +static int xive_esc_read(struct opal_debug *d, void *buf, uint64_t size) +{ + struct xive *x = d->private; + int i, j; + int n = 0; + + n += snprintf(buf + n, size - n, "ESC IVT[%d]\n", x->block_id); + bitmap_for_each_one(*x->eq_map, XIVE_EQ_COUNT >> 3, i) { + for (j = 0; j < NUM_INT_PRIORITIES; j++) { + uint32_t idx = (i << 3) | j; + struct xive_eq *eq; + struct xive_ive *ive; + uint32_t eq_blk, eq_idx, eq_data; + + eq = xive_get_eq(x, idx); + if (!eq || !xive_get_field32(EQ_W0_VALID, eq->w0)) + continue; + if (!xive_get_field32(EQ_W0_ESCALATE_CTL, eq->w0)) + continue; + + ive = (struct xive_ive*)(char *)&eq->w4; + + n += snprintf(buf + n, size - n, "%08x ", + MAKE_ESCALATION_GIRQ(x->block_id, i)); + lock(&x->lock); + xive_eqc_scrub(x, x->block_id, idx); + eq_blk = xive_get_field64(IVE_EQ_BLOCK, ive->w); + eq_idx = xive_get_field64(IVE_EQ_INDEX, ive->w); + eq_data = xive_get_field64(IVE_EQ_DATA, ive->w); + unlock(&x->lock); + + n += snprintf(buf + n, size - n, "eq=%x/%x data=%x\n", + eq_blk, eq_idx, eq_data); + } + } + return n; +} + +static int xive_vpt_read(struct opal_debug *d, void *buf, uint64_t size) +{ + struct xive *x = d->private; + int i; + int n = 0; + + n += snprintf(buf + n, size - n, "VPT[%d]\n", x->block_id); + for (i = 0; i < XIVE_VP_COUNT; i++) { + struct xive_vp *vp; + + /* Ignore the physical CPU VPs */ + if (i >= XIVE_HW_VP_BASE && + i < (XIVE_HW_VP_BASE + XIVE_HW_VP_COUNT)) + continue; + + vp = xive_get_vp(x, i); + if (!vp || !xive_get_field32(VP_W0_VALID, vp->w0)) + continue; + lock(&x->lock); + xive_vpc_scrub(x, x->block_id, i); + unlock(&x->lock); + n += snprintf(buf + n, size - n, + "%08x %08x %08x %08x %08x %08x %08x %08x %08x\n", + i, + vp->w0, vp->w1, vp->w2, vp->w3, + vp->w4, vp->w5, vp->w6, vp->w7); + } + return n; +} + +static const struct opal_debug_ops xive_ivt_ops = { + .read = xive_ivt_read, +}; +static const struct opal_debug_ops xive_eqt_ops = { + .read = xive_eqt_read, +}; +static const struct opal_debug_ops xive_esc_ops = { + .read = xive_esc_read, +}; +static const struct opal_debug_ops xive_vpt_ops = { + .read = xive_vpt_read, +}; + +static const struct { + const char *name; + const struct opal_debug_ops *ops; +} xive_debug_handlers[] = { + { "xive-ivt", &xive_ivt_ops, }, + { "xive-eqt", &xive_eqt_ops, }, + { "xive-esc", &xive_esc_ops, }, + { "xive-vpt", &xive_vpt_ops, }, +}; + +static void xive_init_debug(struct xive *x) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(xive_debug_handlers); i++) { + struct opal_debug *d; + d = opal_debug_create(xive_debug_handlers[i].name, xive_dt_node, + x, xive_debug_handlers[i].ops); + + dt_add_property_cells(d->node, "ibm,chip-id", x->chip_id); + } } From patchwork Thu Nov 5 16:15:38 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?C=C3=A9dric_Le_Goater?= X-Patchwork-Id: 1395090 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [203.11.71.2]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4CRpZN18N8z9sSs for ; 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Thu, 05 Nov 2020 16:15:49 +0000 Received: from d06av23.portsmouth.uk.ibm.com (d06av23.portsmouth.uk.ibm.com [9.149.105.59]) by b06avi18626390.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 0A5GFloi42336692 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Thu, 5 Nov 2020 16:15:47 GMT Received: from d06av23.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 99582A405D; Thu, 5 Nov 2020 16:15:47 +0000 (GMT) Received: from d06av23.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 63F99A4053; Thu, 5 Nov 2020 16:15:47 +0000 (GMT) Received: from smtp.tlslab.ibm.com (unknown [9.101.4.1]) by d06av23.portsmouth.uk.ibm.com (Postfix) with SMTP; Thu, 5 Nov 2020 16:15:47 +0000 (GMT) Received: from yukon.ibmuc.com (sig-9-145-56-135.uk.ibm.com [9.145.56.135]) by smtp.tlslab.ibm.com (Postfix) with ESMTP id C728F2201D0; Thu, 5 Nov 2020 17:15:46 +0100 (CET) From: =?utf-8?q?C=C3=A9dric_Le_Goater?= To: skiboot@lists.ozlabs.org Date: Thu, 5 Nov 2020 17:15:38 +0100 Message-Id: <20201105161542.670165-5-clg@kaod.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201105161542.670165-1-clg@kaod.org> References: <20201105161542.670165-1-clg@kaod.org> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.312, 18.0.737 definitions=2020-11-05_09:2020-11-05, 2020-11-05 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=1 priorityscore=1501 mlxscore=0 impostorscore=0 bulkscore=0 adultscore=0 malwarescore=0 phishscore=0 clxscore=1034 spamscore=0 mlxlogscore=968 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2009150000 definitions=main-2011050106 Subject: [Skiboot] [PATCH 4/4] xive/p9: Add debugfs entries for performance X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?C=C3=A9dric_Le_Goater?= Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" XIVE interrupt controller has some registers collecting internal performance mesures. Expose them through a debug handler. Unfortunately, these can not be reset without a reboot. Signed-off-by: Cédric Le Goater --- include/xive-p9-regs.h | 14 ++++++++++++++ hw/xive.c | 25 +++++++++++++++++++++++++ 2 files changed, 39 insertions(+) diff --git a/include/xive-p9-regs.h b/include/xive-p9-regs.h index fff341cca150..c1dcc7d205c2 100644 --- a/include/xive-p9-regs.h +++ b/include/xive-p9-regs.h @@ -163,6 +163,11 @@ #define X_PC_VPC_CWATCH_DAT7 0x16f #define PC_VPC_CWATCH_DAT7 0x778 +#define X_PC_VPC_ADDITIONAL_PERF_1 0x174 +#define PC_VPC_ADDITIONAL_PERF_1 0x7A0 +#define X_PC_VPC_ADDITIONAL_PERF_2 0x175 +#define PC_VPC_ADDITIONAL_PERF_2 0x7A8 + /* VC0 register offsets */ #define X_VC_GLOBAL_CONFIG 0x200 #define VC_GLOBAL_CONFIG 0x800 @@ -262,6 +267,15 @@ #define VC_SBC_CONF_CIST_BOTH PPC_BIT(45) #define VC_SBC_CONF_NO_UPD_PRF PPC_BIT(59) +#define X_VC_EQC_ADDITIONAL_PERF_1 0x253 +#define VC_EQC_ADDITIONAL_PERF_1 0x970 +#define X_VC_EQC_ADDITIONAL_PERF_2 0x254 +#define VC_EQC_ADDITIONAL_PERF_2 0x978 +#define X_VC_IVC_ADDITIONAL_PERF 0x25B +#define VC_IVC_ADDITIONAL_PERF 0x9F0 +#define X_VC_SBC_ADDITIONAL_PERF 0x263 +#define VC_SBC_ADDITIONAL_PERF 0xA70 + /* VC1 register offsets */ /* VSD Table address register definitions (shared) */ diff --git a/hw/xive.c b/hw/xive.c index 9942d62a7808..51b3daadd1c5 100644 --- a/hw/xive.c +++ b/hw/xive.c @@ -5371,6 +5371,27 @@ static int xive_vpt_read(struct opal_debug *d, void *buf, uint64_t size) return n; } +static int xive_perf_read(struct opal_debug *d, void *buf, uint64_t size) +{ + struct xive *x = d->private; + int n = 0; + + n += snprintf(buf + n, size - n, "Performance counters [%d]\n", x->block_id); + +#define perf_read(reg) \ + n += snprintf(buf + n, size - n, "%30s = %016llx\n", #reg, \ + in_be64(x->ic_base + reg)) + + perf_read(PC_VPC_ADDITIONAL_PERF_1); + perf_read(PC_VPC_ADDITIONAL_PERF_2); + perf_read(VC_EQC_ADDITIONAL_PERF_1); + perf_read(VC_EQC_ADDITIONAL_PERF_2); + perf_read(VC_IVC_ADDITIONAL_PERF); + perf_read(VC_SBC_ADDITIONAL_PERF); + + return n; +} + static const struct opal_debug_ops xive_ivt_ops = { .read = xive_ivt_read, }; @@ -5383,6 +5404,9 @@ static const struct opal_debug_ops xive_esc_ops = { static const struct opal_debug_ops xive_vpt_ops = { .read = xive_vpt_read, }; +static const struct opal_debug_ops xive_perf_ops = { + .read = xive_perf_read, +}; static const struct { const char *name; @@ -5392,6 +5416,7 @@ static const struct { { "xive-eqt", &xive_eqt_ops, }, { "xive-esc", &xive_esc_ops, }, { "xive-vpt", &xive_vpt_ops, }, + { "xive-perf", &xive_perf_ops, }, }; static void xive_init_debug(struct xive *x)