From patchwork Thu Oct 29 06:20:12 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Ramuthevar, Vadivel MuruganX" X-Patchwork-Id: 1389912 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=linux.intel.com Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4CMHkZ6GY5z9sRk for ; Thu, 29 Oct 2020 18:53:42 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727239AbgJ2HYr (ORCPT ); Thu, 29 Oct 2020 03:24:47 -0400 Received: from mga05.intel.com ([192.55.52.43]:24865 "EHLO mga05.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726883AbgJ2HYg (ORCPT ); Thu, 29 Oct 2020 03:24:36 -0400 IronPort-SDR: 0RqP4WdEd/vp5mNRP66GQSafw0El4EOPuSGF+MhkLJ793DAq/WMsl72dhs0Faqolzq3OJ4v2cC CtUlXHl3abfQ== X-IronPort-AV: E=McAfee;i="6000,8403,9788"; a="253086484" X-IronPort-AV: E=Sophos;i="5.77,429,1596524400"; d="scan'208";a="253086484" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Oct 2020 23:20:36 -0700 IronPort-SDR: a55YlRZVCXBUdbo807j6t292jhJ3MR2CTnVHl8ugqZfecVDdPsk5Z/X0lQJWMzJj8JB2UXb8OZ 6QunqfMGw3EQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.77,429,1596524400"; d="scan'208";a="351309525" Received: from sgsxdev004.isng.intel.com (HELO localhost) ([10.226.88.13]) by fmsmga004.fm.intel.com with ESMTP; 28 Oct 2020 23:20:33 -0700 From: "Ramuthevar,Vadivel MuruganX" To: broonie@kernel.org, vigneshr@ti.com, tudor.ambarus@microchip.com, linux-kernel@vger.kernel.org, linux-spi@vger.kernel.org, robh+dt@kernel.org Cc: devicetree@vger.kernel.org, miquel.raynal@bootlin.com, simon.k.r.goldschmidt@gmail.com, dinguyen@kernel.org, richard@nod.at, cheol.yong.kim@intel.com, qi-ming.wu@intel.com, Ramuthevar Vadivel Murugan Subject: [PATCH v5 4/6] spi: Move cadence-quadspi.txt to Documentation/devicetree/bindings/spi Date: Thu, 29 Oct 2020 14:20:12 +0800 Message-Id: <20201029062014.27620-5-vadivel.muruganx.ramuthevar@linux.intel.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20201029062014.27620-1-vadivel.muruganx.ramuthevar@linux.intel.com> References: <20201029062014.27620-1-vadivel.muruganx.ramuthevar@linux.intel.com> Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Ramuthevar Vadivel Murugan Move the Documentation/devicetree/bindings/mtd/cadence-quadspi.txt to Documentation/devicetree/bindings/spi/ Signed-off-by: Ramuthevar Vadivel Murugan Acked-by: Rob Herring --- Documentation/devicetree/bindings/{mtd => spi}/cadence-quadspi.txt | 0 1 file changed, 0 insertions(+), 0 deletions(-) rename Documentation/devicetree/bindings/{mtd => spi}/cadence-quadspi.txt (100%) diff --git a/Documentation/devicetree/bindings/mtd/cadence-quadspi.txt b/Documentation/devicetree/bindings/spi/cadence-quadspi.txt similarity index 100% rename from Documentation/devicetree/bindings/mtd/cadence-quadspi.txt rename to Documentation/devicetree/bindings/spi/cadence-quadspi.txt From patchwork Thu Oct 29 06:20:13 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Ramuthevar, Vadivel MuruganX" X-Patchwork-Id: 1389910 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=linux.intel.com Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4CMHkM2T0fz9sSC for ; Thu, 29 Oct 2020 18:53:31 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727279AbgJ2HYr (ORCPT ); Thu, 29 Oct 2020 03:24:47 -0400 Received: from mga04.intel.com ([192.55.52.120]:18616 "EHLO mga04.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726882AbgJ2HYg (ORCPT ); Thu, 29 Oct 2020 03:24:36 -0400 IronPort-SDR: XyDOaS92guYKCDgRVECZg0liGaGOg96TGsxYpd48e3n34C5J/srwA1wCfBZPRPpjH2qoJCvoiD BUAJvXpLSi4Q== X-IronPort-AV: E=McAfee;i="6000,8403,9788"; a="165796369" X-IronPort-AV: E=Sophos;i="5.77,429,1596524400"; d="scan'208";a="165796369" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Oct 2020 23:20:40 -0700 IronPort-SDR: 7Oq8gPtRlDBrwFM865dOsIOcmZhYbRCAZns1L6WG2v8GEhocjNLVZ7GaXhHsqflclOwtLTk3Kr mNJ1naOW/SbQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.77,429,1596524400"; d="scan'208";a="304332712" Received: from sgsxdev004.isng.intel.com (HELO localhost) ([10.226.88.13]) by fmsmga008.fm.intel.com with ESMTP; 28 Oct 2020 23:20:37 -0700 From: "Ramuthevar,Vadivel MuruganX" To: broonie@kernel.org, vigneshr@ti.com, tudor.ambarus@microchip.com, linux-kernel@vger.kernel.org, linux-spi@vger.kernel.org, robh+dt@kernel.org Cc: devicetree@vger.kernel.org, miquel.raynal@bootlin.com, simon.k.r.goldschmidt@gmail.com, dinguyen@kernel.org, richard@nod.at, cheol.yong.kim@intel.com, qi-ming.wu@intel.com, Ramuthevar Vadivel Murugan Subject: [PATCH v5 5/6] dt-bindings: spi: Convert cadence-quadspi.txt to cadence-quadspi.yaml Date: Thu, 29 Oct 2020 14:20:13 +0800 Message-Id: <20201029062014.27620-6-vadivel.muruganx.ramuthevar@linux.intel.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20201029062014.27620-1-vadivel.muruganx.ramuthevar@linux.intel.com> References: <20201029062014.27620-1-vadivel.muruganx.ramuthevar@linux.intel.com> Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Ramuthevar Vadivel Murugan Convert the cadence-quadspi.txt documentation to cadence-quadspi.yaml remove the cadence-quadspi.txt from Documentation/devicetree/bindings/spi/ Signed-off-by: Ramuthevar Vadivel Murugan --- .../devicetree/bindings/spi/cadence-quadspi.txt | 67 --------- .../devicetree/bindings/spi/cadence-quadspi.yaml | 150 +++++++++++++++++++++ 2 files changed, 150 insertions(+), 67 deletions(-) delete mode 100644 Documentation/devicetree/bindings/spi/cadence-quadspi.txt create mode 100644 Documentation/devicetree/bindings/spi/cadence-quadspi.yaml diff --git a/Documentation/devicetree/bindings/spi/cadence-quadspi.txt b/Documentation/devicetree/bindings/spi/cadence-quadspi.txt deleted file mode 100644 index 945be7d5b236..000000000000 --- a/Documentation/devicetree/bindings/spi/cadence-quadspi.txt +++ /dev/null @@ -1,67 +0,0 @@ -* Cadence Quad SPI controller - -Required properties: -- compatible : should be one of the following: - Generic default - "cdns,qspi-nor". - For TI 66AK2G SoC - "ti,k2g-qspi", "cdns,qspi-nor". - For TI AM654 SoC - "ti,am654-ospi", "cdns,qspi-nor". -- reg : Contains two entries, each of which is a tuple consisting of a - physical address and length. The first entry is the address and - length of the controller register set. The second entry is the - address and length of the QSPI Controller data area. -- interrupts : Unit interrupt specifier for the controller interrupt. -- clocks : phandle to the Quad SPI clock. -- cdns,fifo-depth : Size of the data FIFO in words. -- cdns,fifo-width : Bus width of the data FIFO in bytes. -- cdns,trigger-address : 32-bit indirect AHB trigger address. - -Optional properties: -- cdns,is-decoded-cs : Flag to indicate whether decoder is used or not. -- cdns,rclk-en : Flag to indicate that QSPI return clock is used to latch - the read data rather than the QSPI clock. Make sure that QSPI return - clock is populated on the board before using this property. - -Optional subnodes: -Subnodes of the Cadence Quad SPI controller are spi slave nodes with additional -custom properties: -- cdns,read-delay : Delay for read capture logic, in clock cycles -- cdns,tshsl-ns : Delay in nanoseconds for the length that the master - mode chip select outputs are de-asserted between - transactions. -- cdns,tsd2d-ns : Delay in nanoseconds between one chip select being - de-activated and the activation of another. -- cdns,tchsh-ns : Delay in nanoseconds between last bit of current - transaction and deasserting the device chip select - (qspi_n_ss_out). -- cdns,tslch-ns : Delay in nanoseconds between setting qspi_n_ss_out low - and first bit transfer. -- resets : Must contain an entry for each entry in reset-names. - See ../reset/reset.txt for details. -- reset-names : Must include either "qspi" and/or "qspi-ocp". - -Example: - - qspi: spi@ff705000 { - compatible = "cdns,qspi-nor"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0xff705000 0x1000>, - <0xffa00000 0x1000>; - interrupts = <0 151 4>; - clocks = <&qspi_clk>; - cdns,is-decoded-cs; - cdns,fifo-depth = <128>; - cdns,fifo-width = <4>; - cdns,trigger-address = <0x00000000>; - resets = <&rst QSPI_RESET>, <&rst QSPI_OCP_RESET>; - reset-names = "qspi", "qspi-ocp"; - - flash0: n25q00@0 { - ... - cdns,read-delay = <4>; - cdns,tshsl-ns = <50>; - cdns,tsd2d-ns = <50>; - cdns,tchsh-ns = <4>; - cdns,tslch-ns = <4>; - }; - }; diff --git a/Documentation/devicetree/bindings/spi/cadence-quadspi.yaml b/Documentation/devicetree/bindings/spi/cadence-quadspi.yaml new file mode 100644 index 000000000000..daf891ade577 --- /dev/null +++ b/Documentation/devicetree/bindings/spi/cadence-quadspi.yaml @@ -0,0 +1,150 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/spi/cadence-quadspi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Cadence Quad SPI controller + +maintainers: + - Vadivel Murugan + +allOf: + - $ref: "spi-controller.yaml#" + +properties: + compatible: + oneOf: + - items: + - const: cdns,qspi-nor + - const: ti,k2g-qspi + - const: ti,am654-ospi + - const: ti,k2g-qspi + - const: ti,am654-ospi + + reg: + items: + - description: the controller register set + - description: the controller data area + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + cdns,fifo-depth: + description: + Size of the data FIFO in words. + $ref: "/schemas/types.yaml#/definitions/uint32" + enum: [ 128, 256 ] + default: 128 + + cdns,fifo-width: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Bus width of the data FIFO in bytes. + default: 4 + + cdns,trigger-address: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + 32-bit indirect AHB trigger address. + + cdns,is-decoded-cs: + type: boolean + description: + Flag to indicate whether decoder is used or not. + + cdns,rclk-en: + type: boolean + description: + Flag to indicate that QSPI return clock is used to latch the read + data rather than the QSPI clock. Make sure that QSPI return clock + is populated on the board before using this property. + + resets: + maxItems : 2 + + reset-names: + minItems: 1 + maxItems: 2 + items: + enum: [ qspi, qspi-ocp ] + +# subnode's properties +patternProperties: + "@[0-9a-f]+$": + type: object + description: + flash device uses the subnodes below defined properties. + properties: + cdns,read-delay: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Delay for read capture logic, in clock cycles. + + cdns,tshsl-ns: + description: + Delay in nanoseconds for the length that the master mode chip select + outputs are de-asserted between transactions. + + cdns,tsd2d-ns: + description: + Delay in nanoseconds between one chip select being de-activated + and the activation of another. + + cdns,tchsh-ns: + description: + Delay in nanoseconds between last bit of current transaction and + deasserting the device chip select (qspi_n_ss_out). + + cdns,tslch-ns: + description: + Delay in nanoseconds between setting qspi_n_ss_out low and + first bit transfer. + +required: + - compatible + - reg + - interrupts + - clocks + - cdns,fifo-depth + - cdns,fifo-width + - cdns,trigger-address + - cdns,is-decoded-cs + - cdns,rclk-en + - resets + - reset-names + +additionalProperties: false + +examples: + - | + qspi: spi@ff705000 { + compatible = "cadence,qspi","cdns,qpsi-nor"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xff705000 0x1000>, + <0xffa00000 0x1000>; + interrupts = <0 151 4>; + clocks = <&qspi_clk>; + cdns,fifo-depth = <128>; + cdns,fifo-width = <4>; + cdns,trigger-address = <0x00000000>; + resets = <&rst 0x1>, <&rst 0x2>; + reset-names = "qspi", "qspi-ocp"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0x0>; + cdns,read-delay = <4>; + cdns,tshsl-ns = <50>; + cdns,tsd2d-ns = <50>; + cdns,tchsh-ns = <4>; + cdns,tslch-ns = <4>; + }; + + }; + +... From patchwork Thu Oct 29 06:20:14 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Ramuthevar, Vadivel MuruganX" X-Patchwork-Id: 1389893 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=linux.intel.com Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4CMHQT5CGcz9sRk for ; Thu, 29 Oct 2020 18:39:45 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726805AbgJ2HYs (ORCPT ); Thu, 29 Oct 2020 03:24:48 -0400 Received: from mga09.intel.com ([134.134.136.24]:31205 "EHLO mga09.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726969AbgJ2HYi (ORCPT ); Thu, 29 Oct 2020 03:24:38 -0400 IronPort-SDR: /xFnT0dn/QoWdynKxLn454lP+WeVopLweqbJxnjbc+4i7tYWv3VIf7HJ3t/7Zr+UBEtAUo7+76 weNZjbpVRfBw== X-IronPort-AV: E=McAfee;i="6000,8403,9788"; a="168516557" X-IronPort-AV: E=Sophos;i="5.77,429,1596524400"; d="scan'208";a="168516557" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Oct 2020 23:20:44 -0700 IronPort-SDR: bCPjrRrKs1vuhBjxJf8O0WgEnLbZKO0aPs/TG2r3rrNVrxJaRMmA8t/uU429pv+Vy+wBFc2oyT GVS6tnYxTjoA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.77,429,1596524400"; d="scan'208";a="361383590" Received: from sgsxdev004.isng.intel.com (HELO localhost) ([10.226.88.13]) by FMSMGA003.fm.intel.com with ESMTP; 28 Oct 2020 23:20:41 -0700 From: "Ramuthevar,Vadivel MuruganX" To: broonie@kernel.org, vigneshr@ti.com, tudor.ambarus@microchip.com, linux-kernel@vger.kernel.org, linux-spi@vger.kernel.org, robh+dt@kernel.org Cc: devicetree@vger.kernel.org, miquel.raynal@bootlin.com, simon.k.r.goldschmidt@gmail.com, dinguyen@kernel.org, richard@nod.at, cheol.yong.kim@intel.com, qi-ming.wu@intel.com, Ramuthevar Vadivel Murugan Subject: [PATCH v5 6/6] dt-bindings: spi: Add compatible for Intel LGM SoC Date: Thu, 29 Oct 2020 14:20:14 +0800 Message-Id: <20201029062014.27620-7-vadivel.muruganx.ramuthevar@linux.intel.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20201029062014.27620-1-vadivel.muruganx.ramuthevar@linux.intel.com> References: <20201029062014.27620-1-vadivel.muruganx.ramuthevar@linux.intel.com> Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Ramuthevar Vadivel Murugan Add compatible for Intel LGM SoC. Signed-off-by: Ramuthevar Vadivel Murugan --- Documentation/devicetree/bindings/spi/cadence-quadspi.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/spi/cadence-quadspi.yaml b/Documentation/devicetree/bindings/spi/cadence-quadspi.yaml index daf891ade577..637d82cd1cef 100644 --- a/Documentation/devicetree/bindings/spi/cadence-quadspi.yaml +++ b/Documentation/devicetree/bindings/spi/cadence-quadspi.yaml @@ -21,6 +21,7 @@ properties: - const: ti,am654-ospi - const: ti,k2g-qspi - const: ti,am654-ospi + - const: intel,lgm-qspi reg: items: