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Message-ID: <20201022220938.GA12075@ibm-toto.the-meissners.org> Mail-Followup-To: Michael Meissner , gcc-patches@gcc.gnu.org, Segher Boessenkool , David Edelsohn , Bill Schmidt , Peter Bergner , Jeff Law , Jonathan Wakely MIME-Version: 1.0 Content-Disposition: inline User-Agent: Mutt/1.5.21 (2010-09-15) X-TM-AS-GCONF: 00 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.235, 18.0.737 definitions=2020-10-22_17:2020-10-20, 2020-10-22 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 adultscore=0 lowpriorityscore=0 priorityscore=1501 clxscore=1015 impostorscore=0 spamscore=0 mlxlogscore=999 malwarescore=0 phishscore=0 mlxscore=0 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2009150000 definitions=main-2010220136 X-Spam-Status: No, score=-10.7 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_EF, GIT_PATCH_0, KAM_MANYTO, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Michael Meissner via Gcc-patches From: Michael Meissner Reply-To: Michael Meissner Errors-To: gcc-patches-bounces@gcc.gnu.org Sender: "Gcc-patches" PowerPC: Update IEEE 128-bit built-ins for long double is IEEE 128-bit. I have split all of these patches into separate patches to hopefully get them into the tree. This patch adds long double variants of the power10 __float128 built-in functions. This is needed when long double uses IEEE 128-bit because __float128 uses TFmode in this case instead of KFmode. If this patch is not applied, these built-in functions can't be used when long double is IEEE 128-bit. I have tested this patch with bootstrap builds on a little endian power9 system running Linux. With the other patches, I have built two full bootstrap builds using this patch and the patches after this patch. One build used the current default for long double (IBM extended double) and the other build switched the default to IEEE 128-bit. I used the Advance Toolchain AT 14.0 compiler as the library used by this compiler. There are no regressions between the tests. There are 3 fortran benchmarks (ieee/large_2.f90, default_format_2.f90, and default_format_denormal_2.f90) that now pass. Can I install this into the trunk? We have gotten some requests to back port these changes to GCC 10.x. At the moment, I am not planning to do the back port, but I may need to in the future. gcc/ 2020-10-22 Michael Meissner * config/rs6000/rs6000-call.c (altivec_overloaded_builtins): Add built-in functions for long double built-ins that use IEEE 128-bit. (rs6000_expand_builtin): Change the KF IEEE 128-bit comparison insns to TF if long double is IEEE 128-bit. * config/rs6000/rs6000-builtin.def (scalar_extract_exptf): Add support for long double being IEEE 128-bit built-in functions. (scalar_extract_sigtf): Likewise. (scalar_test_neg_tf): Likewise. (scalar_insert_exp_tf): Likewise. (scalar_insert_exp_tfp): Likewise. (scalar_cmp_exp_tf_gt): Likewise. (scalar_cmp_exp_tf_lt): Likewise. (scalar_cmp_exp_tf_eq): Likewise. (scalar_cmp_exp_tf_unordered): Likewise. (scalar_test_data_class_tf): Likewise. --- gcc/config/rs6000/rs6000-builtin.def | 11 ++++++++ gcc/config/rs6000/rs6000-call.c | 40 ++++++++++++++++++++++++++++ 2 files changed, 51 insertions(+) diff --git a/gcc/config/rs6000/rs6000-builtin.def b/gcc/config/rs6000/rs6000-builtin.def index 3eb55f0ae43..6f5685bf697 100644 --- a/gcc/config/rs6000/rs6000-builtin.def +++ b/gcc/config/rs6000/rs6000-builtin.def @@ -2401,8 +2401,11 @@ BU_P9V_64BIT_VSX_1 (VSESDP, "scalar_extract_sig", CONST, xsxsigdp) BU_FLOAT128_HW_VSX_1 (VSEEQP, "scalar_extract_expq", CONST, xsxexpqp_kf) BU_FLOAT128_HW_VSX_1 (VSESQP, "scalar_extract_sigq", CONST, xsxsigqp_kf) +BU_FLOAT128_HW_VSX_1 (VSEETF, "scalar_extract_exptf", CONST, xsxexpqp_tf) +BU_FLOAT128_HW_VSX_1 (VSESTF, "scalar_extract_sigtf", CONST, xsxsigqp_tf) BU_FLOAT128_HW_VSX_1 (VSTDCNQP, "scalar_test_neg_qp", CONST, xststdcnegqp_kf) +BU_FLOAT128_HW_VSX_1 (VSTDCNTF, "scalar_test_neg_tf", CONST, xststdcnegqp_tf) BU_P9V_VSX_1 (VSTDCNDP, "scalar_test_neg_dp", CONST, xststdcnegdp) BU_P9V_VSX_1 (VSTDCNSP, "scalar_test_neg_sp", CONST, xststdcnegsp) @@ -2420,6 +2423,8 @@ BU_P9V_64BIT_VSX_2 (VSIEDPF, "scalar_insert_exp_dp", CONST, xsiexpdpf) BU_FLOAT128_HW_VSX_2 (VSIEQP, "scalar_insert_exp_q", CONST, xsiexpqp_kf) BU_FLOAT128_HW_VSX_2 (VSIEQPF, "scalar_insert_exp_qp", CONST, xsiexpqpf_kf) +BU_FLOAT128_HW_VSX_2 (VSIETF, "scalar_insert_exp_tf", CONST, xsiexpqp_tf) +BU_FLOAT128_HW_VSX_2 (VSIETFF, "scalar_insert_exp_tfp", CONST, xsiexpqpf_tf) BU_P9V_VSX_2 (VSCEDPGT, "scalar_cmp_exp_dp_gt", CONST, xscmpexpdp_gt) BU_P9V_VSX_2 (VSCEDPLT, "scalar_cmp_exp_dp_lt", CONST, xscmpexpdp_lt) @@ -2431,7 +2436,13 @@ BU_P9V_VSX_2 (VSCEQPLT, "scalar_cmp_exp_qp_lt", CONST, xscmpexpqp_lt_kf) BU_P9V_VSX_2 (VSCEQPEQ, "scalar_cmp_exp_qp_eq", CONST, xscmpexpqp_eq_kf) BU_P9V_VSX_2 (VSCEQPUO, "scalar_cmp_exp_qp_unordered", CONST, xscmpexpqp_unordered_kf) +BU_P9V_VSX_2 (VSCETFGT, "scalar_cmp_exp_tf_gt", CONST, xscmpexpqp_gt_tf) +BU_P9V_VSX_2 (VSCETFLT, "scalar_cmp_exp_tf_lt", CONST, xscmpexpqp_lt_tf) +BU_P9V_VSX_2 (VSCETFEQ, "scalar_cmp_exp_tf_eq", CONST, xscmpexpqp_eq_tf) +BU_P9V_VSX_2 (VSCETFUO, "scalar_cmp_exp_tf_unordered", CONST, xscmpexpqp_unordered_tf) + BU_FLOAT128_HW_VSX_2 (VSTDCQP, "scalar_test_data_class_qp", CONST, xststdcqp_kf) +BU_FLOAT128_HW_VSX_2 (VSTDCTF, "scalar_test_data_class_tf", CONST, xststdcqp_tf) BU_P9V_VSX_2 (VSTDCDP, "scalar_test_data_class_dp", CONST, xststdcdp) BU_P9V_VSX_2 (VSTDCSP, "scalar_test_data_class_sp", CONST, xststdcsp) diff --git a/gcc/config/rs6000/rs6000-call.c b/gcc/config/rs6000/rs6000-call.c index 9fdf97bc803..15dd99ac68d 100644 --- a/gcc/config/rs6000/rs6000-call.c +++ b/gcc/config/rs6000/rs6000-call.c @@ -4585,6 +4585,8 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = { RS6000_BTI_bool_int, RS6000_BTI_double, RS6000_BTI_INTSI, 0 }, { P9V_BUILTIN_VEC_VSTDC, P9V_BUILTIN_VSTDCQP, RS6000_BTI_bool_int, RS6000_BTI_ieee128_float, RS6000_BTI_INTSI, 0 }, + { P9V_BUILTIN_VEC_VSTDC, P9V_BUILTIN_VSTDCTF, + RS6000_BTI_bool_int, RS6000_BTI_long_double, RS6000_BTI_INTSI, 0 }, { P9V_BUILTIN_VEC_VSTDCSP, P9V_BUILTIN_VSTDCSP, RS6000_BTI_bool_int, RS6000_BTI_float, RS6000_BTI_INTSI, 0 }, @@ -4592,6 +4594,8 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = { RS6000_BTI_bool_int, RS6000_BTI_double, RS6000_BTI_INTSI, 0 }, { P9V_BUILTIN_VEC_VSTDCQP, P9V_BUILTIN_VSTDCQP, RS6000_BTI_bool_int, RS6000_BTI_ieee128_float, RS6000_BTI_INTSI, 0 }, + { P9V_BUILTIN_VEC_VSTDCQP, P9V_BUILTIN_VSTDCTF, + RS6000_BTI_bool_int, RS6000_BTI_long_double, RS6000_BTI_INTSI, 0 }, { P9V_BUILTIN_VEC_VSTDCN, P9V_BUILTIN_VSTDCNSP, RS6000_BTI_bool_int, RS6000_BTI_float, 0, 0 }, @@ -4599,6 +4603,8 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = { RS6000_BTI_bool_int, RS6000_BTI_double, 0, 0 }, { P9V_BUILTIN_VEC_VSTDCN, P9V_BUILTIN_VSTDCNQP, RS6000_BTI_bool_int, RS6000_BTI_ieee128_float, 0, 0 }, + { P9V_BUILTIN_VEC_VSTDCN, P9V_BUILTIN_VSTDCNTF, + RS6000_BTI_bool_int, RS6000_BTI_long_double, 0, 0 }, { P9V_BUILTIN_VEC_VSTDCNSP, P9V_BUILTIN_VSTDCNSP, RS6000_BTI_bool_int, RS6000_BTI_float, 0, 0 }, @@ -4606,16 +4612,22 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = { RS6000_BTI_bool_int, RS6000_BTI_double, 0, 0 }, { P9V_BUILTIN_VEC_VSTDCNQP, P9V_BUILTIN_VSTDCNQP, RS6000_BTI_bool_int, RS6000_BTI_ieee128_float, 0, 0 }, + { P9V_BUILTIN_VEC_VSTDCNQP, P9V_BUILTIN_VSTDCNTF, + RS6000_BTI_bool_int, RS6000_BTI_long_double, 0, 0 }, { P9V_BUILTIN_VEC_VSEEDP, P9V_BUILTIN_VSEEDP, RS6000_BTI_UINTSI, RS6000_BTI_double, 0, 0 }, { P9V_BUILTIN_VEC_VSEEDP, P9V_BUILTIN_VSEEQP, RS6000_BTI_UINTDI, RS6000_BTI_ieee128_float, 0, 0 }, + { P9V_BUILTIN_VEC_VSEEDP, P9V_BUILTIN_VSEETF, + RS6000_BTI_UINTDI, RS6000_BTI_long_double, 0, 0 }, { P9V_BUILTIN_VEC_VSESDP, P9V_BUILTIN_VSESDP, RS6000_BTI_UINTDI, RS6000_BTI_double, 0, 0 }, { P9V_BUILTIN_VEC_VSESDP, P9V_BUILTIN_VSESQP, RS6000_BTI_UINTTI, RS6000_BTI_ieee128_float, 0, 0 }, + { P9V_BUILTIN_VEC_VSESDP, P9V_BUILTIN_VSESTF, + RS6000_BTI_UINTTI, RS6000_BTI_long_double, 0, 0 }, { P9V_BUILTIN_VEC_VSIEDP, P9V_BUILTIN_VSIEDP, RS6000_BTI_double, RS6000_BTI_UINTDI, RS6000_BTI_UINTDI, 0 }, @@ -4624,25 +4636,37 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = { { P9V_BUILTIN_VEC_VSIEDP, P9V_BUILTIN_VSIEQP, RS6000_BTI_ieee128_float, RS6000_BTI_UINTTI, RS6000_BTI_UINTDI, 0 }, + { P9V_BUILTIN_VEC_VSIEDP, P9V_BUILTIN_VSIETF, + RS6000_BTI_long_double, RS6000_BTI_UINTTI, RS6000_BTI_UINTDI, 0 }, { P9V_BUILTIN_VEC_VSIEDP, P9V_BUILTIN_VSIEQPF, RS6000_BTI_ieee128_float, RS6000_BTI_ieee128_float, RS6000_BTI_UINTDI, 0 }, + { P9V_BUILTIN_VEC_VSIEDP, P9V_BUILTIN_VSIETFF, + RS6000_BTI_long_double, RS6000_BTI_long_double, RS6000_BTI_UINTDI, 0 }, { P9V_BUILTIN_VEC_VSCEGT, P9V_BUILTIN_VSCEDPGT, RS6000_BTI_INTSI, RS6000_BTI_double, RS6000_BTI_double, 0 }, { P9V_BUILTIN_VEC_VSCEGT, P9V_BUILTIN_VSCEQPGT, RS6000_BTI_INTSI, RS6000_BTI_ieee128_float, RS6000_BTI_ieee128_float, 0 }, + { P9V_BUILTIN_VEC_VSCEGT, P9V_BUILTIN_VSCETFGT, + RS6000_BTI_INTSI, RS6000_BTI_long_double, RS6000_BTI_long_double, 0 }, { P9V_BUILTIN_VEC_VSCELT, P9V_BUILTIN_VSCEDPLT, RS6000_BTI_INTSI, RS6000_BTI_double, RS6000_BTI_double, 0 }, { P9V_BUILTIN_VEC_VSCELT, P9V_BUILTIN_VSCEQPLT, RS6000_BTI_INTSI, RS6000_BTI_ieee128_float, RS6000_BTI_ieee128_float, 0 }, + { P9V_BUILTIN_VEC_VSCELT, P9V_BUILTIN_VSCETFLT, + RS6000_BTI_INTSI, RS6000_BTI_long_double, RS6000_BTI_long_double, 0 }, { P9V_BUILTIN_VEC_VSCEEQ, P9V_BUILTIN_VSCEDPEQ, RS6000_BTI_INTSI, RS6000_BTI_double, RS6000_BTI_double, 0 }, { P9V_BUILTIN_VEC_VSCEEQ, P9V_BUILTIN_VSCEQPEQ, RS6000_BTI_INTSI, RS6000_BTI_ieee128_float, RS6000_BTI_ieee128_float, 0 }, + { P9V_BUILTIN_VEC_VSCEEQ, P9V_BUILTIN_VSCETFEQ, + RS6000_BTI_INTSI, RS6000_BTI_long_double, RS6000_BTI_long_double, 0 }, { P9V_BUILTIN_VEC_VSCEUO, P9V_BUILTIN_VSCEDPUO, RS6000_BTI_INTSI, RS6000_BTI_double, RS6000_BTI_double, 0 }, { P9V_BUILTIN_VEC_VSCEUO, P9V_BUILTIN_VSCEQPUO, RS6000_BTI_INTSI, RS6000_BTI_ieee128_float, RS6000_BTI_ieee128_float, 0 }, + { P9V_BUILTIN_VEC_VSCEUO, P9V_BUILTIN_VSCETFUO, + RS6000_BTI_INTSI, RS6000_BTI_long_double, RS6000_BTI_long_double, 0 }, { P9V_BUILTIN_VEC_XL_LEN_R, P9V_BUILTIN_XL_LEN_R, RS6000_BTI_unsigned_V16QI, ~RS6000_BTI_UINTQI, @@ -12532,6 +12556,22 @@ rs6000_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED, case CODE_FOR_xsiexpqp_kf: icode = CODE_FOR_xsiexpqp_tf; break; case CODE_FOR_xsiexpqpf_kf: icode = CODE_FOR_xsiexpqpf_tf; break; case CODE_FOR_xststdcqp_kf: icode = CODE_FOR_xststdcqp_tf; break; + + case CODE_FOR_xscmpexpqp_eq_kf: + icode = CODE_FOR_xscmpexpqp_eq_tf; + break; + + case CODE_FOR_xscmpexpqp_lt_kf: + icode = CODE_FOR_xscmpexpqp_lt_tf; + break; + + case CODE_FOR_xscmpexpqp_gt_kf: + icode = CODE_FOR_xscmpexpqp_gt_tf; + break; + + case CODE_FOR_xscmpexpqp_unordered_kf: + icode = CODE_FOR_xscmpexpqp_unordered_tf; + break; } if (TARGET_DEBUG_BUILTIN)