From patchwork Thu Oct 22 07:07:09 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Padmarao Begari X-Patchwork-Id: 1386033 X-Patchwork-Delegate: uboot@andestech.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=quarantine dis=none) header.from=microchip.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=microchip.com header.i=@microchip.com header.a=rsa-sha256 header.s=mchp header.b=o0RMZcAh; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4CH03d54jKz9sTc for ; Thu, 22 Oct 2020 18:53:33 +1100 (AEDT) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 5D71182431; Thu, 22 Oct 2020 09:53:25 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=fail (p=quarantine dis=none) header.from=microchip.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=microchip.com header.i=@microchip.com header.b="o0RMZcAh"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id E95188240E; Thu, 22 Oct 2020 09:53:23 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.0 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,RCVD_IN_MSPIKE_H3,RCVD_IN_MSPIKE_WL, SPF_HELO_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.2 Received: from esa2.microchip.iphmx.com (esa2.microchip.iphmx.com [68.232.149.84]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 6C2E88240E for ; Thu, 22 Oct 2020 09:53:19 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=quarantine dis=none) header.from=microchip.com Authentication-Results: phobos.denx.de; spf=fail smtp.mailfrom=Padmarao.Begari@microchip.com DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1603353199; x=1634889199; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=bdsEBjTlG4jvuUct2AvsqU1umago7yi0DCTi8DdFVFo=; b=o0RMZcAhSpDQfRYe1INEzEhmQGCFXhWE3odggRM4qyHXcdCPB4Nq43fU 536sJSYcmu3FPE5ZXlIKDMFQvW7QhAShev2cOq6nCFkTEqH+MYcdqJKVg L/Ff1kXH+rkXx2wQ1iES5p+2E/5pq2hfs50pJCvBe8UKbszm4wApIjDAH L8ZeYcU3ur+c/wbmCvoL3MEJ+uoDjW9I/KbOuDk6bL96191y0bFS0tG93 Bz19NneiCFohquNQMe+QTGrtu7CtcgAg8s/qFzbWC0jHoS9TyckeN29KZ RTKPXZJOobSyhFZUhNFXAqjgs/rRdFidn7y+2W1n6C7DZAp6p8rKsBjYl Q==; IronPort-SDR: x/2FOtpcNY/AXS4jrFD8tLDEWGI7xTcSmZFfU6SPfkB0R/ua46F6bgwKIJavMBB6KBPPJ64nAc bE3hPsXL4x9YJH+xRPltZSWpjsFi6Hmn1/s5aBe0Jv2upVZWl2ngS+Dzwm//KFV6zv644lrALv Gv6ChI6q1j6YOZbVpbR9d6z48IR8Msi4XYFhrtYZn9V+HYj9vU6DBLor+7/PyOiZmqZjrd+dAB gAQsBMXvm9Nn28dqPli873tP664I9bJ2fPgFDHSGparH8bH3n8TmZ+oiy/PR0aPNis9Rzo8e/o 5cg= X-IronPort-AV: E=Sophos;i="5.77,404,1596524400"; d="scan'208";a="93492928" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa2.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 22 Oct 2020 00:53:17 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1979.3; Thu, 22 Oct 2020 00:21:20 -0700 Received: from padmarao-VirtualBox.microchip.com (10.10.115.15) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.1979.3 via Frontend Transport; Thu, 22 Oct 2020 00:21:14 -0700 From: Padmarao Begari To: , , , , , , CC: , , , , , Padmarao Begari Subject: [PATCH v2 1/7] riscv: Add DMA 64-bit address support Date: Thu, 22 Oct 2020 12:37:09 +0530 Message-ID: <20201022070715.14759-2-padmarao.begari@microchip.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201022070715.14759-1-padmarao.begari@microchip.com> References: <20201022070715.14759-1-padmarao.begari@microchip.com> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.3 at phobos.denx.de X-Virus-Status: Clean dma_addr_t holds any valid DMA address. If the DMA API only uses 32/64-bit addresses, dma_addr_t need only be 32/64 bits wide. Signed-off-by: Padmarao Begari Reviewed-by: Anup Patel --- arch/riscv/Kconfig | 5 +++++ arch/riscv/include/asm/types.h | 4 ++++ 2 files changed, 9 insertions(+) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index aaa3b833a5..7ab1ccff40 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -152,6 +152,11 @@ config 32BIT config 64BIT bool +config DMA_ADDR_T_64BIT + bool + depends on 64BIT + default n + config SIFIVE_CLINT bool depends on RISCV_MMODE || SPL_RISCV_MMODE diff --git a/arch/riscv/include/asm/types.h b/arch/riscv/include/asm/types.h index 403cf9a48f..b800b2d221 100644 --- a/arch/riscv/include/asm/types.h +++ b/arch/riscv/include/asm/types.h @@ -29,7 +29,11 @@ typedef unsigned short umode_t; #include +#ifdef CONFIG_DMA_ADDR_T_64BIT +typedef u64 dma_addr_t; +#else typedef u32 dma_addr_t; +#endif typedef unsigned long phys_addr_t; typedef unsigned long phys_size_t; From patchwork Thu Oct 22 07:07:10 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Padmarao Begari X-Patchwork-Id: 1386003 X-Patchwork-Delegate: uboot@andestech.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=quarantine dis=none) header.from=microchip.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=microchip.com header.i=@microchip.com header.a=rsa-sha256 header.s=mchp header.b=z9dkIbZo; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4CGzML1VcHz9sTc for ; Thu, 22 Oct 2020 18:22:06 +1100 (AEDT) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 3BFCE82424; Thu, 22 Oct 2020 09:22:02 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=fail (p=quarantine dis=none) header.from=microchip.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=microchip.com header.i=@microchip.com header.b="z9dkIbZo"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id A1D6E82423; Thu, 22 Oct 2020 09:22:00 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.0 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,RCVD_IN_MSPIKE_H3,RCVD_IN_MSPIKE_WL, SPF_HELO_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.2 Received: from esa1.microchip.iphmx.com (esa1.microchip.iphmx.com [68.232.147.91]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 1387882423 for ; Thu, 22 Oct 2020 09:21:56 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=quarantine dis=none) header.from=microchip.com Authentication-Results: phobos.denx.de; spf=fail smtp.mailfrom=Padmarao.Begari@microchip.com DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1603351317; x=1634887317; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=+jj8kboEUJUSVy8ihZhye/ED321vnb1+ZLHcNkEwgOw=; b=z9dkIbZo0SIy/vMIjw2SlQACa7Z4ZMP4VOSn7BQlUrKiMs1RXVYVgTjo ojPmTM6AsbVBWZXSzvUDfsPjMG0u/t7pUOZduHLgnm5up8rFh1P8KtLv0 pkSrUVZweAbtTAduxQ0I74K4z1DtozgKbD0t21TcK4Qjgu8FsUuDoAXkM /lW+YB7PF2Khr8sNRIinGYDJ98yekxh5ftx+31oKqQoN0S3lEqfqut2hU Pf6pADVC1gZjxi5wYjvE7g4ZPZhQ5rBhk3frQ4pJMAtLDcYN30wWsZgXz 98VoPSd4xCWFw7rRFbv7smSalNparBe8EEH740H3obvNo2hiwj2dpb2Hn A==; IronPort-SDR: UDo8KXfi2RgtOi9qUJ8c9yo7cdugROotbtMmoaKDtd4ZP4850BNMwvZxXYMWMpCwzmSNFglHkE P/RfzsUy5CcfJrQ6sydOMN6R4lSdEW6/Wt8GDA2PP4AKUu9QhYS1YtqzQ97eFZQ2bAU3fO9i/3 /bzLmudScgDdEy8RaKt6M7iA0ASP9o0Epy+MKFm6+W/PaC7x5fvx3b1USe5Dbuu9xOnsHZTdP3 WQvCZGHIxG8UAmuvHLttCCBhiOCQXRVyL1DNopPA3hX2ruIUUaFMwIUg/2qTlU9sGKZubxUHQZ 3E8= X-IronPort-AV: E=Sophos;i="5.77,404,1596524400"; d="scan'208";a="100488915" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa1.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 22 Oct 2020 00:21:54 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1979.3; Thu, 22 Oct 2020 00:21:34 -0700 Received: from padmarao-VirtualBox.microchip.com (10.10.115.15) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.1979.3 via Frontend Transport; Thu, 22 Oct 2020 00:21:28 -0700 From: Padmarao Begari To: , , , , , , CC: , , , , , Padmarao Begari Subject: [PATCH v2 2/7] net: macb: Add DMA 64-bit address support for macb Date: Thu, 22 Oct 2020 12:37:10 +0530 Message-ID: <20201022070715.14759-3-padmarao.begari@microchip.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201022070715.14759-1-padmarao.begari@microchip.com> References: <20201022070715.14759-1-padmarao.begari@microchip.com> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.3 at phobos.denx.de X-Virus-Status: Clean Enable 64-bit DMA support in the macb driver when CONFIG_DMA_ADDR_T_64BIT is enabled. 32-bit DMA is enabled by default. Signed-off-by: Padmarao Begari --- drivers/net/macb.c | 46 ++++++++++++++++++++++++++++++++++++++-------- drivers/net/macb.h | 6 ++++++ 2 files changed, 44 insertions(+), 8 deletions(-) diff --git a/drivers/net/macb.c b/drivers/net/macb.c index b80a259ff7..e0e86a274e 100644 --- a/drivers/net/macb.c +++ b/drivers/net/macb.c @@ -81,6 +81,10 @@ DECLARE_GLOBAL_DATA_PTR; struct macb_dma_desc { u32 addr; u32 ctrl; +#ifdef CONFIG_DMA_ADDR_T_64BIT + u32 addrh; + u32 unused; +#endif }; #define DMA_DESC_BYTES(n) (n * sizeof(struct macb_dma_desc)) @@ -326,7 +330,10 @@ static int _macb_send(struct macb_device *macb, const char *name, void *packet, } macb->tx_ring[tx_head].ctrl = ctrl; - macb->tx_ring[tx_head].addr = paddr; + macb->tx_ring[tx_head].addr = lower_32_bits(paddr); +#ifdef CONFIG_DMA_ADDR_T_64BIT + macb->tx_ring[tx_head].addrh = upper_32_bits(paddr); +#endif barrier(); macb_flush_ring_desc(macb, TX); macb_writel(macb, NCR, MACB_BIT(TE) | MACB_BIT(RE) | MACB_BIT(TSTART)); @@ -732,9 +739,20 @@ static int gmac_init_multi_queues(struct macb_device *macb) flush_dcache_range(macb->dummy_desc_dma, macb->dummy_desc_dma + ALIGN(MACB_TX_DUMMY_DMA_DESC_SIZE, PKTALIGN)); - for (i = 1; i < num_queues; i++) - gem_writel_queue_TBQP(macb, macb->dummy_desc_dma, i - 1); - + for (i = 1; i < num_queues; i++) { + gem_writel_queue_TBQP(macb, + lower_32_bits(macb->dummy_desc_dma), i - 1); +#ifdef CONFIG_DMA_ADDR_T_64BIT + gem_writel_queue_TBQPH(macb, + upper_32_bits(macb->dummy_desc_dma), i - 1); +#endif + gem_writel_queue_RBQP(macb, + lower_32_bits(macb->dummy_desc_dma), i - 1); +#ifdef CONFIG_DMA_ADDR_T_64BIT + gem_writel_queue_RBQPH(macb, + upper_32_bits(macb->dummy_desc_dma), i - 1); +#endif + } return 0; } @@ -760,6 +778,9 @@ static void gmac_configure_dma(struct macb_device *macb) dmacfg &= ~GEM_BIT(ENDIA_DESC); dmacfg &= ~GEM_BIT(ADDR64); +#ifdef CONFIG_DMA_ADDR_T_64BIT + dmacfg |= GEM_BIT(ADDR64); +#endif gem_writel(macb, DMACFG, dmacfg); } @@ -786,8 +807,11 @@ static int _macb_init(struct macb_device *macb, const char *name) for (i = 0; i < MACB_RX_RING_SIZE; i++) { if (i == (MACB_RX_RING_SIZE - 1)) paddr |= MACB_BIT(RX_WRAP); - macb->rx_ring[i].addr = paddr; + macb->rx_ring[i].addr = lower_32_bits(paddr); macb->rx_ring[i].ctrl = 0; +#ifdef CONFIG_DMA_ADDR_T_64BIT + macb->rx_ring[i].addrh = upper_32_bits(paddr); +#endif paddr += macb->rx_buffer_size; } macb_flush_ring_desc(macb, RX); @@ -800,6 +824,9 @@ static int _macb_init(struct macb_device *macb, const char *name) MACB_BIT(TX_WRAP); else macb->tx_ring[i].ctrl = MACB_BIT(TX_USED); +#ifdef CONFIG_DMA_ADDR_T_64BIT + macb->tx_ring[i].addrh = 0x0; +#endif } macb_flush_ring_desc(macb, TX); @@ -812,9 +839,12 @@ static int _macb_init(struct macb_device *macb, const char *name) gem_writel(macb, DMACFG, MACB_ZYNQ_GEM_DMACR_INIT); #endif - macb_writel(macb, RBQP, macb->rx_ring_dma); - macb_writel(macb, TBQP, macb->tx_ring_dma); - + macb_writel(macb, RBQP, lower_32_bits(macb->rx_ring_dma)); + macb_writel(macb, TBQP, lower_32_bits(macb->tx_ring_dma)); +#ifdef CONFIG_DMA_ADDR_T_64BIT + macb_writel(macb, RBQPH, upper_32_bits(macb->rx_ring_dma)); + macb_writel(macb, TBQPH, upper_32_bits(macb->tx_ring_dma)); +#endif if (macb_is_gem(macb)) { /* Initialize DMA properties */ gmac_configure_dma(macb); diff --git a/drivers/net/macb.h b/drivers/net/macb.h index 9b16383eba..72b84ae96e 100644 --- a/drivers/net/macb.h +++ b/drivers/net/macb.h @@ -768,5 +768,11 @@ #define GEM_RX_CSUM_CHECKED_MASK 2 #define gem_writel_queue_TBQP(port, value, queue_num) \ writel((value), (port)->regs + GEM_TBQP(queue_num)) +#define gem_writel_queue_TBQPH(port, value, queue_num) \ + writel((value), (port)->regs + GEM_TBQPH(queue_num)) +#define gem_writel_queue_RBQP(port, value, queue_num) \ + writel((value), (port)->regs + GEM_RBQP(queue_num)) +#define gem_writel_queue_RBQPH(port, value, queue_num) \ + writel((value), (port)->regs + GEM_RBQPH(queue_num)) #endif /* __DRIVERS_MACB_H__ */ From patchwork Thu Oct 22 07:07:11 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Padmarao Begari X-Patchwork-Id: 1386004 X-Patchwork-Delegate: uboot@andestech.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=quarantine dis=none) header.from=microchip.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=microchip.com header.i=@microchip.com header.a=rsa-sha256 header.s=mchp header.b=EFFqf4nw; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4CGzMf4bVPz9sTc for ; Thu, 22 Oct 2020 18:22:22 +1100 (AEDT) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 32BE282456; Thu, 22 Oct 2020 09:22:10 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=fail (p=quarantine dis=none) header.from=microchip.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=microchip.com header.i=@microchip.com header.b="EFFqf4nw"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 67D0382452; Thu, 22 Oct 2020 09:22:09 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.0 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,RCVD_IN_MSPIKE_H4,RCVD_IN_MSPIKE_WL, SPF_HELO_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.2 Received: from esa5.microchip.iphmx.com (esa5.microchip.iphmx.com [216.71.150.166]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 18F6B82441 for ; Thu, 22 Oct 2020 09:22:05 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=quarantine dis=none) header.from=microchip.com Authentication-Results: phobos.denx.de; spf=fail smtp.mailfrom=Padmarao.Begari@microchip.com DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1603351327; x=1634887327; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=3oHIMg9ZBgBocn0QxUESxExZQu1Tni9L1uVdmN+LLik=; b=EFFqf4nwy6lejcSDDAVfxfufP/UdePZYvtYWgklDegIjt6hPwDCFZqZU 4JF8IdeHdc9PKOBSy8FT+fnb8p8zDDMqzsVZ6dUXasD9Q28+Nl0uRzHc4 79Pg1gA9vHi9P2/fo8IgcBnFPiWdJBrlPKmyyVkV+SJsNh0bOSmFm2wHi 5bBEmxvagfJygFGCb5ZUVF85x/MShH2A4e5SlFlGUZGOxQTcJ3EMCGcPu N/HGEPUBMgtIJkwkIR3oqVQx25smtcIY1PwL/wHg4MJS+xoZCB2z4JwFb UQ93E4hBZexAL+amJREAq1rovTTFd226DFXbDzphygofLHEvnxp6mmnDJ g==; IronPort-SDR: /N6UqZT8QIY0u696en4NBZV4HAXZM8AJHyYgCFl/6KTDQ0h1UUs4Vu6C1H6ffivICFNUAe9/P3 CgZLEg2e2MgZNTBaFDdObhOchS9kuh4stULVU+59va7BOnyC8KtgqK3OQ0XQ9IWpM5CvO/f+5q 14nvbiyku0HzT9kQdRy5I2nQG0lhSo7sN31TvXfhYopHmtZmbHVjOx99MgwX8KCOAG3bBBGMKA O2a6mS7E8cwxh76+/vE7QzWBIQgLjCykV5/cFxLf1f3s9TY7ftBY/Fs1XVNWjfi/fH7VIC2L3f VVI= X-IronPort-AV: E=Sophos;i="5.77,404,1596524400"; d="scan'208";a="95584599" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa5.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 22 Oct 2020 00:22:04 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1979.3; Thu, 22 Oct 2020 00:22:00 -0700 Received: from padmarao-VirtualBox.microchip.com (10.10.115.15) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.1979.3 via Frontend Transport; Thu, 22 Oct 2020 00:21:54 -0700 From: Padmarao Begari To: , , , , , , CC: , , , , , Padmarao Begari Subject: [PATCH v2 3/7] net: macb: Add phy address to read it from device tree Date: Thu, 22 Oct 2020 12:37:11 +0530 Message-ID: <20201022070715.14759-4-padmarao.begari@microchip.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201022070715.14759-1-padmarao.begari@microchip.com> References: <20201022070715.14759-1-padmarao.begari@microchip.com> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.3 at phobos.denx.de X-Virus-Status: Clean Read phy address from device tree and use it to find the phy device if not found then search in the range of 0 to 31. Signed-off-by: Padmarao Begari --- drivers/net/macb.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/drivers/net/macb.c b/drivers/net/macb.c index e0e86a274e..7f592d510c 100644 --- a/drivers/net/macb.c +++ b/drivers/net/macb.c @@ -477,6 +477,12 @@ static int macb_phy_find(struct macb_device *macb, const char *name) int i; u16 phy_id; + phy_id = macb_mdio_read(macb, macb->phy_addr, MII_PHYSID1); + if (phy_id != 0xffff) { + printf("%s: PHY present at %d\n", name, macb->phy_addr); + return 0; + } + /* Search for PHY... */ for (i = 0; i < 32; i++) { macb->phy_addr = i; @@ -1256,6 +1262,8 @@ static int macb_eth_probe(struct udevice *dev) struct macb_device *macb = dev_get_priv(dev); const char *phy_mode; int ret; + u32 phy_addr; + ofnode node; phy_mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy-mode", NULL); @@ -1266,6 +1274,13 @@ static int macb_eth_probe(struct udevice *dev) return -EINVAL; } + /* Look for a PHY node under the Ethernet node */ + node = dev_read_subnode(dev, "ethernet-phy"); + if (ofnode_valid(node)) { + ofnode_read_u32(node, "reg", &phy_addr); + macb->phy_addr = phy_addr; + } + macb->regs = (void *)pdata->iobase; macb->is_big_endian = (cpu_to_be32(0x12345678) == 0x12345678); From patchwork Thu Oct 22 07:07:12 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Padmarao Begari X-Patchwork-Id: 1386015 X-Patchwork-Delegate: uboot@andestech.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=quarantine dis=none) header.from=microchip.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=microchip.com header.i=@microchip.com header.a=rsa-sha256 header.s=mchp header.b=MIOToboV; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4CGznP3KmQz9sVN for ; Thu, 22 Oct 2020 18:41:13 +1100 (AEDT) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id CC10582423; Thu, 22 Oct 2020 09:41:02 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=fail (p=quarantine dis=none) header.from=microchip.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=microchip.com header.i=@microchip.com header.b="MIOToboV"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id BABD582424; Thu, 22 Oct 2020 09:41:00 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.0 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,RCVD_IN_MSPIKE_H3,RCVD_IN_MSPIKE_WL, SPF_HELO_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.2 Received: from esa2.microchip.iphmx.com (esa2.microchip.iphmx.com [68.232.149.84]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 41F6F8240E for ; Thu, 22 Oct 2020 09:40:53 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=quarantine dis=none) header.from=microchip.com Authentication-Results: phobos.denx.de; spf=fail smtp.mailfrom=Padmarao.Begari@microchip.com DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1603352453; x=1634888453; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=64d5cMrOvzSsocJf9sqTcWfOsP9ODEu+vkETG6l5yhM=; b=MIOToboVf+yWu8vTLhQfc1DkXA2X4uc6fsDyPXsKW+feA8YIEftnV3y/ YwivDkOq44d+Fqfvlf3SZGxmGw/nz+aY0S9rzZl/Z7V/o75m2MIVfBTzP hLIdsZ/Gb0iGYpbY/XyKBxjI1HeX6aMhyn0Du63M4dQbItRHam+dlwRkL LqZ5E/ncN/IPKVG9XP+aMD3v+x63iXRRJhNh8Ls5SJgeZ+SZ+kvzehsy6 zn7jNR6eKbNH4EUnEsGkvmxWiaSPfqEomL46v/wv9xtfiEYUxL86buADR WAjk5x9XMvibU7VQQNVHCDWM0ailAkEB3sZWjQBRRI4WOMcR9KLhDh52y w==; IronPort-SDR: vgNcy29VBak/x2Vtrc74pIin22xR+gY7lL2ijrlpabyhnUPMAUvpXyQL92jntztfp18vGvECat SKg9AlW2YflfpthgMqSeFUeFAgnoBt4wHi+HhoJ0GC7Q49LFay3kPYnXo6x6NgmnSARiNeExdV Nakj9U2yjiNz5cUIqN3d4fu0pRzdH1aLKY0ADU/buFUglTHPTs3SF43s4sgKpCt2wia2Sd/Qrz gxfmPMcvIuAraIm+BpV+ufxiWAblGGuj0xlf90xQakao+1XHwb4x1yQYmC6Pv1PqfDf7woqF6G 2bE= X-IronPort-AV: E=Sophos;i="5.77,404,1596524400"; d="scan'208";a="93492245" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa2.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 22 Oct 2020 00:40:51 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1979.3; Thu, 22 Oct 2020 00:22:08 -0700 Received: from padmarao-VirtualBox.microchip.com (10.10.115.15) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.1979.3 via Frontend Transport; Thu, 22 Oct 2020 00:22:03 -0700 From: Padmarao Begari To: , , , , , , CC: , , , , , Padmarao Begari Subject: [PATCH v2 4/7] clk: Add Microchip PolarFire SoC clock driver Date: Thu, 22 Oct 2020 12:37:12 +0530 Message-ID: <20201022070715.14759-5-padmarao.begari@microchip.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201022070715.14759-1-padmarao.begari@microchip.com> References: <20201022070715.14759-1-padmarao.begari@microchip.com> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.3 at phobos.denx.de X-Virus-Status: Clean Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari Reviewed-by: Anup Patel --- drivers/clk/Kconfig | 1 + drivers/clk/Makefile | 1 + drivers/clk/microchip/Kconfig | 5 + drivers/clk/microchip/Makefile | 1 + drivers/clk/microchip/clk_pfsoc.c | 127 +++++++++++++ drivers/clk/microchip/clk_pfsoc.h | 19 ++ drivers/clk/microchip/clk_pfsoc_cfg.c | 134 ++++++++++++++ drivers/clk/microchip/clk_pfsoc_periph.c | 173 ++++++++++++++++++ .../dt-bindings/clock/microchip,pfsoc-clock.h | 45 +++++ 9 files changed, 506 insertions(+) create mode 100644 drivers/clk/microchip/Kconfig create mode 100644 drivers/clk/microchip/Makefile create mode 100644 drivers/clk/microchip/clk_pfsoc.c create mode 100644 drivers/clk/microchip/clk_pfsoc.h create mode 100644 drivers/clk/microchip/clk_pfsoc_cfg.c create mode 100644 drivers/clk/microchip/clk_pfsoc_periph.c create mode 100644 include/dt-bindings/clock/microchip,pfsoc-clock.h diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index 4dfbad7986..1161fe7b5a 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -173,6 +173,7 @@ source "drivers/clk/exynos/Kconfig" source "drivers/clk/imx/Kconfig" source "drivers/clk/kendryte/Kconfig" source "drivers/clk/meson/Kconfig" +source "drivers/clk/microchip/Kconfig" source "drivers/clk/mvebu/Kconfig" source "drivers/clk/owl/Kconfig" source "drivers/clk/renesas/Kconfig" diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index d1e295ac7c..bd8a6eed88 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -28,6 +28,7 @@ obj-$(CONFIG_CLK_EXYNOS) += exynos/ obj-$(CONFIG_$(SPL_TPL_)CLK_INTEL) += intel/ obj-$(CONFIG_CLK_HSDK) += clk-hsdk-cgu.o obj-$(CONFIG_CLK_K210) += kendryte/ +obj-$(CONFIG_CLK_MPFS) += microchip/ obj-$(CONFIG_CLK_MPC83XX) += mpc83xx_clk.o obj-$(CONFIG_CLK_OCTEON) += clk_octeon.o obj-$(CONFIG_CLK_OWL) += owl/ diff --git a/drivers/clk/microchip/Kconfig b/drivers/clk/microchip/Kconfig new file mode 100644 index 0000000000..b70241559d --- /dev/null +++ b/drivers/clk/microchip/Kconfig @@ -0,0 +1,5 @@ +config CLK_MPFS + bool "Clock support for Microchip PolarFire SoC" + depends on CLK && CLK_CCF + help + This enables support clock driver for Microchip PolarFire SoC platform. diff --git a/drivers/clk/microchip/Makefile b/drivers/clk/microchip/Makefile new file mode 100644 index 0000000000..c7f5ad21ae --- /dev/null +++ b/drivers/clk/microchip/Makefile @@ -0,0 +1 @@ +obj-y += clk_pfsoc.o clk_pfsoc_cfg.o clk_pfsoc_periph.o diff --git a/drivers/clk/microchip/clk_pfsoc.c b/drivers/clk/microchip/clk_pfsoc.c new file mode 100644 index 0000000000..dd0e9cacb8 --- /dev/null +++ b/drivers/clk/microchip/clk_pfsoc.c @@ -0,0 +1,127 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2020 Microchip Technology Inc. + * Padmarao Begari + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "clk_pfsoc.h" + +/* All methods are delegated to CCF clocks */ + +static ulong pfsoc_clk_get_rate(struct clk *clk) +{ + struct clk *c; + int err = clk_get_by_id(clk->id, &c); + + if (err) + return err; + return clk_get_rate(c); +} + +static ulong pfsoc_clk_set_rate(struct clk *clk, unsigned long rate) +{ + struct clk *c; + int err = clk_get_by_id(clk->id, &c); + + if (err) + return err; + return clk_set_rate(c, rate); +} + +static int pfsoc_clk_set_parent(struct clk *clk, struct clk *parent) +{ + struct clk *c, *p; + int err = clk_get_by_id(clk->id, &c); + + if (err) + return err; + + err = clk_get_by_id(parent->id, &p); + if (err) + return err; + + return clk_set_parent(c, p); +} + +static int pfsoc_clk_endisable(struct clk *clk, bool enable) +{ + struct clk *c; + int err = clk_get_by_id(clk->id, &c); + + if (err) + return err; + return enable ? clk_enable(c) : clk_disable(c); +} + +static int pfsoc_clk_enable(struct clk *clk) +{ + return pfsoc_clk_endisable(clk, true); +} + +static int pfsoc_clk_disable(struct clk *clk) +{ + return pfsoc_clk_endisable(clk, false); +} + +static int pfsoc_clk_probe(struct udevice *dev) +{ + int ret; + void __iomem *base; + u32 clk_rate; + struct clk *clk; + const char *parent_clk_name; + + base = dev_read_addr_ptr(dev); + if (!base) + return -ENODEV; + + clk = kzalloc(sizeof(*clk), GFP_KERNEL); + if (!clk) + return -ENOMEM; + + ret = clk_get_by_index(dev, 0, clk); + if (ret) + return ret; + + dev_read_u32(clk->dev, "clock-frequency", &clk_rate); + parent_clk_name = clk->dev->name; + + ret = pfsoc_clk_register_cfgs(base, clk_rate, parent_clk_name); + if (ret) + return ret; + + ret = pfsoc_clk_register_periphs(base, clk_rate, "clk_ahb"); + + return ret; +} + +static const struct clk_ops pfsoc_clk_ops = { + .set_rate = pfsoc_clk_set_rate, + .get_rate = pfsoc_clk_get_rate, + .set_parent = pfsoc_clk_set_parent, + .enable = pfsoc_clk_enable, + .disable = pfsoc_clk_disable, +}; + +static const struct udevice_id pfsoc_of_match[] = { + { .compatible = "microchip,pfsoc-clkcfg" }, + { } +}; + +U_BOOT_DRIVER(pfsoc_clk) = { + .name = "pfsoc_clk", + .id = UCLASS_CLK, + .of_match = pfsoc_of_match, + .ops = &pfsoc_clk_ops, + .probe = pfsoc_clk_probe, +}; diff --git a/drivers/clk/microchip/clk_pfsoc.h b/drivers/clk/microchip/clk_pfsoc.h new file mode 100644 index 0000000000..3058b83f0d --- /dev/null +++ b/drivers/clk/microchip/clk_pfsoc.h @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2020 Microchip Technology Inc. + * Padmarao Begari + */ +#ifndef __MICROCHIP_PFSOC_CLK_H +#define __MICROCHIP_PFSOC_CLK_H + +#include + +int pfsoc_clk_register_cfgs(void __iomem *base, u32 clk_rate, + const char *parent_name); +int pfsoc_clk_register_periphs(void __iomem *base, u32 clk_rate, + const char *parent_name); +int divider_get_val(unsigned long rate, unsigned long parent_rate, + const struct clk_div_table *table, + u8 width, unsigned long flags); + +#endif /* __MICROCHIP_PFSOC_CLK_H */ diff --git a/drivers/clk/microchip/clk_pfsoc_cfg.c b/drivers/clk/microchip/clk_pfsoc_cfg.c new file mode 100644 index 0000000000..2174b5a03e --- /dev/null +++ b/drivers/clk/microchip/clk_pfsoc_cfg.c @@ -0,0 +1,134 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2020 Microchip Technology Inc. + * Padmarao Begari + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "clk_pfsoc.h" + +#define PFSOC_CFG_CLOCK "pfsoc_cfg_clock" + +#define REG_CLOCK_CONFIG_CR 0x08 + +static const struct clk_div_table pfsoc_div_cpu_axi_table[] = { + { 0, 1 }, { 1, 2 }, { 2, 4 }, { 3, 8 }, + { 0, 0 } +}; + +static const struct clk_div_table pfsoc_div_ahb_table[] = { + { 1, 2 }, { 2, 4}, { 3, 8 }, + { 0, 0 } +}; + +struct pfsoc_cfg_clock { + unsigned int id; + const char *name; + u8 shift; + u8 width; + const struct clk_div_table *table; + unsigned long flags; +}; + +struct pfsoc_cfg_hw_clock { + struct pfsoc_cfg_clock cfg; + void __iomem *sys_base; + u32 prate; + struct clk hw; +}; + +#define to_pfsoc_cfg_clk(_hw) container_of(_hw, struct pfsoc_cfg_hw_clock, hw) + +static ulong pfsoc_cfg_clk_recalc_rate(struct clk *hw) +{ + struct pfsoc_cfg_hw_clock *cfg_hw = to_pfsoc_cfg_clk(hw); + struct pfsoc_cfg_clock *cfg = &cfg_hw->cfg; + void __iomem *base_addr = cfg_hw->sys_base; + unsigned long rate; + u32 val; + + val = readl(base_addr + REG_CLOCK_CONFIG_CR) >> cfg->shift; + val &= clk_div_mask(cfg->width); + rate = cfg_hw->prate / (1u << val); + hw->rate = rate; + + return rate; +} + +static ulong pfsoc_cfg_clk_set_rate(struct clk *hw, ulong rate) +{ + struct pfsoc_cfg_hw_clock *cfg_hw = to_pfsoc_cfg_clk(hw); + struct pfsoc_cfg_clock *cfg = &cfg_hw->cfg; + void __iomem *base_addr = cfg_hw->sys_base; + u32 val; + int divider_setting; + + divider_setting = divider_get_val(rate, cfg_hw->prate, cfg->table, cfg->width, cfg->flags); + + if (divider_setting < 0) + return divider_setting; + + val = readl(base_addr + REG_CLOCK_CONFIG_CR); + val &= ~(clk_div_mask(cfg->width) << cfg_hw->cfg.shift); + val |= divider_setting << cfg->shift; + writel(val, base_addr + REG_CLOCK_CONFIG_CR); + + return clk_get_rate(hw); +} + +#define CLK_CFG(_id, _name, _shift, _width, _table, _flags) { \ + .cfg.id = _id, \ + .cfg.name = _name, \ + .cfg.shift = _shift, \ + .cfg.width = _width, \ + .cfg.table = _table, \ + .cfg.flags = _flags, \ + } + +static struct pfsoc_cfg_hw_clock pfsoc_cfg_clks[] = { + CLK_CFG(CLK_CPU, "clk_cpu", 0, 2, pfsoc_div_cpu_axi_table, 0), + CLK_CFG(CLK_AXI, "clk_axi", 2, 2, pfsoc_div_cpu_axi_table, 0), + CLK_CFG(CLK_AHB, "clk_ahb", 4, 2, pfsoc_div_ahb_table, 0), +}; + +int pfsoc_clk_register_cfgs(void __iomem *base, u32 clk_rate, + const char *parent_name) +{ + int ret; + int i, id, num_clks; + const char *name; + struct clk *hw; + + num_clks = ARRAY_SIZE(pfsoc_cfg_clks); + for (i = 0; i < num_clks; i++) { + hw = &pfsoc_cfg_clks[i].hw; + pfsoc_cfg_clks[i].sys_base = base; + pfsoc_cfg_clks[i].prate = clk_rate; + name = pfsoc_cfg_clks[i].cfg.name; + ret = clk_register(hw, PFSOC_CFG_CLOCK, name, parent_name); + if (ret) + ERR_PTR(ret); + id = pfsoc_cfg_clks[i].cfg.id; + clk_dm(id, hw); + } + return 0; +} + +const struct clk_ops pfsoc_cfg_clk_ops = { + .set_rate = pfsoc_cfg_clk_set_rate, + .get_rate = pfsoc_cfg_clk_recalc_rate, +}; + +U_BOOT_DRIVER(pfsoc_cfg_clock) = { + .name = PFSOC_CFG_CLOCK, + .id = UCLASS_CLK, + .ops = &pfsoc_cfg_clk_ops, +}; diff --git a/drivers/clk/microchip/clk_pfsoc_periph.c b/drivers/clk/microchip/clk_pfsoc_periph.c new file mode 100644 index 0000000000..c8b3b8f738 --- /dev/null +++ b/drivers/clk/microchip/clk_pfsoc_periph.c @@ -0,0 +1,173 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2020 Microchip Technology Inc. + * Padmarao Begari + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "clk_pfsoc.h" + +#define PFSOC_PERIPH_CLOCK "pfsoc_periph_clock" + +#define REG_CLOCK_CONFIG_CR 0x08 +#define REG_SUBBLK_CLOCK_CR 0x84 +#define REG_SUBBLK_RESET_CR 0x88 + +#define CFG_CPU_SHIFT 0x0 +#define CFG_AXI_SHIFT 0x2 +#define CFG_AHB_SHIFT 0x4 +#define CFG_WIDTH 0x2 + +struct pfsoc_periph_clock { + unsigned int id; + const char *name; + u8 shift; + unsigned long flags; +}; + +struct pfsoc_periph_hw_clock { + struct pfsoc_periph_clock periph; + void __iomem *sys_base; + u32 prate; + struct clk hw; +}; + +#define to_pfsoc_periph_clk(_hw) container_of(_hw, struct pfsoc_periph_hw_clock, hw) + +static int pfsoc_periph_clk_enable(struct clk *hw) +{ + struct pfsoc_periph_hw_clock *periph_hw = to_pfsoc_periph_clk(hw); + struct pfsoc_periph_clock *periph = &periph_hw->periph; + void __iomem *base_addr = periph_hw->sys_base; + u32 reg, val; + + if (periph->flags != CLK_IS_CRITICAL) { + reg = readl(base_addr + REG_SUBBLK_RESET_CR); + val = reg & ~(1u << periph->shift); + writel(val, base_addr + REG_SUBBLK_RESET_CR); + + reg = readl(base_addr + REG_SUBBLK_CLOCK_CR); + val = reg | (1u << periph->shift); + writel(val, base_addr + REG_SUBBLK_CLOCK_CR); + } + + return 0; +} + +static int pfsoc_periph_clk_disable(struct clk *hw) +{ + struct pfsoc_periph_hw_clock *periph_hw = to_pfsoc_periph_clk(hw); + struct pfsoc_periph_clock *periph = &periph_hw->periph; + void __iomem *base_addr = periph_hw->sys_base; + u32 reg, val; + + if (periph->flags != CLK_IS_CRITICAL) { + reg = readl(base_addr + REG_SUBBLK_RESET_CR); + val = reg | (1u << periph->shift); + writel(val, base_addr + REG_SUBBLK_RESET_CR); + + reg = readl(base_addr + REG_SUBBLK_CLOCK_CR); + val = reg & ~(1u << periph->shift); + writel(val, base_addr + REG_SUBBLK_CLOCK_CR); + } + + return 0; +} + +static ulong pfsoc_periph_clk_recalc_rate(struct clk *hw) +{ + struct pfsoc_periph_hw_clock *periph_hw = to_pfsoc_periph_clk(hw); + void __iomem *base_addr = periph_hw->sys_base; + unsigned long rate; + u32 val; + + val = readl(base_addr + REG_CLOCK_CONFIG_CR) >> CFG_AHB_SHIFT; + val &= clk_div_mask(CFG_WIDTH); + rate = periph_hw->prate / (1u << val); + hw->rate = rate; + + return rate; +} + +#define CLK_PERIPH(_id, _name, _shift, _flags) { \ + .periph.id = _id, \ + .periph.name = _name, \ + .periph.shift = _shift, \ + .periph.flags = _flags, \ + } + +static struct pfsoc_periph_hw_clock pfsoc_periph_clks[] = { + CLK_PERIPH(CLK_ENVM, "clk_periph_envm", 0, CLK_IS_CRITICAL), + CLK_PERIPH(CLK_MAC0, "clk_periph_mac0", 1, 0), + CLK_PERIPH(CLK_MAC1, "clk_periph_mac1", 2, 0), + CLK_PERIPH(CLK_MMC, "clk_periph_mmc", 3, 0), + CLK_PERIPH(CLK_TIMER, "clk_periph_timer", 4, 0), + CLK_PERIPH(CLK_MMUART0, "clk_periph_mmuart0", 5, 0), + CLK_PERIPH(CLK_MMUART1, "clk_periph_mmuart1", 6, 0), + CLK_PERIPH(CLK_MMUART2, "clk_periph_mmuart2", 7, 0), + CLK_PERIPH(CLK_MMUART3, "clk_periph_mmuart3", 8, 0), + CLK_PERIPH(CLK_MMUART4, "clk_periph_mmuart4", 9, 0), + CLK_PERIPH(CLK_SPI0, "clk_periph_spi0", 10, 0), + CLK_PERIPH(CLK_SPI1, "clk_periph_spi1", 11, 0), + CLK_PERIPH(CLK_I2C0, "clk_periph_i2c0", 12, 0), + CLK_PERIPH(CLK_I2C1, "clk_periph_i2c1", 13, 0), + CLK_PERIPH(CLK_CAN0, "clk_periph_can0", 14, 0), + CLK_PERIPH(CLK_CAN1, "clk_periph_can1", 15, 0), + CLK_PERIPH(CLK_USB, "clk_periph_usb", 16, 0), + CLK_PERIPH(CLK_RTC, "clk_periph_rtc", 18, 0), + CLK_PERIPH(CLK_QSPI, "clk_periph_qspi", 19, 0), + CLK_PERIPH(CLK_GPIO0, "clk_periph_gpio0", 20, 0), + CLK_PERIPH(CLK_GPIO1, "clk_periph_gpio1", 21, 0), + CLK_PERIPH(CLK_GPIO2, "clk_periph_gpio2", 22, 0), + CLK_PERIPH(CLK_DDRC, "clk_periph_ddrc", 23, CLK_IS_CRITICAL), + CLK_PERIPH(CLK_FIC0, "clk_periph_fic0", 24, 0), + CLK_PERIPH(CLK_FIC1, "clk_periph_fic1", 25, 0), + CLK_PERIPH(CLK_FIC2, "clk_periph_fic2", 26, 0), + CLK_PERIPH(CLK_FIC3, "clk_periph_fic3", 27, 0), + CLK_PERIPH(CLK_ATHENA, "clk_periph_athena", 28, 0), + CLK_PERIPH(CLK_CFM, "clk_periph_cfm", 29, 0), +}; + +int pfsoc_clk_register_periphs(void __iomem *base, u32 clk_rate, + const char *parent_name) +{ + int ret; + int i, id, num_clks; + const char *name; + struct clk *hw; + + num_clks = ARRAY_SIZE(pfsoc_periph_clks); + for (i = 0; i < num_clks; i++) { + hw = &pfsoc_periph_clks[i].hw; + pfsoc_periph_clks[i].sys_base = base; + pfsoc_periph_clks[i].prate = clk_rate; + name = pfsoc_periph_clks[i].periph.name; + ret = clk_register(hw, PFSOC_PERIPH_CLOCK, name, parent_name); + if (ret) + ERR_PTR(ret); + id = pfsoc_periph_clks[i].periph.id; + clk_dm(id, hw); + } + + return 0; +} + +const struct clk_ops pfsoc_periph_clk_ops = { + .enable = pfsoc_periph_clk_enable, + .disable = pfsoc_periph_clk_disable, + .get_rate = pfsoc_periph_clk_recalc_rate, +}; + +U_BOOT_DRIVER(pfsoc_periph_clock) = { + .name = PFSOC_PERIPH_CLOCK, + .id = UCLASS_CLK, + .ops = &pfsoc_periph_clk_ops, +}; diff --git a/include/dt-bindings/clock/microchip,pfsoc-clock.h b/include/dt-bindings/clock/microchip,pfsoc-clock.h new file mode 100644 index 0000000000..527cff1a28 --- /dev/null +++ b/include/dt-bindings/clock/microchip,pfsoc-clock.h @@ -0,0 +1,45 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2020 Microchip Technology Inc. + * Padmarao Begari + */ + +#ifndef _DT_BINDINGS_CLK_MICROCHIP_PFSOC_H_ +#define _DT_BINDINGS_CLK_MICROCHIP_PFSOC_H_ + +#define CLK_CPU 0 +#define CLK_AXI 1 +#define CLK_AHB 2 + +#define CLK_ENVM 3 +#define CLK_MAC0 4 +#define CLK_MAC1 5 +#define CLK_MMC 6 +#define CLK_TIMER 7 +#define CLK_MMUART0 8 +#define CLK_MMUART1 9 +#define CLK_MMUART2 10 +#define CLK_MMUART3 11 +#define CLK_MMUART4 12 +#define CLK_SPI0 13 +#define CLK_SPI1 14 +#define CLK_I2C0 15 +#define CLK_I2C1 16 +#define CLK_CAN0 17 +#define CLK_CAN1 18 +#define CLK_USB 19 +#define CLK_RESERVED 20 +#define CLK_RTC 21 +#define CLK_QSPI 22 +#define CLK_GPIO0 23 +#define CLK_GPIO1 24 +#define CLK_GPIO2 25 +#define CLK_DDRC 26 +#define CLK_FIC0 27 +#define CLK_FIC1 28 +#define CLK_FIC2 29 +#define CLK_FIC3 30 +#define CLK_ATHENA 31 +#define CLK_CFM 32 + +#endif /* _DT_BINDINGS_CLK_MICROCHIP_PFSOC_H_ */ From patchwork Thu Oct 22 07:07:13 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Padmarao Begari X-Patchwork-Id: 1386005 X-Patchwork-Delegate: uboot@andestech.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=quarantine dis=none) header.from=microchip.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=microchip.com header.i=@microchip.com header.a=rsa-sha256 header.s=mchp header.b=QjR7nIxU; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4CGzNg48KCz9sTc for ; Thu, 22 Oct 2020 18:23:15 +1100 (AEDT) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id E492282423; Thu, 22 Oct 2020 09:23:11 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=fail (p=quarantine dis=none) header.from=microchip.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=microchip.com header.i=@microchip.com header.b="QjR7nIxU"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id AF87482424; Thu, 22 Oct 2020 09:23:10 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.0 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,RCVD_IN_MSPIKE_H4,RCVD_IN_MSPIKE_WL, SPF_HELO_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.2 Received: from esa5.microchip.iphmx.com (esa5.microchip.iphmx.com [216.71.150.166]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 13F058240E for ; Thu, 22 Oct 2020 09:23:04 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=quarantine dis=none) header.from=microchip.com Authentication-Results: phobos.denx.de; spf=fail smtp.mailfrom=Padmarao.Begari@microchip.com DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1603351386; x=1634887386; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=K9VdI6nZhvfUrazGG5ab5VZOSk63iunsLQZAdEWYkM0=; b=QjR7nIxUtFqQ9TABFLg6DY73dRfpDDzpm/HM/7Elu43GX6jfMbjusiJD JBfy8BXXsp0X8c+Ns2rxgslQovSjSbl2CVVm5FgGbSmF45KHVqKev7+8T d2ZKkwCoUILffWzWXmxvRZZatA9rOzoEglWuZCoAOBPKm+n8IVcssM6BT u09CEUgT66RutdSrVXFghKcajWW4F1W2d/F3Fw+YIByH1uC1V7vU4qFFm qXCUVcjsUCkpB7yldlLrNZn0JyTxcrB3jrZ0bgofdPjH+khpMdiflyU+9 EpbN7s05np5btDAWTXSPeLeHv3/v3WKrkqb0hFQLUHclO7vh6cDNuaas7 Q==; IronPort-SDR: lHLIx3mv8LeK4/3Lf1TpptPvlR5XvybFxuIGqm636/2cv8Rd1rjvbmIQ92YGOiatGMe+oI31+N fe03i70c9DiLB5Dv4k6LPDN3wZc1hKO/KZb9anfpRKiC4kPxu9XEb2iUfBxg1MIQSCsqF5bjQE YHAO2E3Y/lZxPs4pN9SYK7stuqkmfFjMgXLMOoPNt7qOxFaHBUjJn0ivzqEDc+ADHe5FOHLm2z tUzT7TVapJfXu1rQDFTEKh/rKWacm0UUq26WaIrZI+eduuppC/Ts9Wos0ZinymJfMZJPKxsOme qVc= X-IronPort-AV: E=Sophos;i="5.77,404,1596524400"; d="scan'208";a="95584709" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa5.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 22 Oct 2020 00:23:04 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1979.3; Thu, 22 Oct 2020 00:22:48 -0700 Received: from padmarao-VirtualBox.microchip.com (10.10.115.15) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.1979.3 via Frontend Transport; Thu, 22 Oct 2020 00:22:43 -0700 From: Padmarao Begari To: , , , , , , CC: , , , , , Padmarao Begari Subject: [PATCH v2 5/7] riscv: dts: Add device tree for Microchip Icicle Kit Date: Thu, 22 Oct 2020 12:37:13 +0530 Message-ID: <20201022070715.14759-6-padmarao.begari@microchip.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201022070715.14759-1-padmarao.begari@microchip.com> References: <20201022070715.14759-1-padmarao.begari@microchip.com> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.3 at phobos.denx.de X-Virus-Status: Clean Add device tree for Microchip PolarFire SoC Icicle Kit. Signed-off-by: Padmarao Begari Reviewed-by: Anup Patel --- arch/riscv/dts/Makefile | 1 + arch/riscv/dts/microchip-icicle-kit-a000.dts | 426 +++++++++++++++++++ 2 files changed, 427 insertions(+) create mode 100644 arch/riscv/dts/microchip-icicle-kit-a000.dts diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile index 3a6f96c67d..48c43bd122 100644 --- a/arch/riscv/dts/Makefile +++ b/arch/riscv/dts/Makefile @@ -3,6 +3,7 @@ dtb-$(CONFIG_TARGET_AX25_AE350) += ae350_32.dtb ae350_64.dtb dtb-$(CONFIG_TARGET_SIFIVE_FU540) += hifive-unleashed-a00.dtb dtb-$(CONFIG_TARGET_SIPEED_MAIX) += k210-maix-bit.dtb +dtb-$(CONFIG_TARGET_MICROCHIP_ICICLE) += microchip-icicle-kit-a000.dtb targets += $(dtb-y) diff --git a/arch/riscv/dts/microchip-icicle-kit-a000.dts b/arch/riscv/dts/microchip-icicle-kit-a000.dts new file mode 100644 index 0000000000..7110d2a78b --- /dev/null +++ b/arch/riscv/dts/microchip-icicle-kit-a000.dts @@ -0,0 +1,426 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* Copyright (c) 2020 Microchip Technology Inc */ + +/dts-v1/; +#include "dt-bindings/clock/microchip,pfsoc-clock.h" + +/* Clock frequency (in Hz) of the rtcclk */ +#define RTCCLK_FREQ 1000000 + +/ { + #address-cells = <2>; + #size-cells = <2>; + model = "Microchip PolarFire-SoC"; + compatible = "microchip,polarfire-soc"; + + aliases { + serial0 = &uart0; + ethernet0 = &emac1; + }; + + chosen { + stdout-path = "serial0"; + }; + + cpucomplex: cpus { + #address-cells = <1>; + #size-cells = <0>; + timebase-frequency = ; + cpu0: cpu@0 { + clocks = <&clkcfg CLK_CPU>; + compatible = "sifive,e51", "sifive,rocket0", "riscv"; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <128>; + i-cache-size = <16384>; + reg = <0>; + riscv,isa = "rv64imac"; + status = "disabled"; + operating-points = < + /* kHz uV */ + 600000 1100000 + 300000 950000 + 150000 750000 + >; + cpu0intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu1: cpu@1 { + clocks = <&clkcfg CLK_CPU>; + compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; + d-cache-block-size = <64>; + d-cache-sets = <64>; + d-cache-size = <32768>; + d-tlb-sets = <1>; + d-tlb-size = <32>; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <64>; + i-cache-size = <32768>; + i-tlb-sets = <1>; + i-tlb-size = <32>; + mmu-type = "riscv,sv39"; + reg = <1>; + riscv,isa = "rv64imafdc"; + tlb-split; + status = "okay"; + operating-points = < + /* kHz uV */ + 600000 1100000 + 300000 950000 + 150000 750000 + >; + cpu1intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu2: cpu@2 { + clocks = <&clkcfg CLK_CPU>; + compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; + d-cache-block-size = <64>; + d-cache-sets = <64>; + d-cache-size = <32768>; + d-tlb-sets = <1>; + d-tlb-size = <32>; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <64>; + i-cache-size = <32768>; + i-tlb-sets = <1>; + i-tlb-size = <32>; + mmu-type = "riscv,sv39"; + reg = <2>; + riscv,isa = "rv64imafdc"; + tlb-split; + status = "okay"; + operating-points = < + /* kHz uV */ + 600000 1100000 + 300000 950000 + 150000 750000 + >; + cpu2intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu3: cpu@3 { + clocks = <&clkcfg CLK_CPU>; + compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; + d-cache-block-size = <64>; + d-cache-sets = <64>; + d-cache-size = <32768>; + d-tlb-sets = <1>; + d-tlb-size = <32>; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <64>; + i-cache-size = <32768>; + i-tlb-sets = <1>; + i-tlb-size = <32>; + mmu-type = "riscv,sv39"; + reg = <3>; + riscv,isa = "rv64imafdc"; + tlb-split; + status = "okay"; + operating-points = < + /* kHz uV */ + 600000 1100000 + 300000 950000 + 150000 750000 + >; + cpu3intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu4: cpu@4 { + clocks = <&clkcfg CLK_CPU>; + compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; + d-cache-block-size = <64>; + d-cache-sets = <64>; + d-cache-size = <32768>; + d-tlb-sets = <1>; + d-tlb-size = <32>; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <64>; + i-cache-size = <32768>; + i-tlb-sets = <1>; + i-tlb-size = <32>; + mmu-type = "riscv,sv39"; + reg = <4>; + riscv,isa = "rv64imafdc"; + tlb-split; + status = "okay"; + operating-points = < + /* kHz uV */ + 600000 1100000 + 300000 950000 + 150000 750000 + >; + cpu4intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + }; + refclk: refclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <600000000>; + clock-output-names = "msspllclk"; + }; + ddr: memory@80000000 { + device_type = "memory"; + reg = <0x0 0x80000000 0x0 0x40000000>; + clocks = <&clkcfg CLK_DDRC>; + }; + soc: soc { + #address-cells = <2>; + #size-cells = <2>; + compatible = "sifive,fu540-c000", "sifive,fu540", "simple-bus"; + ranges; + clint0: clint@2000000 { + compatible = "riscv,clint0"; + interrupts-extended = <&cpu0intc 3 &cpu0intc 7 + &cpu1intc 3 &cpu1intc 7 + &cpu2intc 3 &cpu2intc 7 + &cpu3intc 3 &cpu3intc 7 + &cpu4intc 3 &cpu4intc 7>; + reg = <0x0 0x2000000 0x0 0x10000>; + reg-names = "control"; + clock-frequency = ; + }; + cachecontroller: cache-controller@2010000 { + compatible = "sifive,fu540-c000-ccache", "cache"; + cache-block-size = <64>; + cache-level = <2>; + cache-sets = <1024>; + cache-size = <2097152>; + cache-unified; + interrupt-parent = <&plic>; + interrupts = <1 2 3>; + reg = <0x0 0x2010000 0x0 0x1000>; + }; + dma: dma@3000000 { + compatible = "sifive,fu540-c000-pdma"; + reg = <0x0 0x3000000 0x0 0x8000>; + interrupt-parent = <&plic>; + interrupts = <23 24 25 26 27 28 29 30>; + #dma-cells = <1>; + }; + plic: interrupt-controller@c000000 { + #interrupt-cells = <1>; + compatible = "sifive,plic-1.0.0"; + reg = <0x0 0xc000000 0x0 0x4000000>; + riscv,max-priority = <7>; + riscv,ndev = <186>; + interrupt-controller; + interrupts-extended = < + &cpu0intc 11 + &cpu1intc 11 &cpu1intc 9 + &cpu2intc 11 &cpu2intc 9 + &cpu3intc 11 &cpu3intc 9 + &cpu4intc 11 &cpu4intc 9>; + }; + uart0: serial@20000000 { + compatible = "ns16550a"; + reg = <0x0 0x20000000 0x0 0x400>; + reg-io-width = <4>; + reg-shift = <2>; + interrupt-parent = <&plic>; + interrupts = <90>; + clock-frequency = <150000000>; + clocks = <&clkcfg CLK_MMUART0>; + status = "okay"; + }; + clkcfg: clkcfg@20002000 { + compatible = "microchip,pfsoc-clkcfg"; + reg = <0x0 0x20002000 0x0 0x1000>; + reg-names = "mss_sysreg"; + clocks = <&refclk>; + #clock-cells = <1>; + clock-output-names = "cpu", "axi", "ahb", "envm", + "mac0", "mac1", "mmc", "timer", + "mmuart0", "mmuart1", "mmuart2", + "mmuart3", "mmuart4", "spi0", "spi1", + "i2c0", "i2c1", "can0", "can1", "usb", + "reserved", "rtc", "qspi", "gpio0", + "gpio1", "gpio2", "ddrc", "fic0", + "fic1", "fic2", "fic3", "athena", + "cfm"; + }; + emmc: mmc@20008000 { + compatible = "cdns,sd4hc"; + reg = <0x0 0x20008000 0x0 0x1000>; + interrupt-parent = <&plic>; + interrupts = <88 89>; + pinctrl-names = "default"; + clocks = <&clkcfg CLK_MMC>; + bus-width = <4>; + cap-mmc-highspeed; + mmc-ddr-3_3v; + max-frequency = <200000000>; + non-removable; + no-sd; + no-sdio; + voltage-ranges = <3300 3300>; + status = "okay"; + }; + sdcard: sd@20008000 { + compatible = "cdns,sd4hc"; + reg = <0x0 0x20008000 0x0 0x1000>; + interrupt-parent = <&plic>; + interrupts = <88>; + pinctrl-names = "default"; + clocks = <&clkcfg CLK_MMC>; + bus-width = <4>; + disable-wp; + cap-sd-highspeed; + card-detect-delay = <200>; + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-sdr104; + max-frequency = <200000000>; + status = "disabled"; + }; + uart1: serial@20100000 { + compatible = "ns16550a"; + reg = <0x0 0x20100000 0x0 0x400>; + reg-io-width = <4>; + reg-shift = <2>; + interrupt-parent = <&plic>; + interrupts = <91>; + clock-frequency = <150000000>; + clocks = <&clkcfg CLK_MMUART1>; + status = "okay"; + }; + uart2: serial@20102000 { + compatible = "ns16550a"; + reg = <0x0 0x20102000 0x0 0x400>; + reg-io-width = <4>; + reg-shift = <2>; + interrupt-parent = <&plic>; + interrupts = <92>; + clock-frequency = <150000000>; + clocks = <&clkcfg CLK_MMUART2>; + status = "okay"; + }; + uart3: serial@20104000 { + compatible = "ns16550a"; + reg = <0x0 0x20104000 0x0 0x400>; + reg-io-width = <4>; + reg-shift = <2>; + interrupt-parent = <&plic>; + interrupts = <93>; + clock-frequency = <150000000>; + clocks = <&clkcfg CLK_MMUART3>; + status = "okay"; + }; + i2c0: i2c@02010a000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "microsemi,ms-pf-mss-i2c"; + reg = <0x0 0x2010a000 0x0 0x1000>; + interrupt-parent = <&plic>; + interrupts = <58>; + clocks = <&clkcfg CLK_I2C0>; + status = "disabled"; + }; + i2c1: i2c@02010b000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "microsemi,ms-pf-mss-i2c"; + reg = <0x0 0x2010b000 0x0 0x1000>; + interrupt-parent = <&plic>; + interrupts = <61>; + clocks = <&clkcfg CLK_I2C1>; + status = "disabled"; + pac193x@0x10 { + compatible = "microchip,pac1934"; + reg = <0x10>; + samp-rate = <64>; + status = "disabled"; + ch1: channel@0 { + uohms-shunt-res = <10000>; + rail-name = "VDD"; + channel_enabled; + }; + ch2: channel@1 { + uohms-shunt-res = <10000>; + rail-name = "VDDA25"; + channel_enabled; + }; + ch3: channel@2 { + uohms-shunt-res = <10000>; + rail-name = "VDD25"; + channel_enabled; + }; + ch4: channel@3 { + uohms-shunt-res = <10000>; + rail-name = "VDDA"; + channel_enabled; + }; + }; + }; + emac0: ethernet@20110000 { + compatible = "cdns,macb"; + reg = <0x0 0x20110000 0x0 0x2000>; + interrupt-parent = <&plic>; + interrupts = <64 65 66 67>; + mac-address = [00 00 00 00 00 00]; + phy-mode = "sgmii"; + clocks = <&clkcfg CLK_MAC0>, <&clkcfg CLK_AXI>; + clock-names = "pclk", "hclk"; + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + phy0: ethernet-phy@8 { + reg = <8>; + ti,fifo-depth = <0x01>; + }; + }; + emac1: ethernet@20112000 { + compatible = "cdns,macb"; + reg = <0x0 0x20112000 0x0 0x2000>; + interrupt-parent = <&plic>; + interrupts = <70 71 72 73>; + mac-address = [00 00 00 00 00 00]; + phy-mode = "sgmii"; + clocks = <&clkcfg CLK_MAC1>, <&clkcfg CLK_AHB>; + clock-names = "pclk", "hclk"; + status = "okay"; + + #address-cells = <1>; + #size-cells = <0>; + phy1: ethernet-phy@9 { + reg = <9>; + ti,fifo-depth = <0x01>; + }; + }; + gpio: gpio@0x20122000 { + compatible = "microsemi,ms-pf-mss-gpio"; + interrupt-parent = <&plic>; + interrupts = <13 14 15 16 17 18 19 20 21 22 23 24 25 26 + 27 28 29 30 31 32 33 34 35 36 37 38 39 + 40 41 42 43 44>; + gpio-controller; + clocks = <&clkcfg CLK_GPIO2>; + reg = <0x00 0x20122000 0x0 0x1000>; + reg-names = "control"; + #gpio-cells = <2>; + status = "disabled"; + }; + }; +}; From patchwork Thu Oct 22 07:07:14 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Padmarao Begari X-Patchwork-Id: 1386006 X-Patchwork-Delegate: uboot@andestech.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=quarantine dis=none) header.from=microchip.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=microchip.com header.i=@microchip.com header.a=rsa-sha256 header.s=mchp header.b=XDUx0sG0; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4CGzPS6S5Tz9sTc for ; Thu, 22 Oct 2020 18:23:56 +1100 (AEDT) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 0BE3C82424; Thu, 22 Oct 2020 09:23:54 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=fail (p=quarantine dis=none) header.from=microchip.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=microchip.com header.i=@microchip.com header.b="XDUx0sG0"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 8480D82442; Thu, 22 Oct 2020 09:23:52 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.0 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,RCVD_IN_MSPIKE_H4,RCVD_IN_MSPIKE_WL, SPF_HELO_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.2 Received: from esa5.microchip.iphmx.com (esa5.microchip.iphmx.com [216.71.150.166]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id A95C082423 for ; Thu, 22 Oct 2020 09:23:45 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=quarantine dis=none) header.from=microchip.com Authentication-Results: phobos.denx.de; spf=fail smtp.mailfrom=Padmarao.Begari@microchip.com DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1603351426; x=1634887426; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=LogaopzTVPnor12EpPkYWaNtDipaRvEgSidHL0Y0CPg=; b=XDUx0sG0JCWYe+KqaHj58f6RwDJ6VgMhg8MBxpVWxz8dG9/Jiurm6TID I5PMJtV560C1ZqHIgD9ryZMvYH6eKIRRIILEtqfFVRJsuod63CjET6JNs O2jS3qIBHUPT5+nzGV86bH7CxyRezxoyOMNP9OhWetRQyjdA1uPGgEAb8 HlDLyt0A2JTy/EtuZHqcejhLTBkM4I19VaapRuVG9UgbVnANHwSUWNu1F AggsH4IKwqT70sT80vrQzoHqdrqJCSuUFCZDsGjkG+jAVhdw0llrByzmd gFQpEixTYhfpJmUG5YlNw4RJvFz/2EUfhLQLUVvLWeRQPa6PIySylTGzD A==; IronPort-SDR: Pqr73TdG8KtA9xyWnP4a3VDdvAQ6zeFEWBRIRW2cNJvgPIRPJnwYt7+nGfy9Dye0kCJ3tr4NvC nth/UoeRWDhkL4tZgZ2TswmeI3nB2VGoSp8LkgUTSvsH1oRqjVzWp8EurKiFWJZjVOA10hzmVI 1q+a7AGw+Bf6SainQY0DGeOqfwxPvhFA+EkyaUYObXbsfGLjU1UsGVDFTZ60Nydg2EpgWCGb3t 6/bfb2RIqRW/ynFk1ZVI9GdDDDGfZB8WBn5akh/AcN8BIfgYLTL7DM/eFDrL7cyFj2+Sw/hDaf xeI= X-IronPort-AV: E=Sophos;i="5.77,404,1596524400"; d="scan'208";a="95584770" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa5.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 22 Oct 2020 00:23:44 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1979.3; Thu, 22 Oct 2020 00:23:08 -0700 Received: from padmarao-VirtualBox.microchip.com (10.10.115.15) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.1979.3 via Frontend Transport; Thu, 22 Oct 2020 00:23:03 -0700 From: Padmarao Begari To: , , , , , , CC: , , , , , Padmarao Begari Subject: [PATCH v2 6/7] riscv: Add Microchip MPFS Icicle Kit support Date: Thu, 22 Oct 2020 12:37:14 +0530 Message-ID: <20201022070715.14759-7-padmarao.begari@microchip.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201022070715.14759-1-padmarao.begari@microchip.com> References: <20201022070715.14759-1-padmarao.begari@microchip.com> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.3 at phobos.denx.de X-Virus-Status: Clean This patch adds Microchip MPFS Icicle Kit support. For now, only NS16550 Serial, Microchip clock, Cadence eMMC and MACB drivers are only enabled. The Microchip MPFS Icicle defconfig by default builds U-Boot for S-Mode because U-Boot on Microchip PolarFire SoC will run in S-Mode as payload of HSS + OpenSBI. Signed-off-by: Padmarao Begari Reviewed-by: Anup Patel --- board/microchip/mpfs_icicle/Kconfig | 25 ++++++ board/microchip/mpfs_icicle/mpfs_icicle.c | 96 ++++++++++++++++++++++- configs/microchip_mpfs_icicle_defconfig | 9 ++- include/configs/microchip_mpfs_icicle.h | 60 +++++--------- 4 files changed, 145 insertions(+), 45 deletions(-) diff --git a/board/microchip/mpfs_icicle/Kconfig b/board/microchip/mpfs_icicle/Kconfig index bf8e1a13ec..2f34c343f1 100644 --- a/board/microchip/mpfs_icicle/Kconfig +++ b/board/microchip/mpfs_icicle/Kconfig @@ -20,7 +20,32 @@ config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select GENERIC_RISCV select BOARD_EARLY_INIT_F + select BOARD_LATE_INIT imply SMP + imply CLK_CCF + imply CLK_MPFS imply SYS_NS16550 + imply CMD_DHCP + imply CMD_EXT2 + imply CMD_EXT4 + imply CMD_FAT + imply CMD_FS_GENERIC + imply CMD_NET + imply CMD_PING + imply CMD_MMC + imply DOS_PARTITION + imply EFI_PARTITION + imply IP_DYN + imply ISO_PARTITION + imply MACB + imply MII + imply NET_RANDOM_ETHADDR + imply PHY_LIB + imply PHY_VITESSE + imply DMA_ADDR_T_64BIT + imply MMC + imply MMC_WRITE + imply MMC_SDHCI + imply MMC_SDHCI_CADENCE endif diff --git a/board/microchip/mpfs_icicle/mpfs_icicle.c b/board/microchip/mpfs_icicle/mpfs_icicle.c index 8381361ec3..02f79541da 100644 --- a/board/microchip/mpfs_icicle/mpfs_icicle.c +++ b/board/microchip/mpfs_icicle/mpfs_icicle.c @@ -6,10 +6,46 @@ #include #include +#include #include #include -#define MPFS_SYSREG_SOFT_RESET ((unsigned int *)0x20002088) +#define MPFS_SYSREG_SOFT_RESET ((unsigned int *)0x20002088) +#define MPFS_SYS_SERVICE_CR ((unsigned int *)0x37020050) +#define MPFS_SYS_SERVICE_SR ((unsigned int *)0x37020054) +#define MPFS_SYS_SERVICE_MAILBOX ((unsigned char *)0x37020800) + +#define PERIPH_RESET_VALUE 0x1e8u +#define SERVICE_CR_REQ 0x1u +#define SERVICE_SR_BUSY 0x2u + +static void read_device_serial_number(u8 *response, u8 response_size) +{ + u8 idx; + u8 *response_buf; + unsigned int val; + + response_buf = (u8 *)response; + + writel(SERVICE_CR_REQ, MPFS_SYS_SERVICE_CR); + + /* REQ bit will remain set till the system controller starts + * processing. + */ + do { + val = readl(MPFS_SYS_SERVICE_CR); + } while (SERVICE_CR_REQ == (val & SERVICE_CR_REQ)); + + /* Once system controller starts processing the busy bit will + * go high and service is completed when busy bit is gone low + */ + do { + val = readl(MPFS_SYS_SERVICE_SR); + } while (SERVICE_SR_BUSY == (val & SERVICE_SR_BUSY)); + + for (idx = 0; idx < response_size; idx++) + response_buf[idx] = readb(MPFS_SYS_SERVICE_MAILBOX + idx); +} int board_init(void) { @@ -22,10 +58,64 @@ int board_early_init_f(void) { unsigned int val; - /* Reset uart peripheral */ + /* Reset uart, mmc peripheral */ val = readl(MPFS_SYSREG_SOFT_RESET); - val = (val & ~(1u << 5u)); + val = (val & ~(PERIPH_RESET_VALUE)); writel(val, MPFS_SYSREG_SOFT_RESET); return 0; } + +int board_late_init(void) +{ + u32 ret; + u32 node; + u8 idx; + u8 device_serial_number[16] = { 0 }; + unsigned char mac_addr[6]; + char icicle_mac_addr[20]; + void *blob = (void *)gd->fdt_blob; + + node = fdt_path_offset(blob, "ethernet0"); + if (node < 0) { + printf("No ethernet0 path offset\n"); + return -ENODEV; + } + + ret = fdtdec_get_byte_array(blob, node, "mac-address", mac_addr, 6); + if (ret) { + printf("No mac-address property\n"); + return -EINVAL; + } + + read_device_serial_number(device_serial_number, 16); + + /* Update MAC address with device serial number */ + mac_addr[0] = 0x00; + mac_addr[1] = 0x04; + mac_addr[2] = 0xA3; + mac_addr[3] = device_serial_number[2]; + mac_addr[4] = device_serial_number[1]; + mac_addr[5] = device_serial_number[0]; + + ret = fdt_setprop(blob, node, "mac-address", mac_addr, 6); + if (ret) { + printf("Error setting mac-address property\n"); + return -ENODEV; + } + + icicle_mac_addr[0] = '['; + + sprintf(&icicle_mac_addr[1], "%pM", mac_addr); + + icicle_mac_addr[18] = ']'; + icicle_mac_addr[19] = '\0'; + + for (idx = 0; idx < 20; idx++) { + if (icicle_mac_addr[idx] == ':') + icicle_mac_addr[idx] = ' '; + } + env_set("icicle_mac_addr", icicle_mac_addr); + + return 0; +} diff --git a/configs/microchip_mpfs_icicle_defconfig b/configs/microchip_mpfs_icicle_defconfig index 2977966473..c789546f70 100644 --- a/configs/microchip_mpfs_icicle_defconfig +++ b/configs/microchip_mpfs_icicle_defconfig @@ -1,12 +1,15 @@ CONFIG_RISCV=y CONFIG_ENV_SIZE=0x2000 CONFIG_TARGET_MICROCHIP_ICICLE=y -CONFIG_NR_CPUS=5 CONFIG_ARCH_RV64I=y +CONFIG_RISCV_SMODE=y +CONFIG_SBI_V01=y +CONFIG_DEFAULT_DEVICE_TREE="microchip-icicle-kit-a000" +CONFIG_DISTRO_DEFAULTS=y +CONFIG_DISPLAY_CPUINFO=y +CONFIG_DISPLAY_BOARDINFO=y CONFIG_FIT=y -CONFIG_BOOTDELAY=3 CONFIG_SYS_PROMPT="RISC-V # " -CONFIG_OF_PRIOR_STAGE=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_BOOTP_SEND_HOSTNAME=y CONFIG_DM_MTD=y diff --git a/include/configs/microchip_mpfs_icicle.h b/include/configs/microchip_mpfs_icicle.h index 8a7470545b..97547057b9 100644 --- a/include/configs/microchip_mpfs_icicle.h +++ b/include/configs/microchip_mpfs_icicle.h @@ -7,53 +7,35 @@ #ifndef __CONFIG_H #define __CONFIG_H -/* - * CPU and Board Configuration Options - */ +#include -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ +#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_2M) -/* - * Print Buffer Size - */ -#define CONFIG_SYS_PBSIZE \ - (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_2M) -/* - * max number of command args - */ -#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_MALLOC_LEN SZ_8M -/* - * Boot Argument Buffer Size - */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - -/* - * Size of malloc() pool - * 512kB is suggested, (CONFIG_ENV_SIZE + 128 * 1024) was not enough - */ -#define CONFIG_SYS_MALLOC_LEN (512 << 10) +#define CONFIG_SYS_BOOTM_LEN SZ_64M -/* - * Physical Memory Map - */ -#define PHYS_SDRAM_0 0x80000000 /* SDRAM Bank #1 */ -#define PHYS_SDRAM_0_SIZE 0x40000000 /* 1 GB */ -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_0 +#define CONFIG_STANDALONE_LOAD_ADDR 0x80200000 -/* Init Stack Pointer */ -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x200000) +/* Environment options */ -#define CONFIG_SYS_LOAD_ADDR 0x80000000 /* SDRAM */ +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 0) \ + func(DHCP, dhcp, na) -/* - * memtest works on DRAM - */ +#include -/* When we use RAM as ENV */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "fdt_high=0xffffffffffffffff\0" \ + "initrd_high=0xffffffffffffffff\0" \ + "kernel_addr_r=0x84000000\0" \ + "fdt_addr_r=0x88000000\0" \ + "scriptaddr=0x88100000\0" \ + "pxefile_addr_r=0x88200000\0" \ + "ramdisk_addr_r=0x88300000\0" \ + BOOTENV #endif /* __CONFIG_H */ From patchwork Thu Oct 22 07:07:15 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Padmarao Begari X-Patchwork-Id: 1386029 X-Patchwork-Delegate: uboot@andestech.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=quarantine dis=none) header.from=microchip.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=microchip.com header.i=@microchip.com header.a=rsa-sha256 header.s=mchp header.b=BR611I4T; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4CH02m5nl8z9sVW for ; Thu, 22 Oct 2020 18:52:48 +1100 (AEDT) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id ABB458240E; Thu, 22 Oct 2020 09:52:43 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=fail (p=quarantine dis=none) header.from=microchip.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=microchip.com header.i=@microchip.com header.b="BR611I4T"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 37AAB82423; Thu, 22 Oct 2020 09:52:42 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.0 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,RCVD_IN_MSPIKE_H3,RCVD_IN_MSPIKE_WL, SPF_HELO_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.2 Received: from esa2.microchip.iphmx.com (esa2.microchip.iphmx.com [68.232.149.84]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 18474823F3 for ; Thu, 22 Oct 2020 09:52:30 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=quarantine dis=none) header.from=microchip.com Authentication-Results: phobos.denx.de; spf=fail smtp.mailfrom=Padmarao.Begari@microchip.com DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1603353151; x=1634889151; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=UJ2Oae4JDEGzoK9E4wdi+tq0VPdsSIJIa1iKyGM1Eig=; b=BR611I4TCfCB4ZYR66g1qgMwGJdyOGuANhvxU4V+Ie1+NOX2J+wVT6G/ yCLRqmzxQMObKpxTMOe/azQ1EJoXMiYTrxnpCeI4FOcy9B+IhQ1neOuLy SGKnaAxh1qwiCuFsfimNtkgmXaSG242z4sehUrG8MCCZN1Mt236ty+3ef 6TrM9SULcXXayOQyaqNclvXMGpVrolnFCgEg//Z+IGpbCDBtZdJwHDbwe CmJtOYSNPlfmJpeuVtHzOq2hba21OOEgdwL6+QASK8AFKoY9KKO0R1VGT R6z4mIx/ytJ/BwLzQ5YpAmSQf3I3bioEQNxJWDiRGwZWjwypG0Jyw46EA Q==; IronPort-SDR: Q5pFcorejV8aboIxwiA4rNbc5hPMLg4zdCLcs++WWJiOFIq8uIRiaCWpEvMBBoIapD8RfKiGgt 4HaIAgV0c1S8NYVRbSO3PDQauryoLcrs28Anpgzllu2TOT2bi0np+FpIcvDoR4NzFNZ7QD+Oj6 E3y7ywSPOEMMpQRjNi3Nfg+JrigsQqc30AwqVZO27UFrIEzjrOnUbfL1D++/6HkjX7pH3dFyRm ZvJKt0JCG9E9V0R4GYrWn1nNrv6X6+Xgk6o+brl7i3t4JRAvSulqGgAJAP/N3vWbpnIkVPPzSl 6PY= X-IronPort-AV: E=Sophos;i="5.77,404,1596524400"; d="scan'208";a="93492815" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa2.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 22 Oct 2020 00:52:28 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1979.3; Thu, 22 Oct 2020 00:23:29 -0700 Received: from padmarao-VirtualBox.microchip.com (10.10.115.15) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.1979.3 via Frontend Transport; Thu, 22 Oct 2020 00:23:23 -0700 From: Padmarao Begari To: , , , , , , CC: , , , , , Padmarao Begari Subject: [PATCH v2 7/7] doc: board: Add Microchip MPFS Icicle Kit doc Date: Thu, 22 Oct 2020 12:37:15 +0530 Message-ID: <20201022070715.14759-8-padmarao.begari@microchip.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201022070715.14759-1-padmarao.begari@microchip.com> References: <20201022070715.14759-1-padmarao.begari@microchip.com> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.3 at phobos.denx.de X-Virus-Status: Clean This doc describes the procedure to build, flash and boot Linux using U-boot on Microchip MPFS Icicle Kit. Signed-off-by: Padmarao Begari --- doc/board/index.rst | 1 + doc/board/microchip/index.rst | 9 + doc/board/microchip/mpfs_icicle.rst | 605 ++++++++++++++++++++++++++++ 3 files changed, 615 insertions(+) create mode 100644 doc/board/microchip/index.rst create mode 100644 doc/board/microchip/mpfs_icicle.rst diff --git a/doc/board/index.rst b/doc/board/index.rst index 63935abcd7..e50a78d752 100644 --- a/doc/board/index.rst +++ b/doc/board/index.rst @@ -15,6 +15,7 @@ Board-specific doc freescale/index google/index intel/index + microchip/index renesas/index rockchip/index sifive/index diff --git a/doc/board/microchip/index.rst b/doc/board/microchip/index.rst new file mode 100644 index 0000000000..b09e6788af --- /dev/null +++ b/doc/board/microchip/index.rst @@ -0,0 +1,9 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +Microchip +====== + +.. toctree:: + :maxdepth: 2 + + mpfs_icicle diff --git a/doc/board/microchip/mpfs_icicle.rst b/doc/board/microchip/mpfs_icicle.rst new file mode 100644 index 0000000000..a4876b02f7 --- /dev/null +++ b/doc/board/microchip/mpfs_icicle.rst @@ -0,0 +1,605 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +Microchip PolarFire SoC Icicle Kit +================================== + +RISC-V PolarFire SoC +--------------------- +The PolarFire SoC is the 4+1 64-bit RISC-V SoC from Microchip. + +The Icicle Kit development platform is based on PolarFire SoC and capable +of running Linux. + +Mainline support +---------------- +The support for following drivers are already enabled: + +1. NS16550 UART Driver. +2. Microchip Clock Driver. +3. Cadence MACB ethernet driver for networking support. +4. Cadence MMC Driver for eMMC/SD support. + +Booting from eMMC using HSS +--------------------------- + +Building +-------- + +1. Add the RISC-V toolchain to your PATH. +2. Setup ARCH & cross compilation environment variable: + +.. code-block:: none + + export CROSS_COMPILE= + +3. make microchip_mpfs_icicle_defconfig +4. make + +Flashing +-------- + +The current U-Boot port is supported in S-mode only and loaded from DRAM. + +A prior stage M-mode firmware/bootloader (e.g HSS with OpenSBI) is required to +boot the u-boot.bin in S-mode. + +Currently, the u-boot.bin is used as a payload of the HSS firmware. + +You will be creating a payload from `u-boot-dtb.bin`. +Copy this file to the toplevel HSS (Hart Software Services) directory. + +Creating the HSS payload +------------------------ + +Please refer to HSS documenation to build the HSS firmware. +(Note: HSS git repo is at +https://github.com/polarfire-soc/hart-software-services/blob/master +/tools/hss-payload-generator/README.md) + +Once the payload binary is generated, it should be copied to the eMMC. + +FPGA design with HSS programming file +------------------------------------- +https://github.com/polarfire-soc/polarfire-soc-documentation/blob/master/boards +/mpfs-icicle-kit-es/updating-icicle-kit/updating-icicle-kit-design-and-linux.md + +The HSS firmware runs from the PolarFire SoC eNVM on reset. + +eMMC +---- +Program eMMC with payload binary is explained in the PolarFire SoC documentation. + +(Note: PolarFire SoC Documentation git repo is at +https://github.com/polarfire-soc/polarfire-soc-documentation/blob/master/boards +/mpfs-icicle-kit-es/updating-icicle-kit/updating-icicle-kit-design-and-linux.md#eMMC + +Once the payload image is copied to the eMMC, press CTRL+C in the HSS command +line interface, then type 'boot' and enter to boot the newly copied image. + +.. code-block:: none + + sudo dd if= of=/dev/sdX bs=512 + +Booting +------- +you should see the U-Boot prompt on UART0. + +Sample boot log from MPFS Icicle Kit +------------------------------------------- + +.. code-block:: none + + U-Boot 2020.10-00822-gb561436cc0-dirty (Oct 22 2020 - 11:21:24 +0530) + + CPU: rv64imafdc + Model: Microchip PolarFire-SoC + DRAM: 1 GiB + MMC: sdhc@20008000: 0 + In: serial@20100000 + Out: serial@20100000 + Err: serial@20100000 + Net: eth0: ethernet@20112000 + Hit any key to stop autoboot: 0 + +Now you can configure your networking, tftp server and use tftp boot method to +load uImage(with initramfs). + +.. code-block:: none + + RISC-V # setenv kernel_addr_r 0x80200000 + RISC-V # setenv fdt_addr_r 0x82200000 + + RISC-V # setenv ipaddr 192.168.1.5 + RISC-V # setenv netmask 255.255.255.0 + RISC-V # setenv serverip 192.168.1.3 + RISC-V # setenv gateway 192.168.1.1 + + RISC-V # tftpboot ${kernel_addr_r} uImage + ethernet@20112000: PHY present at 9 + ethernet@20112000: Starting autonegotiation... + ethernet@20112000: Autonegotiation complete + ethernet@20112000: link up, 1000Mbps full-duplex (lpa: 0x7800) + Using ethernet@20112000 device + TFTP from server 192.168.1.3; our IP address is 192.168.1.5 + Filename 'uImage'. + Load address: 0x80200000 + Loading: ################################################################# + ################################################################# + ################################################################# + ################################################################# + ################################################################# + ################################################################# + ################################################################# + ################################################################# + ################################################################# + ################################################################# + ################################################################# + ################################################################# + ################################################################# + ################################################################# + ################################################################# + ############ + 6.4 MiB/s + done + Bytes transferred = 14482480 (dcfc30 hex) + + RISC-V # tftpboot ${fdt_addr_r} microchip-icicle-kit.dtb + ethernet@20112000: PHY present at 9 + ethernet@20112000: Starting autonegotiation... + ethernet@20112000: Autonegotiation complete + ethernet@20112000: link up, 1000Mbps full-duplex (lpa: 0x7800) + Using ethernet@20112000 device + TFTP from server 192.168.1.3; our IP address is 192.168.1.5 + Filename 'riscvpc.dtb'. + Load address: 0x82200000 + Loading: # + 2.5 MiB/s + done + Bytes transferred = 10282 (282a hex) + + RISC-V # bootm ${kernel_addr_r} - ${fdt_addr_r} + ## Booting kernel from Legacy Image at 80200000 ... + Image Name: Linux + Image Type: RISC-V Linux Kernel Image (uncompressed) + Data Size: 14482416 Bytes = 13.8 MiB + Load Address: 80200000 + Entry Point: 80200000 + Verifying Checksum ... OK + ## Flattened Device Tree blob at 82200000 + Booting using the fdt blob at 0x82200000 + Loading Kernel Image + Using Device Tree in place at 0000000082200000, end 0000000082205829 + + Starting kernel ... + + [ 0.000000] OF: fdt: Ignoring memory range 0x80000000 - 0x80200000 + [ 0.000000] Linux version 5.6.17 (padmarao@padmarao-VirtualBox) (gcc version 7.2.0 (GCC)) #2 SMP Tue Jun 16 21:27:50 IST 2020 + [ 0.000000] initrd not found or empty - disabling initrd + [ 0.000000] Zone ranges: + [ 0.000000] DMA32 [mem 0x0000000080200000-0x00000000bfffffff] + [ 0.000000] Normal empty + [ 0.000000] Movable zone start for each node + [ 0.000000] Early memory node ranges + [ 0.000000] node 0: [mem 0x0000000080200000-0x00000000bfffffff] + [ 0.000000] Initmem setup node 0 [mem 0x0000000080200000-0x00000000bfffffff] + [ 0.000000] software IO TLB: mapped [mem 0xbb1f5000-0xbf1f5000] (64MB) + [ 0.000000] elf_hwcap is 0x112d + [ 0.000000] percpu: Embedded 14 pages/cpu s24856 r0 d32488 u57344 + [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 258055 + [ 0.000000] Kernel command line: console=ttyS0,115200n8 + [ 0.000000] Dentry cache hash table entries: 131072 (order: 8, 1048576 bytes, linear) + [ 0.000000] Inode-cache hash table entries: 65536 (order: 7, 524288 bytes, linear) + [ 0.000000] Sorting __ex_table... + [ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off + [ 0.000000] Memory: 950308K/1046528K available (3289K kernel code, 212K rwdata, 900K rodata, 9476K init, 250K bss, 96220K reserved, 0K cma-reserved) + [ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=4, Nodes=1 + [ 0.000000] rcu: Hierarchical RCU implementation. + [ 0.000000] rcu: RCU event tracing is enabled. + [ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=8 to nr_cpu_ids=4. + [ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 10 jiffies. + [ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=4 + [ 0.000000] NR_IRQS: 0, nr_irqs: 0, preallocated irqs: 0 + [ 0.000000] plic: mapped 186 interrupts with 4 handlers for 9 contexts. + [ 0.000000] riscv_timer_init_dt: Registering clocksource cpuid [0] hartid [1] + [ 0.000000] clocksource: riscv_clocksource: mask: 0xffffffffffffffff max_cycles: 0x1d854df40, max_idle_ns: 3526361616960 ns + [ 0.000015] sched_clock: 64 bits at 1000kHz, resolution 1000ns, wraps every 2199023255500ns + [ 0.000311] Calibrating delay loop (skipped), value calculated using timer frequency.. 2.00 BogoMIPS (lpj=10000) + [ 0.000349] pid_max: default: 32768 minimum: 301 + [ 0.000846] Mount-cache hash table entries: 2048 (order: 2, 16384 bytes, linear) + [ 0.000964] Mountpoint-cache hash table entries: 2048 (order: 2, 16384 bytes, linear) + [ 0.005630] rcu: Hierarchical SRCU implementation. + [ 0.006901] smp: Bringing up secondary CPUs ... + [ 0.012545] smp: Brought up 1 node, 4 CPUs + [ 0.014431] devtmpfs: initialized + [ 0.020526] random: get_random_bytes called from setup_net+0x36/0x192 with crng_init=0 + [ 0.020928] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns + [ 0.020999] futex hash table entries: 1024 (order: 4, 65536 bytes, linear) + [ 0.022768] NET: Registered protocol family 16 + [ 0.035478] microchip-pfsoc-clkcfg 20002000.clkcfg: Registered PFSOC core clocks + [ 0.048429] SCSI subsystem initialized + [ 0.049694] pps_core: LinuxPPS API ver. 1 registered + [ 0.049719] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti + [ 0.049780] PTP clock support registered + [ 0.051781] clocksource: Switched to clocksource riscv_clocksource + [ 0.055326] NET: Registered protocol family 2 + [ 0.056922] tcp_listen_portaddr_hash hash table entries: 512 (order: 1, 8192 bytes, linear) + [ 0.057053] TCP established hash table entries: 8192 (order: 4, 65536 bytes, linear) + [ 0.057648] TCP bind hash table entries: 8192 (order: 5, 131072 bytes, linear) + [ 0.058579] TCP: Hash tables configured (established 8192 bind 8192) + [ 0.059648] UDP hash table entries: 512 (order: 2, 16384 bytes, linear) + [ 0.059837] UDP-Lite hash table entries: 512 (order: 2, 16384 bytes, linear) + [ 0.060707] NET: Registered protocol family 1 + [ 0.266229] workingset: timestamp_bits=62 max_order=18 bucket_order=0 + [ 0.287107] io scheduler mq-deadline registered + [ 0.287140] io scheduler kyber registered + [ 0.429601] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled + [ 0.433979] printk: console [ttyS0] disabled + [ 0.434154] 20000000.serial: ttyS0 at MMIO 0x20000000 (irq = 18, base_baud = 9375000) is a 16550A + [ 0.928039] printk: console [ttyS0] enabled + [ 0.939804] libphy: Fixed MDIO Bus: probed + [ 0.948702] libphy: MACB_mii_bus: probed + [ 0.993698] macb 20112000.ethernet eth0: Cadence GEM rev 0x0107010c at 0x20112000 irq 21 (56:34:12:00:fc:00) + [ 1.006751] mousedev: PS/2 mouse device common for all mice + [ 1.013803] i2c /dev entries driver + [ 1.019451] sdhci: Secure Digital Host Controller Interface driver + [ 1.027242] sdhci: Copyright(c) Pierre Ossman + [ 1.032731] sdhci-pltfm: SDHCI platform and OF driver helper + [ 1.091826] mmc0: SDHCI controller on 20008000.sdhc [20008000.sdhc] using ADMA 64-bit + [ 1.102738] NET: Registered protocol family 17 + [ 1.170326] Freeing unused kernel memory: 9476K + [ 1.176067] This architecture does not have kernel memory protection. + [ 1.184157] Run /init as init process + Starting logging: OK + Starting mdev... + /etc/init.d/S10mdev: line 21: can't create /proc/sys/kernel/hotplug: nonexiste[ 1.331981] mmc0: mmc_select_hs200 failed, error -74 + nt directory + [ 1.355011] mmc0: new MMC card at address 0001 + [ 1.363981] mmcblk0: mmc0:0001 DG4008 7.28 GiB + [ 1.372248] mmcblk0boot0: mmc0:0001 DG4008 partition 1 4.00 MiB + [ 1.382292] mmcblk0boot1: mmc0:0001 DG4008 partition 2 4.00 MiB + [ 1.390265] mmcblk0rpmb: mmc0:0001 DG4008 partition 3 4.00 MiB, chardev (251:0) + [ 1.425234] GPT:Primary header thinks Alt. header is not at the end of the disk. + [ 1.434656] GPT:2255809 != 15273599 + [ 1.439038] GPT:Alternate GPT header not at the end of the disk. + [ 1.446671] GPT:2255809 != 15273599 + [ 1.451048] GPT: Use GNU Parted to correct GPT errors. + [ 1.457755] mmcblk0: p1 p2 p3 + sort: /sys/devices/platform/Fixed: No such file or directory + modprobe: can't change directory to '/lib/modules': No such file or directory + Initializing random number generator... [ 2.830198] random: dd: uninitialized urandom read (512 bytes read) + done. + Starting network... + [ 3.061867] macb 20112000.ethernet eth0: PHY [20112000.ethernet-ffffffff:09] driver [Vitesse VSC8662] (irq=POLL) + [ 3.074674] macb 20112000.ethernet eth0: configuring for phy/sgmii link mode + [ 3.084263] pps pps0: new PPS source ptp0 + [ 3.089710] macb 20112000.ethernet: gem-ptp-timer ptp clock registered. + udhcpc (v1.24.2) started + Sending discover... + Sending discover... + [ 6.380169] macb 20112000.ethernet eth0: Link is Up - 1Gbps/Full - flow control tx + Sending discover... + Sending select for 192.168.1.2... + Lease of 192.168.1.2 obtained, lease time 86400 + deleting routers + adding dns 192.168.1.1 + Starting dropbear sshd: [ 11.385619] random: dropbear: uninitialized urandom read (32 bytes read) + OK + + Welcome to Buildroot + buildroot login: root + Password: + # + +Booting U-Boot and Linux from eMMC +---------------------------------- + +FPGA design with HSS programming file and Linux Image +----------------------------------------------------- +https://github.com/polarfire-soc/polarfire-soc-documentation/blob/master/boards +/mpfs-icicle-kit-es/updating-icicle-kit/updating-icicle-kit-design-and-linux.md + +The HSS firmware runs from the PolarFire SoC eNVM on reset. + +eMMC +---- +Program eMMC with payload binary and Linux image is explained in the +PolarFire SoC documentation. +The payload binary should copied to partition 2 of the eMMC. + +(Note: PolarFire SoC Documentation git repo is at +https://github.com/polarfire-soc/polarfire-soc-documentation/blob/master/boards +/mpfs-icicle-kit-es/updating-icicle-kit/updating-icicle-kit-design-and-linux.md#eMMC) + +once the Linux image and payload binary is copied to the eMMC, press CTRL+C +in the HSS command line interface, then type 'boot' and enter to boot the newly +copied payload and Linux image. + +.. code-block:: none + + zcat .wic.gz | sudo dd of=/dev/sdX bs=4096 iflag=fullblock oflag=direct conv=fsync status=progress + + sudo dd if= of=/dev/sdX2 bs=512 + +You should see the U-Boot prompt on UART0. + +Sample boot log from MPFS Icicle Kit +------------------------------------------- + +.. code-block:: none + + U-Boot 2020.10-00822-gb561436cc0-dirty (Oct 22 2020 - 11:21:24 +0530) + + CPU: rv64imafdc + Model: Microchip PolarFire-SoC + DRAM: 1 GiB + MMC: sdhc@20008000: 0 + In: serial@20100000 + Out: serial@20100000 + Err: serial@20100000 + Net: eth0: ethernet@20112000 + Hit any key to stop autoboot: 0 + + RISC-V # mmc info + Device: sdhc@20008000 + Manufacturer ID: 45 + OEM: 100 + Name: DG400 + Bus Speed: 52000000 + Mode: MMC High Speed (52MHz) + Rd Block Len: 512 + MMC version 5.1 + High Capacity: Yes + Capacity: 7.3 GiB + Bus Width: 4-bit + Erase Group Size: 512 KiB + HC WP Group Size: 8 MiB + User Capacity: 7.3 GiB WRREL + Boot Capacity: 4 MiB ENH + RPMB Capacity: 4 MiB ENH + + RISC-V # mmc part + Partition Map for MMC device 0 -- Partition Type: EFI + + Part Start LBA End LBA Name + Attributes + Type GUID + Partition GUID + 1 0x00002000 0x0000b031 "boot" + attrs: 0x0000000000000004 + type: ebd0a0a2-b9e5-4433-87c0-68b6b72699c7 + guid: 99ff6a94-f2e7-44dd-a7df-f3a2da106ef9 + 2 0x0000b032 0x0000f031 "primary" + attrs: 0x0000000000000000 + type: 21686148-6449-6e6f-744e-656564454649 + guid: 12006052-e64b-4423-beb0-b956ea00f1ba + 3 0x00010000 0x00226b9f "root" + attrs: 0x0000000000000000 + type: 0fc63daf-8483-4772-8e79-3d69d8477de4 + guid: dd2c5619-2272-4c3c-8dc2-e21942e17ce6 + + RISC-V # fatload mmc 0 ${ramdisk_addr_r} fitimage + RISC-V # bootm ${ramdisk_addr_r} + ## Loading kernel from FIT Image at 88300000 ... + Using 'conf@microchip_icicle-kit-es-a000-microchip.dtb' configuration + Trying 'kernel@1' kernel subimage + Description: Linux kernel + Type: Kernel Image + Compression: gzip compressed + Data Start: 0x883000fc + Data Size: 3574555 Bytes = 3.4 MiB + Architecture: RISC-V + OS: Linux + Load Address: 0x80200000 + Entry Point: 0x80200000 + Hash algo: sha256 + Hash value: 21f18d72cf2f0a7192220abb577ad25c77c26960052d779aa02bf55dbf0a6403 + Verifying Hash Integrity ... sha256+ OK + ## Loading fdt from FIT Image at 88300000 ... + Using 'conf@microchip_icicle-kit-es-a000-microchip.dtb' configuration + Trying 'fdt@microchip_icicle-kit-es-a000-microchip.dtb' fdt subimage + Description: Flattened Device Tree blob + Type: Flat Device Tree + Compression: uncompressed + Data Start: 0x88668d44 + Data Size: 9760 Bytes = 9.5 KiB + Architecture: RISC-V + Load Address: 0x82200000 + Hash algo: sha256 + Hash value: 5c3a9f30d41b6b8e53b47916e1f339b3a4d454006554d1f7e1f552ed62409f4b + Verifying Hash Integrity ... sha256+ OK + Loading fdt from 0x88668d44 to 0x82200000 + Booting using the fdt blob at 0x82200000 + Uncompressing Kernel Image + Using Device Tree in place at 0000000082200000, end 000000008220561f + + Starting kernel ... + + [ 0.568114] printk: console [ttyS0] enabled + [ 0.578504] printk: bootconsole [sbi0] disabled + [ 0.592089] 20102000.serial: ttyS1 at MMIO 0x20102000 (irq = 13, base_baud = 9375000) is a 16550A + [ 0.605351] 20104000.serial: ttyS2 at MMIO 0x20104000 (irq = 14, base_baud = 9375000) is a 16550A + [ 0.643484] loop: module loaded + [ 0.697876] Rounding down aligned max_sectors from 4294967295 to 4294967288 + [ 0.707427] db_root: cannot open: /etc/target + [ 0.714543] libphy: Fixed MDIO Bus: probed + [ 0.722533] libphy: MACB_mii_bus: probed + [ 0.731024] macb 20112000.ethernet eth0: Cadence GEM rev 0x0107010c at 0x20112000 irq 17 (56:34:12:00:fc:00) + [ 0.744081] ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver + [ 0.752318] ehci-platform: EHCI generic platform driver + [ 0.759092] ohci_hcd: USB 1.1 'Open' Host Controller (OHCI) Driver + [ 0.766849] ohci-platform: OHCI generic platform driver + [ 0.774100] usbcore: registered new interface driver cdc_acm + [ 0.781164] cdc_acm: USB Abstract Control Model driver for USB modems and ISDN adapters + [ 0.791986] i2c /dev entries driver + [ 0.798057] microsemi-mss-i2c 2010b000.i2c: Microsemi I2C Probe Complete + [ 0.807319] sdhci: Secure Digital Host Controller Interface driver + [ 0.815094] sdhci: Copyright(c) Pierre Ossman + [ 0.820527] sdhci-pltfm: SDHCI platform and OF driver helper + [ 0.860631] mmc0: SDHCI controller on 20008000.sdhc [20008000.sdhc] using ADMA 64-bit + [ 0.871064] usbcore: registered new interface driver usbhid + [ 0.878085] usbhid: USB HID core driver + [ 0.980158] mmc0: mmc_select_hs200 failed, error -74 + [ 0.989240] mmc0: new MMC card at address 0001 + [ 0.997930] mmcblk0: mmc0:0001 DG4008 7.28 GiB + [ 1.005847] mmcblk0boot0: mmc0:0001 DG4008 partition 1 4.00 MiB + [ 1.015369] mmcblk0boot1: mmc0:0001 DG4008 partition 2 4.00 MiB + [ 1.023364] mmcblk0rpmb: mmc0:0001 DG4008 partition 3 4.00 MiB, chardev (247:0) + [ 1.051870] GPT:Primary header thinks Alt. header is not at the end of the disk. + [ 1.061102] GPT:2255809 != 15273599 + [ 1.065561] GPT:Alternate GPT header not at the end of the disk. + [ 1.073088] GPT:2255809 != 15273599 + [ 1.077439] GPT: Use GNU Parted to correct GPT errors. + [ 1.084003] mmcblk0: p1 p2 p3 + [ 1.891482] pac193x 0-0010: failed reading data from register 0xFD + [ 1.899195] pac193x 0-0010: cannot read PAC193x revision + [ 1.905955] pac193x: probe of 0-0010 failed with error -22 + [ 1.915372] NET: Registered protocol family 10 + [ 1.924358] Segment Routing with IPv6 + [ 1.929125] sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver + [ 1.938379] NET: Registered protocol family 17 + [ 1.944944] hctosys: unable to open rtc device (rtc0) + [ 1.962991] EXT4-fs (mmcblk0p3): INFO: recovery required on readonly filesystem + [ 1.972196] EXT4-fs (mmcblk0p3): write access will be enabled during recovery + [ 2.054832] EXT4-fs (mmcblk0p3): recovery complete + [ 2.064742] EXT4-fs (mmcblk0p3): mounted filesystem with ordered data mode. Opts: (null) + [ 2.075057] VFS: Mounted root (ext4 filesystem) readonly on device 179:3. + [ 2.084573] Freeing unused kernel memory: 168K + [ 2.090122] This architecture does not have kernel memory protection. + [ 2.098235] Run /sbin/init as init process + [ 2.612563] random: fast init done + [ 2.809794] systemd[1]: System time before build time, advancing clock. + [ 2.868818] systemd[1]: systemd 244.3+ running in system mode. (+PAM -AUDIT -SELINUX +IMA -APPARMOR -SMACK +SYSVINIT +UTMP -LIBCRYPTSETUP -GCRYPT -GNUTLS +ACL +XZ -LZ4 -SECCOMP +BLKID -ELFUTILS +KMOD -IDN2 -IDN -PCRE2 default-hierarchy=hybrid) + [ 2.896774] systemd[1]: Detected architecture riscv64. + + Welcome to OpenEmbedded nodistro.0! + + [ 2.953510] systemd[1]: Set hostname to . + [ 4.269288] random: systemd: uninitialized urandom read (16 bytes read) + [ 4.281772] systemd[1]: Created slice system-getty.slice. + [ OK ] Created slice system-getty.slice. + [ 4.321956] random: systemd: uninitialized urandom read (16 bytes read) + [ 4.332378] systemd[1]: Created slice system-serial\x2dgetty.slice. + [ OK ] Created slice system-serial\x2dgetty.slice. + [ 4.371978] random: systemd: uninitialized urandom read (16 bytes read) + [ 4.382106] systemd[1]: Created slice User and Session Slice. + [ OK ] Created slice User and Session Slice. + [ 4.422798] systemd[1]: Started Dispatch Password Requests to Console Directory Watch. + [ OK ] Started Dispatch Password …ts to Console Directory Watch. + [ 4.472693] systemd[1]: Started Forward Password Requests to Wall Directory Watch. + [ OK ] Started Forward Password R…uests to Wall Directory Watch. + [ 4.522586] systemd[1]: Reached target Paths. + [ OK ] Reached target Paths. + [ 4.562253] systemd[1]: Reached target Remote File Systems. + [ OK ] Reached target Remote File Systems. + [ 4.602154] systemd[1]: Reached target Slices. + [ OK ] Reached target Slices. + [ 4.642301] systemd[1]: Reached target Swap. + [ OK ] Reached target Swap. + [ 4.683183] systemd[1]: Listening on initctl Compatibility Named Pipe. + [ OK ] Listening on initctl Compatibility Named Pipe. + [ 4.750416] systemd[1]: Condition check resulted in Journal Audit Socket being skipped. + [ 4.762960] systemd[1]: Listening on Journal Socket (/dev/log). + [ OK ] Listening on Journal Socket (/dev/log). + [ 4.803839] systemd[1]: Listening on Journal Socket. + [ OK ] Listening on Journal Socket. + [ 4.844307] systemd[1]: Listening on Network Service Netlink Socket. + [ OK ] Listening on Network Service Netlink Socket. + [ 4.883652] systemd[1]: Listening on udev Control Socket. + [ OK ] Listening on udev Control Socket. + [ 4.923218] systemd[1]: Listening on udev Kernel Socket. + [ OK ] Listening on udev Kernel Socket. + [ 4.963758] systemd[1]: Condition check resulted in Huge Pages File System being skipped. + [ 4.975387] systemd[1]: Condition check resulted in POSIX Message Queue File System being skipped. + [ 4.988039] systemd[1]: Condition check resulted in Kernel Debug File System being skipped. + [ 5.008120] systemd[1]: Mounting Temporary Directory (/tmp)... + Mounting Temporary Directory (/tmp)... + [ 5.052616] systemd[1]: Condition check resulted in Create list of static device nodes for the current kernel being skipped. + [ 5.075536] systemd[1]: Starting File System Check on Root Device... + Starting File System Check on Root Device... + [ 5.136915] systemd[1]: Starting Journal Service... + Starting Journal Service... + [ 5.160116] systemd[1]: Condition check resulted in Load Kernel Modules being skipped. + [ 5.172867] systemd[1]: Condition check resulted in FUSE Control File System being skipped. + [ 5.197446] systemd[1]: Mounting Kernel Configuration File System... + Mounting Kernel Configuration File System... + [ 5.222039] systemd[1]: Starting Apply Kernel Variables... + Starting Apply Kernel Variables... + [ 5.242677] systemd[1]: Starting udev Coldplug all Devices... + Starting udev Coldplug all Devices... + [ 5.277117] systemd[1]: Mounted Temporary Directory (/tmp). + [ OK ] Mounted Temporary Di[ 5.288434] systemd[1]: Mounted Kernel Configuration File System. + rectory (/tmp). + [ OK ] Mounted Kernel Configuration File System. + [ 5.347121] systemd[1]: Started Journal Service. + [ OK ] Started Journal Service. + [ OK ] Started Apply Kernel Variables. + [ OK ] Started File System Check on Root Device. + Starting Remount Root and Kernel File Systems... + [ 5.700818] EXT4-fs (mmcblk0p3): re-mounted. Opts: (null) + [ OK ] Started Remount Root and Kernel File Systems. + Starting Flush Journal to Persistent Storage... + Starting Create Static Device Nodes in /dev... + [ 5.857779] systemd-journald[75]: Received client request to flush runtime journal. + [ OK ] Started Flush Journal to Persistent Storage. + [ OK ] Started Create Static Device Nodes in /dev. + [ OK ] Reached target Local File Systems (Pre). + Mounting /var/volatile... + Starting udev Kernel Device Manager... + [ OK ] Mounted /var/volatile. + Starting Load/Save Random Seed... + [ OK ] Reached target Local File Systems. + Starting Create Volatile Files and Directories... + [ OK ] Started udev Kernel Device Manager. + [ OK ] Started Create Volatile Files and Directories. + Starting Network Time Synchronization... + Starting Update UTMP about System Boot/Shutdown... + [ OK ] Started Update UTMP about System Boot/Shutdown. + [ OK ] Started Network Time Synchronization. + [ OK ] Reached target System Time Set. + [ OK ] Reached target System Time Synchronized. + [ OK ] Started udev Coldplug all Devices. + [ OK ] Reached target System Initialization. + [ OK ] Started Daily Cleanup of Temporary Directories. + [ OK ] Reached target Timers. + [ OK ] Listening on D-Bus System Message Bus Socket. + [ OK ] Listening on dropbear.socket. + [ OK ] Reached target Sockets. + [ OK ] Reached target Basic System. + [ OK ] Started D-Bus System Message Bus. + Starting IPv6 Packet Filtering Framework... + Starting IPv4 Packet Filtering Framework... + Starting Login Service... + [ OK ] Started IPv6 Packet Filtering Framework. + [ OK ] Started IPv4 Packet Filtering Framework. + [ 11.341568] random: crng init done + [ 11.345841] random: 7 urandom warning(s) missed due to ratelimiting + [ OK ] Started Load/Save Random Seed. + [ OK ] Started Login Service. + [ OK ] Reached target Network (Pre). + Starting Network Service... + [ OK ] Started Network Service. + [ 13.673774] macb 20112000.ethernet eth0: PHY [20112000.ethernet-ffffffff:09] driver [Vitesse VSC8662] (irq=POLL) + [ 13.686635] macb 20112000.ethernet eth0: configuring for phy/sgmii link mode + [ 13.702061] pps pps0: new PPS source ptp0 + [ 13.713053] macb 20112000.ethernet: gem-ptp-timer ptp clock registered. + Starting Network Name Resolution... + [ OK ] Started Network Name Resolution. + [ OK ] Reached target Network. + [ OK ] Reached target Host and Network Name Lookups. + [ OK ] Started Collectd. + Starting Permit User Sessions... + [ OK ] Started Permit User Sessions. + [ OK ] Started Getty on tty1. + [ OK ] Started Serial Getty on ttyS0. + [ OK ] Reached target Login Prompts. + [ OK ] Reached target Multi-User System. + Starting Update UTMP about System Runlevel Changes... + [ OK ] Started Update UTMP about System Runlevel Changes. + + OpenEmbedded nodistro.0 icicle-kit-es ttyS0 + + icicle-kit-es login: [ 17.900317] macb 20112000.ethernet eth0: Link is Up - 1Gbps/Full - flow control tx + [ 17.909943] IPv6: ADDRCONF(NETDEV_CHANGE): eth0: link becomes ready + + icicle-kit-es login: root + root@icicle-kit-es:~#