From patchwork Thu Oct 1 07:07:55 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Amitay Isaacs X-Patchwork-Id: 1374866 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4C244p4fsVz9sVM for ; Thu, 1 Oct 2020 17:09:46 +1000 (AEST) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=ozlabs.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; secure) header.d=ozlabs.org header.i=@ozlabs.org header.a=rsa-sha256 header.s=201707 header.b=ORGQnUEY; dkim-atps=neutral Received: from bilbo.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 4C244p2P9tzDqVC for ; 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Thu, 1 Oct 2020 17:09:25 +1000 (AEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ozlabs.org; s=201707; t=1601536178; bh=cxBuUUBFEfbKlbYlEIaL9knBsMuYG1O+3bnIQOTRB/s=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ORGQnUEYoMddku/a+MWB7/zS+kh4CCJ+qOA9xnUAxdnSyg/42JKp9SUyqeT9cO2V7 NFPsRqLo1l2LFTQnMs50k6sMPOeU4woFCmTk+3woRHJIKQ40y4tUwpKD8SAQwKlmWx uPP3st5stUQQHHSPLiWrLnFwqDNgTkTjDRGeaxSSZpU7Pz/hSMwHHd5EsMrDJ+zQYT 38eIWof4u8S1b/4S460YCihKnxs8ED04Lexf82K7dwp7evIWafQ5RaBf/3KA4R/0Rq ublrkFB6uv/QTKnaDwK89ELNSTWV6eBwUaSahyiahKiwQabZaC2ZQ+6NlHqLpF5j/R mW5TRin02dp5g== From: Amitay Isaacs To: pdbg@lists.ozlabs.org Date: Thu, 1 Oct 2020 17:07:55 +1000 Message-Id: <20201001070814.102735-2-amitay@ozlabs.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201001070814.102735-1-amitay@ozlabs.org> References: <20201001070814.102735-1-amitay@ozlabs.org> MIME-Version: 1.0 Subject: [Pdbg] [PATCH v2 01/20] libpdbg: Add p10 X-BeenThere: pdbg@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: "mailing list for https://github.com/open-power/pdbg development" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Amitay Isaacs Errors-To: pdbg-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Pdbg" Signed-off-by: Amitay Isaacs Reviewed-by: Joel Stanley --- libpdbg/libpdbg.h | 1 + libpdbg/target.h | 3 ++- 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/libpdbg/libpdbg.h b/libpdbg/libpdbg.h index 180a609..2630fd7 100644 --- a/libpdbg/libpdbg.h +++ b/libpdbg/libpdbg.h @@ -53,6 +53,7 @@ enum pdbg_proc { PDBG_PROC_UNKNOWN, /**< Unknown processor */ PDBG_PROC_P8, /**< POWER8 processor */ PDBG_PROC_P9, /**< POWER9 processor */ + PDBG_PROC_P10, /**< POWER10 processor */ }; /** diff --git a/libpdbg/target.h b/libpdbg/target.h index a12cce8..572631f 100644 --- a/libpdbg/target.h +++ b/libpdbg/target.h @@ -29,8 +29,9 @@ #define CHIP_ID_P8P 0xd3 #define CHIP_ID_P9 0xd1 #define CHIP_ID_P9P 0xd9 +#define CHIP_ID_P10 0xda -enum chip_type {CHIP_UNKNOWN, CHIP_P8, CHIP_P8NV, CHIP_P9}; +enum chip_type {CHIP_UNKNOWN, CHIP_P8, CHIP_P8NV, CHIP_P9, CHIP_P10}; struct pdbg_target_class { char *name; From patchwork Thu Oct 1 07:07:56 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Amitay Isaacs X-Patchwork-Id: 1374868 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [203.11.71.2]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4C245235Ftz9sVk for ; Thu, 1 Oct 2020 17:09:58 +1000 (AEST) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=ozlabs.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; secure) header.d=ozlabs.org header.i=@ozlabs.org header.a=rsa-sha256 header.s=201707 header.b=TIa1RkHv; dkim-atps=neutral Received: from bilbo.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 4C24522PPWzDqTk for ; Thu, 1 Oct 2020 17:09:58 +1000 (AEST) X-Original-To: pdbg@lists.ozlabs.org Delivered-To: pdbg@lists.ozlabs.org Received: from ozlabs.org (bilbo.ozlabs.org [203.11.71.1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 4C244t2Zc1zDqTD for ; Thu, 1 Oct 2020 17:09:50 +1000 (AEST) Authentication-Results: lists.ozlabs.org; dmarc=pass (p=none dis=none) header.from=ozlabs.org Authentication-Results: lists.ozlabs.org; dkim=pass (2048-bit key; secure) header.d=ozlabs.org header.i=@ozlabs.org header.a=rsa-sha256 header.s=201707 header.b=TIa1RkHv; dkim-atps=neutral Received: from authenticated.ozlabs.org (localhost [127.0.0.1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by mail.ozlabs.org (Postfix) with ESMTPSA id 4C244g2P3Cz9sVL; Thu, 1 Oct 2020 17:09:38 +1000 (AEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ozlabs.org; s=201707; t=1601536189; bh=f3zPZZyR6f95+auFc5w2vErRgwo5uHfwoR4WsYrrAzE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=TIa1RkHv1RHINo0XC83JBk/MHzpNnpPY089E8FQjhngEeRf2+wNmaNjC8Ba9R5Vlz oRLiA+KQXDh6n2v3SSPj+JE0DY+DhOP9arqWaU/BRrDwps9jKNNovh4TyhS1y9kuYo PcC+izA/G3lPu1c9zSE7ymYl0iacHb6HIX8QzpM7qzmVRShh/PqBhG7JwpWaiWWJ0h 82xKXo4PsHvU4DuT/odZ8w2djGehP2n+Jx7+pkpCeUok/+m7doc3Qhasca0P/2Qhpc ux5kvjUvaUqZ6pfglZZdQ7qjqI80CsAFHXQSGuWLyP1CFi9mknN0ZY2uobg4y1ZHOw tQbEv0nDa9T3w== From: Amitay Isaacs To: pdbg@lists.ozlabs.org Date: Thu, 1 Oct 2020 17:07:56 +1000 Message-Id: <20201001070814.102735-3-amitay@ozlabs.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201001070814.102735-1-amitay@ozlabs.org> References: <20201001070814.102735-1-amitay@ozlabs.org> MIME-Version: 1.0 Subject: [Pdbg] [PATCH v2 02/20] dts: Add p10 device tree X-BeenThere: pdbg@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: "mailing list for https://github.com/open-power/pdbg development" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Amitay Isaacs Errors-To: pdbg-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Pdbg" Signed-off-by: Amitay Isaacs Reviewed-by: Joel Stanley --- Makefile.am | 2 +- p10.dts.m4 | 652 ++++++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 653 insertions(+), 1 deletion(-) create mode 100644 p10.dts.m4 diff --git a/Makefile.am b/Makefile.am index dce09ab..d4f7dc1 100644 --- a/Makefile.am +++ b/Makefile.am @@ -60,7 +60,7 @@ DT = fake.dts fake-backend.dts fake2.dts fake2-backend.dts \ p8-fsi.dts p8-i2c.dts p8-kernel.dts \ p9w-fsi.dts p9r-fsi.dts p9z-fsi.dts bmc-kernel.dts \ bmc-sbefifo.dts \ - p8-host.dts p9-host.dts p8.dts p9.dts + p8-host.dts p9-host.dts p8.dts p9.dts p10.dts DT_sources = $(DT:.dts=.dtb.S) DT_headers = $(DT:.dts=.dt.h) diff --git a/p10.dts.m4 b/p10.dts.m4 new file mode 100644 index 0000000..aee608f --- /dev/null +++ b/p10.dts.m4 @@ -0,0 +1,652 @@ +define(`CONCAT', `$1$2')dnl + +dnl +dnl CORE([index]) +dnl +define(`THREAD', +` + thread@$1 { + reg = <0x00>; + compatible = "ibm,power-thread", "ibm,power10-thread"; + index = <0x$1>; + }; +')dnl + +dnl +dnl CORE([index]) +dnl +define(`CORE', +` + core@0 { + #address-cells = <0x01>; + #size-cells = <0x00>; + reg = <0x00 0x00 0xfffff>; + compatible = "ibm,power-core", "ibm,power10-core"; + index = <0x$1>; + + THREAD(0) + THREAD(1) + THREAD(2) + THREAD(3) + }; +')dnl + +dnl +dnl CHIPLET__([index]) +dnl +define(`CHIPLET__', +`define(`addr', CONCAT($1, 000000))dnl + + CONCAT(chiplet@, addr) { + reg = <0x00 CONCAT(0x,addr) 0xfffff>; + compatible = "ibm,power10-chiplet"; + index = <0x$1>; + +')dnl + +dnl +dnl CHIPLET_([index]) +dnl +define(`CHIPLET_', +`define(`addr', CONCAT($1, 000000))dnl + + CONCAT(chiplet@, addr) { + #address-cells = <0x02>; + #size-cells = <0x01>; + reg = <0x00 CONCAT(0x,addr) 0xfffff>; + compatible = "ibm,power10-chiplet"; + index = <0x$1>; + +')dnl + +dnl +dnl EQ_([index]) +dnl +define(`EQ_', +`define(`chiplet_id', CONCAT(1, $1))dnl +define(`addr', CONCAT(chiplet_id, 000000))dnl + + eq@$1 { + #address-cells = <0x02>; + #size-cells = <0x01>; + reg = <0x00 CONCAT(0x,addr) 0xfffff>; + compatible = "ibm,power10-eq"; + index = <$1>; + +')dnl + +dnl +dnl EX_([eq_index, ex_index]) +dnl +define(`EX_', +`define(`chiplet_id', CONCAT(1, $1))dnl +define(`addr', CONCAT(chiplet_id, 000000))dnl + + ex@$2 { + #address-cells = <0x02>; + #size-cells = <0x01>; + reg = <0x00 CONCAT(0x,addr) 0xfffff>; + compatible = "ibm,power10-ex"; + index = <$2>; + +')dnl + +dnl +dnl CHIP([index]) +dnl +define(`CHIP', +` + mem$1 { + index = < 0x$1 >; + }; + + proc$1 { + compatible = "ibm,power-proc", "ibm,power10-proc"; + index = < 0x$1 >; + + fsi { + index = < 0x$1 >; + }; + + pib { + #address-cells = < 0x02 >; + #size-cells = < 0x01 >; + index = < 0x$1 >; + + adu@90000 { + compatible = "ibm,power10-adu"; + reg = < 0x00 0x90000 0x50 >; + system-path = "/mem$1"; + }; + + htm@5012880 { + compatible = "ibm,power10-nhtm"; + reg = < 0x00 0x5012880 0x40 >; + index = < 0x$1 >; + }; + + htm@50128C0 { + compatible = "ibm,power10-nhtm"; + reg = < 0x00 0x50128c0 0x40 >; + index = < 0x$1 >; + }; + + CHIPLET_(1) + tp@0 { + reg = < 0x00 0x1000000 0xfffff >; + compatible = "ibm,power10-tp"; + index = < 0x00 >; + }; + }; + + CHIPLET__(2) + n0 { + compatible = "ibm,power10-nest"; + index = < 0x00 >; + + capp0 { + compatible = "ibm,power10-capp"; + index = < 0x00 >; + }; + }; + }; + + CHIPLET__(3) + n1 { + compatible = "ibm,power10-nest"; + index = < 0x01 >; + + mcs2 { + compatible = "ibm,power10-mcs"; + index = < 0x02 >; + }; + + mcs3 { + compatible = "ibm,power10-mcs"; + index = < 0x03 >; + }; + }; + }; + + CHIPLET__(4) + n2 { + compatible = "ibm,power10-nest"; + index = < 0x02 >; + + capp1 { + compatible = "ibm,power10-capp"; + index = < 0x01 >; + }; + }; + }; + + CHIPLET__(5) + n3 { + compatible = "ibm,power10-nest"; + index = < 0x03 >; + + mcs0 { + compatible = "ibm,power10-mcs"; + index = < 0x00 >; + }; + + mcs1 { + compatible = "ibm,power10-mcs"; + index = < 0x01 >; + }; + }; + }; + + CHIPLET_(6) + xbus$1_0: xbus@0 { + compatible = "ibm,power10-xbus"; + index = < 0x01 >; + reg = < 0x00 0x6000000 0xfffff >; + }; + }; + + CHIPLET_(7) + mc@0 { + reg = < 0x00 0x7000000 0xfffff >; + compatible = "ibm,power10-mc"; + index = < 0x00 >; + + mca0 { + compatible = "ibm,power10-mca"; + index = < 0x00 >; + }; + + mca1 { + compatible = "ibm,power10-mca"; + index = < 0x01 >; + }; + + mca2 { + compatible = "ibm,power10-mca"; + index = < 0x02 >; + }; + + mca3 { + compatible = "ibm,power10-mca"; + index = < 0x03 >; + }; + + mcbist { + compatible = "ibm,power10-mcbist"; + index = < 0x00 >; + }; + }; + }; + + CHIPLET_(8) + mc@1 { + reg = < 0x00 0x8000000 0xfffff >; + compatible = "ibm,power10-mc"; + index = < 0x01 >; + + mca0 { + compatible = "ibm,power10-mca"; + index = < 0x04 >; + }; + + mca1 { + compatible = "ibm,power10-mca"; + index = < 0x05 >; + }; + + mca2 { + compatible = "ibm,power10-mca"; + index = < 0x06 >; + }; + + mca3 { + compatible = "ibm,power10-mca"; + index = < 0x07 >; + }; + + mcbist { + compatible = "ibm,power10-mcbist"; + index = < 0x01 >; + }; + }; + }; + + CHIPLET_(9) + obus@0 { + reg = < 0x00 0x9000000 0xfffff >; + compatible = "ibm,power10-obus"; + index = < 0x00 >; + }; + + obrick0 { + compatible = "ibm,power10-obus_brick"; + index = < 0x00 >; + }; + + obrick1 { + compatible = "ibm,power10-obus_brick"; + index = < 0x01 >; + }; + + obrick2 { + compatible = "ibm,power10-obus_brick"; + index = < 0x02 >; + }; + }; + + CHIPLET_(c) + obus@3 { + reg = < 0x00 0xc000000 0xfffff >; + compatible = "ibm,power10-obus"; + index = < 0x03 >; + }; + + obrick0 { + compatible = "ibm,power10-obus_brick"; + index = < 0x09 >; + }; + + obrick1 { + compatible = "ibm,power10-obus_brick"; + index = < 0x0a >; + }; + + obrick2 { + compatible = "ibm,power10-obus_brick"; + index = < 0x0b >; + }; + }; + + CHIPLET_(d) + pec@d000000 { + reg = < 0x00 0xd000000 0xfffff >; + compatible = "ibm,power10-pec"; + index = < 0x00 >; + }; + + phb0 { + compatible = "ibm,power10-phb"; + index = < 0x00 >; + }; + + phb1 { + compatible = "ibm,power10-phb"; + index = < 0x01 >; + }; + }; + + CHIPLET_(e) + pec@e000000 { + reg = < 0x00 0xe000000 0xfffff >; + compatible = "ibm,power10-pec"; + index = < 0x01 >; + }; + + phb0 { + compatible = "ibm,power10-phb"; + index = < 0x02 >; + }; + + phb1 { + compatible = "ibm,power10-phb"; + index = < 0x03 >; + }; + }; + + CHIPLET_(f) + pec@f000000 { + reg = < 0x00 0xf000000 0xfffff >; + compatible = "ibm,power10-pec"; + index = < 0x02 >; + }; + + phb0 { + compatible = "ibm,power10-phb"; + index = < 0x04 >; + }; + + phb1 { + compatible = "ibm,power10-phb"; + index = < 0x05 >; + }; + }; + + CHIPLET_(10) + EQ_(0) + EX_(0,0) + CHIPLET_(20) + CORE(00) + }; + + CHIPLET_(21) + CORE(01) + }; + }; + + EX_(0,1) + CHIPLET_(22) + CORE(02) + }; + + CHIPLET_(23) + CORE(03) + }; + }; + }; + }; + + CHIPLET_(11) + EQ_(1) + EX_(1,0) + CHIPLET_(24) + CORE(04) + }; + + CHIPLET_(25) + CORE(05) + }; + }; + + EX_(1,1) + CHIPLET_(26) + CORE(06) + }; + + CHIPLET_(27) + CORE(07) + }; + }; + }; + }; + + CHIPLET_(12) + EQ_(2) + EX_(2,0) + CHIPLET_(28) + CORE(08) + }; + + CHIPLET_(29) + CORE(09) + }; + }; + + EX_(2,1) + CHIPLET_(2a) + CORE(0a) + }; + + CHIPLET_(2b) + CORE(0b) + }; + }; + }; + }; + + CHIPLET_(13) + EQ_(3) + EX_(3,0) + CHIPLET_(2c) + CORE(0c) + }; + + CHIPLET_(2d) + CORE(0d) + }; + }; + + EX_(3,1) + CHIPLET_(2e) + CORE(0e) + }; + + CHIPLET_(2f) + CORE(0f) + }; + }; + }; + }; + + CHIPLET_(14) + EQ_(4) + EX_(4,0) + CHIPLET_(30) + CORE(10) + }; + + CHIPLET_(31) + CORE(11) + }; + }; + + EX_(4,1) + CHIPLET_(32) + CORE(12) + }; + + CHIPLET_(33) + CORE(13) + }; + }; + }; + }; + + CHIPLET_(15) + EQ_(5) + EX_(5,0) + CHIPLET_(34) + CORE(14) + }; + + CHIPLET_(35) + CORE(15) + }; + }; + + EX_(5,1) + CHIPLET_(36) + CORE(16) + }; + + CHIPLET_(37) + CORE(17) + }; + }; + }; + }; + + nv0 { + compatible = "ibm,power10-nv"; + index = < 0x00 >; + }; + + nv1 { + compatible = "ibm,power10-nv"; + index = < 0x01 >; + }; + + nv2 { + compatible = "ibm,power10-nv"; + index = < 0x02 >; + }; + + nv3 { + compatible = "ibm,power10-nv"; + index = < 0x03 >; + }; + + nv4 { + compatible = "ibm,power10-nv"; + index = < 0x04 >; + }; + + nv5 { + compatible = "ibm,power10-nv"; + index = < 0x05 >; + }; + + occ0 { + compatible = "ibm,power10-occ"; + index = < 0x00 >; + }; + + sbe0 { + compatible = "ibm,power10-sbe"; + index = < 0x00 >; + }; + + ppe0 { + compatible = "ibm,power10-ppe"; + index = < 0x00 >; + }; + + ppe1 { + compatible = "ibm,power10-ppe"; + index = < 0x0a >; + }; + + ppe2 { + compatible = "ibm,power10-ppe"; + index = < 0x0d >; + }; + + ppe3 { + compatible = "ibm,power10-ppe"; + index = < 0x14 >; + }; + + ppe4 { + compatible = "ibm,power10-ppe"; + index = < 0x19 >; + }; + + ppe5 { + compatible = "ibm,power10-ppe"; + index = < 0x1e >; + }; + + ppe6 { + compatible = "ibm,power10-ppe"; + index = < 0x28 >; + }; + + ppe7 { + compatible = "ibm,power10-ppe"; + index = < 0x29 >; + }; + + ppe8 { + compatible = "ibm,power10-ppe"; + index = < 0x2a >; + }; + + ppe9 { + compatible = "ibm,power10-ppe"; + index = < 0x2b >; + }; + + ppe10 { + compatible = "ibm,power10-ppe"; + index = < 0x2c >; + }; + + ppe11 { + compatible = "ibm,power10-ppe"; + index = < 0x2d >; + }; + + ppe12 { + compatible = "ibm,power10-ppe"; + index = < 0x2e >; + }; + + ppe13 { + compatible = "ibm,power10-ppe"; + index = < 0x32 >; + }; + + ppe14 { + compatible = "ibm,power10-ppe"; + index = < 0x34 >; + }; + + ppe15 { + compatible = "ibm,power10-ppe"; + index = < 0x38 >; + }; + }; + }; +')dnl + +/dts-v1/; + +/ { + CHIP(0) + CHIP(1) + CHIP(2) + CHIP(3) + CHIP(4) + CHIP(5) + CHIP(6) + CHIP(7) +}; From patchwork Thu Oct 1 07:07:57 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Amitay Isaacs X-Patchwork-Id: 1374869 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4C24592Lx6z9sVT for ; Thu, 1 Oct 2020 17:10:05 +1000 (AEST) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=ozlabs.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; secure) header.d=ozlabs.org header.i=@ozlabs.org header.a=rsa-sha256 header.s=201707 header.b=I0XEtavj; dkim-atps=neutral Received: from bilbo.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 4C24591FsqzDqTl for ; Thu, 1 Oct 2020 17:10:05 +1000 (AEST) X-Original-To: pdbg@lists.ozlabs.org Delivered-To: pdbg@lists.ozlabs.org Received: from ozlabs.org (bilbo.ozlabs.org [203.11.71.1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 4C244x4fLrzDqTM for ; Thu, 1 Oct 2020 17:09:53 +1000 (AEST) Authentication-Results: lists.ozlabs.org; dmarc=pass (p=none dis=none) header.from=ozlabs.org Authentication-Results: lists.ozlabs.org; dkim=pass (2048-bit key; secure) header.d=ozlabs.org header.i=@ozlabs.org header.a=rsa-sha256 header.s=201707 header.b=I0XEtavj; dkim-atps=neutral Received: from authenticated.ozlabs.org (localhost [127.0.0.1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by mail.ozlabs.org (Postfix) with ESMTPSA id 4C244v1Nxgz9sVH; Thu, 1 Oct 2020 17:09:50 +1000 (AEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ozlabs.org; s=201707; t=1601536193; bh=5z7L+HO1aBiVabkn8sjL53t8y004qFQXvsbCSAqpMCg=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=I0XEtavjTSsorduDy4N/rCTZRi9NtB0pE0+04x88xgGYUP5D2GDXHb2WphDnZQPmR M5vV/3Ubkx5VYJMvCesadVuaMCq4XrymxF5JecJC66qa1WpaKELVqcon+61LeC3Ap/ UODLtN4UbH+uG1EHm7f9LwzxaxzWCsKV0LWQ6zh1WWYTwacph/dmxcjIj/s+gO5Je1 Rlf2DZngGoHC1Wql6+//ec7z920B6PZCkP7IwxXRDcKl/7S79Z3vHIkJ9+lzSU39dB Q3O7zL2eQ5DU6oXRo0fvI6055qelp5dBNvRBjZAvJ0DjfyES5Gwb5RM81NmqxMa7/p 9Gvsvywz1GugA== From: Amitay Isaacs To: pdbg@lists.ozlabs.org Date: Thu, 1 Oct 2020 17:07:57 +1000 Message-Id: <20201001070814.102735-4-amitay@ozlabs.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201001070814.102735-1-amitay@ozlabs.org> References: <20201001070814.102735-1-amitay@ozlabs.org> MIME-Version: 1.0 Subject: [Pdbg] [PATCH v2 03/20] libpdbg: Enable p10 BMC backend X-BeenThere: pdbg@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: "mailing list for https://github.com/open-power/pdbg development" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Amitay Isaacs Errors-To: pdbg-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Pdbg" Signed-off-by: Amitay Isaacs Reviewed-by: Joel Stanley --- libpdbg/cfam.c | 2 ++ libpdbg/dtb.c | 45 +++++++++++++++++++++++++++++++++++++++++---- 2 files changed, 43 insertions(+), 4 deletions(-) diff --git a/libpdbg/cfam.c b/libpdbg/cfam.c index 0b670d8..ffe6929 100644 --- a/libpdbg/cfam.c +++ b/libpdbg/cfam.c @@ -247,6 +247,8 @@ enum chip_type get_chip_type(uint64_t chip_id) return CHIP_P8NV; case CHIP_ID_P9: return CHIP_P9; + case CHIP_ID_P10: + return CHIP_P10; default: return CHIP_UNKNOWN; } diff --git a/libpdbg/dtb.c b/libpdbg/dtb.c index f47f28f..02464e8 100644 --- a/libpdbg/dtb.c +++ b/libpdbg/dtb.c @@ -48,6 +48,7 @@ #include "p8.dt.h" #include "p9.dt.h" +#include "p10.dt.h" #define AMI_BMC "/proc/ractrends/Helper/FwInfo" #define XSCOM_BASE_PATH "/sys/kernel/debug/powerpc/scom" @@ -228,9 +229,15 @@ static void bmc_target(struct pdbg_dtb *dtb) dtb->backend.fdt = &_binary_bmc_kernel_dtb_o_start; if (!dtb->system.fdt) dtb->system.fdt = &_binary_p9_dtb_o_start; + } else if (!strcmp(pdbg_backend_option, "p10")) { + pdbg_proc = PDBG_PROC_P10; + if (!dtb->backend.fdt) + dtb->backend.fdt = &_binary_bmc_kernel_dtb_o_start; + if (!dtb->system.fdt) + dtb->system.fdt = &_binary_p10_dtb_o_start; } else { pdbg_log(PDBG_ERROR, "Invalid system type %s\n", pdbg_backend_option); - pdbg_log(PDBG_ERROR, "Use 'p8' or 'p9'\n"); + pdbg_log(PDBG_ERROR, "Use 'p8', 'p9' or 'p10'\n"); } return; @@ -240,6 +247,15 @@ static void bmc_target(struct pdbg_dtb *dtb) return; switch(chip_id) { + case CHIP_ID_P10: + pdbg_log(PDBG_INFO, "Found a POWER10 OpenBMC based system\n"); + pdbg_proc = PDBG_PROC_P10; + if (!dtb->backend.fdt) + dtb->backend.fdt = &_binary_bmc_kernel_dtb_o_start; + if (!dtb->system.fdt) + dtb->system.fdt = &_binary_p10_dtb_o_start; + break; + case CHIP_ID_P9: case CHIP_ID_P9P: pdbg_log(PDBG_INFO, "Found a POWER9 OpenBMC based system\n"); @@ -276,9 +292,15 @@ static void sbefifo_target(struct pdbg_dtb *dtb) dtb->backend.fdt = &_binary_bmc_sbefifo_dtb_o_start; if (!dtb->system.fdt) dtb->system.fdt = &_binary_p9_dtb_o_start; + } else if (!strcmp(pdbg_backend_option, "p10")) { + pdbg_proc = PDBG_PROC_P10; + if (!dtb->backend.fdt) + dtb->backend.fdt = &_binary_bmc_sbefifo_dtb_o_start; + if (!dtb->system.fdt) + dtb->system.fdt = &_binary_p10_dtb_o_start; } else { pdbg_log(PDBG_ERROR, "Invalid system type %s\n", pdbg_backend_option); - pdbg_log(PDBG_ERROR, "Use 'p9'\n"); + pdbg_log(PDBG_ERROR, "Use 'p9' or 'p10'\n"); } return; @@ -288,6 +310,15 @@ static void sbefifo_target(struct pdbg_dtb *dtb) return; switch(chip_id) { + case CHIP_ID_P10: + pdbg_log(PDBG_INFO, "Found a POWER10 OpenBMC based system\n"); + pdbg_proc = PDBG_PROC_P10; + if (!dtb->backend.fdt) + dtb->backend.fdt = &_binary_bmc_sbefifo_dtb_o_start; + if (!dtb->system.fdt) + dtb->system.fdt = &_binary_p10_dtb_o_start; + break; + case CHIP_ID_P9: case CHIP_ID_P9P: pdbg_proc = PDBG_PROC_P9; @@ -485,7 +516,7 @@ struct pdbg_dtb *pdbg_default_dtb(void *system_fdt) case PDBG_BACKEND_CRONUS: if (!pdbg_backend_option) { pdbg_log(PDBG_ERROR, "No system type specified\n"); - pdbg_log(PDBG_ERROR, "Use p8@ or p9@\n"); + pdbg_log(PDBG_ERROR, "Use [p8|p9|p10]@\n"); return NULL; } @@ -501,9 +532,15 @@ struct pdbg_dtb *pdbg_default_dtb(void *system_fdt) dtb->backend.fdt = &_binary_cronus_dtb_o_start; if (!dtb->system.fdt) dtb->system.fdt = &_binary_p9_dtb_o_start; + } else if (!strncmp(pdbg_backend_option, "p10", 3)) { + pdbg_proc = PDBG_PROC_P10; + if (!dtb->backend.fdt) + dtb->backend.fdt = &_binary_cronus_dtb_o_start; + if (!dtb->system.fdt) + dtb->system.fdt = &_binary_p10_dtb_o_start; } else { pdbg_log(PDBG_ERROR, "Invalid system type %s\n", pdbg_backend_option); - pdbg_log(PDBG_ERROR, "Use p8@ or p9@\n"); + pdbg_log(PDBG_ERROR, "Use [p8|p9|p10]@\n"); } break; From patchwork Thu Oct 1 07:07:58 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Amitay Isaacs X-Patchwork-Id: 1374870 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4C245N628Lz9sVT for ; Thu, 1 Oct 2020 17:10:16 +1000 (AEST) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=ozlabs.org Authentication-Results: ozlabs.org; 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dkim-atps=neutral Received: from authenticated.ozlabs.org (localhost [127.0.0.1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by mail.ozlabs.org (Postfix) with ESMTPSA id 4C244y5qBXz9sVN; Thu, 1 Oct 2020 17:09:53 +1000 (AEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ozlabs.org; s=201707; t=1601536203; bh=srpPIB0bJua1b1OVH2E5luLFb9M6WfOGnZipW24tA7I=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=UOBMImvkVLAgZL3VVvR4QARUeLUFrYA4pEdSE8pmdlFlVGIXWuh4w24Nwu7FpCWOT +pVeyBr7mhMuzeA1xeRB0D5oXbyGY189tJqo0SgEymuEPNZPCMAcVwWHBBA5Hoswxc gupEqmQwG89YsDUBXxMYfyzmaZtn2SJdy8C0Bdo6YFLp5fOonYXDSpS9vb2B03bFkk wG+dVImHW+lkY5VxAzEoOgNfm91APyCFnmDnJzMd7WGHTNMr4ks7y8TnEgPkm5fCJ6 dtt14r+u7LAkZigLEBBr7mF2rDw8fo8KT2fNElTQENGmFjZdWq0qPh5dowez7e6YN+ 1v1BBNMrdr7yg== From: Amitay Isaacs To: pdbg@lists.ozlabs.org Date: Thu, 1 Oct 2020 17:07:58 +1000 Message-Id: <20201001070814.102735-5-amitay@ozlabs.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201001070814.102735-1-amitay@ozlabs.org> References: <20201001070814.102735-1-amitay@ozlabs.org> MIME-Version: 1.0 Subject: [Pdbg] [PATCH v2 04/20] libpdbg: Introduce p10 FAPI targets and address translation X-BeenThere: pdbg@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: "mailing list for https://github.com/open-power/pdbg development" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: pdbg-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Pdbg" From: Alistair Popple Signed-off-by: Alistair Popple Reviewed-by: Joel Stanley --- Makefile.am | 2 + libpdbg/hwunit.h | 14 + libpdbg/p10_fapi_targets.c | 583 +++++++++++++++++++++++++++++++++++++ libpdbg/p10_scom_addr.h | 133 +++++++++ 4 files changed, 732 insertions(+) create mode 100644 libpdbg/p10_fapi_targets.c create mode 100644 libpdbg/p10_scom_addr.h diff --git a/Makefile.am b/Makefile.am index d4f7dc1..779c52c 100644 --- a/Makefile.am +++ b/Makefile.am @@ -180,6 +180,8 @@ libpdbg_la_SOURCES = \ libpdbg/p9chip.c \ libpdbg/p9_fapi_targets.c \ libpdbg/p9_scom_addr.h \ + libpdbg/p10_fapi_targets.c \ + libpdbg/p10_scom_addr.h \ libpdbg/sbefifo.c \ libpdbg/sprs.h \ libpdbg/target.c \ diff --git a/libpdbg/hwunit.h b/libpdbg/hwunit.h index ee825bb..52fdaf0 100644 --- a/libpdbg/hwunit.h +++ b/libpdbg/hwunit.h @@ -306,4 +306,18 @@ struct capp { }; #define target_to_capp(x) container_of(x, struct capp, target) +struct omi { + struct pdbg_target target; +}; +#define target_to_omi(x) container_of(x, struct omi, target) + +struct omic { + struct pdbg_target target; +}; +#define target_to_omic(x) container_of(x, struct omic, target) + +struct mcc { + struct pdbg_target target; +}; +#define target_to_mcc(x) container_of(x, struct mcc, target) #endif /* __HWUNIT_H */ diff --git a/libpdbg/p10_fapi_targets.c b/libpdbg/p10_fapi_targets.c new file mode 100644 index 0000000..0779f50 --- /dev/null +++ b/libpdbg/p10_fapi_targets.c @@ -0,0 +1,583 @@ +/* Copyright 2020 IBM Corp. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + * implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include +#include +#include +#include +#include +#include + +#include "hwunit.h" +#include "bitutils.h" +#include "p10_scom_addr.h" + +#define t(x) (&(x)->target) + +static uint64_t p10_eq_translate(struct eq *eq, uint64_t addr) +{ + addr = set_chiplet_id(addr, EQ0_CHIPLET_ID + pdbg_target_index(t(eq))); + + return addr; +} + +static struct eq p10_eq = { + .target = { + .name = "POWER10 eq", + .compatible = "ibm,power10-eq", + .class = "eq", + .translate = translate_cast(p10_eq_translate), + }, +}; +DECLARE_HW_UNIT(p10_eq); + +#define NUM_CORES_PER_EQ 4 +static uint64_t p10_core_translate(struct core *c, uint64_t addr) +{ + int region = 0; + int chip_unitnum = pdbg_target_index(t(c)); + + switch(chip_unitnum % NUM_CORES_PER_EQ) { + case 0: + region = 8; + break; + case 1: + region = 4; + break; + case 2: + region = 2; + break; + case 3: + region = 1; + break; + } + addr = set_chiplet_id(addr, EQ0_CHIPLET_ID + pdbg_target_index(t(c)) / 4); + addr &= 0xFFFFFFFFFFFF0FFFULL; + addr |= ((region & 0xF) << 12); + + return addr; +} + +static struct core p10_core = { + .target = { + .name = "POWER10 core", + .compatible = "ibm,power10-core", + .class = "core", + .translate = translate_cast(p10_core_translate), + }, +}; +DECLARE_HW_UNIT(p10_core); + +static uint64_t p10_pec_translate(struct pec *pec, uint64_t addr) +{ + int chip_unitnum = pdbg_target_index(t(pec)); + + if (get_chiplet_id(addr) >= N0_CHIPLET_ID && + get_chiplet_id(addr) <= N1_CHIPLET_ID) + return set_chiplet_id(addr, + chip_unitnum ? N0_CHIPLET_ID : N1_CHIPLET_ID ); + else + return set_chiplet_id(addr, PCI0_CHIPLET_ID + pdbg_target_index(t(pec))); +} + +static struct pec p10_pec = { + .target = { + .name = "POWER10 pec", + .compatible = "ibm,power10-pec", + .class = "pec", + .translate = translate_cast(p10_pec_translate), + }, +}; +DECLARE_HW_UNIT(p10_pec); + +static uint64_t p10_phb_translate(struct phb *phb, uint64_t addr) +{ + int chip_unitnum = pdbg_target_index(t(phb)); + + if (get_chiplet_id(addr) >= N0_CHIPLET_ID && get_chiplet_id(addr) <= N1_CHIPLET_ID) { + addr = set_chiplet_id(addr, chip_unitnum / 3 ? N0_CHIPLET_ID : N1_CHIPLET_ID); + return set_sat_id(addr, 1 + chip_unitnum % 3); + } else { + addr = set_chiplet_id(addr, chip_unitnum / 3 + PCI0_CHIPLET_ID); + if (get_ring_id(addr) == 2) { + if (get_sat_id(addr) >= 1 && get_sat_id(addr) <= 3) + return set_sat_id(addr, 1 + chip_unitnum % 3); + else + return set_sat_id(addr, 4 + chip_unitnum % 3); + } + } + + /* We'll never get here due to the assert but gcc complains */ + return addr; +} + +static struct phb p10_phb = { + .target = { + .name = "POWER10 phb", + .compatible = "ibm,power10-phb", + .class = "phb", + .translate = translate_cast(p10_phb_translate), + }, +}; +DECLARE_HW_UNIT(p10_phb); + +static uint64_t p10_nmmu_translate(struct nmmu *nmmu, uint64_t addr) +{ + return set_chiplet_id(addr, pdbg_target_index(t(nmmu)) + N0_CHIPLET_ID); +} + +static struct nmmu p10_nmmu = { + .target = { + .name = "POWER10 nmmu", + .compatible = "ibm,power10-nmmu", + .class = "nmmu", + .translate = translate_cast(p10_nmmu_translate), + }, +}; +DECLARE_HW_UNIT(p10_nmmu); + +static uint64_t p10_iohs_translate(struct iohs *iohs, uint64_t addr) +{ + int chip_unitnum = pdbg_target_index(t(iohs)); + + if (get_chiplet_id(addr) >= AXON0_CHIPLET_ID && + get_chiplet_id(addr) <= AXON7_CHIPLET_ID) + addr = set_chiplet_id(addr, AXON0_CHIPLET_ID + chip_unitnum); + else if (get_chiplet_id(addr) >= PAU0_CHIPLET_ID && + get_chiplet_id(addr) <= PAU3_CHIPLET_ID) { + addr = set_chiplet_id(addr, chip_unitnum/2 + PAU0_CHIPLET_ID); + } else + /* We should bail here with an assert but it makes testing hard and we + * should never hit it anyway as all code will have been validated + * through the EKB CI process (LOL). */ + assert(1); + + if (get_chiplet_id(addr) >= PAU0_CHIPLET_ID && + get_chiplet_id(addr) <= PAU3_CHIPLET_ID) { + if (chip_unitnum % 2) + addr = set_io_group_addr(addr, 0x1); + else + addr = set_io_group_addr(addr, 0x0); + } + + return addr; +} + +static struct iohs p10_iohs = { + .target = { + .name = "POWER10 iohs", + .compatible = "ibm,power10-iohs", + .class = "iohs", + .translate = translate_cast(p10_iohs_translate), + }, +}; +DECLARE_HW_UNIT(p10_iohs); + +/* We take a struct pdbg_target and avoid the casting here as the translation is + * the same for both target types. */ +static uint64_t p10_mimc_translate(struct pdbg_target *mimc, uint64_t addr) +{ + return set_chiplet_id(addr, pdbg_target_index(mimc) + MC0_CHIPLET_ID); +} + +static struct mi p10_mi = { + .target = { + .name = "POWER10 mi", + .compatible = "ibm,power10-mi", + .class = "mi", + .translate = p10_mimc_translate, + }, +}; +DECLARE_HW_UNIT(p10_mi); + +static struct mc p10_mc = { + .target = { + .name = "POWER10 mc", + .compatible = "ibm,power10-mc", + .class = "mc", + .translate = p10_mimc_translate, + }, +}; +DECLARE_HW_UNIT(p10_mc); + +static uint64_t p10_mcc_translate(struct mcc *mcc, uint64_t addr) +{ + int chip_unitnum = pdbg_target_index(t(mcc)); + uint8_t offset = get_sat_offset(addr); + + addr = set_chiplet_id(addr, chip_unitnum/2 + MC0_CHIPLET_ID); + if (chip_unitnum % 2) { + switch (get_sat_id(addr)) { + case 0x4: + addr = set_sat_id(addr, 0x5); + break; + case 0x8: + addr = set_sat_id(addr, 0x9); + break; + case 0x0: + if (offset >= 0x22 && offset <= 0x2b) + addr = set_sat_offset(addr, offset + 0x10); + break; + case 0xd: + if (offset >= 0x00 && offset <= 0x1f) + addr = set_sat_offset(addr, offset + 0x20); + break; + } + } else { + switch (get_sat_id(addr)) { + case 0x5: + addr = set_sat_id(addr, 0x4); + break; + case 0x9: + addr = set_sat_id(addr, 0x8); + break; + case 0x0: + if (offset >= 0x32 && offset <= 0x3b) + addr = set_sat_offset(addr, offset - 0x10); + break; + case 0xd: + if (offset >= 0x20 && offset <= 0x3f) + addr = set_sat_offset(addr, offset - 0x20); + break; + } + } + + return addr; +} + +static struct mcc p10_mcc = { + .target = { + .name = "POWER10 mcc", + .compatible = "ibm,power10-mcc", + .class = "mcc", + .translate = translate_cast(p10_mcc_translate), + }, +}; +DECLARE_HW_UNIT(p10_mcc); + +static uint64_t p10_omic_translate(struct omic *omic, uint64_t addr) +{ + int chip_unitnum = pdbg_target_index(t(omic)); + int chiplet_id = get_chiplet_id(addr); + + if (chiplet_id >= PAU0_CHIPLET_ID && chiplet_id <= PAU3_CHIPLET_ID) { + if (chip_unitnum == 0 || chip_unitnum == 1) + addr = set_chiplet_id(addr, PAU0_CHIPLET_ID); + else if (chip_unitnum == 2 || chip_unitnum == 3) + addr = set_chiplet_id(addr, PAU2_CHIPLET_ID); + else if (chip_unitnum == 4 || chip_unitnum == 5) + addr = set_chiplet_id(addr, PAU1_CHIPLET_ID); + else if (chip_unitnum == 6 || chip_unitnum == 7) + addr = set_chiplet_id(addr, PAU3_CHIPLET_ID); + else + assert(0); + + if (chip_unitnum % 2) + addr = set_io_group_addr(addr, 0x3); + else + addr = set_io_group_addr(addr, 0x2); + } else { + addr = set_chiplet_id(addr, chip_unitnum/2 + MC0_CHIPLET_ID); + + if (chip_unitnum % 2) + addr = set_ring_id(addr, 0x6); + else + addr = set_ring_id(addr, 0x5); + } + + return addr; +} + +static struct omic p10_omic = { + .target = { + .name = "POWER10 omic", + .compatible = "ibm,power10-omic", + .class = "omic", + .translate = translate_cast(p10_omic_translate), + }, +}; +DECLARE_HW_UNIT(p10_omic); + +static uint64_t p10_omi_translate(struct omi *omi, uint64_t addr) +{ + int chip_unitnum = pdbg_target_index(t(omi)); + int chiplet_id = get_chiplet_id(addr); + + if (chiplet_id >= PAU0_CHIPLET_ID && chiplet_id <= PAU3_CHIPLET_ID) { + if (chip_unitnum >= 0 && chip_unitnum <= 3) + addr = set_chiplet_id(addr, PAU0_CHIPLET_ID); + else if (chip_unitnum >= 4 && chip_unitnum <= 7) + addr = set_chiplet_id(addr, PAU2_CHIPLET_ID); + else if (chip_unitnum >= 8 && chip_unitnum <= 11) + addr = set_chiplet_id(addr, PAU1_CHIPLET_ID); + else if (chip_unitnum >= 12 && chip_unitnum <= 15) + addr = set_chiplet_id(addr, PAU3_CHIPLET_ID); + else + assert(0); + + if (chip_unitnum % 2) + addr = set_io_lane(addr, 8 + get_io_lane(addr) % 8); + else + addr = set_io_lane(addr, get_io_lane(addr) % 8); + + if ((chip_unitnum / 2) % 2) + addr = set_io_group_addr(addr, 0x3); + else + addr = set_io_group_addr(addr, 0x2); + } else { + addr = set_chiplet_id(addr, chip_unitnum/4 + MC0_CHIPLET_ID); + + if (get_sat_offset(addr) >= 16 && get_sat_offset(addr) <= 47) { + if (chip_unitnum % 2) + addr = set_sat_offset(addr, 32 + get_sat_offset(addr) % 16); + else + addr = set_sat_offset(addr, 16 + get_sat_offset(addr) % 16); + } else { + if (chip_unitnum % 2) + addr = set_sat_offset(addr, 56 + get_sat_offset(addr) % 4); + else + addr = set_sat_offset(addr, 48 + get_sat_offset(addr) % 4); + } + + if ((chip_unitnum / 2) %2) + addr = set_ring_id(addr, 0x6); + else + addr = set_ring_id(addr, 0x5); + } + + return addr; +} + +static struct omi p10_omi = { + .target = { + .name = "POWER10 omi", + .compatible = "ibm,power10-omi", + .class = "omi", + .translate = translate_cast(p10_omi_translate), + }, +}; +DECLARE_HW_UNIT(p10_omi); + +static uint64_t p10_pauc_translate(struct pauc *pauc, uint64_t addr) +{ + return set_chiplet_id(addr, pdbg_target_index(t(pauc)) + PAU0_CHIPLET_ID); +} + +static struct pauc p10_pauc = { + .target = { + .name = "POWER10 pauc", + .compatible = "ibm,power10-pauc", + .class = "pauc", + .translate = translate_cast(p10_pauc_translate), + }, +}; +DECLARE_HW_UNIT(p10_pauc); + +static uint64_t p10_pau_translate(struct pau *pau, uint64_t addr) +{ + int chip_unitnum = pdbg_target_index(t(pau)); + + addr = set_chiplet_id(addr, chip_unitnum/2 + PAU0_CHIPLET_ID); + + switch (chip_unitnum) { + case 0: + case 3: + case 4: + case 6: + if (get_ring_id(addr) == 0x4) + addr = set_ring_id(addr, 0x2); + else if (get_ring_id(addr) == 0x5) + addr = set_ring_id(addr, 0x3); + break; + + case 1: + case 2: + case 5: + case 7: + if (get_ring_id(addr) == 0x2) + addr = set_ring_id(addr, 0x4); + else if (get_ring_id(addr) == 0x3) + addr = set_ring_id(addr, 0x5); + break; + } + + return addr; +} + +static struct pau p10_pau = { + .target = { + .name = "POWER10 pau", + .compatible = "ibm,power10-pau", + .class = "pau", + .translate = translate_cast(p10_pau_translate), + }, +}; +DECLARE_HW_UNIT(p10_pau); + +#define HEADER_CHECK_DATA ((uint64_t) 0xc0ffee03 << 32) + +static int p10_chiplet_getring(struct chiplet *chiplet, uint64_t ring_addr, int64_t ring_len, uint32_t result[]) +{ + uint64_t scan_type_addr; + uint64_t scan_data_addr; + uint64_t scan_header_addr; + uint64_t scan_type_data; + uint64_t set_pulse = 1; + uint64_t bits = 32; + uint64_t data; + + /* We skip the first word in the results so we can write it later as it + * should contain the header read out at the end */ + int i = 0; + + scan_type_addr = (ring_addr & 0x7fff0000) | 0x7; + scan_data_addr = (scan_type_addr & 0xffff0000) | 0x8000; + scan_header_addr = scan_data_addr & 0xffffe000; + + scan_type_data = (ring_addr & 0xfff0) << 13; + scan_type_data |= 0x800 >> (ring_addr & 0xf); + scan_type_data <<= 32; + + pib_write(&chiplet->target, scan_type_addr, scan_type_data); + pib_write(&chiplet->target, scan_header_addr, HEADER_CHECK_DATA); + + /* The final 32 bit read is the header which we do at the end */ + ring_len -= 32; + i = 1; + + while (ring_len > 0) { + ring_len -= bits; + if (set_pulse) { + scan_data_addr |= 0x4000; + set_pulse = 0; + } else + scan_data_addr &= ~0x4000ULL; + + scan_data_addr &= ~0xffull; + scan_data_addr |= bits; + pib_read(&chiplet->target, scan_data_addr, &data); + + /* Discard lower 32 bits */ + /* TODO: We always read 64-bits from the ring on P9 so we could + * optimise here by reading 64-bits at a time, but I'm not + * confident I've figured that out and 32-bits is what Hostboot + * does and seems to work. */ + data >>= 32; + + /* Left-align data */ + data <<= 32 - bits; + result[i++] = data; + if (ring_len > 0 && (ring_len < bits)) + bits = ring_len; + } + + pib_read(&chiplet->target, scan_header_addr | 0x20, &data); + data &= 0xffffffff00000000; + result[0] = data >> 32; + if (data != HEADER_CHECK_DATA) + printf("WARNING: Header check failed. Make sure you specified the right ring length!\n" + "Ring data is probably corrupt now.\n"); + + return 0; +} + +#define NET_CTRL0 0xf0040 +#define NET_CTRL0_CHIPLET_ENABLE PPC_BIT(0) +static int p10_chiplet_probe(struct pdbg_target *target) +{ + uint64_t value; + + if (pib_read(target, NET_CTRL0, &value)) + return -1; + + if (!(value & NET_CTRL0_CHIPLET_ENABLE)) + return -1; + + return 0; +} + +static uint64_t p10_chiplet_translate(struct chiplet *chiplet, uint64_t addr) +{ + return set_chiplet_id(addr, pdbg_target_index(t(chiplet))); +} + +static struct chiplet p10_chiplet = { + .target = { + .name = "POWER10 Chiplet", + .compatible = "ibm,power10-chiplet", + .class = "chiplet", + .probe = p10_chiplet_probe, + .translate = translate_cast(p10_chiplet_translate), + }, + .getring = p10_chiplet_getring, +}; +DECLARE_HW_UNIT(p10_chiplet); + +static int p10_thread_probe(struct pdbg_target *target) +{ + struct thread *thread = target_to_thread(target); + + thread->id = pdbg_target_index(target); + + return 0; +} + +static struct thread p10_thread = { + .target = { + .name = "POWER10 Thread", + .compatible = "ibm,power10-thread", + .class = "thread", + .probe = p10_thread_probe, + }, +}; +DECLARE_HW_UNIT(p10_thread); + +static uint64_t no_translate(struct pdbg_target *target, uint64_t addr) +{ + /* No translation performed */ + return 0; +} + +static struct fc p10_fc = { + .target = { + .name = "POWER10 Fused Core", + .compatible = "ibm,power10-fc", + .class = "fc", + .translate = no_translate, + }, +}; +DECLARE_HW_UNIT(p10_fc); + +__attribute__((constructor)) +static void register_p10_fapi_targets(void) +{ + pdbg_hwunit_register(PDBG_DEFAULT_BACKEND, &p10_eq_hw_unit); + pdbg_hwunit_register(PDBG_DEFAULT_BACKEND, &p10_core_hw_unit); + pdbg_hwunit_register(PDBG_DEFAULT_BACKEND, &p10_pec_hw_unit); + pdbg_hwunit_register(PDBG_DEFAULT_BACKEND, &p10_phb_hw_unit); + pdbg_hwunit_register(PDBG_DEFAULT_BACKEND, &p10_nmmu_hw_unit); + pdbg_hwunit_register(PDBG_DEFAULT_BACKEND, &p10_pau_hw_unit); + pdbg_hwunit_register(PDBG_DEFAULT_BACKEND, &p10_iohs_hw_unit); + pdbg_hwunit_register(PDBG_DEFAULT_BACKEND, &p10_mi_hw_unit); + pdbg_hwunit_register(PDBG_DEFAULT_BACKEND, &p10_mc_hw_unit); + pdbg_hwunit_register(PDBG_DEFAULT_BACKEND, &p10_mcc_hw_unit); + pdbg_hwunit_register(PDBG_DEFAULT_BACKEND, &p10_omic_hw_unit); + pdbg_hwunit_register(PDBG_DEFAULT_BACKEND, &p10_omi_hw_unit); + pdbg_hwunit_register(PDBG_DEFAULT_BACKEND, &p10_pauc_hw_unit); + pdbg_hwunit_register(PDBG_DEFAULT_BACKEND, &p10_pau_hw_unit); + pdbg_hwunit_register(PDBG_DEFAULT_BACKEND, &p10_chiplet_hw_unit); + pdbg_hwunit_register(PDBG_DEFAULT_BACKEND, &p10_thread_hw_unit); + pdbg_hwunit_register(PDBG_DEFAULT_BACKEND, &p10_fc_hw_unit); +} diff --git a/libpdbg/p10_scom_addr.h b/libpdbg/p10_scom_addr.h new file mode 100644 index 0000000..f307e46 --- /dev/null +++ b/libpdbg/p10_scom_addr.h @@ -0,0 +1,133 @@ +/* Copyright 2018 IBM Corp. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + * implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef LIBPDBG_SCOM_ADDR +#define LIBPDBG_SCOM_ADDR + +/* Helpers and defines from the ekb. See p10_scom_addr.H */ + +/* P10 Chiplet ID enumeration */ +enum { + PIB_CHIPLET_ID = 0x00, ///< PIB chiplet (FSI) + PERV_CHIPLET_ID = 0x01, ///< TP chiplet + + N0_CHIPLET_ID = 0x02, ///< Nest0 (North) chiplet + N1_CHIPLET_ID = 0x03, ///< Nest1 (South) chiplet + + PCI0_CHIPLET_ID = 0x08, ///< PCIe0 chiplet + PCI1_CHIPLET_ID = 0x09, ///< PCIe1 chiplet + + MC0_CHIPLET_ID = 0x0C, ///< MC0 chiplet + MC1_CHIPLET_ID = 0x0D, ///< MC1 chiplet + MC2_CHIPLET_ID = 0x0E, ///< MC2 chiplet + MC3_CHIPLET_ID = 0x0F, ///< MC3 chiplet + + PAU0_CHIPLET_ID = 0x10, ///< PAU0 chiplet + PAU1_CHIPLET_ID = 0x11, ///< PAU1 chiplet + PAU2_CHIPLET_ID = 0x12, ///< PAU2 chiplet + PAU3_CHIPLET_ID = 0x13, ///< PAU3 chiplet + + AXON0_CHIPLET_ID = 0x18, ///< AXON0 chiplet (high speed io) + AXON1_CHIPLET_ID = 0x19, ///< AXON1 chiplet (high speed io) + AXON2_CHIPLET_ID = 0x1A, ///< AXON2 chiplet (high speed io) + AXON3_CHIPLET_ID = 0x1B, ///< AXON3 chiplet (high speed io) + AXON4_CHIPLET_ID = 0x1C, ///< AXON4 chiplet (high speed io) + AXON5_CHIPLET_ID = 0x1D, ///< AXON5 chiplet (high speed io) + AXON6_CHIPLET_ID = 0x1E, ///< AXON6 chiplet (high speed io) + AXON7_CHIPLET_ID = 0x1F, ///< AXON7 chiplet (high speed io) + + EQ0_CHIPLET_ID = 0x20, ///< Quad0 chiplet (super chiplet) + EQ1_CHIPLET_ID = 0x21, ///< Quad1 chiplet (super chiplet) + EQ2_CHIPLET_ID = 0x22, ///< Quad2 chiplet (super chiplet) + EQ3_CHIPLET_ID = 0x23, ///< Quad3 chiplet (super chiplet) + EQ4_CHIPLET_ID = 0x24, ///< Quad4 chiplet (super chiplet) + EQ5_CHIPLET_ID = 0x25, ///< Quad5 chiplet (super chiplet) + EQ6_CHIPLET_ID = 0x26, ///< Quad6 chiplet (super chiplet) + EQ7_CHIPLET_ID = 0x27, ///< Quad7 chiplet (super chiplet) +}; + +/* Extract pervasive chiplet ID from SCOM address */ +static uint8_t get_chiplet_id(uint64_t addr) +{ + return ((addr >> 24) & 0x3F); +} + +/* Modify SCOM address to update pervasive chiplet ID */ +static uint64_t set_chiplet_id(uint64_t addr, uint8_t chiplet_id) +{ + addr &= 0xFFFFFFFFC0FFFFFFULL; + addr |= ((chiplet_id & 0x3F) << 24); + return addr; +} + +static uint8_t get_ring_id(uint64_t addr) +{ + return (addr >> 10) & 0xF; +} + +static uint64_t set_ring_id(uint64_t addr, uint64_t ring) +{ + addr &= 0xFFFFFFFFFFFF03FFULL; + addr |= ((ring & 0x3F) << 10); + return addr; +} + +static uint32_t get_io_lane(uint64_t addr) +{ + return (addr >> 32) & 0x1F; +} + +static uint64_t set_io_lane(uint64_t addr, uint64_t lane) +{ + addr &= 0xFFFFFFE0FFFFFFFFULL; + addr |= (lane & 0x1F) << 32; + return addr; +} + +static uint8_t get_sat_id(uint64_t addr) +{ + return ((addr >> 6) & 0xF); +} + +/* Modify SCOM address to update satellite ID field */ +static uint64_t set_sat_id(uint64_t addr, uint8_t sat_id) +{ + addr &= 0xFFFFFFFFFFFFFC3FULL; + addr |= ((sat_id & 0xF) << 6); + return addr; +} + +static uint8_t get_sat_offset(uint64_t addr) +{ + return addr & 0x3F; +} + +static uint64_t set_sat_offset(uint64_t addr, uint8_t sat_offset) +{ + addr &= 0xFFFFFFFFFFFFFFC0ULL; + addr |= (sat_offset & 0x3F); + return addr; +} + +static uint64_t set_io_group_addr(uint64_t addr, uint64_t group_addr) +{ + addr &= 0xFFFFFC1FFFFFFFFFULL; + addr |= (group_addr & 0x1F) << 37; + + return addr; +} + +#endif From patchwork Thu Oct 1 07:07:59 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Amitay Isaacs X-Patchwork-Id: 1374871 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4C245W1yClz9sVM for ; Thu, 1 Oct 2020 17:10:23 +1000 (AEST) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=ozlabs.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; secure) header.d=ozlabs.org header.i=@ozlabs.org header.a=rsa-sha256 header.s=201707 header.b=e0EBIurA; dkim-atps=neutral Received: from bilbo.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 4C245W0wgzzDqTn for ; Thu, 1 Oct 2020 17:10:23 +1000 (AEST) X-Original-To: pdbg@lists.ozlabs.org Delivered-To: pdbg@lists.ozlabs.org Received: from ozlabs.org (bilbo.ozlabs.org [IPv6:2401:3900:2:1::2]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 4C245M5HP8zDqTY for ; Thu, 1 Oct 2020 17:10:15 +1000 (AEST) Authentication-Results: lists.ozlabs.org; dmarc=pass (p=none dis=none) header.from=ozlabs.org Authentication-Results: lists.ozlabs.org; dkim=pass (2048-bit key; secure) header.d=ozlabs.org header.i=@ozlabs.org header.a=rsa-sha256 header.s=201707 header.b=e0EBIurA; dkim-atps=neutral Received: from authenticated.ozlabs.org (localhost [127.0.0.1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by mail.ozlabs.org (Postfix) with ESMTPSA id 4C2458543Zz9sVH; Thu, 1 Oct 2020 17:10:04 +1000 (AEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ozlabs.org; s=201707; t=1601536215; bh=Cvmx3Y8ORWGl2fR9SK8co9cPgvfsBjJ2PV+23YAGu8Q=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=e0EBIurAG3pgTRWpxJghwigJCxOhMoPO6uDRFalf0j64x4qVvYfqrKLVGgacdl2r5 UFi4YTdmEBn32YPZUIdFcVxnsoROSyF0RnOpSqAk19zztwLhl+TmYyi2jqBr7feTdu UgE/QICMW1ZRJBtxKaFjEwu3CxGtlMwUR2m90dj6VJ0pC2UGA/IY+5xG2C6Favvq3Z UfF+JWkp4vEfqZ7JFQeq673bLzUnIpguOkT2UUsEUvxhO2kSzsP9/820nRMTPdn6Mw 97wHarZTW2Cy+XF/bB9egzK27kVCRc1Hz81q57+ObUK5cyqej52uMVigvUAR5eGW+R p6+StKSu2148Q== From: Amitay Isaacs To: pdbg@lists.ozlabs.org Date: Thu, 1 Oct 2020 17:07:59 +1000 Message-Id: <20201001070814.102735-6-amitay@ozlabs.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201001070814.102735-1-amitay@ozlabs.org> References: <20201001070814.102735-1-amitay@ozlabs.org> MIME-Version: 1.0 Subject: [Pdbg] [PATCH v2 05/20] dts: Add p10 targets to device tree X-BeenThere: pdbg@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: "mailing list for https://github.com/open-power/pdbg development" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Amitay Isaacs Errors-To: pdbg-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Pdbg" From: Alistair Popple Signed-off-by: Alistair Popple Signed-off-by: Amitay Isaacs Reviewed-by: Joel Stanley --- p10.dts.m4 | 782 +++++++++++++++++++++++++---------------------------- 1 file changed, 365 insertions(+), 417 deletions(-) diff --git a/p10.dts.m4 b/p10.dts.m4 index aee608f..76bbc4d 100644 --- a/p10.dts.m4 +++ b/p10.dts.m4 @@ -16,8 +16,9 @@ dnl dnl CORE([index]) dnl define(`CORE', -` - core@0 { +` define(`id', eval(`0x$1 % 2'))dnl + + CONCAT(core@, id) { #address-cells = <0x01>; #size-cells = <0x00>; reg = <0x00 0x00 0xfffff>; @@ -76,21 +77,193 @@ define(`addr', CONCAT(chiplet_id, 000000))dnl ')dnl dnl -dnl EX_([eq_index, ex_index]) +dnl FC_([index]) dnl -define(`EX_', +define(`FC_', `define(`chiplet_id', CONCAT(1, $1))dnl define(`addr', CONCAT(chiplet_id, 000000))dnl - ex@$2 { + fc@$1 { #address-cells = <0x02>; #size-cells = <0x01>; reg = <0x00 CONCAT(0x,addr) 0xfffff>; - compatible = "ibm,power10-ex"; - index = <$2>; + compatible = "ibm,power10-fc"; + index = <$1>; + +')dnl + +dnl +dnl PAUC_([chiplet], [index]) +dnl +define(`PAUC_', +`define(`chiplet_id', $1)dnl +define(`addr', CONCAT(chiplet_id, 000000))dnl + pauc@$2 { + #address-cells = <0x02>; + #size-cells = <0x01>; + reg = <0x00 CONCAT(0x,addr) 0xfffff>; + compatible = "ibm,power10-pauc"; + index = <$2>; ')dnl +dnl +dnl PAU([chiplet], [index]) +dnl +define(`PAU', +`define(`chiplet_id', $1)dnl +define(`addr', CONCAT(chiplet_id, 000000))dnl + + pau@$2 { + #address-cells = <0x02>; + #size-cells = <0x01>; + reg = <0x00 CONCAT(0x,addr) 0xfffff>; + compatible = "ibm,power10-pau"; + index = <$2>; + }; +') + +dnl +dnl IOHS([chiplet], [index]) +dnl +define(`IOHS', +`define(`chiplet_id', $1)dnl +define(`addr', CONCAT(chiplet_id, 000000))dnl + + iohs@$2 { + #address-cells = <0x02>; + #size-cells = <0x01>; + reg = <0x00 CONCAT(0x,addr) 0xfffff>; + compatible = "ibm,power10-iohs"; + index = <$2>; + }; +') + +dnl +dnl MI_([chiplet], [index]) +dnl +define(`MI_', +`define(`chiplet_id', $1)dnl +define(`addr', CONCAT(chiplet_id, 000000))dnl + + mi@$2 { + #address-cells = <0x02>; + #size-cells = <0x01>; + reg = <0x00 CONCAT(0x,addr) 0xfffff>; + compatible = "ibm,power10-mi"; + index = <$2>; +') + +dnl +dnl MC_([chiplet], [index]) +dnl +define(`MC_', +`define(`chiplet_id', $1)dnl +define(`addr', CONCAT(chiplet_id, 000000))dnl + + mc@$2 { + #address-cells = <0x02>; + #size-cells = <0x01>; + reg = <0x00 CONCAT(0x,addr) 0xfffff>; + compatible = "ibm,power10-mc"; + index = <0x$2>; +') + +dnl +dnl MCC_([chiplet], [index]) +dnl +define(`MCC_', +`define(`chiplet_id', $1)dnl +define(`addr', CONCAT(chiplet_id, 000000))dnl +define(`id', eval(`$2 % 2'))dnl + + CONCAT(mcc@, id) { + #address-cells = <0x02>; + #size-cells = <0x01>; + reg = <0x00 CONCAT(0x,addr) 0xfffff>; + compatible = "ibm,power10-mcc"; + index = <$2>; +') + +dnl +dnl OMIC([chiplet], [index]) +dnl +define(`OMIC', +`define(`chiplet_id', $1)dnl +define(`addr', CONCAT(chiplet_id, 000000))dnl + + omic@$2 { + #address-cells = <0x02>; + #size-cells = <0x01>; + reg = <0x00 CONCAT(0x,addr) 0xfffff>; + compatible = "ibm,power10-omic"; + index = <$2>; + }; +') + +dnl +dnl OMI_([chiplet], [index]) +dnl +define(`OMI_', +`define(`chiplet_id', $1)dnl +define(`addr', CONCAT(chiplet_id, 000000))dnl +define(`id', eval(`$2 % 2'))dnl + + CONCAT(omi@, id) { + #address-cells = <0x02>; + #size-cells = <0x01>; + reg = <0x00 CONCAT(0x,addr) 0xfffff>; + compatible = "ibm,power10-omi"; + index = <$2>; +') + +dnl +dnl PEC_([chiplet], [index]) +dnl +define(`PEC_', +`define(`chiplet_id', $1)dnl +define(`addr', CONCAT(chiplet_id, 000000))dnl + + pec@$2 { + #address-cells = <0x02>; + #size-cells = <0x01>; + reg = <0x00 CONCAT(0x,addr) 0xfffff>; + compatible = "ibm,power10-pec"; + index = <$2>; +') + +dnl +dnl PHB([chiplet], [index]) +dnl +define(`PHB', +`define(`chiplet_id', $1)dnl +define(`addr', CONCAT(chiplet_id, 000000))dnl +define(`id', eval(`$2 % 3'))dnl + + CONCAT(phb@,id) { + #address-cells = <0x02>; + #size-cells = <0x01>; + reg = <0x00 CONCAT(0x,addr) 0xfffff>; + compatible = "ibm,power10-phb"; + index = <$2>; + }; +') + +dnl +dnl NMMU([chiplet], [index]) +dnl +define(`NMMU', +`define(`chiplet_id', $1)dnl +define(`addr', CONCAT(chiplet_id, 000000))dnl + + nmmu@$2 { + reg = <0x00 CONCAT(0x,addr) 0xfffff>; + compatible = "ibm,power10-nmmu"; + index = <$2>; + }; +') + +dnl dnl dnl CHIP([index]) dnl @@ -139,501 +312,276 @@ define(`CHIP', }; }; - CHIPLET__(2) - n0 { - compatible = "ibm,power10-nest"; - index = < 0x00 >; - - capp0 { - compatible = "ibm,power10-capp"; - index = < 0x00 >; - }; - }; + CHIPLET_(2) + NMMU(2,0) }; - CHIPLET__(3) - n1 { - compatible = "ibm,power10-nest"; - index = < 0x01 >; - - mcs2 { - compatible = "ibm,power10-mcs"; - index = < 0x02 >; - }; + CHIPLET_(3) + NMMU(3,1) + }; - mcs3 { - compatible = "ibm,power10-mcs"; - index = < 0x03 >; - }; + CHIPLET_(8) + PEC_(8,0) + PHB(8,0) + PHB(8,1) + PHB(8,2) }; }; - CHIPLET__(4) - n2 { - compatible = "ibm,power10-nest"; - index = < 0x02 >; - - capp1 { - compatible = "ibm,power10-capp"; - index = < 0x01 >; - }; + CHIPLET_(9) + PEC_(9,1) + PHB(9,3) + PHB(9,4) + PHB(9,5) }; }; - CHIPLET__(5) - n3 { - compatible = "ibm,power10-nest"; - index = < 0x03 >; - - mcs0 { - compatible = "ibm,power10-mcs"; - index = < 0x00 >; - }; - - mcs1 { - compatible = "ibm,power10-mcs"; - index = < 0x01 >; + CHIPLET_(c) + MC_(c,0) + MI_(c,0) + MCC_(c,0) + OMI_(c,0) + }; + OMI_(c,1) + }; + }; + MCC_(c,1) + OMI_(c,2) + }; + OMI_(c,3) + }; + }; }; + OMIC(c,0) + OMIC(c,1) }; }; - CHIPLET_(6) - xbus$1_0: xbus@0 { - compatible = "ibm,power10-xbus"; - index = < 0x01 >; - reg = < 0x00 0x6000000 0xfffff >; + CHIPLET_(d) + MC_(d,1) + MI_(d,1) + MCC_(d,2) + OMI_(d,4) + }; + OMI_(d,5) + }; + }; + MCC_(d,3) + OMI_(d,6) + }; + OMI_(d,7) + }; + }; + }; + OMIC(d,2) + OMIC(d,3) }; }; - CHIPLET_(7) - mc@0 { - reg = < 0x00 0x7000000 0xfffff >; - compatible = "ibm,power10-mc"; - index = < 0x00 >; - - mca0 { - compatible = "ibm,power10-mca"; - index = < 0x00 >; - }; - - mca1 { - compatible = "ibm,power10-mca"; - index = < 0x01 >; - }; - - mca2 { - compatible = "ibm,power10-mca"; - index = < 0x02 >; - }; - - mca3 { - compatible = "ibm,power10-mca"; - index = < 0x03 >; - }; - - mcbist { - compatible = "ibm,power10-mcbist"; - index = < 0x00 >; + CHIPLET_(e) + MC_(e,2) + MI_(e,2) + MCC_(e,4) + OMI_(e,8) + }; + OMI_(e,9) + }; + }; + MCC_(e,5) + OMI_(e,10) + }; + OMI_(e,11) + }; + }; }; + OMIC(e,4) + OMIC(e,5) }; }; - CHIPLET_(8) - mc@1 { - reg = < 0x00 0x8000000 0xfffff >; - compatible = "ibm,power10-mc"; - index = < 0x01 >; - - mca0 { - compatible = "ibm,power10-mca"; - index = < 0x04 >; - }; - - mca1 { - compatible = "ibm,power10-mca"; - index = < 0x05 >; - }; - - mca2 { - compatible = "ibm,power10-mca"; - index = < 0x06 >; - }; - - mca3 { - compatible = "ibm,power10-mca"; - index = < 0x07 >; - }; - - mcbist { - compatible = "ibm,power10-mcbist"; - index = < 0x01 >; + CHIPLET_(f) + MC_(f,3) + MI_(f,3) + MCC_(f,6) + OMI_(f,12) + }; + OMI_(f,13) + }; + }; + MCC_(f,7) + OMI_(f,14) + }; + OMI_(f,15) + }; + }; }; + OMIC(f,6) + OMIC(f,7) }; }; - CHIPLET_(9) - obus@0 { - reg = < 0x00 0x9000000 0xfffff >; - compatible = "ibm,power10-obus"; - index = < 0x00 >; - }; - - obrick0 { - compatible = "ibm,power10-obus_brick"; - index = < 0x00 >; - }; - - obrick1 { - compatible = "ibm,power10-obus_brick"; - index = < 0x01 >; - }; - - obrick2 { - compatible = "ibm,power10-obus_brick"; - index = < 0x02 >; + CHIPLET_(10) + PAUC_(10,0) + PAU(10,0) }; }; - CHIPLET_(c) - obus@3 { - reg = < 0x00 0xc000000 0xfffff >; - compatible = "ibm,power10-obus"; - index = < 0x03 >; - }; - - obrick0 { - compatible = "ibm,power10-obus_brick"; - index = < 0x09 >; - }; - - obrick1 { - compatible = "ibm,power10-obus_brick"; - index = < 0x0a >; + CHIPLET_(11) + PAUC_(11,1) + PAU(11,3) }; + }; - obrick2 { - compatible = "ibm,power10-obus_brick"; - index = < 0x0b >; + CHIPLET_(12) + PAUC_(12,2) + PAU(12,4) + PAU(12,5) }; }; - CHIPLET_(d) - pec@d000000 { - reg = < 0x00 0xd000000 0xfffff >; - compatible = "ibm,power10-pec"; - index = < 0x00 >; + CHIPLET_(13) + PAUC_(13,3) + PAU(13,6) + PAU(13,7) }; + }; - phb0 { - compatible = "ibm,power10-phb"; - index = < 0x00 >; - }; + CHIPLET_(18) + IOHS(18,0) + }; - phb1 { - compatible = "ibm,power10-phb"; - index = < 0x01 >; - }; + CHIPLET_(19) + IOHS(19,1) }; - CHIPLET_(e) - pec@e000000 { - reg = < 0x00 0xe000000 0xfffff >; - compatible = "ibm,power10-pec"; - index = < 0x01 >; - }; + CHIPLET_(1a) + IOHS(1a,2) + }; - phb0 { - compatible = "ibm,power10-phb"; - index = < 0x02 >; - }; + CHIPLET_(1b) + IOHS(1b,3) + }; - phb1 { - compatible = "ibm,power10-phb"; - index = < 0x03 >; - }; + CHIPLET_(1c) + IOHS(1c,4) }; - CHIPLET_(f) - pec@f000000 { - reg = < 0x00 0xf000000 0xfffff >; - compatible = "ibm,power10-pec"; - index = < 0x02 >; - }; + CHIPLET_(1d) + IOHS(1d,5) + }; - phb0 { - compatible = "ibm,power10-phb"; - index = < 0x04 >; - }; + CHIPLET_(1e) + IOHS(1e,6) + }; - phb1 { - compatible = "ibm,power10-phb"; - index = < 0x05 >; - }; + CHIPLET_(1f) + IOHS(1f,7) }; - CHIPLET_(10) + CHIPLET_(20) EQ_(0) - EX_(0,0) - CHIPLET_(20) - CORE(00) - }; - - CHIPLET_(21) - CORE(01) - }; + FC_(0) + CORE(0) + CORE(1) }; - - EX_(0,1) - CHIPLET_(22) - CORE(02) - }; - - CHIPLET_(23) - CORE(03) - }; + FC_(1) + CORE(2) + CORE(3) }; }; }; - CHIPLET_(11) + CHIPLET_(21) EQ_(1) - EX_(1,0) - CHIPLET_(24) - CORE(04) - }; - - CHIPLET_(25) - CORE(05) - }; + FC_(0) + CORE(4) + CORE(5) }; - - EX_(1,1) - CHIPLET_(26) - CORE(06) - }; - - CHIPLET_(27) - CORE(07) - }; + FC_(1) + CORE(6) + CORE(7) }; }; }; - CHIPLET_(12) + CHIPLET_(22) EQ_(2) - EX_(2,0) - CHIPLET_(28) - CORE(08) - }; - - CHIPLET_(29) - CORE(09) - }; + FC_(0) + CORE(8) + CORE(9) }; - - EX_(2,1) - CHIPLET_(2a) - CORE(0a) - }; - - CHIPLET_(2b) - CORE(0b) - }; + FC_(1) + CORE(a) + CORE(b) }; }; }; - CHIPLET_(13) + CHIPLET_(23) EQ_(3) - EX_(3,0) - CHIPLET_(2c) - CORE(0c) - }; - - CHIPLET_(2d) - CORE(0d) - }; + FC_(0) + CORE(c) + CORE(d) }; - - EX_(3,1) - CHIPLET_(2e) - CORE(0e) - }; - - CHIPLET_(2f) - CORE(0f) - }; + FC_(1) + CORE(e) + CORE(f) }; }; }; - CHIPLET_(14) + CHIPLET_(24) EQ_(4) - EX_(4,0) - CHIPLET_(30) - CORE(10) - }; - - CHIPLET_(31) - CORE(11) - }; + FC_(0) + CORE(10) + CORE(11) }; - - EX_(4,1) - CHIPLET_(32) - CORE(12) - }; - - CHIPLET_(33) - CORE(13) - }; + FC_(1) + CORE(12) + CORE(13) }; }; }; - CHIPLET_(15) + CHIPLET_(25) EQ_(5) - EX_(5,0) - CHIPLET_(34) - CORE(14) - }; - - CHIPLET_(35) - CORE(15) - }; + FC_(0) + CORE(14) + CORE(15) }; - - EX_(5,1) - CHIPLET_(36) - CORE(16) - }; - - CHIPLET_(37) - CORE(17) - }; + FC_(1) + CORE(16) + CORE(17) }; }; }; - nv0 { - compatible = "ibm,power10-nv"; - index = < 0x00 >; - }; - - nv1 { - compatible = "ibm,power10-nv"; - index = < 0x01 >; - }; - - nv2 { - compatible = "ibm,power10-nv"; - index = < 0x02 >; - }; - - nv3 { - compatible = "ibm,power10-nv"; - index = < 0x03 >; - }; - - nv4 { - compatible = "ibm,power10-nv"; - index = < 0x04 >; - }; - - nv5 { - compatible = "ibm,power10-nv"; - index = < 0x05 >; - }; - - occ0 { - compatible = "ibm,power10-occ"; - index = < 0x00 >; - }; - - sbe0 { - compatible = "ibm,power10-sbe"; - index = < 0x00 >; - }; - - ppe0 { - compatible = "ibm,power10-ppe"; - index = < 0x00 >; - }; - - ppe1 { - compatible = "ibm,power10-ppe"; - index = < 0x0a >; - }; - - ppe2 { - compatible = "ibm,power10-ppe"; - index = < 0x0d >; - }; - - ppe3 { - compatible = "ibm,power10-ppe"; - index = < 0x14 >; - }; - - ppe4 { - compatible = "ibm,power10-ppe"; - index = < 0x19 >; - }; - - ppe5 { - compatible = "ibm,power10-ppe"; - index = < 0x1e >; - }; - - ppe6 { - compatible = "ibm,power10-ppe"; - index = < 0x28 >; - }; - - ppe7 { - compatible = "ibm,power10-ppe"; - index = < 0x29 >; - }; - - ppe8 { - compatible = "ibm,power10-ppe"; - index = < 0x2a >; - }; - - ppe9 { - compatible = "ibm,power10-ppe"; - index = < 0x2b >; - }; - - ppe10 { - compatible = "ibm,power10-ppe"; - index = < 0x2c >; - }; - - ppe11 { - compatible = "ibm,power10-ppe"; - index = < 0x2d >; - }; - - ppe12 { - compatible = "ibm,power10-ppe"; - index = < 0x2e >; - }; - - ppe13 { - compatible = "ibm,power10-ppe"; - index = < 0x32 >; + CHIPLET_(26) + EQ_(6) + FC_(0) + CORE(18) + CORE(19) + }; + FC_(1) + CORE(1a) + CORE(1b) + }; + }; }; - ppe14 { - compatible = "ibm,power10-ppe"; - index = < 0x34 >; + CHIPLET_(27) + EQ_(7) + FC_(0) + CORE(1c) + CORE(1d) + }; + FC_(1) + CORE(1e) + CORE(1f) + }; + }; }; - ppe15 { - compatible = "ibm,power10-ppe"; - index = < 0x38 >; - }; }; }; ')dnl From patchwork Thu Oct 1 07:08:00 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Amitay Isaacs X-Patchwork-Id: 1374872 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [203.11.71.2]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4C246d44pLz9sVN for ; Thu, 1 Oct 2020 17:11:21 +1000 (AEST) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=ozlabs.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; secure) header.d=ozlabs.org header.i=@ozlabs.org header.a=rsa-sha256 header.s=201707 header.b=evVzKa5J; dkim-atps=neutral Received: from bilbo.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 4C246d2h7MzDqTF for ; Thu, 1 Oct 2020 17:11:21 +1000 (AEST) X-Original-To: pdbg@lists.ozlabs.org Delivered-To: pdbg@lists.ozlabs.org Received: from ozlabs.org (bilbo.ozlabs.org [IPv6:2401:3900:2:1::2]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 4C246W3pcLzDqQt for ; Thu, 1 Oct 2020 17:11:15 +1000 (AEST) Authentication-Results: lists.ozlabs.org; dmarc=pass (p=none dis=none) header.from=ozlabs.org Authentication-Results: lists.ozlabs.org; dkim=pass (2048-bit key; secure) header.d=ozlabs.org header.i=@ozlabs.org header.a=rsa-sha256 header.s=201707 header.b=evVzKa5J; dkim-atps=neutral Received: from authenticated.ozlabs.org (localhost [127.0.0.1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by mail.ozlabs.org (Postfix) with ESMTPSA id 4C245N2wSNz9sVL; Thu, 1 Oct 2020 17:10:16 +1000 (AEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ozlabs.org; s=201707; t=1601536275; bh=ScJrdRsIxnBIs6EUArOqWXnkuaflUKjHJ/AGxqh9KZo=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=evVzKa5J9wuSG7OOUlTFiju8z0oBcxMbkM6WGpnCmXNmI7R3Pnfcs5UZgYNvlWRi3 jQ4Y/3ADkqpyUZ4NE6tADNzDigVo8Rrhl52TJ0313CNoq8g0dQha57wzT2DkEV25wY B8hbHBCgDj10CMpqLlTayywa+YACGfRpj72RcS0p2fqjNMFnYvECOXWUJhnlEngdfd zX4hXSFpMg540R1MFck8tGqSifLWSwEO5Edp/Q9NLHN5tWOUNvwSEkd6OLINzqruPk CHuPXPpiymIimZWo4oNCgkvFkzh4GeT8rE1zz8weJ+WoxceC86OKHUGLMIJtzMcfz0 6nUjP6RDGtYGQ== From: Amitay Isaacs To: pdbg@lists.ozlabs.org Date: Thu, 1 Oct 2020 17:08:00 +1000 Message-Id: <20201001070814.102735-7-amitay@ozlabs.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201001070814.102735-1-amitay@ozlabs.org> References: <20201001070814.102735-1-amitay@ozlabs.org> MIME-Version: 1.0 Subject: [Pdbg] [PATCH v2 06/20] tests: Import P10 SCOM HWP for address translation tests X-BeenThere: pdbg@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: "mailing list for https://github.com/open-power/pdbg development" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Amitay Isaacs Errors-To: pdbg-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Pdbg" Signed-off-by: Amitay Isaacs Reviewed-by: Joel Stanley --- src/tests/p10_cu.H | 102 +++++ src/tests/p10_scom_addr.C | 916 ++++++++++++++++++++++++++++++++++++++ src/tests/p10_scom_addr.H | 700 +++++++++++++++++++++++++++++ src/tests/p10_scominfo.C | 838 ++++++++++++++++++++++++++++++++++ src/tests/p10_scominfo.H | 89 ++++ 5 files changed, 2645 insertions(+) create mode 100644 src/tests/p10_cu.H create mode 100644 src/tests/p10_scom_addr.C create mode 100644 src/tests/p10_scom_addr.H create mode 100644 src/tests/p10_scominfo.C create mode 100644 src/tests/p10_scominfo.H diff --git a/src/tests/p10_cu.H b/src/tests/p10_cu.H new file mode 100644 index 0000000..3577f41 --- /dev/null +++ b/src/tests/p10_cu.H @@ -0,0 +1,102 @@ +/// +/// @file p10_cu.H +/// @brief P10 chip unit definitions +/// +/// HWP Owner: thi@us.ibm.com +/// HWP Team: NEST +/// HWP Level: 1 +/// HWP Consumed by: FSP/HB +/// + +#ifndef P10_CU_H +#define P10_CU_H + +// includes +#include + +extern "C" +{ + + /// P10 chip unit type enumeration + typedef enum + { + P10_NO_CU = 0, ///< P10 chip + PU_PERV_CHIPUNIT = 1, ///< Pervasive + PU_EQ_CHIPUNIT = 2, ///< Quad + PU_C_CHIPUNIT = 3, ///< Core + PU_PEC_CHIPUNIT = 4, ///< PCIe (PEC) + PU_PHB_CHIPUNIT = 5, ///< PCIe (PHB) + PU_NMMU_CHIPUNIT = 6, ///< NMMU + PU_IOHS_CHIPUNIT = 7, ///< IOHS (High speed IO) + PU_MC_CHIPUNIT = 8, ///< MC + PU_MI_CHIPUNIT = 9, ///< MI + PU_MCC_CHIPUNIT = 10, ///< MCC + PU_OMI_CHIPUNIT = 11, ///< OMI + PU_OMIC_CHIPUNIT = 12, ///< OMIC + PU_PAU_CHIPUNIT = 13, ///< PAU + PU_PAUC_CHIPUNIT = 14, ///< PAUC + NONE = 0xFF, ///< None/Invalid + } p10ChipUnits_t; + + /// P10 chip unit pairing struct + struct p10_chipUnitPairing_t + { + /// @brief Default constructor + p10_chipUnitPairing_t() + : chipUnitType(NONE), chipUnitNum(0) {} + /// @brief Construct from type/instance number + p10_chipUnitPairing_t (p10ChipUnits_t type, uint32_t num) + : chipUnitType(type), chipUnitNum(num) {} + + p10ChipUnits_t chipUnitType; ///< chip unit type + uint32_t chipUnitNum; ///< chip unit instance number + }; + + struct p10_chipUnitDescription_t + { + const char* strVal; // Chip unit string + const p10ChipUnits_t enumVal; // Chip unit enum value + const uint8_t maxChipUnitNum; // Max Chip unit num value + }; + + + // Max chip unit positions + const uint8_t MAX_PU_CHIPUNIT_NUM = 0; // P10_NO_CU + const uint8_t MAX_PU_EQ_CHIPUNIT_NUM = 7; + const uint8_t MAX_PU_C_CHIPUNIT_NUM = 31; + const uint8_t MAX_PU_PEC_CHIPUNIT_NUM = 1; + const uint8_t MAX_PU_PHB_CHIPUNIT_NUM = 5; + const uint8_t MAX_PU_NMMU_CHIPUNIT_NUM = 1; + const uint8_t MAX_PU_PERV_CHIPUNIT_NUM = 39; // Special case, with gaps + const uint8_t MAX_PU_IOHS_CHIPUNIT_NUM = 7; + const uint8_t MAX_PU_PAU_CHIPUNIT_NUM = 7; + const uint8_t MAX_PU_MC_CHIPUNIT_NUM = 3; + const uint8_t MAX_PU_MI_CHIPUNIT_NUM = 3; + const uint8_t MAX_PU_MCC_CHIPUNIT_NUM = 7; + const uint8_t MAX_PU_OMIC_CHIPUNIT_NUM = 7; + const uint8_t MAX_PU_OMI_CHIPUNIT_NUM = 15; + const uint8_t MAX_PU_PAUC_CHIPUNIT_NUM = 3; + + // Chip unit string/enum/max targes table + const p10_chipUnitDescription_t ChipUnitDescriptionTable[] = + { + { "pu" , P10_NO_CU, MAX_PU_CHIPUNIT_NUM }, + { "eq" , PU_EQ_CHIPUNIT, MAX_PU_EQ_CHIPUNIT_NUM }, + { "c" , PU_C_CHIPUNIT, MAX_PU_C_CHIPUNIT_NUM }, + { "pec" , PU_PEC_CHIPUNIT, MAX_PU_PEC_CHIPUNIT_NUM }, + { "phb" , PU_PHB_CHIPUNIT, MAX_PU_PHB_CHIPUNIT_NUM }, + { "nmmu" , PU_NMMU_CHIPUNIT, MAX_PU_NMMU_CHIPUNIT_NUM }, + { "perv" , PU_PERV_CHIPUNIT, MAX_PU_PERV_CHIPUNIT_NUM }, // Special case, with gaps + { "iohs" , PU_IOHS_CHIPUNIT, MAX_PU_IOHS_CHIPUNIT_NUM }, + { "mc" , PU_MC_CHIPUNIT, MAX_PU_MC_CHIPUNIT_NUM }, + { "mi" , PU_MI_CHIPUNIT, MAX_PU_MI_CHIPUNIT_NUM }, + { "mcc" , PU_MCC_CHIPUNIT, MAX_PU_MCC_CHIPUNIT_NUM }, + { "omi" , PU_OMI_CHIPUNIT, MAX_PU_OMI_CHIPUNIT_NUM }, + { "omic" , PU_OMIC_CHIPUNIT, MAX_PU_OMIC_CHIPUNIT_NUM }, + { "pau" , PU_PAU_CHIPUNIT, MAX_PU_PAU_CHIPUNIT_NUM }, + { "pauc" , PU_PAUC_CHIPUNIT, MAX_PU_PAUC_CHIPUNIT_NUM }, + }; + +} // extern "C" + +#endif /* P10_CU_H */ diff --git a/src/tests/p10_scom_addr.C b/src/tests/p10_scom_addr.C new file mode 100644 index 0000000..507c5a0 --- /dev/null +++ b/src/tests/p10_scom_addr.C @@ -0,0 +1,916 @@ +/// +/// @file p10_scom_addr.C +/// @brief P10 chip unit SCOM address platform translation code +/// +/// HWP HW Maintainer: Thi Tran +/// HWP FW Maintainer: +/// HWP Consumed by: Cronus, HB, HWSV +/// + +// includes +#include "p10_scom_addr.H" + +#define P10_SCOM_ADDR_C + +extern "C" +{ + /// See function description in header file + + // ##################################### + bool p10_scom_addr::isEqTarget() + { + bool l_eqTarget = false; + + // Must have EQ chiplet ID + if ( (getChipletId() >= EQ0_CHIPLET_ID) && + (getChipletId() <= EQ7_CHIPLET_ID) ) + { + // If endpoint is QME (0xE): + // QME per core (bit 20) must be 0 + // region select (bits 16:19) must be 0 + if ( (getEndpoint() == QME_ENDPOINT) && (!getQMEPerCore()) && + (getRegionSelect() == EQ_REGION_SEL) ) + { + l_eqTarget = true; + } + // associate perv target resources with EQ + else if (isPervTarget()) + { + l_eqTarget = true; + } + } + + return l_eqTarget; + } + + // ######################################## + uint8_t p10_scom_addr::getEqTargetInstance() + { + uint8_t l_instance = 0; + l_instance = (getChipletId() - EQ0_CHIPLET_ID); + return l_instance; + } + + // ##################################### + bool p10_scom_addr::isCoreTarget() + { + bool l_coreTarget = false; + + // Must have EQ chiplet ID + if ( (getChipletId() >= EQ0_CHIPLET_ID) && + (getChipletId() <= EQ7_CHIPLET_ID) ) + { + // Region select must be... + if ( (getRegionSelect() == MULTI_HOT_SELECT_C0) || // 0x8 + (getRegionSelect() == MULTI_HOT_SELECT_C1) || // 0x4 + (getRegionSelect() == MULTI_HOT_SELECT_C2) || // 0x2 + (getRegionSelect() == MULTI_HOT_SELECT_C3) || // 0x1 + (getRegionSelect() == EQ_REGION_SEL) ) // 0x0 + { + // If QME endpoint (0xE), QME per core (bit 20) must be 1 + if ( (getEndpoint() == QME_ENDPOINT) && getQMEPerCore() ) + { + l_coreTarget = true; + } + // or must be PSCOM endpoints -- ensure that ring ID is + // associated with a core resource on the first PSCOM + // endpoint (0x1), all are core rings on the second + // PSCOM endpoint (0x2) + else if ( ((getEndpoint() == PSCOM_ENDPOINT) && // 0x1 + ((getEQRingId() != PERV_RING_ID) && // 0x1 + (getEQRingId() != QME_RING_ID))) || // 0x2 + (getEndpoint() == PSCOM_2_ENDPOINT) ) // 0x2 + { + l_coreTarget = true; + } + } + } + + return l_coreTarget; + } + + // ##################################### + uint8_t p10_scom_addr::getCoreTargetInstance() + { + uint8_t l_instance = 0; + + // First core instance of the quad + l_instance = (getChipletId() - EQ0_CHIPLET_ID) * NUM_CORES_PER_EQ; + + // Get core instance based on region select + if (getRegionSelect() == MULTI_HOT_SELECT_C3) + { + l_instance += 3; + } + else if (getRegionSelect() == MULTI_HOT_SELECT_C2) + { + l_instance += 2; + } + else if (getRegionSelect() == MULTI_HOT_SELECT_C1) + { + l_instance += 1; + } + + return l_instance; + } + + // ##################################### + bool p10_scom_addr::isPecTarget() + { + bool l_pecTarget = false; + + // associate perv target resources with PCIE + if ( (getChipletId() >= PCI0_CHIPLET_ID) && // 0x8 + (getChipletId() <= PCI1_CHIPLET_ID) ) // 0x9 + { + l_pecTarget = isPervTarget(); + } + + // Endpoint must be PSCOM (0x1) + if (getEndpoint() == PSCOM_ENDPOINT) // 0x1 + { + // For PEC addresses via NEST regions: + // Ring ID must be 0x6, sat ID must be 0 + if ( (getChipletId() >= N0_CHIPLET_ID) && // 0x2 + (getChipletId() <= N1_CHIPLET_ID) && // 0x3 + (getRingId() == N0_PE1_RING_ID) && // 0x6 + (getSatId() == PEC_SAT_ID) ) // 0x0 + + { + l_pecTarget = true; + } + // For PEC addresses via PCIE: + else if ( (getChipletId() >= PCI0_CHIPLET_ID) && // 0x8 + (getChipletId() <= PCI1_CHIPLET_ID) ) // 0x9 + { + // Ring IDs must be 0x4-0x5 (iopci rings) or + // Ring ID is 0x2 (pci ring) and sat Id = 0x0 + if ( (getRingId() == IO_PCI0_RING_ID) || // 0x4 + (getRingId() == IO_PCI1_RING_ID) || // 0x5 + ((getRingId() == PCI_RING_ID) && // 0x2 + (getSatId() == PEC_SAT_ID)) ) // 0x0 + { + l_pecTarget = true; + } + } + } + + return l_pecTarget; + } + + // ##################################### + uint8_t p10_scom_addr::getPecTargetInstance() + { + uint8_t l_instance = 0; + + // PEC addresses via NEST regions + l_instance = N1_CHIPLET_ID - getChipletId(); + + // PEC addresses via PCIE + if ( (getChipletId() == PCI0_CHIPLET_ID) || + (getChipletId() == PCI1_CHIPLET_ID) ) + { + l_instance = getChipletId() - PCI0_CHIPLET_ID; + } + + return l_instance; + } + + // ##################################### + bool p10_scom_addr::isPhbTarget() + { + bool l_phbTarget = false; + + // Endpoint must be PSCOM (0x1) + if ( (getEndpoint() == PSCOM_ENDPOINT) ) // 0x1 + { + // PCIE chiplet ID + if ( (getChipletId() >= PCI0_CHIPLET_ID) && // 0x8 + (getChipletId() <= PCI1_CHIPLET_ID) ) // 0x9 + { + // Ring ID of 0x2, Sat ID 1-6 + if ( (getRingId() == PCI_RING_ID) && // 0x2 + (getSatId() >= PHB0_AIB_SAT_ID) && // 0x1 + (getSatId() <= PHB2_PHB_SAT_ID) ) // 0x6 + { + l_phbTarget = true; + } + } + + // N0/N1 chiplet ID + if ( (getChipletId() >= N0_CHIPLET_ID) && // 0x2 + (getChipletId() <= N1_CHIPLET_ID) && // 0x3 + (getRingId() == N0_PE1_RING_ID) && // 0x6 + (getSatId() >= PHB0_AIB_SAT_ID) && // 0x1 + (getSatId() <= PHB2_AIB_SAT_ID) ) // 0x3 + { + l_phbTarget = true; + } + } + + return l_phbTarget; + } + + // ##################################### + uint8_t p10_scom_addr::getPhbTargetInstance() + { + uint8_t l_instance = 0; + + if ( (getChipletId() == N0_CHIPLET_ID) || + (getChipletId() == PCI1_CHIPLET_ID) ) + { + l_instance += 3; + } + + if ( (getRingId() == N0_PE1_RING_ID) ) + { + l_instance += (getSatId() - 1); + } + else if ( (getRingId() == PCI_RING_ID ) ) + { + l_instance += ((getSatId() - 1) % 3); + } + else + { + l_instance += (getRingId() - 3); + } + + return l_instance; + } + + // ##################################### + bool p10_scom_addr::isNmmuTarget() + { + bool l_nmmuTarget = false; + + // Must have NEST chiplet ID + if ( (getChipletId() == N0_CHIPLET_ID) || + (getChipletId() == N1_CHIPLET_ID) ) + { + // Endpoint must be PSCOM, ring ID must be 0x3, Sat ID must be 0/1 + if ( (getEndpoint() == PSCOM_ENDPOINT) && // 0x1 + (getRingId() == N0_MM0_RING_ID) && // 0x3 + (getSatId() >= NMMU_SAT_ID0) && // 0x0 + (getSatId() <= NMMU_SAT_ID1) ) // 0x1 + { + l_nmmuTarget = true; + } + } + + return l_nmmuTarget; + } + + // ##################################### + uint8_t p10_scom_addr::getNmmuTargetInstance() + { + return (getChipletId() - N0_CHIPLET_ID); + } + + // ##################################### + bool p10_scom_addr::isPervTarget() + { + bool l_pervTarget = false; + uint8_t l_index = 0; + + // Check chiplet ID by looping through PERV chiplet ID table + for (l_index = 0; + l_index < sizeof(PervTargetChipletIdTable) / sizeof(p10ChipletId_t); + l_index++) + { + // See if Chiplet ID is a perv chiplet ID from table + if (getChipletId() == PervTargetChipletIdTable[l_index]) + { + if (getEndpoint() == PSCOM_ENDPOINT) // 0x1 + { + // EQ specific PSCOM endpoint logic + // ensure ring being accessed is EQ scoped (non-core) + if ( (getChipletId() >= EQ0_CHIPLET_ID) && + (getChipletId() <= EQ7_CHIPLET_ID) ) + { + if ( (getEQRingId() == PERV_RING_ID) || // 0x1 + (getEQRingId() == QME_RING_ID) ) // 0x2 + { + l_pervTarget = true; + } + } + + // non-EQ chiplet, just match for ring ID = 0 / 1 + else + { + if ( (getRingId() == PSCOM_RING_ID) || // 0x0 + (getRingId() == PERV_RING_ID) ) // 0x1 + { + l_pervTarget = true; + } + } + } + else if (getEndpoint() == CLOCK_CTRL_ENDPOINT) // 0x3 + { + l_pervTarget = true; + } + // Check if Endpoint is a PERV endpoint + else if ( (getEndpoint() == CHIPLET_CTRL_ENDPOINT) || // 0x0 + (getEndpoint() == FIR_ENDPOINT) || // 0x4 + (getEndpoint() == THERMAL_ENDPOINT) || // 0x5 + (getEndpoint() == PCBSLV_ENDPOINT) ) // 0xF + { + if ( getRingId() == PSCOM_RING_ID) // 0x0 + { + l_pervTarget = true; + } + } + + break; + } + } + + return l_pervTarget; + } + + // ##################################### + uint8_t p10_scom_addr::getPervTargetInstance() + { + return getChipletId(); + } + + // ##################################### + bool p10_scom_addr::isIoHsTarget() + { + bool l_iohsTarget = false; + + // IOHS can be targeted by AXON or PAU chiplets (indirect scom), + + // Associate perv target resources with AXON + if ( (getChipletId() >= AXON0_CHIPLET_ID) && // 0x18 + (getChipletId() <= AXON7_CHIPLET_ID) ) // 0x1F + { + l_iohsTarget = isPervTarget(); + + // If not a PERV target check for IOHS target that uses AXON chiplet + if (l_iohsTarget == false) + { + if ( (getEndpoint() == PSCOM_ENDPOINT) && + (getRingId() == AXONE_PDL_RING_ID) && // 0x4 + (getSatId() == DLP_SAT_ID) ) // 0x0 + { + l_iohsTarget = true; + } + } + } + + // Target via PAU chiplets + else if ( isIndirect() && + (getChipletId() >= PAU0_CHIPLET_ID) && // 0x10 + (getChipletId() <= PAU3_CHIPLET_ID) ) // 0x13 + { + // Endpoint must be PSCOM and RingID is IOPPE + if ( (getEndpoint() == PSCOM_ENDPOINT) && + (getRingId() == PAU_IOPPE_RING_ID) ) // 0xB + { + // Group address (bits 22:26 of upper address) must be 0b00000 or 0b00001, + // and indirect register address should be per-group or per-lane + // Group 0: IOHS[0] + // Group 1: IOHS[1] + if ( ( (getIoGroupAddr() == 0x0) || + (getIoGroupAddr() == 0x1) ) && + ((getIoRegAddr() & 0x1E0) != 0x1E0) ) + { + l_iohsTarget = true; + } + } + } + + return l_iohsTarget; + } + + // ##################################### + uint8_t p10_scom_addr::getIoHsTargetInstance() + { + uint8_t l_instance = 0; + + // Chiplet ID is AXON + if ( (getChipletId() >= AXON0_CHIPLET_ID) && + (getChipletId() <= AXON7_CHIPLET_ID) ) + { + l_instance = getChipletId() - AXON0_CHIPLET_ID; + } + // Chiplet ID is PAU + else + { + // If chiplet ID is PAU then this is indirect address. + // Use PAU and Group address (bits 22:26) to calculate instance. + // PAU0 (lower right) -> IOHS0 + IOHS1 + // PAU1 (upper right) -> IOHS2 + IOHS3 + // PAU2 (lower left) -> IOHS4 + IOHS5 + // PAU3 (upper left) -> IOHS6 + IOHS7 + // + // Group address bits (22:26) of upper 32-bit + // Group 0: IOHS[0] + // Group 1: IOHS[1] + if ( (getChipletId() >= PAU0_CHIPLET_ID) && // 0x10 + (getChipletId() <= PAU3_CHIPLET_ID) ) // 0x13 + { + l_instance = (getChipletId() - PAU0_CHIPLET_ID) * 2; + + if (getIoGroupAddr() == 0x1) + { + l_instance += 1; + } + } + } + + return l_instance; + } + + // ##################################### + bool p10_scom_addr::isPauTarget() + { + bool l_pauTarget = false; + + // Endpoint must be PSCOM + if ( getEndpoint() == PSCOM_ENDPOINT) + { + // Check chiplet ID + if ( (getChipletId() >= PAU0_CHIPLET_ID) && + (getChipletId() <= PAU3_CHIPLET_ID) ) + { + if ( (getRingId() == PAU0346_0_RING_ID) || // 0x02 + (getRingId() == PAU0346_1_RING_ID) ) // 0x03 + + { + l_pauTarget = true; + } + else if ( (getChipletId() == PAU2_CHIPLET_ID) || + (getChipletId() == PAU3_CHIPLET_ID) ) + { + if ( (getRingId() == PAU57_0_RING_ID) || // 0x04 + (getRingId() == PAU57_1_RING_ID) ) // 0x05 + { + l_pauTarget = true; + } + } + } + } + + return l_pauTarget; + } + + // ##################################### + uint8_t p10_scom_addr::getPauTargetInstance() + { + uint8_t l_instance = 0; + + if ( (getRingId() == PAU0346_0_RING_ID) || // 0x02 + (getRingId() == PAU0346_1_RING_ID) ) // 0x03 + { + if (getChipletId() == PAU0_CHIPLET_ID) + { + l_instance = 0; + } + else if (getChipletId() == PAU1_CHIPLET_ID) + { + l_instance = 3; + } + else if (getChipletId() == PAU2_CHIPLET_ID) + { + l_instance = 4; + } + else if (getChipletId() == PAU3_CHIPLET_ID) + { + l_instance = 6; + } + } + + else if ( (getRingId() == PAU57_0_RING_ID) || // 0x04 + (getRingId() == PAU57_1_RING_ID) ) // 0x05 + { + if (getChipletId() == PAU2_CHIPLET_ID) + { + l_instance = 5; + } + else if (getChipletId() == PAU3_CHIPLET_ID) + { + l_instance = 7; + } + } + + return l_instance; + } + + // ##################################### + bool p10_scom_addr::isMcTarget() + { + // Same as MI + return isMiTarget(); + } + + // ##################################### + uint8_t p10_scom_addr::getMcTargetInstance() + { + // Same as MI + return getMiTargetInstance(); + } + + // ##################################### + bool p10_scom_addr::isMiTarget() + { + bool l_miTarget = false; + + // Chiplet ID must belong to MCs + if ( (getChipletId() >= MC0_CHIPLET_ID) && // 0x0C + (getChipletId() <= MC3_CHIPLET_ID) ) // 0x0F + { + // allow access to perv endpoints on MC chiplets + if (isPervTarget()) + { + l_miTarget = true; + } + // Endpoint = PSCOM_ENDPOINT, and ringID = MC_0_RING_ID + else if ( (getEndpoint() == PSCOM_ENDPOINT) && // 0x1 + (getRingId() == MC_0_RING_ID) ) // 0x3 + { + // PBI satellite + if (getSatId() == MC_SAT_ID0) // 0x0 (PBI) + { + // avoid match on MCC register space + if (!(((getSatOffset() >= 0x22) && + (getSatOffset() <= 0x2B)) || + ((getSatOffset() >= 0x32) && + (getSatOffset() <= 0x3B)))) + { + l_miTarget = true; + } + } + + // MCBIST satellite ID space + // avoid match on MCC register space in 0xD + if ( (getSatId() == MC_SAT_ID12) || // 0xC,0xE,0xF (MCBIST) + (getSatId() == MC_SAT_ID14) || + (getSatId() == MC_SAT_ID15) ) + { + l_miTarget = true; + } + } + } + + return l_miTarget; + } + + // ##################################### + uint8_t p10_scom_addr::getMiTargetInstance() + { + return getChipletId() - MC0_CHIPLET_ID; + } + + // ##################################### + bool p10_scom_addr::isMccTarget() + { + bool l_mccTarget = false; + + // Chiplet ID must belong to MCs, Endpoint = PSCOM_ENDPOINT, + // and ringID = MC_0_RING_ID + if ( (getChipletId() >= MC0_CHIPLET_ID) && // 0x0C + (getChipletId() <= MC3_CHIPLET_ID) && // 0x0F + (getEndpoint() == PSCOM_ENDPOINT) && // 0x1 + (getRingId() == MC_0_RING_ID) ) // 0x3 + { + // MCC Sat ID + if ( (getSatId() == MC_SAT_ID4) || // 0x4 + (getSatId() == MC_SAT_ID8) || // 0x8 + (getSatId() == MC_SAT_ID5) || // 0x5 + (getSatId() == MC_SAT_ID9) ) // 0x9 + { + l_mccTarget = true; + } + + // MCC register space in PBI + if (getSatId() == MC_SAT_ID0) + { + if (((getSatOffset() >= 0x22) && + (getSatOffset() <= 0x2B)) || + ((getSatOffset() >= 0x32) && + (getSatOffset() <= 0x3B))) + { + l_mccTarget = true; + } + } + + // MCC register space in MCBIST + if (getSatId() == MC_SAT_ID13) + { + l_mccTarget = true; + } + } + + return l_mccTarget; + } + + // ##################################### + uint8_t p10_scom_addr::getMccTargetInstance() + { + uint8_t l_instance = (getChipletId() - MC0_CHIPLET_ID) * 2; + + // MCC Sat ID + if ( (getSatId() == MC_SAT_ID5) || // 5 + (getSatId() == MC_SAT_ID9) ) // 9 + { + l_instance += 1; + } + + // MCC register space in PBI + if ( getSatId() == MC_SAT_ID0 ) // 0 + { + if ((getSatOffset() >= 0x32) && + (getSatOffset() <= 0x3B)) + { + l_instance += 1; + } + } + + // MCC register space in MCBIST + if ( getSatId() == MC_SAT_ID13) // 13 + { + // MSB of SatOffset denotes channel + if (getSatOffset() >= 0x20) + { + l_instance += 1; + } + } + + return l_instance; + } + + // ##################################### + bool p10_scom_addr::isOmiTarget() + { + bool l_omiTarget = false; + + // PAU chiplet, IOPPE ringId (indirect scom) + if ( isIndirect() && // indirect + ( getChipletId() >= PAU0_CHIPLET_ID ) && // 0x10 + ( getChipletId() <= PAU3_CHIPLET_ID ) && // 0x13 + ( getEndpoint() == PSCOM_ENDPOINT ) && // 0x1 + ( getRingId() == PAU_IOPPE_RING_ID) && // 0xB + ( getSatId() == PPE_SAT_ID0) ) // 0x0 + { + // Group address (bits 22:26 of upper address) + // must be 0b00010 or 0b00011 (for OMI) + if ( (getIoGroupAddr() == 0x2 ) || + (getIoGroupAddr() == 0x3 ) ) + { + // Reg address must start with 0xxx (per lane) + uint32_t regAddr = getIoRegAddr(); + + if ( ( regAddr & 0x100 ) == 0x000 ) + { + l_omiTarget = true; + } + } + } + + // MC chiplet direct SCOM + if ( ( getChipletId() >= MC0_CHIPLET_ID ) && // 0x0C + ( getChipletId() <= MC3_CHIPLET_ID ) && // 0x0F + ( getEndpoint() == PSCOM_ENDPOINT ) && // 0x1 + ( getRingId() >= OMI0_RING_ID ) && // 0x5 + ( getRingId() <= OMI1_RING_ID ) && // 0x6 + ( getSatId() == MC_SAT_ID0 ) ) // 0x0 (DL) + { + if (((getSatOffset() >= 16) && // 16:31 (subchannel 0) + (getSatOffset() <= 47)) || // 32:47 (subchannel 1) + ((getSatOffset() >= 48) && // 48:51 (subchannel 0, pm regs) + (getSatOffset() <= 51)) || + ((getSatOffset() >= 56) && // 48:51 (subchannel 1, pm regs) + (getSatOffset() <= 59))) + { + l_omiTarget = true; + } + } + + return l_omiTarget; + } + + // ##################################### + uint8_t p10_scom_addr::getOmiTargetInstance() + { + uint8_t l_instance = 0; + + // PAU chiplet indirect SCOM + if ( (getChipletId() >= PAU0_CHIPLET_ID) && // 0x10 + (getChipletId() <= PAU3_CHIPLET_ID) ) // 0x13 + { + // PAU0 --> OMI 0/1/2/3 + // PAU1 --> OMI 8/9/10/11 + // PAU2 --> OMI 4/5/6/7 + // PAU3 --> OMI 12/13/14/15 + // set basis based on direct chiplet ID + if (getChipletId() == PAU0_CHIPLET_ID) + { + l_instance = 0; + } + else if (getChipletId() == PAU1_CHIPLET_ID) + { + l_instance = 8; + } + else if (getChipletId() == PAU2_CHIPLET_ID) + { + l_instance = 4; + } + else + { + l_instance = 12; + } + + // account for IO group address + if (getIoGroupAddr() == 0x3) + { + l_instance += 2; + } + + // account for IO lane selection + if ( ( getIoLane() >= 8 ) && + ( getIoLane() <= 15) ) + { + l_instance += 1; + } + } + + // MC direct + if ( (getChipletId() >= MC0_CHIPLET_ID) && + (getChipletId() <= MC3_CHIPLET_ID) ) + { + // Instances 0, 4, 8, 12 + l_instance = (getChipletId() - MC0_CHIPLET_ID) * 4; + + // Instances 2, 6, 10, 14 + if ( getRingId() == OMI1_RING_ID ) // 0x6 + { + l_instance += 2; + } + + // Instances 1, 3, 5, 7, 9, 11, 13, 15 + if ( ((getSatOffset() >= 32) && + (getSatOffset() <= 47)) || + ((getSatOffset() >= 56) && + (getSatOffset() <= 59)) ) + { + l_instance += 1; + } + } + + return l_instance; + } + + // ##################################### + bool p10_scom_addr::isOmicTarget() + { + bool l_omicTarget = false; + + // PAU chiplet, IOPPE ringId (indirect scom) + if ( isIndirect() && // indirect + ( getChipletId() >= PAU0_CHIPLET_ID ) && // 0x10 + ( getChipletId() <= PAU3_CHIPLET_ID ) && // 0x13 + ( getEndpoint() == PSCOM_ENDPOINT ) && // 0x1 + ( getRingId() == PAU_IOPPE_RING_ID) && // 0xB + ( getSatId() == PPE_SAT_ID0) ) // 0x0 + { + // Group address (bits 22:26 of upper address) + // must be 0b00010 or 0b00011 (for OMI) + if ( (getIoGroupAddr() == 0x2 ) || + (getIoGroupAddr() == 0x3 ) ) + { + // Reg address must start with 1xxx (per group), + // excluding 1111 (per bus) + uint32_t regAddr = getIoRegAddr(); + + if ( ( ( regAddr & 0x1E0 ) != 0x1E0 ) && + ( ( regAddr & 0x100 ) == 0x100 ) ) + { + l_omicTarget = true; + } + } + } + + // MC chiplet direct SCOM + if ( ( getChipletId() >= MC0_CHIPLET_ID ) && // 0x0C + ( getChipletId() <= MC3_CHIPLET_ID ) && // 0x0F + ( getEndpoint() == PSCOM_ENDPOINT ) && // 0x1 + ( getRingId() >= OMI0_RING_ID ) && // 0x5 + ( getRingId() <= OMI1_RING_ID ) && // 0x6 + ( getSatId() == MC_SAT_ID0 ) && // 0x0 (DL) + ( getSatOffset() >= 0 ) && // shared regs 0-15 + ( getSatOffset() <= 15 ) ) + { + l_omicTarget = true; + } + + return l_omicTarget; + } + + // ##################################### + uint8_t p10_scom_addr::getOmicTargetInstance() + { + uint8_t l_instance = 0; + + // PAU indirect + if ( ( getChipletId() >= PAU0_CHIPLET_ID ) && // 0x10 + ( getChipletId() <= PAU3_CHIPLET_ID ) ) // 0x13 + { + // PAU0 --> OMIC 0/1 + // PAU1 --> OMIC 4/5 + // PAU2 --> OMIC 2/3 + // PAU3 --> OMIC 6/7 + if (getChipletId() == PAU0_CHIPLET_ID) + { + l_instance = 0; + } + else if (getChipletId() == PAU1_CHIPLET_ID) + { + l_instance = 4; + } + else if (getChipletId() == PAU2_CHIPLET_ID) + { + l_instance = 2; + } + else // PAU3_CHIPLET_ID + { + l_instance = 6; + } + + if (getIoGroupAddr() == 0x3) + { + l_instance += 1; + } + } + + // MC direct + if ( ( getChipletId() >= MC0_CHIPLET_ID ) && // 0x0C + ( getChipletId() <= MC3_CHIPLET_ID ) ) // 0x0F + { + l_instance = (getChipletId() - MC0_CHIPLET_ID) * 2; + + if (getRingId() == 0x6) + { + l_instance += 1; + } + } + + return l_instance; + } + + // ##################################### + bool p10_scom_addr::isPaucTarget() + { + bool l_paucTarget = false; + + if ( (getChipletId() >= PAU0_CHIPLET_ID) && // 0x10 + (getChipletId() <= PAU3_CHIPLET_ID) ) // 0x13 + { + // allow access to perv endpoints on MC chiplets + if (isPervTarget()) + { + l_paucTarget = true; + } + else if ( getEndpoint() == PSCOM_ENDPOINT ) // 0x1 + { + // IO PPE access + if ( isDirect() && // direct + (getRingId() == PAU_IOPPE_RING_ID) && // 0xB + ( (getSatId() == PPE_SAT_ID0) || // 0x0 + (getSatId() == PPE_SAT_ID1) ) ) // 0x1 + { + l_paucTarget = true; + } + + // TL access + if ( (getRingId() == PAU_TL_RING_ID) && // 0x6 + ( (getSatId() == TL_SAT_ID) ) ) // 0x0 + { + l_paucTarget = true; + } + + // per-bus IO super wrapper registers + if ( isIndirect() && // indirect + ((getIoRegAddr() & 0x1E0) == 0x1E0) && // register(0:3) = 0b1111 + (getRingId() == PAU_IOPPE_RING_ID) && // 0xB + (getSatId() == PPE_SAT_ID0) ) // 0x0 + { + l_paucTarget = true; + } + } + } + + return l_paucTarget; + } + + // ##################################### + uint8_t p10_scom_addr::getPaucTargetInstance() + { + uint8_t l_instance = (getChipletId() - PAU0_CHIPLET_ID); + + return l_instance; + } + +} // extern "C" + +#undef P10_SCOM_ADDR_C diff --git a/src/tests/p10_scom_addr.H b/src/tests/p10_scom_addr.H new file mode 100644 index 0000000..a764f2a --- /dev/null +++ b/src/tests/p10_scom_addr.H @@ -0,0 +1,700 @@ +/// +/// @file p10_scom_addr.H +/// @brief P10 SCOM address class +/// +/// HWP HW Maintainer: Thi Tran +/// HWP FW Maintainer: +/// HWP Consumed by: Cronus, HB, HWSV +/// + +#ifndef P10_SCOM_ADDR_H +#define P10_SCOM_ADDR_H + +// includes +#include + +extern "C" +{ + /// Constants + const uint32_t NUM_CORES_PER_EQ = 4; // Num of cores in an EQ chiplet + + /// P10 Chiplet ID enumeration + typedef enum + { + PIB_CHIPLET_ID = 0x00, ///< PIB chiplet (FSI) + PERV_CHIPLET_ID = 0x01, ///< TP chiplet + + N0_CHIPLET_ID = 0x02, ///< Nest0 (North) chiplet + N1_CHIPLET_ID = 0x03, ///< Nest1 (South) chiplet + + PCI0_CHIPLET_ID = 0x08, ///< PCIe0 chiplet + PCI1_CHIPLET_ID = 0x09, ///< PCIe1 chiplet + + MC0_CHIPLET_ID = 0x0C, ///< MC0 chiplet + MC1_CHIPLET_ID = 0x0D, ///< MC1 chiplet + MC2_CHIPLET_ID = 0x0E, ///< MC2 chiplet + MC3_CHIPLET_ID = 0x0F, ///< MC3 chiplet + + PAU0_CHIPLET_ID = 0x10, ///< PAU0 chiplet + PAU1_CHIPLET_ID = 0x11, ///< PAU1 chiplet + PAU2_CHIPLET_ID = 0x12, ///< PAU2 chiplet + PAU3_CHIPLET_ID = 0x13, ///< PAU3 chiplet + + AXON0_CHIPLET_ID = 0x18, ///< AXON0 chiplet (high speed io) + AXON1_CHIPLET_ID = 0x19, ///< AXON1 chiplet (high speed io) + AXON2_CHIPLET_ID = 0x1A, ///< AXON2 chiplet (high speed io) + AXON3_CHIPLET_ID = 0x1B, ///< AXON3 chiplet (high speed io) + AXON4_CHIPLET_ID = 0x1C, ///< AXON4 chiplet (high speed io) + AXON5_CHIPLET_ID = 0x1D, ///< AXON5 chiplet (high speed io) + AXON6_CHIPLET_ID = 0x1E, ///< AXON6 chiplet (high speed io) + AXON7_CHIPLET_ID = 0x1F, ///< AXON7 chiplet (high speed io) + + EQ0_CHIPLET_ID = 0x20, ///< Quad0 chiplet (super chiplet) + EQ1_CHIPLET_ID = 0x21, ///< Quad1 chiplet (super chiplet) + EQ2_CHIPLET_ID = 0x22, ///< Quad2 chiplet (super chiplet) + EQ3_CHIPLET_ID = 0x23, ///< Quad3 chiplet (super chiplet) + EQ4_CHIPLET_ID = 0x24, ///< Quad4 chiplet (super chiplet) + EQ5_CHIPLET_ID = 0x25, ///< Quad5 chiplet (super chiplet) + EQ6_CHIPLET_ID = 0x26, ///< Quad6 chiplet (super chiplet) + EQ7_CHIPLET_ID = 0x27, ///< Quad7 chiplet (super chiplet) + } p10ChipletId_t; + + /// P10 SCOM Endpoint ID enumeration + typedef enum + { + CHIPLET_CTRL_ENDPOINT = 0x0, ///< Chiplet Control + PSCOM_ENDPOINT = 0x1, ///< EQ:PSCOM (L3), others: PSCOM + PSCOM_2_ENDPOINT = 0x2, ///< EQ:PSCOM (Core/L2), TP:ITR, Nest:TOD (Time Of Day) + CLOCK_CTRL_ENDPOINT = 0x3, ///< Clock controller + FIR_ENDPOINT = 0x4, ///< FIR + THERMAL_ENDPOINT = 0x5, ///< Thermal + DPLL_ENDPOINT = 0x6, ///< TP (only): DPLL + QME_ENDPOINT = 0xE, ///< EQ (only): QME + PCBSLV_ENDPOINT = 0xF, ///< PCB Slave registers + } p10EndpointID_t; + + /// P10 region select (CoreId/One-hot) + typedef enum + { + EQ_REGION_SEL = 0x0, + MULTI_HOT_SELECT_C0 = 0x8, + MULTI_HOT_SELECT_C1 = 0x4, + MULTI_HOT_SELECT_C2 = 0x2, + MULTI_HOT_SELECT_C3 = 0x1, + } p10RegionSelect_t; + + /// ************************************* + /// Ring ID enums + /// ************************************* + + /// P10 N0 chiplet ring ID enumeration + typedef enum + { + N0_MM0_RING_ID = 0x3, + N0_PE1_RING_ID = 0x6, + } p10_N0_RingId_t; + + /// P10 N1 chiplet ring ID enumeration + /// source: tpc_p10_n1_top.vhdl + typedef enum + { + N1_MM1_RING_ID = 0x3, + N1_PE0_RING_ID = 0x6, + } p10_N1_RingId_t; + + /// P10 PCIe chiplet SCOM ring ID enumeration + typedef enum + { + PCI_RING_ID = 0x2, + IO_PCI0_RING_ID = 0x4, + IO_PCI1_RING_ID = 0x5, + } p10_PCI_RingId_t; + + /// P10 PERV chiplet and PSCOM ring ID enumeration + typedef enum + { + PSCOM_RING_ID = 0x0, + PERV_RING_ID = 0x1, + } p10_PSCOM_PERV_RingId_t; + + /// P10 AXONE chiplet ring ID enumeration + typedef enum + { + AXONE_PDL_RING_ID = 0x4, + } p10_AXONE_RingId_t; + + /// P10 PAU chiplet ring ID enumeration + typedef enum + { + PAU0346_0_RING_ID = 0x2, + PAU0346_1_RING_ID = 0x3, + PAU57_0_RING_ID = 0x4, + PAU57_1_RING_ID = 0x5, + PAU_TL_RING_ID = 0x6, + PAU_IOPPE_RING_ID = 0xB, + } p10_PAU_RingId_t; + + /// P10 MC chiplet ring ID enumeration + typedef enum + { + MC_0_RING_ID = 0x3, + MC_1_RING_ID = 0x4, + OMI0_RING_ID = 0x5, + OMI1_RING_ID = 0x6, + } p10_MC_RingId_t; + + /// P10 EQ chiplet ring ID enumeration + typedef enum + { + QME_RING_ID = 0x2, + L3_RING_ID = 0x3, + } p10_EQ_PSCOM_RingId_t; + + typedef enum + { + L2_RING_ID = 0x0, + C_0_RING_ID = 0x2, + C_1_RING_ID = 0x3, + C_3_RING_ID = 0x5, + } p10_EQ_PSCOM2_RingId_t; + + /// ----------------------- + /// Satellite ID defintions + /// ----------------------- + typedef enum + { + NMMU_SAT_ID0 = 0x0, + NMMU_SAT_ID1 = 0x1, + } p10_NMMU_SatId_t; + + typedef enum + { + PEC_SAT_ID = 0x0, + PHB0_AIB_SAT_ID = 0x1, + PHB1_AIB_SAT_ID = 0x2, + PHB2_AIB_SAT_ID = 0x3, + PHB0_PHB_SAT_ID = 0x4, + PHB1_PHB_SAT_ID = 0x5, + PHB2_PHB_SAT_ID = 0x6, + } p10_PCI_SatId_t; + + typedef enum + { + MC_SAT_ID0 = 0x0, + MC_SAT_ID4 = 0x4, + MC_SAT_ID5 = 0x5, + MC_SAT_ID8 = 0x8, + MC_SAT_ID9 = 0x9, + MC_SAT_ID12 = 0xC, + MC_SAT_ID13 = 0xD, + MC_SAT_ID14 = 0xE, + MC_SAT_ID15 = 0xF, + } p10_MC_SatId_t; + + typedef enum + { + PPE_SAT_ID0 = 0x0, + TL_SAT_ID = 0x0, + PPE_SAT_ID1 = 0x1, + } p10_PAU_SatId_t; + + typedef enum + { + DLP_SAT_ID = 0x0, + } p10_AXONE_SatId_t; + + /// ************************************* + /// Perv target table + /// ************************************* + const p10ChipletId_t PervTargetChipletIdTable[] = + { + PIB_CHIPLET_ID, + PERV_CHIPLET_ID, + N0_CHIPLET_ID, + N1_CHIPLET_ID, + PCI0_CHIPLET_ID, + PCI1_CHIPLET_ID, + MC0_CHIPLET_ID, + MC1_CHIPLET_ID, + MC2_CHIPLET_ID, + MC3_CHIPLET_ID, + PAU0_CHIPLET_ID, + PAU1_CHIPLET_ID, + PAU2_CHIPLET_ID, + PAU3_CHIPLET_ID, + AXON0_CHIPLET_ID, + AXON1_CHIPLET_ID, + AXON2_CHIPLET_ID, + AXON3_CHIPLET_ID, + AXON4_CHIPLET_ID, + AXON5_CHIPLET_ID, + AXON6_CHIPLET_ID, + AXON7_CHIPLET_ID, + EQ0_CHIPLET_ID, + EQ1_CHIPLET_ID, + EQ2_CHIPLET_ID, + EQ3_CHIPLET_ID, + EQ4_CHIPLET_ID, + EQ5_CHIPLET_ID, + EQ6_CHIPLET_ID, + EQ7_CHIPLET_ID, + }; + +// ---------------------- +// For non-EQ chiplets +// ---------------------- +// 8 7 6 5 4 3 2 1 +// +// |0 1 2 3| |4 5 6 7| |8 9 10 11| |12 13 14 15| |16 17 18 19| |20 21 22 23| |24 25 26 27| |28 29 30 31| +// {A}{ B } { C } 0 0 { D } { E } { F } +// +// A - Is multiCast if bit 1 = 0x1 +// B - Chiplet ID (6 bits) [2:7] +// C - Endpoint ID (4 bits) [12:15] +// D - Ring (4 bits) [18:21] +// E - Sat ID (4 bits) [22:25] +// F - Sat Offset (6 bits) [26:31] + +// ---------------------- +// For EQ/Core chiplets +// ---------------------- +// 8 7 6 5 4 3 2 1 +// +// |0 1 2 3| |4 5 6 7| |8 9 10 11| |12 13 14 15| |16 17 18 19| |20 21 22 23| |24 25 26 27| |28 29 30 31| +// {A}{ B } { C } { D } E F { G } { H } +// +// A - Is multiCast if bit 1 = 0x1 +// B - Chiplet ID (6 bits) [2:7] +// C - Endpoint ID (4 bits) [12:15] +// D - Region select (4 bits) [16:19] +// E - QME per core (1 bit) [20] +// F - QME Sat Enable (1 bit) [21] +// G - QME Sat sel (2 bits) [22:23] +// H - QME reg (8 bits) [24:31] + + /// P10 SCOM address class + class p10_scom_addr + { + public: + + /// @brief Construct a SCOM address object + /// @param[in] i_addr 64-bit raw SCOM address + p10_scom_addr(const uint64_t i_addr) + : iv_addr(i_addr) + { + } + + /// @brief Set full/raw SCOM address + /// @param[in] i_addr 64-bit SCOM address + /// @retval none + inline void setAddr(const uint64_t i_addr) + { + iv_addr = i_addr; + return; + } + + /// @brief Retrieve full/raw SCOM address + /// @retval uint64_t 64-bit SCOM address + inline uint64_t getAddr() const + { + return (iv_addr); + } + + /// @brief Determine if SCOM address is direct-form (bit 0) + /// @retval bool True if SCOM address is direct-form, false otherwise + inline bool isDirect() const + { + return (((iv_addr >> 63) & 0x1) == 0x0); + } + + /// @brief Determine if SCOM address is indirect-form + /// @retval bool True if SCOM address is indirect-form, false otherwise + inline bool isIndirect() const + { + return (!isDirect()); + } + + /// @brief Determine if SCOM address is multicast (bit 1) + /// @retval bool True if SCOM address is multicast, false otherwise + inline bool isMulticast() const + { + return (((iv_addr >> 30) & 0x1) == 0x1); + } + + /// @brief Determine if SCOM address is unicast + /// @retval bool True if SCOM address is unicast, false otherwise + inline bool isUnicast() const + { + return (!(isMulticast())); + } + + /// @brief Extract pervasive chiplet ID from SCOM address (bits 2:7) + /// @retval uint8_t Pervasive chiplet ID value + inline uint8_t getChipletId() const + { + return ((iv_addr >> 24) & 0x3F); + } + + /// @brief Modify SCOM address, update pervasive chiplet ID + /// @param[in] i_chiplet_id Chiplet ID value to write + /// @retval none + inline void setChipletId(const uint8_t i_chiplet_id) + { + iv_addr &= 0xFFFFFFFFC0FFFFFFULL; + iv_addr |= ((i_chiplet_id & 0x3F) << 24); + return; + } + + /// @brief Extract Endpoint field from SCOM address (bits 12:15) + /// @retval uint8_t Endpoint field value + inline uint8_t getEndpoint() const + { + return ((iv_addr >> 16) & 0xF); + } + + /// @brief Modify the Endpoint field from SCOM address + /// @retval none + inline void setEndpoint(const uint8_t i_port) + { + iv_addr &= 0xFFFFFFFFFFF0FFFFULL; + iv_addr |= ((i_port & 0xF) << 16); + return; + } + + /// @brief Extract region select field (core id) from SCOM address (bits 16:19) + /// @retval uint8_t Region select value + inline uint8_t getRegionSelect() const + { + return ((iv_addr >> 12) & 0xF); + } + + /// @brief Modify the region select field (core id) from SCOM address + /// @retval none + inline void setRegionSelect(const uint8_t i_regionSelect) + { + iv_addr &= 0xFFFFFFFFFFFF0FFFULL; + iv_addr |= ((i_regionSelect & 0xF) << 12); + return; + } + + /// @brief Extract ring field from SCOM address (bits 18:21) + /// @retval uint8_t Ring id value + inline uint8_t getRingId() const + { + return ((iv_addr >> 10) & 0xF); + } + + /// @brief Extract EQ ring field from SCOM address (bits 20:22) + /// @retval uint8_t Ring id value + inline uint8_t getEQRingId() const + { + return ((iv_addr >> 9) & 0x7); + } + + /// @brief Modify SCOM address, update ring field value + /// @param[in] i_ring Ring field value to write + /// @retval none + inline void setRingId(const uint8_t i_ring) + { + iv_addr &= 0xFFFFFFFFFFFF03FFULL; + iv_addr |= ((i_ring & 0x3F) << 10); + return; + } + + /// @brief Extract satellite ID field from SCOM address (bits 22:25) + /// @retval uint8_t Satellite ID field value + inline uint8_t getSatId() const + { + return ((iv_addr >> 6) & 0xF); + } + + /// @brief Extract EQ satellite ID field from SCOM address (bits 23:25) + /// @retval uint8_t Ring id value + inline uint8_t getEQSatId() const + { + return ((iv_addr >> 6) & 0x7); + } + + /// @brief Modify SCOM address, update satellite ID field + /// @param[in] i_sat_id Satellite ID value to write + /// @retval none + inline void setSatId(const uint8_t i_satId) + { + iv_addr &= 0xFFFFFFFFFFFFFC3FULL; + iv_addr |= ((i_satId & 0xF) << 6); + return; + } + + /// @brief Extract satellite register offset field from SCOM address (bits 26:31) + /// @retval uint8_t Satellite register offset field value + inline uint8_t getSatOffset() const + { + return (iv_addr & 0x3F); + } + + /// @brief Modify SCOM address, update satellite offset field + /// @param[in] i_sat_offset Satellite offset value to write + /// @retval none + inline void setSatOffset(const uint8_t i_sat_offset) + { + iv_addr &= 0xFFFFFFFFFFFFFFC0ULL; + iv_addr |= (i_sat_offset & 0x3F); + return; + } + + /// @brief Get the OBUS Super Wrapper Group address (bits 22:26) of + /// an indirect scom address + /// @retval uint8_t Group address + inline uint8_t getIoGroupAddr() const + { + return ((iv_addr >> 37) & 0x1F); + } + + /// @brief Set the OBUS Super Wrapper Group address (bits 22:26) of + /// an indirect scom address + /// @param[in] i_group_addr Group address value to write + /// @retval none + inline void setIoGroupAddr(const uint8_t i_group_addr) + { + iv_addr &= 0xFFFFFC1FFFFFFFFFULL; + iv_addr |= ( ((uint64_t)i_group_addr & 0x1F) << 37 ); + return; + } + + /// @brief Get Super Wrapper Register address (bits 12:20) + /// of an indirect scom address + /// @retval uint32_t Register address + inline uint32_t getIoRegAddr() const + { + return ((iv_addr >> 43) & 0x1FF); + } + + /// @brief Get the OBUS Super Wrapper TX/RX bit (bit 21) + /// of an indirect scom address + /// @retval uint8_t TX/RX bit + inline uint32_t getIoTxRxBit() const + { + return ((iv_addr >> 42) & 0x1); + } + + /// @brief Get the OBUS Super Wrapper Lane (bits 27:31) + /// of an indirect scom address + /// @retval uint8_t Lane + inline uint32_t getIoLane() const + { + return ((iv_addr >> 32) & 0x1F); + } + + /// @brief Set the OBUS Super Wrapper Lane (bits 27:31) + /// of an indirect scom address + /// @retval uint8_t Lane + inline void setIoLane(const uint8_t i_lane) + { + iv_addr &= 0xFFFFFFE0FFFFFFFFULL; + iv_addr |= ( ((uint64_t)i_lane & 0x1F) << 32); + } + + /// IOP indirect SCOMs + /// IOP0.top0.pma0 (PMA0) -> 0x8000xxxx0801113f + /// IOP0.top0.pma1 (PMA1) -> 0x8001xxxx0801113f + /// IOP0.top1.pma0 (PMA2) -> 0x8000xxxx0801153f + /// IOP0.top1.pma1 (PMA3) -> 0x8001xxxx0801153f + /// IOP1.top0.pma0 (PMA0) -> 0x8000xxxx0901113f + /// IOP1.top0.pma1 (PMA1) -> 0x8001xxxx0901113f + /// IOP1.top1.pma0 (PMA2) -> 0x8000xxxx0901153f + /// IOP1.top1.pma1 (PMA3) -> 0x8001xxxx0901153f + + /// @brief Get PEC IOP Control Register value (bits 12:31) from + /// an indirect scom address + /// @retval uint32_t CR register + inline uint32_t getIopIndCRreg() const + { + return ((iv_addr >> 32) & 0xFFFFF); + } + + /// @brief Get IOP TOP value (bit 53) from an indirect scom address + /// @retval uint8_t Top value (0 or 1) + inline uint8_t getIopTop() const + { + return ((iv_addr >> 10) & 0x1); + } + + /// @brief Get PMA value (bit 15) from an indirect scom address + /// @retval uint8_t Top value (0 or 1) + inline uint8_t getPMA() const + { + return ( ((iv_addr >> 48) & 0x1) + (getIopTop() * 2) ); + } + + /// @brief Determine if SCOM address is valid/well-formed + /// @retval bool True if SCOM address is valid, false otherwise + inline bool isValid() const + { + return true; + } + + /// @brief Determine if this address belongs to EQ target type + /// @retval true or false. + bool isEqTarget(); + + /// @brief Determine the EQ instance for this address + /// Function prereq: Address must belong to EQ target type + /// @retval uint8_t EQ target instance + uint8_t getEqTargetInstance(); + + /// @brief Determine if this address belongs to core target type + /// @retval true or false. + bool isCoreTarget(); + + /// @brief Determine the core instance for this address. + /// Function prereq: Address must belong to core target type + /// @retval uint8_t Core target instance + uint8_t getCoreTargetInstance(); + + /// @brief Determine if this address belongs to PEC target type + /// @retval true or false. + bool isPecTarget(); + + /// @brief Determine the pec instance for this address + /// Function prereq: Address must belong to PEC target type + /// @retval uint8_t PEC target instance + uint8_t getPecTargetInstance(); + + /// @brief Determine if this address belongs to PHB target type + /// @retval true or false. + bool isPhbTarget(); + + /// @brief Determine the PHB instance for this address + /// Function prereq: Address must belong to PHB target type + /// @retval uint8_t PHB target instance + uint8_t getPhbTargetInstance(); + + /// @brief Determine if this address belongs to NMMU target type + /// @retval true or false. + bool isNmmuTarget(); + + /// @brief Determine the NMMU instance for this address + /// Function prereq: Address must belong to NMMU target type + /// @retval uint8_t NMMU target instance + uint8_t getNmmuTargetInstance(); + + /// @brief Get the QME Per Core value (bit 20, EQ/Core only) + /// Function prereq: Address must belong to EQ or Core target type + /// @retval uint8_t QME Per Core value + inline uint8_t getQMEPerCore() + { + return (iv_addr >> 11) & 0x1; + } + + /// @brief Get the QME Sat Enable value (bit 21, EQ/Core only) + /// Function prereq: Address must belong to EQ or Core target type + /// @retval uint8_t QME Sat Enable value + inline uint8_t getQMESatEn() + { + return (iv_addr >> 10) & 0x1; + } + + /// @brief Get the QME Sat Select value (bit 22:23, EQ/Core only) + /// Function prereq: Address must belong to EQ or Core target type + /// @retval uint8_t QME Sat Sel value + inline uint8_t getQMESatSel() + { + return (iv_addr >> 8) & 0x3; + } + + /// @brief Get the QME reg value (bit 24:31, EQ/Core only) + /// Function prereq: Address must belong to EQ or Core target type + /// @retval uint8_t QME reg value + inline uint8_t getQMEReg() + { + return (iv_addr & 0xFF); + } + + /// @brief Determine if this address belongs to PERV target type + /// @retval true or false. + bool isPervTarget(); + + /// @brief Determine the PERV instance for this address + /// Function prereq: Address must belong to PERV target type + /// @retval uint8_t PERV target instance. + uint8_t getPervTargetInstance(); + + /// @brief Determine if this address belongs to IOHS target type + /// @retval true or false. + bool isIoHsTarget(); + + /// @brief Determine the IOHS instance for this address + /// Function prereq: Address must belong to IOHS target type + /// @retval uint8_t IOHS target instance. + uint8_t getIoHsTargetInstance(); + + /// @brief Determine if this address belongs to PAU target type + /// @retval true or false. + bool isPauTarget(); + + /// @brief Determine the PAU instance for this address + /// Function prereq: Address must belong to PAU target type + /// @retval uint8_t PAU target instance. + uint8_t getPauTargetInstance(); + + /// @brief Determine if this address belongs to MC target type + /// @retval true or false. + bool isMcTarget(); + + /// @brief Determine the MC instance for this address + /// Function prereq: Address must belong to MI target type + /// @retval uint8_t MC target instance. + uint8_t getMcTargetInstance(); + + /// @brief Determine if this address belongs to MI target type + /// @retval true or false. + bool isMiTarget(); + + /// @brief Determine the MI instance for this address + /// Function prereq: Address must belong to MI target type + /// @retval uint8_t MI target instance. + uint8_t getMiTargetInstance(); + + /// @brief Determine if this address belongs to MCC target type + /// @retval true or false. + bool isMccTarget(); + + /// @brief Determine the MCC instance for this address + /// Function prereq: Address must belong to MCC target type + /// @retval uint8_t MCC target instance. + uint8_t getMccTargetInstance(); + + /// @brief Determine if this address belongs to OMI target type + /// @retval true or false. + bool isOmiTarget(); + + /// @brief Determine the OMI instance for this address + /// Function prereq: Address must belong to OMI target type + /// @retval uint8_t OMI target instance. + uint8_t getOmiTargetInstance(); + + /// @brief Determine if this address belongs to OMIC target type + /// @retval true or false. + bool isOmicTarget(); + + /// @brief Determine the OMIC instance for this address + /// Function prereq: Address must belong to OMIC target type + /// @retval uint8_t OMIC target instance. + uint8_t getOmicTargetInstance(); + + /// @brief Determine if this address belongs to PAUC target type + /// @retval true or false. + bool isPaucTarget(); + + /// @brief Determine the PAUC instance for this address + /// Function prereq: Address must belong to PAUC target type + /// @retval uint8_t PAUC target instance. + uint8_t getPaucTargetInstance(); + + private: + uint64_t iv_addr; ///< 64-bit raw SCOM address + }; + +} // extern "C" + +#endif /* P10_SCOM_ADDR_H */ diff --git a/src/tests/p10_scominfo.C b/src/tests/p10_scominfo.C new file mode 100644 index 0000000..0294a50 --- /dev/null +++ b/src/tests/p10_scominfo.C @@ -0,0 +1,838 @@ +/// +/// @file p10_scominfo.C +/// @brief P10 chip unit SCOM address platform translation code +/// +/// HWP HW Maintainer: Thi Tran +/// HWP FW Maintainer: +/// HWP Consumed by: Cronus, HB, HWSV +/// + +// includes +#include "p10_scominfo.H" +#include "p10_scom_addr.H" + +#define P10_SCOMINFO_C + +extern "C" +{ + + // --------------------------- + // Internal functions + // --------------------------- + + //################################################################################ + /// @brief Calculate the region select (core ID) value for given core + /// instance + /// @param[in] i_coreInstance Core instance number (0-31) + /// @retval uint8_t Region select value + uint8_t calcRegionSelect(uint8_t i_coreInstanceNum) + { + uint8_t l_regionSel = 0; + + if (i_coreInstanceNum % NUM_CORES_PER_EQ == 0) + { + l_regionSel = 8; + } + else if (i_coreInstanceNum % NUM_CORES_PER_EQ == 1) + { + l_regionSel = 4; + } + else if (i_coreInstanceNum % NUM_CORES_PER_EQ == 2) + { + l_regionSel = 2; + } + else + { + l_regionSel = 1; + } + + return l_regionSel; + } + + //################################################################################ + /// @brief Get the chiplet ID for a chip unit instance based on given + /// address and chip unit type + /// @param[in] i_addr SCOM address + /// @param[in] i_chipUnitNum Instance number + /// @param[in] i_chipUnitType Chip unit type + /// @param[out] o_chipletId Output chiplet id + /// @retval Non-zero if error + uint8_t getChipletId(const uint64_t i_addr, + const uint8_t i_chipUnitNum, + const p10ChipUnits_t i_chipUnitType, + uint8_t& o_chipletId) + { + uint8_t l_rc = 0; + + do + { + p10_scom_addr l_scom(i_addr); + + switch (i_chipUnitType) + { + case PU_EQ_CHIPUNIT: + o_chipletId = EQ0_CHIPLET_ID + i_chipUnitNum; + break; + + case PU_C_CHIPUNIT: + o_chipletId = EQ0_CHIPLET_ID + (i_chipUnitNum / NUM_CORES_PER_EQ); + break; + + case PU_PEC_CHIPUNIT: + + // If input address is of Nest chiplets + if ( (l_scom.getChipletId() >= N0_CHIPLET_ID) && + (l_scom.getChipletId() <= N1_CHIPLET_ID) ) + { + o_chipletId = ((i_chipUnitNum) ? (N0_CHIPLET_ID) : (N1_CHIPLET_ID)); + } + // If input address is of PCI chiplets + else + { + o_chipletId = PCI0_CHIPLET_ID + i_chipUnitNum; + } + + break; + + case PU_PHB_CHIPUNIT: + + // If input address is of Nest chiplets + if ( (l_scom.getChipletId() >= N0_CHIPLET_ID) && + (l_scom.getChipletId() <= N1_CHIPLET_ID) ) + { + o_chipletId = ((i_chipUnitNum / 3) ? (N0_CHIPLET_ID) : (N1_CHIPLET_ID)); + } + // If input address is of PCI chiplets + else + { + o_chipletId = (i_chipUnitNum / 3) + PCI0_CHIPLET_ID; + } + + break; + + case PU_NMMU_CHIPUNIT: + o_chipletId = i_chipUnitNum + N0_CHIPLET_ID; + break; + + case PU_PERV_CHIPUNIT: + o_chipletId = i_chipUnitNum; + break; + + case PU_IOHS_CHIPUNIT: + + // If input address is of AXON chiplets + if ( (l_scom.getChipletId() >= AXON0_CHIPLET_ID) && // 0x18 + (l_scom.getChipletId() <= AXON7_CHIPLET_ID) ) // 0x1F + { + o_chipletId = AXON0_CHIPLET_ID + i_chipUnitNum; + } + else if ( (l_scom.getChipletId() >= PAU0_CHIPLET_ID) && + (l_scom.getChipletId() <= PAU3_CHIPLET_ID) ) + { + // PAU0 --> IOHS0, IOHS1 + // PAU1 --> IOHS2, IOHS3 + // PAU2 --> IOHS4, IOHS5 + // PAU3 --> IOHS6, IOHS7 + o_chipletId = (i_chipUnitNum / 2) + PAU0_CHIPLET_ID; + } + else + { + l_rc = 1; + } + + break; + + case PU_MI_CHIPUNIT: + case PU_MC_CHIPUNIT: + o_chipletId = i_chipUnitNum + MC0_CHIPLET_ID; + break; + + case PU_MCC_CHIPUNIT: + o_chipletId = (i_chipUnitNum / 2) + MC0_CHIPLET_ID; + break; + + case PU_OMIC_CHIPUNIT: + + // PAU indirect + if ( (l_scom.getChipletId() >= PAU0_CHIPLET_ID) && // 0x10 + (l_scom.getChipletId() <= PAU3_CHIPLET_ID) ) // 0x13 + { + // PAU0 --> OMIC 0/1 + // PAU1 --> OMIC 4/5 + // PAU2 --> OMIC 2/3 + // PAU3 --> OMIC 6/7 + if (i_chipUnitNum >= 0 && i_chipUnitNum <= 1) + { + o_chipletId = PAU0_CHIPLET_ID; + } + else if (i_chipUnitNum >= 2 && i_chipUnitNum <= 3) + { + o_chipletId = PAU2_CHIPLET_ID; + } + else if (i_chipUnitNum >= 4 && i_chipUnitNum <= 5) + { + o_chipletId = PAU1_CHIPLET_ID; + } + else if (i_chipUnitNum >= 6 && i_chipUnitNum <= 7) + { + o_chipletId = PAU3_CHIPLET_ID; + } + else + { + l_rc = 1; + } + } + // MC direct + else + { + o_chipletId = (i_chipUnitNum / 2) + MC0_CHIPLET_ID; + } + + break; + + case PU_OMI_CHIPUNIT: + + // PAU indirect + if ( (l_scom.getChipletId() >= PAU0_CHIPLET_ID) && // 0x10 + (l_scom.getChipletId() <= PAU3_CHIPLET_ID) ) // 0x13 + { + // PAU0 --> OMI 0/1/2/3 + // PAU1 --> OMI 8/9/10/11 + // PAU2 --> OMI 4/5/6/7 + // PAU3 --> OMI 12/13/14/15 + if (i_chipUnitNum >= 0 && i_chipUnitNum <= 3) + { + o_chipletId = PAU0_CHIPLET_ID; + } + else if (i_chipUnitNum >= 4 && i_chipUnitNum <= 7) + { + o_chipletId = PAU2_CHIPLET_ID; + } + else if (i_chipUnitNum >= 8 && i_chipUnitNum <= 11) + { + o_chipletId = PAU1_CHIPLET_ID; + } + else if (i_chipUnitNum >= 12 && i_chipUnitNum <= 15) + { + o_chipletId = PAU3_CHIPLET_ID; + } + else + { + l_rc = 1; + } + } + // MC direct + else + { + o_chipletId = (i_chipUnitNum / 4) + MC0_CHIPLET_ID; + } + + break; + + case PU_PAUC_CHIPUNIT: + o_chipletId = i_chipUnitNum + PAU0_CHIPLET_ID; + break; + + case PU_PAU_CHIPUNIT: + o_chipletId = (i_chipUnitNum / 2) + PAU0_CHIPLET_ID; + break; + + default: + l_rc = 1; + break; + }; + + } + while (0); + + return (l_rc); + } + + // See header file for function description + uint64_t p10_scominfo_createChipUnitScomAddr( + const p10ChipUnits_t i_p10CU, + const uint8_t i_ecLevel, + const uint8_t i_chipUnitNum, + const uint64_t i_scomAddr, + const uint32_t i_mode) + { + uint8_t l_rc = 0; + p10_scom_addr l_scom(i_scomAddr); + uint8_t l_chipletId = 0; + + do + { + // Make sure i_chipUnitNum is within range + l_rc = validateChipUnitNum(i_chipUnitNum, i_p10CU); + + if (l_rc) + { + break; + } + + // If chip unit type is a chip, return input address + if (i_p10CU == P10_NO_CU) + { + l_scom.setAddr(i_scomAddr); + break; + } + + // Set the chiplet ID + l_rc = getChipletId(i_scomAddr, i_chipUnitNum, i_p10CU, l_chipletId); + + if (l_rc) + { + break; + } + + l_scom.setChipletId(l_chipletId); + + // Set other address fields (ringId, satId, etc...) + // for Chip unit types that are needed. + switch (i_p10CU) + { + case PU_C_CHIPUNIT: + // Set the core's region select (core ID) + l_scom.setRegionSelect(calcRegionSelect(i_chipUnitNum)); + break; + + case PU_PHB_CHIPUNIT: + + // If input address is of Nest chiplets + if ( (l_scom.getChipletId() >= N0_CHIPLET_ID) && + (l_scom.getChipletId() <= N1_CHIPLET_ID) ) + { + l_scom.setSatId(1 + (i_chipUnitNum % 3)); + } + // If input address is of PCI chiplets + else + { + if (l_scom.getRingId() == 2) + { + if ((l_scom.getSatId() >= 1) && + (l_scom.getSatId() <= 3)) + { + l_scom.setSatId(1 + (i_chipUnitNum % 3)); + } + else + { + l_scom.setSatId(4 + (i_chipUnitNum % 3)); + } + } + } + + break; + + case PU_MCC_CHIPUNIT: + + // Set Sat ID + if (i_chipUnitNum % 2) + { + uint8_t l_offset = l_scom.getSatOffset(); + + // MCC Sat ID + // For odd MCC instance, Sat Id is to be set to 5, or 9 + // If input address is an even instance that has: + // SatId = 0x4 --> set translated SatId to 0x5 + // = 0x8 --> set translated SatId to 0x9 + // If input address is an odd instance, leave the SatId + // as input address. + if (l_scom.getSatId() == 0x4) + { + l_scom.setSatId(0x5); + } + else if (l_scom.getSatId() == 0x8) + { + l_scom.setSatId(0x9); + } + // PBI Sat ID + else if (l_scom.getSatId() == 0x0) + { + if ((l_offset >= 0x22) && + (l_offset <= 0x2B)) + { + l_scom.setSatOffset(l_offset + 0x10); + } + } + // MCBIST Sat ID + else if (l_scom.getSatId() == 0xD) + { + if ((l_offset >= 0x00) && + (l_offset <= 0x1F)) + { + l_scom.setSatOffset(l_offset + 0x20); + } + } + } + else + { + uint8_t l_offset = l_scom.getSatOffset(); + + // For even MCC instance, Sat Id is to be set to 4, or 8 + // If input address is an odd instance that has: + // SatId = 0x5 --> set translated SatId to 0x4 + // = 0x9 --> set translated SatId to 0x8 + // If input address is an even instance, leave the SatId + // as input address. + if (l_scom.getSatId() == 0x5) + { + l_scom.setSatId(0x4); + } + else if (l_scom.getSatId() == 0x9) + { + l_scom.setSatId(0x8); + } + // PBI Sat ID + else if (l_scom.getSatId() == 0x0) + { + if ((l_offset >= 0x32) && + (l_offset <= 0x3B)) + { + l_scom.setSatOffset(l_offset - 0x10); + } + } + // MCBIST Sat ID + else if (l_scom.getSatId() == 0xD) + { + if ((l_offset >= 0x20) && + (l_offset <= 0x3F)) + { + l_scom.setSatOffset(l_offset - 0x20); + } + } + } + + break; + + + case PU_IOHS_CHIPUNIT: + + // PAU indirect + if ( (l_scom.getChipletId() >= PAU0_CHIPLET_ID) && // 0x10 + (l_scom.getChipletId() <= PAU3_CHIPLET_ID) ) // 0x13 + { + // for odd IOHS instances, set IO group = 1 + if ( i_chipUnitNum % 2 ) + { + l_scom.setIoGroupAddr(0x1); + } + // for even IOHS instances, set IO group = 0 + else + { + l_scom.setIoGroupAddr(0x0); + } + } + + break; + + case PU_OMI_CHIPUNIT: + + // PAU indirect + if ( (l_scom.getChipletId() >= PAU0_CHIPLET_ID) && // 0x10 + (l_scom.getChipletId() <= PAU3_CHIPLET_ID) ) // 0x13 + { + // for odd OMI instances, set IO lane between 8-15 + if ( i_chipUnitNum % 2 ) + { + l_scom.setIoLane(8 + (l_scom.getIoLane() % 8)); + } + // for even OMI instances, set IO lane between 0-7 + else + { + l_scom.setIoLane(0 + (l_scom.getIoLane() % 8)); + } + + // for odd OMI instances after dividing by 2, set IO group = 3 + if ( (i_chipUnitNum / 2) % 2 ) + { + l_scom.setIoGroupAddr(0x3); + } + // for even OMI instances after dividing by 2, set IO group = 2 + else + { + l_scom.setIoGroupAddr(0x2); + } + } + // MC direct + else + { + // non-PM regs + if ((l_scom.getSatOffset() >= 16) && (l_scom.getSatOffset() <= 47)) + { + // for odd OMI instances, set sat reg ID between 32-47 + if ( i_chipUnitNum % 2 ) + { + l_scom.setSatOffset(32 + (l_scom.getSatOffset() % 16)); + } + // for even OMI instances, set sat reg ID between 16-31 + else + { + l_scom.setSatOffset(16 + (l_scom.getSatOffset() % 16)); + } + } + // PM regs + else + { + // for odd OMI instances, set sat reg ID between 56-59 + if ( i_chipUnitNum % 2 ) + { + l_scom.setSatOffset(56 + (l_scom.getSatOffset() % 4)); + } + // for even OMI instances, set sat reg ID between 48-51 + else + { + l_scom.setSatOffset(48 + (l_scom.getSatOffset() % 4)); + } + + } + + // for odd OMI instances after dividing by 2, set ring ID = 6 + if ( (i_chipUnitNum / 2) % 2 ) + { + l_scom.setRingId(0x6); + } + // for even OMI instances after dividing by 2, set ring ID = 5 + else + { + l_scom.setRingId(0x5); + } + } + + break; + + case PU_OMIC_CHIPUNIT: + + // PAU indirect + if ( (l_scom.getChipletId() >= PAU0_CHIPLET_ID) && // 0x10 + (l_scom.getChipletId() <= PAU3_CHIPLET_ID) ) // 0x13 + { + if (i_chipUnitNum % 2) + { + // For odd OMIC instance, set IO group ID=3 + l_scom.setIoGroupAddr(0x3); + } + else + { + // For even OMIC instance, set IO group ID=2 + l_scom.setIoGroupAddr(0x2); + } + } + // MC direct + else + { + if (i_chipUnitNum % 2) + { + // For odd OMIC instance, set ring ID=6 + l_scom.setRingId(0x6); + } + else + { + // For even OMIC instance, set ring ID=5 + l_scom.setRingId(0x5); + } + } + + break; + + case PU_PAU_CHIPUNIT: + + // Setting RingId for instances 0, 3, 4, and 6 + // If input address has: + // RingId = 0x4 --> set translated RingId to 0x2 + // 0x5 --> set translated RingId to 0x3 + // Leave RingId as is otherwise + if ( (i_chipUnitNum == 0) || + (i_chipUnitNum == 3) || + (i_chipUnitNum == 4) || + (i_chipUnitNum == 6) ) + { + if (l_scom.getRingId() == 0x4) + { + l_scom.setRingId(0x2); + } + else if (l_scom.getRingId() == 0x5) + { + l_scom.setRingId(0x3); + } + } + + // Setting RingId for instances 1, 2, 5, and 7 + // If input address has: + // RingId = 0x2 --> set translated RingId to 0x4 + // 0x3 --> set translated RingId to 0x5 + // Leave RingId as is otherwise + else if ( (i_chipUnitNum == 1) || + (i_chipUnitNum == 2) || + (i_chipUnitNum == 5) || + (i_chipUnitNum == 7) ) + { + if (l_scom.getRingId() == 0x2) + { + l_scom.setRingId(0x4); + } + else if (l_scom.getRingId() == 0x3) + { + l_scom.setRingId(0x5); + } + } + + break; + + default: + break; + } + + // Break out if error + if (l_rc) + { + break; + } + + } + while(0); + + if (l_rc) + { + l_scom.setAddr(FAILED_TRANSLATION); + } + + return l_scom.getAddr(); + } + + // See header file for function description + uint32_t p10_scominfo_isChipUnitScom(const p10ChipUnits_t i_p10CU, + const uint8_t i_ecLevel, + const uint64_t i_scomAddr, + bool& o_chipUnitRelated, + std::vector& o_chipUnitPairing, + const p10TranslationMode_t i_mode) + { + p10_scom_addr l_scom(i_scomAddr); + o_chipUnitRelated = false; + o_chipUnitPairing.clear(); + + // Quad registers which can be addressed by EQ target type + // eq: 0..7 + if (l_scom.isEqTarget()) + { + o_chipUnitRelated = true; + // PU_EQ_CHIPUNIT + o_chipUnitPairing.push_back(p10_chipUnitPairing_t(PU_EQ_CHIPUNIT, + l_scom.getEqTargetInstance())); + } + + // Core, L2, L3 registers which can be addressed by core target type + // c: 0..31 + if (l_scom.isCoreTarget()) + { + o_chipUnitRelated = true; + // PU_C_CHIPUNIT + o_chipUnitPairing.push_back(p10_chipUnitPairing_t(PU_C_CHIPUNIT, + l_scom.getCoreTargetInstance())); + } + + // PEC registers which can be addressed by pec target type + // pec: 0..1 + if (l_scom.isPecTarget()) + { + o_chipUnitRelated = true; + // PU_PEC_CHIPUNIT + o_chipUnitPairing.push_back(p10_chipUnitPairing_t(PU_PEC_CHIPUNIT, + l_scom.getPecTargetInstance())); + } + + // PHB registers + // phb: 0..5 + if (l_scom.isPhbTarget()) + { + o_chipUnitRelated = true; + // PU_PHB_CHIPUNIT + o_chipUnitPairing.push_back(p10_chipUnitPairing_t(PU_PHB_CHIPUNIT, + l_scom.getPhbTargetInstance())); + } + + // NMMU registers + // nmmu: 0..1 + if (l_scom.isNmmuTarget()) + { + o_chipUnitRelated = true; + // PU_NMMU_CHIPUNIT + o_chipUnitPairing.push_back(p10_chipUnitPairing_t(PU_NMMU_CHIPUNIT, + l_scom.getNmmuTargetInstance())); + } + + // IOHS registers + if (l_scom.isIoHsTarget() && + // prevent matching on IOHS SCOMs in ENGD build mode + (i_mode != P10_ENGD_BUILD_MODE)) + { + o_chipUnitRelated = true; + // PU_IOHS_CHIPUNIT + o_chipUnitPairing.push_back(p10_chipUnitPairing_t(PU_IOHS_CHIPUNIT, + l_scom.getIoHsTargetInstance())); + } + + // PAU registers + if (l_scom.isPauTarget()) + { + o_chipUnitRelated = true; + // PU_PAU_CHIPUNIT + o_chipUnitPairing.push_back(p10_chipUnitPairing_t(PU_PAU_CHIPUNIT, + l_scom.getPauTargetInstance())); + } + + // MC registers + if (l_scom.isMcTarget()) + { + o_chipUnitRelated = true; + // PU_MC_CHIPUNIT + o_chipUnitPairing.push_back(p10_chipUnitPairing_t(PU_MC_CHIPUNIT, + l_scom.getMcTargetInstance())); + } + + // MI registers + if (l_scom.isMiTarget()) + { + o_chipUnitRelated = true; + // PU_MI_CHIPUNIT + o_chipUnitPairing.push_back(p10_chipUnitPairing_t(PU_MI_CHIPUNIT, + l_scom.getMiTargetInstance())); + } + + // MCC registers + if (l_scom.isMccTarget()) + { + o_chipUnitRelated = true; + // PU_MCC_CHIPUNIT + o_chipUnitPairing.push_back(p10_chipUnitPairing_t(PU_MCC_CHIPUNIT, + l_scom.getMccTargetInstance())); + } + + // OMI registers + if (l_scom.isOmiTarget()) + { + o_chipUnitRelated = true; + // PU_OMI_CHIPUNIT + o_chipUnitPairing.push_back(p10_chipUnitPairing_t(PU_OMI_CHIPUNIT, + l_scom.getOmiTargetInstance())); + } + + // OMIC registers + if (l_scom.isOmicTarget()) + { + o_chipUnitRelated = true; + // PU_OMIC_CHIPUNIT + o_chipUnitPairing.push_back(p10_chipUnitPairing_t(PU_OMIC_CHIPUNIT, + l_scom.getOmicTargetInstance())); + } + + // PAUC registers + if (l_scom.isPaucTarget() && + // prevent matching on indirect SCOMs (physically targeting IOHS + // scan latches) in ENGD build mode + ((i_mode != P10_ENGD_BUILD_MODE) || + (l_scom.isDirect()))) + { + o_chipUnitRelated = true; + // PU_PAUC_CHIPUNIT + o_chipUnitPairing.push_back(p10_chipUnitPairing_t(PU_PAUC_CHIPUNIT, + l_scom.getPaucTargetInstance())); + } + + // PERV registers + if (l_scom.isPervTarget()) + { + // if running in engineering data build flow context, do not + // emit associations for registers which would have only + // a single association of type PERV + if (!((o_chipUnitPairing.size() == 0) && + (i_mode == P10_ENGD_BUILD_MODE))) + { + o_chipUnitRelated = true; + // PU_PERV_CHIPUNIT + o_chipUnitPairing.push_back(p10_chipUnitPairing_t(PU_PERV_CHIPUNIT, + l_scom.getPervTargetInstance())); + } + } + + /// Address may be of a chip, let it pass through + return (!l_scom.isValid()); + } + + uint32_t p10_scominfo_fixChipUnitScomAddrOrTarget(const p10ChipUnits_t i_p10CU, + const uint8_t i_ecLevel, + const uint32_t i_targetChipUnitNum, + const uint64_t i_scomaddr, + uint64_t& o_modifiedScomAddr, + p10ChipUnits_t& o_p10CU, + uint32_t& o_modifiedChipUnitNum, + const uint32_t i_mode) + { + uint32_t rc = 0; + + o_modifiedScomAddr = i_scomaddr; + o_p10CU = i_p10CU; + o_modifiedChipUnitNum = i_targetChipUnitNum; + + return rc; + } + + //################################################################################ + uint8_t validateChipUnitNum(const uint8_t i_chipUnitNum, + const p10ChipUnits_t i_chipUnitType) + { + uint8_t l_rc = 0; + uint8_t l_index; + + for (l_index = 0; + l_index < (sizeof(ChipUnitDescriptionTable) / sizeof(p10_chipUnitDescription_t)); + l_index++) + { + // Looking for input chip unit type in table + if (i_chipUnitType == ChipUnitDescriptionTable[l_index].enumVal) + { + // Found a match, check input i_chipUnitNum to be <= max chip unit num + // for this unit type + if (i_chipUnitNum > ChipUnitDescriptionTable[l_index].maxChipUnitNum) + { + l_rc = 1; + } + + // Additional check for PERV targets, where there are gaps between instances + else if (i_chipUnitType == PU_PERV_CHIPUNIT) + { + // Note: We allow content in chiplet ID = 0x00 to be referenced with a perv target instance, + // so do not check for instance = 0 here. + if ( ((i_chipUnitNum > 3) && (i_chipUnitNum < 8)) || + ((i_chipUnitNum > 9) && (i_chipUnitNum < 12)) || + ((i_chipUnitNum > 19) && (i_chipUnitNum < 24)) ) + { + l_rc = 1; + } + } + + // Additional check for PAU targets, where instance 1 and 2 are not valid + else if (i_chipUnitType == PU_PAU_CHIPUNIT) + { + if ( (i_chipUnitNum == 1) || (i_chipUnitNum == 2) ) + { + l_rc = 1; + } + } + + break; + } + } + + // Can't find i_chipUnitType in table + if ( l_index >= (sizeof(ChipUnitDescriptionTable) / sizeof(p10_chipUnitDescription_t)) ) + { + l_rc = 1; + } + + return (l_rc); + } + +} // extern "C" + +#undef P10_SCOMINFO_C diff --git a/src/tests/p10_scominfo.H b/src/tests/p10_scominfo.H new file mode 100644 index 0000000..2075d08 --- /dev/null +++ b/src/tests/p10_scominfo.H @@ -0,0 +1,89 @@ +/// +/// @file p10_scominfo.H +/// @brief P10 chip unit SCOM address platform translation code +/// +/// HWP HW Maintainer: Thi Tran +/// HWP FW Maintainer: +/// HWP Consumed by: Cronus, HB, HWSV +/// + +#ifndef P10_SCOMINFO_H +#define P10_SCOMINFO_H + +// includes +#include +#include +#include "p10_cu.H" + +extern "C" +{ + // Modes of translation + typedef enum + { + P10_DEFAULT_MODE = 0, // Default platform behavior + P10_ENGD_BUILD_MODE = 1, // Apply customization for ENGD build + } p10TranslationMode_t; + + typedef enum + { + FAILED_TRANSLATION = 0xFFFFFFFFFFFFFFF1ull + } p10TranslationResult_t; + + /// @brief Creates the actual SCOM address based on the chip unit type, instance, and the input SCOM address (relative to chip unit instance 0) + /// @param[in] i_p10CU Enumeration of the chip unit type + /// @param[in] i_ecLevel Chip EC level represented in HEX digit value. Example: i_ecLevel = 0x12 --> EC level 1.2 + /// @param[in] i_chipUnitNum Instance number of the chip unit + /// @param[in] i_scomAddr The input SCOM address associated with the chip unit type + /// @param[in] i_mode Translation mode, specifying different addr translation methods. + /// @retval uint64_t Actual SCOM address for the chip unit instance passed in + uint64_t p10_scominfo_createChipUnitScomAddr(const p10ChipUnits_t i_p10CU, + const uint8_t i_ecLevel, + const uint8_t i_chipUnitNum, + const uint64_t i_scomAddr, + const uint32_t i_mode = 0); + + /// @brief Determine if the provided SCOM address correlates to any chip units (if so creates a list of chipUnitPairing structures which correspond) + /// @param[in] i_p10CU Enumeration of the chip unit type + /// @param[in] i_ecLevel Chip EC level represented in HEX digit value. Example: i_ecLevel = 0x12 --> EC level 1.2 + /// @param[in] i_scomAddr SCOM address to be tested + /// @param[out] o_chipUnitRelated Returns true if SCOM address is associated with any chip units + /// @param[out] o_chipUnitPairing Collection of chipUnitPairing enums + /// @param[in] i_mode Translation mode, specifying different addr translation methods. + /// @retval uint32_t Return non-zero for error + uint32_t p10_scominfo_isChipUnitScom(const p10ChipUnits_t i_p10CU, + const uint8_t i_ecLevel, + const uint64_t i_scomAddr, + bool& o_chipUnitRelated, + std::vector& o_chipUnitPairing, + const p10TranslationMode_t i_mode = P10_DEFAULT_MODE); + + /// @brief Alter the unit/unitnum of a target for spys where the clocks-on vs clocks-off targets are different. + /// @param[in] i_p10CU Target used for the spy request + /// @param[in] i_ecLevel Chip EC level represented in HEX digit value. Example: i_ecLevel = 0x12 --> EC level 1.2 + /// @param[in] i_targetChipUnitNum The instance number of the target used for the spy request + /// @param[in] i_scomaddr The scom from the clocks-on portion of the spy + /// @param[out] o_modifiedScomAddr The translated scom address (none may be needed) + /// @param[out] o_p10CU The translated target type + /// @param[out] o_modifiedChipUnitNum The translated target instance number + /// @param[in] i_mode Translation mode, specifying different addr translation methods. + /// @retval uint32_t Return non-zero for error + uint32_t p10_scominfo_fixChipUnitScomAddrOrTarget(const p10ChipUnits_t i_p10CU, + const uint8_t i_ecLevel, + const uint32_t i_targetChipUnitNum, + const uint64_t i_scomaddr, + uint64_t& o_modifiedScomAddr, + p10ChipUnits_t& o_p10CU, + uint32_t& o_modifiedChipUnitNum, + const uint32_t i_mode = 0); + + /// @brief Validate the chip unit number to be within range + /// of a chip unit type. + /// @param[in] i_chipUnitNum Value of chip unit number (instance) + /// @param[in] i_chipUnitType Chip unit type + /// @retval Non-zero if error + uint8_t validateChipUnitNum(const uint8_t i_chipUnitNum, + const p10ChipUnits_t i_chipUnitType); + +} // extern "C" + +#endif /* P10_SCOMINFO_H */ From patchwork Thu Oct 1 07:08:01 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Amitay Isaacs X-Patchwork-Id: 1374873 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [203.11.71.2]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4C246k6Fzrz9sVN for ; Thu, 1 Oct 2020 17:11:26 +1000 (AEST) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=ozlabs.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; secure) header.d=ozlabs.org header.i=@ozlabs.org header.a=rsa-sha256 header.s=201707 header.b=Ru/OZZ08; dkim-atps=neutral Received: from bilbo.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 4C246k39TYzDqTv for ; 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Thu, 1 Oct 2020 17:11:15 +1000 (AEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ozlabs.org; s=201707; t=1601536279; bh=hKaTn4RcM8td7y1+jRhoRRLzQBYK4vtQ97sYQ3a4q6U=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Ru/OZZ08mK+3MXWAHDo2aK1URAVEXei9q4G4JYtEYdkScRxtXOuyKSwOVd+i+gNnZ lrV2lGjSJxcGEw7tHxujqBm75MKdZMG/r+mM3b6OQsicuvVB8gk2pj4ZlRVZWIP6rG 9F81H3T6o0vNjkmvcCQqGnAGyok+M5tZMfPqlNiSm3c5EFF1E+ALL6v1UZAYvhkqer tnP9IviTejDfxcjHCn0axncZzW7VtP0gJH8Eb5MLUKZIiP4+GTsvihUBIomTheOSz+ MvLrZoPLB2rWjT5K40OKIas5tOY3tZ/+f0NJUTHJxDyOxG8AXdP9CQx0657YUrOEv1 cnsXR8qp96jmA== From: Amitay Isaacs To: pdbg@lists.ozlabs.org Date: Thu, 1 Oct 2020 17:08:01 +1000 Message-Id: <20201001070814.102735-8-amitay@ozlabs.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201001070814.102735-1-amitay@ozlabs.org> References: <20201001070814.102735-1-amitay@ozlabs.org> MIME-Version: 1.0 Subject: [Pdbg] [PATCH v2 07/20] tests: Add fapi p10 address translation tests X-BeenThere: pdbg@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: "mailing list for https://github.com/open-power/pdbg development" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: pdbg-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Pdbg" From: Alistair Popple Signed-off-by: Alistair Popple Reviewed-by: Joel Stanley --- Makefile.am | 7 ++ src/tests/libpdbg_p10_fapi_translation_test.C | 113 ++++++++++++++++++ 2 files changed, 120 insertions(+) create mode 100644 src/tests/libpdbg_p10_fapi_translation_test.C diff --git a/Makefile.am b/Makefile.am index 779c52c..ceeadb9 100644 --- a/Makefile.am +++ b/Makefile.am @@ -16,6 +16,7 @@ libpdbg_tests = libpdbg_target_test \ bin_PROGRAMS = pdbg check_PROGRAMS = $(libpdbg_tests) libpdbg_dtree_test \ libpdbg_p9_fapi_translation_test \ + libpdbg_p10_fapi_translation_test \ optcmd_test hexdump_test cronus_proxy \ libpdbg_prop_test libpdbg_attr_test \ libpdbg_traverse_test @@ -252,6 +253,12 @@ libpdbg_p9_fapi_translation_test_CXXFLAGS = $(libpdbg_test_cflags) libpdbg_p9_fapi_translation_test_LDFLAGS = $(libpdbg_test_ldflags) libpdbg_p9_fapi_translation_test_LDADD = $(libpdbg_test_ldadd) +libpdbg_p10_fapi_translation_test_SOURCES = src/tests/libpdbg_p10_fapi_translation_test.C \ + src/tests/p10_scominfo.C src/tests/p10_scom_addr.C +libpdbg_p10_fapi_translation_test_CXXFLAGS = $(libpdbg_test_cflags) +libpdbg_p10_fapi_translation_test_LDFLAGS = $(libpdbg_test_ldflags) +libpdbg_p10_fapi_translation_test_LDADD = $(libpdbg_test_ldadd) + libpdbg_prop_test_SOURCES = src/tests/libpdbg_prop_test.c libpdbg_prop_test_CFLAGS = $(libpdbg_test_cflags) libpdbg_prop_test_LDFLAGS = $(libpdbg_test_ldflags) diff --git a/src/tests/libpdbg_p10_fapi_translation_test.C b/src/tests/libpdbg_p10_fapi_translation_test.C new file mode 100644 index 0000000..eb6db73 --- /dev/null +++ b/src/tests/libpdbg_p10_fapi_translation_test.C @@ -0,0 +1,113 @@ +#include +#include + +#define class klass +#include "libpdbg/libpdbg.h" +#include "libpdbg/hwunit.h" +#include "libpdbg/target.h" +#undef class + +#include "p10_scominfo.H" + +#define MAX_INDEX 30 + +int test_unit_translation(struct pdbg_target *target, p10ChipUnits_t cu, int index, uint64_t addr) +{ + uint64_t pdbg_addr, fapi_addr; + + target->index = index; + + /* TODO: Check standard chiplet translation */ + if (!target->translate) + return 1; + + if (validateChipUnitNum(index, cu)) + return 1; + + pdbg_addr = target->translate(target, addr); + fapi_addr = p10_scominfo_createChipUnitScomAddr(cu, 0x10, index, addr, 0); + + /* Ignore bad addresses. We should really test that we get an assert error + * from the translation code though. */ + if (fapi_addr == FAILED_TRANSLATION) + return 1; + + if (pdbg_addr != fapi_addr) + fprintf(stderr, + "PDBG Address 0x%016" PRIx64 " does not match FAPI Address 0x%016" PRIx64 + " for address 0x%016" PRIx64 " on target %s@%d\n", + pdbg_addr, fapi_addr, addr, pdbg_target_path(target), index); + + return pdbg_addr == fapi_addr; +} + +static struct chip_unit { + p10ChipUnits_t cu; + const char *classname; +} chip_unit[] = { + { PU_C_CHIPUNIT, "core" }, + { PU_EQ_CHIPUNIT, "eq" }, + { PU_PEC_CHIPUNIT, "pec" }, + { PU_PHB_CHIPUNIT, "phb" }, + { PU_MI_CHIPUNIT, "mi" }, + { PU_MCC_CHIPUNIT, "mcc" }, + { PU_OMIC_CHIPUNIT, "omic" }, + { PU_OMI_CHIPUNIT, "omi" }, + { PU_PERV_CHIPUNIT, "chiplet" }, + { PU_MC_CHIPUNIT, "mc" }, + { PU_NMMU_CHIPUNIT, "nmmu" }, + { PU_IOHS_CHIPUNIT, "iohs" }, + { PU_PAU_CHIPUNIT, "pau" }, + { PU_PAUC_CHIPUNIT, "pauc" }, + { NONE, NULL }, +}; + +int main(int argc, const char **argv) +{ + struct pdbg_target *target; + p10ChipUnits_t cu = NONE; + int i, count=0; + + if (argc != 2) { + fprintf(stderr, "Usage: %s \n", argv[0]); + return 1; + } + + // pdbg_set_loglevel(PDBG_DEBUG); + + pdbg_targets_init(NULL); + + for (i=0; chip_unit[i].classname; i++) { + if (!strcmp(argv[1], chip_unit[i].classname)) { + cu = chip_unit[i].cu; + } + } + + if (cu == NONE) { + fprintf(stderr, "Unknown class '%s'\n", argv[1]); + return 1; + } + + pdbg_for_each_class_target(argv[1], target) { + uint64_t addr; + int index = pdbg_target_index(target); + + /* We only need to test targets on proc0, translation won't change for + * other procs */ + if (pdbg_target_index(pdbg_target_parent("proc", target))) + continue; + + printf("Testing %s %d\n", pdbg_target_path(target), index); + /* Test every sat offset */ + for (addr = 0; addr < 0xffffffff; addr += 0x40) + assert(test_unit_translation(target, cu, index, addr)); + + count++; + } + + if (count == 0) { + printf("Test skipped for class '%s'\n", argv[1]); + } + + return 0; +} From patchwork Thu Oct 1 07:08:02 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Amitay Isaacs X-Patchwork-Id: 1374874 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4C246q6sfSz9sVK for ; Thu, 1 Oct 2020 17:11:31 +1000 (AEST) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=ozlabs.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; secure) header.d=ozlabs.org header.i=@ozlabs.org header.a=rsa-sha256 header.s=201707 header.b=yP9MXqPu; dkim-atps=neutral Received: from bilbo.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 4C246q5nCyzDqTn for ; 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Thu, 1 Oct 2020 17:11:19 +1000 (AEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ozlabs.org; s=201707; t=1601536284; bh=aZFm1sGl3/fbXlzrzknoviTQf2ifkBG7fMNEWd+R6EE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=yP9MXqPu9RMOSrUwzfAv2AvL2ZjjQ41TQKwfy+NxlJcgjtbkyTbD9dA3Hfputk6lu mAoMgH2yQtw84NpYBAPfcSmoOCxT18O50iYHgyuzZV8VuO380W+0Q6HRbOfW0w5CSf TMGSRgGOigGUjqpLEH7bvxVHJtri5NFcvR4d1RQi2UpK8FPEYA74iqcRBHS6rQMEz1 sW7zOf5ykU37uojVqfppYQTPUUorSREOMZ8CAxgBqW/H43oHQ8lqHd16mTaGcw3BER CZEmnANgLFfsLxGwW1JznZkP3yG5IWcBS7YgMGCI5Xloz5eZsCynZcrsHrAZqL9rM1 4nZZZc4fvURUQ== From: Amitay Isaacs To: pdbg@lists.ozlabs.org Date: Thu, 1 Oct 2020 17:08:02 +1000 Message-Id: <20201001070814.102735-9-amitay@ozlabs.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201001070814.102735-1-amitay@ozlabs.org> References: <20201001070814.102735-1-amitay@ozlabs.org> MIME-Version: 1.0 Subject: [Pdbg] [PATCH v2 08/20] tests: Add P10 address translation tests wrapper X-BeenThere: pdbg@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: "mailing list for https://github.com/open-power/pdbg development" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Amitay Isaacs Errors-To: pdbg-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Pdbg" Signed-off-by: Amitay Isaacs Reviewed-by: Joel Stanley --- Makefile.am | 4 +- tests/test_p10_fapi_translation.sh | 206 +++++++++++++++++++++++++++++ 2 files changed, 209 insertions(+), 1 deletion(-) create mode 100755 tests/test_p10_fapi_translation.sh diff --git a/Makefile.am b/Makefile.am index ceeadb9..d902863 100644 --- a/Makefile.am +++ b/Makefile.am @@ -32,13 +32,15 @@ PDBG_TESTS = \ tests/test_attr_array.sh \ tests/test_attr_packed.sh \ tests/test_traverse.sh \ - tests/test_p9_fapi_translation.sh + tests/test_p9_fapi_translation.sh \ + tests/test_p10_fapi_translation.sh TESTS = $(libpdbg_tests) optcmd_test $(PDBG_TESTS) tests/test_tree2.sh: fake2.dtb fake2-backend.dtb tests/test_prop.sh: fake.dtb fake-backend.dtb tests/test_p9_fapi_translation.sh: p9.dtb bmc-kernel.dtb +tests/test_p10_fapi_translation.sh: p10.dtb bmc-kernel.dtb test: $(libpdbg_tests) diff --git a/tests/test_p10_fapi_translation.sh b/tests/test_p10_fapi_translation.sh new file mode 100755 index 0000000..5e58ccb --- /dev/null +++ b/tests/test_p10_fapi_translation.sh @@ -0,0 +1,206 @@ +#!/bin/sh + +. $(dirname "$0")/driver.sh + +test_group "p10 fapi translation tests" + +export PDBG_BACKEND_DTB=bmc-kernel.dtb +export PDBG_DTB=p10.dtb + +test_result 0 < X-Patchwork-Id: 1374875 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [203.11.71.2]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4C246v66rhz9sVN for ; Thu, 1 Oct 2020 17:11:35 +1000 (AEST) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=ozlabs.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; secure) header.d=ozlabs.org header.i=@ozlabs.org header.a=rsa-sha256 header.s=201707 header.b=Q0SG2SWV; dkim-atps=neutral Received: from bilbo.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 4C246v5CYhzDqTb for ; Thu, 1 Oct 2020 17:11:35 +1000 (AEST) X-Original-To: pdbg@lists.ozlabs.org Delivered-To: pdbg@lists.ozlabs.org Received: from ozlabs.org (bilbo.ozlabs.org [203.11.71.1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 4C246n3dvSzDqTK for ; Thu, 1 Oct 2020 17:11:29 +1000 (AEST) Authentication-Results: lists.ozlabs.org; dmarc=pass (p=none dis=none) header.from=ozlabs.org Authentication-Results: lists.ozlabs.org; dkim=pass (2048-bit key; secure) header.d=ozlabs.org header.i=@ozlabs.org header.a=rsa-sha256 header.s=201707 header.b=Q0SG2SWV; dkim-atps=neutral Received: from authenticated.ozlabs.org (localhost [127.0.0.1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by mail.ozlabs.org (Postfix) with ESMTPSA id 4C246k1qPTz9sVL; Thu, 1 Oct 2020 17:11:25 +1000 (AEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ozlabs.org; s=201707; t=1601536289; bh=vuKxTrARS10oogqlXJLa66FN1+8zQKrrBWTDKmIFSYg=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Q0SG2SWVNogkG3SOVJ1IaEGmbgqcpGJabpgrg5RFUKLdqpOcE/yQf9PkqQqEEmhc7 2qy0oX19gGa4mw9ISyYPA3/wP5AY/dr0mp143Swz905Xen8kgFSve3TZ9uAdFHQHWc zTQgD/jCrrQRj93T1nID/kZOmRwmOvnOumPWc5Ct3sMXuPQKfHC4qUPr2PXFn4efpO kQZW2NZYxxz4rnTg/nvta6kOFK0JvQkOtI0KgNEISLjtsckgwrZbcgSOaZiByPFevP NNWJQPoQ7wmO3CjCxTBgKHGwEHnMhUEa0erDzZYvuBfX3V14H8pYB0995OubLeBv49 OtYV+SxOXauag== From: Amitay Isaacs To: pdbg@lists.ozlabs.org Date: Thu, 1 Oct 2020 17:08:03 +1000 Message-Id: <20201001070814.102735-10-amitay@ozlabs.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201001070814.102735-1-amitay@ozlabs.org> References: <20201001070814.102735-1-amitay@ozlabs.org> MIME-Version: 1.0 Subject: [Pdbg] [PATCH v2 09/20] libpdbg: Add processor type to libsbefifo implementation X-BeenThere: pdbg@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: "mailing list for https://github.com/open-power/pdbg development" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Amitay Isaacs Errors-To: pdbg-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Pdbg" There are few changes between P9 and P10 sbefifo api. Use proc type to implement the changes in the api. Signed-off-by: Amitay Isaacs Reviewed-by: Joel Stanley --- libpdbg/cronus.c | 18 ++++++++++++++++-- libpdbg/sbefifo.c | 18 ++++++++++++++++-- libsbefifo/connect.c | 26 ++++++++++++++++++++++++-- libsbefifo/libsbefifo.h | 8 ++++++-- libsbefifo/sbefifo_private.h | 1 + 5 files changed, 63 insertions(+), 8 deletions(-) diff --git a/libpdbg/cronus.c b/libpdbg/cronus.c index 23d555b..8966843 100644 --- a/libpdbg/cronus.c +++ b/libpdbg/cronus.c @@ -155,13 +155,27 @@ static int cronus_sbefifo_transport(uint8_t *msg, uint32_t msg_len, static int cronus_sbefifo_probe(struct pdbg_target *target) { struct sbefifo *sf = target_to_sbefifo(target); - int rc; + int rc, proc; rc = cronus_probe(target); if (rc) return rc; - rc = sbefifo_connect_transport(cronus_sbefifo_transport, sf, &sf->sf_ctx); + switch (pdbg_get_proc()) { + case PDBG_PROC_P9: + proc = SBEFIFO_PROC_P9; + break; + + case PDBG_PROC_P10: + proc = SBEFIFO_PROC_P10; + break; + + default: + PR_ERROR("SBEFIFO driver not supported\n"); + return -1; + } + + rc = sbefifo_connect_transport(proc, cronus_sbefifo_transport, sf, &sf->sf_ctx); if (rc) { PR_ERROR("Unable to initialize sbefifo driver\n"); return rc; diff --git a/libpdbg/sbefifo.c b/libpdbg/sbefifo.c index 6e45088..63a37e9 100644 --- a/libpdbg/sbefifo.c +++ b/libpdbg/sbefifo.c @@ -631,12 +631,26 @@ static int sbefifo_probe(struct pdbg_target *target) { struct sbefifo *sf = target_to_sbefifo(target); const char *sbefifo_path; - int rc; + int rc, proc; sbefifo_path = pdbg_target_property(target, "device-path", NULL); assert(sbefifo_path); - rc = sbefifo_connect(sbefifo_path, &sf->sf_ctx); + switch (pdbg_get_proc()) { + case PDBG_PROC_P9: + proc = SBEFIFO_PROC_P9; + break; + + case PDBG_PROC_P10: + proc = SBEFIFO_PROC_P10; + break; + + default: + PR_ERROR("SBEFIFO driver not supported\n"); + return -1; + } + + rc = sbefifo_connect(sbefifo_path, proc, &sf->sf_ctx); if (rc) { PR_ERROR("Unable to open sbefifo driver %s\n", sbefifo_path); return rc; diff --git a/libsbefifo/connect.c b/libsbefifo/connect.c index 1295dc5..1d23af5 100644 --- a/libsbefifo/connect.c +++ b/libsbefifo/connect.c @@ -20,15 +20,27 @@ #include #include #include +#include #include "libsbefifo.h" #include "sbefifo_private.h" -int sbefifo_connect(const char *fifo_path, struct sbefifo_context **out) +static bool proc_valid(int proc) +{ + if (proc == SBEFIFO_PROC_P9 || proc == SBEFIFO_PROC_P10) + return true; + + return false; +} + +int sbefifo_connect(const char *fifo_path, int proc, struct sbefifo_context **out) { struct sbefifo_context *sctx; int fd, rc; + if (!proc_valid(proc)) + return EINVAL; + sctx = malloc(sizeof(struct sbefifo_context)); if (!sctx) { fprintf(stderr, "Memory allocation error\n"); @@ -37,6 +49,7 @@ int sbefifo_connect(const char *fifo_path, struct sbefifo_context **out) *sctx = (struct sbefifo_context) { .fd = -1, + .proc = proc, }; fd = open(fifo_path, O_RDWR | O_SYNC); @@ -53,10 +66,13 @@ int sbefifo_connect(const char *fifo_path, struct sbefifo_context **out) return 0; } -int sbefifo_connect_transport(sbefifo_transport_fn transport, void *priv, struct sbefifo_context **out) +int sbefifo_connect_transport(int proc, sbefifo_transport_fn transport, void *priv, struct sbefifo_context **out) { struct sbefifo_context *sctx; + if (!proc_valid(proc)) + return EINVAL; + sctx = malloc(sizeof(struct sbefifo_context)); if (!sctx) { fprintf(stderr, "Memory allocation error\n"); @@ -65,6 +81,7 @@ int sbefifo_connect_transport(sbefifo_transport_fn transport, void *priv, struct *sctx = (struct sbefifo_context) { .fd = -1, + .proc = proc, .transport = transport, .priv = priv, }; @@ -84,6 +101,11 @@ void sbefifo_disconnect(struct sbefifo_context *sctx) free(sctx); } +int sbefifo_proc(struct sbefifo_context *sctx) +{ + return sctx->proc; +} + void sbefifo_debug(const char *fmt, ...) { va_list ap; diff --git a/libsbefifo/libsbefifo.h b/libsbefifo/libsbefifo.h index cbfb76d..3af54b4 100644 --- a/libsbefifo/libsbefifo.h +++ b/libsbefifo/libsbefifo.h @@ -48,15 +48,19 @@ #define SBEFIFO_SEC_PIB_ERROR 0x0011 #define SBEFIFO_SEC_PARITY_ERROR 0x0012 +#define SBEFIFO_PROC_P9 0x01 +#define SBEFIFO_PROC_P10 0x02 + struct sbefifo_context; typedef int (*sbefifo_transport_fn)(uint8_t *msg, uint32_t msg_len, uint8_t *out, uint32_t *out_len, void *private_data); -int sbefifo_connect(const char *fifo_path, struct sbefifo_context **out); -int sbefifo_connect_transport(sbefifo_transport_fn transport, void *priv, struct sbefifo_context **out); +int sbefifo_connect(const char *fifo_path, int proc, struct sbefifo_context **out); +int sbefifo_connect_transport(int proc, sbefifo_transport_fn transport, void *priv, struct sbefifo_context **out); void sbefifo_disconnect(struct sbefifo_context *sctx); +int sbefifo_proc(struct sbefifo_context *sctx); int sbefifo_parse_output(struct sbefifo_context *sctx, uint32_t cmd, uint8_t *buf, uint32_t buflen, diff --git a/libsbefifo/sbefifo_private.h b/libsbefifo/sbefifo_private.h index d94112f..6262c3e 100644 --- a/libsbefifo/sbefifo_private.h +++ b/libsbefifo/sbefifo_private.h @@ -65,6 +65,7 @@ struct sbefifo_context { int fd; + int proc; sbefifo_transport_fn transport; void *priv; From patchwork Thu Oct 1 07:08:04 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Amitay Isaacs X-Patchwork-Id: 1374876 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [203.11.71.2]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4C247268stz9sVM for ; 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dkim=pass (2048-bit key; secure) header.d=ozlabs.org header.i=@ozlabs.org header.a=rsa-sha256 header.s=201707 header.b=oVNL2SNe; dkim-atps=neutral Received: from authenticated.ozlabs.org (localhost [127.0.0.1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by mail.ozlabs.org (Postfix) with ESMTPSA id 4C246p0gM7z9sVJ; Thu, 1 Oct 2020 17:11:29 +1000 (AEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ozlabs.org; s=201707; t=1601536292; bh=2T9W4V8U7Xrrfrc/CZ9xh9uejDHlMRTCvmfgzIunwE8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=oVNL2SNezv5Poh8Lpgq4+BvBx9yXIGsTD5d3NaE01xlsTSGa07frQ9y2gwboHy8No IkmS8PMxj0VgFvdcOmmWZEVqnrd7F2FPuGzdPxuNCFPw8i8aiAUhvs+NUZlXyZAMKz rKLwlk3dxFvUli5jxBGsVJVeMpRsn+4J+NLN8eIUeWZXhXTKYFxfPigIZEMS3j7+hS ciqs5nzjGGEjbkaIclhefF20b7d0NeBmG4/xYX5ZDCdzlfhMxPcL1+G4iU9/QKT7Mm q9ei8ZiORkbl7y+MIzeTEIuvVcIP89iTjQbFdtTHAamlqIzJqGAwwt8K5lrxEfnxLG +JjhfWW5qi4sA== From: Amitay Isaacs To: pdbg@lists.ozlabs.org Date: Thu, 1 Oct 2020 17:08:04 +1000 Message-Id: <20201001070814.102735-11-amitay@ozlabs.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201001070814.102735-1-amitay@ozlabs.org> References: <20201001070814.102735-1-amitay@ozlabs.org> MIME-Version: 1.0 Subject: [Pdbg] [PATCH v2 10/20] libsbefifo: Add implementation of suspend_io chipop X-BeenThere: pdbg@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: "mailing list for https://github.com/open-power/pdbg development" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Amitay Isaacs Errors-To: pdbg-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Pdbg" Signed-off-by: Amitay Isaacs Reviewed-by: Joel Stanley --- libsbefifo/cmd_control.c | 51 ++++++++++++++++++++++++++++++++++++ libsbefifo/libsbefifo.h | 1 + libsbefifo/sbefifo_private.h | 1 + 3 files changed, 53 insertions(+) diff --git a/libsbefifo/cmd_control.c b/libsbefifo/cmd_control.c index 9293ef9..4826b5d 100644 --- a/libsbefifo/cmd_control.c +++ b/libsbefifo/cmd_control.c @@ -76,3 +76,54 @@ int sbefifo_istep_execute(struct sbefifo_context *sctx, uint8_t major, uint8_t m return rc; } + +static int sbefifo_suspend_io_push(uint8_t **buf, uint32_t *buflen) +{ + uint32_t *msg; + uint32_t nwords, cmd; + + nwords = 2; + *buflen = nwords * sizeof(uint32_t); + msg = malloc(*buflen); + if (!msg) + return ENOMEM; + + cmd = SBEFIFO_CMD_CLASS_CONTROL | SBEFIFO_CMD_SUSPEND_IO; + + msg[0] = htobe32(nwords); + msg[1] = htobe32(cmd); + + *buf = (uint8_t *)msg; + return 0; +} + +static int sbefifo_suspend_io_pull(uint8_t *buf, uint32_t buflen) +{ + if (buflen != 0) + return EPROTO; + + return 0; +} + +int sbefifo_suspend_io(struct sbefifo_context *sctx) +{ + uint8_t *msg, *out; + uint32_t msg_len, out_len; + int rc; + + rc = sbefifo_suspend_io_push(&msg, &msg_len); + if (rc) + return rc; + + out_len = 0; + rc = sbefifo_operation(sctx, msg, msg_len, &out, &out_len); + free(msg); + if (rc) + return rc; + + rc = sbefifo_suspend_io_pull(out, out_len); + if (out) + free(out); + + return rc; +} diff --git a/libsbefifo/libsbefifo.h b/libsbefifo/libsbefifo.h index 3af54b4..1c26ea3 100644 --- a/libsbefifo/libsbefifo.h +++ b/libsbefifo/libsbefifo.h @@ -73,6 +73,7 @@ uint32_t sbefifo_ffdc_get(struct sbefifo_context *sctx, const uint8_t **ffdc, ui void sbefifo_ffdc_dump(struct sbefifo_context *sctx); int sbefifo_istep_execute(struct sbefifo_context *sctx, uint8_t major, uint8_t minor); +int sbefifo_suspend_io(struct sbefifo_context *sctx); #define SBEFIFO_SCOM_OPERAND_NONE 0 #define SBEFIFO_SCOM_OPERAND_OR 1 diff --git a/libsbefifo/sbefifo_private.h b/libsbefifo/sbefifo_private.h index 6262c3e..5c9b10a 100644 --- a/libsbefifo/sbefifo_private.h +++ b/libsbefifo/sbefifo_private.h @@ -22,6 +22,7 @@ #define SBEFIFO_CMD_CLASS_CONTROL 0xA100 #define SBEFIFO_CMD_EXECUTE_ISTEP 0x01 +#define SBEFIFO_CMD_SUSPEND_IO 0x02 #define SBEFIFO_CMD_CLASS_SCOM 0xA200 #define SBEFIFO_CMD_GET_SCOM 0x01 From patchwork Thu Oct 1 07:08:05 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Amitay Isaacs X-Patchwork-Id: 1374877 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4C24762m6sz9sVT for ; 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dkim=pass (2048-bit key; secure) header.d=ozlabs.org header.i=@ozlabs.org header.a=rsa-sha256 header.s=201707 header.b=lh5qUzYv; dkim-atps=neutral Received: from authenticated.ozlabs.org (localhost [127.0.0.1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by mail.ozlabs.org (Postfix) with ESMTPSA id 4C246t1dW3z9sVK; Thu, 1 Oct 2020 17:11:33 +1000 (AEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ozlabs.org; s=201707; t=1601536297; bh=Z402cTjPt9JlrMd4kfolu9HaME1hP0YVnfFuVUDuuy8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=lh5qUzYvn99D3aPaR4VrQ1qcFzyyQ/8dBWrDgBrdqhOsq5KW4tMIMNM+xyZPe1fNw b37wpLrIg4BL/vzC0kq61WueBMcEhjRPL8+wlw/zs9jCSjbt2ykNfK/wMjwOVoHbFF MK9K854zntca9T/J5oo3jabWXAaD0ddMCOdyzHDEsZwEFv7l5TJ/N2FWOYk6Zjk6VE x6SkQ9ms96hicWifvcsP002dITCODZVXXfomQv77Sgi2+cDv7H8UegVLWC81leYNTU TCEAurHnhnOjvT3nxOxRsndFM1DY4oVtUsoP8ZhAwC6HRGN9q4UOdjN0Yhp5HvL+p9 8TgItas7fMgJA== From: Amitay Isaacs To: pdbg@lists.ozlabs.org Date: Thu, 1 Oct 2020 17:08:05 +1000 Message-Id: <20201001070814.102735-12-amitay@ozlabs.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201001070814.102735-1-amitay@ozlabs.org> References: <20201001070814.102735-1-amitay@ozlabs.org> MIME-Version: 1.0 Subject: [Pdbg] [PATCH v2 11/20] libsbefifo: Add new definitions for P10 sbe X-BeenThere: pdbg@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: "mailing list for https://github.com/open-power/pdbg development" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Amitay Isaacs Errors-To: pdbg-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Pdbg" Signed-off-by: Amitay Isaacs Reviewed-by: Joel Stanley --- libsbefifo/libsbefifo.h | 50 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 50 insertions(+) diff --git a/libsbefifo/libsbefifo.h b/libsbefifo/libsbefifo.h index 1c26ea3..e149de5 100644 --- a/libsbefifo/libsbefifo.h +++ b/libsbefifo/libsbefifo.h @@ -19,6 +19,12 @@ #include +/* + * libsbefifo implements SBE interfaces available via SBEFIFO device. The + * details of the interface can be found in SBE interface specification + * document (2.0 for P10). + */ + #define ESBEFIFO 201 #define SBEFIFO_PRI_SUCCESS 0x00000000 @@ -26,6 +32,7 @@ #define SBEFIFO_PRI_INVALID_DATA 0x00020000 #define SBEFIFO_PRI_SEQUENCE_ERROR 0x00030000 #define SBEFIFO_PRI_INTERNAL_ERROR 0x00040000 +#define SBEFIFO_PRI_ACCESS_DENIED 0x00050000 #define SBEFIFO_PRI_UNKNOWN_ERROR 0x00FE0000 #define SBEFIFO_SEC_SUCCESS 0x0000 @@ -47,6 +54,44 @@ #define SBEFIFO_SEC_HW_TIMEOUT 0x0010 #define SBEFIFO_SEC_PIB_ERROR 0x0011 #define SBEFIFO_SEC_PARITY_ERROR 0x0012 +#define SBEFIFO_SEC_UNUSED 0x0013 +#define SBEFIFO_SEC_MEM_INVALID_ACCESS 0x0014 +#define SBEFIFO_SEC_MEM_REGION_NOT_FOUND 0x0015 +#define SBEFIFO_SEC_MEM_OVERFLOW_REGION 0x0016 +#define SBEFIFO_SEC_MEM_REGION_AMEND 0x0017 +#define SBEFIFO_SEC_INPUT_BUFFER_OVERFLOW 0x0018 +#define SBEFIFO_SEC_INVALID_PARAM 0x0019 +/* Missing error codes */ +#define SBEFIFO_SEC_INVALID_CHIPOP 0x0020 +#define SBEFIFO_SEC_DEADMAN_TIMEOUT 0x0021 +#define SBEFIFO_SEC_SYSTEM_CHECKSTOP 0x0022 +#define SBEFIFO_SEC_REG_ACCESS_BLOCKED 0x0023 +#define SBEFIFO_SEC_START_MPIPL_FAIL 0x0024 +#define SBEFIFO_SEC_STOP_CLOCK_FAIL 0x0025 +#define SBEFIFO_SEC_CONT_MPIPL_FAIL 0x0026 +#define SBEFIFO_SEC_IO_TOGGLE_FAIL 0x0027 +#define SBEFIFO_SEC_SPL_WKUP_TIMEOUT 0x0028 +#define SBEFIFO_SEC_SPL_WKUP_SCOM_FAIL 0x0029 +#define SBEFIFO_SEC_REG_DUMP_FAIL 0x002A +#define SBEFIFO_SEC_LPC_ACCESS_FAIL 0x002B +#define SBEFIFO_SEC_HWP_FAIL 0x002C +#define SBEFIFO_SEC_ATTN_CORE_READ_FAIL 0x002D +#define SBEFIFO_SEC_ATTN_DATA_READ_FAIL 0x002E +#define SBEFIFO_SEC_PUT_SRAM_FAIL 0x002F +#define SBEFIFO_SEC_GET_SRAM_FAIL 0x0030 +#define SBEFIFO_SEC_THREAD_CONTROL_FAIL 0x0031 +#define SBEFIFO_SEC_RAM_CORE_SETUP_FAIL 0x0032 +#define SBEFIFO_SEC_RAM_CORE_ACCESS_FAIL 0x0033 +#define SBEFIFO_SEC_RAM_CORE_CLEAN_FAIL 0x0034 +#define SBEFIFO_SEC_SUSPEND_IO_FAIL 0x0035 +#define SBEFIFO_SEC_ENTER_MPIPL_FAIL2 0x0036 +#define SBEFIFO_SEC_STOP_CLOCK_FAIL2 0x0037 + +#define SBEFIFO_TARGET_TYPE_PROC 0x0000 +#define SBEFIFO_TARGET_TYPE_PERV 0x0001 +#define SBEFIFO_TARGET_TYPE_EQ 0x0002 +#define SBEFIFO_TARGET_TYPE_CORE 0x0003 +#define SBEFIFO_TARGET_TYPE_OCMB 0x0004 #define SBEFIFO_PROC_P9 0x01 #define SBEFIFO_PROC_P10 0x02 @@ -102,6 +147,11 @@ int sbefifo_ring_put_from_image(struct sbefifo_context *sctx, uint16_t target, u int sbefifo_mem_get(struct sbefifo_context *sctx, uint64_t addr, uint32_t size, uint16_t flags, uint8_t **data); int sbefifo_mem_put(struct sbefifo_context *sctx, uint64_t addr, uint8_t *data, uint32_t len, uint16_t flags); + +#define SBEFIFO_MEMORY_MODE_NORMAL 0x01 +#define SBEFIFO_MEMORY_MODE_DEBUG 0x02 +#define SBEFIFO_MEMORY_MODE_CIRCULAR 0x03 + int sbefifo_occsram_get(struct sbefifo_context *sctx, uint32_t addr, uint32_t size, uint8_t mode, uint8_t **data, uint32_t *data_len); int sbefifo_occsram_put(struct sbefifo_context *sctx, uint32_t addr, uint8_t *data, uint32_t data_len, uint8_t mode); From patchwork Thu Oct 1 07:08:06 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Amitay Isaacs X-Patchwork-Id: 1374878 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [203.11.71.2]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4C24792CZwz9sVM for ; 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dkim=pass (2048-bit key; secure) header.d=ozlabs.org header.i=@ozlabs.org header.a=rsa-sha256 header.s=201707 header.b=fcYkfRqp; dkim-atps=neutral Received: from authenticated.ozlabs.org (localhost [127.0.0.1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by mail.ozlabs.org (Postfix) with ESMTPSA id 4C246y72d8z9sVL; Thu, 1 Oct 2020 17:11:38 +1000 (AEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ozlabs.org; s=201707; t=1601536302; bh=e3OZmmr9VZb/oZF1HN/w8GFZO50VczqzwGnnJz8KzjA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=fcYkfRqpLNCQSWMNg3pKRWya2mjsKQd+yjNmpm8XV4hg8zbq/Skx7yw1/kYslqaTG AkcXnvv0/gvb44cjCQ/VTciMcJ3rpo2QbOY5vAvJu4wRB+8/SK4anUmgquZfk2ra1n Z2LMUwvHzvUTeiySPB1rVGbWW+gzCuCGFPuCC0c2JZR0/SlKKUUfm2wcRJXlcj2LOx Ucq0mJS57AA8HSCnufYMd6RL9vRVn3nr6Jc4J9AfNTZPIcBFOpBjRwanYrInu9fWPm hY/x0UTL5h1GC/TMKm89t/oOBf3E8wIBtDHgonXTGSPm0aRlOzHTt1yOrDJDaoU0z9 cNGLAlSppQ0mQ== From: Amitay Isaacs To: pdbg@lists.ozlabs.org Date: Thu, 1 Oct 2020 17:08:06 +1000 Message-Id: <20201001070814.102735-13-amitay@ozlabs.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201001070814.102735-1-amitay@ozlabs.org> References: <20201001070814.102735-1-amitay@ozlabs.org> MIME-Version: 1.0 Subject: [Pdbg] [PATCH v2 12/20] libsbefifo: P10 dropped put_ring_from_image chipop X-BeenThere: pdbg@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: "mailing list for https://github.com/open-power/pdbg development" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Amitay Isaacs Errors-To: pdbg-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Pdbg" Signed-off-by: Amitay Isaacs Reviewed-by: Joel Stanley --- libsbefifo/cmd_ring.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/libsbefifo/cmd_ring.c b/libsbefifo/cmd_ring.c index c1c0ec2..44e8eff 100644 --- a/libsbefifo/cmd_ring.c +++ b/libsbefifo/cmd_ring.c @@ -178,6 +178,9 @@ int sbefifo_ring_put_from_image(struct sbefifo_context *sctx, uint16_t target, u uint32_t msg_len, out_len; int rc; + if (sctx->proc != SBEFIFO_PROC_P9) + return ENOSYS; + rc = sbefifo_ring_put_from_image_push(target, chiplet_id, ring_id, ring_mode, &msg, &msg_len); if (rc) return rc; From patchwork Thu Oct 1 07:08:07 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Amitay Isaacs X-Patchwork-Id: 1374879 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4C247K1sbKz9sVN for ; Thu, 1 Oct 2020 17:11:57 +1000 (AEST) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=ozlabs.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; secure) header.d=ozlabs.org header.i=@ozlabs.org header.a=rsa-sha256 header.s=201707 header.b=JVc3rEcY; dkim-atps=neutral Received: from bilbo.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 4C247K0zfbzDqTW for ; Thu, 1 Oct 2020 17:11:57 +1000 (AEST) X-Original-To: pdbg@lists.ozlabs.org Delivered-To: pdbg@lists.ozlabs.org Received: from ozlabs.org (bilbo.ozlabs.org [203.11.71.1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 4C24792B97zDqTk for ; Thu, 1 Oct 2020 17:11:49 +1000 (AEST) Authentication-Results: lists.ozlabs.org; dmarc=pass (p=none dis=none) header.from=ozlabs.org Authentication-Results: lists.ozlabs.org; dkim=pass (2048-bit key; secure) header.d=ozlabs.org header.i=@ozlabs.org header.a=rsa-sha256 header.s=201707 header.b=JVc3rEcY; dkim-atps=neutral Received: from authenticated.ozlabs.org (localhost [127.0.0.1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by mail.ozlabs.org (Postfix) with ESMTPSA id 4C2473723Jz9sVN; Thu, 1 Oct 2020 17:11:43 +1000 (AEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ozlabs.org; s=201707; t=1601536308; bh=SZyieNjYRLZpSX1pFxYAG2SWlq7GFw4Iq2pFmxiZvUk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=JVc3rEcYYptbIw903v/keqeGEdavz2sJkhqFuTW4hTo+J8fuIcMSV+mO8xD9NfbHf fGUpZNFRiepJ901mh7QieCtvrGpn48mWTCUR7vdSSY+itYRevjZ8AwneVKLOHzv6Tg A3sukbIYQ8or9bL0vhocDL1Bmq+QXErxKeTh44lije21bms3jqAF8mPTsIsRPvldJi S6axVCZsITzfFht05TyZMHd02N6eUvgVcD3pGlpjMIEB1uQJ4A0/gjIIVZ1XsfO77P HjuPaL8Hv+mVZkAWwyORs9dpI822iNoHBhDG0Y7TJiRAWBnwL5hC1CfCfCQ9P3L6dn XqNDUQUsXADjw== From: Amitay Isaacs To: pdbg@lists.ozlabs.org Date: Thu, 1 Oct 2020 17:08:07 +1000 Message-Id: <20201001070814.102735-14-amitay@ozlabs.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201001070814.102735-1-amitay@ozlabs.org> References: <20201001070814.102735-1-amitay@ozlabs.org> MIME-Version: 1.0 Subject: [Pdbg] [PATCH v2 13/20] libpdbg: Update sbefifo chip-ops as per changes in p10 X-BeenThere: pdbg@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: "mailing list for https://github.com/open-power/pdbg development" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Amitay Isaacs Errors-To: pdbg-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Pdbg" Signed-off-by: Amitay Isaacs Reviewed-by: Joel Stanley --- libpdbg/sbefifo.c | 69 ++++++++++++++++++++++++++++++----------------- 1 file changed, 45 insertions(+), 24 deletions(-) diff --git a/libpdbg/sbefifo.c b/libpdbg/sbefifo.c index 63a37e9..1200919 100644 --- a/libpdbg/sbefifo.c +++ b/libpdbg/sbefifo.c @@ -253,9 +253,11 @@ static int sbefifo_pib_thread_op(struct pib *pib, uint32_t oper) thread_id = 0xf; /* Enforce special-wakeup for thread stop and sreset */ - if ((oper & 0xf) == SBEFIFO_INSN_OP_STOP || - (oper & 0xf) == SBEFIFO_INSN_OP_SRESET) - mode = 0x2; + if (sbefifo_proc(sctx) == SBEFIFO_PROC_P9) { + if ((oper & 0xf) == SBEFIFO_INSN_OP_STOP || + (oper & 0xf) == SBEFIFO_INSN_OP_SRESET) + mode = 0x2; + } return sbefifo_control_insn(sctx, core_id, thread_id, oper, mode); } @@ -285,6 +287,20 @@ static int sbefifo_pib_thread_sreset(struct pib *pib) return sbefifo_pib_thread_op(pib, SBEFIFO_INSN_OP_SRESET); } +static uint8_t sbefifo_core_id(struct sbefifo_context *sctx, struct thread *thread) +{ + struct pdbg_target *parent; + + if (sbefifo_proc(sctx) == SBEFIFO_PROC_P9) + /* P9 uses pervasive (chiplet) id as core-id */ + parent = pdbg_target_require_parent("chiplet", &thread->target); + else + /* P10 uses core id as core-id */ + parent = pdbg_target_require_parent("core", &thread->target); + + return pdbg_target_index(parent) & 0xff; +} + static int sbefifo_thread_probe(struct pdbg_target *target) { struct thread *thread = target_to_thread(target); @@ -300,21 +316,23 @@ static void sbefifo_thread_release(struct pdbg_target *target) static int sbefifo_thread_op(struct thread *thread, uint32_t oper) { - struct pdbg_target *chiplet = - pdbg_target_require_parent("chiplet", &thread->target); - struct pdbg_target *pib = pdbg_target_require_parent("pib", chiplet); + struct pdbg_target *pib = pdbg_target_require_parent("pib", &thread->target); struct sbefifo *sbefifo = pib_to_sbefifo(pib); struct sbefifo_context *sctx = sbefifo->get_sbefifo_context(sbefifo); uint8_t mode = 0; + uint8_t core_id; /* Enforce special-wakeup for thread stop and sreset */ - if ((oper & 0xf) == SBEFIFO_INSN_OP_STOP || - (oper & 0xf) == SBEFIFO_INSN_OP_SRESET) - mode = 0x2; + if (sbefifo_proc(sctx) == SBEFIFO_PROC_P9) { + if ((oper & 0xf) == SBEFIFO_INSN_OP_STOP || + (oper & 0xf) == SBEFIFO_INSN_OP_SRESET) + mode = 0x2; + } + + core_id = sbefifo_core_id(sctx, thread); - /* This chip-op requires core-id as pervasive (chiplet) id */ return sbefifo_control_insn(sctx, - pdbg_target_index(chiplet), + core_id, thread->id, oper, mode); @@ -347,20 +365,21 @@ static int sbefifo_thread_sreset(struct thread *thread) static int sbefifo_thread_getregs(struct thread *thread, struct thread_regs *regs) { - struct pdbg_target *chiplet = pdbg_target_require_parent("chiplet", &thread->target); - struct pdbg_target *pib = pdbg_target_require_parent("pib", chiplet); + struct pdbg_target *pib = pdbg_target_require_parent("pib", &thread->target); struct sbefifo *sbefifo = pib_to_sbefifo(pib); struct sbefifo_context *sctx = sbefifo->get_sbefifo_context(sbefifo); uint32_t reg_id[34]; uint64_t *value; + uint8_t core_id; int ret, i; for (i=0; i<32; i++) reg_id[i] = i; - /* This chip-op requires core-id as pervasive (chiplet) id */ + core_id = sbefifo_core_id(sctx, thread); + ret = sbefifo_register_get(sctx, - pdbg_target_index(chiplet), + core_id, thread->id, SBEFIFO_REGISTER_TYPE_GPR, reg_id, @@ -410,7 +429,7 @@ static int sbefifo_thread_getregs(struct thread *thread, struct thread_regs *reg reg_id[33] = SPR_PPR; ret = sbefifo_register_get(sctx, - pdbg_target_index(chiplet), + core_id, thread->id, SBEFIFO_REGISTER_TYPE_SPR, reg_id, @@ -461,16 +480,17 @@ static int sbefifo_thread_getregs(struct thread *thread, struct thread_regs *reg static int sbefifo_thread_get_reg(struct thread *thread, uint8_t reg_type, uint32_t reg_id, uint64_t *value) { - struct pdbg_target *chiplet = pdbg_target_require_parent("chiplet", &thread->target); - struct pdbg_target *pib = pdbg_target_require_parent("pib", chiplet); + struct pdbg_target *pib = pdbg_target_require_parent("pib", &thread->target); struct sbefifo *sbefifo = pib_to_sbefifo(pib); struct sbefifo_context *sctx = sbefifo->get_sbefifo_context(sbefifo); uint64_t *v; + uint8_t core_id; int ret; - /* This chip-op requires core-id as pervasive (chiplet) id */ + core_id = sbefifo_core_id(sctx, thread); + ret = sbefifo_register_get(sctx, - pdbg_target_index(chiplet), + core_id, thread->id, reg_type, ®_id, @@ -487,14 +507,15 @@ static int sbefifo_thread_get_reg(struct thread *thread, uint8_t reg_type, uint3 static int sbefifo_thread_put_reg(struct thread *thread, uint8_t reg_type, uint32_t reg_id, uint64_t value) { - struct pdbg_target *chiplet = pdbg_target_require_parent("chiplet", &thread->target); - struct pdbg_target *pib = pdbg_target_require_parent("pib", chiplet); + struct pdbg_target *pib = pdbg_target_require_parent("pib", &thread->target); struct sbefifo *sbefifo = pib_to_sbefifo(pib); struct sbefifo_context *sctx = sbefifo->get_sbefifo_context(sbefifo); + uint8_t core_id; + + core_id = sbefifo_core_id(sctx, thread); - /* This chip-op requires core-id as pervasive (chiplet) id */ return sbefifo_register_put(sctx, - pdbg_target_index(chiplet), + core_id, thread->id, reg_type, ®_id, From patchwork Thu Oct 1 07:08:08 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Amitay Isaacs X-Patchwork-Id: 1374880 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [203.11.71.2]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4C247M4rk3z9sVN for ; Thu, 1 Oct 2020 17:11:59 +1000 (AEST) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=ozlabs.org Authentication-Results: ozlabs.org; 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dkim-atps=neutral Received: from authenticated.ozlabs.org (localhost [127.0.0.1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by mail.ozlabs.org (Postfix) with ESMTPSA id 4C24795yqnz9sVT; Thu, 1 Oct 2020 17:11:49 +1000 (AEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ozlabs.org; s=201707; t=1601536314; bh=KcEIBZBBGB9tj9417fgh+hPlNqK/hfF20M65+PMywLI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=F3tbtg+NTnd54TSIO6n7ChPx1NLCvXzGZBnJSLeVM4rSr0NZNOJ2hLsbm4uWLKA7p MQvrTb2LS/zPI/6BoNuOhaOpqCbguyUJPR/k+lUkpR20VL7djKuQsbqkAyNMq+CZgi RcqQ+eozOXopDQf2TeI5OisZOoT8q7spj4uzFX1eAcpEOyfsekj/leVSQ39cnU2bC7 uu2lcqniULIYBZRqRkrAtItS6qYisLumd4W2MXuk4OmVV0C+LwB2Uq7O/Qi1uX57RX r3syH+HVje2TKz38xYaM1VrTR6f5iInr5VUqs+irvvZ3B4x2k2j9SEnTD8Syly+YwS poDYCnzxYxEUQ== From: Amitay Isaacs To: pdbg@lists.ozlabs.org Date: Thu, 1 Oct 2020 17:08:08 +1000 Message-Id: <20201001070814.102735-15-amitay@ozlabs.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201001070814.102735-1-amitay@ozlabs.org> References: <20201001070814.102735-1-amitay@ozlabs.org> MIME-Version: 1.0 Subject: [Pdbg] [PATCH v2 14/20] libsbefifo: Use proper cast X-BeenThere: pdbg@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: "mailing list for https://github.com/open-power/pdbg development" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Amitay Isaacs Errors-To: pdbg-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Pdbg" Signed-off-by: Amitay Isaacs Reviewed-by: Joel Stanley --- libsbefifo/cmd_control.c | 2 +- libsbefifo/cmd_scom.c | 6 ++++-- 2 files changed, 5 insertions(+), 3 deletions(-) diff --git a/libsbefifo/cmd_control.c b/libsbefifo/cmd_control.c index 4826b5d..e64f555 100644 --- a/libsbefifo/cmd_control.c +++ b/libsbefifo/cmd_control.c @@ -36,7 +36,7 @@ static int sbefifo_istep_execute_push(uint8_t major, uint8_t minor, uint8_t **bu cmd = SBEFIFO_CMD_CLASS_CONTROL | SBEFIFO_CMD_EXECUTE_ISTEP; - step = (major << 16) | minor; + step = ((uint32_t)major << 16) | (uint32_t)minor; msg[0] = htobe32(nwords); msg[1] = htobe32(cmd); diff --git a/libsbefifo/cmd_scom.c b/libsbefifo/cmd_scom.c index 935a00f..db8214d 100644 --- a/libsbefifo/cmd_scom.c +++ b/libsbefifo/cmd_scom.c @@ -139,7 +139,7 @@ int sbefifo_scom_put(struct sbefifo_context *sctx, uint64_t addr, uint64_t value static int sbefifo_scom_modify_push(uint64_t addr, uint64_t value, uint8_t operand, uint8_t **buf, uint32_t *buflen) { uint32_t *msg; - uint32_t nwords, cmd; + uint32_t nwords, cmd, oper; nwords = 7; *buflen = nwords * sizeof(uint32_t); @@ -149,9 +149,11 @@ static int sbefifo_scom_modify_push(uint64_t addr, uint64_t value, uint8_t opera cmd = SBEFIFO_CMD_CLASS_SCOM | SBEFIFO_CMD_MODIFY_SCOM; + oper = (uint32_t)operand; + msg[0] = htobe32(nwords); msg[1] = htobe32(cmd); - msg[2] = htobe32(operand); + msg[2] = htobe32(oper); msg[3] = htobe32(addr >> 32); msg[4] = htobe32(addr & 0xffffffff); msg[5] = htobe32(value >> 32); From patchwork Thu Oct 1 07:08:09 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Amitay Isaacs X-Patchwork-Id: 1374881 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [203.11.71.2]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4C247V6LNmz9sVL for ; Thu, 1 Oct 2020 17:12:06 +1000 (AEST) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=ozlabs.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; secure) header.d=ozlabs.org header.i=@ozlabs.org header.a=rsa-sha256 header.s=201707 header.b=R5jRdOcZ; dkim-atps=neutral Received: from bilbo.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 4C247V5fxQzDqTY for ; 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Thu, 1 Oct 2020 17:11:54 +1000 (AEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ozlabs.org; s=201707; t=1601536319; bh=oGtiiefrAZoRBMHrm1UATzfoEuNbxiEGtmpygPrM+rU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=R5jRdOcZADW04If0a+XG2YiQ6WIpm+7phSg41cN+Yq5jKixuEPSXdM+hO7R+tpLkH XXIcAl8XqOpuhrvRD1IsBZm3Rwlq2DaWzSMpAakGfBy/ACRA7E4+xSanOOldzE10cU JVDsevie447SeMGMR1BM26XdmHh42kGRpmUdIcCh10VuYmJk+rS7hxzCsz1olW5Kes zcPXruXaq4+blUfFjEwwSdDQa5DpfUhxShQ8q7ncBLZYbwtzD1CqutbG3IglGm7Ud3 /T/prLev2cPHDjNlPKyJyM3/7Q17NLM2RvqxQvmicdeFWLzmAcnC1DHJ/D0ApcNalU vVY2E/Y+61JtQ== From: Amitay Isaacs To: pdbg@lists.ozlabs.org Date: Thu, 1 Oct 2020 17:08:09 +1000 Message-Id: <20201001070814.102735-16-amitay@ozlabs.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201001070814.102735-1-amitay@ozlabs.org> References: <20201001070814.102735-1-amitay@ozlabs.org> MIME-Version: 1.0 Subject: [Pdbg] [PATCH v2 15/20] libsbefifo: Update sram get/put api X-BeenThere: pdbg@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: "mailing list for https://github.com/open-power/pdbg development" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Amitay Isaacs Errors-To: pdbg-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Pdbg" Since occsram_{get|put} api was not used for P9, rename it as per P10 change. Signed-off-by: Amitay Isaacs Reviewed-by: Joel Stanley --- libsbefifo/cmd_memory.c | 75 ++++++++++++++++++++++-------------- libsbefifo/libsbefifo.h | 5 ++- libsbefifo/sbefifo_private.h | 4 +- 3 files changed, 52 insertions(+), 32 deletions(-) diff --git a/libsbefifo/cmd_memory.c b/libsbefifo/cmd_memory.c index 47d4de7..4195a12 100644 --- a/libsbefifo/cmd_memory.c +++ b/libsbefifo/cmd_memory.c @@ -219,11 +219,11 @@ int sbefifo_mem_put(struct sbefifo_context *sctx, uint64_t addr, uint8_t *data, return rc; } -static int sbefifo_occsram_get_push(uint32_t addr, uint32_t size, uint8_t mode, uint8_t **buf, uint32_t *buflen) +static int sbefifo_sram_get_push(uint16_t chiplet_id, uint64_t addr, uint32_t size, uint8_t mode, uint8_t **buf, uint32_t *buflen) { uint32_t *msg; - uint32_t nwords, cmd; - uint32_t start_addr, end_addr; + uint32_t nwords, cmd, flags; + uint64_t start_addr, end_addr; uint32_t align, len; align = 8; @@ -233,29 +233,32 @@ static int sbefifo_occsram_get_push(uint32_t addr, uint32_t size, uint8_t mode, if (end_addr < start_addr) return EINVAL; - nwords = 5; + nwords = 6; *buflen = nwords * sizeof(uint32_t); msg = malloc(*buflen); if (!msg) return ENOMEM; - len = end_addr - start_addr; + len = (end_addr - start_addr) / 8; + + cmd = SBEFIFO_CMD_CLASS_MEMORY | SBEFIFO_CMD_GET_SRAM; - cmd = SBEFIFO_CMD_CLASS_MEMORY | SBEFIFO_CMD_GET_OCCSRAM; + flags = ((uint32_t)chiplet_id << 16 | (uint32_t)mode); msg[0] = htobe32(nwords); msg[1] = htobe32(cmd); - msg[2] = htobe32(mode); - msg[3] = htobe32(start_addr); - msg[4] = htobe32(len); + msg[2] = htobe32(flags); + msg[3] = htobe32(start_addr >> 32); + msg[4] = htobe32(start_addr & 0xffffffff); + msg[5] = htobe32(len); *buf = (uint8_t *)msg; return 0; } -static int sbefifo_occsram_get_pull(uint8_t *buf, uint32_t buflen, uint32_t addr, uint32_t size, uint8_t **data, uint32_t *data_len) +static int sbefifo_sram_get_pull(uint8_t *buf, uint32_t buflen, uint64_t addr, uint32_t size, uint8_t **data, uint32_t *data_len) { - uint32_t start_addr; + uint64_t start_addr; uint32_t align, offset; if (buflen < 4) @@ -278,19 +281,22 @@ static int sbefifo_occsram_get_pull(uint8_t *buf, uint32_t buflen, uint32_t addr return 0; } -int sbefifo_occsram_get(struct sbefifo_context *sctx, uint32_t addr, uint32_t size, uint8_t mode, uint8_t **data, uint32_t *data_len) +int sbefifo_sram_get(struct sbefifo_context *sctx, uint16_t chiplet_id, uint64_t addr, uint32_t size, uint8_t mode, uint8_t **data, uint32_t *data_len) { uint8_t *msg, *out; uint32_t msg_len, out_len; uint32_t len; int rc; - rc = sbefifo_occsram_get_push(addr, size, mode, &msg, &msg_len); + if (sctx->proc == SBEFIFO_PROC_P9) + return ENOSYS; + + rc = sbefifo_sram_get_push(chiplet_id, addr, size, mode, &msg, &msg_len); if (rc) return rc; - /* length is 5th word in the request */ - len = be32toh(*(uint32_t *)(msg + 16)); + /* length is 6th word in the request */ + len = be32toh(*(uint32_t *)(msg + 20)); out_len = len + 4; rc = sbefifo_operation(sctx, msg, msg_len, &out, &out_len); @@ -298,18 +304,19 @@ int sbefifo_occsram_get(struct sbefifo_context *sctx, uint32_t addr, uint32_t si if (rc) return rc; - rc = sbefifo_occsram_get_pull(out, out_len, addr, size, data, data_len); + rc = sbefifo_sram_get_pull(out, out_len, addr, size, data, data_len); if (out) free(out); return rc; } -static int sbefifo_occsram_put_push(uint32_t addr, uint8_t *data, uint32_t data_len, uint8_t mode, uint8_t **buf, uint32_t *buflen) +static int sbefifo_sram_put_push(uint16_t chiplet_id, uint64_t addr, uint8_t *data, uint32_t data_len, bool multicast, uint8_t mode, uint8_t **buf, uint32_t *buflen) { uint32_t *msg; - uint32_t nwords, cmd; - uint32_t align; + uint32_t nwords, cmd, flags; + uint32_t align, len; + uint8_t multicast_bit; align = 8; @@ -319,26 +326,35 @@ static int sbefifo_occsram_put_push(uint32_t addr, uint8_t *data, uint32_t data_ if (data_len & (align-1)) return EINVAL; - nwords = 5 + data_len/4; + nwords = 6 + data_len/4; *buflen = nwords * sizeof(uint32_t); msg = malloc(*buflen); if (!msg) return ENOMEM; - cmd = SBEFIFO_CMD_CLASS_MEMORY | SBEFIFO_CMD_PUT_OCCSRAM; + multicast_bit = multicast ? 0x80 : 0x00; + + cmd = SBEFIFO_CMD_CLASS_MEMORY | SBEFIFO_CMD_PUT_SRAM; + + flags = ((uint32_t)chiplet_id << 16) | + ((uint32_t)multicast_bit << 8) | + (uint32_t)mode; + + len = data_len / 8; msg[0] = htobe32(nwords); msg[1] = htobe32(cmd); - msg[2] = htobe32(mode); - msg[3] = htobe32(addr); - msg[4] = htobe32(data_len); + msg[2] = htobe32(flags); + msg[3] = htobe32(addr >> 32); + msg[4] = htobe32(addr & 0xffffffff); + msg[5] = htobe32(len); memcpy(&msg[5], data, data_len); *buf = (uint8_t *)msg; return 0; } -static int sbefifo_occsram_put_pull(uint8_t *buf, uint32_t buflen) +static int sbefifo_sram_put_pull(uint8_t *buf, uint32_t buflen) { if (buflen != sizeof(uint32_t)) return EPROTO; @@ -346,13 +362,16 @@ static int sbefifo_occsram_put_pull(uint8_t *buf, uint32_t buflen) return 0; } -int sbefifo_occsram_put(struct sbefifo_context *sctx, uint32_t addr, uint8_t *data, uint32_t data_len, uint8_t mode) +int sbefifo_sram_put(struct sbefifo_context *sctx, uint16_t chiplet_id, uint64_t addr, uint8_t *data, uint32_t data_len, bool multicast, uint8_t mode) { uint8_t *msg, *out; uint32_t msg_len, out_len; int rc; - rc = sbefifo_occsram_put_push(addr, data, data_len, mode, &msg, &msg_len); + if (sctx->proc == SBEFIFO_PROC_P9) + return ENOSYS; + + rc = sbefifo_sram_put_push(chiplet_id, addr, data, data_len, multicast, mode, &msg, &msg_len); if (rc) return rc; @@ -362,7 +381,7 @@ int sbefifo_occsram_put(struct sbefifo_context *sctx, uint32_t addr, uint8_t *da if (rc) return rc; - rc = sbefifo_occsram_put_pull(out, out_len); + rc = sbefifo_sram_put_pull(out, out_len); if (out) free(out); diff --git a/libsbefifo/libsbefifo.h b/libsbefifo/libsbefifo.h index e149de5..7c85c25 100644 --- a/libsbefifo/libsbefifo.h +++ b/libsbefifo/libsbefifo.h @@ -18,6 +18,7 @@ #define __LIBSBEFIFO_H__ #include +#include /* * libsbefifo implements SBE interfaces available via SBEFIFO device. The @@ -152,8 +153,8 @@ int sbefifo_mem_put(struct sbefifo_context *sctx, uint64_t addr, uint8_t *data, #define SBEFIFO_MEMORY_MODE_DEBUG 0x02 #define SBEFIFO_MEMORY_MODE_CIRCULAR 0x03 -int sbefifo_occsram_get(struct sbefifo_context *sctx, uint32_t addr, uint32_t size, uint8_t mode, uint8_t **data, uint32_t *data_len); -int sbefifo_occsram_put(struct sbefifo_context *sctx, uint32_t addr, uint8_t *data, uint32_t data_len, uint8_t mode); +int sbefifo_sram_get(struct sbefifo_context *sctx, uint16_t chiplet_id, uint64_t addr, uint32_t size, uint8_t mode, uint8_t **data, uint32_t *data_len); +int sbefifo_sram_put(struct sbefifo_context *sctx, uint16_t chiplet_id, uint64_t addr, uint8_t *data, uint32_t data_len, bool multicast, uint8_t mode); #define SBEFIFO_REGISTER_TYPE_GPR 0x0 #define SBEFIFO_REGISTER_TYPE_SPR 0x1 diff --git a/libsbefifo/sbefifo_private.h b/libsbefifo/sbefifo_private.h index 5c9b10a..d3f6a8b 100644 --- a/libsbefifo/sbefifo_private.h +++ b/libsbefifo/sbefifo_private.h @@ -39,8 +39,8 @@ #define SBEFIFO_CMD_CLASS_MEMORY 0xA400 #define SBEFIFO_CMD_GET_MEMORY 0x01 #define SBEFIFO_CMD_PUT_MEMORY 0x02 -#define SBEFIFO_CMD_GET_OCCSRAM 0x03 -#define SBEFIFO_CMD_PUT_OCCSRAM 0x04 +#define SBEFIFO_CMD_GET_SRAM 0x03 +#define SBEFIFO_CMD_PUT_SRAM 0x04 #define SBEFIFO_CMD_CLASS_REGISTER 0xA500 #define SBEFIFO_CMD_GET_REGISTER 0x01 From patchwork Thu Oct 1 07:08:10 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Amitay Isaacs X-Patchwork-Id: 1374882 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [203.11.71.2]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4C247Z6XKPz9sVT for ; Thu, 1 Oct 2020 17:12:10 +1000 (AEST) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=ozlabs.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; secure) header.d=ozlabs.org header.i=@ozlabs.org header.a=rsa-sha256 header.s=201707 header.b=HCmu/rw5; dkim-atps=neutral Received: from bilbo.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 4C247Z56XvzDqRD for ; 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Thu, 1 Oct 2020 17:12:00 +1000 (AEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ozlabs.org; s=201707; t=1601536324; bh=0iMSjzjijOWrlJcNeJaEeNNugWY4Ln2WUJYb8L+dP74=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=HCmu/rw5djoL6AFdyUPSz1vviVxPo1pFfTrGIy4A5MEXsd6yPz6x18/DiApRkkJ6i h18MGJgoZJDAwuajHyFhYwdCwq6ZuqRY71fLhUOGFnOPMQeL/GETIfrrmD8J6tQxLJ gzK9bHhV4mb+NSBUtW6boazcliIP7rKD+Acsa1l8mcgK3qJ7X6bewZMTHhTWuIeQQ2 zOSIgM1KX69pL2lpUzWMgNa1dBilBUNCl2qJ5VECidVYGs55/G4z2kCosNUmv3O7/v OkLlkUDdYHB4vcVmatePPPyzIUHfR8SmSxuszRIUshK6SIWevsaMgV0KVNUaVB7gLM RFrzTBvtlmzEQ== From: Amitay Isaacs To: pdbg@lists.ozlabs.org Date: Thu, 1 Oct 2020 17:08:10 +1000 Message-Id: <20201001070814.102735-17-amitay@ozlabs.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201001070814.102735-1-amitay@ozlabs.org> References: <20201001070814.102735-1-amitay@ozlabs.org> MIME-Version: 1.0 Subject: [Pdbg] [PATCH v2 16/20] libsbefifo: Add new chip-ops for hw register get/put X-BeenThere: pdbg@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: "mailing list for https://github.com/open-power/pdbg development" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Amitay Isaacs Errors-To: pdbg-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Pdbg" Signed-off-by: Amitay Isaacs Reviewed-by: Joel Stanley --- libsbefifo/cmd_register.c | 131 +++++++++++++++++++++++++++++++++++ libsbefifo/libsbefifo.h | 3 + libsbefifo/sbefifo_private.h | 2 + 3 files changed, 136 insertions(+) diff --git a/libsbefifo/cmd_register.c b/libsbefifo/cmd_register.c index 060d3dc..6c3f336 100644 --- a/libsbefifo/cmd_register.c +++ b/libsbefifo/cmd_register.c @@ -165,3 +165,134 @@ int sbefifo_register_put(struct sbefifo_context *sctx, uint8_t core_id, uint8_t return rc; } + +static int sbefifo_hw_register_get_push(uint8_t target_type, uint8_t instance_id, uint64_t reg_id, uint8_t **buf, uint32_t *buflen) +{ + uint32_t *msg; + uint32_t nwords, cmd; + uint32_t target; + + nwords = 5; + *buflen = nwords * sizeof(uint32_t); + msg = malloc(*buflen); + if (!msg) + return ENOMEM; + + cmd = SBEFIFO_CMD_CLASS_REGISTER | SBEFIFO_CMD_GET_HW_REGISTER; + + target = ((uint32_t)(target_type & 0xff) << 16) | + ((uint32_t)(instance_id & 0xff)); + + msg[0] = htobe32(nwords); + msg[1] = htobe32(cmd); + msg[2] = htobe32(target); + msg[3] = htobe32(reg_id >> 32); + msg[4] = htobe32(reg_id & 0xffffffff); + + *buf = (uint8_t *)msg; + return 0; +} + +static int sbefifo_hw_register_get_pull(uint8_t *buf, uint32_t buflen, uint64_t *value) +{ + uint32_t val1, val2; + + if (buflen != 8) + return EPROTO; + + val1 = be32toh(*(uint32_t *) &buf[0]); + val2 = be32toh(*(uint32_t *) &buf[4]); + + *value = ((uint64_t)val1 << 32) | (uint64_t)val2; + + return 0; +} + +int sbefifo_hw_register_get(struct sbefifo_context *sctx, uint8_t target_type, uint8_t instance_id, uint64_t reg_id, uint64_t *value) +{ + uint8_t *msg, *out; + uint32_t msg_len, out_len; + int rc; + + if (sctx->proc == SBEFIFO_PROC_P9) + return ENOSYS; + + rc = sbefifo_hw_register_get_push(target_type, instance_id, reg_id, &msg, &msg_len); + if (rc) + return rc; + + out_len = 8; + rc = sbefifo_operation(sctx, msg, msg_len, &out, &out_len); + free(msg); + if (rc) + return rc; + + rc = sbefifo_hw_register_get_pull(out, out_len, value); + if (out) + free(out); + + return rc; +} + +static int sbefifo_hw_register_put_push(uint8_t target_type, uint8_t instance_id, uint64_t reg_id, uint64_t value, uint8_t **buf, uint32_t *buflen) +{ + uint32_t *msg; + uint32_t nwords, cmd; + uint32_t target; + + nwords = 7; + *buflen = nwords * sizeof(uint32_t); + msg = malloc(*buflen); + if (!msg) + return ENOMEM; + + cmd = SBEFIFO_CMD_CLASS_REGISTER | SBEFIFO_CMD_PUT_HW_REGISTER; + + target = ((uint32_t)(target_type & 0xff) << 16) | + ((uint32_t)(instance_id & 0xff)); + + msg[0] = htobe32(nwords); + msg[1] = htobe32(cmd); + msg[2] = htobe32(target); + msg[3] = htobe32(reg_id >> 32); + msg[4] = htobe32(reg_id & 0xffffffff); + msg[5] = htobe32(value >> 32); + msg[6] = htobe32(value & 0xffffffff); + + *buf = (uint8_t *)msg; + return 0; +} + +static int sbefifo_hw_register_put_pull(uint8_t *buf, uint32_t buflen) +{ + if (buflen != 0) + return EPROTO; + + return 0; +} + +int sbefifo_hw_register_put(struct sbefifo_context *sctx, uint8_t target_type, uint8_t instance_id, uint64_t reg_id, uint64_t value) +{ + uint8_t *msg, *out; + uint32_t msg_len, out_len; + int rc; + + if (sctx->proc == SBEFIFO_PROC_P9) + return ENOSYS; + + rc = sbefifo_hw_register_put_push(target_type, instance_id, reg_id, value, &msg, &msg_len); + if (rc) + return rc; + + out_len = 0; + rc = sbefifo_operation(sctx, msg, msg_len, &out, &out_len); + free(msg); + if (rc) + return rc; + + rc = sbefifo_hw_register_put_pull(out, out_len); + if (out) + free(out); + + return rc; +} diff --git a/libsbefifo/libsbefifo.h b/libsbefifo/libsbefifo.h index 7c85c25..4d6b016 100644 --- a/libsbefifo/libsbefifo.h +++ b/libsbefifo/libsbefifo.h @@ -163,6 +163,9 @@ int sbefifo_sram_put(struct sbefifo_context *sctx, uint16_t chiplet_id, uint64_t int sbefifo_register_get(struct sbefifo_context *sctx, uint8_t core_id, uint8_t thread_id, uint8_t reg_type, uint32_t *reg_id, uint8_t reg_count, uint64_t **value); int sbefifo_register_put(struct sbefifo_context *sctx, uint8_t core_id, uint8_t thread_id, uint8_t reg_type, uint32_t *reg_id, uint8_t reg_count, uint64_t *value); +int sbefifo_hw_register_get(struct sbefifo_context *sctx, uint8_t target_type, uint8_t instance_id, uint64_t reg_id, uint64_t *value); +int sbefifo_hw_register_put(struct sbefifo_context *sctx, uint8_t target_type, uint8_t instance_id, uint64_t reg_id, uint64_t value); + int sbefifo_control_fast_array(struct sbefifo_context *sctx, uint16_t target_type, uint8_t chiplet_id, uint8_t mode, uint64_t clock_cycle); int sbefifo_control_trace_array(struct sbefifo_context *sctx, uint16_t target_type, uint8_t chiplet_id, uint16_t array_id, uint16_t operation, uint8_t **trace_data, uint32_t *trace_data_len); diff --git a/libsbefifo/sbefifo_private.h b/libsbefifo/sbefifo_private.h index d3f6a8b..e49f673 100644 --- a/libsbefifo/sbefifo_private.h +++ b/libsbefifo/sbefifo_private.h @@ -45,6 +45,8 @@ #define SBEFIFO_CMD_CLASS_REGISTER 0xA500 #define SBEFIFO_CMD_GET_REGISTER 0x01 #define SBEFIFO_CMD_PUT_REGISTER 0x02 +#define SBEFIFO_CMD_GET_HW_REGISTER 0x03 +#define SBEFIFO_CMD_PUT_HW_REGISTER 0x04 #define SBEFIFO_CMD_CLASS_ARRAY 0xA600 #define SBEFIFO_CMD_FAST_ARRAY 0x01 From patchwork Thu Oct 1 07:08:11 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Amitay Isaacs X-Patchwork-Id: 1374883 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [203.11.71.2]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4C247h05l8z9sVK for ; Thu, 1 Oct 2020 17:12:16 +1000 (AEST) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=ozlabs.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; secure) header.d=ozlabs.org header.i=@ozlabs.org header.a=rsa-sha256 header.s=201707 header.b=bkd9EJns; dkim-atps=neutral Received: from bilbo.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 4C247g6Nt0zDqTb for ; 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Thu, 1 Oct 2020 17:12:04 +1000 (AEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ozlabs.org; s=201707; t=1601536329; bh=/wdhj0+M6/5cW/nlmAElOm2p4gyFn9gizgGdwHFw78s=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=bkd9EJnsjAMuohJKbs60KBZEfGNcDolhLarn93At59CynmdqgLzCZ9iE0toqpRKiz x7S8fJ14I3q3W8HIobcJb1Acsynf1b0uDOOISSTzHKB/n7IZWWR4BoR7PaNt2OgC79 8yv5k6wNnLp6ouMGLKNbD80VU+D3Cw7siEJRxMGdvU5qMsZArxLMYrrTeQGsDXmp6/ +2V/bsdE7+vGHooJmqHhRjC6BGSyqt5a4FMGG5M4xbUx7LOC8k7/xLQpQVzj03dH79 5ADvL+BXlWmUUOBGUwsaS2+Q0Z7eZjY5kswJzGKygkaCZEG4QrAXgoIXbHcMZ2Ue0N igc75+t0EtNTw== From: Amitay Isaacs To: pdbg@lists.ozlabs.org Date: Thu, 1 Oct 2020 17:08:11 +1000 Message-Id: <20201001070814.102735-18-amitay@ozlabs.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201001070814.102735-1-amitay@ozlabs.org> References: <20201001070814.102735-1-amitay@ozlabs.org> MIME-Version: 1.0 Subject: [Pdbg] [PATCH v2 17/20] libpdbg: Add ocmb hwunit X-BeenThere: pdbg@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: "mailing list for https://github.com/open-power/pdbg development" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Amitay Isaacs Errors-To: pdbg-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Pdbg" Signed-off-by: Amitay Isaacs Reviewed-by: Joel Stanley --- libpdbg/hwunit.h | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/libpdbg/hwunit.h b/libpdbg/hwunit.h index 52fdaf0..f1f164e 100644 --- a/libpdbg/hwunit.h +++ b/libpdbg/hwunit.h @@ -320,4 +320,12 @@ struct mcc { struct pdbg_target target; }; #define target_to_mcc(x) container_of(x, struct mcc, target) + +struct ocmb { + struct pdbg_target target; + int (*getscom)(struct ocmb *, uint64_t, uint64_t *); + int (*putscom)(struct ocmb *, uint64_t, uint64_t); +}; +#define target_to_ocmb(x) container_of(x, struct ocmb, target); + #endif /* __HWUNIT_H */ From patchwork Thu Oct 1 07:08:12 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Amitay Isaacs X-Patchwork-Id: 1374884 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [203.11.71.2]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4C247l55Pvz9sVM for ; Thu, 1 Oct 2020 17:12:19 +1000 (AEST) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=ozlabs.org Authentication-Results: ozlabs.org; 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dkim-atps=neutral Received: from authenticated.ozlabs.org (localhost [127.0.0.1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by mail.ozlabs.org (Postfix) with ESMTPSA id 4C247Z1ffdz9sVL; Thu, 1 Oct 2020 17:12:09 +1000 (AEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ozlabs.org; s=201707; t=1601536332; bh=QRpfrOQ/dqWlr/xtjof2onxyzisi3vXictZXfkwFrLw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=LJjVT/AZXAQ9JvAP/Au1Ugcn3hvWHcTPxgsxWlpJcSYAyTq7WdEx1QCHFYfKp3Ahz OjLNISBQZ7SwnuV1k/Ldpf9TfSg8y/0LE9T/ruv7J7++nmvkK7q6nxNTsmwOfzeMtd y4MkdJIgSv7JMcEKeURWQnylepgrxVjXh8kaz56ly6+Y++cSPrua8p4WeZyX0aQa4c 4Fp/CGMtBe+Px9hx3XBp6hqGxp5+Dr7i05gBnQSKkS0HwCD6Lr8fGt52Qou8kDX2td 8/6fPopACi8tjYM21+hwejhYYaNHvPA1A5s8YzA2EwSB2/gudb6rlelvsTaKOtozik A2iHvxrALtvjw== From: Amitay Isaacs To: pdbg@lists.ozlabs.org Date: Thu, 1 Oct 2020 17:08:12 +1000 Message-Id: <20201001070814.102735-19-amitay@ozlabs.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201001070814.102735-1-amitay@ozlabs.org> References: <20201001070814.102735-1-amitay@ozlabs.org> MIME-Version: 1.0 Subject: [Pdbg] [PATCH v2 18/20] libpdbg: Add sbefifo based implementation of ocmb getscom/putscom X-BeenThere: pdbg@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: "mailing list for https://github.com/open-power/pdbg development" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Amitay Isaacs Errors-To: pdbg-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Pdbg" Signed-off-by: Amitay Isaacs Reviewed-by: Joel Stanley --- Makefile.am | 1 + libpdbg/ocmb.c | 85 ++++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 86 insertions(+) create mode 100644 libpdbg/ocmb.c diff --git a/Makefile.am b/Makefile.am index d902863..a970ab9 100644 --- a/Makefile.am +++ b/Makefile.am @@ -178,6 +178,7 @@ libpdbg_la_SOURCES = \ libpdbg/kernel.c \ libpdbg/libpdbg.c \ libpdbg/libpdbg.h \ + libpdbg/ocmb.c \ libpdbg/operations.h \ libpdbg/p8chip.c \ libpdbg/p9chip.c \ diff --git a/libpdbg/ocmb.c b/libpdbg/ocmb.c new file mode 100644 index 0000000..ef929f9 --- /dev/null +++ b/libpdbg/ocmb.c @@ -0,0 +1,85 @@ +/* Copyright 2020 IBM Corp. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + * implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include + +#include + +#include "hwunit.h" + +static struct sbefifo *ocmb_to_sbefifo(struct ocmb *ocmb) +{ + struct pdbg_target *pib = pdbg_target_require_parent("pib", &ocmb->target); + struct pdbg_target *target; + struct sbefifo *sbefifo = NULL; + + pdbg_for_each_class_target("sbefifo", target) { + if (pdbg_target_index(target) == pdbg_target_index(pib)) { + sbefifo = target_to_sbefifo(target); + break; + } + } + + assert(sbefifo); + + return sbefifo; +} + +static int sbefifo_ocmb_getscom(struct ocmb *ocmb, uint64_t addr, uint64_t *value) +{ + struct sbefifo *sbefifo = ocmb_to_sbefifo(ocmb); + struct sbefifo_context *sctx = sbefifo->get_sbefifo_context(sbefifo); + uint8_t instance_id; + + instance_id = pdbg_target_index(&ocmb->target) & 0xff; + + return sbefifo_hw_register_get(sctx, + SBEFIFO_TARGET_TYPE_OCMB, + instance_id, + addr, + value); +} + +static int sbefifo_ocmb_putscom(struct ocmb *ocmb, uint64_t addr, uint64_t value) +{ + struct sbefifo *sbefifo = ocmb_to_sbefifo(ocmb); + struct sbefifo_context *sctx = sbefifo->get_sbefifo_context(sbefifo); + uint8_t instance_id; + + instance_id = pdbg_target_index(&ocmb->target) & 0xff; + + return sbefifo_hw_register_put(sctx, + SBEFIFO_TARGET_TYPE_OCMB, + instance_id, + addr, + value); +} + +static struct ocmb sbefifo_ocmb = { + .target = { + .name = "SBE FIFO Chip-op based OCMB", + .compatible = "ibm,power-ocmb", + .class = "ocmb", + }, + .getscom = sbefifo_ocmb_getscom, + .putscom = sbefifo_ocmb_putscom, +}; +DECLARE_HW_UNIT(sbefifo_ocmb); + +__attribute__((constructor)) +static void register_ocmb(void) +{ + pdbg_hwunit_register(PDBG_DEFAULT_BACKEND, &sbefifo_ocmb_hw_unit); +} From patchwork Thu Oct 1 07:08:13 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Amitay Isaacs X-Patchwork-Id: 1374885 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4C247q4Xmdz9sVH for ; Thu, 1 Oct 2020 17:12:23 +1000 (AEST) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=ozlabs.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; secure) header.d=ozlabs.org header.i=@ozlabs.org header.a=rsa-sha256 header.s=201707 header.b=QYd0AAli; dkim-atps=neutral Received: from bilbo.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 4C247q3Fn1zDqVS for ; Thu, 1 Oct 2020 17:12:23 +1000 (AEST) X-Original-To: pdbg@lists.ozlabs.org Delivered-To: pdbg@lists.ozlabs.org Received: from ozlabs.org (bilbo.ozlabs.org [203.11.71.1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 4C247j1XJ9zDqTp for ; Thu, 1 Oct 2020 17:12:17 +1000 (AEST) Authentication-Results: lists.ozlabs.org; dmarc=pass (p=none dis=none) header.from=ozlabs.org Authentication-Results: lists.ozlabs.org; dkim=pass (2048-bit key; secure) header.d=ozlabs.org header.i=@ozlabs.org header.a=rsa-sha256 header.s=201707 header.b=QYd0AAli; dkim-atps=neutral Received: from authenticated.ozlabs.org (localhost [127.0.0.1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by mail.ozlabs.org (Postfix) with ESMTPSA id 4C247f2hFMz9sVT; Thu, 1 Oct 2020 17:12:13 +1000 (AEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ozlabs.org; s=201707; t=1601536336; bh=71E33fv1ti80a+QXFTdsRzJI6Qzqpet7wqib+soD4Uk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=QYd0AAliB5Nk2kHjjV4KkeufJPSNnYoVHjURD4NV6ukdIwRigZ54yF9FYgMXqPtIr +sKXeW8pjEWGbos+BUDN92kON8sLog1I3gy/4u57TN52koddaUfcTEfJ9bOWTbBVJr nhzAtbyhWacY1ujeYby4FKoZM1mPmngvyXtjf5T5jcu2TOjUnSoVTRHiB2ApPfxhar b/GdFhlzpyTdCBYI5Egg9lhvLcHxqwVJWPUisuhPCLiItEGcA7kAwdcMa3569EyZxV R36g5uO/mXenD+ICygJShZznjmqVeMHh1ap4ugBgk3VGZ8KSDk2EoNKxGkasSe8Ot1 11MxcwtEm/OjA== From: Amitay Isaacs To: pdbg@lists.ozlabs.org Date: Thu, 1 Oct 2020 17:08:13 +1000 Message-Id: <20201001070814.102735-20-amitay@ozlabs.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201001070814.102735-1-amitay@ozlabs.org> References: <20201001070814.102735-1-amitay@ozlabs.org> MIME-Version: 1.0 Subject: [Pdbg] [PATCH v2 19/20] libpdbg: Add ocmb_{getscom/putscom} api X-BeenThere: pdbg@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: "mailing list for https://github.com/open-power/pdbg development" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Amitay Isaacs Errors-To: pdbg-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Pdbg" Signed-off-by: Amitay Isaacs Reviewed-by: Joel Stanley --- libpdbg/libpdbg.h | 22 ++++++++++++++++++++++ libpdbg/target.c | 38 ++++++++++++++++++++++++++++++++++++++ 2 files changed, 60 insertions(+) diff --git a/libpdbg/libpdbg.h b/libpdbg/libpdbg.h index 2630fd7..08894d6 100644 --- a/libpdbg/libpdbg.h +++ b/libpdbg/libpdbg.h @@ -1329,6 +1329,28 @@ int sbe_mpipl_continue(struct pdbg_target *target); */ int sbe_mpipl_get_ti_info(struct pdbg_target *target, uint8_t **data, uint32_t *data_len); +/** + * @brief Read a OCMB SCOM register + * + * @param[in] target ocmb target + * @param[in] addr the address offset relative to target + * @param[out] val the read data + * + * @return 0 on success, -1 on failure + */ +int ocmb_getscom(struct pdbg_target *target, uint64_t addr, uint64_t *val); + +/** + * @brief Write a OCMB SCOM register + * + * @param[in] target ocmb target + * @param[in] addr the address offset relative to target + * @param[in] val the write data + * + * @return 0 on success, -1 on failure + */ +int ocmb_putscom(struct pdbg_target *target, uint64_t addr, uint64_t val); + /** * @brief Type for specifying a progress callback for long running * operations diff --git a/libpdbg/target.c b/libpdbg/target.c index 8a7d1a6..89006d0 100644 --- a/libpdbg/target.c +++ b/libpdbg/target.c @@ -455,6 +455,44 @@ int sbe_mpipl_get_ti_info(struct pdbg_target *target, uint8_t **data, uint32_t * return chipop->mpipl_get_ti_info(chipop, data, data_len); } +int ocmb_getscom(struct pdbg_target *target, uint64_t addr, uint64_t *val) +{ + struct ocmb *ocmb; + + assert(pdbg_target_is_class(target, "ocmb")); + + if (pdbg_target_status(target) != PDBG_TARGET_ENABLED) + return -1; + + ocmb = target_to_ocmb(target); + + if (!ocmb->getscom) { + PR_ERROR("getscom() not implemented for the target\n"); + return -1; + } + + return ocmb->getscom(ocmb, addr, val); +} + +int ocmb_putscom(struct pdbg_target *target, uint64_t addr, uint64_t val) +{ + struct ocmb *ocmb; + + assert(pdbg_target_is_class(target, "ocmb")); + + if (pdbg_target_status(target) != PDBG_TARGET_ENABLED) + return -1; + + ocmb = target_to_ocmb(target); + + if (!ocmb->putscom) { + PR_ERROR("putscom() not implemented for the target\n"); + return -1; + } + + return ocmb->putscom(ocmb, addr, val); +} + uint32_t sbe_ffdc_get(struct pdbg_target *target, uint8_t **ffdc, uint32_t *ffdc_len) { struct chipop *chipop; From patchwork Thu Oct 1 07:08:14 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Amitay Isaacs X-Patchwork-Id: 1374886 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4C247w4pwlz9sVH for ; Thu, 1 Oct 2020 17:12:28 +1000 (AEST) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=ozlabs.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; secure) header.d=ozlabs.org header.i=@ozlabs.org header.a=rsa-sha256 header.s=201707 header.b=X9SF2I14; dkim-atps=neutral Received: from bilbo.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 4C247v5GpbzDqTp for ; Thu, 1 Oct 2020 17:12:27 +1000 (AEST) X-Original-To: pdbg@lists.ozlabs.org Delivered-To: pdbg@lists.ozlabs.org Received: from ozlabs.org (bilbo.ozlabs.org [IPv6:2401:3900:2:1::2]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 4C247n2SHTzDqTY for ; Thu, 1 Oct 2020 17:12:21 +1000 (AEST) Authentication-Results: lists.ozlabs.org; dmarc=pass (p=none dis=none) header.from=ozlabs.org Authentication-Results: lists.ozlabs.org; dkim=pass (2048-bit key; secure) header.d=ozlabs.org header.i=@ozlabs.org header.a=rsa-sha256 header.s=201707 header.b=X9SF2I14; dkim-atps=neutral Received: from authenticated.ozlabs.org (localhost [127.0.0.1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by mail.ozlabs.org (Postfix) with ESMTPSA id 4C247k39fdz9sVK; Thu, 1 Oct 2020 17:12:18 +1000 (AEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ozlabs.org; s=201707; t=1601536340; bh=km5olN075QsEY9nU0QDIkPS15SoAbhEF39eCLtM5QPw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=X9SF2I14Dci9O29wTl0//w2Ywqz64SjRZYI8qgVjdiqdu8C5d52bqWtRnyUTvMtSR IxUvOHIrifrPL5IoJeqKbrIoVb3CtktTCH1QRBYEQhOnKxDfOP+VH2Bbb3PfbbatuE WCvCeYraV3QiXZ/8l06BUeOYobJ+OgHd3P6TMuuT1y3LyBp/qR8gLdKVZSeECVtd4d d9fTdDrdUbvfaF3GYCMD57yxxllGHSF/4nd+GUoPucrrbh4kYPrFm36NlomAxvJB+d WP1uX1nVk0t8Fr1v/PT4igjkN+4LJw4OjhjZpcPkh7BUzknw8tIyUsU9+a2cma2JXs cfgDSir86Wt9A== From: Amitay Isaacs To: pdbg@lists.ozlabs.org Date: Thu, 1 Oct 2020 17:08:14 +1000 Message-Id: <20201001070814.102735-21-amitay@ozlabs.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201001070814.102735-1-amitay@ozlabs.org> References: <20201001070814.102735-1-amitay@ozlabs.org> MIME-Version: 1.0 Subject: [Pdbg] [PATCH v2 20/20] dts: Add ocmb targets to p10.dts X-BeenThere: pdbg@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: "mailing list for https://github.com/open-power/pdbg development" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Amitay Isaacs Errors-To: pdbg-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Pdbg" Signed-off-by: Amitay Isaacs Reviewed-by: Joel Stanley --- p10.dts.m4 | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/p10.dts.m4 b/p10.dts.m4 index 76bbc4d..15ecc08 100644 --- a/p10.dts.m4 +++ b/p10.dts.m4 @@ -217,6 +217,20 @@ define(`id', eval(`$2 % 2'))dnl index = <$2>; ') +dnl +dnl OCMB([index]) +dnl +define(`OCMB', +` + CONCAT(ocmb@, $1) { + #address-cells = <0x02>; + #size-cells = <0x01>; + reg = <0x00 0x08010000 0x3c00>; + compatible = "ibm,power-ocmb", "ibm,power10-ocmb"; + index = <$1>; + }; +') + dnl dnl PEC_([chiplet], [index]) dnl @@ -341,14 +355,18 @@ define(`CHIP', MI_(c,0) MCC_(c,0) OMI_(c,0) + OCMB(0) }; OMI_(c,1) + OCMB(1) }; }; MCC_(c,1) OMI_(c,2) + OCMB(2) }; OMI_(c,3) + OCMB(3) }; }; }; @@ -362,14 +380,18 @@ define(`CHIP', MI_(d,1) MCC_(d,2) OMI_(d,4) + OCMB(4) }; OMI_(d,5) + OCMB(5) }; }; MCC_(d,3) OMI_(d,6) + OCMB(6) }; OMI_(d,7) + OCMB(7) }; }; };