From patchwork Tue Sep 29 13:46:40 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Crystal Guo X-Patchwork-Id: 1373428 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=mediatek.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=mediatek.com header.i=@mediatek.com header.a=rsa-sha256 header.s=dk header.b=DwLJyhUo; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4C11045P2Rz9sTC for ; Tue, 29 Sep 2020 23:47:00 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730211AbgI2Nq7 (ORCPT ); Tue, 29 Sep 2020 09:46:59 -0400 Received: from mailgw01.mediatek.com ([210.61.82.183]:58262 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1728844AbgI2Nq7 (ORCPT ); Tue, 29 Sep 2020 09:46:59 -0400 X-UUID: 81e6a7b9132f4f48a38f97897c513b27-20200929 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=WmWSE7IzhJl4QSCNXojtBre/0v5HhT1SrIhjLveOb40=; b=DwLJyhUovKVB9chSFmABya5T24wW9pOntpI3rIuqRSBYuDnds0Msn3mVO+ESZG1L0KowBZxdkeFDuMm/q20qZD/Q+PT8+RgKyTtUDkMmVVYypscu7vf9IyrfNwpg+c9SrSgjTXGoLOw6sIyi4CyDkshyfp71RCTjOsb/AeF+fRU=; X-UUID: 81e6a7b9132f4f48a38f97897c513b27-20200929 Received: from mtkcas10.mediatek.inc [(172.21.101.39)] by mailgw01.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.14 Build 0819 with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1416023101; Tue, 29 Sep 2020 21:46:53 +0800 Received: from MTKCAS06.mediatek.inc (172.21.101.30) by mtkmbs05n2.mediatek.inc (172.21.101.140) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 29 Sep 2020 21:46:50 +0800 Received: from localhost.localdomain (10.17.3.153) by MTKCAS06.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 29 Sep 2020 21:46:49 +0800 From: Crystal Guo To: , , CC: , , , , , , , , , , , Crystal Guo Subject: [v5,1/3] dt-binding: reset-controller: mediatek: add YAML schemas Date: Tue, 29 Sep 2020 21:46:40 +0800 Message-ID: <20200929134642.26561-2-crystal.guo@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20200929134642.26561-1-crystal.guo@mediatek.com> References: <20200929134642.26561-1-crystal.guo@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add a YAML documentation for Mediatek, which uses ti reset-controller driver directly. The TI reset controller provides a common reset management, and is suitable for Mediatek SoCs. Signed-off-by: Crystal Guo --- .../bindings/reset/mediatek-syscon-reset.yaml | 51 +++++++++++++++++++ 1 file changed, 51 insertions(+) create mode 100644 Documentation/devicetree/bindings/reset/mediatek-syscon-reset.yaml diff --git a/Documentation/devicetree/bindings/reset/mediatek-syscon-reset.yaml b/Documentation/devicetree/bindings/reset/mediatek-syscon-reset.yaml new file mode 100644 index 000000000000..dab630e95a0d --- /dev/null +++ b/Documentation/devicetree/bindings/reset/mediatek-syscon-reset.yaml @@ -0,0 +1,51 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/reset/mediatek-syscon-reset.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Mediatek Reset Controller + +maintainers: + - Crystal Guo + +description: + The bindings describe the reset-controller for Mediatek SoCs, + which is based on TI reset controller. For more detail, please + visit Documentation/devicetree/bindings/reset/ti-syscon-reset.txt. + +properties: + compatible: + const: mediatek,syscon-reset + + '#reset-cells': + const: 1 + + mediatek,reset-bits: + description: > + Contains the reset control register information, please refer to + Documentation/devicetree/bindings/reset/ti-syscon-reset.txt. + +required: + - compatible + - '#reset-cells' + - mediatek,reset-bits + +additionalProperties: false + +examples: + - | + #include + infracfg: infracfg@10001000 { + compatible = "mediatek,mt8192-infracfg", "syscon", "simple-mfd"; + reg = <0 0x10001000 0 0x1000>; + #clock-cells = <1>; + + infracfg_rst: reset-controller { + compatible = "mediatek,syscon-reset"; + #reset-cells = <1>; + mediatek,reset-bits = < + 0x140 15 0x144 15 0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE) + >; + }; + };