From patchwork Wed Sep 23 08:52:36 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nobuhiro Iwamatsu X-Patchwork-Id: 1369684 Return-Path: X-Original-To: incoming-imx@patchwork.ozlabs.org Delivered-To: patchwork-incoming-imx@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.infradead.org (client-ip=2001:8b0:10b:1231::1; helo=merlin.infradead.org; envelope-from=linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=toshiba.co.jp Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; secure) header.d=lists.infradead.org header.i=@lists.infradead.org header.a=rsa-sha256 header.s=merlin.20170209 header.b=0wdYupzU; dkim-atps=neutral Received: from merlin.infradead.org (merlin.infradead.org [IPv6:2001:8b0:10b:1231::1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4BxBm5258rz9sSn for ; Wed, 23 Sep 2020 18:53:23 +1000 (AEST) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:Message-ID:Subject:To:From:Date: Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From:Resent-Sender :Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References:List-Owner; bh=M6KZ8u+l6O2/JeUJNh+UfXD1kymhdDGn1eV495Hs8WQ=; b=0wdYupzUhWTPJboDViOL9fph6N yeXYCZEDtblqZzlt3K3/Qkhg3OCVuafenSmce+VyOSdGh+o+xl6LT+N97DyIoStVssb2Ukgyb9HDp KAV8WMebXLDf9rwdPmd8EWsY9eKgpHiGNrcI4vfGS6Jo1rfyhyZ1o3l0wk70P2vsF6r3tGg9lEIsa 6nzkntztxAbGb+/Btso5sKVY1e185K9mLjJqAtvsoc4Wr+PxjrkMa13/xMQlNEWPZywg8BJp6Hoh4 jGPiKyIntlInFE2pj8P1IJFuek9QmRPR+p8fzrcbWGDPvBGipXzOe7r64hADnvy5BPBpvZk/617q9 doC+U/HQ==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kL0WL-0001oE-Jt; Wed, 23 Sep 2020 08:53:01 +0000 Received: from mo-csw1515.securemx.jp ([210.130.202.154] helo=mo-csw.securemx.jp) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1kL0WJ-0001nZ-D7 for linux-arm-kernel@lists.infradead.org; Wed, 23 Sep 2020 08:53:00 +0000 Received: by mo-csw.securemx.jp (mx-mo-csw1515) id 08N8qf0A011709; Wed, 23 Sep 2020 17:52:41 +0900 X-Iguazu-Qid: 34trRpZzTvUKx62MeD X-Iguazu-QSIG: v=2; s=0; t=1600851160; q=34trRpZzTvUKx62MeD; m=FoeEqvgkbzloI0PWEQ80MBPC6Oa6KTLcETPQBEE/oj0= Received: from imx12.toshiba.co.jp (imx12.toshiba.co.jp [61.202.160.132]) by relay.securemx.jp (mx-mr1510) id 08N8qcDR005328; Wed, 23 Sep 2020 17:52:38 +0900 Received: from enc02.toshiba.co.jp ([61.202.160.51]) by imx12.toshiba.co.jp with ESMTP id 08N8qcnT017248; Wed, 23 Sep 2020 17:52:38 +0900 (JST) Received: from hop101.toshiba.co.jp ([133.199.85.107]) by enc02.toshiba.co.jp with ESMTP id 08N8qbna004432; Wed, 23 Sep 2020 17:52:37 +0900 Date: Wed, 23 Sep 2020 17:52:36 +0900 From: Nobuhiro Iwamatsu To: soc@kernel.org Subject: [GIT PULL] Initial support Visconti SoC for v5.10 kernel (take two) X-TSB-HOP: ON Message-ID: <20200923085236.4hu53gmnnmqkttuy@toshiba.co.jp> MIME-Version: 1.0 Content-Disposition: inline X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200923_045259_782492_FFBECBE0 X-CRM114-Status: GOOD ( 12.63 ) X-Spam-Score: -0.7 (/) X-Spam-Report: SpamAssassin version 3.4.4 on merlin.infradead.org summary: Content analysis details: (-0.7 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at https://www.dnswl.org/, low trust [210.130.202.154 listed in list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record -0.0 SPF_HELO_PASS SPF: HELO matches SPF record 0.0 RCVD_IN_MSPIKE_H3 RBL: Good reputation (+3) [210.130.202.154 listed in wl.mailspike.net] 0.0 RCVD_IN_MSPIKE_WL Mailspike good senders X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, punit1.agrawal@toshiba.co.jp, arnd@arndb.de, catalin.marinas@arm.com, linus.walleij@linaro.org, olof@lixom.net, linux-gpio@vger.kernel.org, will@kernel.org, robh+dt@kernel.org, sudeep.holla@arm.com, maz@misterjones.org, yuji2.ishikawa@toshiba.co.jp, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org Hi, This is the first pull request for Toshiba ARM SoC, Visconti5. Please pull this new SoC patches for v5.10 kernel cycle. Best regards, Nobuhiro The following changes since commit d012a7190fc1fd72ed48911e77ca97ba4521bccd: Linux 5.9-rc2 (2020-08-23 14:08:43 -0700) are available in the Git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/iwamatsu/linux-visconti.git tags/visconti-initial-for-5.10-tag2 for you to fetch changes up to c29900d50f4445e25a8e70dbd794bcc51d531639: arm64: defconfig: Enable configs for Toshiba Visconti (2020-09-23 17:09:17 +0900) ---------------------------------------------------------------- Visconti5 SoC changes for v5.10 (take two) - Add dt-bindings for Toshiba Visconti ARM SoCs - Add dt-bindings for the TMPV7708 RM main board - Add initial support for Toshiba Visconti platform - Add device tree for TMPV7708 RM main board - Add information for Toshiba Visconti ARM SoCs to MAINTAINERS - Enable configs for Toshiba Visconti to arm64's defconfig ---------------------------------------------------------------- Nobuhiro Iwamatsu (6): dt-bindings: arm: toshiba: add Toshiba Visconti ARM SoCs dt-bindings: arm: toshiba: Add the TMPV7708 RM main board arm64: visconti: Add initial support for Toshiba Visconti platform arm64: dts: visconti: Add device tree for TMPV7708 RM main board MAINTAINERS: Add information for Toshiba Visconti ARM SoCs arm64: defconfig: Enable configs for Toshiba Visconti Documentation/devicetree/bindings/arm/toshiba.yaml | 22 ++++++++++ MAINTAINERS | 11 +++++ arch/arm64/Kconfig.platforms | 7 ++++ arch/arm64/boot/dts/Makefile | 1 + arch/arm64/boot/dts/toshiba/Makefile | 2 + arch/arm64/boot/dts/toshiba/tmpv7708-rm-mbrc.dts | 43 +++++++++++++++++++ arch/arm64/boot/dts/toshiba/tmpv7708.dtsi | 390 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ arch/arm64/boot/dts/toshiba/tmpv7708_pins.dtsi | 93 +++++++++++++++++++++++++++++++++++++++++ arch/arm64/configs/defconfig | 1 + 9 files changed, 570 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/toshiba.yaml create mode 100644 arch/arm64/boot/dts/toshiba/Makefile create mode 100644 arch/arm64/boot/dts/toshiba/tmpv7708-rm-mbrc.dts create mode 100644 arch/arm64/boot/dts/toshiba/tmpv7708.dtsi create mode 100644 arch/arm64/boot/dts/toshiba/tmpv7708_pins.dtsi