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[108.51.35.162]) by smtp.gmail.com with ESMTPSA id c70sm8658105qkg.4.2020.09.21.04.51.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 21 Sep 2020 04:51:55 -0700 (PDT) From: Sean Anderson To: u-boot@lists.denx.de Cc: Heinrich Schuchardt , Rick Chen , alankao@andestech.com, Leo Liang , Bin Meng , Sean Anderson , Bin Meng Subject: [PATCH v3 1/7] Revert "riscv: Clear pending interrupts before enabling IPIs" Date: Mon, 21 Sep 2020 07:51:35 -0400 Message-Id: <20200921115141.70598-2-seanga2@gmail.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20200921115141.70598-1-seanga2@gmail.com> References: <20200921115141.70598-1-seanga2@gmail.com> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.3 at phobos.denx.de X-Virus-Status: Clean Clearing MIP.MSIP is not guaranteed to do anything by the spec. In addition, most existing RISC-V hardware does nothing when this bit is set. The following commits "riscv: Use a valid bit to ignore already-pending IPIs" and "riscv: Clear pending IPIs on initialization" should implement the original intent of the reverted commit in a more robust manner. This reverts commit 9472630337e7c4ac442066b5a752aaa8c3b4d4a6. Signed-off-by: Sean Anderson Reviewed-by: Bin Meng Reviewed-by: Rick Chen --- (no changes since v1) arch/riscv/cpu/start.S | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S index bf9fdf369b..e3222b1ea7 100644 --- a/arch/riscv/cpu/start.S +++ b/arch/riscv/cpu/start.S @@ -65,8 +65,6 @@ _start: #else li t0, SIE_SSIE #endif - /* Clear any pending IPIs */ - csrc MODE_PREFIX(ip), t0 csrs MODE_PREFIX(ie), t0 #endif From patchwork Mon Sep 21 11:51:36 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sean Anderson X-Patchwork-Id: 1368297 X-Patchwork-Delegate: uboot@andestech.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=XSR420p0; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4Bw2qc62RCz9sV0 for ; Mon, 21 Sep 2020 21:52:28 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id F32BB82553; Mon, 21 Sep 2020 13:52:07 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="XSR420p0"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 0F79582552; Mon, 21 Sep 2020 13:52:01 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.0 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FROM,SPF_HELO_NONE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.2 Received: from mail-qt1-x844.google.com (mail-qt1-x844.google.com [IPv6:2607:f8b0:4864:20::844]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 0FEAD82549 for ; Mon, 21 Sep 2020 13:51:58 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=seanga2@gmail.com Received: by mail-qt1-x844.google.com with SMTP id r8so11894487qtp.13 for ; Mon, 21 Sep 2020 04:51:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=4uk0oeNK/Hb3oB6Sr2q8ilxfJsp6vbE+SnmYR91w7XE=; b=XSR420p0oqaILzSX2IMD6hvmsj0EBMNmJsfLdsyyScooCzn/HnOh8Tm7dlDqKz3YFL i9ZxPRutFBjOdWuWAFXyk7SC8+U+GeKFlRv73wRhAwOG4PVxdDLimkdo6boZvY6bc02t 5A6oMnK4MuXR0M2LGPO+JPFbP/pxwzDzugM8PvviplNFqsyFZjZDrwrdEvFTSSM1qc03 zPV26F56FzWpulck3eUgmw2lW5zpJ4+MWQvRvMkHjTTJ8Mkmnzwk8hWNsqajo8aeuroM XKf5DiiAG5qgvmFl/YyThGZTA60HFvpZ3bPeJfIhL8X8NAErLKNmEgC3mf9hgsXl7ycQ H47w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=4uk0oeNK/Hb3oB6Sr2q8ilxfJsp6vbE+SnmYR91w7XE=; b=tG4AkB1X+Sc1muRK2vEyNrjBFKGouuGczlq1krLWaTgxLFzEJwNkkwIlrMWyNhaQ9Z 9cGnzPYAM3RMyhesJYIZobeuGWub3XW9zsVxFgcKgB4rHipC/X4F9xsFPTG8ISZjTLtH ZGUp8GBZt3HCSB5VlMdf+fsRSY/YLOvRxDVwCEx2KWuDLFfoChlnO3RggvgxQJu2mNEj 2S/CWvuUdTee6cLEhT/tPYOTk9FcdrlivJ2dsaNmK6c5BXw7N7X95y44pB/RgFEeO1Ld 8yOmNQwJjkL2bQG/dx9o+QyjG90mDJRnBTVtuga1cl1U9RY7CWebZIcgSNCg5p0XilXR +B3A== X-Gm-Message-State: AOAM533IV3rFdxk51mMhsqL0C9JoUO+BXZiOk3ckp9y2d7TZlFBQKbeY RpxRssHpV95AqlIY2f/DVAv7VhTcInDKUg== X-Google-Smtp-Source: ABdhPJwUEQ24f4JMIL7drpspS5Sf5FTNg/7gosRukvvjmMkMR9VLyeC59coZvcVBTWA2FmzcufLfNQ== X-Received: by 2002:aed:2a83:: with SMTP id t3mr347074qtd.178.1600689116676; Mon, 21 Sep 2020 04:51:56 -0700 (PDT) Received: from godwin.fios-router.home (pool-108-51-35-162.washdc.fios.verizon.net. [108.51.35.162]) by smtp.gmail.com with ESMTPSA id c70sm8658105qkg.4.2020.09.21.04.51.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 21 Sep 2020 04:51:56 -0700 (PDT) From: Sean Anderson To: u-boot@lists.denx.de Cc: Heinrich Schuchardt , Rick Chen , alankao@andestech.com, Leo Liang , Bin Meng , Sean Anderson , Bin Meng , Rick Chen Subject: [PATCH v3 2/7] riscv: Match memory barriers between send_ipi_many and handle_ipi Date: Mon, 21 Sep 2020 07:51:36 -0400 Message-Id: <20200921115141.70598-3-seanga2@gmail.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20200921115141.70598-1-seanga2@gmail.com> References: <20200921115141.70598-1-seanga2@gmail.com> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.3 at phobos.denx.de X-Virus-Status: Clean Without a matching barrier on the write side, the barrier in handle_ipi does nothing. It was entirely possible for the boot hart to write to addr, arg0, and arg1 *after* sending the IPI, because there was no barrier on the sending side. Fixes: 90ae281437 ("riscv: add option to wait for ack from secondary harts in smp functions") Signed-off-by: Sean Anderson Reviewed-by: Bin Meng Reviewed-by: Rick Chen Reviewed-by: Leo Liang --- (no changes since v1) arch/riscv/lib/smp.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/riscv/lib/smp.c b/arch/riscv/lib/smp.c index ac22136314..ab6d8bd7fa 100644 --- a/arch/riscv/lib/smp.c +++ b/arch/riscv/lib/smp.c @@ -54,6 +54,8 @@ static int send_ipi_many(struct ipi_data *ipi, int wait) gd->arch.ipi[reg].arg0 = ipi->arg0; gd->arch.ipi[reg].arg1 = ipi->arg1; + __smp_mb(); + ret = riscv_send_ipi(reg); if (ret) { pr_err("Cannot send IPI to hart %d\n", reg); From patchwork Mon Sep 21 11:51:37 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sean Anderson X-Patchwork-Id: 1368298 X-Patchwork-Delegate: uboot@andestech.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=ThNdYv5V; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4Bw2qh2Wj4z9sV0 for ; Mon, 21 Sep 2020 21:52:32 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id AA3FB8255D; Mon, 21 Sep 2020 13:52:09 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="ThNdYv5V"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 9DDC48255D; Mon, 21 Sep 2020 13:52:02 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.0 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FROM,SPF_HELO_NONE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.2 Received: from mail-qt1-x843.google.com (mail-qt1-x843.google.com [IPv6:2607:f8b0:4864:20::843]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id EBA0F82525 for ; Mon, 21 Sep 2020 13:51:58 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=seanga2@gmail.com Received: by mail-qt1-x843.google.com with SMTP id p65so11920068qtd.2 for ; Mon, 21 Sep 2020 04:51:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=/d21Imbmsi+AnJb6SY6eTwSMHfpXNj0ALmGNqMGzOck=; b=ThNdYv5VFNZ+U5u/UGH1rOgcDsTcqA2DyVGlGQf5UEUcTnJJzO2BLHv5P3X0GXFmmE xqudkBjUu7dECElroaqzf/f4LRnKy3nV2G9sXNhnEJq+1iMchdL3yVAGvJO1twHMrlZ5 ohFUp465EUWAdUnxiHExMzovn2Hlt0x/y/1ptfeZHON7dluewR9A3zwmMuw4b+KsyErm wQF1i8PQFiPt6Z8zFmHy+ljfPOOlaRBIlrPNz9uwqwiCGoAwGJCGZVaoS8WS1DXdu7YG fXcpTSLadWHXAiy7LwycfkjfDZNgWMu6VWw8KdILwy7pvO3pv6Ojop09NZJUBoYXhaZw 32qQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=/d21Imbmsi+AnJb6SY6eTwSMHfpXNj0ALmGNqMGzOck=; b=ooSJmx5BslESjFOMeu92Jmh47kYX9Qof6q+5+fzbc/jr3csI4lX80wh4y6JDIEdH8D Xj55+H1P9vNMeXUQHS6xLwxhML1Kc78qB6D/E6DxiK9VmtpUn73qd7z3wlOpw6jfk3V+ b+Q7xndGaxtC5b2jWZGzYChWjK1bMXy441GY9fM0VChoF7z6AaA7is514EwNKK/+H/lz lWUjIa4drXTyMUzuisBlHlUm3Rn54xlLKDAVn9CPi/Q26t9EIKfxEmcZ1CgJAz2TT/Al lWE4ZJ+9RWkbwRzNyPz6M2xoD8k9+aSvBqS2zVXSVoFsUF2Fe/EE8/MQLzFg1FsYM+Fs Rotw== X-Gm-Message-State: AOAM532FOpq6cGurTz1qV54Jap+Qg8B74Em37LjqLUyezXvt+bIG5E+u 4XjSIOS9eKeBwmjHDOErCHxi8Y6ZVMjvjQ== X-Google-Smtp-Source: ABdhPJz9YCL8pKFFlFjadq/HWlJB4rzdFK7ZFm6vtuikvuAFZn6f+r8pm6LUnZuXQpylsIFhNGmvMg== X-Received: by 2002:aed:2c61:: with SMTP id f88mr33035110qtd.388.1600689117665; Mon, 21 Sep 2020 04:51:57 -0700 (PDT) Received: from godwin.fios-router.home (pool-108-51-35-162.washdc.fios.verizon.net. [108.51.35.162]) by smtp.gmail.com with ESMTPSA id c70sm8658105qkg.4.2020.09.21.04.51.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 21 Sep 2020 04:51:57 -0700 (PDT) From: Sean Anderson To: u-boot@lists.denx.de Cc: Heinrich Schuchardt , Rick Chen , alankao@andestech.com, Leo Liang , Bin Meng , Sean Anderson , Bin Meng , Rick Chen Subject: [PATCH v3 3/7] riscv: Use a valid bit to ignore already-pending IPIs Date: Mon, 21 Sep 2020 07:51:37 -0400 Message-Id: <20200921115141.70598-4-seanga2@gmail.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20200921115141.70598-1-seanga2@gmail.com> References: <20200921115141.70598-1-seanga2@gmail.com> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.3 at phobos.denx.de X-Virus-Status: Clean Some IPIs may already be pending when U-Boot is started. This could be a problem if a secondary hart tries to handle an IPI before the boot hart has initialized the IPI device. To be specific, the Kendryte K210 ROM-based bootloader does not clear IPIs before passing control to U-Boot. Without this patch, the secondary hart jumps to address 0x0 as soon as it enters secondary_hart_loop, and then hangs in its trap handler. This commit introduces a valid bit so secondary harts know when and IPI originates from U-Boot, and it is safe to use the IPI API. The valid bit is initialized to 0 by board_init_f_init_reserve. Before this, secondary harts wait in wait_for_gd_init. Signed-off-by: Sean Anderson Reviewed-by: Bin Meng Reviewed-by: Rick Chen Reviewed-by: Leo Liang --- (no changes since v2) Changes in v2: - Use a valid bit instead of addr to validate IPIs arch/riscv/include/asm/smp.h | 7 +++++++ arch/riscv/lib/smp.c | 16 ++++++++++++++-- 2 files changed, 21 insertions(+), 2 deletions(-) diff --git a/arch/riscv/include/asm/smp.h b/arch/riscv/include/asm/smp.h index 1b428856b2..2dae0800ce 100644 --- a/arch/riscv/include/asm/smp.h +++ b/arch/riscv/include/asm/smp.h @@ -18,14 +18,21 @@ * IPI data structure. The hart ID is inserted by the hart handling the IPI and * calling the function. * + * @valid is used to determine whether a sent IPI originated from U-Boot. It is + * initialized to zero by board_init_f_alloc_reserve. When U-Boot sends its + * first IPI, it is set to 1. This prevents already-pending IPIs not sent by + * U-Boot from being taken. + * * @addr: Address of function * @arg0: First argument of function * @arg1: Second argument of function + * @valid: Whether this IPI is valid */ struct ipi_data { ulong addr; ulong arg0; ulong arg1; + unsigned int valid; }; /** diff --git a/arch/riscv/lib/smp.c b/arch/riscv/lib/smp.c index ab6d8bd7fa..8f33ce1fe3 100644 --- a/arch/riscv/lib/smp.c +++ b/arch/riscv/lib/smp.c @@ -54,7 +54,13 @@ static int send_ipi_many(struct ipi_data *ipi, int wait) gd->arch.ipi[reg].arg0 = ipi->arg0; gd->arch.ipi[reg].arg1 = ipi->arg1; - __smp_mb(); + /* + * Ensure valid only becomes set when the IPI parameters are + * set. An IPI may already be pending on other harts, so we + * need a way to signal that the IPI device has been + * initialized, and that it is ok to call the function. + */ + __smp_store_release(&gd->arch.ipi[reg].valid, 1); ret = riscv_send_ipi(reg); if (ret) { @@ -83,7 +89,13 @@ void handle_ipi(ulong hart) if (hart >= CONFIG_NR_CPUS) return; - __smp_mb(); + /* + * If valid is not set, then U-Boot has not requested the IPI. The + * IPI device may not be initialized, so all we can do is wait for + * U-Boot to initialize it and send an IPI + */ + if (!__smp_load_acquire(&gd->arch.ipi[hart].valid)) + return; smp_function = (void (*)(ulong, ulong, ulong))gd->arch.ipi[hart].addr; invalidate_icache_all(); From patchwork Mon Sep 21 11:51:38 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sean Anderson X-Patchwork-Id: 1368299 X-Patchwork-Delegate: uboot@andestech.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=WrUcWwb+; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4Bw2qw3Jh2z9sV0 for ; Mon, 21 Sep 2020 21:52:44 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 0A71482563; Mon, 21 Sep 2020 13:52:11 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="WrUcWwb+"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 45D7582556; Mon, 21 Sep 2020 13:52:03 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.0 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FROM,SPF_HELO_NONE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.2 Received: from mail-qt1-x841.google.com (mail-qt1-x841.google.com [IPv6:2607:f8b0:4864:20::841]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 1489582546 for ; Mon, 21 Sep 2020 13:52:00 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=seanga2@gmail.com Received: by mail-qt1-x841.google.com with SMTP id g3so11899417qtq.10 for ; Mon, 21 Sep 2020 04:52:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=rxX2Y4ZN50mibmoTtEAtYEY8rXWm5nQy6bSuIh3SuJo=; b=WrUcWwb+tOuPptrImzauuLvPDR539h4otKSFm0Hb6fNQA7KIuHGtiiAAlaIQsZEHIc O7kb/4t+G8UEEfmHxtKXhvwnjPoZgNKMjvnnzyViElhkPSHph32YHlTEV6TO+DqVL8w/ jlXvIOcMfmBTl4Yy6jBpiYk4OOIkjBDS1TPKlMBXJDq21GDd5dZNbmByZ40wvBQxZaWV XcCk4Nf13k+7R9CHlXy2EIfZnRZSDTXsRp2tfjK81jAg5SZXLjy918yJZolO6AtJFGDv VgG6TxpWDwKLHKvVp5f2MNLT///IMwGjEl2Qxmwnaze595tTBey07GOybuUNkcdBGNUc WpQQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=rxX2Y4ZN50mibmoTtEAtYEY8rXWm5nQy6bSuIh3SuJo=; b=Pr+/nHuEoziJf7AR1h6UjD+V8dipUmJ7BzVWHEGSicRuIJLluhu7MhkH2jXziYD3KE TLzZy3llErk9mnXAeQp0JxcGBgaskC1NHnxDPhXaoaWYZdjSGt0OXleQYD/A3ou7nIzh B26tkKHfZYE4gyPJcl0D+4v263FezbC5zzLnHQ/vbyUE7jzoSX8lC4SLroOnikSxkMMi vdruTYFJS5dtp8cRYMoZ7txlr91f0zWaWCH725dgqxSok3KEVc4Msz1KrE1AdJW5Yt8c /dS+EIlqioh7pb4/KjbtYtS2SrNiJm6dBfBZH0OC3zUQIDqWiesIvAUCBJRPmWD+GGTQ fHpw== X-Gm-Message-State: AOAM530JRjQ+QAT/gCu0eZvfvBhp+OhORZHyr0GdOIYu62hKgSGPT5fC MEDgW7jd0QzJE8FtnKyButCu2m40BETa8A== X-Google-Smtp-Source: ABdhPJwfQtnP7Qc7KJ/nmmKqOW75Sy+k5l8VQtpADfkXTz3O5yADfCmB6cP8ZS/Hs2W59xsvzUhjAQ== X-Received: by 2002:ac8:1832:: with SMTP id q47mr341192qtj.215.1600689118783; Mon, 21 Sep 2020 04:51:58 -0700 (PDT) Received: from godwin.fios-router.home (pool-108-51-35-162.washdc.fios.verizon.net. [108.51.35.162]) by smtp.gmail.com with ESMTPSA id c70sm8658105qkg.4.2020.09.21.04.51.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 21 Sep 2020 04:51:58 -0700 (PDT) From: Sean Anderson To: u-boot@lists.denx.de Cc: Heinrich Schuchardt , Rick Chen , alankao@andestech.com, Leo Liang , Bin Meng , Sean Anderson , Bin Meng Subject: [PATCH v3 4/7] riscv: Clear pending IPIs on initialization Date: Mon, 21 Sep 2020 07:51:38 -0400 Message-Id: <20200921115141.70598-5-seanga2@gmail.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20200921115141.70598-1-seanga2@gmail.com> References: <20200921115141.70598-1-seanga2@gmail.com> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.3 at phobos.denx.de X-Virus-Status: Clean Even though we no longer call smp_function if an IPI was not sent by U-Boot, we still need to clear any IPIs which were pending from the execution environment. Otherwise, secondary harts will busy-wait in secondary_hart_loop, instead of relaxing. Along with the previous commit ("riscv: Use a valid bit to ignore already-pending IPIs"), this fixes SMP booting on the Kendryte K210. Signed-off-by: Sean Anderson Reviewed-by: Bin Meng Reviewed-by: Rick Chen --- Changes in v3: - Rename riscv_ipi_init_secondary_hart to dummy_pending_ipi_clear - Only compile dummy_pending_ipi_clear when SMP is enabled Changes in v2: - Make riscv_ipi_init_secondary_hart static arch/riscv/cpu/cpu.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c index bfa2d4a426..85592f5bee 100644 --- a/arch/riscv/cpu/cpu.c +++ b/arch/riscv/cpu/cpu.c @@ -72,6 +72,17 @@ static int riscv_cpu_probe(void) return 0; } +/* + * This is called on secondary harts just after the IPI is init'd. Currently + * there's nothing to do, since we just need to clear any existing IPIs, and + * that is handled by the sending of an ipi itself. + */ +#if CONFIG_IS_ENABLED(SMP) +static void dummy_pending_ipi_clear(ulong hart, ulong arg0, ulong arg1) +{ +} +#endif + int arch_cpu_init_dm(void) { int ret; @@ -111,6 +122,15 @@ int arch_cpu_init_dm(void) ret = riscv_init_ipi(); if (ret) return ret; + + /* + * Clear all pending IPIs on secondary harts. We don't do anything on + * the boot hart, since we never send an IPI to ourselves, and no + * interrupts are enabled + */ + ret = smp_call_function((ulong)dummy_pending_ipi_clear, 0, 0, 0); + if (ret) + return ret; #endif return 0; From patchwork Mon Sep 21 11:51:39 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sean Anderson X-Patchwork-Id: 1368300 X-Patchwork-Delegate: uboot@andestech.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=Ank3f5kg; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4Bw2r90JJgz9sV0 for ; Mon, 21 Sep 2020 21:52:56 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id A3FE582567; Mon, 21 Sep 2020 13:52:16 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="Ank3f5kg"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 7E26282556; Mon, 21 Sep 2020 13:52:04 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.0 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FROM,SPF_HELO_NONE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.2 Received: from mail-qt1-x841.google.com (mail-qt1-x841.google.com [IPv6:2607:f8b0:4864:20::841]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 14A0582549 for ; Mon, 21 Sep 2020 13:52:01 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=seanga2@gmail.com Received: by mail-qt1-x841.google.com with SMTP id e7so11891720qtj.11 for ; Mon, 21 Sep 2020 04:52:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=RldxFTNey5QQgKiSb6ASq56KSa5M/nbmnG3QDOrTxPo=; b=Ank3f5kgNfCT+QHHRURvtrk/CRqqHXhEgwWFW+3MzWbjXWao+nw3AYvoCFgo+mQjS1 ourCVGBeDGBHpV22stTXUhyLUnLQUuT0CSEMrglvDRbSbL8o1rNhRYrWIA/5p3/I6lU0 3jC4+lBGwcyUvWXsaoVGlTpM9jmR9c+Y9OUipJhPqB78sGwPVl8PSddx/l4BR4zPjkWm lhUSXNqH/aatYK+s5hQmLUtwMTwpNt2Jqr8PMJytN7cqRnksFFf5648afrp+2KCTiJ6p 3gP3xm7BpJqp0MzyZ3rupV4ny8fqkgtfUZ1fgj9Nr5Q/u0fqDxaPplI+uX5GD6LE8scP F1Pg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=RldxFTNey5QQgKiSb6ASq56KSa5M/nbmnG3QDOrTxPo=; b=V3J1pmqGyv31h6bcP0+8CXFgicqAXdpb59MBgsaqVuji7Ilbdy2IHrqM51Dy2n+orJ 9FEFGZCUH7K+oYKxb5GMMQuWdiDd/O6KixiJ65pmS+ZwYHBBRXfryA6mZTbExkO5QXLP IAfeGkbNMnW4gFS+BLisPioKpNCu85YMn+zY+y4tmjZP4BRyp9Ou5BLqCHjq/0H+O/nP +/qqKmSVAI+baGdmGsmWpqdS1xpXDuatdLO53+HGX2nBe1vXAT+T3XeDNCGD6PWt5tr9 N/uKmd43cjjj5hhaNqvO2cWAZKn7wkwhveBO8Kkyg8o+m8QJ4t7MR/ht6++JeotG+sez NFqg== X-Gm-Message-State: AOAM532Z5zauAZhhRXhNNZ8wiTxo113DftTmAWeQEGAcfXRfmV6wyuWu Fy7/r1TUQsnHD0b6C0D3Qpg8tzvykjpplw== X-Google-Smtp-Source: ABdhPJyZWifWuegPXCQkaJBp9Qa/ODeWxhZafqsGyXWdyOaalCxi3hJkaEoRiFId/d/ug59FTnXyNA== X-Received: by 2002:ac8:3f3d:: with SMTP id c58mr355378qtk.53.1600689119806; Mon, 21 Sep 2020 04:51:59 -0700 (PDT) Received: from godwin.fios-router.home (pool-108-51-35-162.washdc.fios.verizon.net. [108.51.35.162]) by smtp.gmail.com with ESMTPSA id c70sm8658105qkg.4.2020.09.21.04.51.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 21 Sep 2020 04:51:59 -0700 (PDT) From: Sean Anderson To: u-boot@lists.denx.de Cc: Heinrich Schuchardt , Rick Chen , alankao@andestech.com, Leo Liang , Bin Meng , Sean Anderson , Bin Meng , Rick Chen Subject: [PATCH v3 5/7] riscv: Consolidate fences into AMOs for available_harts_lock Date: Mon, 21 Sep 2020 07:51:39 -0400 Message-Id: <20200921115141.70598-6-seanga2@gmail.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20200921115141.70598-1-seanga2@gmail.com> References: <20200921115141.70598-1-seanga2@gmail.com> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.3 at phobos.denx.de X-Virus-Status: Clean We can reduce the number of instructions needed to use available_harts_lock by using the aq and rl suffixes for AMOs. Signed-off-by: Sean Anderson Reviewed-by: Bin Meng Reviewed-by: Rick Chen --- (no changes since v2) Changes in v2: - Remove fences after amoswaps - Reword commit message arch/riscv/cpu/start.S | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S index e3222b1ea7..66ca1c7020 100644 --- a/arch/riscv/cpu/start.S +++ b/arch/riscv/cpu/start.S @@ -125,14 +125,12 @@ call_board_init_f_0: #ifndef CONFIG_XIP la t0, available_harts_lock - fence rw, w - amoswap.w zero, zero, 0(t0) + amoswap.w.rl zero, zero, 0(t0) wait_for_gd_init: la t0, available_harts_lock li t1, 1 -1: amoswap.w t1, t1, 0(t0) - fence r, rw +1: amoswap.w.aq t1, t1, 0(t0) bnez t1, 1b /* register available harts in the available_harts mask */ @@ -142,8 +140,7 @@ wait_for_gd_init: or t2, t2, t1 SREG t2, GD_AVAILABLE_HARTS(gp) - fence rw, w - amoswap.w zero, zero, 0(t0) + amoswap.w.rl zero, zero, 0(t0) /* * Continue on hart lottery winner, others branch to From patchwork Mon Sep 21 11:51:40 2020 Content-Type: text/plain; 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[108.51.35.162]) by smtp.gmail.com with ESMTPSA id c70sm8658105qkg.4.2020.09.21.04.51.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 21 Sep 2020 04:52:00 -0700 (PDT) From: Sean Anderson To: u-boot@lists.denx.de Cc: Heinrich Schuchardt , Rick Chen , alankao@andestech.com, Leo Liang , Bin Meng , Sean Anderson , Bin Meng Subject: [PATCH v3 6/7] riscv: Ensure gp is NULL or points to valid data Date: Mon, 21 Sep 2020 07:51:40 -0400 Message-Id: <20200921115141.70598-7-seanga2@gmail.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20200921115141.70598-1-seanga2@gmail.com> References: <20200921115141.70598-1-seanga2@gmail.com> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.3 at phobos.denx.de X-Virus-Status: Clean This ensures constructs like `if (gd & gd->...) { ... }` work when accessing the global data pointer. Without this change, it was possible for a very early trap to cause _exit_trap to directly or indirectly (through printf) to read arbitrary memory. This could cause a second trap, preventing show_regs from being printed. printf (and specifically puts) uses gd to determine what function to print with. These functions in turn use gd to find the serial device, etc. However, before accessing gd, puts first checks to see if it is non-NULL. This indicates an existing (perhaps undocumented) assumption that either gd is NULL or it is completely valid. Before this patch, gd either points to unexpected data (because it retains the value it did from the prior-stage) or points to uninitialized data (because it has not yet been initialized by board_init_f_init_reserve) until the hart has acquired available_harts_lock. This can cause two problems, depending on the value of gd->flags. If GD_FLG_SERIAL_READY is unset, then some garbage data will be printed to stdout, but there will not be a second trap. However, if GD_FLG_SERIAL_READY is set, then puts will try to print with serial_puts, which will likely cause a second trap. After this patch, gd is zero up until either a hart has set it in wait_for_gd_init, or until it is set by arch_init_gd. This prevents its usage before its data is initialized because both handle_trap and puts ensure that gd is nonzero before using it. After gd has been set, it is OK to access it because its data has been cleared (and so flags is valid). XIP cannot use locks because flash is not writable. This leaves it vulnerable to the same class of bugs regarding already-pending IPIs as before this series. Fixing that would require finding another method of synchronization, which is outside the scope of this series. Fixes: 7c6ca03eae ("riscv: additional crash information") Signed-off-by: Sean Anderson Reviewed-by: Bin Meng Reviewed-by: Rick Chen --- Changes in v3: - Clarify XIP comment Changes in v2: - Set gp early with XIP arch/riscv/cpu/start.S | 28 +++++++++++++++++++++++++--- arch/riscv/lib/interrupts.c | 3 ++- 2 files changed, 27 insertions(+), 4 deletions(-) diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S index 66ca1c7020..eb852538ca 100644 --- a/arch/riscv/cpu/start.S +++ b/arch/riscv/cpu/start.S @@ -47,6 +47,13 @@ _start: mv tp, a0 mv s1, a1 + /* + * Set the global data pointer to a known value in case we get a very + * early trap. The global data pointer will be set its actual value only + * after it has been initialized. + */ + mv gp, zero + la t0, trap_entry csrw MODE_PREFIX(tvec), t0 @@ -85,10 +92,10 @@ call_board_init_f_0: jal board_init_f_alloc_reserve /* - * Set global data pointer here for all harts, uninitialized at this - * point. + * Save global data pointer for later. We don't set it here because it + * is not initialized yet. */ - mv gp, a0 + mv s0, a0 /* setup stack */ #if CONFIG_IS_ENABLED(SMP) @@ -109,6 +116,14 @@ call_board_init_f_0: amoswap.w s2, t1, 0(t0) bnez s2, wait_for_gd_init #else + /* + * FIXME: gp is set before it is initialized. If an XIP U-Boot ever + * encounters a pending IPI on boot it is liable to jump to whatever + * memory happens to be in ipi_data.addr on boot. It may also run into + * problems if it encounters an exception too early (because printf/puts + * accesses gd). + */ + mv gp, s0 bnez tp, secondary_hart_loop #endif @@ -133,6 +148,13 @@ wait_for_gd_init: 1: amoswap.w.aq t1, t1, 0(t0) bnez t1, 1b + /* + * Set the global data pointer only when gd_t has been initialized. + * This was already set by arch_setup_gd on the boot hart, but all other + * harts' global data pointers gets set here. + */ + mv gp, s0 + /* register available harts in the available_harts mask */ li t1, 1 sll t1, t1, tp diff --git a/arch/riscv/lib/interrupts.c b/arch/riscv/lib/interrupts.c index cd47e64487..ad870e98d8 100644 --- a/arch/riscv/lib/interrupts.c +++ b/arch/riscv/lib/interrupts.c @@ -78,7 +78,8 @@ static void _exit_trap(ulong code, ulong epc, ulong tval, struct pt_regs *regs) printf("EPC: " REG_FMT " RA: " REG_FMT " TVAL: " REG_FMT "\n", epc, regs->ra, tval); - if (gd->flags & GD_FLG_RELOC) + /* Print relocation adjustments, but only if gd is initialized */ + if (gd && gd->flags & GD_FLG_RELOC) printf("EPC: " REG_FMT " RA: " REG_FMT " reloc adjusted\n\n", epc - gd->reloc_off, regs->ra - gd->reloc_off); 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[108.51.35.162]) by smtp.gmail.com with ESMTPSA id c70sm8658105qkg.4.2020.09.21.04.52.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 21 Sep 2020 04:52:01 -0700 (PDT) From: Sean Anderson To: u-boot@lists.denx.de Cc: Heinrich Schuchardt , Rick Chen , alankao@andestech.com, Leo Liang , Bin Meng , Sean Anderson , Bin Meng , Rick Chen Subject: [PATCH v3 7/7] riscv: Add some comments to start.S Date: Mon, 21 Sep 2020 07:51:41 -0400 Message-Id: <20200921115141.70598-8-seanga2@gmail.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20200921115141.70598-1-seanga2@gmail.com> References: <20200921115141.70598-1-seanga2@gmail.com> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.3 at phobos.denx.de X-Virus-Status: Clean This adds comments regarding the ordering and purpose of certain instructions as I understand them. Signed-off-by: Sean Anderson Reviewed-by: Bin Meng Reviewed-by: Rick Chen Reviewed-by: Leo Liang --- (no changes since v2) Changes in v2: - Clarify comments regarding tp arch/riscv/cpu/start.S | 19 +++++++++++++++++-- 1 file changed, 17 insertions(+), 2 deletions(-) diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S index eb852538ca..bbc737ed9a 100644 --- a/arch/riscv/cpu/start.S +++ b/arch/riscv/cpu/start.S @@ -43,7 +43,10 @@ _start: csrr a0, CSR_MHARTID #endif - /* save hart id and dtb pointer */ + /* + * Save hart id and dtb pointer. The thread pointer register is not + * modified by C code. It is used by secondary_hart_loop. + */ mv tp, a0 mv s1, a1 @@ -54,10 +57,18 @@ _start: */ mv gp, zero + /* + * Set the trap handler. This must happen after initializing gp because + * the handler may use it. + */ la t0, trap_entry csrw MODE_PREFIX(tvec), t0 - /* mask all interrupts */ + /* + * Mask all interrupts. Interrupts are disabled globally (in m/sstatus) + * for U-Boot, but we will need to read m/sip to determine if we get an + * IPI + */ csrw MODE_PREFIX(ie), zero #if CONFIG_IS_ENABLED(SMP) @@ -412,6 +423,10 @@ secondary_hart_relocate: mv gp, a2 #endif +/* + * Interrupts are disabled globally, but they can still be read from m/sip. The + * wfi function will wake us up if we get an IPI, even if we do not trap. + */ secondary_hart_loop: wfi