From patchwork Thu Sep 17 09:42:06 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jack Mitchell X-Patchwork-Id: 1365996 X-Patchwork-Delegate: ykai007@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=embed.me.uk Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4BsX7P6bjwz9sPB for ; Thu, 17 Sep 2020 19:42:24 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 60A828235A; Thu, 17 Sep 2020 11:42:20 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=embed.me.uk Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id 888608233D; Thu, 17 Sep 2020 11:42:19 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,SPF_HELO_PASS, URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.2 Received: from outbound.soverin.net (outbound.soverin.net [116.202.65.218]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id E965C8233D for ; Thu, 17 Sep 2020 11:42:16 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=embed.me.uk Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=ml@embed.me.uk Received: from smtp.soverin.net (unknown [10.10.3.24]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by outbound.soverin.net (Postfix) with ESMTPS id 8AA8B60236; Thu, 17 Sep 2020 09:42:16 +0000 (UTC) Received: from smtp.soverin.net (smtp.soverin.net [159.69.232.138]) by soverin.net From: Jack Mitchell To: u-boot@lists.denx.de Cc: Jagan Teki , Heiko Stuebner , Kever Yang , Jack Mitchell Subject: [PATCH] clk: rockchip: rk3399: implement getting wdt/alive clocks Date: Thu, 17 Sep 2020 10:42:06 +0100 Message-Id: <20200917094206.470783-1-ml@embed.me.uk> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.3 at phobos.denx.de X-Virus-Status: Clean In order to correctly calculate the designware watchdog timeouts, the watchdog clock is required. Implement required clocks to facilitate this. Signed-off-by: Jack Mitchell Reviewed-by: Philipp Tomsich Reviewed-by: Kever Yang --- drivers/clk/rockchip/clk_rk3399.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c index c8075e3dd2..4caa3bbdf5 100644 --- a/drivers/clk/rockchip/clk_rk3399.c +++ b/drivers/clk/rockchip/clk_rk3399.c @@ -241,6 +241,10 @@ enum { DCLK_VOP_DIV_CON_MASK = 0xff, DCLK_VOP_DIV_CON_SHIFT = 0, + /* CLKSEL_CON57 */ + PCLK_ALIVE_DIV_CON_SHIFT = 0, + PCLK_ALIVE_DIV_CON_MASK = 0x1f << PCLK_ALIVE_DIV_CON_SHIFT, + /* CLKSEL_CON58 */ CLK_SPI_PLL_SEL_WIDTH = 1, CLK_SPI_PLL_SEL_MASK = ((1 < CLK_SPI_PLL_SEL_WIDTH) - 1), @@ -875,6 +879,17 @@ static ulong rk3399_ddr_set_clk(struct rockchip_cru *cru, return set_rate; } +static ulong rk3399_alive_get_clk(struct rockchip_cru *cru) +{ + u32 div, val; + + val = readl(&cru->clksel_con[57]); + div = (val & PCLK_ALIVE_DIV_CON_MASK) >> + PCLK_ALIVE_DIV_CON_SHIFT; + + return DIV_TO_RATE(GPLL_HZ, div); +} + static ulong rk3399_saradc_get_clk(struct rockchip_cru *cru) { u32 div, val; @@ -944,6 +959,10 @@ static ulong rk3399_clk_get_rate(struct clk *clk) case ACLK_GIC_PRE: case PCLK_DDR: break; + case PCLK_ALIVE: + case PCLK_WDT: + rate = rk3399_alive_get_clk(priv->cru); + break; default: log_debug("Unknown clock %lu\n", clk->id); return -ENOENT; @@ -1510,6 +1529,7 @@ static ulong rk3399_pmuclk_get_rate(struct clk *clk) case PLL_PPLL: return PPLL_HZ; case PCLK_RKPWM_PMU: + case PCLK_WDT_M0_PMU: rate = rk3399_pwm_get_clk(priv->pmucru); break; case SCLK_I2C0_PMU: