From patchwork Wed Sep 16 08:47:01 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joel Stanley X-Patchwork-Id: 1365059 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [203.11.71.2]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4BrtyY6hWZz9sPB for ; Wed, 16 Sep 2020 18:47:33 +1000 (AEST) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=jms.id.au Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=TszW/Mbo; dkim-atps=neutral Received: from bilbo.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 4BrtyY6GQHzDqW5 for ; Wed, 16 Sep 2020 18:47:33 +1000 (AEST) X-Original-To: linux-aspeed@lists.ozlabs.org Delivered-To: linux-aspeed@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gmail.com (client-ip=2607:f8b0:4864:20::544; helo=mail-pg1-x544.google.com; envelope-from=joel.stan@gmail.com; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=none (p=none dis=none) header.from=jms.id.au Authentication-Results: lists.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=TszW/Mbo; dkim-atps=neutral Received: from mail-pg1-x544.google.com (mail-pg1-x544.google.com [IPv6:2607:f8b0:4864:20::544]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 4BrtyP1J6ZzDq9R for ; Wed, 16 Sep 2020 18:47:25 +1000 (AEST) Received: by mail-pg1-x544.google.com with SMTP id k14so3494856pgi.9 for ; Wed, 16 Sep 2020 01:47:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=pHK7taTCw9nSBaBjuGMlwJwFvRIpsgkWzFQ7ZL1+xd4=; b=TszW/MboMkw7QtAHY0aBHMn+cYGx1Ew9jX44vDWBD5q1u/ecQYqbOJ4jDsWgn1Hf4o 7wV3dKbiAQpFct7IGBzwFk6UR+50o/iAE/GtGpK7WyXyBEWkIbQTyV54Tk1k0Axc8MzI FW1kIiaqKeF9ry2HecCXbZ82xEbnTWbDS2js38l/bC1/xGehGttGV8B+bG2uHHFp3Kw6 24Y5vjoSwYLIiAkwlN9ohYeutWM3bIyEzFfefMPWreQmbe9g3wMXCk1/yk5AFzWMgs8e p66Ulc8ghcG48X7nvVWama7+q1Fxuk2wilizbSBiI8dQ+BOhHPwxeV4nuPEG6MhJGdSY 3uFA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=pHK7taTCw9nSBaBjuGMlwJwFvRIpsgkWzFQ7ZL1+xd4=; b=fq5MEa9sfw1CrjZp8poXKD6oeK0YDJG6OInk5cNxHv8+nq3IHuWfu7Xy3upUIpo7DB kuykxbI35AJtiiNlNyCmVuSq1Jb02mBdR7gFkGDbkIns410ut52DUz8OJ9H3bZ+9i5d1 UVIYW+CJtOP1TZZlkvriD1pcj+iRqQ/Few+iQJ8we9BFKotQqaG3tDfS1EEMzOQPNDu0 HwKl/cqR191S3UMuhZYNeiCr2NLQQvcXlXEUkO0L0cAdpnVstoHO4asol3MRm6U5JqC7 iVpojqaSw5NaMtFvUpn6unEhJRUZD9yhc/mj4iloFVs6ZfZY2FY6DGk+XDxe+6IH7OBK xiVA== X-Gm-Message-State: AOAM532BNXDLlfmVNpmE4L6JlxGa1oEKkt7ZkV/kUHbECMVjpTjuXiQe /JGdhpSEWv05VSVKoaM7Pvg= X-Google-Smtp-Source: ABdhPJyMneAW/o+OiG0mNVCMTpMZMjrGqowzwtjmuV3KH8FIuw29RrGq70WNLOHyuqYDwBD5iKXudQ== X-Received: by 2002:a63:8f0e:: with SMTP id n14mr17997425pgd.211.1600246042668; Wed, 16 Sep 2020 01:47:22 -0700 (PDT) Received: from localhost.localdomain ([45.124.203.18]) by smtp.gmail.com with ESMTPSA id kf10sm1925323pjb.2.2020.09.16.01.47.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 16 Sep 2020 01:47:21 -0700 (PDT) From: Joel Stanley To: Rob Herring Subject: [PATCH 1/3] dt-bindings: aspeed: Add silicon id node to SCU Date: Wed, 16 Sep 2020 18:17:01 +0930 Message-Id: <20200916084703.778386-2-joel@jms.id.au> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20200916084703.778386-1-joel@jms.id.au> References: <20200916084703.778386-1-joel@jms.id.au> MIME-Version: 1.0 X-BeenThere: linux-aspeed@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux ASPEED SoC development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-aspeed@lists.ozlabs.org, linux-arm-kernel@lists.infradead.org Errors-To: linux-aspeed-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Linux-aspeed" Different Aspeed families have various unique hardware silicon identifiers within the SoC. Signed-off-by: Joel Stanley --- .../devicetree/bindings/mfd/aspeed-scu.txt | 23 +++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/Documentation/devicetree/bindings/mfd/aspeed-scu.txt b/Documentation/devicetree/bindings/mfd/aspeed-scu.txt index 4d92c0bb6687..fff3151f06ee 100644 --- a/Documentation/devicetree/bindings/mfd/aspeed-scu.txt +++ b/Documentation/devicetree/bindings/mfd/aspeed-scu.txt @@ -20,3 +20,26 @@ syscon: syscon@1e6e2000 { #clock-cells = <1>; #reset-cells = <1>; }; + +Silicon ID +----------------- + +Families have unique hardware silicon identifiers within the SoC. + +Required properties: + + - compatible: "aspeed,silicon-id" or: + "aspeed,ast2400-silicon-id" or + "aspeed,ast2501-silicon-id" or + "aspeed,ast2600-silicon-id" + + - reg: offset and length of the silicon id information + optionally, a second offset and length describes the unique chip id + +Example: + + +silicon-id@7c { + compatible = "aspeed,ast2500-silicon-id", "aspeed,silicon-id"; + reg = <0x7c 0x4 0x150 0x8>; +}; From patchwork Wed Sep 16 08:47:02 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joel Stanley X-Patchwork-Id: 1365060 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4Brtyj5S42z9sPB for ; Wed, 16 Sep 2020 18:47:41 +1000 (AEST) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=jms.id.au Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=Fn8qiLiB; dkim-atps=neutral Received: from bilbo.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 4Brtyj0nyTzDqWF for ; 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Wed, 16 Sep 2020 01:47:26 -0700 (PDT) Received: from localhost.localdomain ([45.124.203.18]) by smtp.gmail.com with ESMTPSA id kf10sm1925323pjb.2.2020.09.16.01.47.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 16 Sep 2020 01:47:25 -0700 (PDT) From: Joel Stanley To: Rob Herring Subject: [PATCH 2/3] soc: aspeed: Add soc info driver Date: Wed, 16 Sep 2020 18:17:02 +0930 Message-Id: <20200916084703.778386-3-joel@jms.id.au> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20200916084703.778386-1-joel@jms.id.au> References: <20200916084703.778386-1-joel@jms.id.au> MIME-Version: 1.0 X-BeenThere: linux-aspeed@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux ASPEED SoC development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-aspeed@lists.ozlabs.org, linux-arm-kernel@lists.infradead.org Errors-To: linux-aspeed-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Linux-aspeed" This adds a SOC_BUS info driver for the ASPEED platform. The full ID table is preserved in this commit message in case someone finds a need to change the implemntation in the future. { "AST1100-A0", 0x00000200 }, { "AST1100-A1", 0x00000201 }, { "AST1100-A2", 0x00000202 }, { "AST1100-A3", 0x00000202 }, { "AST2050-A0", 0x00000200 }, { "AST2050-A1", 0x00000201 }, { "AST2050-A2", 0x00000202 }, { "AST2050-A3", 0x00000202 }, { "AST2100-A0", 0x00000300 }, { "AST2100-A1", 0x00000301 }, { "AST2100-A2", 0x00000302 }, { "AST2100-A3", 0x00000302 }, { "AST2150-A0", 0x00000202 }, { "AST2150-A1", 0x00000202 }, { "AST2200-A0", 0x00000102 }, { "AST2200-A1", 0x00000102 }, { "AST2300-A0", 0x01000003 }, { "AST2300-A1", 0x01010303 }, { "AST1300-A1", 0x01010003 }, { "AST1050-A1", 0x01010203 }, { "AST2400-A0", 0x02000303 }, { "AST2400-A1", 0x02010303 }, { "AST1400-A1", 0x02010103 }, { "AST1250-A1", 0x02010303 }, { "AST2500-A0", 0x04000303 }, { "AST2510-A0", 0x04000103 }, { "AST2520-A0", 0x04000203 }, { "AST2530-A0", 0x04000403 }, { "AST2500-A1", 0x04010303 }, { "AST2510-A1", 0x04010103 }, { "AST2520-A1", 0x04010203 }, { "AST2530-A1", 0x04010403 }, { "AST2500-A2", 0x04030303 }, { "AST2510-A2", 0x04030103 }, { "AST2520-A2", 0x04030203 }, { "AST2530-A2", 0x04030403 }, { "AST2600-A0", 0x05000303 }, { "AST2600-A1", 0x05010303 }, { "AST2600-A2", 0x05020303 }, { "AST2620-A1", 0x05010203 }, { "AST2620-A2", 0x05020203 }, Signed-off-by: Joel Stanley --- drivers/soc/aspeed/Kconfig | 7 ++ drivers/soc/aspeed/Makefile | 1 + drivers/soc/aspeed/aspeed-socinfo.c | 141 ++++++++++++++++++++++++++++ 3 files changed, 149 insertions(+) create mode 100644 drivers/soc/aspeed/aspeed-socinfo.c diff --git a/drivers/soc/aspeed/Kconfig b/drivers/soc/aspeed/Kconfig index 3c03c255e6e9..be5a29e8b0dc 100644 --- a/drivers/soc/aspeed/Kconfig +++ b/drivers/soc/aspeed/Kconfig @@ -35,6 +35,13 @@ config ASPEED_P2A_CTRL driver also provides an interface for userspace mappings to a pre-defined region. +config ASPEED_SOCINFO + bool "ASPEED SoC Information driver" + default ARCH_ASPEED + select SOC_BUS + help + Say yes to support decoding of ASPEED BMC information. + endmenu endif diff --git a/drivers/soc/aspeed/Makefile b/drivers/soc/aspeed/Makefile index b64be47f2b1f..fcab7192e1a4 100644 --- a/drivers/soc/aspeed/Makefile +++ b/drivers/soc/aspeed/Makefile @@ -2,3 +2,4 @@ obj-$(CONFIG_ASPEED_LPC_CTRL) += aspeed-lpc-ctrl.o obj-$(CONFIG_ASPEED_LPC_SNOOP) += aspeed-lpc-snoop.o obj-$(CONFIG_ASPEED_P2A_CTRL) += aspeed-p2a-ctrl.o +obj-$(CONFIG_ASPEED_SOCINFO) += aspeed-socinfo.o diff --git a/drivers/soc/aspeed/aspeed-socinfo.c b/drivers/soc/aspeed/aspeed-socinfo.c new file mode 100644 index 000000000000..b72c449f7ccb --- /dev/null +++ b/drivers/soc/aspeed/aspeed-socinfo.c @@ -0,0 +1,141 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* Copyright 2019 IBM Corp. */ + +#include +#include +#include +#include +#include +#include +#include + +static struct { + const char *name; + const u32 id; +} const rev_table[] = { + /* AST2400 */ + { "AST2400", 0x02000303 }, + { "AST1400", 0x02010103 }, + { "AST1250", 0x02010303 }, + /* AST2500 */ + { "AST2500", 0x04000303 }, + { "AST2510", 0x04000103 }, + { "AST2520", 0x04000203 }, + { "AST2530", 0x04000403 }, + /* AST2600 */ + { "AST2600", 0x05000303 }, + { "AST2620", 0x05010203 }, +}; + +static const char *siliconid_to_name(u32 siliconid) +{ + unsigned int id = siliconid & 0xff00ffff; + unsigned int i; + + for (i = 0 ; i < ARRAY_SIZE(rev_table) ; ++i) { + if (rev_table[i].id == id) + return rev_table[i].name; + } + + return "Unknown"; +} + +static const char *siliconid_to_rev(u32 siliconid) +{ + unsigned int rev = (siliconid >> 16) & 0xff; + + switch (rev) { + case 0: + return "A0"; + case 1: + return "A1"; + case 3: + return "A2"; + }; + + return "??"; +} + +static int __init aspeed_socinfo_init(void) +{ + struct soc_device_attribute *attrs; + struct soc_device *soc_dev; + struct device_node *np; + void __iomem *reg; + bool has_chipid = false; + u32 siliconid; + u32 chipid[2]; + const char *machine = NULL; + + np = of_find_compatible_node(NULL, NULL, "aspeed,silicon-id"); + if (!of_device_is_available(np)) { + of_node_put(np); + return -ENODEV; + } + + reg = of_iomap(np, 0); + if (!reg) + return -ENODEV; + siliconid = readl(reg); + of_node_put(np); + iounmap(reg); + + /* This is optional, the ast2400 does not have it */ + reg = of_iomap(np, 1); + if (reg) { + has_chipid = true; + chipid[0] = readl(reg); + chipid[1] = readl(reg + 4); + iounmap(reg); + of_node_put(np); + } + + attrs = kzalloc(sizeof(*attrs), GFP_KERNEL); + if (!attrs) + return -ENODEV; + + /* + * Machine: Romulus BMC + * Family: AST2500 + * Revision: A1 + * SoC ID: raw silicon revision id + * Serial Nnumber: 64-bit chipid + */ + + np = of_find_node_by_path("/"); + of_property_read_string(np, "model", &machine); + if (machine) + attrs->machine = kstrdup(machine, GFP_KERNEL); + of_node_put(np); + + attrs->family = kasprintf(GFP_KERNEL, "%s", + siliconid_to_name(siliconid)); + + attrs->revision = kasprintf(GFP_KERNEL, "%s", + siliconid_to_rev(siliconid)); + + attrs->soc_id = kasprintf(GFP_KERNEL, "%08x", siliconid); + + if (has_chipid) { + attrs->serial_number = kasprintf(GFP_KERNEL, "%08x%08x", + chipid[1], chipid[0]); + } + + soc_dev = soc_device_register(attrs); + if (IS_ERR(soc_dev)) { + kfree(attrs->family); + kfree(attrs->revision); + kfree(attrs->soc_id); + kfree(attrs->serial_number); + kfree(attrs); + return PTR_ERR(soc_dev); + } + + pr_info("ASPEED BMC %s rev %s (%s)\n", + attrs->family, + attrs->revision, + attrs->soc_id); + + return 0; +} +early_initcall(aspeed_socinfo_init); From patchwork Wed Sep 16 08:47:03 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joel Stanley X-Patchwork-Id: 1365061 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [203.11.71.2]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4Brtyq3Zlsz9sSC for ; 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Wed, 16 Sep 2020 01:47:29 -0700 (PDT) From: Joel Stanley To: Rob Herring Subject: [PATCH 3/3] ARM: dts: aspeed: Add silicon id node Date: Wed, 16 Sep 2020 18:17:03 +0930 Message-Id: <20200916084703.778386-4-joel@jms.id.au> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20200916084703.778386-1-joel@jms.id.au> References: <20200916084703.778386-1-joel@jms.id.au> MIME-Version: 1.0 X-BeenThere: linux-aspeed@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux ASPEED SoC development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-aspeed@lists.ozlabs.org, linux-arm-kernel@lists.infradead.org Errors-To: linux-aspeed-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Linux-aspeed" This register describes the silicon id and chip unique id. It varies between CPU revisions, but is always part of the SCU. Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-g4.dtsi | 5 +++++ arch/arm/boot/dts/aspeed-g5.dtsi | 5 +++++ arch/arm/boot/dts/aspeed-g6.dtsi | 5 +++++ 3 files changed, 15 insertions(+) diff --git a/arch/arm/boot/dts/aspeed-g4.dtsi b/arch/arm/boot/dts/aspeed-g4.dtsi index 82f0213e3a3c..bc580b75f801 100644 --- a/arch/arm/boot/dts/aspeed-g4.dtsi +++ b/arch/arm/boot/dts/aspeed-g4.dtsi @@ -192,6 +192,11 @@ p2a: p2a-control@2c { status = "disabled"; }; + silicon-id@7c { + compatible = "aspeed,ast2400-silicon-id", "aspeed,silicon-id"; + reg = <0x7c 0x4>; + }; + pinctrl: pinctrl@80 { reg = <0x80 0x18>, <0xa0 0x10>; compatible = "aspeed,ast2400-pinctrl"; diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi index 9c91afb2b404..c6862182313a 100644 --- a/arch/arm/boot/dts/aspeed-g5.dtsi +++ b/arch/arm/boot/dts/aspeed-g5.dtsi @@ -239,6 +239,11 @@ p2a: p2a-control@2c { status = "disabled"; }; + silicon-id@7c { + compatible = "aspeed,ast2500-silicon-id", "aspeed,silicon-id"; + reg = <0x7c 0x4 0x150 0x8>; + }; + pinctrl: pinctrl@80 { compatible = "aspeed,ast2500-pinctrl"; reg = <0x80 0x18>, <0xa0 0x10>; diff --git a/arch/arm/boot/dts/aspeed-g6.dtsi b/arch/arm/boot/dts/aspeed-g6.dtsi index b58220a49cbd..1ce3a1f06f7f 100644 --- a/arch/arm/boot/dts/aspeed-g6.dtsi +++ b/arch/arm/boot/dts/aspeed-g6.dtsi @@ -311,6 +311,11 @@ pinctrl: pinctrl { compatible = "aspeed,ast2600-pinctrl"; }; + silicon-id@14 { + compatible = "aspeed,ast2600-silicon-id", "aspeed,silicon-id"; + reg = <0x14 0x4 0x5b0 0x8>; + }; + smp-memram@180 { compatible = "aspeed,ast2600-smpmem"; reg = <0x180 0x40>;