From patchwork Tue Sep 8 10:24:38 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abel Vesa X-Patchwork-Id: 1359652 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=nxp.com Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4Bm1Xk4xVSz9sTR for ; Tue, 8 Sep 2020 20:26:46 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729576AbgIHK0l (ORCPT ); Tue, 8 Sep 2020 06:26:41 -0400 Received: from inva021.nxp.com ([92.121.34.21]:56194 "EHLO inva021.nxp.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729333AbgIHK0J (ORCPT ); Tue, 8 Sep 2020 06:26:09 -0400 Received: from inva021.nxp.com (localhost [127.0.0.1]) by inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id 7333320021E; Tue, 8 Sep 2020 12:26:06 +0200 (CEST) Received: from inva024.eu-rdc02.nxp.com (inva024.eu-rdc02.nxp.com [134.27.226.22]) by inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id 64A29201595; Tue, 8 Sep 2020 12:26:06 +0200 (CEST) Received: from fsr-ub1664-175.ea.freescale.net (fsr-ub1664-175.ea.freescale.net [10.171.82.40]) by inva024.eu-rdc02.nxp.com (Postfix) with ESMTP id 9677D2036D; Tue, 8 Sep 2020 12:26:05 +0200 (CEST) From: Abel Vesa To: Mike Turquette , Stephen Boyd , Rob Herring , Shawn Guo , Sascha Hauer , Fabio Estevam , Philipp Zabel , Anson Huang , Jacky Bai , Peng Fan , Dong Aisheng , Fugang Duan , devicetree@vger.kernel.org Cc: NXP Linux Team , linux-arm-kernel@lists.infradead.org, Linux Kernel Mailing List , linux-clk@vger.kernel.org, Abel Vesa Subject: [PATCH v3 01/14] dt-bindings: clocks: imx8mp: Rename audiomix ids clocks to audio_blk_ctl Date: Tue, 8 Sep 2020 13:24:38 +0300 Message-Id: <1599560691-3763-2-git-send-email-abel.vesa@nxp.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1599560691-3763-1-git-send-email-abel.vesa@nxp.com> References: <1599560691-3763-1-git-send-email-abel.vesa@nxp.com> X-Virus-Scanned: ClamAV using ClamSMTP Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org In the reference manual the actual name is Audio BLK_CTL. Lets make it more obvious here by renaming from audiomix to audio_blk_ctl. Signed-off-by: Abel Vesa Acked-by: Rob Herring Reviewed-by: Dong Aisheng --- include/dt-bindings/clock/imx8mp-clock.h | 120 +++++++++++++++---------------- 1 file changed, 60 insertions(+), 60 deletions(-) diff --git a/include/dt-bindings/clock/imx8mp-clock.h b/include/dt-bindings/clock/imx8mp-clock.h index e8d68fb..89c67b7 100644 --- a/include/dt-bindings/clock/imx8mp-clock.h +++ b/include/dt-bindings/clock/imx8mp-clock.h @@ -324,66 +324,66 @@ #define IMX8MP_CLK_END 313 -#define IMX8MP_CLK_AUDIOMIX_SAI1_IPG 0 -#define IMX8MP_CLK_AUDIOMIX_SAI1_MCLK1 1 -#define IMX8MP_CLK_AUDIOMIX_SAI1_MCLK2 2 -#define IMX8MP_CLK_AUDIOMIX_SAI1_MCLK3 3 -#define IMX8MP_CLK_AUDIOMIX_SAI2_IPG 4 -#define IMX8MP_CLK_AUDIOMIX_SAI2_MCLK1 5 -#define IMX8MP_CLK_AUDIOMIX_SAI2_MCLK2 6 -#define IMX8MP_CLK_AUDIOMIX_SAI2_MCLK3 7 -#define IMX8MP_CLK_AUDIOMIX_SAI3_IPG 8 -#define IMX8MP_CLK_AUDIOMIX_SAI3_MCLK1 9 -#define IMX8MP_CLK_AUDIOMIX_SAI3_MCLK2 10 -#define IMX8MP_CLK_AUDIOMIX_SAI3_MCLK3 11 -#define IMX8MP_CLK_AUDIOMIX_SAI5_IPG 12 -#define IMX8MP_CLK_AUDIOMIX_SAI5_MCLK1 13 -#define IMX8MP_CLK_AUDIOMIX_SAI5_MCLK2 14 -#define IMX8MP_CLK_AUDIOMIX_SAI5_MCLK3 15 -#define IMX8MP_CLK_AUDIOMIX_SAI6_IPG 16 -#define IMX8MP_CLK_AUDIOMIX_SAI6_MCLK1 17 -#define IMX8MP_CLK_AUDIOMIX_SAI6_MCLK2 18 -#define IMX8MP_CLK_AUDIOMIX_SAI6_MCLK3 19 -#define IMX8MP_CLK_AUDIOMIX_SAI7_IPG 20 -#define IMX8MP_CLK_AUDIOMIX_SAI7_MCLK1 21 -#define IMX8MP_CLK_AUDIOMIX_SAI7_MCLK2 22 -#define IMX8MP_CLK_AUDIOMIX_SAI7_MCLK3 23 -#define IMX8MP_CLK_AUDIOMIX_ASRC_IPG 24 -#define IMX8MP_CLK_AUDIOMIX_PDM_IPG 25 -#define IMX8MP_CLK_AUDIOMIX_SDMA2_ROOT 26 -#define IMX8MP_CLK_AUDIOMIX_SDMA3_ROOT 27 -#define IMX8MP_CLK_AUDIOMIX_SPBA2_ROOT 28 -#define IMX8MP_CLK_AUDIOMIX_DSP_ROOT 29 -#define IMX8MP_CLK_AUDIOMIX_DSPDBG_ROOT 30 -#define IMX8MP_CLK_AUDIOMIX_EARC_IPG 31 -#define IMX8MP_CLK_AUDIOMIX_OCRAMA_IPG 32 -#define IMX8MP_CLK_AUDIOMIX_AUD2HTX_IPG 33 -#define IMX8MP_CLK_AUDIOMIX_EDMA_ROOT 34 -#define IMX8MP_CLK_AUDIOMIX_AUDPLL_ROOT 35 -#define IMX8MP_CLK_AUDIOMIX_MU2_ROOT 36 -#define IMX8MP_CLK_AUDIOMIX_MU3_ROOT 37 -#define IMX8MP_CLK_AUDIOMIX_EARC_PHY 38 -#define IMX8MP_CLK_AUDIOMIX_PDM_ROOT 39 -#define IMX8MP_CLK_AUDIOMIX_SAI1_MCLK1_SEL 40 -#define IMX8MP_CLK_AUDIOMIX_SAI1_MCLK2_SEL 41 -#define IMX8MP_CLK_AUDIOMIX_SAI2_MCLK1_SEL 42 -#define IMX8MP_CLK_AUDIOMIX_SAI2_MCLK2_SEL 43 -#define IMX8MP_CLK_AUDIOMIX_SAI3_MCLK1_SEL 44 -#define IMX8MP_CLK_AUDIOMIX_SAI3_MCLK2_SEL 45 -#define IMX8MP_CLK_AUDIOMIX_SAI4_MCLK1_SEL 46 -#define IMX8MP_CLK_AUDIOMIX_SAI4_MCLK2_SEL 47 -#define IMX8MP_CLK_AUDIOMIX_SAI5_MCLK1_SEL 48 -#define IMX8MP_CLK_AUDIOMIX_SAI5_MCLK2_SEL 49 -#define IMX8MP_CLK_AUDIOMIX_SAI6_MCLK1_SEL 50 -#define IMX8MP_CLK_AUDIOMIX_SAI6_MCLK2_SEL 51 -#define IMX8MP_CLK_AUDIOMIX_SAI7_MCLK1_SEL 52 -#define IMX8MP_CLK_AUDIOMIX_SAI7_MCLK2_SEL 53 -#define IMX8MP_CLK_AUDIOMIX_PDM_SEL 54 -#define IMX8MP_CLK_AUDIOMIX_SAI_PLL_REF_SEL 55 -#define IMX8MP_CLK_AUDIOMIX_SAI_PLL 56 -#define IMX8MP_CLK_AUDIOMIX_SAI_PLL_BYPASS 57 -#define IMX8MP_CLK_AUDIOMIX_SAI_PLL_OUT 58 +#define IMX8MP_CLK_AUDIO_BLK_CTL_SAI1_IPG 0 +#define IMX8MP_CLK_AUDIO_BLK_CTL_SAI1_MCLK1 1 +#define IMX8MP_CLK_AUDIO_BLK_CTL_SAI1_MCLK2 2 +#define IMX8MP_CLK_AUDIO_BLK_CTL_SAI1_MCLK3 3 +#define IMX8MP_CLK_AUDIO_BLK_CTL_SAI2_IPG 4 +#define IMX8MP_CLK_AUDIO_BLK_CTL_SAI2_MCLK1 5 +#define IMX8MP_CLK_AUDIO_BLK_CTL_SAI2_MCLK2 6 +#define IMX8MP_CLK_AUDIO_BLK_CTL_SAI2_MCLK3 7 +#define IMX8MP_CLK_AUDIO_BLK_CTL_SAI3_IPG 8 +#define IMX8MP_CLK_AUDIO_BLK_CTL_SAI3_MCLK1 9 +#define IMX8MP_CLK_AUDIO_BLK_CTL_SAI3_MCLK2 10 +#define IMX8MP_CLK_AUDIO_BLK_CTL_SAI3_MCLK3 11 +#define IMX8MP_CLK_AUDIO_BLK_CTL_SAI5_IPG 12 +#define IMX8MP_CLK_AUDIO_BLK_CTL_SAI5_MCLK1 13 +#define IMX8MP_CLK_AUDIO_BLK_CTL_SAI5_MCLK2 14 +#define IMX8MP_CLK_AUDIO_BLK_CTL_SAI5_MCLK3 15 +#define IMX8MP_CLK_AUDIO_BLK_CTL_SAI6_IPG 16 +#define IMX8MP_CLK_AUDIO_BLK_CTL_SAI6_MCLK1 17 +#define IMX8MP_CLK_AUDIO_BLK_CTL_SAI6_MCLK2 18 +#define IMX8MP_CLK_AUDIO_BLK_CTL_SAI6_MCLK3 19 +#define IMX8MP_CLK_AUDIO_BLK_CTL_SAI7_IPG 20 +#define IMX8MP_CLK_AUDIO_BLK_CTL_SAI7_MCLK1 21 +#define IMX8MP_CLK_AUDIO_BLK_CTL_SAI7_MCLK2 22 +#define IMX8MP_CLK_AUDIO_BLK_CTL_SAI7_MCLK3 23 +#define IMX8MP_CLK_AUDIO_BLK_CTL_ASRC_IPG 24 +#define IMX8MP_CLK_AUDIO_BLK_CTL_PDM_IPG 25 +#define IMX8MP_CLK_AUDIO_BLK_CTL_SDMA2_ROOT 26 +#define IMX8MP_CLK_AUDIO_BLK_CTL_SDMA3_ROOT 27 +#define IMX8MP_CLK_AUDIO_BLK_CTL_SPBA2_ROOT 28 +#define IMX8MP_CLK_AUDIO_BLK_CTL_DSP_ROOT 29 +#define IMX8MP_CLK_AUDIO_BLK_CTL_DSPDBG_ROOT 30 +#define IMX8MP_CLK_AUDIO_BLK_CTL_EARC_IPG 31 +#define IMX8MP_CLK_AUDIO_BLK_CTL_OCRAMA_IPG 32 +#define IMX8MP_CLK_AUDIO_BLK_CTL_AUD2HTX_IPG 33 +#define IMX8MP_CLK_AUDIO_BLK_CTL_EDMA_ROOT 34 +#define IMX8MP_CLK_AUDIO_BLK_CTL_AUDPLL_ROOT 35 +#define IMX8MP_CLK_AUDIO_BLK_CTL_MU2_ROOT 36 +#define IMX8MP_CLK_AUDIO_BLK_CTL_MU3_ROOT 37 +#define IMX8MP_CLK_AUDIO_BLK_CTL_EARC_PHY 38 +#define IMX8MP_CLK_AUDIO_BLK_CTL_PDM_ROOT 39 +#define IMX8MP_CLK_AUDIO_BLK_CTL_SAI1_MCLK1_SEL 40 +#define IMX8MP_CLK_AUDIO_BLK_CTL_SAI1_MCLK2_SEL 41 +#define IMX8MP_CLK_AUDIO_BLK_CTL_SAI2_MCLK1_SEL 42 +#define IMX8MP_CLK_AUDIO_BLK_CTL_SAI2_MCLK2_SEL 43 +#define IMX8MP_CLK_AUDIO_BLK_CTL_SAI3_MCLK1_SEL 44 +#define IMX8MP_CLK_AUDIO_BLK_CTL_SAI3_MCLK2_SEL 45 +#define IMX8MP_CLK_AUDIO_BLK_CTL_SAI4_MCLK1_SEL 46 +#define IMX8MP_CLK_AUDIO_BLK_CTL_SAI4_MCLK2_SEL 47 +#define IMX8MP_CLK_AUDIO_BLK_CTL_SAI5_MCLK1_SEL 48 +#define IMX8MP_CLK_AUDIO_BLK_CTL_SAI5_MCLK2_SEL 49 +#define IMX8MP_CLK_AUDIO_BLK_CTL_SAI6_MCLK1_SEL 50 +#define IMX8MP_CLK_AUDIO_BLK_CTL_SAI6_MCLK2_SEL 51 +#define IMX8MP_CLK_AUDIO_BLK_CTL_SAI7_MCLK1_SEL 52 +#define IMX8MP_CLK_AUDIO_BLK_CTL_SAI7_MCLK2_SEL 53 +#define IMX8MP_CLK_AUDIO_BLK_CTL_PDM_SEL 54 +#define IMX8MP_CLK_AUDIO_BLK_CTL_SAI_PLL_REF_SEL 55 +#define IMX8MP_CLK_AUDIO_BLK_CTL_SAI_PLL 56 +#define IMX8MP_CLK_AUDIO_BLK_CTL_SAI_PLL_BYPASS 57 +#define IMX8MP_CLK_AUDIO_BLK_CTL_SAI_PLL_OUT 58 -#define IMX8MP_CLK_AUDIOMIX_END 59 +#define IMX8MP_CLK_AUDIO_BLK_CTL_END 59 #endif From patchwork Tue Sep 8 10:24:39 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abel Vesa X-Patchwork-Id: 1359654 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=nxp.com Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4Bm1b25ZDMz9sT6 for ; Tue, 8 Sep 2020 20:28:46 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729572AbgIHK0j (ORCPT ); Tue, 8 Sep 2020 06:26:39 -0400 Received: from inva021.nxp.com ([92.121.34.21]:56212 "EHLO inva021.nxp.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729496AbgIHK0I (ORCPT ); Tue, 8 Sep 2020 06:26:08 -0400 Received: from inva021.nxp.com (localhost [127.0.0.1]) by inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id 3A2CB2011AF; Tue, 8 Sep 2020 12:26:07 +0200 (CEST) Received: from inva024.eu-rdc02.nxp.com (inva024.eu-rdc02.nxp.com [134.27.226.22]) by inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id 2DDE720119C; Tue, 8 Sep 2020 12:26:07 +0200 (CEST) Received: from fsr-ub1664-175.ea.freescale.net (fsr-ub1664-175.ea.freescale.net [10.171.82.40]) by inva024.eu-rdc02.nxp.com (Postfix) with ESMTP id 742C420327; Tue, 8 Sep 2020 12:26:06 +0200 (CEST) From: Abel Vesa To: Mike Turquette , Stephen Boyd , Rob Herring , Shawn Guo , Sascha Hauer , Fabio Estevam , Philipp Zabel , Anson Huang , Jacky Bai , Peng Fan , Dong Aisheng , Fugang Duan , devicetree@vger.kernel.org Cc: NXP Linux Team , linux-arm-kernel@lists.infradead.org, Linux Kernel Mailing List , linux-clk@vger.kernel.org, Abel Vesa Subject: [PATCH v3 02/14] dt-bindings: reset: imx8mp: Add audio blk_ctl reset IDs Date: Tue, 8 Sep 2020 13:24:39 +0300 Message-Id: <1599560691-3763-3-git-send-email-abel.vesa@nxp.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1599560691-3763-1-git-send-email-abel.vesa@nxp.com> References: <1599560691-3763-1-git-send-email-abel.vesa@nxp.com> X-Virus-Scanned: ClamAV using ClamSMTP Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org These will be used by the imx8mp for blk_ctl driver. Signed-off-by: Abel Vesa Acked-by: Rob Herring Reviewed-by: Dong Aisheng --- include/dt-bindings/reset/imx8mp-reset.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/include/dt-bindings/reset/imx8mp-reset.h b/include/dt-bindings/reset/imx8mp-reset.h index 2e8c910..6c7f17f 100644 --- a/include/dt-bindings/reset/imx8mp-reset.h +++ b/include/dt-bindings/reset/imx8mp-reset.h @@ -47,4 +47,9 @@ #define IMX8MP_RESET_NUM 38 +#define IMX8MP_AUDIO_BLK_CTL_EARC_RESET 0 +#define IMX8MP_AUDIO_BLK_CTL_EARC_PHY_RESET 1 + +#define IMX8MP_AUDIO_BLK_CTL_RESET_NUM 2 + #endif From patchwork Tue Sep 8 10:24:40 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abel Vesa X-Patchwork-Id: 1359667 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=nxp.com Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4Bm1sV1vcvz9sSn for ; Tue, 8 Sep 2020 20:41:18 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729824AbgIHKdf (ORCPT ); Tue, 8 Sep 2020 06:33:35 -0400 Received: from inva020.nxp.com ([92.121.34.13]:44786 "EHLO inva020.nxp.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729512AbgIHK0e (ORCPT ); Tue, 8 Sep 2020 06:26:34 -0400 Received: from inva020.nxp.com (localhost [127.0.0.1]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 07BD91A032D; Tue, 8 Sep 2020 12:26:08 +0200 (CEST) Received: from inva024.eu-rdc02.nxp.com (inva024.eu-rdc02.nxp.com [134.27.226.22]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id EC12A1A0335; Tue, 8 Sep 2020 12:26:07 +0200 (CEST) Received: from fsr-ub1664-175.ea.freescale.net (fsr-ub1664-175.ea.freescale.net [10.171.82.40]) by inva024.eu-rdc02.nxp.com (Postfix) with ESMTP id 3DBB820327; Tue, 8 Sep 2020 12:26:07 +0200 (CEST) From: Abel Vesa To: Mike Turquette , Stephen Boyd , Rob Herring , Shawn Guo , Sascha Hauer , Fabio Estevam , Philipp Zabel , Anson Huang , Jacky Bai , Peng Fan , Dong Aisheng , Fugang Duan , devicetree@vger.kernel.org Cc: NXP Linux Team , linux-arm-kernel@lists.infradead.org, Linux Kernel Mailing List , linux-clk@vger.kernel.org, Abel Vesa Subject: [PATCH v3 03/14] dt-bindings: clock: imx8mp: Add ids for the audio shared gate Date: Tue, 8 Sep 2020 13:24:40 +0300 Message-Id: <1599560691-3763-4-git-send-email-abel.vesa@nxp.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1599560691-3763-1-git-send-email-abel.vesa@nxp.com> References: <1599560691-3763-1-git-send-email-abel.vesa@nxp.com> X-Virus-Scanned: ClamAV using ClamSMTP Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org All these IDs are for one single HW gate (CCGR101) that is shared between these root clocks. Signed-off-by: Abel Vesa Acked-by: Rob Herring Reviewed-by: Dong Aisheng --- include/dt-bindings/clock/imx8mp-clock.h | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/include/dt-bindings/clock/imx8mp-clock.h b/include/dt-bindings/clock/imx8mp-clock.h index 89c67b7..5fc2c40 100644 --- a/include/dt-bindings/clock/imx8mp-clock.h +++ b/include/dt-bindings/clock/imx8mp-clock.h @@ -322,7 +322,17 @@ #define IMX8MP_CLK_HSIO_AXI 311 #define IMX8MP_CLK_MEDIA_ISP 312 -#define IMX8MP_CLK_END 313 +#define IMX8MP_CLK_AUDIO_AHB_ROOT 313 +#define IMX8MP_CLK_AUDIO_AXI_ROOT 314 +#define IMX8MP_CLK_SAI1_ROOT 315 +#define IMX8MP_CLK_SAI2_ROOT 316 +#define IMX8MP_CLK_SAI3_ROOT 317 +#define IMX8MP_CLK_SAI5_ROOT 318 +#define IMX8MP_CLK_SAI6_ROOT 319 +#define IMX8MP_CLK_SAI7_ROOT 320 +#define IMX8MP_CLK_PDM_ROOT 321 + +#define IMX8MP_CLK_END 322 #define IMX8MP_CLK_AUDIO_BLK_CTL_SAI1_IPG 0 #define IMX8MP_CLK_AUDIO_BLK_CTL_SAI1_MCLK1 1 From patchwork Tue Sep 8 10:24:41 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abel Vesa X-Patchwork-Id: 1359664 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=nxp.com Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4Bm1hm5788z9sSn for ; Tue, 8 Sep 2020 20:33:44 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729368AbgIHKdf (ORCPT ); Tue, 8 Sep 2020 06:33:35 -0400 Received: from inva020.nxp.com ([92.121.34.13]:44830 "EHLO inva020.nxp.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729278AbgIHK0i (ORCPT ); Tue, 8 Sep 2020 06:26:38 -0400 Received: from inva020.nxp.com (localhost [127.0.0.1]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id BCEFD1A0335; Tue, 8 Sep 2020 12:26:08 +0200 (CEST) Received: from inva024.eu-rdc02.nxp.com (inva024.eu-rdc02.nxp.com [134.27.226.22]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id ABEB91A032F; Tue, 8 Sep 2020 12:26:08 +0200 (CEST) Received: from fsr-ub1664-175.ea.freescale.net (fsr-ub1664-175.ea.freescale.net [10.171.82.40]) by inva024.eu-rdc02.nxp.com (Postfix) with ESMTP id 078FE2036D; Tue, 8 Sep 2020 12:26:07 +0200 (CEST) From: Abel Vesa To: Mike Turquette , Stephen Boyd , Rob Herring , Shawn Guo , Sascha Hauer , Fabio Estevam , Philipp Zabel , Anson Huang , Jacky Bai , Peng Fan , Dong Aisheng , Fugang Duan , devicetree@vger.kernel.org Cc: NXP Linux Team , linux-arm-kernel@lists.infradead.org, Linux Kernel Mailing List , linux-clk@vger.kernel.org, Abel Vesa Subject: [PATCH v3 04/14] dt-bindings: clock: imx8mp: Add media blk_ctl clock IDs Date: Tue, 8 Sep 2020 13:24:41 +0300 Message-Id: <1599560691-3763-5-git-send-email-abel.vesa@nxp.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1599560691-3763-1-git-send-email-abel.vesa@nxp.com> References: <1599560691-3763-1-git-send-email-abel.vesa@nxp.com> X-Virus-Scanned: ClamAV using ClamSMTP Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org These will be used by the imx8mp for blk_ctl driver. Signed-off-by: Abel Vesa Acked-by: Rob Herring Reviewed-by: Dong Aisheng --- include/dt-bindings/clock/imx8mp-clock.h | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/include/dt-bindings/clock/imx8mp-clock.h b/include/dt-bindings/clock/imx8mp-clock.h index 5fc2c40..12632fa 100644 --- a/include/dt-bindings/clock/imx8mp-clock.h +++ b/include/dt-bindings/clock/imx8mp-clock.h @@ -396,4 +396,32 @@ #define IMX8MP_CLK_AUDIO_BLK_CTL_END 59 +#define IMX8MP_CLK_MEDIA_BLK_CTL_MIPI_DSI_PCLK 0 +#define IMX8MP_CLK_MEDIA_BLK_CTL_MIPI_DSI_CLKREF 1 +#define IMX8MP_CLK_MEDIA_BLK_CTL_MIPI_CSI_PCLK 2 +#define IMX8MP_CLK_MEDIA_BLK_CTL_MIPI_CSI_ACLK 3 +#define IMX8MP_CLK_MEDIA_BLK_CTL_LCDIF_PIXEL 4 +#define IMX8MP_CLK_MEDIA_BLK_CTL_LCDIF_APB 5 +#define IMX8MP_CLK_MEDIA_BLK_CTL_ISI_PROC 6 +#define IMX8MP_CLK_MEDIA_BLK_CTL_ISI_APB 7 +#define IMX8MP_CLK_MEDIA_BLK_CTL_BUS_BLK 8 +#define IMX8MP_CLK_MEDIA_BLK_CTL_MIPI_CSI2_PCLK 9 +#define IMX8MP_CLK_MEDIA_BLK_CTL_MIPI_CSI2_ACLK 10 +#define IMX8MP_CLK_MEDIA_BLK_CTL_LCDIF2_PIXEL 11 +#define IMX8MP_CLK_MEDIA_BLK_CTL_LCDIF2_APB 12 +#define IMX8MP_CLK_MEDIA_BLK_CTL_ISP1_COR 13 +#define IMX8MP_CLK_MEDIA_BLK_CTL_ISP1_AXI 14 +#define IMX8MP_CLK_MEDIA_BLK_CTL_ISP1_AHB 15 +#define IMX8MP_CLK_MEDIA_BLK_CTL_ISP0_COR 16 +#define IMX8MP_CLK_MEDIA_BLK_CTL_ISP0_AXI 17 +#define IMX8MP_CLK_MEDIA_BLK_CTL_ISP0_AHB 18 +#define IMX8MP_CLK_MEDIA_BLK_CTL_DWE_COR 19 +#define IMX8MP_CLK_MEDIA_BLK_CTL_DWE_AXI 20 +#define IMX8MP_CLK_MEDIA_BLK_CTL_DWE_AHB 21 +#define IMX8MP_CLK_MEDIA_BLK_CTL_MIPI_DSI2 22 +#define IMX8MP_CLK_MEDIA_BLK_CTL_LCDIF_AXI 23 +#define IMX8MP_CLK_MEDIA_BLK_CTL_LCDIF2_AXI 24 + +#define IMX8MP_CLK_MEDIA_BLK_CTL_END 25 + #endif From patchwork Tue Sep 8 10:24:42 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abel Vesa X-Patchwork-Id: 1359656 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=nxp.com Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4Bm1bT17n1z9sSn for ; Tue, 8 Sep 2020 20:29:09 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729953AbgIHK3F (ORCPT ); Tue, 8 Sep 2020 06:29:05 -0400 Received: from inva020.nxp.com ([92.121.34.13]:44848 "EHLO inva020.nxp.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729527AbgIHK0i (ORCPT ); Tue, 8 Sep 2020 06:26:38 -0400 Received: from inva020.nxp.com (localhost [127.0.0.1]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 7B5711A034D; Tue, 8 Sep 2020 12:26:09 +0200 (CEST) Received: from inva024.eu-rdc02.nxp.com (inva024.eu-rdc02.nxp.com [134.27.226.22]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 6E96E1A0344; Tue, 8 Sep 2020 12:26:09 +0200 (CEST) Received: from fsr-ub1664-175.ea.freescale.net (fsr-ub1664-175.ea.freescale.net [10.171.82.40]) by inva024.eu-rdc02.nxp.com (Postfix) with ESMTP id BBBF220327; Tue, 8 Sep 2020 12:26:08 +0200 (CEST) From: Abel Vesa To: Mike Turquette , Stephen Boyd , Rob Herring , Shawn Guo , Sascha Hauer , Fabio Estevam , Philipp Zabel , Anson Huang , Jacky Bai , Peng Fan , Dong Aisheng , Fugang Duan , devicetree@vger.kernel.org Cc: NXP Linux Team , linux-arm-kernel@lists.infradead.org, Linux Kernel Mailing List , linux-clk@vger.kernel.org, Abel Vesa Subject: [PATCH v3 05/14] dt-bindings: reset: imx8mp: Add media blk_ctl reset IDs Date: Tue, 8 Sep 2020 13:24:42 +0300 Message-Id: <1599560691-3763-6-git-send-email-abel.vesa@nxp.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1599560691-3763-1-git-send-email-abel.vesa@nxp.com> References: <1599560691-3763-1-git-send-email-abel.vesa@nxp.com> X-Virus-Scanned: ClamAV using ClamSMTP Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org These will be used by the imx8mp for blk_ctl driver. Signed-off-by: Abel Vesa Acked-by: Rob Herring Reviewed-by: Dong Aisheng --- include/dt-bindings/reset/imx8mp-reset.h | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/include/dt-bindings/reset/imx8mp-reset.h b/include/dt-bindings/reset/imx8mp-reset.h index 6c7f17f..ba70248 100644 --- a/include/dt-bindings/reset/imx8mp-reset.h +++ b/include/dt-bindings/reset/imx8mp-reset.h @@ -52,4 +52,32 @@ #define IMX8MP_AUDIO_BLK_CTL_RESET_NUM 2 +#define IMX8MP_MEDIA_BLK_CTL_RESET_MIPI_DSI_PCLK 0 +#define IMX8MP_MEDIA_BLK_CTL_RESET_MIPI_DSI_CLKREF 1 +#define IMX8MP_MEDIA_BLK_CTL_RESET_MIPI_CSI_PCLK 2 +#define IMX8MP_MEDIA_BLK_CTL_RESET_MIPI_CSI_ACLK 3 +#define IMX8MP_MEDIA_BLK_CTL_RESET_LCDIF_PIXEL 4 +#define IMX8MP_MEDIA_BLK_CTL_RESET_LCDIF_APB 5 +#define IMX8MP_MEDIA_BLK_CTL_RESET_ISI_PROC 6 +#define IMX8MP_MEDIA_BLK_CTL_RESET_ISI_APB 7 +#define IMX8MP_MEDIA_BLK_CTL_RESET_BUS_BLK 8 +#define IMX8MP_MEDIA_BLK_CTL_RESET_MIPI_CSI2_PCLK 9 +#define IMX8MP_MEDIA_BLK_CTL_RESET_MIPI_CSI2_ACLK 10 +#define IMX8MP_MEDIA_BLK_CTL_RESET_LCDIF2_PIXEL 11 +#define IMX8MP_MEDIA_BLK_CTL_RESET_LCDIF2_APB 12 +#define IMX8MP_MEDIA_BLK_CTL_RESET_ISP1_COR 13 +#define IMX8MP_MEDIA_BLK_CTL_RESET_ISP1_AXI 14 +#define IMX8MP_MEDIA_BLK_CTL_RESET_ISP1_AHB 15 +#define IMX8MP_MEDIA_BLK_CTL_RESET_ISP0_COR 16 +#define IMX8MP_MEDIA_BLK_CTL_RESET_ISP0_AXI 17 +#define IMX8MP_MEDIA_BLK_CTL_RESET_ISP0_AHB 18 +#define IMX8MP_MEDIA_BLK_CTL_RESET_DWE_COR 19 +#define IMX8MP_MEDIA_BLK_CTL_RESET_DWE_AXI 20 +#define IMX8MP_MEDIA_BLK_CTL_RESET_DWE_AHB 21 +#define IMX8MP_MEDIA_BLK_CTL_RESET_MIPI_DSI2 22 +#define IMX8MP_MEDIA_BLK_CTL_RESET_LCDIF_AXI 23 +#define IMX8MP_MEDIA_BLK_CTL_RESET_LCDIF2_AXI 24 + +#define IMX8MP_MEDIA_BLK_CTL_RESET_NUM 25 + #endif From patchwork Tue Sep 8 10:24:43 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abel Vesa X-Patchwork-Id: 1359660 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=nxp.com Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4Bm1gj6MwWz9sSn for ; Tue, 8 Sep 2020 20:32:49 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729422AbgIHK3C (ORCPT ); Tue, 8 Sep 2020 06:29:02 -0400 Received: from inva020.nxp.com ([92.121.34.13]:44896 "EHLO inva020.nxp.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729489AbgIHK0i (ORCPT ); Tue, 8 Sep 2020 06:26:38 -0400 Received: from inva020.nxp.com (localhost [127.0.0.1]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 3CA701A035F; Tue, 8 Sep 2020 12:26:10 +0200 (CEST) Received: from inva024.eu-rdc02.nxp.com (inva024.eu-rdc02.nxp.com [134.27.226.22]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 2ED6A1A0339; Tue, 8 Sep 2020 12:26:10 +0200 (CEST) Received: from fsr-ub1664-175.ea.freescale.net (fsr-ub1664-175.ea.freescale.net [10.171.82.40]) by inva024.eu-rdc02.nxp.com (Postfix) with ESMTP id 7E33220327; Tue, 8 Sep 2020 12:26:09 +0200 (CEST) From: Abel Vesa To: Mike Turquette , Stephen Boyd , Rob Herring , Shawn Guo , Sascha Hauer , Fabio Estevam , Philipp Zabel , Anson Huang , Jacky Bai , Peng Fan , Dong Aisheng , Fugang Duan , devicetree@vger.kernel.org Cc: NXP Linux Team , linux-arm-kernel@lists.infradead.org, Linux Kernel Mailing List , linux-clk@vger.kernel.org, Abel Vesa Subject: [PATCH v3 06/14] dt-bindings: clock: imx8mp: Add hdmi blk_ctl clock IDs Date: Tue, 8 Sep 2020 13:24:43 +0300 Message-Id: <1599560691-3763-7-git-send-email-abel.vesa@nxp.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1599560691-3763-1-git-send-email-abel.vesa@nxp.com> References: <1599560691-3763-1-git-send-email-abel.vesa@nxp.com> X-Virus-Scanned: ClamAV using ClamSMTP Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org These will be used by the imx8mp for blk_ctl driver. Signed-off-by: Abel Vesa Acked-by: Rob Herring Reviewed-by: Dong Aisheng --- include/dt-bindings/clock/imx8mp-clock.h | 40 ++++++++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/include/dt-bindings/clock/imx8mp-clock.h b/include/dt-bindings/clock/imx8mp-clock.h index 12632fa..de7d522 100644 --- a/include/dt-bindings/clock/imx8mp-clock.h +++ b/include/dt-bindings/clock/imx8mp-clock.h @@ -424,4 +424,44 @@ #define IMX8MP_CLK_MEDIA_BLK_CTL_END 25 +#define IMX8MP_CLK_HDMI_BLK_CTL_GLOBAL_APB_CLK 0 +#define IMX8MP_CLK_HDMI_BLK_CTL_GLOBAL_B_CLK 1 +#define IMX8MP_CLK_HDMI_BLK_CTL_GLOBAL_REF266M_CLK 2 +#define IMX8MP_CLK_HDMI_BLK_CTL_GLOBAL_XTAL24M_CLK 3 +#define IMX8MP_CLK_HDMI_BLK_CTL_GLOBAL_XTAL32K_CLK 4 +#define IMX8MP_CLK_HDMI_BLK_CTL_GLOBAL_TX_PIX_CLK 5 +#define IMX8MP_CLK_HDMI_BLK_CTL_IRQS_STEER_CLK 6 +#define IMX8MP_CLK_HDMI_BLK_CTL_NOC_HDMI_CLK 7 +#define IMX8MP_CLK_HDMI_BLK_CTL_NOC_HDCP_CLK 8 +#define IMX8MP_CLK_HDMI_BLK_CTL_LCDIF_APB_CLK 9 +#define IMX8MP_CLK_HDMI_BLK_CTL_LCDIF_B_CLK 10 +#define IMX8MP_CLK_HDMI_BLK_CTL_LCDIF_PDI_CLK 11 +#define IMX8MP_CLK_HDMI_BLK_CTL_LCDIF_PIX_CLK 12 +#define IMX8MP_CLK_HDMI_BLK_CTL_LCDIF_SPU_CLK 13 +#define IMX8MP_CLK_HDMI_BLK_CTL_FDCC_REF_CLK 14 +#define IMX8MP_CLK_HDMI_BLK_CTL_HRV_MWR_APB_CLK 15 +#define IMX8MP_CLK_HDMI_BLK_CTL_HRV_MWR_B_CLK 16 +#define IMX8MP_CLK_HDMI_BLK_CTL_HRV_MWR_CEA_CLK 17 +#define IMX8MP_CLK_HDMI_BLK_CTL_VSFD_CEA_CLK 18 +#define IMX8MP_CLK_HDMI_BLK_CTL_TX_HPI_CLK 19 +#define IMX8MP_CLK_HDMI_BLK_CTL_TX_APB_CLK 20 +#define IMX8MP_CLK_HDMI_BLK_CTL_TX_CEC_CLK 21 +#define IMX8MP_CLK_HDMI_BLK_CTL_TX_ESM_CLK 22 +#define IMX8MP_CLK_HDMI_BLK_CTL_TX_GPA_CLK 23 +#define IMX8MP_CLK_HDMI_BLK_CTL_TX_PIXEL_CLK 24 +#define IMX8MP_CLK_HDMI_BLK_CTL_TX_SFR_CLK 25 +#define IMX8MP_CLK_HDMI_BLK_CTL_TX_SKP_CLK 26 +#define IMX8MP_CLK_HDMI_BLK_CTL_TX_PREP_CLK 27 +#define IMX8MP_CLK_HDMI_BLK_CTL_TX_PHY_APB_CLK 28 +#define IMX8MP_CLK_HDMI_BLK_CTL_TX_PHY_INT_CLK 29 +#define IMX8MP_CLK_HDMI_BLK_CTL_TX_SEC_MEM_CLK 30 +#define IMX8MP_CLK_HDMI_BLK_CTL_TX_TRNG_SKP_CLK 31 +#define IMX8MP_CLK_HDMI_BLK_CTL_TX_VID_LINK_PIX_CLK 32 +#define IMX8MP_CLK_HDMI_BLK_CTL_TX_TRNG_APB_CLK 33 +#define IMX8MP_CLK_HDMI_BLK_CTL_HTXPHY_CLK_SEL 34 +#define IMX8MP_CLK_HDMI_BLK_CTL_LCDIF_CLK_SEL 35 +#define IMX8MP_CLK_HDMI_BLK_CTL_TX_PIPE_CLK_SEL 36 + +#define IMX8MP_CLK_HDMI_BLK_CTL_END 37 + #endif From patchwork Tue Sep 8 10:24:44 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abel Vesa X-Patchwork-Id: 1359665 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=nxp.com Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4Bm1jG4wBHz9sSn for ; Tue, 8 Sep 2020 20:34:10 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729954AbgIHKdn (ORCPT ); Tue, 8 Sep 2020 06:33:43 -0400 Received: from inva021.nxp.com ([92.121.34.21]:56324 "EHLO inva021.nxp.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729533AbgIHK0e (ORCPT ); Tue, 8 Sep 2020 06:26:34 -0400 Received: from inva021.nxp.com (localhost [127.0.0.1]) by inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id 05E632011C1; Tue, 8 Sep 2020 12:26:11 +0200 (CEST) Received: from inva024.eu-rdc02.nxp.com (inva024.eu-rdc02.nxp.com [134.27.226.22]) by inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id EDEF7201198; Tue, 8 Sep 2020 12:26:10 +0200 (CEST) Received: from fsr-ub1664-175.ea.freescale.net (fsr-ub1664-175.ea.freescale.net [10.171.82.40]) by inva024.eu-rdc02.nxp.com (Postfix) with ESMTP id 3EB4420327; Tue, 8 Sep 2020 12:26:10 +0200 (CEST) From: Abel Vesa To: Mike Turquette , Stephen Boyd , Rob Herring , Shawn Guo , Sascha Hauer , Fabio Estevam , Philipp Zabel , Anson Huang , Jacky Bai , Peng Fan , Dong Aisheng , Fugang Duan , devicetree@vger.kernel.org Cc: NXP Linux Team , linux-arm-kernel@lists.infradead.org, Linux Kernel Mailing List , linux-clk@vger.kernel.org, Abel Vesa Subject: [PATCH v3 07/14] dt-bindings: reset: imx8mp: Add hdmi blk_ctl reset IDs Date: Tue, 8 Sep 2020 13:24:44 +0300 Message-Id: <1599560691-3763-8-git-send-email-abel.vesa@nxp.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1599560691-3763-1-git-send-email-abel.vesa@nxp.com> References: <1599560691-3763-1-git-send-email-abel.vesa@nxp.com> X-Virus-Scanned: ClamAV using ClamSMTP Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org These will be used imx8mp for blk_ctl driver. Signed-off-by: Abel Vesa Acked-by: Rob Herring Reviewed-by: Dong Aisheng --- include/dt-bindings/reset/imx8mp-reset.h | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/include/dt-bindings/reset/imx8mp-reset.h b/include/dt-bindings/reset/imx8mp-reset.h index ba70248..eb9ed21 100644 --- a/include/dt-bindings/reset/imx8mp-reset.h +++ b/include/dt-bindings/reset/imx8mp-reset.h @@ -80,4 +80,16 @@ #define IMX8MP_MEDIA_BLK_CTL_RESET_NUM 25 +#define IMX8MP_HDMI_BLK_CTL_HDMI_TX_RESET 0 +#define IMX8MP_HDMI_BLK_CTL_HDMI_PHY_RESET 1 +#define IMX8MP_HDMI_BLK_CTL_HDMI_PAI_RESET 2 +#define IMX8MP_HDMI_BLK_CTL_HDMI_PVI_RESET 3 +#define IMX8MP_HDMI_BLK_CTL_HDMI_TRNG_RESET 4 +#define IMX8MP_HDMI_BLK_CTL_IRQ_STEER_RESET 5 +#define IMX8MP_HDMI_BLK_CTL_HDMI_HDCP_RESET 6 +#define IMX8MP_HDMI_BLK_CTL_LCDIF_RESET 7 + +#define IMX8MP_HDMI_BLK_CTL_RESET_NUM 8 + + #endif From patchwork Tue Sep 8 10:24:46 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abel Vesa X-Patchwork-Id: 1359655 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=nxp.com Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4Bm1b54wFjz9sSn for ; Tue, 8 Sep 2020 20:28:49 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729573AbgIHK2q (ORCPT ); Tue, 8 Sep 2020 06:28:46 -0400 Received: from inva020.nxp.com ([92.121.34.13]:45004 "EHLO inva020.nxp.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729534AbgIHK0i (ORCPT ); Tue, 8 Sep 2020 06:26:38 -0400 Received: from inva020.nxp.com (localhost [127.0.0.1]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 8370E1A0351; Tue, 8 Sep 2020 12:26:12 +0200 (CEST) Received: from inva024.eu-rdc02.nxp.com (inva024.eu-rdc02.nxp.com [134.27.226.22]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 745CB1A1074; Tue, 8 Sep 2020 12:26:12 +0200 (CEST) Received: from fsr-ub1664-175.ea.freescale.net (fsr-ub1664-175.ea.freescale.net [10.171.82.40]) by inva024.eu-rdc02.nxp.com (Postfix) with ESMTP id C0E0C20327; Tue, 8 Sep 2020 12:26:11 +0200 (CEST) From: Abel Vesa To: Mike Turquette , Stephen Boyd , Rob Herring , Shawn Guo , Sascha Hauer , Fabio Estevam , Philipp Zabel , Anson Huang , Jacky Bai , Peng Fan , Dong Aisheng , Fugang Duan , devicetree@vger.kernel.org Cc: NXP Linux Team , linux-arm-kernel@lists.infradead.org, Linux Kernel Mailing List , linux-clk@vger.kernel.org, Abel Vesa Subject: [PATCH v3 09/14] Documentation: bindings: clk: Add bindings for i.MX BLK_CTL Date: Tue, 8 Sep 2020 13:24:46 +0300 Message-Id: <1599560691-3763-10-git-send-email-abel.vesa@nxp.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1599560691-3763-1-git-send-email-abel.vesa@nxp.com> References: <1599560691-3763-1-git-send-email-abel.vesa@nxp.com> X-Virus-Scanned: ClamAV using ClamSMTP Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Document the i.MX BLK_CTL with its devicetree properties. Signed-off-by: Abel Vesa Reviewed-by: Dong Aisheng Reviewed-by: Rob Herring --- .../devicetree/bindings/clock/fsl,imx-blk-ctl.yaml | 60 ++++++++++++++++++++++ 1 file changed, 60 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/fsl,imx-blk-ctl.yaml diff --git a/Documentation/devicetree/bindings/clock/fsl,imx-blk-ctl.yaml b/Documentation/devicetree/bindings/clock/fsl,imx-blk-ctl.yaml new file mode 100644 index 00000000..5e9eb40 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/fsl,imx-blk-ctl.yaml @@ -0,0 +1,60 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/fsl,imx-blk-ctl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP i.MX BLK_CTL + +maintainers: + - Abel Vesa + +description: + i.MX BLK_CTL is a conglomerate of different GPRs that are + dedicated to a specific subsystem. Because it usually contains + clocks amongst other things, it needs access to the i.MX clocks + API. All the other functionalities it provides can work just fine + from the clock subsystem tree. + +properties: + compatible: + items: + - enum: + - fsl,imx8mp-audio-blk-ctl + - fsl,imx8mp-hdmi-blk-ctl + - fsl,imx8mp-media-blk-ctl + - const: syscon + + reg: + maxItems: 1 + + power-domains: + maxItems: 1 + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + +required: + - compatible + - reg + - power-domains + - '#clock-cells' + - '#reset-cells' + +additionalProperties: false + +examples: + - | + #include + + audio_blk_ctl: clock-controller@30e20000 { + compatible = "fsl,imx8mp-audio-blk-ctl", "syscon"; + reg = <0x30e20000 0x10000>; + power-domains = <&audiomix_pd>; + + #clock-cells = <1>; + #reset-cells = <1>; + };