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Thu, 27 Aug 2020 02:43:28 +0000 Received: from b03ledav005.gho.boulder.ibm.com (b03ledav005.gho.boulder.ibm.com [9.17.130.236]) by b03cxnp07028.gho.boulder.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 07R2hQxp39977306 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Thu, 27 Aug 2020 02:43:26 GMT Received: from b03ledav005.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 5F5F4BE058; Thu, 27 Aug 2020 02:43:26 +0000 (GMT) Received: from b03ledav005.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 87252BE04F; Thu, 27 Aug 2020 02:43:25 +0000 (GMT) Received: from ibm-toto.the-meissners.org (unknown [9.160.12.160]) by b03ledav005.gho.boulder.ibm.com (Postfix) with ESMTPS; Thu, 27 Aug 2020 02:43:25 +0000 (GMT) Date: Wed, 26 Aug 2020 22:43:23 -0400 To: Michael Meissner , gcc-patches@gcc.gnu.org, Segher Boessenkool , David Edelsohn , Bill Schmidt , Peter Bergner Subject: [PATCH 1/4] PowerPC: Change cmove function return to bool Message-ID: <20200827024323.GA21803@ibm-toto.the-meissners.org> Mail-Followup-To: Michael Meissner , gcc-patches@gcc.gnu.org, Segher Boessenkool , David Edelsohn , Bill Schmidt , Peter Bergner References: <20200827024142.GA15560@ibm-toto.the-meissners.org> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20200827024142.GA15560@ibm-toto.the-meissners.org> User-Agent: Mutt/1.5.21 (2010-09-15) X-TM-AS-GCONF: 00 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.235, 18.0.687 definitions=2020-08-26_14:2020-08-26, 2020-08-26 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 suspectscore=0 adultscore=0 impostorscore=0 priorityscore=1501 mlxscore=0 spamscore=0 bulkscore=0 mlxlogscore=999 clxscore=1015 malwarescore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2006250000 definitions=main-2008270016 X-Spam-Status: No, score=-9.5 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_DNSWL_LOW, RCVD_IN_MSPIKE_H2, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Michael Meissner via Gcc-patches From: Michael Meissner Reply-To: Michael Meissner Errors-To: gcc-patches-bounces@gcc.gnu.org Sender: "Gcc-patches" PowerPC: Change cmove function return to bool. In doing the other work for adding ISA 3.1 128-bit minimum, maximum, and conditional move support, I noticed the two functions that process conditional moves return 'int' instead of 'bool'. This patch changes these functions to return 'bool'. I have built compilers on a little endian power9 Linux system with all 4 patches applied. I did bootstrap builds and ran the testsuite, with no regressions. Previous versions of the patch was also tested on a little endian power8 Linux system. I would like to check this patch into the master branch for GCC 11. At this time, I do not anticipate needing to backport these changes to GCC 10.3. gcc/ 2020-08-26 Michael Meissner * config/rs6000/rs6000-protos.h (rs6000_emit_cmove): Change return type to bool. (rs6000_emit_int_cmove): Change return type to bool. * config/rs6000/rs6000.c (rs6000_emit_cmove): Change return type to bool. (rs6000_emit_int_cmove): Change return type to bool. --- gcc/config/rs6000/rs6000-protos.h | 4 ++-- gcc/config/rs6000/rs6000.c | 32 +++++++++++++++---------------- 2 files changed, 18 insertions(+), 18 deletions(-) diff --git a/gcc/config/rs6000/rs6000-protos.h b/gcc/config/rs6000/rs6000-protos.h index 28e859f4381..02e4d71922f 100644 --- a/gcc/config/rs6000/rs6000-protos.h +++ b/gcc/config/rs6000/rs6000-protos.h @@ -119,8 +119,8 @@ extern char * output_cbranch (rtx, const char *, int, rtx_insn *); extern const char * output_probe_stack_range (rtx, rtx, rtx); extern void rs6000_emit_dot_insn (rtx dst, rtx src, int dot, rtx ccreg); extern bool rs6000_emit_set_const (rtx, rtx); -extern int rs6000_emit_cmove (rtx, rtx, rtx, rtx); -extern int rs6000_emit_int_cmove (rtx, rtx, rtx, rtx); +extern bool rs6000_emit_cmove (rtx, rtx, rtx, rtx); +extern bool rs6000_emit_int_cmove (rtx, rtx, rtx, rtx); extern int rs6000_emit_vector_cond_expr (rtx, rtx, rtx, rtx, rtx, rtx); extern void rs6000_emit_minmax (rtx, enum rtx_code, rtx, rtx); extern void rs6000_expand_atomic_compare_and_swap (rtx op[]); diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index 1c1caa90ede..bac50c2bcf6 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -15159,7 +15159,7 @@ rs6000_emit_p9_fp_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond) operands of the last comparison is nonzero/true, FALSE_COND if it is zero/false. Return 0 if the hardware has no such operation. */ -int +bool rs6000_emit_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond) { enum rtx_code code = GET_CODE (op); @@ -15175,11 +15175,11 @@ rs6000_emit_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond) /* In the isel case however, we can use a compare immediate, so op1 may be a small constant. */ && (!TARGET_ISEL || !short_cint_operand (op1, VOIDmode))) - return 0; + return false; if (GET_MODE (true_cond) != result_mode) - return 0; + return false; if (GET_MODE (false_cond) != result_mode) - return 0; + return false; /* See if we can use the ISA 3.0 (power9) min/max/compare functions. */ if (TARGET_P9_MINMAX @@ -15187,16 +15187,16 @@ rs6000_emit_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond) && (result_mode == SFmode || result_mode == DFmode)) { if (rs6000_emit_p9_fp_minmax (dest, op, true_cond, false_cond)) - return 1; + return true; if (rs6000_emit_p9_fp_cmove (dest, op, true_cond, false_cond)) - return 1; + return true; } /* Don't allow using floating point comparisons for integer results for now. */ if (FLOAT_MODE_P (compare_mode) && !FLOAT_MODE_P (result_mode)) - return 0; + return false; /* First, work out if the hardware can do this at all, or if it's too slow.... */ @@ -15204,7 +15204,7 @@ rs6000_emit_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond) { if (TARGET_ISEL) return rs6000_emit_int_cmove (dest, op, true_cond, false_cond); - return 0; + return false; } is_against_zero = op1 == CONST0_RTX (compare_mode); @@ -15216,7 +15216,7 @@ rs6000_emit_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond) generated. */ if (SCALAR_FLOAT_MODE_P (compare_mode) && flag_trapping_math && ! is_against_zero) - return 0; + return false; /* Eliminate half of the comparisons by switching operands, this makes the remaining code simpler. */ @@ -15232,7 +15232,7 @@ rs6000_emit_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond) /* UNEQ and LTGT take four instructions for a comparison with zero, it'll probably be faster to use a branch here too. */ if (code == UNEQ && HONOR_NANS (compare_mode)) - return 0; + return false; /* We're going to try to implement comparisons by performing a subtract, then comparing against zero. Unfortunately, @@ -15247,14 +15247,14 @@ rs6000_emit_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond) && ((! rtx_equal_p (op0, false_cond) && ! rtx_equal_p (op1, false_cond)) || (! rtx_equal_p (op0, true_cond) && ! rtx_equal_p (op1, true_cond)))) - return 0; + return false; /* At this point we know we can use fsel. */ /* Don't allow compare_mode other than SFmode or DFmode, for others there is no fsel instruction. */ if (compare_mode != SFmode && compare_mode != DFmode) - return 0; + return false; /* Reduce the comparison to a comparison against zero. */ if (! is_against_zero) @@ -15353,12 +15353,12 @@ rs6000_emit_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond) gen_rtx_GE (VOIDmode, op0, op1), true_cond, false_cond))); - return 1; + return true; } /* Same as above, but for ints (isel). */ -int +bool rs6000_emit_int_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond) { rtx condition_rtx, cr; @@ -15368,7 +15368,7 @@ rs6000_emit_int_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond) bool signedp; if (mode != SImode && (!TARGET_POWERPC64 || mode != DImode)) - return 0; + return false; /* We still have to do the compare, because isel doesn't do a compare, it just looks at the CRx bits set by a previous compare @@ -15403,7 +15403,7 @@ rs6000_emit_int_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond) emit_insn (isel_func (dest, condition_rtx, true_cond, false_cond, cr)); - return 1; + return true; } void From patchwork Thu Aug 27 02:44:22 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Meissner X-Patchwork-Id: 1352208 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=8.43.85.97; helo=sourceware.org; envelope-from=gcc-patches-bounces@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=gcc.gnu.org Authentication-Results: ozlabs.org; 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Thu, 27 Aug 2020 02:44:24 +0000 (GMT) Received: from b01ledav001.gho.pok.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 4500428059; Thu, 27 Aug 2020 02:44:24 +0000 (GMT) Received: from ibm-toto.the-meissners.org (unknown [9.160.12.160]) by b01ledav001.gho.pok.ibm.com (Postfix) with ESMTPS; Thu, 27 Aug 2020 02:44:24 +0000 (GMT) Date: Wed, 26 Aug 2020 22:44:22 -0400 To: Michael Meissner , gcc-patches@gcc.gnu.org, Segher Boessenkool , David Edelsohn , Bill Schmidt , Peter Bergner Subject: [PATCH 2/4] PowerPC: Rename functions for min, max, cmove Message-ID: <20200827024422.GB21803@ibm-toto.the-meissners.org> Mail-Followup-To: Michael Meissner , gcc-patches@gcc.gnu.org, Segher Boessenkool , David Edelsohn , Bill Schmidt , Peter Bergner References: <20200827024142.GA15560@ibm-toto.the-meissners.org> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20200827024142.GA15560@ibm-toto.the-meissners.org> User-Agent: Mutt/1.5.21 (2010-09-15) X-TM-AS-GCONF: 00 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.235, 18.0.687 definitions=2020-08-26_14:2020-08-26, 2020-08-26 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 priorityscore=1501 spamscore=0 adultscore=0 malwarescore=0 mlxscore=0 bulkscore=0 lowpriorityscore=0 mlxlogscore=999 impostorscore=0 phishscore=0 clxscore=1015 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2006250000 definitions=main-2008270016 X-Spam-Status: No, score=-9.8 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_DNSWL_LOW, RCVD_IN_MSPIKE_H2, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Michael Meissner via Gcc-patches From: Michael Meissner Reply-To: Michael Meissner Errors-To: gcc-patches-bounces@gcc.gnu.org Sender: "Gcc-patches" PowerPC: Rename functions for min, max, cmove. This patch renames the functions that generate the ISA 3.0 C minimum, C maximum, and conditional move instructions to use a better name than just using a _p9 suffix. Because the functions can fail, the names use "maybe_emit" instead of "generate_" in the name. I have built compilers on a little endian power9 Linux system with all 4 patches applied. I did bootstrap builds and ran the testsuite, with no regressions. Previous versions of the patch was also tested on a little endian power8 Linux system. I would like to check this patch into the master branch for GCC 11. At this time, I do not anticipate needing to backport these changes to GCC 10.3. gcc/ 2020-08-26 Michael Meissner * config/rs6000/rs6000.c (rs6000_emit_p9_fp_minmax): Rename to maybe_emit_fp_c_minmax. (maybe_emit_fp_c_minmax): Rename rs6000_emit_p9_fp_minmax. Return bool instead of int. (rs6000_emit_p9_fp_cmove): Rename to maybe_emit_fp_cmove. (maybe_emit_fp_cmove): Rename rs6000_emit_p9_fp_cmove. Return bool instead of int. (have_compare_and_set_mask): New helper function. (rs6000_emit_cmove): Rework support of ISA 3.0 functions to generate "C" minimum, "C" maximum, and conditional move instructions for scalar floating point. --- gcc/config/rs6000/rs6000.c | 77 ++++++++++++++++++++++++++------------ 1 file changed, 53 insertions(+), 24 deletions(-) diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index bac50c2bcf6..6324f930628 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -15056,13 +15056,17 @@ rs6000_emit_vector_cond_expr (rtx dest, rtx op_true, rtx op_false, return 1; } -/* ISA 3.0 (power9) minmax subcase to emit a XSMAXCDP or XSMINCDP instruction - for SF/DF scalars. Move TRUE_COND to DEST if OP of the operands of the last - comparison is nonzero/true, FALSE_COND if it is zero/false. Return 0 if the - hardware has no such operation. */ +/* Possibly emit the C variant of the minimum or maximum instruction for + floating point scalars (xsmincdp, xsmaxcdp, etc.). -static int -rs6000_emit_p9_fp_minmax (rtx dest, rtx op, rtx true_cond, rtx false_cond) + Move TRUE_COND to DEST if OP of the operands of the last comparison is + nonzero/true, FALSE_COND if it is zero/false. + + Return false if we can't generate the appropriate minimum or maximum, and + true if we can did the minimum or maximum. */ + +static bool +maybe_emit_fp_c_minmax (rtx dest, rtx op, rtx true_cond, rtx false_cond) { enum rtx_code code = GET_CODE (op); rtx op0 = XEXP (op, 0); @@ -15072,14 +15076,14 @@ rs6000_emit_p9_fp_minmax (rtx dest, rtx op, rtx true_cond, rtx false_cond) bool max_p = false; if (result_mode != compare_mode) - return 0; + return false; if (code == GE || code == GT) max_p = true; else if (code == LE || code == LT) max_p = false; else - return 0; + return false; if (rtx_equal_p (op0, true_cond) && rtx_equal_p (op1, false_cond)) ; @@ -15092,19 +15096,23 @@ rs6000_emit_p9_fp_minmax (rtx dest, rtx op, rtx true_cond, rtx false_cond) max_p = !max_p; else - return 0; + return false; rs6000_emit_minmax (dest, max_p ? SMAX : SMIN, op0, op1); - return 1; + return true; } -/* ISA 3.0 (power9) conditional move subcase to emit XSCMP{EQ,GE,GT,NE}DP and - XXSEL instructions for SF/DF scalars. Move TRUE_COND to DEST if OP of the - operands of the last comparison is nonzero/true, FALSE_COND if it is - zero/false. Return 0 if the hardware has no such operation. */ +/* Possibly emit a floating point conditional move by generating a compare that + sets a mask instruction and a XXSEL select instruction. -static int -rs6000_emit_p9_fp_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond) + Move TRUE_COND to DEST if OP of the operands of the last comparison is + nonzero/true, FALSE_COND if it is zero/false. + + Return false if the operation cannot be generated, and true if we could + generate the instruction. */ + +static bool +maybe_emit_fp_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond) { enum rtx_code code = GET_CODE (op); rtx op0 = XEXP (op, 0); @@ -15132,7 +15140,7 @@ rs6000_emit_p9_fp_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond) break; default: - return 0; + return false; } /* Generate: [(parallel [(set (dest) @@ -15152,7 +15160,28 @@ rs6000_emit_p9_fp_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond) emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, cmove_rtx, clobber_rtx))); - return 1; + return true; +} + +/* Helper function to return true if the target has instructions to do a + compare and set mask instruction that can be used with XXSEL to implement a + conditional move. It is also assumed that such a target also supports the + "C" minimum and maximum instructions. */ + +static bool +have_compare_and_set_mask (machine_mode mode) +{ + switch (mode) + { + case SFmode: + case DFmode: + return TARGET_P9_MINMAX; + + default: + break; + } + + return false; } /* Emit a conditional move: move TRUE_COND to DEST if OP of the @@ -15181,15 +15210,15 @@ rs6000_emit_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond) if (GET_MODE (false_cond) != result_mode) return false; - /* See if we can use the ISA 3.0 (power9) min/max/compare functions. */ - if (TARGET_P9_MINMAX - && (compare_mode == SFmode || compare_mode == DFmode) - && (result_mode == SFmode || result_mode == DFmode)) + /* See if we can use the "C" minimum, "C" maximum, and compare and set mask + instructions. */ + if (have_compare_and_set_mask (compare_mode) + && have_compare_and_set_mask (result_mode)) { - if (rs6000_emit_p9_fp_minmax (dest, op, true_cond, false_cond)) + if (maybe_emit_fp_c_minmax (dest, op, true_cond, false_cond)) return true; - if (rs6000_emit_p9_fp_cmove (dest, op, true_cond, false_cond)) + if (maybe_emit_fp_cmove (dest, op, true_cond, false_cond)) return true; } From patchwork Thu Aug 27 02:45:26 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Meissner X-Patchwork-Id: 1352209 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=8.43.85.97; helo=sourceware.org; envelope-from=gcc-patches-bounces@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=gcc.gnu.org Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.a=rsa-sha256 header.s=default header.b=HD5ag+Oh; dkim-atps=neutral Received: from sourceware.org (server2.sourceware.org [8.43.85.97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4BcRt80cMgz9sSP for ; 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Thu, 27 Aug 2020 02:45:28 +0000 Received: from b01ledav006.gho.pok.ibm.com (b01ledav006.gho.pok.ibm.com [9.57.199.111]) by b01cxnp23032.gho.pok.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 07R2jSPp34341258 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Thu, 27 Aug 2020 02:45:28 GMT Received: from b01ledav006.gho.pok.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 006A2AC060; Thu, 27 Aug 2020 02:45:28 +0000 (GMT) Received: from b01ledav006.gho.pok.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 89889AC059; Thu, 27 Aug 2020 02:45:27 +0000 (GMT) Received: from ibm-toto.the-meissners.org (unknown [9.160.12.160]) by b01ledav006.gho.pok.ibm.com (Postfix) with ESMTPS; Thu, 27 Aug 2020 02:45:27 +0000 (GMT) Date: Wed, 26 Aug 2020 22:45:26 -0400 To: Michael Meissner , gcc-patches@gcc.gnu.org, Segher Boessenkool , David Edelsohn , Bill Schmidt , Peter Bergner Subject: [PATCH 3/4] PowerPC: Add power10 xsmaxcqp/xsmincqp support Message-ID: <20200827024525.GC21803@ibm-toto.the-meissners.org> Mail-Followup-To: Michael Meissner , gcc-patches@gcc.gnu.org, Segher Boessenkool , David Edelsohn , Bill Schmidt , Peter Bergner References: <20200827024142.GA15560@ibm-toto.the-meissners.org> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20200827024142.GA15560@ibm-toto.the-meissners.org> User-Agent: Mutt/1.5.21 (2010-09-15) X-TM-AS-GCONF: 00 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.235, 18.0.687 definitions=2020-08-26_14:2020-08-26, 2020-08-26 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 suspectscore=0 adultscore=0 impostorscore=0 priorityscore=1501 mlxscore=0 spamscore=0 bulkscore=0 mlxlogscore=999 clxscore=1015 malwarescore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2006250000 definitions=main-2008270016 X-Spam-Status: No, score=-10.0 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_DNSWL_LOW, RCVD_IN_MSPIKE_H2, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Michael Meissner via Gcc-patches From: Michael Meissner Reply-To: Michael Meissner Errors-To: gcc-patches-bounces@gcc.gnu.org Sender: "Gcc-patches" PowerPC: Add power10 xsmaxcqp/xsmincqp support. This patch adds support for the ISA 3.1 (power10) IEEE 128-bit "C" minimum and maximum functions. Because of the NaN differences, the built-in functions will only generate these instructions if -ffast-math is used until the conditional move support is added in the next patch. I have built compilers on a little endian power9 Linux system with all 4 patches applied. I did bootstrap builds and ran the testsuite, with no regressions. Previous versions of the patch was also tested on a little endian power8 Linux system. I would like to check this patch into the master branch for GCC 11. At this time, I do not anticipate needing to backport these changes to GCC 10.3. gcc/ 2020-08-26 Michael Meissner * config/rs6000/rs6000.h (FLOAT128_IEEE_MINMAX_P): New helper macro. * config/rs6000/rs6000.md (FSCALAR): New mode iterator for floating point scalars. (Fm): New mode attribute for floating point scalars. (s): Add support for the ISA 3.1 IEEE 128-bit minimum and maximum instructions. (s3_vsx): Add support for the ISA 3.1 IEEE 128-bit minimum and maximum instructions. gcc/testsuite/ 2020-08-26 Michael Meissner * gcc.target/powerpc/float128-minmax-2.c: New test. --- gcc/config/rs6000/rs6000.c | 3 +- gcc/config/rs6000/rs6000.h | 4 +++ gcc/config/rs6000/rs6000.md | 28 +++++++++++++++---- .../gcc.target/powerpc/float128-minmax-2.c | 15 ++++++++++ 4 files changed, 43 insertions(+), 7 deletions(-) create mode 100644 gcc/testsuite/gcc.target/powerpc/float128-minmax-2.c diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index 6324f930628..05eb141a2cd 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -15445,7 +15445,8 @@ rs6000_emit_minmax (rtx dest, enum rtx_code code, rtx op0, rtx op1) /* VSX/altivec have direct min/max insns. */ if ((code == SMAX || code == SMIN) && (VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode) - || (mode == SFmode && VECTOR_UNIT_VSX_P (DFmode)))) + || (mode == SFmode && VECTOR_UNIT_VSX_P (DFmode)) + || FLOAT128_IEEE_MINMAX_P (mode))) { emit_insn (gen_rtx_SET (dest, gen_rtx_fmt_ee (code, mode, op0, op1))); return; diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h index bbd8060e143..b504aaa0199 100644 --- a/gcc/config/rs6000/rs6000.h +++ b/gcc/config/rs6000/rs6000.h @@ -345,6 +345,10 @@ extern const char *host_detect_local_cpu (int argc, const char **argv); || ((MODE) == TDmode) \ || (!TARGET_FLOAT128_TYPE && FLOAT128_IEEE_P (MODE))) +/* Macro whether the float128 min/max instructions are enabled. */ +#define FLOAT128_IEEE_MINMAX_P(MODE) \ + (TARGET_POWER10 && TARGET_FLOAT128_HW && FLOAT128_IEEE_P (MODE)) + /* Return true for floating point that does not use a vector register. */ #define SCALAR_FLOAT_MODE_NOT_VECTOR_P(MODE) \ (SCALAR_FLOAT_MODE_P (MODE) && !FLOAT128_VECTOR_P (MODE)) diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index 43b620ae1c0..006e60f09bc 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -789,6 +789,18 @@ (define_code_attr minmax [(smin "min") (define_code_attr SMINMAX [(smin "SMIN") (smax "SMAX")]) +;; Mode iterator for scalar binary floating point operations +(define_mode_iterator FSCALAR [SF + DF + (KF "FLOAT128_IEEE_MINMAX_P (KFmode)") + (TF "FLOAT128_IEEE_MINMAX_P (TFmode)")]) + +;; Constraints to use for scalar FP operations +(define_mode_attr Fm [(SF "wa") + (DF "wa") + (TF "v") + (KF "v")]) + ;; Iterator to optimize the following cases: ;; D-form load to FPR register & move to Altivec register ;; Move Altivec register to FPR register and store @@ -5142,9 +5154,9 @@ (define_insn "copysign3_fcpsgn" ;; to allow either DF/SF to use only traditional registers. (define_expand "s3" - [(set (match_operand:SFDF 0 "gpc_reg_operand") - (fp_minmax:SFDF (match_operand:SFDF 1 "gpc_reg_operand") - (match_operand:SFDF 2 "gpc_reg_operand")))] + [(set (match_operand:FSCALAR 0 "gpc_reg_operand") + (fp_minmax:FSCALAR (match_operand:FSCALAR 1 "gpc_reg_operand") + (match_operand:FSCALAR 2 "gpc_reg_operand")))] "TARGET_MINMAX" { rs6000_emit_minmax (operands[0], , operands[1], operands[2]); @@ -5152,11 +5164,15 @@ (define_expand "s3" }) (define_insn "*s3_vsx" - [(set (match_operand:SFDF 0 "vsx_register_operand" "=") - (fp_minmax:SFDF (match_operand:SFDF 1 "vsx_register_operand" "") - (match_operand:SFDF 2 "vsx_register_operand" "")))] + [(set (match_operand:FSCALAR 0 "vsx_register_operand" "=") + (fp_minmax:FSCALAR + (match_operand:FSCALAR 1 "vsx_register_operand" "") + (match_operand:FSCALAR 2 "vsx_register_operand" "")))] "TARGET_VSX && TARGET_HARD_FLOAT" { + if (FLOAT128_IEEE_P (mode)) + return "xscqp %0,%1,%2"; + return (TARGET_P9_MINMAX ? "xscdp %x0,%x1,%x2" : "xsdp %x0,%x1,%x2"); diff --git a/gcc/testsuite/gcc.target/powerpc/float128-minmax-2.c b/gcc/testsuite/gcc.target/powerpc/float128-minmax-2.c new file mode 100644 index 00000000000..c71ba08c9f8 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/float128-minmax-2.c @@ -0,0 +1,15 @@ +/* { dg-require-effective-target ppc_float128_hw } */ +/* { dg-require-effective-target power10_ok } */ +/* { dg-options "-mdejagnu-cpu=power10 -O2 -ffast-math" } */ + +#ifndef TYPE +#define TYPE _Float128 +#endif + +/* Test that the fminf128/fmaxf128 functions generate if/then/else and not a + call. */ +TYPE f128_min (TYPE a, TYPE b) { return __builtin_fminf128 (a, b); } +TYPE f128_max (TYPE a, TYPE b) { return __builtin_fmaxf128 (a, b); } + +/* { dg-final { scan-assembler {\mxsmaxcqp\M} } } */ +/* { dg-final { scan-assembler {\mxsmincqp\M} } } */ From patchwork Thu Aug 27 02:46:37 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Meissner X-Patchwork-Id: 1352210 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; 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Thu, 27 Aug 2020 02:46:39 GMT Received: from b01ledav002.gho.pok.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id B6B5B124052; Thu, 27 Aug 2020 02:46:39 +0000 (GMT) Received: from b01ledav002.gho.pok.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 351EB124053; Thu, 27 Aug 2020 02:46:39 +0000 (GMT) Received: from ibm-toto.the-meissners.org (unknown [9.160.12.160]) by b01ledav002.gho.pok.ibm.com (Postfix) with ESMTPS; Thu, 27 Aug 2020 02:46:39 +0000 (GMT) Date: Wed, 26 Aug 2020 22:46:37 -0400 To: Michael Meissner , gcc-patches@gcc.gnu.org, Segher Boessenkool , David Edelsohn , Bill Schmidt , Peter Bergner Subject: [PATCH 4/4] PowerPC: Add power10 xscmp{eq,gt,ge}qp support Message-ID: <20200827024637.GD21803@ibm-toto.the-meissners.org> Mail-Followup-To: Michael Meissner , gcc-patches@gcc.gnu.org, Segher Boessenkool , David Edelsohn , Bill Schmidt , Peter Bergner References: <20200827024142.GA15560@ibm-toto.the-meissners.org> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20200827024142.GA15560@ibm-toto.the-meissners.org> User-Agent: Mutt/1.5.21 (2010-09-15) X-TM-AS-GCONF: 00 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.235, 18.0.687 definitions=2020-08-26_14:2020-08-26, 2020-08-26 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 priorityscore=1501 spamscore=0 adultscore=0 malwarescore=0 mlxscore=0 bulkscore=0 lowpriorityscore=0 mlxlogscore=999 impostorscore=0 phishscore=0 clxscore=1015 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2006250000 definitions=main-2008270016 X-Spam-Status: No, score=-10.2 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_DNSWL_LOW, RCVD_IN_MSPIKE_H2, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Michael Meissner via Gcc-patches From: Michael Meissner Reply-To: Michael Meissner Errors-To: gcc-patches-bounces@gcc.gnu.org Sender: "Gcc-patches" PowerPC: Add power10 xscmp{eq,gt,ge}qp support. This patch adds the conditional move support. In adding the conditional move support, the optimizers will be able to convert things like: a = (b > c) ? b : c; into the instructions. This patch merges together the scalar SF/DF conditional move with the scalar KF/TF conditional move. It extends the optimization that was previously used for SFmode and DFmode to allow the comparison to be a different scalar floating point mode than the move. I.e. __float128 a, b, c; float x, y; /* ... */ a = (x == y) ? b : c; I did have to add an XXPERMDI if the comparison mode was SFmode or DFmode, and the move mode is KFmode or TFmode (the XSCMP{EQ,GT,GE}DP instructions explicitly set the bottom 64 bits of the vector register to 0). I have built compilers on a little endian power9 Linux system with all 4 patches applied. I did bootstrap builds and ran the testsuite, with no regressions. Previous versions of the patch was also tested on a little endian power8 Linux system. I would like to check this patch into the master branch for GCC 11. At this time, I do not anticipate needing to backport these changes to GCC 10.3. gcc/ 2020-08-26 Michael Meissner * config/rs6000/predicates.md (fpmask_normal_or_invert_operator): New predicate. * config/rs6000/rs6000.c (have_compare_and_set_mask): Add IEEE 128-bit floating point types. * config/rs6000/rs6000.md (FSCALAR2): New iterator for floating point conditional moves. (movcc_p9): Replace with mov. (movcc_invert_p9): Replace with mov. (mov): Combine both movcc_p9 and movcc_invert_p9 patterns. Add ISA 3.1 support for IEEE 128-bit conditional moves. Always use an earlyclobber register for the mask. Use XXPERMDI to extend the mask if we have a 64-bit comparison and 128-bit move. register for the mask. (fpmask, xxsel): Add ISA 3.1 support for IEEE 128-bit conditional moves. Enable the generator functionality so mov can call it. Update constraints for 128-bit operations. gcc/testsuite/ 2020-08-26 Michael Meissner * gcc.target/powerpc/float128-cmove.c: New test. * gcc.target/powerpc/float128-minmax-3.c: New test. --- gcc/config/rs6000/predicates.md | 5 + gcc/config/rs6000/rs6000.c | 4 + gcc/config/rs6000/rs6000.md | 154 ++++++++++-------- .../gcc.target/powerpc/float128-cmove.c | 93 +++++++++++ .../gcc.target/powerpc/float128-minmax-3.c | 15 ++ 5 files changed, 200 insertions(+), 71 deletions(-) create mode 100644 gcc/testsuite/gcc.target/powerpc/float128-cmove.c create mode 100644 gcc/testsuite/gcc.target/powerpc/float128-minmax-3.c diff --git a/gcc/config/rs6000/predicates.md b/gcc/config/rs6000/predicates.md index 2709e46f7e5..60b45601e9b 100644 --- a/gcc/config/rs6000/predicates.md +++ b/gcc/config/rs6000/predicates.md @@ -1225,6 +1225,11 @@ (define_predicate "fpmask_comparison_operator" (define_predicate "invert_fpmask_comparison_operator" (match_code "ne,unlt,unle")) +;; Return 1 if OP is either a fpmask_comparison_operator or +;; invert_fpmask_comparsion_operator. +(define_predicate "fpmask_normal_or_invert_operator" + (match_code "eq,gt,ge,ne,unlt,unle")) + ;; Return 1 if OP is a comparison operation suitable for integer vector/scalar ;; comparisons that generate a -1/0 mask. (define_predicate "vecint_comparison_operator" diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index 05eb141a2cd..403897926c5 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -15177,6 +15177,10 @@ have_compare_and_set_mask (machine_mode mode) case DFmode: return TARGET_P9_MINMAX; + case KFmode: + case TFmode: + return FLOAT128_IEEE_MINMAX_P (mode); + default: break; } diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index 006e60f09bc..147c635994c 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -795,6 +795,15 @@ (define_mode_iterator FSCALAR [SF (KF "FLOAT128_IEEE_MINMAX_P (KFmode)") (TF "FLOAT128_IEEE_MINMAX_P (TFmode)")]) +;; Secondary iterator for scalar binary floating point operations. This is +;; used for the conditional moves when we have a compare and set mask +;; instruction. Using this instruction allows us to do a conditional move +;; where the comparison type might be different from the values being moved. +(define_mode_iterator FSCALAR2 [SF + DF + (KF "FLOAT128_IEEE_MINMAX_P (KFmode)") + (TF "FLOAT128_IEEE_MINMAX_P (TFmode)")]) + ;; Constraints to use for scalar FP operations (define_mode_attr Fm [(SF "wa") (DF "wa") @@ -5290,10 +5299,10 @@ (define_insn "*setnbcr_signed_" ;; Floating point conditional move (define_expand "movcc" - [(set (match_operand:SFDF 0 "gpc_reg_operand") - (if_then_else:SFDF (match_operand 1 "comparison_operator") - (match_operand:SFDF 2 "gpc_reg_operand") - (match_operand:SFDF 3 "gpc_reg_operand")))] + [(set (match_operand:FSCALAR 0 "gpc_reg_operand") + (if_then_else:FSCALAR (match_operand 1 "comparison_operator") + (match_operand:FSCALAR 2 "gpc_reg_operand") + (match_operand:FSCALAR 3 "gpc_reg_operand")))] "TARGET_HARD_FLOAT && TARGET_PPC_GFXOPT" { if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3])) @@ -5313,92 +5322,95 @@ (define_insn "*fsel4" "fsel %0,%1,%2,%3" [(set_attr "type" "fp")]) -(define_insn_and_split "*movcc_p9" - [(set (match_operand:SFDF 0 "vsx_register_operand" "=&,") - (if_then_else:SFDF - (match_operator:CCFP 1 "fpmask_comparison_operator" - [(match_operand:SFDF2 2 "vsx_register_operand" ",") - (match_operand:SFDF2 3 "vsx_register_operand" ",")]) - (match_operand:SFDF 4 "vsx_register_operand" ",") - (match_operand:SFDF 5 "vsx_register_operand" ","))) - (clobber (match_scratch:V2DI 6 "=0,&wa"))] +;; Conditional moves using scalar floating point types if we have a compare and +;; set mask instruction (like xscmpeqdp). +;; +;; If we have a 64-bit comparison and a 128-bit mode, such as: +;; +;; double x, y; +;; __float128 a, b, c; +;; a = (x == y) ? b : c; +;; +;; We need to extend the comparison (XSCMPEQDP puts 0's in the bottom 64-bits). +(define_insn_and_split "*movcc" + [(set (match_operand:FSCALAR 0 "vsx_register_operand" "=") + (if_then_else:FSCALAR + (match_operator:CCFP 1 "fpmask_normal_or_invert_operator" + [(match_operand:FSCALAR2 2 "vsx_register_operand" "") + (match_operand:FSCALAR2 3 "vsx_register_operand" "")]) + (match_operand:FSCALAR 4 "vsx_register_operand" "") + (match_operand:FSCALAR 5 "vsx_register_operand" ""))) + (clobber (match_scratch:V2DI 6 "="))] "TARGET_P9_MINMAX" "#" - "" - [(set (match_dup 6) - (if_then_else:V2DI (match_dup 1) - (match_dup 7) - (match_dup 8))) - (set (match_dup 0) - (if_then_else:SFDF (ne (match_dup 6) - (match_dup 8)) - (match_dup 4) - (match_dup 5)))] + "&& 1" + [(pc)] { - if (GET_CODE (operands[6]) == SCRATCH) - operands[6] = gen_reg_rtx (V2DImode); + rtx dest = operands[0]; + rtx cmp = operands[1]; + rtx cmp_op1 = operands[2]; + rtx cmp_op2 = operands[3]; + rtx move_t = operands[4]; + rtx move_f = operands[5]; + rtx mask_reg = operands[6]; + rtx mask_m1 = CONSTM1_RTX (V2DImode); + rtx mask_0 = CONST0_RTX (V2DImode); - operands[7] = CONSTM1_RTX (V2DImode); - operands[8] = CONST0_RTX (V2DImode); -} - [(set_attr "length" "8") - (set_attr "type" "vecperm")]) + if (GET_CODE (mask_reg) == SCRATCH) + mask_reg = gen_reg_rtx (V2DImode); -;; Handle inverting the fpmask comparisons. -(define_insn_and_split "*movcc_invert_p9" - [(set (match_operand:SFDF 0 "vsx_register_operand" "=&,") - (if_then_else:SFDF - (match_operator:CCFP 1 "invert_fpmask_comparison_operator" - [(match_operand:SFDF2 2 "vsx_register_operand" ",") - (match_operand:SFDF2 3 "vsx_register_operand" ",")]) - (match_operand:SFDF 4 "vsx_register_operand" ",") - (match_operand:SFDF 5 "vsx_register_operand" ","))) - (clobber (match_scratch:V2DI 6 "=0,&wa"))] - "TARGET_P9_MINMAX" - "#" - "&& 1" - [(set (match_dup 6) - (if_then_else:V2DI (match_dup 9) - (match_dup 7) - (match_dup 8))) - (set (match_dup 0) - (if_then_else:SFDF (ne (match_dup 6) - (match_dup 8)) - (match_dup 5) - (match_dup 4)))] -{ - rtx op1 = operands[1]; - enum rtx_code cond = reverse_condition_maybe_unordered (GET_CODE (op1)); + /* Reverse the operands and test if the comparison operator is inverted. */ + if (invert_fpmask_comparison_operator (cmp, CCFPmode)) + { + enum rtx_code cond = reverse_condition_maybe_unordered (GET_CODE (cmp)); + cmp = gen_rtx_fmt_ee (cond, CCFPmode, cmp_op1, cmp_op2); + std::swap (move_t, move_f); + } - if (GET_CODE (operands[6]) == SCRATCH) - operands[6] = gen_reg_rtx (V2DImode); + /* Emit the compare and set mask instruction. */ + emit_insn (gen_fpmask (mask_reg, cmp, cmp_op1, cmp_op2, + mask_m1, mask_0)); - operands[7] = CONSTM1_RTX (V2DImode); - operands[8] = CONST0_RTX (V2DImode); + /* If we have a 64-bit comparison, but an 128-bit move, we need to extend the + mask. Because we are using the splat builtin to extend the V2DImode, we + need to use element 1 on little endian systems. */ + if (!FLOAT128_IEEE_P (mode) + && FLOAT128_IEEE_P (mode)) + { + rtx element = WORDS_BIG_ENDIAN ? const0_rtx : const1_rtx; + emit_insn (gen_vsx_xxspltd_v2di (mask_reg, mask_reg, element)); + } - operands[9] = gen_rtx_fmt_ee (cond, CCFPmode, operands[2], operands[3]); + /* Now emit the XXSEL insn. */ + emit_insn (gen_xxsel (dest, mask_reg, mask_0, move_t, move_f)); + DONE; } [(set_attr "length" "8") (set_attr "type" "vecperm")]) -(define_insn "*fpmask" - [(set (match_operand:V2DI 0 "vsx_register_operand" "=wa") +(define_insn "fpmask" + [(set (match_operand:V2DI 0 "vsx_register_operand" "=") (if_then_else:V2DI (match_operator:CCFP 1 "fpmask_comparison_operator" - [(match_operand:SFDF 2 "vsx_register_operand" "") - (match_operand:SFDF 3 "vsx_register_operand" "")]) + [(match_operand:FSCALAR 2 "vsx_register_operand" "") + (match_operand:FSCALAR 3 "vsx_register_operand" "")]) (match_operand:V2DI 4 "all_ones_constant" "") (match_operand:V2DI 5 "zero_constant" "")))] "TARGET_P9_MINMAX" - "xscmp%V1dp %x0,%x2,%x3" +{ + return (FLOAT128_IEEE_P (mode) + ? "xscmp%V1qp %0,%2,%3" + : "xscmp%V1dp %x0,%x2,%x3"); +} [(set_attr "type" "fpcompare")]) -(define_insn "*xxsel" - [(set (match_operand:SFDF 0 "vsx_register_operand" "=") - (if_then_else:SFDF (ne (match_operand:V2DI 1 "vsx_register_operand" "wa") - (match_operand:V2DI 2 "zero_constant" "")) - (match_operand:SFDF 3 "vsx_register_operand" "") - (match_operand:SFDF 4 "vsx_register_operand" "")))] +(define_insn "xxsel" + [(set (match_operand:FSCALAR 0 "vsx_register_operand" "=") + (if_then_else:FSCALAR + (ne (match_operand:V2DI 1 "vsx_register_operand" "") + (match_operand:V2DI 2 "zero_constant" "")) + (match_operand:FSCALAR 3 "vsx_register_operand" "") + (match_operand:FSCALAR 4 "vsx_register_operand" "")))] "TARGET_P9_MINMAX" "xxsel %x0,%x4,%x3,%x1" [(set_attr "type" "vecmove")]) diff --git a/gcc/testsuite/gcc.target/powerpc/float128-cmove.c b/gcc/testsuite/gcc.target/powerpc/float128-cmove.c new file mode 100644 index 00000000000..639d5a77087 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/float128-cmove.c @@ -0,0 +1,93 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target ppc_float128_hw } */ +/* { dg-require-effective-target power10_ok } */ +/* { dg-options "-mdejagnu-cpu=power10 -O2" } */ +/* { dg-final { scan-assembler {\mxscmpeq[dq]p\M} } } */ +/* { dg-final { scan-assembler {\mxxpermdi\M} } } */ +/* { dg-final { scan-assembler {\mxxsel\M} } } */ +/* { dg-final { scan-assembler-not {\mxscmpu[dq]p\M} } } */ +/* { dg-final { scan-assembler-not {\mfcmp[uo]\M} } } */ +/* { dg-final { scan-assembler-not {\mfsel\M} } } */ + +/* This series of tests tests whether you can do a conditional move where the + test is one floating point type, and the result is another floating point + type. + + If the comparison type is SF/DFmode, and the move type is IEEE 128-bit + floating point, we have to duplicate the mask in the lower 64-bits with + XXPERMDI because XSCMPEQDP clears the bottom 64-bits of the mask register. + + Going the other way (IEEE 128-bit comparsion, 64-bit move) is fine as the + mask word will be 128-bits. */ + +float +eq_f_d (float a, float b, double x, double y) +{ + return (x == y) ? a : b; +} + +double +eq_d_f (double a, double b, float x, float y) +{ + return (x == y) ? a : b; +} + +float +eq_f_f128 (float a, float b, __float128 x, __float128 y) +{ + return (x == y) ? a : b; +} + +double +eq_d_f128 (double a, double b, __float128 x, __float128 y) +{ + return (x == y) ? a : b; +} + +__float128 +eq_f128_f (__float128 a, __float128 b, float x, float y) +{ + return (x == y) ? a : b; +} + +__float128 +eq_f128_d (__float128 a, __float128 b, double x, double y) +{ + return (x != y) ? a : b; +} + +float +ne_f_d (float a, float b, double x, double y) +{ + return (x != y) ? a : b; +} + +double +ne_d_f (double a, double b, float x, float y) +{ + return (x != y) ? a : b; +} + +float +ne_f_f128 (float a, float b, __float128 x, __float128 y) +{ + return (x != y) ? a : b; +} + +double +ne_d_f128 (double a, double b, __float128 x, __float128 y) +{ + return (x != y) ? a : b; +} + +__float128 +ne_f128_f (__float128 a, __float128 b, float x, float y) +{ + return (x != y) ? a : b; +} + +__float128 +ne_f128_d (__float128 a, __float128 b, double x, double y) +{ + return (x != y) ? a : b; +} diff --git a/gcc/testsuite/gcc.target/powerpc/float128-minmax-3.c b/gcc/testsuite/gcc.target/powerpc/float128-minmax-3.c new file mode 100644 index 00000000000..6f7627c0f2a --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/float128-minmax-3.c @@ -0,0 +1,15 @@ +/* { dg-require-effective-target ppc_float128_hw } */ +/* { dg-require-effective-target power10_ok } */ +/* { dg-options "-mdejagnu-cpu=power10 -O2" } */ + +#ifndef TYPE +#define TYPE _Float128 +#endif + +/* Test that the fminf128/fmaxf128 functions generate if/then/else and not a + call. */ +TYPE f128_min (TYPE a, TYPE b) { return (a < b) ? a : b; } +TYPE f128_max (TYPE a, TYPE b) { return (b > a) ? b : a; } + +/* { dg-final { scan-assembler {\mxsmaxcqp\M} } } */ +/* { dg-final { scan-assembler {\mxsmincqp\M} } } */