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([2a02:908:965:2ca0:9145:4b2e:56dd:b5f7]) by smtp.gmail.com with ESMTPSA id v8sm22136729wrm.53.2020.08.24.14.57.48 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Mon, 24 Aug 2020 14:57:49 -0700 (PDT) Subject: [PATCH] serial: zynq: disable TX and RX while changing baud rate To: Michal Simek Cc: U-Boot References: <5fc1e33f-3ab8-1864-d5c5-c40c085b6641@xrpbot.org> From: Norbert Braun Message-ID: Date: Mon, 24 Aug 2020 23:57:48 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.9.0 MIME-Version: 1.0 In-Reply-To: Content-Language: en-US X-Mailman-Approved-At: Tue, 25 Aug 2020 04:46:14 +0200 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.3 at phobos.denx.de X-Virus-Status: Clean According to the Zynq-7000 TRM (UG585), the UART transmitter and receiver must be disabled while changing the baud rate. Change _uart_zynq_serial_setbrg accordingly. --- drivers/serial/serial_zynq.c | 24 ++++++++++++++++++++++-- 1 file changed, 22 insertions(+), 2 deletions(-) diff --git a/drivers/serial/serial_zynq.c b/drivers/serial/serial_zynq.c index 0e71cada1b..4f7bab16fa 100644 --- a/drivers/serial/serial_zynq.c +++ b/drivers/serial/serial_zynq.c @@ -23,7 +23,9 @@ #define ZYNQ_UART_SR_TXFULL BIT(4) /* TX FIFO full */ #define ZYNQ_UART_SR_RXEMPTY BIT(1) /* RX FIFO empty */ +#define ZYNQ_UART_CR_TX_DIS BIT(5) /* TX disable */ #define ZYNQ_UART_CR_TX_EN BIT(4) /* TX enabled */ +#define ZYNQ_UART_CR_RX_DIS BIT(3) /* RX disable */ #define ZYNQ_UART_CR_RX_EN BIT(2) /* RX enabled */ #define ZYNQ_UART_CR_TXRST BIT(1) /* TX logic reset */ #define ZYNQ_UART_CR_RXRST BIT(0) /* RX logic reset */ @@ -82,8 +84,26 @@ static void _uart_zynq_serial_setbrg(struct uart_zynq *regs, break; } - writel(bdiv, ®s->baud_rate_divider); - writel(bgen, ®s->baud_rate_gen); + /* Check if baud rate registers actually need to be changed. */ + if(readl(®s->baud_rate_divider) != bdiv || + readl(®s->baud_rate_gen) != bgen) { + /* + * Configure the baud rate. + * + * This follows the procedure from the + * Zynq-7000 SoC Technical Reference Manual, + * UG585 (v1.12.2), + * section 19.3.2, part 2. + */ + + writel(ZYNQ_UART_CR_RX_DIS, ®s->control); + writel(ZYNQ_UART_CR_TX_DIS, ®s->control); + writel(bgen, ®s->baud_rate_gen); + writel(bdiv, ®s->baud_rate_divider); + writel(ZYNQ_UART_CR_TXRST | ZYNQ_UART_CR_RXRST, ®s->control); + writel(ZYNQ_UART_CR_RX_EN, ®s->control); + writel(ZYNQ_UART_CR_TX_EN, ®s->control); + } } /* Initialize the UART, with...some settings. */