From patchwork Fri Aug 14 07:15:08 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Frank Wunderlich X-Patchwork-Id: 1344693 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=fw-web.de Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=mailerdienst.de header.i=@mailerdienst.de header.a=rsa-sha256 header.s=20200217 header.b=DsnqQOz0; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4BSZTW273xz9sPB for ; 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Fri, 14 Aug 2020 07:15:16 +0000 (UTC) From: Frank Wunderlich To: u-boot@lists.denx.de Cc: Frank Wunderlich , GSS_MTK_Uboot_upstream@mediatek.com, chunfeng.yun@mediatek.com Subject: [PATCH 1/3] clk: mt7622: add needed clocks for ssusb-node Date: Fri, 14 Aug 2020 09:15:08 +0200 Message-Id: <20200814071510.6869-2-linux@fw-web.de> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200814071510.6869-1-linux@fw-web.de> References: <20200814071510.6869-1-linux@fw-web.de> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.3 at phobos.denx.de X-Virus-Status: Clean From: Frank Wunderlich MT7622 needs additional clock definitions to work properly Signed-off-by: Frank Wunderlich --- drivers/clk/mediatek/clk-mt7622.c | 42 +++++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/drivers/clk/mediatek/clk-mt7622.c b/drivers/clk/mediatek/clk-mt7622.c index 95c5232957..85df13338e 100644 --- a/drivers/clk/mediatek/clk-mt7622.c +++ b/drivers/clk/mediatek/clk-mt7622.c @@ -521,6 +521,20 @@ static const struct mtk_gate_regs sgmii_cg_regs = { .flags = CLK_GATE_NO_SETCLR_INV | CLK_PARENT_TOPCKGEN, \ } +static const struct mtk_gate_regs ssusb_cg_regs = { + .set_ofs = 0x30, + .clr_ofs = 0x30, + .sta_ofs = 0x30, +}; + +#define GATE_SSUSB(_id, _parent, _shift) { \ + .id = _id, \ + .parent = _parent, \ + .regs = &ssusb_cg_regs, \ + .shift = _shift, \ + .flags = CLK_GATE_NO_SETCLR_INV | CLK_PARENT_TOPCKGEN, \ +} + static const struct mtk_gate sgmii_cgs[] = { GATE_SGMII(CLK_SGMII_TX250M_EN, CLK_TOP_SSUSB_TX250M, 2), GATE_SGMII(CLK_SGMII_RX250M_EN, CLK_TOP_SSUSB_EQ_RX250M, 3), @@ -528,6 +542,15 @@ static const struct mtk_gate sgmii_cgs[] = { GATE_SGMII(CLK_SGMII_CDR_FB, CLK_TOP_SSUSB_CDR_FB, 5), }; +static const struct mtk_gate ssusb_cgs[] = { + GATE_SSUSB(CLK_SSUSB_U2_PHY_1P_EN, CLK_TOP_TO_U2_PHY_1P, 0), + GATE_SSUSB(CLK_SSUSB_U2_PHY_EN, CLK_TOP_TO_U2_PHY, 1), + GATE_SSUSB(CLK_SSUSB_REF_EN, CLK_TOP_TO_USB3_REF, 5), + GATE_SSUSB(CLK_SSUSB_SYS_EN, CLK_TOP_TO_USB3_SYS, 6), + GATE_SSUSB(CLK_SSUSB_MCU_EN, CLK_TOP_AXI_SEL, 7), + GATE_SSUSB(CLK_SSUSB_DMA_EN, CLK_TOP_HIF_SEL, 8), +}; + static const struct mtk_clk_tree mt7622_clk_tree = { .xtal_rate = 25 * MHZ, .xtal2_rate = 25 * MHZ, @@ -631,6 +654,11 @@ static int mt7622_sgmiisys_probe(struct udevice *dev) return mtk_common_clk_gate_init(dev, &mt7622_clk_tree, sgmii_cgs); } +static int mt7622_ssusbsys_probe(struct udevice *dev) +{ + return mtk_common_clk_gate_init(dev, &mt7622_clk_tree, ssusb_cgs); +} + static const struct udevice_id mt7622_apmixed_compat[] = { { .compatible = "mediatek,mt7622-apmixedsys" }, { } @@ -671,6 +699,11 @@ static const struct udevice_id mt7622_mcucfg_compat[] = { { } }; +static const struct udevice_id mt7622_ssusbsys_compat[] = { + { .compatible = "mediatek,mt7622-ssusbsys" }, + { } +}; + U_BOOT_DRIVER(mtk_mcucfg) = { .name = "mt7622-mcucfg", .id = UCLASS_SYSCON, @@ -747,3 +780,12 @@ U_BOOT_DRIVER(mtk_clk_sgmiisys) = { .priv_auto_alloc_size = sizeof(struct mtk_cg_priv), .ops = &mtk_clk_gate_ops, }; + +U_BOOT_DRIVER(mtk_clk_ssusbsys) = { + .name = "mt7622-clock-ssusbsys", + .id = UCLASS_CLK, + .of_match = mt7622_ssusbsys_compat, + .probe = mt7622_ssusbsys_probe, + .priv_auto_alloc_size = sizeof(struct mtk_cg_priv), + .ops = &mtk_clk_gate_ops, +}; From patchwork Fri Aug 14 07:15:09 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Frank Wunderlich X-Patchwork-Id: 1344696 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; 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Fri, 14 Aug 2020 07:15:18 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=mailerdienst.de; s=20200217; t=1597389318; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=jXgmJVuQv65auIlHwyTpMSFeFUCak3ObeD1T1LZdMws=; b=g4vBzWNyYz1ViQpEPDAuUx7o9SAFSxhgZbwzjnhBc0pbzrqYkZyhKW+w0YcG3/qfPO0ksr QJoRZZ7Rw/7BACE111Bnll5R0u6NrOuhBbSv6B1jdx1VPfQg9KKrGMHDTg44TnV155MQCv 21KkXtfPWWwEeCxS9qMk7SdK3jX+P0s= Received: from localhost.localdomain (fttx-pool-217.61.153.63.bambit.de [217.61.153.63]) by mxbox1.masterlogin.de (Postfix) with ESMTPSA id 8C83B402C0; Fri, 14 Aug 2020 07:15:17 +0000 (UTC) From: Frank Wunderlich To: u-boot@lists.denx.de Cc: Frank Wunderlich , GSS_MTK_Uboot_upstream@mediatek.com, chunfeng.yun@mediatek.com Subject: [PATCH 2/3] arm: dts: mt7622: add USB nodes Date: Fri, 14 Aug 2020 09:15:09 +0200 Message-Id: <20200814071510.6869-3-linux@fw-web.de> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200814071510.6869-1-linux@fw-web.de> References: <20200814071510.6869-1-linux@fw-web.de> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.3 at phobos.denx.de X-Virus-Status: Clean From: Frank Wunderlich Add DTS nodes for MT7622/BPI-R64 Signed-off-by: Frank Wunderlich --- this is based on xHCI driver Update (0.96 support) [1] and BPI-R64 DTS [2] [1] https://patchwork.ozlabs.org/project/uboot/list/?series=195331 [2] https://patchwork.ozlabs.org/project/uboot/list/?series=194922 --- arch/arm/dts/mt7622-bpi-r64.dts | 8 +++++ arch/arm/dts/mt7622.dtsi | 64 +++++++++++++++++++++++++++++++++ 2 files changed, 72 insertions(+) diff --git a/arch/arm/dts/mt7622-bpi-r64.dts b/arch/arm/dts/mt7622-bpi-r64.dts index aaa4d9a246..7f780db1a5 100644 --- a/arch/arm/dts/mt7622-bpi-r64.dts +++ b/arch/arm/dts/mt7622-bpi-r64.dts @@ -244,3 +244,11 @@ output-low; }; }; + +&ssusb { + status = "okay"; +}; + +&u3phy { + status = "okay"; +}; diff --git a/arch/arm/dts/mt7622.dtsi b/arch/arm/dts/mt7622.dtsi index 2802909671..e94884ad66 100644 --- a/arch/arm/dts/mt7622.dtsi +++ b/arch/arm/dts/mt7622.dtsi @@ -81,6 +81,12 @@ #clock-cells = <0>; }; + clk25m: dummy25m { + compatible = "fixed-clock"; + clock-frequency = <25000000>; + #clock-cells = <0>; + }; + infracfg: infracfg@10000000 { compatible = "mediatek,mt7622-infracfg", "syscon"; @@ -192,6 +198,14 @@ status = "disabled"; }; + ssusbsys: ssusbsys@1a000000 { + compatible = "mediatek,mt7622-ssusbsys", + "syscon"; + reg = <0x1a000000 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + pciesys: pciesys@1a100800 { compatible = "mediatek,mt7622-pciesys", "syscon"; reg = <0x1a100800 0x1000>; @@ -314,6 +328,56 @@ }; }; + ssusb: usb@1a0c0000 { + compatible = "mediatek,mt7622-xhci", + "mediatek,mtk-xhci"; + reg = <0x1a0c0000 0x01000>, + <0x1a0c4700 0x0100>; + reg-names = "mac", "ippc"; + interrupts = ; + power-domains = <&scpsys MT7629_POWER_DOMAIN_HIF1>; + clocks = <&ssusbsys CLK_SSUSB_SYS_EN>, + <&ssusbsys CLK_SSUSB_REF_EN>, + <&ssusbsys CLK_SSUSB_MCU_EN>, + <&ssusbsys CLK_SSUSB_DMA_EN>; + clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck"; + phys = <&u2port0 PHY_TYPE_USB2>, + <&u3port0 PHY_TYPE_USB3>, + <&u2port1 PHY_TYPE_USB2>; + status = "disabled"; + }; + + u3phy: usb-phy@1a0c4000 { + compatible = "mediatek,mt7622-u3phy", + "mediatek,generic-tphy-v1"; + reg = <0x1a0c4000 0x700>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + status = "disabled"; + + u2port0: usb-phy@1a0c4800 { + reg = <0x1a0c4800 0x0100>; + #phy-cells = <1>; + clocks = <&ssusbsys CLK_SSUSB_U2_PHY_EN>; + clock-names = "ref"; + }; + + u3port0: usb-phy@1a0c4900 { + reg = <0x1a0c4900 0x0700>; + #phy-cells = <1>; + clocks = <&clk25m>; + clock-names = "ref"; + }; + + u2port1: usb-phy@1a0c5000 { + reg = <0x1a0c5000 0x0100>; + #phy-cells = <1>; + clocks = <&ssusbsys CLK_SSUSB_U2_PHY_1P_EN>; + clock-names = "ref"; + }; + }; + ethsys: syscon@1b000000 { compatible = "mediatek,mt7622-ethsys", "syscon"; reg = <0x1b000000 0x1000>; From patchwork Fri Aug 14 07:15:10 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Frank Wunderlich X-Patchwork-Id: 1344697 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=fw-web.de Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=mailerdienst.de header.i=@mailerdienst.de header.a=rsa-sha256 header.s=20200217 header.b=dau7k9y0; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4BSZV83TMfz9sPB for ; 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Fri, 14 Aug 2020 07:15:18 +0000 (UTC) From: Frank Wunderlich To: u-boot@lists.denx.de Cc: Frank Wunderlich , GSS_MTK_Uboot_upstream@mediatek.com, chunfeng.yun@mediatek.com Subject: [PATCH 3/3] arm: dts: mt7623: add USB nodes Date: Fri, 14 Aug 2020 09:15:10 +0200 Message-Id: <20200814071510.6869-4-linux@fw-web.de> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200814071510.6869-1-linux@fw-web.de> References: <20200814071510.6869-1-linux@fw-web.de> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.3 at phobos.denx.de X-Virus-Status: Clean From: Frank Wunderlich This adds USB nodes for MT7623/BPI-R2 Signed-off-by: Frank Wunderlich --- needs xHCI 0.96 support [1] [1] https://patchwork.ozlabs.org/project/uboot/list/?series=195331 --- arch/arm/dts/mt7623.dtsi | 46 ++++++++++++++++++++++++ arch/arm/dts/mt7623n-bananapi-bpi-r2.dts | 16 +++++++++ 2 files changed, 62 insertions(+) diff --git a/arch/arm/dts/mt7623.dtsi b/arch/arm/dts/mt7623.dtsi index 0452889ef8..e753e08545 100644 --- a/arch/arm/dts/mt7623.dtsi +++ b/arch/arm/dts/mt7623.dtsi @@ -352,6 +352,52 @@ }; }; + usb1: usb@1a1c0000 { + compatible = "mediatek,mt7623-xhci", "mediatek,mtk-xhci"; + reg = <0x1a1c0000 0x1000>, <0x1a1c4700 0x0100>; + reg-names = "mac", "ippc"; + power-domains = <&scpsys MT7623_POWER_DOMAIN_HIF>; + clocks = <&hifsys CLK_HIFSYS_USB0PHY>, <&topckgen CLK_TOP_ETHIF_SEL>; + clock-names = "sys_ck", "ref_ck"; + phys = <&u2port0 PHY_TYPE_USB2>, <&u3port0 PHY_TYPE_USB3>; + status = "disabled"; + }; + + u3phy1: usb-phy1@1a1c4000 { + compatible = "mediatek,mt7623-tphy", "mediatek,generic-tphy-v1"; + + reg = <0x1a1c4000 0x0700>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + status = "disabled"; + + u2port0: usb-phy@1a1c4800 { + reg = <0x1a1c4800 0x0100>; + #phy-cells = <1>; + clocks = <&topckgen CLK_TOP_USB_PHY48M>; + clock-names = "ref"; + }; + + u3port0: usb-phy@1a1c4900 { + reg = <0x1a1c4900 0x0700>; + #phy-cells = <1>; + clocks = <&clk26m>; + clock-names = "ref"; + }; + }; + + usb2: usb@1a240000 { + compatible = "mediatek,mt7623-xhci", "mediatek,mtk-xhci"; + reg = <0x1a240000 0x1000>, <0x1a244700 0x0100>; + reg-names = "mac", "ippc"; + power-domains = <&scpsys MT7623_POWER_DOMAIN_HIF>; + clocks = <&hifsys CLK_HIFSYS_USB1PHY>, <&topckgen CLK_TOP_ETHIF_SEL>; + clock-names = "sys_ck", "ref_ck"; + phys = <&u2port1 PHY_TYPE_USB2>, <&u3port1 PHY_TYPE_USB3>; + status = "disabled"; + }; + u3phy2: usb-phy@1a244000 { compatible = "mediatek,generic-tphy-v1"; reg = <0x1a244000 0x0700>; diff --git a/arch/arm/dts/mt7623n-bananapi-bpi-r2.dts b/arch/arm/dts/mt7623n-bananapi-bpi-r2.dts index bcedcf20f1..ef07369627 100644 --- a/arch/arm/dts/mt7623n-bananapi-bpi-r2.dts +++ b/arch/arm/dts/mt7623n-bananapi-bpi-r2.dts @@ -248,3 +248,19 @@ pinctrl-0 = <&uart2_pins_a>; status = "okay"; }; + +&usb1 { + status = "okay"; +}; + +&u3phy1 { + status = "okay"; +}; + +&usb2 { + status = "okay"; +}; + +&u3phy2 { + status = "okay"; +};