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[147.11.224.80]) by smtp.gmail.com with ESMTPSA id g6sm15584898pfr.129.2020.07.19.23.06.39 (version=TLS1 cipher=AES128-SHA bits=128/128); Sun, 19 Jul 2020 23:06:40 -0700 (PDT) From: Bin Meng To: Rick Chen , Pragnesh Patel , Sagar Kadam , U-Boot Mailing List Cc: Bin Meng Subject: [PATCH v2 1/2] riscv: dts: hifive-unleashed-a00: Make memory node available to SPL Date: Sun, 19 Jul 2020 23:06:34 -0700 Message-Id: <1595225195-23197-1-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 1.7.1 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.3 at phobos.denx.de X-Virus-Status: Clean From: Bin Meng Make memory node available to SPL in prepration to updates to SiFive DDR RAM driver to read memory information from DT. Signed-off-by: Bin Meng Reviewed-by: Pragnesh Patel --- Changes in v2: - rebase on top of u-boot-riscv/master arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi b/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi index 7d838bf..5d0c928 100644 --- a/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi +++ b/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi @@ -20,6 +20,10 @@ u-boot,spl-payload-offset = <0x105000>; /* loader2 @1044KB */ }; + memory@80000000 { + u-boot,dm-spl; + }; + hfclk { u-boot,dm-spl; }; From patchwork Mon Jul 20 06:06:35 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 1332038 X-Patchwork-Delegate: uboot@andestech.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=VvpQWaol; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4B9B8C5kw3z9sR4 for ; Mon, 20 Jul 2020 16:07:07 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id F1ED581F73; Mon, 20 Jul 2020 08:06:51 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="VvpQWaol"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 13AD881C35; Mon, 20 Jul 2020 08:06:47 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.0 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FROM,SPF_HELO_NONE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.2 Received: from mail-pg1-x544.google.com (mail-pg1-x544.google.com [IPv6:2607:f8b0:4864:20::544]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 3EE5681C30 for ; Mon, 20 Jul 2020 08:06:43 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=bmeng.cn@gmail.com Received: by mail-pg1-x544.google.com with SMTP id w2so9793895pgg.10 for ; Sun, 19 Jul 2020 23:06:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=tIuQ7wxPB5HzgBykNKeZKko+HGucFlfHW9xaaoahp3g=; b=VvpQWaoll1RHEqqq4P4UgS1RnT02tyIev9ggLfNN9eOgAjwe39xIMdny2vhazlALwe vPWI1ohBa+CtEVL5DF1TwNlrrEtoEpfk8LotBMtcBTmFB5VmEyn+z+MYqJNQJ0cTGgBc iibxNvEBA127VWAgH1reoHEkvyhR0QV/Nqg62xqdJXrFB2lDG1ufJi1vKKfV6MKT9fOP 8kzP/qK8IbwxF8C4tNQeYQDHjtAOjnKVwadmKHXMz78jygd2k/LtmHFVK39VE44Q4al2 Pjbptuck9pNjx4dshKLSV7wi95LoaW8ZZ56dYMCRuVMmkRA+7laFNjAB3jrRr0ULQ4K4 SIcg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=tIuQ7wxPB5HzgBykNKeZKko+HGucFlfHW9xaaoahp3g=; b=ZneMXnTcN8Qfm4lcmTYetVQ8WXQ+DN7511ocRc2RWRjG6mfcKtqFnf75m2gDwPwRvv 1t6xrNOZ3HjA91zXGd5BZSN9c/zelOfnk2xfg9UNPjw/nxZnWSBWLTtns5IlQRv7KPdV gVArDmKJd8ZCvqvuvokX4vofhqK/KG/m37vdk84dmk8M2Fhsg76bTadtksKdT8fq6/9H kFw33lrtRrVoBJvS7489rMUpVRcJtbyXXOAfwJ9rr5Ygqb0zxUbeoSR/7stoxwXRWR4z TKDn4C0QnCxCUO/ex9tS9qb8zl8W7AZTOqOJgWQ/7xeRzBPYD1l9qpQlaMupM3F+IK+b eQJw== X-Gm-Message-State: AOAM5306enQFmJ/euvFKVLGWcFm/IeTmTJDd6N3QLEsaRpGcUoroK5QI n1aCQkGBmns9gl3mrvHzuIw= X-Google-Smtp-Source: ABdhPJxtoGSmmG9HwQA5QiV/NY65KBqZRVXZ7o126fPHgKy3Zzi2yDfADUlhMCinusOVa1GKDXRkVA== X-Received: by 2002:aa7:970a:: with SMTP id a10mr19082929pfg.319.1595225201741; Sun, 19 Jul 2020 23:06:41 -0700 (PDT) Received: from localhost.localdomain (unknown-224-80.windriver.com. [147.11.224.80]) by smtp.gmail.com with ESMTPSA id g6sm15584898pfr.129.2020.07.19.23.06.40 (version=TLS1 cipher=AES128-SHA bits=128/128); Sun, 19 Jul 2020 23:06:41 -0700 (PDT) From: Bin Meng To: Rick Chen , Pragnesh Patel , Sagar Kadam , U-Boot Mailing List Cc: Bin Meng Subject: [PATCH v2 2/2] ram: sifive: Avoid using hardcoded ram base and size Date: Sun, 19 Jul 2020 23:06:35 -0700 Message-Id: <1595225195-23197-2-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1595225195-23197-1-git-send-email-bmeng.cn@gmail.com> References: <1595225195-23197-1-git-send-email-bmeng.cn@gmail.com> X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.3 at phobos.denx.de X-Virus-Status: Clean From: Bin Meng At present the SiFive FU540 RAM driver uses hard-coded memory base address and size to initialize the DDR controller. This may not be true when this driver is used on another board based on FU540. Update the driver to read the memory information from DT and use that during the initialization. Signed-off-by: Bin Meng Reviewed-by: Leo Liang Reviewed-by: Pragnesh Patel --- Changes in v2: - Change to use fdtdec_setup_mem_size_base() API - Drop the 2 patches that added a new API in fdtdec drivers/ram/sifive/fu540_ddr.c | 30 +++++++++++++++--------------- 1 file changed, 15 insertions(+), 15 deletions(-) diff --git a/drivers/ram/sifive/fu540_ddr.c b/drivers/ram/sifive/fu540_ddr.c index f8f8ca9..2eef1e7 100644 --- a/drivers/ram/sifive/fu540_ddr.c +++ b/drivers/ram/sifive/fu540_ddr.c @@ -8,6 +8,7 @@ #include #include +#include #include #include #include @@ -39,9 +40,6 @@ #define DENALI_PHY_1152 1152 #define DENALI_PHY_1214 1214 -#define PAYLOAD_DEST 0x80000000 -#define DDR_MEM_SIZE (8UL * 1024UL * 1024UL * 1024UL) - #define DRAM_CLASS_OFFSET 8 #define DRAM_CLASS_DDR4 0xA #define OPTIMAL_RMODW_EN_OFFSET 0 @@ -65,6 +63,8 @@ #define PHY_RX_CAL_DQ0_0_OFFSET 0 #define PHY_RX_CAL_DQ1_0_OFFSET 16 +DECLARE_GLOBAL_DATA_PTR; + struct fu540_ddrctl { volatile u32 denali_ctl[265]; }; @@ -235,8 +235,8 @@ static int fu540_ddr_setup(struct udevice *dev) struct fu540_ddr_params *params = &plat->ddr_params; volatile u32 *denali_ctl = priv->ctl->denali_ctl; volatile u32 *denali_phy = priv->phy->denali_phy; - const u64 ddr_size = DDR_MEM_SIZE; - const u64 ddr_end = PAYLOAD_DEST + ddr_size; + const u64 ddr_size = priv->info.size; + const u64 ddr_end = priv->info.base + ddr_size; int ret, i; u32 physet; @@ -302,7 +302,7 @@ static int fu540_ddr_setup(struct udevice *dev) | (1 << MULTIPLE_OUT_OF_RANGE_OFFSET)); /* set up range protection */ - fu540_ddr_setup_range_protection(denali_ctl, DDR_MEM_SIZE); + fu540_ddr_setup_range_protection(denali_ctl, priv->info.size); /* Mask off port command error interrupt DENALI_CTL_136 */ setbits_le32(DENALI_CTL_136 + denali_ctl, @@ -314,14 +314,14 @@ static int fu540_ddr_setup(struct udevice *dev) /* check size */ priv->info.size = get_ram_size((long *)priv->info.base, - DDR_MEM_SIZE); + ddr_size); debug("%s : %lx\n", __func__, priv->info.size); /* check memory access for all memory */ - if (priv->info.size != DDR_MEM_SIZE) { + if (priv->info.size != ddr_size) { printf("DDR invalid size : 0x%lx, expected 0x%lx\n", - priv->info.size, DDR_MEM_SIZE); + priv->info.size, (uintptr_t)ddr_size); return -EINVAL; } @@ -333,6 +333,11 @@ static int fu540_ddr_probe(struct udevice *dev) { struct fu540_ddr_info *priv = dev_get_priv(dev); + /* Read memory base and size from DT */ + fdtdec_setup_mem_size_base(); + priv->info.base = gd->ram_base; + priv->info.size = gd->ram_size; + #if defined(CONFIG_SPL_BUILD) struct regmap *map; int ret; @@ -368,14 +373,9 @@ static int fu540_ddr_probe(struct udevice *dev) priv->phy = regmap_get_range(map, 1); priv->physical_filter_ctrl = regmap_get_range(map, 2); - priv->info.base = CONFIG_SYS_SDRAM_BASE; - - priv->info.size = 0; return fu540_ddr_setup(dev); -#else - priv->info.base = CONFIG_SYS_SDRAM_BASE; - priv->info.size = DDR_MEM_SIZE; #endif + return 0; }