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bh=X6mNIgAdYa0tMgiZma453G5C1wEi3y1OH6L/dlG5+eA=; b=eon6EM3ScOl3b0lG3BoBQwjP7LSH6YZ4uxTHSHZt07O3r8Pvgc2qY30M4S2yGel132/KbM nHC/xNr/kvhK1j+pNGWWBrEQ4bWu8M+2oQU7GCxQkhfRjcvo8JGSHu5m1mAA96Egwty+YA UK0jL6eajvPZ8vq18CrLPbl2+DSTALtJUCuBz/zw42MBD2Lz/3m0x/6LEyFjoQVfXCV1Y5 LEHFtdWHu5ppctRghog8sXljsF1399DQAdXKS8wOstBM4Lug9qLeksvaxyv0KKChd1kbKU UqZcanz0d0E5u72TRUTOkZAsoHuU1J770Vua5gsADGACtQfskr2Z0lADgKyLhQ== From: Sander Vanheule To: openwrt-devel@lists.openwrt.org Subject: [RFC PATCH 1/7] ath79: add lots of missing regs for QCA956x Date: Fri, 17 Jul 2020 13:37:34 +0200 Message-Id: <42cb33c5127101e8f68227d16e355c262173c398.1594981871.git.sander@svanheule.net> X-Mailer: git-send-email 2.26.2 In-Reply-To: References: MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200717_073843_456721_080DE99D X-CRM114-Status: GOOD ( 10.80 ) X-Spam-Score: 0.6 (/) X-Spam-Report: SpamAssassin version 3.4.4 on merlin.infradead.org summary: Content analysis details: (0.6 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [84.16.241.116 listed in list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record -0.0 SPF_HELO_PASS SPF: HELO matches SPF record 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.8 UPPERCASE_50_75 message body is 50-75% uppercase X-BeenThere: openwrt-devel@lists.openwrt.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: OpenWrt Development List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Sander Vanheule , me@bibbl.com, julien.dusser@free.fr, john@phrozen.org, rafal@milecki.pl, ynezz@true.cz, mail@david-bauer.net Sender: "openwrt-devel" Errors-To: openwrt-devel-bounces+incoming=patchwork.ozlabs.org@lists.openwrt.org This patch adds many registers and values for QCA956x GMAC interface. QCA956X_PLL_SWITCH_CLOCK_CONTROL_REG, QCA956X_PLL_ETH_XMII_CONTROL_REG and QCA956X_ETH_CFG_RGMII_EN names are fixed to match original names. Values are taken from U-Boot 1.1.4 of CAF. Signed-off-by: Julien Dusser Signed-off-by: Sander Vanheule --- .../920-qca956x-add-more-registers.patch | 186 ++++++++++++++++++ .../920-qca956x-add-more-registers.patch | 186 ++++++++++++++++++ 2 files changed, 372 insertions(+) create mode 100644 target/linux/ath79/patches-4.19/920-qca956x-add-more-registers.patch create mode 100644 target/linux/ath79/patches-5.4/920-qca956x-add-more-registers.patch diff --git a/target/linux/ath79/patches-4.19/920-qca956x-add-more-registers.patch b/target/linux/ath79/patches-4.19/920-qca956x-add-more-registers.patch new file mode 100644 index 0000000000..961bfe05ba --- /dev/null +++ b/target/linux/ath79/patches-4.19/920-qca956x-add-more-registers.patch @@ -0,0 +1,186 @@ +MIPS: ath79: add lots of missing registers for QCA956x SoCs + +This patch adds many registers and values for QCA956x GMAC interface. + +QCA956X_PLL_SWITCH_CLOCK_CONTROL_REG, QCA956X_PLL_ETH_XMII_CONTROL_REG +and QCA956X_ETH_CFG_RGMII_EN names are fixed to match original names. + +Values are taken from U-Boot 1.1.4 of CAF. + +Signed-off-by: Julien Dusser +--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h ++++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h +@@ -438,8 +438,18 @@ + #define QCA956X_PLL_DDR_CONFIG_REG 0x08 + #define QCA956X_PLL_DDR_CONFIG1_REG 0x0c + #define QCA956X_PLL_CLK_CTRL_REG 0x10 +-#define QCA956X_PLL_SWITCH_CLOCK_CONTROL_REG 0x28 +-#define QCA956X_PLL_ETH_XMII_CONTROL_REG 0x30 ++#define QCA956X_PLL_PCIE_PLL_CONFIG_REG 0x14 ++#define QCA956X_PLL_PCIE_PLL_DITHER_DIV_MAX_REG 0x18 ++#define QCA956X_PLL_PCIE_PLL_DITHER_DIV_MIN_REG 0x1c ++#define QCA956X_PLL_SWITCH_CLOCK_SPARE_REG 0x28 ++#define QCA956X_PLL_CURRENT_PCIE_PLL_DITHER_REG 0x2c ++#define QCA956X_PLL_ETH_XMII_REG 0x30 ++#define QCA956X_PLL_BB_PLL_CONFIG_REG 0x34 ++#define QCA956X_PLL_DDR_PLL_DITHER1_REG 0x38 ++#define QCA956X_PLL_DDR_PLL_DITHER2_REG 0x3c ++#define QCA956X_PLL_CPU_PLL_DITHER1_REG 0x40 ++#define QCA956X_PLL_CPU_PLL_DITHER2_REG 0x44 ++#define QCA956X_PLL_ETH_SGMII_REG 0x48 + #define QCA956X_PLL_ETH_SGMII_SERDES_REG 0x4c + + #define QCA956X_PLL_CPU_CONFIG_REFDIV_SHIFT 12 +@@ -1333,24 +1343,39 @@ + * QCA956X GMAC Interface + */ + +-#define QCA956X_GMAC_REG_ETH_CFG 0x00 +-#define QCA956X_GMAC_REG_SGMII_RESET 0x14 +-#define QCA956X_GMAC_REG_SGMII_SERDES 0x18 +-#define QCA956X_GMAC_REG_MR_AN_CONTROL 0x1c +-#define QCA956X_GMAC_REG_SGMII_CONFIG 0x34 +-#define QCA956X_GMAC_REG_SGMII_DEBUG 0x58 +- +-#define QCA956X_ETH_CFG_RGMII_EN BIT(0) ++#define QCA956X_GMAC_REG_ETH_CFG 0x00 ++#define QCA956X_GMAC_REG_SGMII_RESET 0x14 ++#define QCA956X_GMAC_REG_SGMII_SERDES 0x18 ++#define QCA956X_GMAC_REG_MR_AN_CONTROL 0x1c ++#define QCA956X_GMAC_REG_SGMII_CONFIG 0x34 ++#define QCA956X_GMAC_REG_SGMII_MAC_RX_CONFIG 0x38 ++#define QCA956X_GMAC_REG_ETH_SGMII 0x48 ++#define QCA956X_GMAC_REG_SGMII_DEBUG 0x58 ++#define QCA956X_GMAC_REG_SGMII_INTERRUPT 0x5c ++#define QCA956X_GMAC_REG_SGMII_INTERRUPT_MASK 0x60 ++ ++#define QCA956X_ETH_CFG_RGMII_GE0 BIT(0) ++#define QCA956X_ETH_CFG_MII_GE0 BIT(1) ++#define QCA956X_ETH_CFG_GMII_GE0 BIT(2) ++#define QCA956X_ETH_CFG_MII_GE0_MASTER BIT(3) ++#define QCA956X_ETH_CFG_MII_GE0_SLAVE BIT(4) ++#define QCA956X_ETH_CFG_GE0_ERR BIT(5) + #define QCA956X_ETH_CFG_GE0_SGMII BIT(6) + #define QCA956X_ETH_CFG_SW_ONLY_MODE BIT(7) + #define QCA956X_ETH_CFG_SW_PHY_SWAP BIT(8) + #define QCA956X_ETH_CFG_SW_PHY_ADDR_SWAP BIT(9) + #define QCA956X_ETH_CFG_SW_APB_ACCESS BIT(10) ++#define QCA956X_ETH_CFG_MII_CNTL_SPEED BIT(11) ++#define QCA956X_ETH_CFG_RMII_GE0_MASTER BIT(12) + #define QCA956X_ETH_CFG_SW_ACC_MSB_FIRST BIT(13) + #define QCA956X_ETH_CFG_RXD_DELAY_MASK 0x3 + #define QCA956X_ETH_CFG_RXD_DELAY_SHIFT 14 + #define QCA956X_ETH_CFG_RDV_DELAY_MASK 0x3 + #define QCA956X_ETH_CFG_RDV_DELAY_SHIFT 16 ++#define QCA956X_ETH_CFG_TXD_DELAY_MASK 0x3 ++#define QCA956X_ETH_CFG_TXD_DELAY_SHIFT 18 ++#define QCA956X_ETH_CFG_TXE_DELAY_MASK 0x3 ++#define QCA956X_ETH_CFG_TXE_DELAY_SHIFT 20 + + #define QCA956X_SGMII_RESET_RX_CLK_N_RESET 0x0 + #define QCA956X_SGMII_RESET_RX_CLK_N BIT(0) +@@ -1359,25 +1384,87 @@ + #define QCA956X_SGMII_RESET_TX_125M_N BIT(3) + #define QCA956X_SGMII_RESET_HW_RX_125M_N BIT(4) + +-#define QCA956X_SGMII_SERDES_CDR_BW_MASK 0x3 +-#define QCA956X_SGMII_SERDES_CDR_BW_SHIFT 1 +-#define QCA956X_SGMII_SERDES_TX_DR_CTRL_MASK 0x7 +-#define QCA956X_SGMII_SERDES_TX_DR_CTRL_SHIFT 4 +-#define QCA956X_SGMII_SERDES_PLL_BW BIT(8) +-#define QCA956X_SGMII_SERDES_VCO_FAST BIT(9) +-#define QCA956X_SGMII_SERDES_VCO_SLOW BIT(10) +-#define QCA956X_SGMII_SERDES_LOCK_DETECT_STATUS BIT(15) +-#define QCA956X_SGMII_SERDES_EN_SIGNAL_DETECT BIT(16) +-#define QCA956X_SGMII_SERDES_FIBER_SDO BIT(17) +-#define QCA956X_SGMII_SERDES_RES_CALIBRATION_SHIFT 23 +-#define QCA956X_SGMII_SERDES_RES_CALIBRATION_MASK 0xf +-#define QCA956X_SGMII_SERDES_VCO_REG_SHIFT 27 +-#define QCA956X_SGMII_SERDES_VCO_REG_MASK 0xf +- ++#define QCA956X_SGMII_SERDES_RX_IMPEDANCE BIT(0) ++#define QCA956X_SGMII_SERDES_CDR_BW_MASK 0x3 ++#define QCA956X_SGMII_SERDES_CDR_BW_SHIFT 1 ++#define QCA956X_SGMII_SERDES_HALF_TX BIT(3) ++#define QCA956X_SGMII_SERDES_TX_DR_CTRL_MASK 0x7 ++#define QCA956X_SGMII_SERDES_TX_DR_CTRL_SHIFT 4 ++#define QCA956X_SGMII_SERDES_TX_IMPEDANCE BIT(7) ++#define QCA956X_SGMII_SERDES_PLL_BW BIT(8) ++#define QCA956X_SGMII_SERDES_VCO_FAST BIT(9) ++#define QCA956X_SGMII_SERDES_VCO_SLOW BIT(10) ++#define QCA956X_SGMII_SERDES_LOCK_DETECT_STATUS BIT(15) ++#define QCA956X_SGMII_SERDES_EN_SIGNAL_DETECT BIT(16) ++#define QCA956X_SGMII_SERDES_FIBER_SDO BIT(17) ++#define QCA956X_SGMII_SERDES_THRESHOLD_CTRL_SHIFT 18 ++#define QCA956X_SGMII_SERDES_THRESHOLD_CTRL_MASK 0x3 ++#define QCA956X_SGMII_SERDES_FIBER_MODE_SHIFT 20 ++#define QCA956X_SGMII_SERDES_FIBER_MODE_MASK 0x3 ++#define QCA956X_SGMII_SERDES_RES_CALIBRATION_SHIFT 23 ++#define QCA956X_SGMII_SERDES_RES_CALIBRATION_MASK 0xf ++#define QCA956X_SGMII_SERDES_VCO_REG_SHIFT 27 ++#define QCA956X_SGMII_SERDES_VCO_REG_MASK 0xf ++ ++#define QCA956X_MR_AN_CONTROL_SPEED_SEL1 BIT(6) ++#define QCA956X_MR_AN_CONTROL_DUPLEX_MODE BIT(8) ++#define QCA956X_MR_AN_CONTROL_RESTART_AN BIT(9) ++#define QCA956X_MR_AN_CONTROL_POWER_DOWN BIT(11) + #define QCA956X_MR_AN_CONTROL_AN_ENABLE BIT(12) ++#define QCA956X_MR_AN_CONTROL_SPEED_SEL0 BIT(13) ++#define QCA956X_MR_AN_CONTROL_LOOPBACK BIT(14) + #define QCA956X_MR_AN_CONTROL_PHY_RESET BIT(15) + +-#define QCA956X_SGMII_CONFIG_MODE_CTRL_SHIFT 0 +-#define QCA956X_SGMII_CONFIG_MODE_CTRL_MASK 0x7 ++#define QCA956X_SGMII_CONFIG_MODE_CTRL_SHIFT 0 ++#define QCA956X_SGMII_CONFIG_MODE_CTRL_MASK 0x7 ++#define QCA956X_SGMII_CONFIG_ENABLE_SGMII_TX_PAUSE BIT(3) ++#define QCA956X_SGMII_CONFIG_MR_REG4_CHANGED BIT(4) ++#define QCA956X_SGMII_CONFIG_FORCE_SPEED BIT(5) ++#define QCA956X_SGMII_CONFIG_SPEED_SHIFT 6 ++#define QCA956X_SGMII_CONFIG_SPEED_MASK 0x3 ++#define QCA956X_SGMII_CONFIG_REMOTE_PHY_LOOPBACK BIT(8) ++#define QCA956X_SGMII_CONFIG_NEXT_PAGE_LOADED BIT(9) ++#define QCA956X_SGMII_CONFIG_MDIO_ENABLE BIT(10) ++#define QCA956X_SGMII_CONFIG_MDIO_PULSE BIT(11) ++#define QCA956X_SGMII_CONFIG_MDIO_COMPLETE BIT(12) ++#define QCA956X_SGMII_CONFIG_PRBS_ENABLE BIT(13) ++#define QCA956X_SGMII_CONFIG_BERT_ENABLE BIT(14) ++ ++#define QCA956X_SGMII_MAC_RX_CONFIG_RES0 BIT(0) ++#define QCA956X_SGMII_MAC_RX_CONFIG_PAUSE BIT(7) ++#define QCA956X_SGMII_MAC_RX_CONFIG_ASM_PAUSE BIT(8) ++#define QCA956X_SGMII_MAC_RX_CONFIG_SPEED_MODE_SHIFT 10 ++#define QCA956X_SGMII_MAC_RX_CONFIG_SPEED_MODE_MASK 0x3 ++#define QCA956X_SGMII_MAC_RX_CONFIG_DUPLEX_MODE BIT(12) ++#define QCA956X_SGMII_MAC_RX_CONFIG_ACK BIT(14) ++#define QCA956X_SGMII_MAC_RX_CONFIG_LINK BIT(15) ++ ++#define QCA956X_ETH_SGMII_PHASE0_COUNT_SHIFT 0 ++#define QCA956X_ETH_SGMII_PHASE0_COUNT_MASK 0xff ++#define QCA956X_ETH_SGMII_PHASE1_COUNT_SHIFT 8 ++#define QCA956X_ETH_SGMII_PHASE1_COUNT_MASK 0xff ++#define QCA956X_ETH_SGMII_GIGE BIT(24) ++#define QCA956X_ETH_SGMII_CLK_SEL BIT(25) ++#define QCA956X_ETH_SGMII_TX_DELAY_SHIFT 26 ++#define QCA956X_ETH_SGMII_TX_DELAY_MASK 0x3 ++#define QCA956X_ETH_SGMII_RX_DELAY_SHIFT 28 ++#define QCA956X_ETH_SGMII_RX_DELAY_MASK 0x3 ++#define QCA956X_ETH_SGMII_GIGE_QUAD BIT(30) ++#define QCA956X_ETH_SGMII_TX_INVERT BIT(31) ++ ++#define QCA956X_SGMII_DEBUG_TX_STATE_SHIFT 0 ++#define QCA956X_SGMII_DEBUG_TX_STATE_MASK 0xff ++#define QCA956X_SGMII_DEBUG_RX_STATE_SHIFT 8 ++#define QCA956X_SGMII_DEBUG_RX_STATE_MSB 0xff ++#define QCA956X_SGMII_DEBUG_RX_SYNC_STATE_SHIFT 16 ++#define QCA956X_SGMII_DEBUG_RX_SYNC_STATE_MASK 0xff ++#define QCA956X_SGMII_DEBUG_ARB_STATE_SHIFT 24 ++#define QCA956X_SGMII_DEBUG_ARB_STATE_MASK 0xf ++ ++#define QCA956X_SGMII_INTERRUPT_INTR_SHIFT 0 ++#define QCA956X_SGMII_INTERRUPT_INTR_MASK 0xff ++ ++#define QCA956X_SGMII_INTERRUPT_MASK_MASK_SHIFT 0 ++#define QCA956X_SGMII_INTERRUPT_MASK_MASK_MASK 0xff + + #endif /* __ASM_MACH_AR71XX_REGS_H */ diff --git a/target/linux/ath79/patches-5.4/920-qca956x-add-more-registers.patch b/target/linux/ath79/patches-5.4/920-qca956x-add-more-registers.patch new file mode 100644 index 0000000000..946669666f --- /dev/null +++ b/target/linux/ath79/patches-5.4/920-qca956x-add-more-registers.patch @@ -0,0 +1,186 @@ +MIPS: ath79: add lots of missing registers for QCA956x SoCs + +This patch adds many registers and values for QCA956x GMAC interface. + +QCA956X_PLL_SWITCH_CLOCK_CONTROL_REG, QCA956X_PLL_ETH_XMII_CONTROL_REG +and QCA956X_ETH_CFG_RGMII_EN names are fixed to match original names. + +Values are taken from U-Boot 1.1.4 of CAF. + +Signed-off-by: Julien Dusser +--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h ++++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h +@@ -435,8 +435,18 @@ + #define QCA956X_PLL_DDR_CONFIG_REG 0x08 + #define QCA956X_PLL_DDR_CONFIG1_REG 0x0c + #define QCA956X_PLL_CLK_CTRL_REG 0x10 +-#define QCA956X_PLL_SWITCH_CLOCK_CONTROL_REG 0x28 +-#define QCA956X_PLL_ETH_XMII_CONTROL_REG 0x30 ++#define QCA956X_PLL_PCIE_PLL_CONFIG_REG 0x14 ++#define QCA956X_PLL_PCIE_PLL_DITHER_DIV_MAX_REG 0x18 ++#define QCA956X_PLL_PCIE_PLL_DITHER_DIV_MIN_REG 0x1c ++#define QCA956X_PLL_SWITCH_CLOCK_SPARE_REG 0x28 ++#define QCA956X_PLL_CURRENT_PCIE_PLL_DITHER_REG 0x2c ++#define QCA956X_PLL_ETH_XMII_REG 0x30 ++#define QCA956X_PLL_BB_PLL_CONFIG_REG 0x34 ++#define QCA956X_PLL_DDR_PLL_DITHER1_REG 0x38 ++#define QCA956X_PLL_DDR_PLL_DITHER2_REG 0x3c ++#define QCA956X_PLL_CPU_PLL_DITHER1_REG 0x40 ++#define QCA956X_PLL_CPU_PLL_DITHER2_REG 0x44 ++#define QCA956X_PLL_ETH_SGMII_REG 0x48 + #define QCA956X_PLL_ETH_SGMII_SERDES_REG 0x4c + + #define QCA956X_PLL_CPU_CONFIG_REFDIV_SHIFT 12 +@@ -1330,24 +1340,39 @@ + * QCA956X GMAC Interface + */ + +-#define QCA956X_GMAC_REG_ETH_CFG 0x00 +-#define QCA956X_GMAC_REG_SGMII_RESET 0x14 +-#define QCA956X_GMAC_REG_SGMII_SERDES 0x18 +-#define QCA956X_GMAC_REG_MR_AN_CONTROL 0x1c +-#define QCA956X_GMAC_REG_SGMII_CONFIG 0x34 +-#define QCA956X_GMAC_REG_SGMII_DEBUG 0x58 +- +-#define QCA956X_ETH_CFG_RGMII_EN BIT(0) ++#define QCA956X_GMAC_REG_ETH_CFG 0x00 ++#define QCA956X_GMAC_REG_SGMII_RESET 0x14 ++#define QCA956X_GMAC_REG_SGMII_SERDES 0x18 ++#define QCA956X_GMAC_REG_MR_AN_CONTROL 0x1c ++#define QCA956X_GMAC_REG_SGMII_CONFIG 0x34 ++#define QCA956X_GMAC_REG_SGMII_MAC_RX_CONFIG 0x38 ++#define QCA956X_GMAC_REG_ETH_SGMII 0x48 ++#define QCA956X_GMAC_REG_SGMII_DEBUG 0x58 ++#define QCA956X_GMAC_REG_SGMII_INTERRUPT 0x5c ++#define QCA956X_GMAC_REG_SGMII_INTERRUPT_MASK 0x60 ++ ++#define QCA956X_ETH_CFG_RGMII_GE0 BIT(0) ++#define QCA956X_ETH_CFG_MII_GE0 BIT(1) ++#define QCA956X_ETH_CFG_GMII_GE0 BIT(2) ++#define QCA956X_ETH_CFG_MII_GE0_MASTER BIT(3) ++#define QCA956X_ETH_CFG_MII_GE0_SLAVE BIT(4) ++#define QCA956X_ETH_CFG_GE0_ERR BIT(5) + #define QCA956X_ETH_CFG_GE0_SGMII BIT(6) + #define QCA956X_ETH_CFG_SW_ONLY_MODE BIT(7) + #define QCA956X_ETH_CFG_SW_PHY_SWAP BIT(8) + #define QCA956X_ETH_CFG_SW_PHY_ADDR_SWAP BIT(9) + #define QCA956X_ETH_CFG_SW_APB_ACCESS BIT(10) ++#define QCA956X_ETH_CFG_MII_CNTL_SPEED BIT(11) ++#define QCA956X_ETH_CFG_RMII_GE0_MASTER BIT(12) + #define QCA956X_ETH_CFG_SW_ACC_MSB_FIRST BIT(13) + #define QCA956X_ETH_CFG_RXD_DELAY_MASK 0x3 + #define QCA956X_ETH_CFG_RXD_DELAY_SHIFT 14 + #define QCA956X_ETH_CFG_RDV_DELAY_MASK 0x3 + #define QCA956X_ETH_CFG_RDV_DELAY_SHIFT 16 ++#define QCA956X_ETH_CFG_TXD_DELAY_MASK 0x3 ++#define QCA956X_ETH_CFG_TXD_DELAY_SHIFT 18 ++#define QCA956X_ETH_CFG_TXE_DELAY_MASK 0x3 ++#define QCA956X_ETH_CFG_TXE_DELAY_SHIFT 20 + + #define QCA956X_SGMII_RESET_RX_CLK_N_RESET 0x0 + #define QCA956X_SGMII_RESET_RX_CLK_N BIT(0) +@@ -1356,25 +1381,87 @@ + #define QCA956X_SGMII_RESET_TX_125M_N BIT(3) + #define QCA956X_SGMII_RESET_HW_RX_125M_N BIT(4) + +-#define QCA956X_SGMII_SERDES_CDR_BW_MASK 0x3 +-#define QCA956X_SGMII_SERDES_CDR_BW_SHIFT 1 +-#define QCA956X_SGMII_SERDES_TX_DR_CTRL_MASK 0x7 +-#define QCA956X_SGMII_SERDES_TX_DR_CTRL_SHIFT 4 +-#define QCA956X_SGMII_SERDES_PLL_BW BIT(8) +-#define QCA956X_SGMII_SERDES_VCO_FAST BIT(9) +-#define QCA956X_SGMII_SERDES_VCO_SLOW BIT(10) +-#define QCA956X_SGMII_SERDES_LOCK_DETECT_STATUS BIT(15) +-#define QCA956X_SGMII_SERDES_EN_SIGNAL_DETECT BIT(16) +-#define QCA956X_SGMII_SERDES_FIBER_SDO BIT(17) +-#define QCA956X_SGMII_SERDES_RES_CALIBRATION_SHIFT 23 +-#define QCA956X_SGMII_SERDES_RES_CALIBRATION_MASK 0xf +-#define QCA956X_SGMII_SERDES_VCO_REG_SHIFT 27 +-#define QCA956X_SGMII_SERDES_VCO_REG_MASK 0xf +- ++#define QCA956X_SGMII_SERDES_RX_IMPEDANCE BIT(0) ++#define QCA956X_SGMII_SERDES_CDR_BW_MASK 0x3 ++#define QCA956X_SGMII_SERDES_CDR_BW_SHIFT 1 ++#define QCA956X_SGMII_SERDES_HALF_TX BIT(3) ++#define QCA956X_SGMII_SERDES_TX_DR_CTRL_MASK 0x7 ++#define QCA956X_SGMII_SERDES_TX_DR_CTRL_SHIFT 4 ++#define QCA956X_SGMII_SERDES_TX_IMPEDANCE BIT(7) ++#define QCA956X_SGMII_SERDES_PLL_BW BIT(8) ++#define QCA956X_SGMII_SERDES_VCO_FAST BIT(9) ++#define QCA956X_SGMII_SERDES_VCO_SLOW BIT(10) ++#define QCA956X_SGMII_SERDES_LOCK_DETECT_STATUS BIT(15) ++#define QCA956X_SGMII_SERDES_EN_SIGNAL_DETECT BIT(16) ++#define QCA956X_SGMII_SERDES_FIBER_SDO BIT(17) ++#define QCA956X_SGMII_SERDES_THRESHOLD_CTRL_SHIFT 18 ++#define QCA956X_SGMII_SERDES_THRESHOLD_CTRL_MASK 0x3 ++#define QCA956X_SGMII_SERDES_FIBER_MODE_SHIFT 20 ++#define QCA956X_SGMII_SERDES_FIBER_MODE_MASK 0x3 ++#define QCA956X_SGMII_SERDES_RES_CALIBRATION_SHIFT 23 ++#define QCA956X_SGMII_SERDES_RES_CALIBRATION_MASK 0xf ++#define QCA956X_SGMII_SERDES_VCO_REG_SHIFT 27 ++#define QCA956X_SGMII_SERDES_VCO_REG_MASK 0xf ++ ++#define QCA956X_MR_AN_CONTROL_SPEED_SEL1 BIT(6) ++#define QCA956X_MR_AN_CONTROL_DUPLEX_MODE BIT(8) ++#define QCA956X_MR_AN_CONTROL_RESTART_AN BIT(9) ++#define QCA956X_MR_AN_CONTROL_POWER_DOWN BIT(11) + #define QCA956X_MR_AN_CONTROL_AN_ENABLE BIT(12) ++#define QCA956X_MR_AN_CONTROL_SPEED_SEL0 BIT(13) ++#define QCA956X_MR_AN_CONTROL_LOOPBACK BIT(14) + #define QCA956X_MR_AN_CONTROL_PHY_RESET BIT(15) + +-#define QCA956X_SGMII_CONFIG_MODE_CTRL_SHIFT 0 +-#define QCA956X_SGMII_CONFIG_MODE_CTRL_MASK 0x7 ++#define QCA956X_SGMII_CONFIG_MODE_CTRL_SHIFT 0 ++#define QCA956X_SGMII_CONFIG_MODE_CTRL_MASK 0x7 ++#define QCA956X_SGMII_CONFIG_ENABLE_SGMII_TX_PAUSE BIT(3) ++#define QCA956X_SGMII_CONFIG_MR_REG4_CHANGED BIT(4) ++#define QCA956X_SGMII_CONFIG_FORCE_SPEED BIT(5) ++#define QCA956X_SGMII_CONFIG_SPEED_SHIFT 6 ++#define QCA956X_SGMII_CONFIG_SPEED_MASK 0x3 ++#define QCA956X_SGMII_CONFIG_REMOTE_PHY_LOOPBACK BIT(8) ++#define QCA956X_SGMII_CONFIG_NEXT_PAGE_LOADED BIT(9) ++#define QCA956X_SGMII_CONFIG_MDIO_ENABLE BIT(10) ++#define QCA956X_SGMII_CONFIG_MDIO_PULSE BIT(11) ++#define QCA956X_SGMII_CONFIG_MDIO_COMPLETE BIT(12) ++#define QCA956X_SGMII_CONFIG_PRBS_ENABLE BIT(13) ++#define QCA956X_SGMII_CONFIG_BERT_ENABLE BIT(14) ++ ++#define QCA956X_SGMII_MAC_RX_CONFIG_RES0 BIT(0) ++#define QCA956X_SGMII_MAC_RX_CONFIG_PAUSE BIT(7) ++#define QCA956X_SGMII_MAC_RX_CONFIG_ASM_PAUSE BIT(8) ++#define QCA956X_SGMII_MAC_RX_CONFIG_SPEED_MODE_SHIFT 10 ++#define QCA956X_SGMII_MAC_RX_CONFIG_SPEED_MODE_MASK 0x3 ++#define QCA956X_SGMII_MAC_RX_CONFIG_DUPLEX_MODE BIT(12) ++#define QCA956X_SGMII_MAC_RX_CONFIG_ACK BIT(14) ++#define QCA956X_SGMII_MAC_RX_CONFIG_LINK BIT(15) ++ ++#define QCA956X_ETH_SGMII_PHASE0_COUNT_SHIFT 0 ++#define QCA956X_ETH_SGMII_PHASE0_COUNT_MASK 0xff ++#define QCA956X_ETH_SGMII_PHASE1_COUNT_SHIFT 8 ++#define QCA956X_ETH_SGMII_PHASE1_COUNT_MASK 0xff ++#define QCA956X_ETH_SGMII_GIGE BIT(24) ++#define QCA956X_ETH_SGMII_CLK_SEL BIT(25) ++#define QCA956X_ETH_SGMII_TX_DELAY_SHIFT 26 ++#define QCA956X_ETH_SGMII_TX_DELAY_MASK 0x3 ++#define QCA956X_ETH_SGMII_RX_DELAY_SHIFT 28 ++#define QCA956X_ETH_SGMII_RX_DELAY_MASK 0x3 ++#define QCA956X_ETH_SGMII_GIGE_QUAD BIT(30) ++#define QCA956X_ETH_SGMII_TX_INVERT BIT(31) ++ ++#define QCA956X_SGMII_DEBUG_TX_STATE_SHIFT 0 ++#define QCA956X_SGMII_DEBUG_TX_STATE_MASK 0xff ++#define QCA956X_SGMII_DEBUG_RX_STATE_SHIFT 8 ++#define QCA956X_SGMII_DEBUG_RX_STATE_MSB 0xff ++#define QCA956X_SGMII_DEBUG_RX_SYNC_STATE_SHIFT 16 ++#define QCA956X_SGMII_DEBUG_RX_SYNC_STATE_MASK 0xff ++#define QCA956X_SGMII_DEBUG_ARB_STATE_SHIFT 24 ++#define QCA956X_SGMII_DEBUG_ARB_STATE_MASK 0xf ++ ++#define QCA956X_SGMII_INTERRUPT_INTR_SHIFT 0 ++#define QCA956X_SGMII_INTERRUPT_INTR_MASK 0xff ++ ++#define QCA956X_SGMII_INTERRUPT_MASK_MASK_SHIFT 0 ++#define QCA956X_SGMII_INTERRUPT_MASK_MASK_MASK 0xff + + #endif /* __ASM_MACH_AR71XX_REGS_H */ From patchwork Fri Jul 17 11:37:35 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sander Vanheule X-Patchwork-Id: 1331083 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.openwrt.org (client-ip=2001:8b0:10b:1231::1; helo=merlin.infradead.org; envelope-from=openwrt-devel-bounces+incoming=patchwork.ozlabs.org@lists.openwrt.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail 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Linux)) id 1jwOhO-0005Bm-K5 for openwrt-devel@lists.openwrt.org; Fri, 17 Jul 2020 11:38:44 +0000 Received: from terra.local.svanheule.net (unknown [IPv6:2a02:a03f:5670:b301:1c6f:d128:905e:da70]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) (Authenticated sender: sander@svanheule.net) by polaris.svanheule.net (Postfix) with ESMTPSA id 257661601B4; Fri, 17 Jul 2020 13:38:39 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=svanheule.net; s=mail1707; t=1594985919; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=Fq8Pc8F/Hg/g9DQAb+ieXM2ZgfHycVmKKaILef5zLBQ=; b=OGfe/6173iEw6MkgI08uSRulTxzF8Iq9XpnBWc1Mj0ngDKL+qmBX9fcE1ulP9D1puldH0z wrEx4RuThxtC0Sxvyq/wGSYEL8XnplPKvvv86ZcQHfJmTq3xIgkSCvt6GSbqo9GLCRjQVk xCjUdpMTsx7g/+DGB4C8vkRob7/458T/K8r01BhI/hV9HhJliM5fEDwL3zjr4BJbC6po0t BlfrpreI3OLIyUkoKxJOlIBPlZt5TidN9uxfIZvepUNFkREySp2nGGe0JYLnxrjuQ1bYru DXo9gAujcjo6G/ojNZ+HyqqPSbOOEXxIvjhrmxN3Ny5YPgtYfx/zD4TSBXUKJg== From: Sander Vanheule To: openwrt-devel@lists.openwrt.org Subject: [RFC PATCH 2/7] ath79: export more QCA956x GMAC settings to DT Date: Fri, 17 Jul 2020 13:37:35 +0200 Message-Id: X-Mailer: git-send-email 2.26.2 In-Reply-To: References: MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200717_073843_385547_034C1DBB X-CRM114-Status: UNSURE ( 7.24 ) X-CRM114-Notice: Please train this message. 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Signed-off-by: Julien Dusser Signed-off-by: Sander Vanheule --- .../net/ethernet/atheros/ag71xx/ag71xx_gmac.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/target/linux/ath79/files/drivers/net/ethernet/atheros/ag71xx/ag71xx_gmac.c b/target/linux/ath79/files/drivers/net/ethernet/atheros/ag71xx/ag71xx_gmac.c index cc0a15d3a4..57b8bf2eec 100644 --- a/target/linux/ath79/files/drivers/net/ethernet/atheros/ag71xx/ag71xx_gmac.c +++ b/target/linux/ath79/files/drivers/net/ethernet/atheros/ag71xx/ag71xx_gmac.c @@ -88,9 +88,23 @@ static void ag71xx_setup_gmac_956x(struct device_node *np, void __iomem *base) { u32 val = __raw_readl(base + QCA956X_GMAC_REG_ETH_CFG); + ag71xx_of_bit(np, "rgmii-ge0", &val, QCA956X_ETH_CFG_RGMII_GE0); + ag71xx_of_bit(np, "mii-ge0", &val, QCA956X_ETH_CFG_MII_GE0); + ag71xx_of_bit(np, "gmii-ge0", &val, QCA956X_ETH_CFG_GMII_GE0); + ag71xx_of_bit(np, "mii-ge0-master", &val, QCA956X_ETH_CFG_MII_GE0_MASTER); + ag71xx_of_bit(np, "mii-ge0-slave", &val, QCA956X_ETH_CFG_MII_GE0_SLAVE); + ag71xx_of_bit(np, "ge0-sgmii", &val, QCA956X_ETH_CFG_GE0_SGMII); ag71xx_of_bit(np, "switch-phy-swap", &val, QCA956X_ETH_CFG_SW_PHY_SWAP); ag71xx_of_bit(np, "switch-phy-addr-swap", &val, QCA956X_ETH_CFG_SW_PHY_ADDR_SWAP); + ag71xx_of_set(np, "txen-delay", &val, QCA956X_ETH_CFG_TXE_DELAY_SHIFT, + QCA956X_ETH_CFG_TXE_DELAY_MASK); + ag71xx_of_set(np, "txd-delay", &val, QCA956X_ETH_CFG_TXD_DELAY_SHIFT, + QCA956X_ETH_CFG_TXD_DELAY_MASK); + ag71xx_of_set(np, "rxdv-delay", &val, QCA956X_ETH_CFG_RDV_DELAY_SHIFT, + QCA956X_ETH_CFG_RDV_DELAY_MASK); + ag71xx_of_set(np, "rxd-delay", &val, QCA956X_ETH_CFG_RXD_DELAY_SHIFT, + QCA956X_ETH_CFG_RXD_DELAY_MASK); __raw_writel(val, base + QCA956X_GMAC_REG_ETH_CFG); } From patchwork Fri Jul 17 11:37:36 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sander Vanheule X-Patchwork-Id: 1331082 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; 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Fri, 17 Jul 2020 11:38:50 +0000 Received: from polaris.svanheule.net ([84.16.241.116]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1jwOhP-0005Bn-CE for openwrt-devel@lists.openwrt.org; Fri, 17 Jul 2020 11:38:45 +0000 Received: from terra.local.svanheule.net (unknown [IPv6:2a02:a03f:5670:b301:1c6f:d128:905e:da70]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) (Authenticated sender: sander@svanheule.net) by polaris.svanheule.net (Postfix) with ESMTPSA id 9FE691601B5; Fri, 17 Jul 2020 13:38:39 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=svanheule.net; s=mail1707; t=1594985920; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=jRMyhG3NbK4/kTdtie4ArQ9vwams4xaNm/lsN+WAfAE=; b=7OiJAuhbQ+HLoyfSLUR3YcNG3H+rJ2X6I+I5sr5vs8FodqiNAyU0zwxbaE927QXbfWN5cb 82YDy08th9hnaA0onyrO47sRzrgoyiDLpKESPSr70xt8oKPS2ba1WsHWgYGabtZUTE/Nje LOgwrJIUW3b/iOvKcW2dz9FjhIVM2U/xDnSZciNPwzPHib5OSnEJxJYM+OBoN0SmxIzBbu t20qCxbe05p5ODtMF4AzZ46Ymx6CVMh0dVU0OLNsXz18nrngKHpEPP1fGELq6CcK689+D8 M5B0JrRytn5OkQnm3cFpAUk7iAL4FdWOogrRzaiIEALNpfC4gs/4Pwc3YHftjg== From: Sander Vanheule To: openwrt-devel@lists.openwrt.org Subject: [RFC PATCH 3/7] ath79: add QCA956x SERDES init workaround Date: Fri, 17 Jul 2020 13:37:36 +0200 Message-Id: X-Mailer: git-send-email 2.26.2 In-Reply-To: References: MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200717_073843_575984_F547450A X-CRM114-Status: GOOD ( 13.55 ) X-Spam-Score: -0.2 (/) X-Spam-Report: SpamAssassin version 3.4.4 on merlin.infradead.org summary: Content analysis details: (-0.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [84.16.241.116 listed in list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record -0.0 SPF_HELO_PASS SPF: HELO matches SPF record 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature X-BeenThere: openwrt-devel@lists.openwrt.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: OpenWrt Development List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Sander Vanheule , me@bibbl.com, julien.dusser@free.fr, john@phrozen.org, rafal@milecki.pl, ynezz@true.cz, mail@david-bauer.net Sender: "openwrt-devel" Errors-To: openwrt-devel-bounces+incoming=patchwork.ozlabs.org@lists.openwrt.org This commit add a workaround for non working SGMII link observed on some QCA956x SoCs. The workaround originates part from the U-Boot source code from QCA, part from the implementation from TP-Link found in the GPL tarball for the EAP245v1. Extends commit 0d416a8d3b990e3b78628f0e7546527709c877f7 for QCA956x. Note that reset is the same on QCA955x and QCA956x, same register offset and values. Auto calibration is done on u-boot, but always fall back to default value 0x7. Add a DTS entry serdes-cal in case a device require another value. Signed-off-by: Julien Dusser Signed-off-by: Sander Vanheule --- .../net/ethernet/atheros/ag71xx/ag71xx_main.c | 78 +++++++++++++++++++ 1 file changed, 78 insertions(+) diff --git a/target/linux/ath79/files/drivers/net/ethernet/atheros/ag71xx/ag71xx_main.c b/target/linux/ath79/files/drivers/net/ethernet/atheros/ag71xx/ag71xx_main.c index d611007a86..1a22dbfd4d 100644 --- a/target/linux/ath79/files/drivers/net/ethernet/atheros/ag71xx/ag71xx_main.c +++ b/target/linux/ath79/files/drivers/net/ethernet/atheros/ag71xx/ag71xx_main.c @@ -577,6 +577,79 @@ static void ag71xx_bit_clear(void __iomem *reg, u32 bit) __raw_readl(reg); } +/* Set SGMII VCO resistor value */ +static void ag71xx_serdes_cal_qca956x(struct device_node *np) +{ + struct device_node *np_dev; + void __iomem *gmac_base; + int err = 0; + u32 serdes_cal; + u32 t; + + np = of_get_child_by_name(np, "gmac-config"); + if (!np) + return; + + if(of_property_read_u32(np, "serdes-cal", &serdes_cal)) + /* By default, use middle value for resistor calibration */ + serdes_cal = 0x7; + + np_dev = of_parse_phandle(np, "device", 0); + if (!np_dev) + goto out; + + gmac_base = of_iomap(np_dev, 0); + if (!gmac_base) { + pr_err("%pOF: can't map GMAC registers\n", np_dev); + err = -ENOMEM; + goto err_iomap; + } + + pr_info("%pOF: fixup SERDES calibration to value %i\n", np_dev, serdes_cal); + t = __raw_readl(gmac_base + QCA956X_GMAC_REG_SGMII_SERDES); + t &= ~(QCA956X_SGMII_SERDES_RES_CALIBRATION_MASK + << QCA956X_SGMII_SERDES_RES_CALIBRATION_SHIFT); + t |= (serdes_cal & QCA956X_SGMII_SERDES_RES_CALIBRATION_MASK) + << QCA956X_SGMII_SERDES_RES_CALIBRATION_SHIFT; + __raw_writel(t, gmac_base + QCA956X_GMAC_REG_SGMII_SERDES); + + ath79_pll_wr(QCA956X_PLL_ETH_SGMII_SERDES_REG, + QCA956X_PLL_ETH_SGMII_SERDES_LOCK_DETECT + | QCA956X_PLL_ETH_SGMII_SERDES_EN_PLL); + + t = __raw_readl(gmac_base + QCA956X_GMAC_REG_SGMII_SERDES); + + /* missing in QCA u-boot code, clear before setting */ + t &= ~(QCA956X_SGMII_SERDES_CDR_BW_MASK + << QCA956X_SGMII_SERDES_CDR_BW_SHIFT | + QCA956X_SGMII_SERDES_TX_DR_CTRL_MASK + << QCA956X_SGMII_SERDES_TX_DR_CTRL_SHIFT | + QCA956X_SGMII_SERDES_VCO_REG_MASK + << QCA956X_SGMII_SERDES_VCO_REG_SHIFT); + + t |= (3 << QCA956X_SGMII_SERDES_CDR_BW_SHIFT) | + (1 << QCA956X_SGMII_SERDES_TX_DR_CTRL_SHIFT) | + QCA956X_SGMII_SERDES_PLL_BW | + QCA956X_SGMII_SERDES_EN_SIGNAL_DETECT | + QCA956X_SGMII_SERDES_FIBER_SDO | + (3 << QCA956X_SGMII_SERDES_VCO_REG_SHIFT); + + __raw_writel(t, gmac_base + QCA956X_GMAC_REG_SGMII_SERDES); + + ath79_device_reset_clear(QCA956X_RESET_SGMII_ANALOG); + ath79_device_reset_clear(QCA956X_RESET_SGMII); + + while (!(__raw_readl(gmac_base + QCA956X_GMAC_REG_SGMII_SERDES) + & QCA956X_SGMII_SERDES_LOCK_DETECT_STATUS)) + ; + + iounmap(gmac_base); +err_iomap: + of_node_put(np_dev); +out: + of_node_put(np); +} + static void ag71xx_sgmii_init_qca955x(struct device_node *np) { struct device_node *np_dev; @@ -1423,6 +1496,11 @@ static int ag71xx_probe(struct platform_device *pdev) if (!res) return -EINVAL; + if (of_property_read_bool(np, "qca956x-serdes-fixup")) { + ag71xx_serdes_cal_qca956x(np); + ag71xx_sgmii_init_qca955x(np); + } + err = ag71xx_setup_gmac(np); if (err) return err; From patchwork Fri Jul 17 11:37:37 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sander Vanheule X-Patchwork-Id: 1331079 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.openwrt.org (client-ip=2001:8b0:10b:1231::1; helo=merlin.infradead.org; envelope-from=openwrt-devel-bounces+incoming=patchwork.ozlabs.org@lists.openwrt.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=svanheule.net Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; secure) header.d=lists.infradead.org header.i=@lists.infradead.org header.a=rsa-sha256 header.s=merlin.20170209 header.b=ZTGWuSlr; dkim=fail reason="signature verification failed" (2048-bit key; secure) header.d=svanheule.net header.i=@svanheule.net header.a=rsa-sha256 header.s=mail1707 header.b=hHxuBIvl; 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bh=tBE24szsdmbx3ytx4wtf2As/P7hOFVj3IJ6ThsX3pzo=; b=hHxuBIvlqtCgQ9CZqsbaXuK4cWn9/ndDIyEyAk/iwgtFJvFa5xOsK6ZNVvqnpaepg4RSP9 wJw2pwTe9iLPY+mKwy1psAIEPB3mr/t7B5O83ZP8v5Wdtx8JtbCIuhPbfFko4rn5r4vJJh T2Nq9tm6f187qOspYfJD74orI7WZVYqOi+ivyVyuywSo7DS7jJ0psnJY3tGAuLbuq9ILuy uLo+hkmpPiYu9QP3qylB2paXRPTY3z9iv0GLMB6Br6svl29qQL4EjJGTN5KmmocV8JqfKi CniGtwEpstDnpeJjkLIXP52Nc5zNvpUmZpdfVlcfZlowZXms41TpmW9U2Z857w== From: Sander Vanheule To: openwrt-devel@lists.openwrt.org Subject: [RFC PATCH 4/7] ath79: prepare for 1-port TP-Link EAP2x5 devices Date: Fri, 17 Jul 2020 13:37:37 +0200 Message-Id: <9c4be5fee600b47ae0d346d4005acdbbf5662925.1594981871.git.sander@svanheule.net> X-Mailer: git-send-email 2.26.2 In-Reply-To: References: MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200717_073844_638723_D9B06F89 X-CRM114-Status: GOOD ( 12.36 ) X-Spam-Score: -0.2 (/) X-Spam-Report: SpamAssassin version 3.4.4 on merlin.infradead.org summary: Content analysis details: (-0.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2a00:c98:2060:a004:1:0:0:200 listed in] [list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record -0.0 SPF_HELO_PASS SPF: HELO matches SPF record 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature X-BeenThere: openwrt-devel@lists.openwrt.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: OpenWrt Development List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Sander Vanheule , me@bibbl.com, julien.dusser@free.fr, john@phrozen.org, rafal@milecki.pl, ynezz@true.cz, mail@david-bauer.net Sender: "openwrt-devel" Errors-To: openwrt-devel-bounces+incoming=patchwork.ozlabs.org@lists.openwrt.org TP-Link has developed a number of access points based on the AP152 reference board. In the EAP-series of 802.11ac access points, this includes the following devices with one ethernet port: * EAP225 v1/v2 * EAP225 v3 * EAP225-Outdoor v1 * EAP245 v1 Since the only differences between these devices are the ath10k wireless radios and LEDs, a common base is provided for the overlapping support requirements. Hardware commonalities: * SoC: QCA9563-AL3A MIPS 74kc v5.0 @ 775MHz * RAM: 128MiB DDR2 @ 650MHz * Flash: 16MiB SPI NOR * Wi-Fi 2.4GHz: provided by SoC * Wi-Fi 5Ghz: ath10k chip on PCIe * Ethernet: AR8033-AL1A, one 1GbE port (802.3at PoE) This patch was originally developed by Julien Dusser for the EAP245 v1, and was adapted by Sander Vanheule to support more devices. Signed-off-by: Julien Dusser Signed-off-by: Sander Vanheule --- .../dts/qca9563_tplink_eap2x5_1port.dtsi | 174 ++++++++++++++++++ target/linux/ath79/image/generic-tp-link.mk | 10 + 2 files changed, 184 insertions(+) create mode 100644 target/linux/ath79/dts/qca9563_tplink_eap2x5_1port.dtsi diff --git a/target/linux/ath79/dts/qca9563_tplink_eap2x5_1port.dtsi b/target/linux/ath79/dts/qca9563_tplink_eap2x5_1port.dtsi new file mode 100644 index 0000000000..1b55bb855c --- /dev/null +++ b/target/linux/ath79/dts/qca9563_tplink_eap2x5_1port.dtsi @@ -0,0 +1,174 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/dts-v1/; + +#include +#include + +#include "qca956x.dtsi" + +/ { + aliases { + label-device-mac = ð0; + led-boot = &led_status_green; + led-failsafe = &led_status_amber; + led-running = &led_status_green; + led-upgrade = &led_status_amber; + }; + + leds { + compatible = "gpio-leds"; + + led_status_green: status_green { + status = "disabled"; + label = "tp-link:green:status"; + default-state = "on"; + }; + + led_status_amber: status_amber { + status = "disabled"; + label = "tp-link:amber:status"; + }; + + led_status_red: status_red { + status = "disabled"; + label = "tp-link:red:status"; + }; + }; + + keys { + compatible = "gpio-keys"; + + reset { + label = "Reset button"; + linux,code = ; + gpios = <&gpio 2 GPIO_ACTIVE_LOW>; + debounce-interval = <60>; + }; + }; +}; + +&pcie { + status = "okay"; +}; + +&uart { + status = "okay"; +}; + +&gpio { + status = "okay"; +}; + +&spi { + status = "okay"; + num-cs = <1>; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <25000000>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "u-boot"; + reg = <0x000000 0x020000>; + read-only; + }; + + partition@20000 { + label = "partition-table"; + reg = <0x020000 0x010000>; + read-only; + }; + + info: partition@30000 { + label = "info"; + reg = <0x030000 0x010000>; + read-only; + }; + + partition@40000 { + compatible = "openwrt,elf"; + label = "firmware"; + reg = <0x040000 0xec0000>; + }; + + partition@f00000 { + label = "config"; + reg = <0xf00000 0x030000>; + read-only; + }; + + partition@f30000 { + label = "mutil-log"; + reg = <0xf30000 0x080000>; + read-only; + }; + + partition@fb0000 { + label = "oops"; + reg = <0xfb0000 0x040000>; + read-only; + }; + + art: partition@ff0000 { + label = "art"; + reg = <0xff0000 0x010000>; + read-only; + }; + }; + }; +}; + +&pinmux { + mdio_pins: pinux_mdio_pins { + /* GPIO 8 as MDC(0x21), GPIO 10 as MDIO(0x20) */ + pinctrl-single,bits = <0x8 0x00000021 0x000000ff>, + <0x8 0x00200000 0x00ff0000>; + }; +}; + +&mdio0 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&mdio_pins>; + + phy-mask = <0x10>; + + phy4: ethernet-phy@4 { + reg = <4>; + phy-mode = "sgmii"; + reset-gpios = <&gpio 11 GPIO_ACTIVE_LOW>; + }; +}; + +ð0 { + status = "okay"; + + phy-handle = <&phy4>; + + mtd-mac-address = <&info 0x8>; + + qca956x-serdes-fixup; + + gmac-config { + device = <&gmac>; + + rgmii-ge0 = <1>; + ge0-sgmii = <1>; + rxdv-delay = <3>; + rxd-delay = <3>; + }; +}; + +&wmac { + status = "okay"; + + mtd-cal-data = <&art 0x1000>; + mtd-mac-address = <&info 0x8>; +}; diff --git a/target/linux/ath79/image/generic-tp-link.mk b/target/linux/ath79/image/generic-tp-link.mk index 8a26e4bebe..d2cc8d09bd 100644 --- a/target/linux/ath79/image/generic-tp-link.mk +++ b/target/linux/ath79/image/generic-tp-link.mk @@ -362,6 +362,16 @@ define Device/tplink_cpe610-v2 endef TARGET_DEVICES += tplink_cpe610-v2 +define Device/tplink_eap2x5_1port + $(Device/tplink-safeloader) + SOC := qca9563 + IMAGE_SIZE := 15104k + LOADER_TYPE := elf + KERNEL := kernel-bin | append-dtb | lzma | loader-kernel + KERNEL_INITRAMFS := $$(KERNEL) + IMAGE/factory.bin := append-rootfs | tplink-safeloader factory | pad-extra 128 +endef + define Device/tplink_eap245-v3 $(Device/tplink-safeloader) SOC := qca9563 From patchwork Fri Jul 17 11:37:38 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Sander Vanheule X-Patchwork-Id: 1331085 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; 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Fri, 17 Jul 2020 11:38:55 +0000 Received: from polaris.svanheule.net ([2a00:c98:2060:a004:1::200]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1jwOhR-0005D4-Nc for openwrt-devel@lists.openwrt.org; Fri, 17 Jul 2020 11:38:47 +0000 Received: from terra.local.svanheule.net (unknown [IPv6:2a02:a03f:5670:b301:1c6f:d128:905e:da70]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) (Authenticated sender: sander@svanheule.net) by polaris.svanheule.net (Postfix) with ESMTPSA id CD0231601B8; Fri, 17 Jul 2020 13:38:41 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=svanheule.net; s=mail1707; t=1594985922; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=0eluv3KPN+a68+NdYV+GLRQfFaCDcih+uEYG8WqF8Ho=; b=qJM45KYoFAe45WpkVeHw48vQwiu7ZP/jNCTeBG71jOy5zfjVzd3CToxUTkW+OurQvewY58 bWQeHyXeJrayC7ySNRjEWGZgp3+XLZ2JdC4YrIFe9E1dk7NOfVXTLBGRiy1odLlIlb7E0V fas3BG2onRJLSotLsKgo8EoN3hvjexuEGtV7yOjnoj5Ab4GjxR/tkb+8bbHRuozltEfzlr D327R22/8rkjXU3O616h2IUJScOv4ikyuZQtIRj6kiWyps81mCFkFotAzUpoBkv9PbRwx2 BH7xBLZxN4J/jdBEVdWbHWPnsrK1jEWYxzuwBIUOzOgGDDNl8CQvcbRkM/vhDw== From: Sander Vanheule To: openwrt-devel@lists.openwrt.org Subject: [RFC PATCH 5/7] ath79: support for TP-Link EAP245 v1 Date: Fri, 17 Jul 2020 13:37:38 +0200 Message-Id: X-Mailer: git-send-email 2.26.2 In-Reply-To: References: MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200717_073846_064623_490EDB9B X-CRM114-Status: GOOD ( 18.30 ) X-Spam-Score: -0.2 (/) X-Spam-Report: SpamAssassin version 3.4.4 on merlin.infradead.org summary: Content analysis details: (-0.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2a00:c98:2060:a004:1:0:0:200 listed in] [list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record -0.0 SPF_HELO_PASS SPF: HELO matches SPF record 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature X-BeenThere: openwrt-devel@lists.openwrt.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: OpenWrt Development List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Sander Vanheule , me@bibbl.com, julien.dusser@free.fr, john@phrozen.org, rafal@milecki.pl, ynezz@true.cz, mail@david-bauer.net Sender: "openwrt-devel" Errors-To: openwrt-devel-bounces+incoming=patchwork.ozlabs.org@lists.openwrt.org TP-Link EAP245 v1 is an AC1750 (802.11ac Wave-1) ceiling mount access point. Device specifications: * SoC: QCA9563 @ 775MHz * RAM: 128MiB DDR2 * Flash: 16MiB SPI-NOR * Wireless 2.4GHz (SoC): b/g/n, 3x3 * Wireless 5Ghz (QCA9880): a/n/ac, 3x3 * Ethernet (AR8033): 1× 1GbE, 803.2at PoE Flashing instructions: * Extract /usr/bin/uclited from the device via ssh and apply the binary patch listed below. The patch is required to prevent `uclited -u` in the last step from crashing. * Exploit the user management page in the web interface to start telnetd by changing the username to `;/usr/sbin/telnetd -l/bin/sh&`. * Immediately change the malformed username back to something valid (e.g. 'admin') to make ssh work again. * Use the root shell via telnet to make /tmp world writeable (chmod 777) * Copy the patched uclited programme back to the device at /tmp/uclited (via ssh) * Upload the factory image to /tmp/upgrade.bin (via ssh) * Run `chmod +x /tmp/uclited && /tmp/uclited -u` to flash OpenWrt. --- xxd uclited +++ xxd uclited-patched @@ -53796,7 +53796,7 @@ 000d2240: 8c44 0000 0320 f809 0000 0000 8fbc 0010 .D... .......... 000d2250: 8fa6 0a4c 02c0 2821 8f82 87b8 0000 0000 ...L..(!........ -000d2260: 8c44 0000 0c13 45e0 27a7 0018 8fbc 0010 .D....E.'....... +000d2260: 8c44 0000 2402 0000 0000 0000 8fbc 0010 .D..$........... 000d2270: 1040 001d 0000 1821 8f99 8374 3c04 0058 .@.....!...t<..X 000d2280: 3c05 0056 2484 a898 24a5 9a30 0320 f809 <..V$...$..0. .. Debricking: * Serial port can be soldered on PCB J3 (1: TXD, 2: RXD, 3: GND, 4: VCC) * Bridge unpopulated resistors R225 (TXD) and R237 (RXD). Do NOT bridge R230. * Use 3.3V, 115200 baud, 8n1 * Interrupt bootloader with by holding CTRL+B during boot * tftp initramfs to flash via Luci web-interface Tested on the EAP245v1 running the latest firmware (v1.4.0). The binary patch might not apply to uclited from other firmware versions. Signed-off-by: Sander Vanheule --- .../ath79/dts/qca9563_tplink_eap245-v1.dts | 26 +++++++++++++++++ .../generic/base-files/etc/board.d/02_network | 1 + .../etc/hotplug.d/firmware/11-ath10k-caldata | 3 +- target/linux/ath79/image/generic-tp-link.mk | 9 ++++++ tools/firmware-utils/src/tplink-safeloader.c | 28 +++++++++++++++++++ 5 files changed, 66 insertions(+), 1 deletion(-) create mode 100644 target/linux/ath79/dts/qca9563_tplink_eap245-v1.dts diff --git a/target/linux/ath79/dts/qca9563_tplink_eap245-v1.dts b/target/linux/ath79/dts/qca9563_tplink_eap245-v1.dts new file mode 100644 index 0000000000..8a11d2e469 --- /dev/null +++ b/target/linux/ath79/dts/qca9563_tplink_eap245-v1.dts @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/dts-v1/; + +#include + +#include "qca9563_tplink_eap2x5_1port.dtsi" + +/ { + compatible = "tplink,eap245-v1", "qca,qca9563"; + model = "TP-Link EAP245 v1"; +}; + +&led_status_green { + status = "okay"; + gpios = <&gpio 7 GPIO_ACTIVE_HIGH>; +}; + +&led_status_amber { + status = "okay"; + gpios = <&gpio 9 GPIO_ACTIVE_HIGH>; +}; + +&led_status_red { + status = "okay"; + gpios = <&gpio 1 GPIO_ACTIVE_HIGH>; +}; diff --git a/target/linux/ath79/generic/base-files/etc/board.d/02_network b/target/linux/ath79/generic/base-files/etc/board.d/02_network index 7524806d72..d19f885e27 100755 --- a/target/linux/ath79/generic/base-files/etc/board.d/02_network +++ b/target/linux/ath79/generic/base-files/etc/board.d/02_network @@ -38,6 +38,7 @@ ath79_setup_interfaces() pisen,wmb001n|\ pisen,wmm003n|\ siemens,ws-ap3610|\ + tplink,eap245-v1|\ tplink,cpe210-v2|\ tplink,cpe210-v3|\ tplink,cpe510-v2|\ diff --git a/target/linux/ath79/generic/base-files/etc/hotplug.d/firmware/11-ath10k-caldata b/target/linux/ath79/generic/base-files/etc/hotplug.d/firmware/11-ath10k-caldata index 2926796d65..d722f2dcaf 100644 --- a/target/linux/ath79/generic/base-files/etc/hotplug.d/firmware/11-ath10k-caldata +++ b/target/linux/ath79/generic/base-files/etc/hotplug.d/firmware/11-ath10k-caldata @@ -63,7 +63,8 @@ case "$FIRMWARE" in caldata_extract "art" 0x5000 0x844 ath10k_patch_mac $(macaddr_add $(mtd_get_mac_ascii u-boot-env ethaddr) +1) ;; - engenius,ews511ap) + engenius,ews511ap|\ + tplink,eap245-v1) caldata_extract "art" 0x5000 0x844 ath10k_patch_mac $(macaddr_add $(cat /sys/class/net/eth0/address) +1) ;; diff --git a/target/linux/ath79/image/generic-tp-link.mk b/target/linux/ath79/image/generic-tp-link.mk index d2cc8d09bd..a4a14ed889 100644 --- a/target/linux/ath79/image/generic-tp-link.mk +++ b/target/linux/ath79/image/generic-tp-link.mk @@ -372,6 +372,15 @@ define Device/tplink_eap2x5_1port IMAGE/factory.bin := append-rootfs | tplink-safeloader factory | pad-extra 128 endef +define Device/tplink_eap245-v1 + $(Device/tplink_eap2x5_1port) + DEVICE_MODEL := EAP245 + DEVICE_VARIANT := v1 + TPLINK_BOARD_ID := EAP245-V1 + DEVICE_PACKAGES := kmod-ath10k-ct ath10k-firmware-qca988x-ct +endef +TARGET_DEVICES += tplink_eap245-v1 + define Device/tplink_eap245-v3 $(Device/tplink-safeloader) SOC := qca9563 diff --git a/tools/firmware-utils/src/tplink-safeloader.c b/tools/firmware-utils/src/tplink-safeloader.c index e9e6f01ebd..a20304150b 100644 --- a/tools/firmware-utils/src/tplink-safeloader.c +++ b/tools/firmware-utils/src/tplink-safeloader.c @@ -1291,6 +1291,34 @@ static struct device_info boards[] = { .last_sysupgrade_partition = "file-system" }, + /** Firmware layout for the EAP245 v1 */ + { + .id = "EAP245-V1", + .support_list = + "SupportList:\r\n" + "EAP245(TP-LINK|UN|AC1750-D):1.0\r\n", + .support_trail = '\xff', + .soft_ver = NULL, + + .partitions = { + {"fs-uboot", 0x00000, 0x20000}, + {"partition-table", 0x20000, 0x02000}, + {"default-mac", 0x30000, 0x01000}, + {"support-list", 0x31000, 0x00100}, + {"product-info", 0x31100, 0x00400}, + {"soft-version", 0x32000, 0x00100}, + {"firmware", 0x40000, 0xc00000}, + {"user-config", 0xdc0000, 0x10000}, + {"backup-config", 0xdd0000, 0x10000}, + {"log", 0xde0000, 0x10000}, + {"radio", 0xff0000, 0x10000}, + {NULL, 0, 0} + }, + + .first_sysupgrade_partition = "os-image", + .last_sysupgrade_partition = "file-system" + }, + /** Firmware layout for the EAP245 v3 */ { .id = "EAP245-V3", From patchwork Fri Jul 17 11:37:39 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Sander Vanheule X-Patchwork-Id: 1331081 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.openwrt.org (client-ip=2001:8b0:10b:1231::1; helo=merlin.infradead.org; envelope-from=openwrt-devel-bounces+incoming=patchwork.ozlabs.org@lists.openwrt.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=svanheule.net Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; secure) header.d=lists.infradead.org header.i=@lists.infradead.org header.a=rsa-sha256 header.s=merlin.20170209 header.b=jOMCEKbA; dkim=fail reason="signature verification failed" (2048-bit key; secure) header.d=svanheule.net header.i=@svanheule.net header.a=rsa-sha256 header.s=mail1707 header.b=T5vYBFNW; dkim-atps=neutral Received: from merlin.infradead.org (merlin.infradead.org [IPv6:2001:8b0:10b:1231::1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4B7Th63Rplz9s1x for ; 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Fri, 17 Jul 2020 11:38:56 +0000 Received: from polaris.svanheule.net ([2a00:c98:2060:a004:1::200]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1jwOhS-0005D5-3s for openwrt-devel@lists.openwrt.org; Fri, 17 Jul 2020 11:38:48 +0000 Received: from terra.local.svanheule.net (unknown [IPv6:2a02:a03f:5670:b301:1c6f:d128:905e:da70]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) (Authenticated sender: sander@svanheule.net) by polaris.svanheule.net (Postfix) with ESMTPSA id D22571601BA; Fri, 17 Jul 2020 13:38:42 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=svanheule.net; s=mail1707; t=1594985923; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=Bb8fTVdhqxjX3yV+BAnVCxUZwK3p441dF62Zw+rqohM=; b=T5vYBFNWlAf1qjtSlEKogluYru4Q2R3GHer7DmqStZIIK4mgtA4okVLuj4ehtIn+/2D8/D aXQu1gYapq9RPmpexeI28AxINm2vFg1SgPgz+IPBwNNDzFTSJ6PzCloKwpN/w4kKmG2lzP XAzLlilBt2+LM9C48VR4CNa+6qeoMqG4EL5rGU4ImyumQ2Qr1Z6kBHiOogwbtnXQcGtpBT 6RTSSpViWdjFGOVr4AX5mdub5Rre7ZBEGBnxlGIXeig06A4W7+Py9jbTHPhSQK+JTj+N7g ZwB1nhUsUdRf8AUlzoQBNEz/rpn4WPUwLI7L1N7ozYM4oSLxkR7cmN/zpl9gXA== From: Sander Vanheule To: openwrt-devel@lists.openwrt.org Subject: [RFC PATCH 6/7] ath79: support for TP-Link EAP225-Outdoor v1 Date: Fri, 17 Jul 2020 13:37:39 +0200 Message-Id: X-Mailer: git-send-email 2.26.2 In-Reply-To: References: MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200717_073846_414991_E18F2391 X-CRM114-Status: GOOD ( 15.31 ) X-Spam-Score: -0.2 (/) X-Spam-Report: SpamAssassin version 3.4.4 on merlin.infradead.org summary: Content analysis details: (-0.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2a00:c98:2060:a004:1:0:0:200 listed in] [list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record -0.0 SPF_HELO_PASS SPF: HELO matches SPF record 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature X-BeenThere: openwrt-devel@lists.openwrt.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: OpenWrt Development List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Sander Vanheule , me@bibbl.com, julien.dusser@free.fr, john@phrozen.org, rafal@milecki.pl, ynezz@true.cz, mail@david-bauer.net Sender: "openwrt-devel" Errors-To: openwrt-devel-bounces+incoming=patchwork.ozlabs.org@lists.openwrt.org TP-Link EAP225-Outdoor v1 is an AC1200 (802.11ac Wave-2) pole or wall mount access point. Device specifications: * SoC: QCA9563 @ 775MHz * Memory: 128MiB DDR2 * Flash: 16MiB SPI-NOR * Wireless 2.4GHz (SoC): b/g/n 2x2 * Wireless 5GHz (QCA9886): a/n/ac 2x2 MU-MIMO * Ethernet (AR8033): 1× 1GbE, PoE Flashing instructions: * ssh into target device with recent (>= v1.6.0) firmware * run `cliclientd stopcs` on target device * upload factory image via web interface MAC addresses: MAC address (as on device label) is stored in device info partition at an offset of 8 bytes. ath9k device has same address as ethernet, ath10k uses address incremented by 1. From stock ifconfig: ath0 Link encap:Ethernet HWaddr D8:...:2E ath10 Link encap:Ethernet HWaddr D8:...:2F br0 Link encap:Ethernet HWaddr D8:...:2E eth0 Link encap:Ethernet HWaddr D8:...:2E Tested by forum user PolynomialDivision on firmware v1.7.0. Signed-off-by: Sander Vanheule --- .../ath79/dts/qca9563_tplink_eap225od-v1.dts | 21 ++++++++++++++ .../generic/base-files/etc/board.d/02_network | 1 + .../etc/hotplug.d/firmware/11-ath10k-caldata | 6 ++++ target/linux/ath79/image/generic-tp-link.mk | 10 +++++++ tools/firmware-utils/src/tplink-safeloader.c | 29 +++++++++++++++++++ 5 files changed, 67 insertions(+) create mode 100644 target/linux/ath79/dts/qca9563_tplink_eap225od-v1.dts diff --git a/target/linux/ath79/dts/qca9563_tplink_eap225od-v1.dts b/target/linux/ath79/dts/qca9563_tplink_eap225od-v1.dts new file mode 100644 index 0000000000..dcfdb7e524 --- /dev/null +++ b/target/linux/ath79/dts/qca9563_tplink_eap225od-v1.dts @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/dts-v1/; + +#include + +#include "qca9563_tplink_eap2x5_1port.dtsi" + +/ { + compatible = "tplink,eap225od-v1", "qca,qca9563"; + model = "TP-Link EAP225-Outdoor v1"; +}; + +&led_status_green { + status = "okay"; + gpios = <&gpio 7 GPIO_ACTIVE_LOW>; +}; + +&led_status_amber { + status = "okay"; + gpios = <&gpio 9 GPIO_ACTIVE_LOW>; +}; diff --git a/target/linux/ath79/generic/base-files/etc/board.d/02_network b/target/linux/ath79/generic/base-files/etc/board.d/02_network index d19f885e27..9bcee6da0e 100755 --- a/target/linux/ath79/generic/base-files/etc/board.d/02_network +++ b/target/linux/ath79/generic/base-files/etc/board.d/02_network @@ -38,6 +38,7 @@ ath79_setup_interfaces() pisen,wmb001n|\ pisen,wmm003n|\ siemens,ws-ap3610|\ + tplink,eap225od-v1|\ tplink,eap245-v1|\ tplink,cpe210-v2|\ tplink,cpe210-v3|\ diff --git a/target/linux/ath79/generic/base-files/etc/hotplug.d/firmware/11-ath10k-caldata b/target/linux/ath79/generic/base-files/etc/hotplug.d/firmware/11-ath10k-caldata index d722f2dcaf..b964c302d5 100644 --- a/target/linux/ath79/generic/base-files/etc/hotplug.d/firmware/11-ath10k-caldata +++ b/target/linux/ath79/generic/base-files/etc/hotplug.d/firmware/11-ath10k-caldata @@ -194,6 +194,12 @@ case "$FIRMWARE" in ln -sf /lib/firmware/ath10k/pre-cal-pci-0000\:00\:00.0.bin \ /lib/firmware/ath10k/QCA9888/hw2.0/board.bin ;; + tplink,eap225od-v1) + caldata_extract "art" 0x5000 0x2f20 + ath10k_patch_mac $(macaddr_add $(mtd_get_mac_binary info 0x8) +1) + ln -sf /lib/firmware/ath10k/pre-cal-pci-0000\:00\:00.0.bin \ + /lib/firmware/ath10k/QCA9888/hw2.0/board.bin + ;; tplink,eap245-v3) caldata_extract "art" 0x5000 0x2f20 ath10k_patch_mac $(macaddr_add $(mtd_get_mac_binary info 0x8) +1) diff --git a/target/linux/ath79/image/generic-tp-link.mk b/target/linux/ath79/image/generic-tp-link.mk index a4a14ed889..9ac24908fe 100644 --- a/target/linux/ath79/image/generic-tp-link.mk +++ b/target/linux/ath79/image/generic-tp-link.mk @@ -372,6 +372,16 @@ define Device/tplink_eap2x5_1port IMAGE/factory.bin := append-rootfs | tplink-safeloader factory | pad-extra 128 endef +define Device/tplink_eap225od-v1 + $(Device/tplink_eap2x5_1port) + DEVICE_MODEL := EAP225-Outdoor + DEVICE_VARIANT := v1 + TPLINK_BOARD_ID := EAP225OD-V1 + DEVICE_PACKAGES := kmod-ath10k-ct ath10k-firmware-qca9888-ct +endef +TARGET_DEVICES += tplink_eap225od-v1 + define Device/tplink_eap245-v1 $(Device/tplink_eap2x5_1port) DEVICE_MODEL := EAP245 diff --git a/tools/firmware-utils/src/tplink-safeloader.c b/tools/firmware-utils/src/tplink-safeloader.c index a20304150b..e38729eb8a 100644 --- a/tools/firmware-utils/src/tplink-safeloader.c +++ b/tools/firmware-utils/src/tplink-safeloader.c @@ -1291,6 +1291,35 @@ static struct device_info boards[] = { .last_sysupgrade_partition = "file-system" }, + /** Firmware layout for the EAP225-Outdoor v1 */ + { + .id = "EAP225OD-V1", + .support_list = + "SupportList:\r\n" + "EAP225-Outdoor(TP-Link|UN|AC1200-D):1.0\r\n", + .support_trail = '\xff', + .soft_ver = NULL, + .soft_ver_compat_level = 1, + + .partitions = { + {"fs-uboot", 0x00000, 0x20000}, + {"partition-table", 0x20000, 0x02000}, + {"default-mac", 0x30000, 0x01000}, + {"support-list", 0x31000, 0x00100}, + {"product-info", 0x31100, 0x00400}, + {"soft-version", 0x32000, 0x00100}, + {"firmware", 0x40000, 0xd80000}, + {"user-config", 0xdc0000, 0x10000}, + {"mutil-log", 0xf30000, 0x80000}, + {"oops", 0xfb0000, 0x40000}, + {"radio", 0xff0000, 0x10000}, + {NULL, 0, 0} + }, + + .first_sysupgrade_partition = "os-image", + .last_sysupgrade_partition = "file-system" + }, + /** Firmware layout for the EAP245 v1 */ { .id = "EAP245-V1", From patchwork Fri Jul 17 11:37:40 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Sander Vanheule X-Patchwork-Id: 1331084 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.openwrt.org (client-ip=2001:8b0:10b:1231::1; helo=merlin.infradead.org; envelope-from=openwrt-devel-bounces+incoming=patchwork.ozlabs.org@lists.openwrt.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=svanheule.net Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; secure) header.d=lists.infradead.org header.i=@lists.infradead.org header.a=rsa-sha256 header.s=merlin.20170209 header.b=Za33ZJEN; dkim=fail reason="signature verification failed" (2048-bit key; secure) header.d=svanheule.net header.i=@svanheule.net header.a=rsa-sha256 header.s=mail1707 header.b=53izh6z0; dkim-atps=neutral Received: from merlin.infradead.org (merlin.infradead.org [IPv6:2001:8b0:10b:1231::1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4B7ThD3D4pz9s1x for ; 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Fri, 17 Jul 2020 11:38:57 +0000 Received: from polaris.svanheule.net ([2a00:c98:2060:a004:1::200]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1jwOhS-0005DB-Jy for openwrt-devel@lists.openwrt.org; Fri, 17 Jul 2020 11:38:48 +0000 Received: from terra.local.svanheule.net (unknown [IPv6:2a02:a03f:5670:b301:1c6f:d128:905e:da70]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) (Authenticated sender: sander@svanheule.net) by polaris.svanheule.net (Postfix) with ESMTPSA id E80861601BB; Fri, 17 Jul 2020 13:38:43 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=svanheule.net; s=mail1707; t=1594985924; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=1lUMbPguJjNzh2E/bGFTrQrMMfg4DO3ObwqsewceIL0=; b=53izh6z0DwXsZJHl/xhYF4T+NQ7gzJ5UtY2sNh29RpreOLuW8Eyas0WjGVK8aQV6CYHHpp l9EO0vC9UViTSIMj6kuGMmu8CTUjVlNwiBGm+/HX3iqecUq4UCxP+IPCPhhUZ1C3jzBTnk ep3UDXZLkiisGiNPM8WrI0d5pn0NLHCjnGhvvglMU8fzr0KLnUhGJm0jaCNyFH/3C3a7wb 0KQqD1hBEAMpAzJm43WP88DIzvEobim+yM/l+yzp4A3ptemdgK1/H/0f11XE/mx/FoETPr WobAZFlLabOX6jKshmJZ0OH5QpEMVNQ3UUyl38dYvQp7p4xPxireJWahc+t+jg== From: Sander Vanheule To: openwrt-devel@lists.openwrt.org Subject: [RFC PATCH 7/7] ath79: support for TP-Link EAP225 v3 Date: Fri, 17 Jul 2020 13:37:40 +0200 Message-Id: <759c769dcbb9b737538c276d4f88a488afd21667.1594981871.git.sander@svanheule.net> X-Mailer: git-send-email 2.26.2 In-Reply-To: References: MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200717_073846_947707_9C7647FA X-CRM114-Status: GOOD ( 14.83 ) X-Spam-Score: -0.2 (/) X-Spam-Report: SpamAssassin version 3.4.4 on merlin.infradead.org summary: Content analysis details: (-0.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2a00:c98:2060:a004:1:0:0:200 listed in] [list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record -0.0 SPF_HELO_PASS SPF: HELO matches SPF record 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature X-BeenThere: openwrt-devel@lists.openwrt.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: OpenWrt Development List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Sander Vanheule , me@bibbl.com, julien.dusser@free.fr, john@phrozen.org, rafal@milecki.pl, ynezz@true.cz, mail@david-bauer.net Sender: "openwrt-devel" Errors-To: openwrt-devel-bounces+incoming=patchwork.ozlabs.org@lists.openwrt.org TP-Link EAP225 v3 is an AC1350 (802.11ac Wave-2) ceiling mount access point. Device specifications: * SoC: QCA9563 @ 775MHz * RAM: 128MiB DDR2 * Flash: 16MiB SPI-NOR * Wireless 2.4GHz (SoC): b/g/n, 3x3 * Wireless 5Ghz (QCA9886): a/n/ac, 2x2 MU-MINO * Ethernet (AR8033): 1× 1GbE, 803.2at PoE Flashing instructions: * ssh into target device and run `cliclientd stopcs` * Upgrade with factory image via web interface Debricking: * Serial port can be soldered on PCB J3 (1: TXD, 2: RXD, 3: GND, 4: VCC) * Bridge unpopulated resistors R225 (TXD) and R237 (RXD). Do NOT bridge R230. * Use 3.3V, 115200 baud, 8n1 * Interrupt bootloader with by holding CTRL+B during boot * tftp initramfs to flash via Luci web-interface MAC addresses: MAC address (as on device label) is stored in device info partition at an offset of 8 bytes. ath9k device has same address as ethernet, ath10k uses address incremented by 1. From OEM boot log: Using interface ath0 with hwaddr b0:...:3e and ssid "..." Using interface ath10 with hwaddr b0:...:3f and ssid "..." Tested by forum user blinkstar88 Signed-off-by: Sander Vanheule --- .../ath79/dts/qca9563_tplink_eap225-v3.dts | 21 ++++++++++++++ .../generic/base-files/etc/board.d/02_network | 1 + .../etc/hotplug.d/firmware/11-ath10k-caldata | 1 + target/linux/ath79/image/generic-tp-link.mk | 9 ++++++ tools/firmware-utils/src/tplink-safeloader.c | 28 +++++++++++++++++++ 5 files changed, 60 insertions(+) create mode 100644 target/linux/ath79/dts/qca9563_tplink_eap225-v3.dts diff --git a/target/linux/ath79/dts/qca9563_tplink_eap225-v3.dts b/target/linux/ath79/dts/qca9563_tplink_eap225-v3.dts new file mode 100644 index 0000000000..391494b8dc --- /dev/null +++ b/target/linux/ath79/dts/qca9563_tplink_eap225-v3.dts @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/dts-v1/; + +#include + +#include "qca9563_tplink_eap2x5_1port.dtsi" + +/ { + compatible = "tplink,eap225-v3", "qca,qca9563"; + model = "TP-Link EAP225 v3"; +}; + +&led_status_green { + status = "okay"; + gpios = <&gpio 7 GPIO_ACTIVE_HIGH>; +}; + +&led_status_amber { + status = "okay"; + gpios = <&gpio 9 GPIO_ACTIVE_HIGH>; +}; diff --git a/target/linux/ath79/generic/base-files/etc/board.d/02_network b/target/linux/ath79/generic/base-files/etc/board.d/02_network index 9bcee6da0e..2b11c00abb 100755 --- a/target/linux/ath79/generic/base-files/etc/board.d/02_network +++ b/target/linux/ath79/generic/base-files/etc/board.d/02_network @@ -38,6 +38,7 @@ ath79_setup_interfaces() pisen,wmb001n|\ pisen,wmm003n|\ siemens,ws-ap3610|\ + tplink,eap225-v3|\ tplink,eap225od-v1|\ tplink,eap245-v1|\ tplink,cpe210-v2|\ diff --git a/target/linux/ath79/generic/base-files/etc/hotplug.d/firmware/11-ath10k-caldata b/target/linux/ath79/generic/base-files/etc/hotplug.d/firmware/11-ath10k-caldata index b964c302d5..a3992d02b8 100644 --- a/target/linux/ath79/generic/base-files/etc/hotplug.d/firmware/11-ath10k-caldata +++ b/target/linux/ath79/generic/base-files/etc/hotplug.d/firmware/11-ath10k-caldata @@ -194,6 +194,7 @@ case "$FIRMWARE" in ln -sf /lib/firmware/ath10k/pre-cal-pci-0000\:00\:00.0.bin \ /lib/firmware/ath10k/QCA9888/hw2.0/board.bin ;; + tplink,eap225-v3|\ tplink,eap225od-v1) caldata_extract "art" 0x5000 0x2f20 ath10k_patch_mac $(macaddr_add $(mtd_get_mac_binary info 0x8) +1) diff --git a/target/linux/ath79/image/generic-tp-link.mk b/target/linux/ath79/image/generic-tp-link.mk index 9ac24908fe..70d62f5287 100644 --- a/target/linux/ath79/image/generic-tp-link.mk +++ b/target/linux/ath79/image/generic-tp-link.mk @@ -372,6 +372,15 @@ define Device/tplink_eap2x5_1port IMAGE/factory.bin := append-rootfs | tplink-safeloader factory | pad-extra 128 endef +define Device/tplink_eap225-v3 + $(Device/tplink_eap2x5_1port) + DEVICE_MODEL := EAP225 + DEVICE_VARIANT := v3 + TPLINK_BOARD_ID := EAP225-V3 + DEVICE_PACKAGES := kmod-ath10k-ct ath10k-firmware-qca9888-ct +endef +TARGET_DEVICES += tplink_eap225-v3 + define Device/tplink_eap225od-v1 $(Device/tplink_eap2x5_1port) DEVICE_MODEL := EAP225-Outdoor diff --git a/tools/firmware-utils/src/tplink-safeloader.c b/tools/firmware-utils/src/tplink-safeloader.c index e38729eb8a..c4b9dd7865 100644 --- a/tools/firmware-utils/src/tplink-safeloader.c +++ b/tools/firmware-utils/src/tplink-safeloader.c @@ -1291,6 +1291,34 @@ static struct device_info boards[] = { .last_sysupgrade_partition = "file-system" }, + /** Firmware layout for the EAP225 v3 */ + { + .id = "EAP225-V3", + .support_list = + "SupportList:\r\n" + "EAP225(TP-Link|UN|AC1350-D):3.0\r\n", + .soft_ver = NULL, + .soft_ver_compat_level = 1, + + .partitions = { + {"fs-uboot", 0x00000, 0x20000}, + {"partition-table", 0x20000, 0x02000}, + {"default-mac", 0x30000, 0x01000}, + {"support-list", 0x31000, 0x00100}, + {"product-info", 0x31100, 0x00400}, + {"soft-version", 0x32000, 0x00100}, + {"firmware", 0x40000, 0xd80000}, + {"user-config", 0xdc0000, 0x30000}, + {"mutil-log", 0xf30000, 0x80000}, + {"oops", 0xfb0000, 0x40000}, + {"radio", 0xff0000, 0x10000}, + {NULL, 0, 0} + }, + + .first_sysupgrade_partition = "os-image", + .last_sysupgrade_partition = "file-system" + }, + /** Firmware layout for the EAP225-Outdoor v1 */ { .id = "EAP225OD-V1",