From patchwork Wed Jul 15 15:48:33 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Igor Russkikh X-Patchwork-Id: 1329651 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: patchwork-incoming-netdev@ozlabs.org Delivered-To: patchwork-incoming-netdev@ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=netdev-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=marvell.com Authentication-Results: ozlabs.org; dkim=fail reason="key not found in DNS" header.d=marvell.com header.i=@marvell.com header.a=rsa-sha256 header.s=pfpt0818 header.b=WLx2aa4n; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4B6MJY4ZCFz9sRK for ; Thu, 16 Jul 2020 01:49:33 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727916AbgGOPtc (ORCPT ); Wed, 15 Jul 2020 11:49:32 -0400 Received: from mx0a-0016f401.pphosted.com ([67.231.148.174]:61606 "EHLO mx0b-0016f401.pphosted.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1727043AbgGOPtC (ORCPT ); Wed, 15 Jul 2020 11:49:02 -0400 Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id 06FFf123032713; Wed, 15 Jul 2020 08:49:01 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=pfpt0818; bh=pE/yc1u9tbBnLpY8dDHGbLYSYG7E7GuM8aEpfRg5vG8=; b=WLx2aa4nCoSXblDSJ2stQgiOyACLI9F9oQIRzzAylg0qn8H+lGRH4xWKUUbWnhKxC0l9 PW2Kqdhp87AqCNPtQ4Q8PKHSQC9salydczxfHr4TskjrbhRsD/G1/y4htbS747evPZrb FCDKSitCkvV65RwNIpLPMbj4zZZ0avqFTGgjHJAqK21xE3g6fjXhfFqFW2xDz/4WFLg9 5mpeQeAuOmxDp4tsORzwUrSml8H0ps/MWTKRAHYOWeHLkoSFkQcTtsWbSAvvKa8CNZtR U9ZW82S1KDIZ03OsUYMvO9IMlbDufd019FaY+nz8Zg9msPynA26Q89FVVwVmNkViFYPq dw== Received: from sc-exch04.marvell.com ([199.233.58.184]) by mx0a-0016f401.pphosted.com with ESMTP id 327asnja56-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Wed, 15 Jul 2020 08:49:01 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by SC-EXCH04.marvell.com (10.93.176.84) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 15 Jul 2020 08:49:00 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 15 Jul 2020 08:49:00 -0700 Received: from NN-LT0019.marvell.com (NN-LT0019.marvell.com [10.193.54.28]) by maili.marvell.com (Postfix) with ESMTP id 7C92D3F703F; Wed, 15 Jul 2020 08:48:58 -0700 (PDT) From: Igor Russkikh To: CC: "David S . Miller" , Mark Starovoytov , Jakub Kicinski , Igor Russkikh Subject: [PATCH v2 net-next 01/10] net: atlantic: move FRAC_PER_NS to aq_hw.h Date: Wed, 15 Jul 2020 18:48:33 +0300 Message-ID: <20200715154842.305-2-irusskikh@marvell.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200715154842.305-1-irusskikh@marvell.com> References: <20200715154842.305-1-irusskikh@marvell.com> MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.235,18.0.687 definitions=2020-07-15_12:2020-07-15,2020-07-15 signatures=0 Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org From: Mark Starovoytov This patch moves FRAC_PER_NS to aq_hw.h so that it can be used in both hw_atl (A1) and hw_atl2 (A2) in the future. Signed-off-by: Mark Starovoytov Signed-off-by: Igor Russkikh --- .../net/ethernet/aquantia/atlantic/aq_hw.h | 2 ++ .../aquantia/atlantic/hw_atl/hw_atl_b0.c | 20 +++++++++---------- 2 files changed, 11 insertions(+), 11 deletions(-) diff --git a/drivers/net/ethernet/aquantia/atlantic/aq_hw.h b/drivers/net/ethernet/aquantia/atlantic/aq_hw.h index f2663ad22209..284ea943e8cd 100644 --- a/drivers/net/ethernet/aquantia/atlantic/aq_hw.h +++ b/drivers/net/ethernet/aquantia/atlantic/aq_hw.h @@ -36,6 +36,8 @@ enum aq_tc_mode { (AQ_RX_LAST_LOC_FVLANID - AQ_RX_FIRST_LOC_FVLANID + 1U) #define AQ_RX_QUEUE_NOT_ASSIGNED 0xFFU +#define AQ_FRAC_PER_NS 0x100000000LL + /* Used for rate to Mbps conversion */ #define AQ_MBPS_DIVISOR 125000 /* 1000000 / 8 */ diff --git a/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_b0.c b/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_b0.c index b023c3324a59..97672ff142a8 100644 --- a/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_b0.c +++ b/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_b0.c @@ -54,8 +54,6 @@ .mac_regs_count = 88, \ .hw_alive_check_addr = 0x10U -#define FRAC_PER_NS 0x100000000LL - const struct aq_hw_caps_s hw_atl_b0_caps_aqc100 = { DEFAULT_B0_BOARD_BASIC_CAPABILITIES, .media_type = AQ_HW_MEDIA_TYPE_FIBRE, @@ -1233,7 +1231,7 @@ static void hw_atl_b0_adj_params_get(u64 freq, s64 adj, u32 *ns, u32 *fns) if (base_ns != nsi * NSEC_PER_SEC) { s64 divisor = div64_s64((s64)NSEC_PER_SEC * NSEC_PER_SEC, base_ns - nsi * NSEC_PER_SEC); - nsi_frac = div64_s64(FRAC_PER_NS * NSEC_PER_SEC, divisor); + nsi_frac = div64_s64(AQ_FRAC_PER_NS * NSEC_PER_SEC, divisor); } *ns = (u32)nsi; @@ -1246,23 +1244,23 @@ hw_atl_b0_mac_adj_param_calc(struct hw_fw_request_ptp_adj_freq *ptp_adj_freq, { s64 adj_fns_val; s64 fns_in_sec_phy = phyfreq * (ptp_adj_freq->fns_phy + - FRAC_PER_NS * ptp_adj_freq->ns_phy); + AQ_FRAC_PER_NS * ptp_adj_freq->ns_phy); s64 fns_in_sec_mac = macfreq * (ptp_adj_freq->fns_mac + - FRAC_PER_NS * ptp_adj_freq->ns_mac); - s64 fault_in_sec_phy = FRAC_PER_NS * NSEC_PER_SEC - fns_in_sec_phy; - s64 fault_in_sec_mac = FRAC_PER_NS * NSEC_PER_SEC - fns_in_sec_mac; + AQ_FRAC_PER_NS * ptp_adj_freq->ns_mac); + s64 fault_in_sec_phy = AQ_FRAC_PER_NS * NSEC_PER_SEC - fns_in_sec_phy; + s64 fault_in_sec_mac = AQ_FRAC_PER_NS * NSEC_PER_SEC - fns_in_sec_mac; /* MAC MCP counter freq is macfreq / 4 */ s64 diff_in_mcp_overflow = (fault_in_sec_mac - fault_in_sec_phy) * - 4 * FRAC_PER_NS; + 4 * AQ_FRAC_PER_NS; diff_in_mcp_overflow = div64_s64(diff_in_mcp_overflow, AQ_HW_MAC_COUNTER_HZ); - adj_fns_val = (ptp_adj_freq->fns_mac + FRAC_PER_NS * + adj_fns_val = (ptp_adj_freq->fns_mac + AQ_FRAC_PER_NS * ptp_adj_freq->ns_mac) + diff_in_mcp_overflow; - ptp_adj_freq->mac_ns_adj = div64_s64(adj_fns_val, FRAC_PER_NS); + ptp_adj_freq->mac_ns_adj = div64_s64(adj_fns_val, AQ_FRAC_PER_NS); ptp_adj_freq->mac_fns_adj = adj_fns_val - ptp_adj_freq->mac_ns_adj * - FRAC_PER_NS; + AQ_FRAC_PER_NS; } static int hw_atl_b0_adj_sys_clock(struct aq_hw_s *self, s64 delta) From patchwork Wed Jul 15 15:48:34 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Igor Russkikh X-Patchwork-Id: 1329649 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: patchwork-incoming-netdev@ozlabs.org Delivered-To: patchwork-incoming-netdev@ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=netdev-owner@vger.kernel.org; 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Wed, 15 Jul 2020 08:49:02 -0700 Received: from NN-LT0019.marvell.com (NN-LT0019.marvell.com [10.193.54.28]) by maili.marvell.com (Postfix) with ESMTP id 96D8D3F704B; Wed, 15 Jul 2020 08:49:00 -0700 (PDT) From: Igor Russkikh To: CC: "David S . Miller" , Mark Starovoytov , Jakub Kicinski , Dmitry Bogdanov , Igor Russkikh Subject: [PATCH v2 net-next 02/10] net: atlantic: additional per-queue stats Date: Wed, 15 Jul 2020 18:48:34 +0300 Message-ID: <20200715154842.305-3-irusskikh@marvell.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200715154842.305-1-irusskikh@marvell.com> References: <20200715154842.305-1-irusskikh@marvell.com> MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.235,18.0.687 definitions=2020-07-15_12:2020-07-15,2020-07-15 signatures=0 Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org From: Dmitry Bogdanov This patch adds additional per-queue stats, these could be useful for debugging and diagnostics. Signed-off-by: Dmitry Bogdanov Signed-off-by: Mark Starovoytov Signed-off-by: Igor Russkikh --- .../ethernet/aquantia/atlantic/aq_ethtool.c | 3 ++ .../net/ethernet/aquantia/atlantic/aq_nic.c | 42 ++++++++++++++++- .../net/ethernet/aquantia/atlantic/aq_nic.h | 6 +++ .../net/ethernet/aquantia/atlantic/aq_ring.c | 4 ++ .../net/ethernet/aquantia/atlantic/aq_ring.h | 10 ++-- .../net/ethernet/aquantia/atlantic/aq_vec.c | 46 +++++-------------- .../net/ethernet/aquantia/atlantic/aq_vec.h | 14 ++++-- 7 files changed, 81 insertions(+), 44 deletions(-) diff --git a/drivers/net/ethernet/aquantia/atlantic/aq_ethtool.c b/drivers/net/ethernet/aquantia/atlantic/aq_ethtool.c index a8f0fbbbd91a..420fa5b791f9 100644 --- a/drivers/net/ethernet/aquantia/atlantic/aq_ethtool.c +++ b/drivers/net/ethernet/aquantia/atlantic/aq_ethtool.c @@ -96,6 +96,9 @@ static const char * const aq_ethtool_queue_stat_names[] = { "%sQueue[%d] InJumboPackets", "%sQueue[%d] InLroPackets", "%sQueue[%d] InErrors", + "%sQueue[%d] AllocFails", + "%sQueue[%d] SkbAllocFails", + "%sQueue[%d] Polls", }; #if IS_ENABLED(CONFIG_MACSEC) diff --git a/drivers/net/ethernet/aquantia/atlantic/aq_nic.c b/drivers/net/ethernet/aquantia/atlantic/aq_nic.c index 43b8914c3ef5..45d99c1a9635 100644 --- a/drivers/net/ethernet/aquantia/atlantic/aq_nic.c +++ b/drivers/net/ethernet/aquantia/atlantic/aq_nic.c @@ -857,6 +857,20 @@ int aq_nic_get_regs_count(struct aq_nic_s *self) return self->aq_nic_cfg.aq_hw_caps->mac_regs_count; } +static int aq_nic_get_tc_stats(struct aq_vec_s *vec, const unsigned int tc, + u64 *data, unsigned int *p_count) +{ + struct aq_ring_stats_rx_s stats_rx; + struct aq_ring_stats_tx_s stats_tx; + + memset(&stats_rx, 0U, sizeof(struct aq_ring_stats_rx_s)); + memset(&stats_tx, 0U, sizeof(struct aq_ring_stats_tx_s)); + + aq_vec_add_stats(vec, tc, &stats_rx, &stats_tx); + + return aq_nic_fill_stats_data(&stats_rx, &stats_tx, data, p_count); +} + u64 *aq_nic_get_stats(struct aq_nic_s *self, u64 *data) { struct aq_vec_s *aq_vec = NULL; @@ -907,13 +921,13 @@ u64 *aq_nic_get_stats(struct aq_nic_s *self, u64 *data) aq_vec && self->aq_vecs > i; ++i, aq_vec = self->aq_vec[i]) { data += count; - aq_vec_get_sw_stats(aq_vec, tc, data, &count); + aq_nic_get_tc_stats(aq_vec, tc, data, &count); } } data += count; -err_exit:; +err_exit: return data; } @@ -932,6 +946,30 @@ static void aq_nic_update_ndev_stats(struct aq_nic_s *self) ndev->stats.multicast = stats->mprc; } +int aq_nic_fill_stats_data(struct aq_ring_stats_rx_s *stats_rx, + struct aq_ring_stats_tx_s *stats_tx, + u64 *data, + unsigned int *p_count) +{ + unsigned int count = 0U; + /* This data should mimic aq_ethtool_queue_stat_names structure + */ + data[count] += stats_rx->packets; + data[++count] += stats_tx->packets; + data[++count] += stats_tx->queue_restarts; + data[++count] += stats_rx->jumbo_packets; + data[++count] += stats_rx->lro_packets; + data[++count] += stats_rx->errors; + data[++count] += stats_rx->alloc_fails; + data[++count] += stats_rx->skb_alloc_fails; + data[++count] += stats_rx->polls; + + if (p_count) + *p_count = ++count; + + return 0; +} + void aq_nic_get_link_ksettings(struct aq_nic_s *self, struct ethtool_link_ksettings *cmd) { diff --git a/drivers/net/ethernet/aquantia/atlantic/aq_nic.h b/drivers/net/ethernet/aquantia/atlantic/aq_nic.h index 317bfc646f0a..0c7233d8ecd6 100644 --- a/drivers/net/ethernet/aquantia/atlantic/aq_nic.h +++ b/drivers/net/ethernet/aquantia/atlantic/aq_nic.h @@ -15,6 +15,8 @@ #include "aq_hw.h" struct aq_ring_s; +struct aq_ring_stats_rx_s; +struct aq_ring_stats_tx_s; struct aq_hw_ops; struct aq_fw_s; struct aq_vec_s; @@ -175,6 +177,10 @@ int aq_nic_xmit(struct aq_nic_s *self, struct sk_buff *skb); int aq_nic_get_regs(struct aq_nic_s *self, struct ethtool_regs *regs, void *p); int aq_nic_get_regs_count(struct aq_nic_s *self); u64 *aq_nic_get_stats(struct aq_nic_s *self, u64 *data); +int aq_nic_fill_stats_data(struct aq_ring_stats_rx_s *stats_rx, + struct aq_ring_stats_tx_s *stats_tx, + u64 *data, + unsigned int *p_count); int aq_nic_stop(struct aq_nic_s *self); void aq_nic_deinit(struct aq_nic_s *self, bool link_down); void aq_nic_set_power(struct aq_nic_s *self); diff --git a/drivers/net/ethernet/aquantia/atlantic/aq_ring.c b/drivers/net/ethernet/aquantia/atlantic/aq_ring.c index 8dd59e9fc3aa..20b606aa7974 100644 --- a/drivers/net/ethernet/aquantia/atlantic/aq_ring.c +++ b/drivers/net/ethernet/aquantia/atlantic/aq_ring.c @@ -88,6 +88,8 @@ static int aq_get_rxpages(struct aq_ring_s *self, struct aq_ring_buff_s *rxbuf, if (!rxbuf->rxdata.page) { ret = aq_get_rxpage(&rxbuf->rxdata, order, aq_nic_get_dev(self->aq_nic)); + if (ret) + self->stats.rx.alloc_fails++; return ret; } @@ -392,6 +394,7 @@ int aq_ring_rx_clean(struct aq_ring_s *self, skb = build_skb(aq_buf_vaddr(&buff->rxdata), AQ_CFG_RX_FRAME_MAX); if (unlikely(!skb)) { + self->stats.rx.skb_alloc_fails++; err = -ENOMEM; goto err_exit; } @@ -405,6 +408,7 @@ int aq_ring_rx_clean(struct aq_ring_s *self, } else { skb = napi_alloc_skb(napi, AQ_CFG_RX_HDR_SIZE); if (unlikely(!skb)) { + self->stats.rx.skb_alloc_fails++; err = -ENOMEM; goto err_exit; } diff --git a/drivers/net/ethernet/aquantia/atlantic/aq_ring.h b/drivers/net/ethernet/aquantia/atlantic/aq_ring.h index 2c96f20f6289..0e40ccbaf19a 100644 --- a/drivers/net/ethernet/aquantia/atlantic/aq_ring.h +++ b/drivers/net/ethernet/aquantia/atlantic/aq_ring.h @@ -1,7 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -/* - * aQuantia Corporation Network Driver - * Copyright (C) 2014-2019 aQuantia Corporation. All rights reserved +/* Atlantic Network Driver + * + * Copyright (C) 2014-2019 aQuantia Corporation + * Copyright (C) 2019-2020 Marvell International Ltd. */ /* File aq_ring.h: Declaration of functions for Rx/Tx rings. */ @@ -93,6 +94,9 @@ struct aq_ring_stats_rx_s { u64 bytes; u64 lro_packets; u64 jumbo_packets; + u64 alloc_fails; + u64 skb_alloc_fails; + u64 polls; u64 pg_losts; u64 pg_flips; u64 pg_reuses; diff --git a/drivers/net/ethernet/aquantia/atlantic/aq_vec.c b/drivers/net/ethernet/aquantia/atlantic/aq_vec.c index d1d43c8ce400..eafcb98c274f 100644 --- a/drivers/net/ethernet/aquantia/atlantic/aq_vec.c +++ b/drivers/net/ethernet/aquantia/atlantic/aq_vec.c @@ -1,7 +1,8 @@ // SPDX-License-Identifier: GPL-2.0-only -/* - * aQuantia Corporation Network Driver - * Copyright (C) 2014-2017 aQuantia Corporation. All rights reserved +/* Atlantic Network Driver + * + * Copyright (C) 2014-2019 aQuantia Corporation + * Copyright (C) 2019-2020 Marvell International Ltd. */ /* File aq_vec.c: Definition of common structure for vector of Rx and Tx rings. @@ -44,6 +45,7 @@ static int aq_vec_poll(struct napi_struct *napi, int budget) } else { for (i = 0U, ring = self->ring[0]; self->tx_rings > i; ++i, ring = self->ring[i]) { + ring[AQ_VEC_RX_ID].stats.rx.polls++; if (self->aq_hw_ops->hw_ring_tx_head_update) { err = self->aq_hw_ops->hw_ring_tx_head_update( self->aq_hw, @@ -349,10 +351,10 @@ cpumask_t *aq_vec_get_affinity_mask(struct aq_vec_s *self) return &self->aq_ring_param.affinity_mask; } -static void aq_vec_add_stats(struct aq_vec_s *self, - const unsigned int tc, - struct aq_ring_stats_rx_s *stats_rx, - struct aq_ring_stats_tx_s *stats_tx) +void aq_vec_add_stats(struct aq_vec_s *self, + const unsigned int tc, + struct aq_ring_stats_rx_s *stats_rx, + struct aq_ring_stats_tx_s *stats_tx) { struct aq_ring_s *ring = self->ring[tc]; @@ -364,6 +366,9 @@ static void aq_vec_add_stats(struct aq_vec_s *self, stats_rx->errors += rx->errors; stats_rx->jumbo_packets += rx->jumbo_packets; stats_rx->lro_packets += rx->lro_packets; + stats_rx->alloc_fails += rx->alloc_fails; + stats_rx->skb_alloc_fails += rx->skb_alloc_fails; + stats_rx->polls += rx->polls; stats_rx->pg_losts += rx->pg_losts; stats_rx->pg_flips += rx->pg_flips; stats_rx->pg_reuses += rx->pg_reuses; @@ -378,30 +383,3 @@ static void aq_vec_add_stats(struct aq_vec_s *self, stats_tx->queue_restarts += tx->queue_restarts; } } - -int aq_vec_get_sw_stats(struct aq_vec_s *self, const unsigned int tc, u64 *data, - unsigned int *p_count) -{ - struct aq_ring_stats_rx_s stats_rx; - struct aq_ring_stats_tx_s stats_tx; - unsigned int count = 0U; - - memset(&stats_rx, 0U, sizeof(struct aq_ring_stats_rx_s)); - memset(&stats_tx, 0U, sizeof(struct aq_ring_stats_tx_s)); - - aq_vec_add_stats(self, tc, &stats_rx, &stats_tx); - - /* This data should mimic aq_ethtool_queue_stat_names structure - */ - data[count] += stats_rx.packets; - data[++count] += stats_tx.packets; - data[++count] += stats_tx.queue_restarts; - data[++count] += stats_rx.jumbo_packets; - data[++count] += stats_rx.lro_packets; - data[++count] += stats_rx.errors; - - if (p_count) - *p_count = ++count; - - return 0; -} diff --git a/drivers/net/ethernet/aquantia/atlantic/aq_vec.h b/drivers/net/ethernet/aquantia/atlantic/aq_vec.h index 541af85e6510..876781a1e2b3 100644 --- a/drivers/net/ethernet/aquantia/atlantic/aq_vec.h +++ b/drivers/net/ethernet/aquantia/atlantic/aq_vec.h @@ -1,7 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -/* - * aQuantia Corporation Network Driver - * Copyright (C) 2014-2017 aQuantia Corporation. All rights reserved +/* Atlantic Network Driver + * + * Copyright (C) 2014-2019 aQuantia Corporation + * Copyright (C) 2019-2020 Marvell International Ltd. */ /* File aq_vec.h: Definition of common structures for vector of Rx and Tx rings. @@ -35,7 +36,10 @@ void aq_vec_ring_free(struct aq_vec_s *self); int aq_vec_start(struct aq_vec_s *self); void aq_vec_stop(struct aq_vec_s *self); cpumask_t *aq_vec_get_affinity_mask(struct aq_vec_s *self); -int aq_vec_get_sw_stats(struct aq_vec_s *self, const unsigned int tc, u64 *data, - unsigned int *p_count); + +void aq_vec_add_stats(struct aq_vec_s *self, + const unsigned int tc, + struct aq_ring_stats_rx_s *stats_rx, + struct aq_ring_stats_tx_s *stats_tx); #endif /* AQ_VEC_H */ From patchwork Wed Jul 15 15:48:35 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Igor Russkikh X-Patchwork-Id: 1329642 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: patchwork-incoming-netdev@ozlabs.org Delivered-To: patchwork-incoming-netdev@ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=netdev-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=marvell.com Authentication-Results: ozlabs.org; dkim=fail reason="key not found in DNS" header.d=marvell.com header.i=@marvell.com header.a=rsa-sha256 header.s=pfpt0818 header.b=rVhz2T6/; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4B6MJ71JRYz9sTM for ; Thu, 16 Jul 2020 01:49:11 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727837AbgGOPtK (ORCPT ); Wed, 15 Jul 2020 11:49:10 -0400 Received: from mx0a-0016f401.pphosted.com ([67.231.148.174]:45508 "EHLO mx0b-0016f401.pphosted.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1726929AbgGOPtI (ORCPT ); Wed, 15 Jul 2020 11:49:08 -0400 Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id 06FFf2DR032718; Wed, 15 Jul 2020 08:49:06 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=pfpt0818; bh=3hJp31Ls7U691tWmm9UMuHh0W+Hpjs8C4PDlLlj4p+M=; b=rVhz2T6/XlWspPl7VlBCQOXAJYpjtmaYNEMlOCPvwxwPUOlwNPzE8Tu8cQBP37oJ37Sr zASYWlYWPJrHw0TxxWJFF68aeu324ZAa7bkaJ0r0P1okeT/AkH8Fy36ODqDLGV0Rl3RG k+RXLX/AOWydEfIKYj3xEMeT5KLjpDSh049ORBSIpISP/JR9f6m8eFld3bDPdqxbqmYU oV89VNW6v4+kGTfVUAQXxFXmsOb7KXyh6RqSvsaHlCOHGLsIM5uWUy2H0JZl57E5HsUu ViFD/1wAfbqeRlKv6aAng6m/lsXFAfLvCN12sHZOXu3l37taraC+ultHd6PaYOZZsYI5 Yg== Received: from sc-exch04.marvell.com ([199.233.58.184]) by mx0a-0016f401.pphosted.com with ESMTP id 327asnja5r-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Wed, 15 Jul 2020 08:49:06 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by SC-EXCH04.marvell.com (10.93.176.84) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 15 Jul 2020 08:49:05 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 15 Jul 2020 08:49:04 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 15 Jul 2020 08:49:04 -0700 Received: from NN-LT0019.marvell.com (NN-LT0019.marvell.com [10.193.54.28]) by maili.marvell.com (Postfix) with ESMTP id 0A36A3F703F; Wed, 15 Jul 2020 08:49:02 -0700 (PDT) From: Igor Russkikh To: CC: "David S . Miller" , Mark Starovoytov , Jakub Kicinski , Igor Russkikh Subject: [PATCH v2 net-next 03/10] net: atlantic: use u64_stats_update_* to protect access to 64-bit stats Date: Wed, 15 Jul 2020 18:48:35 +0300 Message-ID: <20200715154842.305-4-irusskikh@marvell.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200715154842.305-1-irusskikh@marvell.com> References: <20200715154842.305-1-irusskikh@marvell.com> MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.235,18.0.687 definitions=2020-07-15_12:2020-07-15,2020-07-15 signatures=0 Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org From: Mark Starovoytov This patch adds u64_stats_update_* usage to protect access to 64-bit stats. Signed-off-by: Mark Starovoytov Signed-off-by: Igor Russkikh --- .../net/ethernet/aquantia/atlantic/aq_ring.c | 28 +++++++- .../net/ethernet/aquantia/atlantic/aq_ring.h | 1 + .../net/ethernet/aquantia/atlantic/aq_vec.c | 68 +++++++++++++------ 3 files changed, 77 insertions(+), 20 deletions(-) diff --git a/drivers/net/ethernet/aquantia/atlantic/aq_ring.c b/drivers/net/ethernet/aquantia/atlantic/aq_ring.c index 20b606aa7974..b073c340c005 100644 --- a/drivers/net/ethernet/aquantia/atlantic/aq_ring.c +++ b/drivers/net/ethernet/aquantia/atlantic/aq_ring.c @@ -70,26 +70,35 @@ static int aq_get_rxpages(struct aq_ring_s *self, struct aq_ring_buff_s *rxbuf, rxbuf->rxdata.pg_off += AQ_CFG_RX_FRAME_MAX; if (rxbuf->rxdata.pg_off + AQ_CFG_RX_FRAME_MAX <= (PAGE_SIZE << order)) { + u64_stats_update_begin(&self->stats.syncp); self->stats.rx.pg_flips++; + u64_stats_update_end(&self->stats.syncp); } else { /* Buffer exhausted. We have other users and * should release this page and realloc */ aq_free_rxpage(&rxbuf->rxdata, aq_nic_get_dev(self->aq_nic)); + u64_stats_update_begin(&self->stats.syncp); self->stats.rx.pg_losts++; + u64_stats_update_end(&self->stats.syncp); } } else { rxbuf->rxdata.pg_off = 0; + u64_stats_update_begin(&self->stats.syncp); self->stats.rx.pg_reuses++; + u64_stats_update_end(&self->stats.syncp); } } if (!rxbuf->rxdata.page) { ret = aq_get_rxpage(&rxbuf->rxdata, order, aq_nic_get_dev(self->aq_nic)); - if (ret) + if (ret) { + u64_stats_update_begin(&self->stats.syncp); self->stats.rx.alloc_fails++; + u64_stats_update_end(&self->stats.syncp); + } return ret; } @@ -213,6 +222,7 @@ int aq_ring_init(struct aq_ring_s *self) self->hw_head = 0; self->sw_head = 0; self->sw_tail = 0; + u64_stats_init(&self->stats.syncp); return 0; } @@ -240,7 +250,9 @@ void aq_ring_queue_wake(struct aq_ring_s *ring) ring->idx))) { netif_wake_subqueue(ndev, AQ_NIC_RING2QMAP(ring->aq_nic, ring->idx)); + u64_stats_update_begin(&ring->stats.syncp); ring->stats.tx.queue_restarts++; + u64_stats_update_end(&ring->stats.syncp); } } @@ -282,8 +294,10 @@ bool aq_ring_tx_clean(struct aq_ring_s *self) } if (unlikely(buff->is_eop)) { + u64_stats_update_begin(&self->stats.syncp); ++self->stats.tx.packets; self->stats.tx.bytes += buff->skb->len; + u64_stats_update_end(&self->stats.syncp); dev_kfree_skb_any(buff->skb); } @@ -303,7 +317,9 @@ static void aq_rx_checksum(struct aq_ring_s *self, return; if (unlikely(buff->is_cso_err)) { + u64_stats_update_begin(&self->stats.syncp); ++self->stats.rx.errors; + u64_stats_update_end(&self->stats.syncp); skb->ip_summed = CHECKSUM_NONE; return; } @@ -373,13 +389,17 @@ int aq_ring_rx_clean(struct aq_ring_s *self, buff_->is_cleaned = true; } while (!buff_->is_eop); + u64_stats_update_begin(&self->stats.syncp); ++self->stats.rx.errors; + u64_stats_update_end(&self->stats.syncp); continue; } } if (buff->is_error) { + u64_stats_update_begin(&self->stats.syncp); ++self->stats.rx.errors; + u64_stats_update_end(&self->stats.syncp); continue; } @@ -394,7 +414,9 @@ int aq_ring_rx_clean(struct aq_ring_s *self, skb = build_skb(aq_buf_vaddr(&buff->rxdata), AQ_CFG_RX_FRAME_MAX); if (unlikely(!skb)) { + u64_stats_update_begin(&self->stats.syncp); self->stats.rx.skb_alloc_fails++; + u64_stats_update_end(&self->stats.syncp); err = -ENOMEM; goto err_exit; } @@ -408,7 +430,9 @@ int aq_ring_rx_clean(struct aq_ring_s *self, } else { skb = napi_alloc_skb(napi, AQ_CFG_RX_HDR_SIZE); if (unlikely(!skb)) { + u64_stats_update_begin(&self->stats.syncp); self->stats.rx.skb_alloc_fails++; + u64_stats_update_end(&self->stats.syncp); err = -ENOMEM; goto err_exit; } @@ -482,8 +506,10 @@ int aq_ring_rx_clean(struct aq_ring_s *self, : AQ_NIC_RING2QMAP(self->aq_nic, self->idx)); + u64_stats_update_begin(&self->stats.syncp); ++self->stats.rx.packets; self->stats.rx.bytes += skb->len; + u64_stats_update_end(&self->stats.syncp); napi_gro_receive(napi, skb); } diff --git a/drivers/net/ethernet/aquantia/atlantic/aq_ring.h b/drivers/net/ethernet/aquantia/atlantic/aq_ring.h index 0e40ccbaf19a..7ccdaeb957f7 100644 --- a/drivers/net/ethernet/aquantia/atlantic/aq_ring.h +++ b/drivers/net/ethernet/aquantia/atlantic/aq_ring.h @@ -110,6 +110,7 @@ struct aq_ring_stats_tx_s { }; union aq_ring_stats_s { + struct u64_stats_sync syncp; struct aq_ring_stats_rx_s rx; struct aq_ring_stats_tx_s tx; }; diff --git a/drivers/net/ethernet/aquantia/atlantic/aq_vec.c b/drivers/net/ethernet/aquantia/atlantic/aq_vec.c index eafcb98c274f..6539d2cc5459 100644 --- a/drivers/net/ethernet/aquantia/atlantic/aq_vec.c +++ b/drivers/net/ethernet/aquantia/atlantic/aq_vec.c @@ -45,7 +45,9 @@ static int aq_vec_poll(struct napi_struct *napi, int budget) } else { for (i = 0U, ring = self->ring[0]; self->tx_rings > i; ++i, ring = self->ring[i]) { + u64_stats_update_begin(&ring[AQ_VEC_RX_ID].stats.syncp); ring[AQ_VEC_RX_ID].stats.rx.polls++; + u64_stats_update_end(&ring[AQ_VEC_RX_ID].stats.syncp); if (self->aq_hw_ops->hw_ring_tx_head_update) { err = self->aq_hw_ops->hw_ring_tx_head_update( self->aq_hw, @@ -357,29 +359,57 @@ void aq_vec_add_stats(struct aq_vec_s *self, struct aq_ring_stats_tx_s *stats_tx) { struct aq_ring_s *ring = self->ring[tc]; + u64 packets, bytes, errors; + unsigned int start; if (tc < self->rx_rings) { - struct aq_ring_stats_rx_s *rx = &ring[AQ_VEC_RX_ID].stats.rx; - - stats_rx->packets += rx->packets; - stats_rx->bytes += rx->bytes; - stats_rx->errors += rx->errors; - stats_rx->jumbo_packets += rx->jumbo_packets; - stats_rx->lro_packets += rx->lro_packets; - stats_rx->alloc_fails += rx->alloc_fails; - stats_rx->skb_alloc_fails += rx->skb_alloc_fails; - stats_rx->polls += rx->polls; - stats_rx->pg_losts += rx->pg_losts; - stats_rx->pg_flips += rx->pg_flips; - stats_rx->pg_reuses += rx->pg_reuses; + u64 jumbo_packets, lro_packets, alloc_fails, skb_alloc_fails; + union aq_ring_stats_s *stats = &ring[AQ_VEC_RX_ID].stats; + u64 polls, pg_losts, pg_flips, pg_reuses; + + do { + start = u64_stats_fetch_begin_irq(&stats->syncp); + packets = stats->rx.packets; + bytes = stats->rx.bytes; + errors = stats->rx.errors; + jumbo_packets = stats->rx.jumbo_packets; + lro_packets = stats->rx.lro_packets; + alloc_fails = stats->rx.alloc_fails; + skb_alloc_fails = stats->rx.skb_alloc_fails; + polls = stats->rx.polls; + pg_losts = stats->rx.pg_losts; + pg_flips = stats->rx.pg_flips; + pg_reuses = stats->rx.pg_reuses; + } while (u64_stats_fetch_retry_irq(&stats->syncp, start)); + + stats_rx->packets += packets; + stats_rx->bytes += bytes; + stats_rx->errors += errors; + stats_rx->jumbo_packets += jumbo_packets; + stats_rx->lro_packets += lro_packets; + stats_rx->alloc_fails += alloc_fails; + stats_rx->skb_alloc_fails += skb_alloc_fails; + stats_rx->polls += polls; + stats_rx->pg_losts += pg_losts; + stats_rx->pg_flips += pg_flips; + stats_rx->pg_reuses += pg_reuses; } if (tc < self->tx_rings) { - struct aq_ring_stats_tx_s *tx = &ring[AQ_VEC_TX_ID].stats.tx; - - stats_tx->packets += tx->packets; - stats_tx->bytes += tx->bytes; - stats_tx->errors += tx->errors; - stats_tx->queue_restarts += tx->queue_restarts; + union aq_ring_stats_s *stats = &ring[AQ_VEC_TX_ID].stats; + u64 queue_restarts; + + do { + start = u64_stats_fetch_begin_irq(&stats->syncp); + packets = stats->tx.packets; + bytes = stats->tx.bytes; + errors = stats->tx.errors; + queue_restarts = stats->tx.queue_restarts; + } while (u64_stats_fetch_retry_irq(&stats->syncp, start)); + + stats_tx->packets += packets; + stats_tx->bytes += bytes; + stats_tx->errors += errors; + stats_tx->queue_restarts += queue_restarts; } } From patchwork Wed Jul 15 15:48:36 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Igor Russkikh X-Patchwork-Id: 1329643 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: patchwork-incoming-netdev@ozlabs.org Delivered-To: patchwork-incoming-netdev@ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=netdev-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=marvell.com Authentication-Results: ozlabs.org; dkim=fail reason="key not found in DNS" header.d=marvell.com header.i=@marvell.com header.a=rsa-sha256 header.s=pfpt0818 header.b=rCnSIBH6; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4B6MJ95qlWz9sTM for ; Thu, 16 Jul 2020 01:49:13 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727848AbgGOPtL (ORCPT ); Wed, 15 Jul 2020 11:49:11 -0400 Received: from mx0a-0016f401.pphosted.com ([67.231.148.174]:48002 "EHLO mx0b-0016f401.pphosted.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1726715AbgGOPtJ (ORCPT ); Wed, 15 Jul 2020 11:49:09 -0400 Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id 06FFf2Gq032725; Wed, 15 Jul 2020 08:49:07 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=pfpt0818; bh=qyTsU5vZYD8mlmP0ubLCaKedXVY/FlYx1+pft4gLRkY=; b=rCnSIBH6GuT2oP58VUQzr5KwWNt5SMOuJXfl62TRI2GjZv9rBEsTr2dcboJ2iIXl/q/8 XpqAS7OvxFjUIhlvFrl5oa7ojXEjTErfv5apP7xzxTwCHFmyJuGOKmfnQkeePFPT/GWy aa8G6QEmPRm7XKQecIx3BiSD525tQdnzMDPNHSIQF+S8C74rr2quDgnJs2TQMsQXXTzd BR1kUNh4bDeb8EmZzi5jBXNcia1A3TW8mrO2YlDzdWLpvE4ku5Hdv+mublrFoiza9v9/ kk4PXopXMnW1EQI4UiAckD6wGui6If1yHod/zgtBvPkOfxhsrna55hyPVinAc5L2iIqv cw== Received: from sc-exch03.marvell.com ([199.233.58.183]) by mx0a-0016f401.pphosted.com with ESMTP id 327asnja5x-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Wed, 15 Jul 2020 08:49:07 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by SC-EXCH03.marvell.com (10.93.176.83) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 15 Jul 2020 08:49:07 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 15 Jul 2020 08:49:07 -0700 Received: from NN-LT0019.marvell.com (NN-LT0019.marvell.com [10.193.54.28]) by maili.marvell.com (Postfix) with ESMTP id 1FC113F7040; Wed, 15 Jul 2020 08:49:04 -0700 (PDT) From: Igor Russkikh To: CC: "David S . Miller" , Mark Starovoytov , Jakub Kicinski , Pavel Belous , Igor Russkikh Subject: [PATCH v2 net-next 04/10] net: atlantic: PTP statistics Date: Wed, 15 Jul 2020 18:48:36 +0300 Message-ID: <20200715154842.305-5-irusskikh@marvell.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200715154842.305-1-irusskikh@marvell.com> References: <20200715154842.305-1-irusskikh@marvell.com> MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.235,18.0.687 definitions=2020-07-15_12:2020-07-15,2020-07-15 signatures=0 Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org From: Pavel Belous This patch adds PTP rings statistics. Before that these were missing from overall stats, hardening debugging and analysis. Signed-off-by: Pavel Belous Signed-off-by: Mark Starovoytov Signed-off-by: Igor Russkikh --- .../ethernet/aquantia/atlantic/aq_ethtool.c | 31 ++++++++++ .../net/ethernet/aquantia/atlantic/aq_ptp.c | 57 +++++++++++++------ .../net/ethernet/aquantia/atlantic/aq_ptp.h | 25 +++++++- 3 files changed, 94 insertions(+), 19 deletions(-) diff --git a/drivers/net/ethernet/aquantia/atlantic/aq_ethtool.c b/drivers/net/ethernet/aquantia/atlantic/aq_ethtool.c index 420fa5b791f9..950a837a8fa0 100644 --- a/drivers/net/ethernet/aquantia/atlantic/aq_ethtool.c +++ b/drivers/net/ethernet/aquantia/atlantic/aq_ethtool.c @@ -173,6 +173,14 @@ static u32 aq_ethtool_n_stats(struct net_device *ndev) ARRAY_SIZE(aq_ethtool_queue_stat_names) * cfg->vecs * cfg->tcs; +#if IS_REACHABLE(CONFIG_PTP_1588_CLOCK) + if (nic->aq_ptp) { + int ring_cnt = aq_ptp_get_ring_cnt(nic); + + n_stats += ARRAY_SIZE(aq_ethtool_queue_stat_names) * ring_cnt; + } +#endif + #if IS_ENABLED(CONFIG_MACSEC) if (nic->macsec_cfg) { n_stats += ARRAY_SIZE(aq_macsec_stat_names) + @@ -195,6 +203,10 @@ static void aq_ethtool_stats(struct net_device *ndev, memset(data, 0, aq_ethtool_n_stats(ndev) * sizeof(u64)); data = aq_nic_get_stats(aq_nic, data); +#if IS_REACHABLE(CONFIG_PTP_1588_CLOCK) + if (aq_nic->aq_ptp) + data = aq_ptp_get_stats(aq_nic, data); +#endif #if IS_ENABLED(CONFIG_MACSEC) data = aq_macsec_get_stats(aq_nic, data); #endif @@ -263,6 +275,25 @@ static void aq_ethtool_get_strings(struct net_device *ndev, } } } +#if IS_REACHABLE(CONFIG_PTP_1588_CLOCK) + if (nic->aq_ptp) { + int ptp_ring_cnt = aq_ptp_get_ring_cnt(nic); + unsigned int ptp_ring_idx = + aq_ptp_ring_idx(nic->aq_nic_cfg.tc_mode); + + snprintf(tc_string, 8, "PTP "); + + for (i = 0; i < ptp_ring_cnt; i++) { + for (si = 0; si < stat_cnt; si++) { + snprintf(p, ETH_GSTRING_LEN, + aq_ethtool_queue_stat_names[si], + tc_string, + i ? PTP_HWST_RING_IDX : ptp_ring_idx); + p += ETH_GSTRING_LEN; + } + } + } +#endif #if IS_ENABLED(CONFIG_MACSEC) if (!nic->macsec_cfg) break; diff --git a/drivers/net/ethernet/aquantia/atlantic/aq_ptp.c b/drivers/net/ethernet/aquantia/atlantic/aq_ptp.c index cb9bf41470fd..b4cf9e310e1f 100644 --- a/drivers/net/ethernet/aquantia/atlantic/aq_ptp.c +++ b/drivers/net/ethernet/aquantia/atlantic/aq_ptp.c @@ -81,6 +81,8 @@ struct aq_ptp_s { bool extts_pin_enabled; u64 last_sync1588_ts; + + bool a1_ptp; }; struct ptp_tm_offset { @@ -945,21 +947,6 @@ void aq_ptp_ring_deinit(struct aq_nic_s *aq_nic) aq_ring_rx_deinit(&aq_ptp->ptp_rx); } -#define PTP_8TC_RING_IDX 8 -#define PTP_4TC_RING_IDX 16 -#define PTP_HWST_RING_IDX 31 - -/* Index must be 8 (8 TCs) or 16 (4 TCs). - * It depends on Traffic Class mode. - */ -static unsigned int ptp_ring_idx(const enum aq_tc_mode tc_mode) -{ - if (tc_mode == AQ_TC_MODE_8TCS) - return PTP_8TC_RING_IDX; - - return PTP_4TC_RING_IDX; -} - int aq_ptp_ring_alloc(struct aq_nic_s *aq_nic) { struct aq_ptp_s *aq_ptp = aq_nic->aq_ptp; @@ -971,7 +958,7 @@ int aq_ptp_ring_alloc(struct aq_nic_s *aq_nic) if (!aq_ptp) return 0; - tx_ring_idx = ptp_ring_idx(aq_nic->aq_nic_cfg.tc_mode); + tx_ring_idx = aq_ptp_ring_idx(aq_nic->aq_nic_cfg.tc_mode); ring = aq_ring_tx_alloc(&aq_ptp->ptp_tx, aq_nic, tx_ring_idx, &aq_nic->aq_nic_cfg); @@ -980,7 +967,7 @@ int aq_ptp_ring_alloc(struct aq_nic_s *aq_nic) goto err_exit; } - rx_ring_idx = ptp_ring_idx(aq_nic->aq_nic_cfg.tc_mode); + rx_ring_idx = aq_ptp_ring_idx(aq_nic->aq_nic_cfg.tc_mode); ring = aq_ring_rx_alloc(&aq_ptp->ptp_rx, aq_nic, rx_ring_idx, &aq_nic->aq_nic_cfg); @@ -1172,11 +1159,17 @@ static void aq_ptp_poll_sync_work_cb(struct work_struct *w); int aq_ptp_init(struct aq_nic_s *aq_nic, unsigned int idx_vec) { + bool a1_ptp = ATL_HW_IS_CHIP_FEATURE(aq_nic->aq_hw, ATLANTIC); struct hw_atl_utils_mbox mbox; struct ptp_clock *clock; struct aq_ptp_s *aq_ptp; int err = 0; + if (!a1_ptp) { + aq_nic->aq_ptp = NULL; + return 0; + } + if (!aq_nic->aq_hw_ops->hw_get_ptp_ts) { aq_nic->aq_ptp = NULL; return 0; @@ -1203,6 +1196,7 @@ int aq_ptp_init(struct aq_nic_s *aq_nic, unsigned int idx_vec) } aq_ptp->aq_nic = aq_nic; + aq_ptp->a1_ptp = a1_ptp; spin_lock_init(&aq_ptp->ptp_lock); spin_lock_init(&aq_ptp->ptp_ring_lock); @@ -1393,4 +1387,33 @@ static void aq_ptp_poll_sync_work_cb(struct work_struct *w) schedule_delayed_work(&aq_ptp->poll_sync, timeout); } } + +int aq_ptp_get_ring_cnt(struct aq_nic_s *aq_nic) +{ + return aq_nic->aq_ptp->a1_ptp ? 2 : 1; +} + +u64 *aq_ptp_get_stats(struct aq_nic_s *aq_nic, u64 *data) +{ + struct aq_ptp_s *aq_ptp = aq_nic->aq_ptp; + struct aq_ring_stats_rx_s *stats_rx; + struct aq_ring_stats_tx_s *stats_tx; + unsigned int count = 0U; + + stats_rx = &aq_ptp->ptp_rx.stats.rx; + stats_tx = &aq_ptp->ptp_tx.stats.tx; + + aq_nic_fill_stats_data(stats_rx, stats_tx, data, &count); + + if (aq_ptp->a1_ptp) { + data += count; + stats_rx = &aq_ptp->hwts_rx.stats.rx; + /* Only Receive ring for HWTS */ + memset(stats_tx, 0, sizeof(struct aq_ring_stats_tx_s)); + aq_nic_fill_stats_data(stats_rx, stats_tx, data, &count); + } + + return data; +} + #endif diff --git a/drivers/net/ethernet/aquantia/atlantic/aq_ptp.h b/drivers/net/ethernet/aquantia/atlantic/aq_ptp.h index 231906431a48..ccf0f4d0156c 100644 --- a/drivers/net/ethernet/aquantia/atlantic/aq_ptp.h +++ b/drivers/net/ethernet/aquantia/atlantic/aq_ptp.h @@ -1,6 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -/* Aquantia Corporation Network Driver - * Copyright (C) 2014-2019 Aquantia Corporation. All rights reserved +/* Atlantic Network Driver + * + * Copyright (C) 2014-2019 aQuantia Corporation + * Copyright (C) 2019-2020 Marvell International Ltd. */ /* File aq_ptp.h: Declaration of PTP functions. @@ -10,6 +12,21 @@ #include +#define PTP_8TC_RING_IDX 8 +#define PTP_4TC_RING_IDX 16 +#define PTP_HWST_RING_IDX 31 + +/* Index must to be 8 (8 TCs) or 16 (4 TCs). + * It depends from Traffic Class mode. + */ +static inline unsigned int aq_ptp_ring_idx(const enum aq_tc_mode tc_mode) +{ + if (tc_mode == AQ_TC_MODE_8TCS) + return PTP_8TC_RING_IDX; + + return PTP_4TC_RING_IDX; +} + #if IS_REACHABLE(CONFIG_PTP_1588_CLOCK) /* Common functions */ @@ -55,6 +72,10 @@ struct ptp_clock *aq_ptp_get_ptp_clock(struct aq_ptp_s *aq_ptp); int aq_ptp_link_change(struct aq_nic_s *aq_nic); +/* PTP ring statistics */ +int aq_ptp_get_ring_cnt(struct aq_nic_s *aq_nic); +u64 *aq_ptp_get_stats(struct aq_nic_s *aq_nic, u64 *data); + #else static inline int aq_ptp_init(struct aq_nic_s *aq_nic, unsigned int idx_vec) From patchwork Wed Jul 15 15:48:37 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Igor Russkikh X-Patchwork-Id: 1329644 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: patchwork-incoming-netdev@ozlabs.org Delivered-To: patchwork-incoming-netdev@ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=netdev-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=marvell.com Authentication-Results: ozlabs.org; dkim=fail reason="key not found in DNS" header.d=marvell.com header.i=@marvell.com header.a=rsa-sha256 header.s=pfpt0818 header.b=vG0TPeRN; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4B6MJF3nrTz9sRK for ; Thu, 16 Jul 2020 01:49:17 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727864AbgGOPtQ (ORCPT ); Wed, 15 Jul 2020 11:49:16 -0400 Received: from mx0b-0016f401.pphosted.com ([67.231.156.173]:8124 "EHLO mx0b-0016f401.pphosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726715AbgGOPtN (ORCPT ); Wed, 15 Jul 2020 11:49:13 -0400 Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id 06FFejf2017387; Wed, 15 Jul 2020 08:49:10 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=pfpt0818; bh=VHjAWX0Kinr3NunoqHpev+OawVrjp1HuqFupLVbCx7g=; b=vG0TPeRNaUcrYVQ6yMGedlJJ46xlW1IQxG123KGEKJmVGLFnAMZgFpy7qmhysJPKjZW/ 1EN0gupK/mW5cnU3Pd/kL2XStLebv+/WUK1L8CseeDWk7jI8Yh+NQg1c+fyQPQKAg6/R 69x6S11ThF+OuwsyhgGM8t/Lr+EaIVd4o84sqi5WZfsBjJWvNI89jjiob6oYZ5jJY9vq Tbl+6IstmtAA/ZI//BEX0LExgDAVsQGMN/0bpnTBsCoVWIOv5KstbyrMy8I+GH16TYXI wn4Qld5d2AE4H1i+VoAqEKLy79slPjICBXGgYocTBriE6Ox+ME97NW6GWqdhXkf2/tL9 Hw== Received: from sc-exch03.marvell.com ([199.233.58.183]) by mx0b-0016f401.pphosted.com with ESMTP id 328mmhudnx-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Wed, 15 Jul 2020 08:49:10 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by SC-EXCH03.marvell.com (10.93.176.83) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 15 Jul 2020 08:49:09 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 15 Jul 2020 08:49:09 -0700 Received: from NN-LT0019.marvell.com (NN-LT0019.marvell.com [10.193.54.28]) by maili.marvell.com (Postfix) with ESMTP id 6BE6A3F7041; Wed, 15 Jul 2020 08:49:07 -0700 (PDT) From: Igor Russkikh To: CC: "David S . Miller" , Mark Starovoytov , Jakub Kicinski , Igor Russkikh Subject: [PATCH v2 net-next 05/10] net: atlantic: enable ipv6 support for TCP LSO and UDP GSO Date: Wed, 15 Jul 2020 18:48:37 +0300 Message-ID: <20200715154842.305-6-irusskikh@marvell.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200715154842.305-1-irusskikh@marvell.com> References: <20200715154842.305-1-irusskikh@marvell.com> MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.235,18.0.687 definitions=2020-07-15_12:2020-07-15,2020-07-15 signatures=0 Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org This patch enables ipv6 support for TCP LSO and UDP GSO. The code itself (aq_nic_map_skb) was ready for this after udp gso feature, but corresponding NETIF_F_TSO6 wasn't enabled. We now have tested both tcp and udp v6 GSO, and enabling them safely. Signed-off-by: Igor Russkikh Signed-off-by: Mark Starovoytov --- drivers/net/ethernet/aquantia/atlantic/aq_nic.c | 2 +- drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_b0.c | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/net/ethernet/aquantia/atlantic/aq_nic.c b/drivers/net/ethernet/aquantia/atlantic/aq_nic.c index 45d99c1a9635..9ca04d738aba 100644 --- a/drivers/net/ethernet/aquantia/atlantic/aq_nic.c +++ b/drivers/net/ethernet/aquantia/atlantic/aq_nic.c @@ -371,7 +371,7 @@ void aq_nic_ndev_init(struct aq_nic_s *self) self->ndev->features = aq_hw_caps->hw_features; self->ndev->vlan_features |= NETIF_F_HW_CSUM | NETIF_F_RXCSUM | NETIF_F_RXHASH | NETIF_F_SG | - NETIF_F_LRO | NETIF_F_TSO; + NETIF_F_LRO | NETIF_F_TSO | NETIF_F_TSO6; self->ndev->gso_partial_features = NETIF_F_GSO_UDP_L4; self->ndev->priv_flags = aq_hw_caps->hw_priv_flags; self->ndev->priv_flags |= IFF_LIVE_ADDR_CHANGE; diff --git a/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_b0.c b/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_b0.c index 97672ff142a8..51c8962b7a0e 100644 --- a/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_b0.c +++ b/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_b0.c @@ -40,6 +40,7 @@ NETIF_F_RXHASH | \ NETIF_F_SG | \ NETIF_F_TSO | \ + NETIF_F_TSO6 | \ NETIF_F_LRO | \ NETIF_F_NTUPLE | \ NETIF_F_HW_VLAN_CTAG_FILTER | \ From patchwork Wed Jul 15 15:48:38 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Igor Russkikh X-Patchwork-Id: 1329645 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: patchwork-incoming-netdev@ozlabs.org Delivered-To: patchwork-incoming-netdev@ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=netdev-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=marvell.com Authentication-Results: ozlabs.org; dkim=fail reason="key not found in DNS" header.d=marvell.com header.i=@marvell.com header.a=rsa-sha256 header.s=pfpt0818 header.b=fMzq9X7C; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4B6MJG0mzPz9sTM for ; Thu, 16 Jul 2020 01:49:18 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727854AbgGOPtP (ORCPT ); Wed, 15 Jul 2020 11:49:15 -0400 Received: from mx0a-0016f401.pphosted.com ([67.231.148.174]:27358 "EHLO mx0b-0016f401.pphosted.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1727849AbgGOPtN (ORCPT ); Wed, 15 Jul 2020 11:49:13 -0400 Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id 06FFf2DS032718; Wed, 15 Jul 2020 08:49:12 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=pfpt0818; bh=cjfNL3jkm4f2F8+BJmRw6FzoN3HCXduCVHArcBM2Wj4=; b=fMzq9X7CY11yNxEeej73zO38BlbpS7fCsWuTR0raSUthacjc4ZMgtp4AxU96ODirPuPn L4YfZPdy0Ih6jYFOPtD1QcLxc6x9UCoARj56OG6ZQS+68kxP5McAYQKsVaEzASTcuwje D18SRM+Ye/0HyMYYbv7K+wlTU4xUzg0RFwWz++QjIIFQyS6E3vcZbMOu0sJf7PEzv4vV s2iuQLtF8l9tLM9jG8y1ZE6nSsAOpVSgh4yXoijLscOu1xqujHPeIYBB9n1RSeKLgGMc versDu/58L0hgqvD9UJueDirvU9Gtxj9cYiKMvUk1FYifF3afxHG92tzbA4AhbcLAjHQ 1g== Received: from sc-exch02.marvell.com ([199.233.58.182]) by mx0a-0016f401.pphosted.com with ESMTP id 327asnja6b-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Wed, 15 Jul 2020 08:49:12 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by SC-EXCH02.marvell.com (10.93.176.82) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 15 Jul 2020 08:49:11 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 15 Jul 2020 08:49:11 -0700 Received: from NN-LT0019.marvell.com (NN-LT0019.marvell.com [10.193.54.28]) by maili.marvell.com (Postfix) with ESMTP id 845C33F703F; Wed, 15 Jul 2020 08:49:09 -0700 (PDT) From: Igor Russkikh To: CC: "David S . Miller" , Mark Starovoytov , Jakub Kicinski , Pavel Belous , Igor Russkikh Subject: [PATCH v2 net-next 06/10] net: atlantic: add support for 64-bit reads/writes Date: Wed, 15 Jul 2020 18:48:38 +0300 Message-ID: <20200715154842.305-7-irusskikh@marvell.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200715154842.305-1-irusskikh@marvell.com> References: <20200715154842.305-1-irusskikh@marvell.com> MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.235,18.0.687 definitions=2020-07-15_12:2020-07-15,2020-07-15 signatures=0 Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org From: Pavel Belous This patch adds support for 64-bit reads/writes where applicable, e.g. A2 supports them. Signed-off-by: Pavel Belous Signed-off-by: Mark Starovoytov Signed-off-by: Igor Russkikh --- .../net/ethernet/aquantia/atlantic/aq_hw.h | 1 + .../ethernet/aquantia/atlantic/aq_hw_utils.c | 29 +++++++++++++++---- .../ethernet/aquantia/atlantic/aq_hw_utils.h | 8 +++-- .../aquantia/atlantic/hw_atl/hw_atl_a0.c | 1 + .../aquantia/atlantic/hw_atl/hw_atl_b0.c | 1 + .../aquantia/atlantic/hw_atl2/hw_atl2.c | 1 + 6 files changed, 33 insertions(+), 8 deletions(-) diff --git a/drivers/net/ethernet/aquantia/atlantic/aq_hw.h b/drivers/net/ethernet/aquantia/atlantic/aq_hw.h index 284ea943e8cd..96d59ee3eb70 100644 --- a/drivers/net/ethernet/aquantia/atlantic/aq_hw.h +++ b/drivers/net/ethernet/aquantia/atlantic/aq_hw.h @@ -67,6 +67,7 @@ struct aq_hw_caps_s { u8 rx_rings; bool flow_control; bool is_64_dma; + bool op64bit; u32 priv_data_len; }; diff --git a/drivers/net/ethernet/aquantia/atlantic/aq_hw_utils.c b/drivers/net/ethernet/aquantia/atlantic/aq_hw_utils.c index 342c5179f846..ae85c0a7d238 100644 --- a/drivers/net/ethernet/aquantia/atlantic/aq_hw_utils.c +++ b/drivers/net/ethernet/aquantia/atlantic/aq_hw_utils.c @@ -1,7 +1,8 @@ // SPDX-License-Identifier: GPL-2.0-only -/* - * aQuantia Corporation Network Driver - * Copyright (C) 2014-2017 aQuantia Corporation. All rights reserved +/* Atlantic Network Driver + * + * Copyright (C) 2014-2019 aQuantia Corporation + * Copyright (C) 2019-2020 Marvell International Ltd. */ /* File aq_hw_utils.c: Definitions of helper functions used across @@ -9,6 +10,9 @@ */ #include "aq_hw_utils.h" + +#include + #include "aq_hw.h" #include "aq_nic.h" @@ -56,13 +60,28 @@ void aq_hw_write_reg(struct aq_hw_s *hw, u32 reg, u32 value) */ u64 aq_hw_read_reg64(struct aq_hw_s *hw, u32 reg) { - u64 value = aq_hw_read_reg(hw, reg); + u64 value = U64_MAX; - value |= (u64)aq_hw_read_reg(hw, reg + 4) << 32; + if (hw->aq_nic_cfg->aq_hw_caps->op64bit) + value = readq(hw->mmio + reg); + else + value = lo_hi_readq(hw->mmio + reg); + + if (value == U64_MAX && + readl(hw->mmio + hw->aq_nic_cfg->aq_hw_caps->hw_alive_check_addr) == U32_MAX) + aq_utils_obj_set(&hw->flags, AQ_HW_FLAG_ERR_UNPLUG); return value; } +void aq_hw_write_reg64(struct aq_hw_s *hw, u32 reg, u64 value) +{ + if (hw->aq_nic_cfg->aq_hw_caps->op64bit) + writeq(value, hw->mmio + reg); + else + lo_hi_writeq(value, hw->mmio + reg); +} + int aq_hw_err_from_flags(struct aq_hw_s *hw) { int err = 0; diff --git a/drivers/net/ethernet/aquantia/atlantic/aq_hw_utils.h b/drivers/net/ethernet/aquantia/atlantic/aq_hw_utils.h index 32aa5f2fb840..ffa6e4067c21 100644 --- a/drivers/net/ethernet/aquantia/atlantic/aq_hw_utils.h +++ b/drivers/net/ethernet/aquantia/atlantic/aq_hw_utils.h @@ -1,7 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -/* - * aQuantia Corporation Network Driver - * Copyright (C) 2014-2017 aQuantia Corporation. All rights reserved +/* Atlantic Network Driver + * + * Copyright (C) 2014-2019 aQuantia Corporation + * Copyright (C) 2019-2020 Marvell International Ltd. */ /* File aq_hw_utils.h: Declaration of helper functions used across hardware @@ -33,6 +34,7 @@ u32 aq_hw_read_reg_bit(struct aq_hw_s *aq_hw, u32 addr, u32 msk, u32 shift); u32 aq_hw_read_reg(struct aq_hw_s *hw, u32 reg); void aq_hw_write_reg(struct aq_hw_s *hw, u32 reg, u32 value); u64 aq_hw_read_reg64(struct aq_hw_s *hw, u32 reg); +void aq_hw_write_reg64(struct aq_hw_s *hw, u32 reg, u64 value); int aq_hw_err_from_flags(struct aq_hw_s *hw); int aq_hw_num_tcs(struct aq_hw_s *hw); int aq_hw_q_per_tc(struct aq_hw_s *hw); diff --git a/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_a0.c b/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_a0.c index a312864969af..8f8b90436ced 100644 --- a/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_a0.c +++ b/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_a0.c @@ -18,6 +18,7 @@ #define DEFAULT_A0_BOARD_BASIC_CAPABILITIES \ .is_64_dma = true, \ + .op64bit = false, \ .msix_irqs = 4U, \ .irq_mask = ~0U, \ .vecs = HW_ATL_A0_RSS_MAX, \ diff --git a/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_b0.c b/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_b0.c index 51c8962b7a0e..ee74cad4a168 100644 --- a/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_b0.c +++ b/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_b0.c @@ -20,6 +20,7 @@ #define DEFAULT_B0_BOARD_BASIC_CAPABILITIES \ .is_64_dma = true, \ + .op64bit = false, \ .msix_irqs = 8U, \ .irq_mask = ~0U, \ .vecs = HW_ATL_B0_RSS_MAX, \ diff --git a/drivers/net/ethernet/aquantia/atlantic/hw_atl2/hw_atl2.c b/drivers/net/ethernet/aquantia/atlantic/hw_atl2/hw_atl2.c index c65e6daad0e5..92f64048bf69 100644 --- a/drivers/net/ethernet/aquantia/atlantic/hw_atl2/hw_atl2.c +++ b/drivers/net/ethernet/aquantia/atlantic/hw_atl2/hw_atl2.c @@ -21,6 +21,7 @@ static int hw_atl2_act_rslvr_table_set(struct aq_hw_s *self, u8 location, #define DEFAULT_BOARD_BASIC_CAPABILITIES \ .is_64_dma = true, \ + .op64bit = true, \ .msix_irqs = 8U, \ .irq_mask = ~0U, \ .vecs = HW_ATL2_RSS_MAX, \ From patchwork Wed Jul 15 15:48:39 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Igor Russkikh X-Patchwork-Id: 1329646 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: patchwork-incoming-netdev@ozlabs.org Delivered-To: patchwork-incoming-netdev@ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=netdev-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=marvell.com Authentication-Results: ozlabs.org; dkim=fail reason="key not found in DNS" header.d=marvell.com header.i=@marvell.com header.a=rsa-sha256 header.s=pfpt0818 header.b=VHceRx0K; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4B6MJG6C0Lz9sRK for ; Thu, 16 Jul 2020 01:49:18 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727869AbgGOPtS (ORCPT ); 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Wed, 15 Jul 2020 08:49:15 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by SC-EXCH03.marvell.com (10.93.176.83) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 15 Jul 2020 08:49:14 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 15 Jul 2020 08:49:13 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 15 Jul 2020 08:49:13 -0700 Received: from NN-LT0019.marvell.com (NN-LT0019.marvell.com [10.193.54.28]) by maili.marvell.com (Postfix) with ESMTP id C7BAB3F703F; Wed, 15 Jul 2020 08:49:11 -0700 (PDT) From: Igor Russkikh To: CC: "David S . Miller" , Mark Starovoytov , Jakub Kicinski , Igor Russkikh Subject: [PATCH v2 net-next 07/10] net: atlantic: use U32_MAX in aq_hw_utils.c Date: Wed, 15 Jul 2020 18:48:39 +0300 Message-ID: <20200715154842.305-8-irusskikh@marvell.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200715154842.305-1-irusskikh@marvell.com> References: <20200715154842.305-1-irusskikh@marvell.com> MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.235,18.0.687 definitions=2020-07-15_12:2020-07-15,2020-07-15 signatures=0 Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org From: Mark Starovoytov This patch replaces magic constant ~0U usage with U32_MAX in aq_hw_utils.c Signed-off-by: Mark Starovoytov Signed-off-by: Igor Russkikh --- drivers/net/ethernet/aquantia/atlantic/aq_hw_utils.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/net/ethernet/aquantia/atlantic/aq_hw_utils.c b/drivers/net/ethernet/aquantia/atlantic/aq_hw_utils.c index ae85c0a7d238..1921741f7311 100644 --- a/drivers/net/ethernet/aquantia/atlantic/aq_hw_utils.c +++ b/drivers/net/ethernet/aquantia/atlantic/aq_hw_utils.c @@ -41,9 +41,8 @@ u32 aq_hw_read_reg(struct aq_hw_s *hw, u32 reg) { u32 value = readl(hw->mmio + reg); - if ((~0U) == value && - (~0U) == readl(hw->mmio + - hw->aq_nic_cfg->aq_hw_caps->hw_alive_check_addr)) + if (value == U32_MAX && + readl(hw->mmio + hw->aq_nic_cfg->aq_hw_caps->hw_alive_check_addr) == U32_MAX) aq_utils_obj_set(&hw->flags, AQ_HW_FLAG_ERR_UNPLUG); return value; From patchwork Wed Jul 15 15:48:40 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Igor Russkikh X-Patchwork-Id: 1329647 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: patchwork-incoming-netdev@ozlabs.org Delivered-To: patchwork-incoming-netdev@ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=netdev-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=marvell.com Authentication-Results: ozlabs.org; dkim=fail reason="key not found in DNS" header.d=marvell.com header.i=@marvell.com header.a=rsa-sha256 header.s=pfpt0818 header.b=XUy9Z8SQ; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4B6MJL3mSPz9sRK for ; Thu, 16 Jul 2020 01:49:22 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727879AbgGOPtV (ORCPT ); Wed, 15 Jul 2020 11:49:21 -0400 Received: from mx0b-0016f401.pphosted.com ([67.231.156.173]:16994 "EHLO mx0b-0016f401.pphosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727863AbgGOPtU (ORCPT ); Wed, 15 Jul 2020 11:49:20 -0400 Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id 06FFej2H017373; Wed, 15 Jul 2020 08:49:17 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=pfpt0818; bh=yFCv+yX5x0m+7w+YjIQi4F4/tzx1fIYqa88hpi0/ssc=; b=XUy9Z8SQF9GZOuLy8EPnHRdky4wz/RXIx+aBb4peCl5HDrtW5Y9PluelQJiLRiqjuqGW GipImKJfI6187bVtOTSLZYME6jx0AKrqhEE34/uaL2qMXvX/6fyiOQSHx/gOBjKHcttC tAtE04hHjgi7QTulE7zJz0VS9fzYrh0R9+FVGvA0rT3XMxV9wB7zbSMvsyd2Im8eBshu vLUFI0NwMlPlwyC/5/qw76iahliMRHBaXRe62o6KR7aGb54sNrrynJWqYkZGsDDvS2IF 2+1WChTM6RIkvVyE8JSomykWeo9PdhililOLLr3ws+/CmRtL5dGHN1ZaC+Gl7M3FrksC 7Q== Received: from sc-exch04.marvell.com ([199.233.58.184]) by mx0b-0016f401.pphosted.com with ESMTP id 328mmhudp8-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Wed, 15 Jul 2020 08:49:17 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by SC-EXCH04.marvell.com (10.93.176.84) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 15 Jul 2020 08:49:15 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 15 Jul 2020 08:49:15 -0700 Received: from NN-LT0019.marvell.com (NN-LT0019.marvell.com [10.193.54.28]) by maili.marvell.com (Postfix) with ESMTP id DCEE83F7043; Wed, 15 Jul 2020 08:49:13 -0700 (PDT) From: Igor Russkikh To: CC: "David S . Miller" , Mark Starovoytov , Jakub Kicinski , Nikita Danilov , Igor Russkikh Subject: [PATCH v2 net-next 08/10] net: atlantic: use intermediate variable to improve readability a bit Date: Wed, 15 Jul 2020 18:48:40 +0300 Message-ID: <20200715154842.305-9-irusskikh@marvell.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200715154842.305-1-irusskikh@marvell.com> References: <20200715154842.305-1-irusskikh@marvell.com> MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.235,18.0.687 definitions=2020-07-15_12:2020-07-15,2020-07-15 signatures=0 Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org From: Nikita Danilov This patch syncs up hw_atl_a0.c with an out-of-tree driver, where an intermediate variable was introduced in a couple of functions to improve the code readability a bit. Signed-off-by: Nikita Danilov Signed-off-by: Mark Starovoytov Signed-off-by: Igor Russkikh --- .../aquantia/atlantic/hw_atl/hw_atl_a0.c | 21 +++++++++---------- 1 file changed, 10 insertions(+), 11 deletions(-) diff --git a/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_a0.c b/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_a0.c index 8f8b90436ced..e1877d520135 100644 --- a/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_a0.c +++ b/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_a0.c @@ -752,6 +752,7 @@ static int hw_atl_a0_hw_irq_read(struct aq_hw_s *self, u64 *mask) static int hw_atl_a0_hw_packet_filter_set(struct aq_hw_s *self, unsigned int packet_filter) { + struct aq_nic_cfg_s *cfg = self->aq_nic_cfg; unsigned int i = 0U; hw_atl_rpfl2promiscuous_mode_en_set(self, @@ -760,14 +761,13 @@ static int hw_atl_a0_hw_packet_filter_set(struct aq_hw_s *self, IS_FILTER_ENABLED(IFF_MULTICAST), 0); hw_atl_rpfl2broadcast_en_set(self, IS_FILTER_ENABLED(IFF_BROADCAST)); - self->aq_nic_cfg->is_mc_list_enabled = - IS_FILTER_ENABLED(IFF_MULTICAST); + cfg->is_mc_list_enabled = IS_FILTER_ENABLED(IFF_MULTICAST); for (i = HW_ATL_A0_MAC_MIN; i < HW_ATL_A0_MAC_MAX; ++i) hw_atl_rpfl2_uc_flr_en_set(self, - (self->aq_nic_cfg->is_mc_list_enabled && - (i <= self->aq_nic_cfg->mc_list_count)) ? - 1U : 0U, i); + (cfg->is_mc_list_enabled && + (i <= cfg->mc_list_count)) ? 1U : 0U, + i); return aq_hw_err_from_flags(self); } @@ -780,19 +780,18 @@ static int hw_atl_a0_hw_multicast_list_set(struct aq_hw_s *self, [ETH_ALEN], u32 count) { + struct aq_nic_cfg_s *cfg = self->aq_nic_cfg; int err = 0; if (count > (HW_ATL_A0_MAC_MAX - HW_ATL_A0_MAC_MIN)) { err = EBADRQC; goto err_exit; } - for (self->aq_nic_cfg->mc_list_count = 0U; - self->aq_nic_cfg->mc_list_count < count; - ++self->aq_nic_cfg->mc_list_count) { - u32 i = self->aq_nic_cfg->mc_list_count; + for (cfg->mc_list_count = 0U; cfg->mc_list_count < count; ++cfg->mc_list_count) { + u32 i = cfg->mc_list_count; u32 h = (ar_mac[i][0] << 8) | (ar_mac[i][1]); u32 l = (ar_mac[i][2] << 24) | (ar_mac[i][3] << 16) | - (ar_mac[i][4] << 8) | ar_mac[i][5]; + (ar_mac[i][4] << 8) | ar_mac[i][5]; hw_atl_rpfl2_uc_flr_en_set(self, 0U, HW_ATL_A0_MAC_MIN + i); @@ -805,7 +804,7 @@ static int hw_atl_a0_hw_multicast_list_set(struct aq_hw_s *self, HW_ATL_A0_MAC_MIN + i); hw_atl_rpfl2_uc_flr_en_set(self, - (self->aq_nic_cfg->is_mc_list_enabled), + (cfg->is_mc_list_enabled), HW_ATL_A0_MAC_MIN + i); } From patchwork Wed Jul 15 15:48:41 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Igor Russkikh X-Patchwork-Id: 1329648 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: patchwork-incoming-netdev@ozlabs.org Delivered-To: patchwork-incoming-netdev@ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=netdev-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=marvell.com Authentication-Results: ozlabs.org; dkim=fail reason="key not found in DNS" header.d=marvell.com header.i=@marvell.com header.a=rsa-sha256 header.s=pfpt0818 header.b=J7Cn8uk4; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4B6MJQ2WvVz9s1x for ; Thu, 16 Jul 2020 01:49:26 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727888AbgGOPtY (ORCPT ); Wed, 15 Jul 2020 11:49:24 -0400 Received: from mx0b-0016f401.pphosted.com ([67.231.156.173]:1544 "EHLO mx0b-0016f401.pphosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727886AbgGOPtW (ORCPT ); Wed, 15 Jul 2020 11:49:22 -0400 Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id 06FFeiow017345; Wed, 15 Jul 2020 08:49:19 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=pfpt0818; bh=liEtudmisDs61h3nffEGfhTg6n2tiMuIT4m7/3K6Q+Y=; b=J7Cn8uk4P/14ZrztHHWzK3rilSBRHiiee6nPoVJCSYONcIZmdcSwlgNshbOAJRqDT3CO 61ZwmnsNHpYTAhUvBb7B68YPw5/3OpkVHGUDOGqqRQ8B2f4OvYXZAxFsNa/HK6oKAuWL 3BMApUVvNq6rcHs52tIGJDAgQrUaRrCBlliwOVf0wTaI023AGeRIG1ALyBInBomXsPUn NAh1Q0S6Nu9xoEkcPPbErbJjxm4KUoGfz9nkihLxI0WrKgZsHgZvsEQQX4zFPJzOHLfE sjTyqegpeXgkiumsCNZXfA2EsIISVWGlIEvO9I4EtRit2+gB9mE+MwV6P7S8lWP6o4MW Hw== Received: from sc-exch02.marvell.com ([199.233.58.182]) by mx0b-0016f401.pphosted.com with ESMTP id 328mmhudpd-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Wed, 15 Jul 2020 08:49:19 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by SC-EXCH02.marvell.com (10.93.176.82) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 15 Jul 2020 08:49:18 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 15 Jul 2020 08:49:18 -0700 Received: from NN-LT0019.marvell.com (NN-LT0019.marvell.com [10.193.54.28]) by maili.marvell.com (Postfix) with ESMTP id 3B14C3F7041; Wed, 15 Jul 2020 08:49:15 -0700 (PDT) From: Igor Russkikh To: CC: "David S . Miller" , Mark Starovoytov , Jakub Kicinski , Dmitry Bogdanov , Igor Russkikh Subject: [PATCH v2 net-next 09/10] net: atlantic: A0 ntuple filters Date: Wed, 15 Jul 2020 18:48:41 +0300 Message-ID: <20200715154842.305-10-irusskikh@marvell.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200715154842.305-1-irusskikh@marvell.com> References: <20200715154842.305-1-irusskikh@marvell.com> MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.235,18.0.687 definitions=2020-07-15_12:2020-07-15,2020-07-15 signatures=0 Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org From: Dmitry Bogdanov This patch adds support for ntuple filters on A0. Signed-off-by: Dmitry Bogdanov Signed-off-by: Mark Starovoytov Signed-off-by: Igor Russkikh --- .../aquantia/atlantic/hw_atl/hw_atl_a0.c | 116 +++++++++++++----- 1 file changed, 88 insertions(+), 28 deletions(-) diff --git a/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_a0.c b/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_a0.c index e1877d520135..c38a4b8a14cb 100644 --- a/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_a0.c +++ b/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_a0.c @@ -16,33 +16,35 @@ #include "hw_atl_llh.h" #include "hw_atl_a0_internal.h" -#define DEFAULT_A0_BOARD_BASIC_CAPABILITIES \ - .is_64_dma = true, \ - .op64bit = false, \ - .msix_irqs = 4U, \ - .irq_mask = ~0U, \ - .vecs = HW_ATL_A0_RSS_MAX, \ - .tcs_max = HW_ATL_A0_TC_MAX, \ - .rxd_alignment = 1U, \ - .rxd_size = HW_ATL_A0_RXD_SIZE, \ - .rxds_max = HW_ATL_A0_MAX_RXD, \ - .rxds_min = HW_ATL_A0_MIN_RXD, \ - .txd_alignment = 1U, \ - .txd_size = HW_ATL_A0_TXD_SIZE, \ - .txds_max = HW_ATL_A0_MAX_TXD, \ - .txds_min = HW_ATL_A0_MIN_RXD, \ - .txhwb_alignment = 4096U, \ - .tx_rings = HW_ATL_A0_TX_RINGS, \ - .rx_rings = HW_ATL_A0_RX_RINGS, \ - .hw_features = NETIF_F_HW_CSUM | \ - NETIF_F_RXHASH | \ - NETIF_F_RXCSUM | \ - NETIF_F_SG | \ - NETIF_F_TSO, \ - .hw_priv_flags = IFF_UNICAST_FLT, \ - .flow_control = true, \ - .mtu = HW_ATL_A0_MTU_JUMBO, \ - .mac_regs_count = 88, \ +#define DEFAULT_A0_BOARD_BASIC_CAPABILITIES \ + .is_64_dma = true, \ + .op64bit = false, \ + .msix_irqs = 4U, \ + .irq_mask = ~0U, \ + .vecs = HW_ATL_A0_RSS_MAX, \ + .tcs_max = HW_ATL_A0_TC_MAX, \ + .rxd_alignment = 1U, \ + .rxd_size = HW_ATL_A0_RXD_SIZE, \ + .rxds_max = HW_ATL_A0_MAX_RXD, \ + .rxds_min = HW_ATL_A0_MIN_RXD, \ + .txd_alignment = 1U, \ + .txd_size = HW_ATL_A0_TXD_SIZE, \ + .txds_max = HW_ATL_A0_MAX_TXD, \ + .txds_min = HW_ATL_A0_MIN_RXD, \ + .txhwb_alignment = 4096U, \ + .tx_rings = HW_ATL_A0_TX_RINGS, \ + .rx_rings = HW_ATL_A0_RX_RINGS, \ + .hw_features = NETIF_F_HW_CSUM | \ + NETIF_F_RXHASH | \ + NETIF_F_RXCSUM | \ + NETIF_F_SG | \ + NETIF_F_TSO | \ + NETIF_F_NTUPLE | \ + NETIF_F_HW_VLAN_CTAG_FILTER, \ + .hw_priv_flags = IFF_UNICAST_FLT, \ + .flow_control = true, \ + .mtu = HW_ATL_A0_MTU_JUMBO, \ + .mac_regs_count = 88, \ .hw_alive_check_addr = 0x10U const struct aq_hw_caps_s hw_atl_a0_caps_aqc100 = { @@ -330,6 +332,7 @@ static int hw_atl_a0_hw_mac_addr_set(struct aq_hw_s *self, u8 *mac_addr) err = -EINVAL; goto err_exit; } + h = (mac_addr[0] << 8) | (mac_addr[1]); l = (mac_addr[2] << 24) | (mac_addr[3] << 16) | (mac_addr[4] << 8) | mac_addr[5]; @@ -356,7 +359,6 @@ static int hw_atl_a0_hw_init(struct aq_hw_s *self, u8 *mac_addr) struct aq_nic_cfg_s *aq_nic_cfg = self->aq_nic_cfg; int err = 0; - hw_atl_a0_hw_init_tx_path(self); hw_atl_a0_hw_init_rx_path(self); @@ -885,6 +887,63 @@ static int hw_atl_a0_hw_ring_rx_stop(struct aq_hw_s *self, return aq_hw_err_from_flags(self); } +static int hw_atl_a0_hw_fl3l4_clear(struct aq_hw_s *self, + struct aq_rx_filter_l3l4 *data) +{ + u8 location = data->location; + + if (!data->is_ipv6) { + hw_atl_rpfl3l4_cmd_clear(self, location); + hw_atl_rpf_l4_spd_set(self, 0U, location); + hw_atl_rpf_l4_dpd_set(self, 0U, location); + hw_atl_rpfl3l4_ipv4_src_addr_clear(self, location); + hw_atl_rpfl3l4_ipv4_dest_addr_clear(self, location); + } else { + int i; + + for (i = 0; i < HW_ATL_RX_CNT_REG_ADDR_IPV6; ++i) { + hw_atl_rpfl3l4_cmd_clear(self, location + i); + hw_atl_rpf_l4_spd_set(self, 0U, location + i); + hw_atl_rpf_l4_dpd_set(self, 0U, location + i); + } + hw_atl_rpfl3l4_ipv6_src_addr_clear(self, location); + hw_atl_rpfl3l4_ipv6_dest_addr_clear(self, location); + } + + return aq_hw_err_from_flags(self); +} + +static int hw_atl_a0_hw_fl3l4_set(struct aq_hw_s *self, + struct aq_rx_filter_l3l4 *data) +{ + u8 location = data->location; + + hw_atl_a0_hw_fl3l4_clear(self, data); + + if (data->cmd) { + if (!data->is_ipv6) { + hw_atl_rpfl3l4_ipv4_dest_addr_set(self, + location, + data->ip_dst[0]); + hw_atl_rpfl3l4_ipv4_src_addr_set(self, + location, + data->ip_src[0]); + } else { + hw_atl_rpfl3l4_ipv6_dest_addr_set(self, + location, + data->ip_dst); + hw_atl_rpfl3l4_ipv6_src_addr_set(self, + location, + data->ip_src); + } + } + hw_atl_rpf_l4_dpd_set(self, data->p_dst, location); + hw_atl_rpf_l4_spd_set(self, data->p_src, location); + hw_atl_rpfl3l4_cmd_set(self, location, data->cmd); + + return aq_hw_err_from_flags(self); +} + const struct aq_hw_ops hw_atl_ops_a0 = { .hw_soft_reset = hw_atl_utils_soft_reset, .hw_prepare = hw_atl_utils_initfw, @@ -911,6 +970,7 @@ const struct aq_hw_ops hw_atl_ops_a0 = { .hw_ring_rx_init = hw_atl_a0_hw_ring_rx_init, .hw_ring_tx_init = hw_atl_a0_hw_ring_tx_init, .hw_packet_filter_set = hw_atl_a0_hw_packet_filter_set, + .hw_filter_l3l4_set = hw_atl_a0_hw_fl3l4_set, .hw_multicast_list_set = hw_atl_a0_hw_multicast_list_set, .hw_interrupt_moderation_set = hw_atl_a0_hw_interrupt_moderation_set, .hw_rss_set = hw_atl_a0_hw_rss_set, From patchwork Wed Jul 15 15:48:42 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Igor Russkikh X-Patchwork-Id: 1329650 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: patchwork-incoming-netdev@ozlabs.org Delivered-To: patchwork-incoming-netdev@ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=netdev-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=marvell.com Authentication-Results: ozlabs.org; dkim=fail reason="key not found in DNS" header.d=marvell.com header.i=@marvell.com header.a=rsa-sha256 header.s=pfpt0818 header.b=BQVSKD4u; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4B6MJV1ckpz9s1x for ; Thu, 16 Jul 2020 01:49:30 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727908AbgGOPt3 (ORCPT ); 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Wed, 15 Jul 2020 08:49:22 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by SC-EXCH03.marvell.com (10.93.176.83) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 15 Jul 2020 08:49:21 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 15 Jul 2020 08:49:20 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 15 Jul 2020 08:49:20 -0700 Received: from NN-LT0019.marvell.com (NN-LT0019.marvell.com [10.193.54.28]) by maili.marvell.com (Postfix) with ESMTP id 8557B3F703F; Wed, 15 Jul 2020 08:49:18 -0700 (PDT) From: Igor Russkikh To: CC: "David S . Miller" , Mark Starovoytov , Jakub Kicinski , Igor Russkikh Subject: [PATCH v2 net-next 10/10] net: atlantic: add hwmon getter for MAC temperature Date: Wed, 15 Jul 2020 18:48:42 +0300 Message-ID: <20200715154842.305-11-irusskikh@marvell.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200715154842.305-1-irusskikh@marvell.com> References: <20200715154842.305-1-irusskikh@marvell.com> MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.235,18.0.687 definitions=2020-07-15_12:2020-07-15,2020-07-15 signatures=0 Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org From: Mark Starovoytov This patch adds the possibility to obtain MAC temperature via hwmon. On A1 there are two separate temperature sensors. On A2 there's only one temperature sensor, which is used for reporting both MAC and PHY temperature. Signed-off-by: Mark Starovoytov Signed-off-by: Igor Russkikh --- .../ethernet/aquantia/atlantic/aq_drvinfo.c | 62 ++++++++++++++----- .../ethernet/aquantia/atlantic/aq_drvinfo.h | 10 +-- .../net/ethernet/aquantia/atlantic/aq_hw.h | 4 ++ .../aquantia/atlantic/hw_atl/hw_atl_b0.c | 44 +++++++++++++ .../aquantia/atlantic/hw_atl/hw_atl_llh.c | 51 ++++++++++++++- .../aquantia/atlantic/hw_atl/hw_atl_llh.h | 25 +++++++- .../atlantic/hw_atl/hw_atl_llh_internal.h | 37 ++++++++++- .../aquantia/atlantic/hw_atl/hw_atl_utils.c | 1 + .../atlantic/hw_atl/hw_atl_utils_fw2x.c | 1 + .../atlantic/hw_atl2/hw_atl2_utils_fw.c | 21 +++++++ 10 files changed, 226 insertions(+), 30 deletions(-) diff --git a/drivers/net/ethernet/aquantia/atlantic/aq_drvinfo.c b/drivers/net/ethernet/aquantia/atlantic/aq_drvinfo.c index 6da65099047d..d3526cd38f3d 100644 --- a/drivers/net/ethernet/aquantia/atlantic/aq_drvinfo.c +++ b/drivers/net/ethernet/aquantia/atlantic/aq_drvinfo.c @@ -1,5 +1,9 @@ // SPDX-License-Identifier: GPL-2.0-only -/* Copyright (C) 2014-2019 aQuantia Corporation. */ +/* Atlantic Network Driver + * + * Copyright (C) 2014-2019 aQuantia Corporation + * Copyright (C) 2019-2020 Marvell International Ltd. + */ /* File aq_drvinfo.c: Definition of common code for firmware info in sys.*/ @@ -12,32 +16,51 @@ #include #include "aq_drvinfo.h" +#include "aq_nic.h" #if IS_REACHABLE(CONFIG_HWMON) +static const char * const atl_temp_label[] = { + "PHY Temperature", + "MAC Temperature", +}; + static int aq_hwmon_read(struct device *dev, enum hwmon_sensor_types type, u32 attr, int channel, long *value) { struct aq_nic_s *aq_nic = dev_get_drvdata(dev); + int err = 0; int temp; - int err; if (!aq_nic) return -EIO; - if (type != hwmon_temp) + if (type != hwmon_temp || attr != hwmon_temp_input) return -EOPNOTSUPP; - if (!aq_nic->aq_fw_ops->get_phy_temp) - return -EOPNOTSUPP; + switch (channel) { + case 0: + if (!aq_nic->aq_fw_ops->get_phy_temp) + return -EOPNOTSUPP; - switch (attr) { - case hwmon_temp_input: err = aq_nic->aq_fw_ops->get_phy_temp(aq_nic->aq_hw, &temp); *value = temp; - return err; + break; + case 1: + if (!aq_nic->aq_fw_ops->get_mac_temp && + !aq_nic->aq_hw_ops->hw_get_mac_temp) + return -EOPNOTSUPP; + + if (aq_nic->aq_fw_ops->get_mac_temp) + err = aq_nic->aq_fw_ops->get_mac_temp(aq_nic->aq_hw, &temp); + else + err = aq_nic->aq_hw_ops->hw_get_mac_temp(aq_nic->aq_hw, &temp); + *value = temp; + break; default: return -EOPNOTSUPP; } + + return err; } static int aq_hwmon_read_string(struct device *dev, @@ -49,28 +72,32 @@ static int aq_hwmon_read_string(struct device *dev, if (!aq_nic) return -EIO; - if (type != hwmon_temp) + if (type != hwmon_temp || attr != hwmon_temp_label) return -EOPNOTSUPP; - if (!aq_nic->aq_fw_ops->get_phy_temp) + if (channel < ARRAY_SIZE(atl_temp_label)) + *str = atl_temp_label[channel]; + else return -EOPNOTSUPP; - switch (attr) { - case hwmon_temp_label: - *str = "PHY Temperature"; - return 0; - default: - return -EOPNOTSUPP; - } + return 0; } static umode_t aq_hwmon_is_visible(const void *data, enum hwmon_sensor_types type, u32 attr, int channel) { + const struct aq_nic_s *nic = data; + if (type != hwmon_temp) return 0; + if (channel == 0 && !nic->aq_fw_ops->get_phy_temp) + return 0; + else if (channel == 1 && !nic->aq_fw_ops->get_mac_temp && + !nic->aq_hw_ops->hw_get_mac_temp) + return 0; + switch (attr) { case hwmon_temp_input: case hwmon_temp_label: @@ -87,6 +114,7 @@ static const struct hwmon_ops aq_hwmon_ops = { }; static u32 aq_hwmon_temp_config[] = { + HWMON_T_INPUT | HWMON_T_LABEL, HWMON_T_INPUT | HWMON_T_LABEL, 0, }; diff --git a/drivers/net/ethernet/aquantia/atlantic/aq_drvinfo.h b/drivers/net/ethernet/aquantia/atlantic/aq_drvinfo.h index 23a0487893a7..59113a20622a 100644 --- a/drivers/net/ethernet/aquantia/atlantic/aq_drvinfo.h +++ b/drivers/net/ethernet/aquantia/atlantic/aq_drvinfo.h @@ -1,14 +1,16 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -/* Copyright (C) 2014-2017 aQuantia Corporation. */ +/* Atlantic Network Driver + * + * Copyright (C) 2014-2019 aQuantia Corporation + * Copyright (C) 2019-2020 Marvell International Ltd. + */ /* File aq_drvinfo.h: Declaration of common code for firmware info in sys.*/ #ifndef AQ_DRVINFO_H #define AQ_DRVINFO_H -#include "aq_nic.h" -#include "aq_hw.h" -#include "hw_atl/hw_atl_utils.h" +struct net_device; int aq_drvinfo_init(struct net_device *ndev); diff --git a/drivers/net/ethernet/aquantia/atlantic/aq_hw.h b/drivers/net/ethernet/aquantia/atlantic/aq_hw.h index 96d59ee3eb70..95ee1336ac79 100644 --- a/drivers/net/ethernet/aquantia/atlantic/aq_hw.h +++ b/drivers/net/ethernet/aquantia/atlantic/aq_hw.h @@ -333,6 +333,8 @@ struct aq_hw_ops { int (*hw_set_fc)(struct aq_hw_s *self, u32 fc, u32 tc); int (*hw_set_loopback)(struct aq_hw_s *self, u32 mode, bool enable); + + int (*hw_get_mac_temp)(struct aq_hw_s *self, u32 *temp); }; struct aq_fw_ops { @@ -355,6 +357,8 @@ struct aq_fw_ops { int (*update_stats)(struct aq_hw_s *self); + int (*get_mac_temp)(struct aq_hw_s *self, int *temp); + int (*get_phy_temp)(struct aq_hw_s *self, int *temp); u32 (*get_flow_control)(struct aq_hw_s *self, u32 *fcmode); diff --git a/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_b0.c b/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_b0.c index ee74cad4a168..34626eef2909 100644 --- a/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_b0.c +++ b/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_b0.c @@ -1581,6 +1581,48 @@ int hw_atl_b0_set_loopback(struct aq_hw_s *self, u32 mode, bool enable) return 0; } +static u32 hw_atl_b0_ts_ready_and_latch_high_get(struct aq_hw_s *self) +{ + if (hw_atl_ts_ready_get(self) && hw_atl_ts_ready_latch_high_get(self)) + return 1; + + return 0; +} + +static int hw_atl_b0_get_mac_temp(struct aq_hw_s *self, u32 *temp) +{ + bool ts_disabled; + int err; + u32 val; + u32 ts; + + ts_disabled = (hw_atl_ts_power_down_get(self) == 1U); + + if (ts_disabled) { + // Set AFE Temperature Sensor to on (off by default) + hw_atl_ts_power_down_set(self, 0U); + + // Reset internal capacitors, biasing, and counters + hw_atl_ts_reset_set(self, 1); + hw_atl_ts_reset_set(self, 0); + } + + err = readx_poll_timeout_atomic(hw_atl_b0_ts_ready_and_latch_high_get, + self, val, val == 1, 10000U, 500000U); + if (err) + return err; + + ts = hw_atl_ts_data_get(self); + *temp = ts * ts * 16 / 100000 + 60 * ts - 83410; + + if (ts_disabled) { + // Set AFE Temperature Sensor back to off + hw_atl_ts_power_down_set(self, 1U); + } + + return 0; +} + const struct aq_hw_ops hw_atl_ops_b0 = { .hw_soft_reset = hw_atl_utils_soft_reset, .hw_prepare = hw_atl_utils_initfw, @@ -1637,4 +1679,6 @@ const struct aq_hw_ops hw_atl_ops_b0 = { .hw_set_offload = hw_atl_b0_hw_offload_set, .hw_set_loopback = hw_atl_b0_set_loopback, .hw_set_fc = hw_atl_b0_set_fc, + + .hw_get_mac_temp = hw_atl_b0_get_mac_temp, }; diff --git a/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_llh.c b/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_llh.c index d775b23025c1..745634141f47 100644 --- a/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_llh.c +++ b/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_llh.c @@ -1,7 +1,8 @@ // SPDX-License-Identifier: GPL-2.0-only -/* - * aQuantia Corporation Network Driver - * Copyright (C) 2014-2019 aQuantia Corporation. All rights reserved +/* Atlantic Network Driver + * + * Copyright (C) 2014-2019 aQuantia Corporation + * Copyright (C) 2019-2020 Marvell International Ltd. */ /* File hw_atl_llh.c: Definitions of bitfield and register access functions for @@ -12,6 +13,50 @@ #include "hw_atl_llh_internal.h" #include "../aq_hw_utils.h" +void hw_atl_ts_reset_set(struct aq_hw_s *aq_hw, u32 val) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_TS_RESET_ADR, + HW_ATL_TS_RESET_MSK, + HW_ATL_TS_RESET_SHIFT, + val); +} + +void hw_atl_ts_power_down_set(struct aq_hw_s *aq_hw, u32 val) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_TS_POWER_DOWN_ADR, + HW_ATL_TS_POWER_DOWN_MSK, + HW_ATL_TS_POWER_DOWN_SHIFT, + val); +} + +u32 hw_atl_ts_power_down_get(struct aq_hw_s *aq_hw) +{ + return aq_hw_read_reg_bit(aq_hw, HW_ATL_TS_POWER_DOWN_ADR, + HW_ATL_TS_POWER_DOWN_MSK, + HW_ATL_TS_POWER_DOWN_SHIFT); +} + +u32 hw_atl_ts_ready_get(struct aq_hw_s *aq_hw) +{ + return aq_hw_read_reg_bit(aq_hw, HW_ATL_TS_READY_ADR, + HW_ATL_TS_READY_MSK, + HW_ATL_TS_READY_SHIFT); +} + +u32 hw_atl_ts_ready_latch_high_get(struct aq_hw_s *aq_hw) +{ + return aq_hw_read_reg_bit(aq_hw, HW_ATL_TS_READY_LATCH_HIGH_ADR, + HW_ATL_TS_READY_LATCH_HIGH_MSK, + HW_ATL_TS_READY_LATCH_HIGH_SHIFT); +} + +u32 hw_atl_ts_data_get(struct aq_hw_s *aq_hw) +{ + return aq_hw_read_reg_bit(aq_hw, HW_ATL_TS_DATA_OUT_ADR, + HW_ATL_TS_DATA_OUT_MSK, + HW_ATL_TS_DATA_OUT_SHIFT); +} + /* global */ void hw_atl_reg_glb_cpu_sem_set(struct aq_hw_s *aq_hw, u32 glb_cpu_sem, u32 semaphore) diff --git a/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_llh.h b/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_llh.h index 61a6f70c51cd..ed46f5eaca12 100644 --- a/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_llh.h +++ b/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_llh.h @@ -1,7 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -/* - * aQuantia Corporation Network Driver - * Copyright (C) 2014-2019 aQuantia Corporation. All rights reserved +/* Atlantic Network Driver + * + * Copyright (C) 2014-2019 aQuantia Corporation + * Copyright (C) 2019-2020 Marvell International Ltd. */ /* File hw_atl_llh.h: Declarations of bitfield and register access functions for @@ -15,6 +16,24 @@ struct aq_hw_s; +/* set temperature sense reset */ +void hw_atl_ts_reset_set(struct aq_hw_s *aq_hw, u32 val); + +/* set temperature sense power down */ +void hw_atl_ts_power_down_set(struct aq_hw_s *aq_hw, u32 val); + +/* get temperature sense power down */ +u32 hw_atl_ts_power_down_get(struct aq_hw_s *aq_hw); + +/* get temperature sense ready */ +u32 hw_atl_ts_ready_get(struct aq_hw_s *aq_hw); + +/* get temperature sense ready latch high */ +u32 hw_atl_ts_ready_latch_high_get(struct aq_hw_s *aq_hw); + +/* get temperature sense data */ +u32 hw_atl_ts_data_get(struct aq_hw_s *aq_hw); + /* global */ /* set global microprocessor semaphore */ diff --git a/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_llh_internal.h b/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_llh_internal.h index 7430ff025134..c9807afaf0a9 100644 --- a/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_llh_internal.h +++ b/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_llh_internal.h @@ -1,7 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -/* - * aQuantia Corporation Network Driver - * Copyright (C) 2014-2019 aQuantia Corporation. All rights reserved +/* Atlantic Network Driver + * + * Copyright (C) 2014-2019 aQuantia Corporation + * Copyright (C) 2019-2020 Marvell International Ltd. */ /* File hw_atl_llh_internal.h: Preprocessor definitions @@ -11,6 +12,36 @@ #ifndef HW_ATL_LLH_INTERNAL_H #define HW_ATL_LLH_INTERNAL_H +/* COM Temperature Sense Reset Bitfield Definitions */ +#define HW_ATL_TS_RESET_ADR 0x00003100 +#define HW_ATL_TS_RESET_MSK 0x00000004 +#define HW_ATL_TS_RESET_SHIFT 2 +#define HW_ATL_TS_RESET_WIDTH 1 + +/* COM Temperature Sense Power Down Bitfield Definitions */ +#define HW_ATL_TS_POWER_DOWN_ADR 0x00003100 +#define HW_ATL_TS_POWER_DOWN_MSK 0x00000001 +#define HW_ATL_TS_POWER_DOWN_SHIFT 0 +#define HW_ATL_TS_POWER_DOWN_WIDTH 1 + +/* COM Temperature Sense Ready Bitfield Definitions */ +#define HW_ATL_TS_READY_ADR 0x00003120 +#define HW_ATL_TS_READY_MSK 0x80000000 +#define HW_ATL_TS_READY_SHIFT 31 +#define HW_ATL_TS_READY_WIDTH 1 + +/* COM Temperature Sense Ready Latch High Bitfield Definitions */ +#define HW_ATL_TS_READY_LATCH_HIGH_ADR 0x00003120 +#define HW_ATL_TS_READY_LATCH_HIGH_MSK 0x40000000 +#define HW_ATL_TS_READY_LATCH_HIGH_SHIFT 30 +#define HW_ATL_TS_READY_LATCH_HIGH_WIDTH 1 + +/* COM Temperature Sense Data Out [B:0] Bitfield Definitions */ +#define HW_ATL_TS_DATA_OUT_ADR 0x00003120 +#define HW_ATL_TS_DATA_OUT_MSK 0x00000FFF +#define HW_ATL_TS_DATA_OUT_SHIFT 0 +#define HW_ATL_TS_DATA_OUT_WIDTH 12 + /* global microprocessor semaphore definitions * base address: 0x000003a0 * parameter: semaphore {s} | stride size 0x4 | range [0, 15] diff --git a/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils.c b/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils.c index bf4c41cc312b..e0cc6caef6f7 100644 --- a/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils.c +++ b/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils.c @@ -1046,6 +1046,7 @@ const struct aq_fw_ops aq_fw_1x_ops = { .set_state = hw_atl_utils_mpi_set_state, .update_link_status = hw_atl_utils_mpi_get_link_status, .update_stats = hw_atl_utils_update_stats, + .get_mac_temp = NULL, .get_phy_temp = NULL, .set_power = aq_fw1x_set_power, .set_eee_rate = NULL, diff --git a/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils_fw2x.c b/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils_fw2x.c index 013676cd38e4..51e58f0c7b00 100644 --- a/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils_fw2x.c +++ b/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils_fw2x.c @@ -681,6 +681,7 @@ const struct aq_fw_ops aq_fw_2x_ops = { .set_state = aq_fw2x_set_state, .update_link_status = aq_fw2x_update_link_status, .update_stats = aq_fw2x_update_stats, + .get_mac_temp = NULL, .get_phy_temp = aq_fw2x_get_phy_temp, .set_power = aq_fw2x_set_power, .set_eee_rate = aq_fw2x_set_eee_rate, diff --git a/drivers/net/ethernet/aquantia/atlantic/hw_atl2/hw_atl2_utils_fw.c b/drivers/net/ethernet/aquantia/atlantic/hw_atl2/hw_atl2_utils_fw.c index a8ce9a2c1c51..85628acbcc1d 100644 --- a/drivers/net/ethernet/aquantia/atlantic/hw_atl2/hw_atl2_utils_fw.c +++ b/drivers/net/ethernet/aquantia/atlantic/hw_atl2/hw_atl2_utils_fw.c @@ -379,6 +379,25 @@ static int aq_a2_fw_update_stats(struct aq_hw_s *self) return 0; } +static int aq_a2_fw_get_phy_temp(struct aq_hw_s *self, int *temp) +{ + struct phy_health_monitor_s phy_health_monitor; + + hw_atl2_shared_buffer_read_safe(self, phy_health_monitor, + &phy_health_monitor); + + *temp = (int8_t)phy_health_monitor.phy_temperature * 1000; + return 0; +} + +static int aq_a2_fw_get_mac_temp(struct aq_hw_s *self, int *temp) +{ + /* There's only one temperature sensor on A2, use it for + * both MAC and PHY. + */ + return aq_a2_fw_get_phy_temp(self, temp); +} + static int aq_a2_fw_set_eee_rate(struct aq_hw_s *self, u32 speed) { struct link_options_s link_options; @@ -510,6 +529,8 @@ const struct aq_fw_ops aq_a2_fw_ops = { .set_state = aq_a2_fw_set_state, .update_link_status = aq_a2_fw_update_link_status, .update_stats = aq_a2_fw_update_stats, + .get_mac_temp = aq_a2_fw_get_mac_temp, + .get_phy_temp = aq_a2_fw_get_phy_temp, .set_eee_rate = aq_a2_fw_set_eee_rate, .get_eee_rate = aq_a2_fw_get_eee_rate, .set_flow_control = aq_a2_fw_set_flow_control,