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Ip=[63.35.35.123]; Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: AM5EUR03FT035.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: HE1PR08MB2668 X-Spam-Status: No, score=-16.1 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, GIT_PATCH_0, MSGID_FROM_MTA_HEADER, RCVD_IN_DNSWL_LOW, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_PASS, TXREP, UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard.Earnshaw@arm.com, nd@arm.com, Marcus.Shawcroft@arm.com Errors-To: gcc-patches-bounces@gcc.gnu.org Sender: "Gcc-patches" Hi All, This patch fixes a couple of issues in AArch64's -mcpu=native processing: The buffer used to read the lines from /proc/cpuinfo is 128 bytes long. While this was enough in the past with the increase in architecture extensions it is no longer enough. It results in two bugs: 1) No option string longer than 127 characters is correctly parsed. Features that are supported are silently ignored. 2) It incorrectly enables features that are not present on the machine: a) It checks for substring matching instead of full word matching. This makes it incorrectly detect sb support when ssbs is provided instead. b) Due to the truncation at the 127 char border it also incorrectly enables features due to the full feature being cut off and the part that is left accidentally enables something else. This breaks -mcpu=native detection on some of our newer system. The patch fixes these issues by reading full lines up to the \n in a string. This gives us the full feature line. Secondly it creates a set from this string to: 1) Reduce matching complexity from O(n*m) to O(n*logm). 2) Perform whole word matching instead of substring matching. To make this code somewhat cleaner I also changed from using char* to using std::string and std::set. Note that I have intentionally avoided the use of ifstream and stringstream to make it easier to backport. I have also not change the substring matching for the initial line classification as I cannot find a documented cpuinfo format which leads me to believe there may be kernels out there that require this which may be why the original code does this. I also do not want this to break if the kernel adds a new line that is long and indents the file by two tabs to keep everything aligned. In short I think an imprecise match is the right thing here. Test for this is added as the last thing in this series as it requires some changes to be made to be able to test this. Bootstrapped Regtested on aarch64-none-linux-gnu and no issues. Ok for master, GCC 10, 9 and 8? Thanks, Tamar gcc/ChangeLog: * config/aarch64/driver-aarch64.c (INCLUDE_SET): New. (parse_field): Use std::string. (split_words, readline): New. (host_detect_local_cpu): Fix truncation issues. diff --git a/gcc/config/aarch64/driver-aarch64.c b/gcc/config/aarch64/driver-aarch64.c index d1229e676806f9607c258e5d678fb3175fadf1c2..3accf3216102a54009af6ece3b2796a55af934ae 100644 --- a/gcc/config/aarch64/driver-aarch64.c +++ b/gcc/config/aarch64/driver-aarch64.c @@ -21,6 +21,7 @@ #include "config.h" #define INCLUDE_STRING +#define INCLUDE_SET #include "system.h" #include "coretypes.h" #include "tm.h" @@ -116,9 +117,9 @@ valid_bL_core_p (unsigned int *core, unsigned int bL_core) /* Returns the hex integer that is after ':' for the FIELD. Returns -1 is returned if there was problem parsing the integer. */ static unsigned -parse_field (const char *field) +parse_field (const std::string field) { - const char *rest = strchr (field, ':'); + const char *rest = strchr (field.c_str (), ':'); char *after; unsigned fint = strtol (rest + 1, &after, 16); if (after == rest + 1) @@ -126,6 +127,57 @@ parse_field (const char *field) return fint; } +/* Splits and returns a string based on whitespace and return it as + part of a set. Empty strings are ignored. */ + +static void +split_words (const std::string val, std::set &result) +{ + size_t cur, prev = 0; + std::string word; + while ((cur = val.find_first_of (" \n", prev)) != std::string::npos) + { + word = val.substr (prev, cur - prev); + /* Skip adding empty words. */ + if (!word.empty ()) + result.insert (word); + prev = cur+1; + } + + word = val.substr (prev, cur - prev); + if (!word.empty ()) + result.insert (word); +} + +/* Read an entire line from F until '\n' or EOF. */ + +static std::string +readline (FILE *f) +{ + char *buf = NULL; + int size = 0; + int last = 0; + const int buf_size = 128; + + if (feof (f)) + return std::string (); + + do + { + size += buf_size; + buf = (char*)xrealloc (buf, size); + gcc_assert (buf); + fgets (buf+last, buf_size, f); + /* If we're not at the end of the line then override the + \0 added by fgets. */ + last = strlen (buf) - 1; + } while (!feof (f) && buf[last]!='\n'); + + std::string result (buf); + free (buf); + return result; +} + /* Return true iff ARR contains CORE, in either of the two elements. */ static bool @@ -164,7 +216,6 @@ host_detect_local_cpu (int argc, const char **argv) { const char *res = NULL; static const int num_exts = ARRAY_SIZE (aarch64_extensions); - char buf[128]; FILE *f = NULL; bool arch = false; bool tune = false; @@ -178,6 +229,7 @@ host_detect_local_cpu (int argc, const char **argv) bool processed_exts = false; uint64_t extension_flags = 0; uint64_t default_flags = 0; + std::string buf; gcc_assert (argc); @@ -202,9 +254,9 @@ host_detect_local_cpu (int argc, const char **argv) /* Look through /proc/cpuinfo to determine the implementer and then the part number that identifies a particular core. */ - while (fgets (buf, sizeof (buf), f) != NULL) + while (!(buf = readline (f)).empty ()) { - if (strstr (buf, "implementer") != NULL) + if (buf.find ("implementer") != std::string::npos) { unsigned cimp = parse_field (buf); if (cimp == INVALID_IMP) @@ -216,8 +268,7 @@ host_detect_local_cpu (int argc, const char **argv) else if (imp != cimp) goto not_found; } - - if (strstr (buf, "variant") != NULL) + else if (buf.find ("variant") != std::string::npos) { unsigned cvariant = parse_field (buf); if (!contains_core_p (variants, cvariant)) @@ -229,8 +280,7 @@ host_detect_local_cpu (int argc, const char **argv) } continue; } - - if (strstr (buf, "part") != NULL) + else if (buf.find ("part") != std::string::npos) { unsigned ccore = parse_field (buf); if (!contains_core_p (cores, ccore)) @@ -242,39 +292,36 @@ host_detect_local_cpu (int argc, const char **argv) } continue; } - if (!tune && !processed_exts && strstr (buf, "Features") != NULL) + else if (!tune && !processed_exts + && buf.find ("Features") != std::string::npos) { + /* First create the list of features in the buffer. */ + std::set features; + /* Drop everything till the :. */ + buf = buf.substr (buf.find (':') + 1); + split_words (buf, features); + for (i = 0; i < num_exts; i++) { - const char *p = aarch64_extensions[i].feat_string; + const std::string val (aarch64_extensions[i].feat_string); /* If the feature contains no HWCAPS string then ignore it for the auto detection. */ - if (*p == '\0') + if (val.empty ()) continue; bool enabled = true; /* This may be a multi-token feature string. We need to match all parts, which could be in any order. */ - size_t len = strlen (buf); - do - { - const char *end = strchr (p, ' '); - if (end == NULL) - end = strchr (p, '\0'); - if (memmem (buf, len, p, end - p) == NULL) - { - /* Failed to match this token. Turn off the - features we'd otherwise enable. */ - enabled = false; - break; - } - if (*end == '\0') - break; - p = end + 1; - } - while (1); + std::set tokens; + split_words (val, tokens); + std::set::iterator it; + + /* Iterate till the first feature isn't found or all of them + are found. */ + for (it = tokens.begin (); enabled && it != tokens.end (); ++it) + enabled = enabled && features.count (*it); if (enabled) extension_flags |= aarch64_extensions[i].flag; From patchwork Thu Jul 9 09:54:49 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tamar Christina X-Patchwork-Id: 1325862 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=sourceware.org; envelope-from=gcc-patches-bounces@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; 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Thu, 9 Jul 2020 09:54:58 +0000 Date: Thu, 9 Jul 2020 10:54:49 +0100 From: Tamar Christina To: gcc-patches@gcc.gnu.org Subject: [PATCH 2/6] AArch64: Add GCC_CPUINFO override Message-ID: <20200709095445.GA31010@arm.com> Content-Disposition: inline User-Agent: Mutt/1.9.4 (2018-02-28) X-ClientProxiedBy: DM5PR07CA0109.namprd07.prod.outlook.com (2603:10b6:4:ae::38) To VI1PR08MB5325.eurprd08.prod.outlook.com (2603:10a6:803:13e::17) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from arm.com (217.140.106.49) by DM5PR07CA0109.namprd07.prod.outlook.com (2603:10b6:4:ae::38) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3174.22 via Frontend Transport; Thu, 9 Jul 2020 09:54:55 +0000 X-Originating-IP: [217.140.106.49] X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-HT: Tenant X-MS-Office365-Filtering-Correlation-Id: c874a2d5-0f24-468a-c375-08d823ee285b X-MS-TrafficTypeDiagnostic: VI1PR08MB4111:|AM6PR08MB4952: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: x-checkrecipientrouted: true NoDisclaimer: true X-MS-Oob-TLC-OOBClassifiers: OLM:7219;OLM:7219; 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Ip=[63.35.35.123]; Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: DB5EUR03FT049.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM6PR08MB4952 X-Spam-Status: No, score=-16.1 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, GIT_PATCH_0, MSGID_FROM_MTA_HEADER, RCVD_IN_DNSWL_LOW, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_PASS, TXREP, UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard.Earnshaw@arm.com, nd@arm.com, Marcus.Shawcroft@arm.com Errors-To: gcc-patches-bounces@gcc.gnu.org Sender: "Gcc-patches" Hi All, This adds an in intentionally undocumented environment variable GCC_CPUINFO which can be used to test -mcpu=native. Tests using this are added later on. Bootstrapped Regtested on aarch64-none-linux-gnu and no issues. Ok for master, GCC 10, 9 and 8? Thanks, Tamar gcc/ChangeLog: * config/aarch64/driver-aarch64.c (host_detect_local_cpu): Add GCC_CPUINFO. diff --git a/gcc/config/aarch64/driver-aarch64.c b/gcc/config/aarch64/driver-aarch64.c index 78616379189e80e75a28973f6b90ca4ca287e4bc..498350f5588e1109472ed95a61f1021d697eb057 100644 --- a/gcc/config/aarch64/driver-aarch64.c +++ b/gcc/config/aarch64/driver-aarch64.c @@ -230,6 +230,7 @@ host_detect_local_cpu (int argc, const char **argv) uint64_t extension_flags = 0; uint64_t default_flags = 0; std::string buf; + char *fcpu_info; gcc_assert (argc); @@ -247,7 +248,11 @@ host_detect_local_cpu (int argc, const char **argv) if (!arch && !tune && !cpu) goto not_found; - f = fopen ("/proc/cpuinfo", "r"); + fcpu_info = getenv ("GCC_CPUINFO"); + if (fcpu_info) + f = fopen (fcpu_info, "r"); + else + f = fopen ("/proc/cpuinfo", "r"); if (f == NULL) goto not_found; From patchwork Thu Jul 9 09:55:26 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tamar Christina X-Patchwork-Id: 1325863 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; 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Tests using these are added later on. Bootstrapped Regtested on arm-none-linux-gnueabihf and no issues. Ok for master, GCC 10, 9 and 8? Thanks, Tamar gcc/ChangeLog: * config/arm/driver-arm.c (host_detect_local_cpu): Add GCC_CPUINFO. diff --git a/gcc/config/arm/driver-arm.c b/gcc/config/arm/driver-arm.c index 254e5ba53a6130183cf7561913943765a3a56898..85058f257c9d34f31c395c5d4502f73a7f00625e 100644 --- a/gcc/config/arm/driver-arm.c +++ b/gcc/config/arm/driver-arm.c @@ -61,6 +61,7 @@ host_detect_local_cpu (int argc, const char **argv) FILE *f = NULL; bool arch; const struct vendor_cpu *cpu_table = NULL; + char *fcpu_info = NULL; if (argc < 1) goto not_found; @@ -69,7 +70,12 @@ host_detect_local_cpu (int argc, const char **argv) if (!arch && strcmp (argv[0], "cpu") != 0 && strcmp (argv[0], "tune")) goto not_found; - f = fopen ("/proc/cpuinfo", "r"); + fcpu_info = getenv ("GCC_CPUINFO"); + if (fcpu_info) + f = fopen (fcpu_info, "r"); + else + f = fopen ("/proc/cpuinfo", "r"); + if (f == NULL) goto not_found; From patchwork Thu Jul 9 09:56:35 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tamar Christina X-Patchwork-Id: 1325865 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; 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X-Microsoft-Antispam-Message-Info: Dm1gTsMYji5Z7kTkOBJIAggV4U7GteKZqOi1jEZhh3K8WaowF0azP11kNCnz7w1DeRDh2GSTyATV78MTiFOSWPOgLkIB4E+ZnuOm3W07TZkRlLlCjQf3WZVp3uUAWkpH0XagzXII7gXi3heHKUJn00h9NDTad77fae3bd0Vf2kJlreCvUAUV3Qfbd900QsXypW9gTScRv8HZSdD9rrl+8fJLrWTVLONhVh099MpsRLGbpd0R6Oi4zK0W6w2RZr93+Bhi8IwuqUDSdXo+HMIlW1ifJ9M7k6VX2eIQXnC/g0CzjOCcn7pk5cF3q9wjHr09ztYIRi0mOUa/BNTY2c6Cwkso+YKQOhNm0bElfgKijz5a1J26jMAaTK8RqbuQvuhUawo1/9Zm4mGtA1exooZy0gPafDJcujnu36CW8N+b/iU= X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Jul 2020 09:56:44.3342 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1d90d105-b61c-4508-6978-08d823ee6305 X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d; Ip=[63.35.35.123]; Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: DB5EUR03FT042.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: VI1PR0802MB2413 X-Spam-Status: No, score=-16.1 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, GIT_PATCH_0, MSGID_FROM_MTA_HEADER, RCVD_IN_DNSWL_LOW, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_PASS, TXREP, UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: nd@arm.com Errors-To: gcc-patches-bounces@gcc.gnu.org Sender: "Gcc-patches" Hi All, This adds verbose output to dg-set-compiler-env-var and dg-set-target-env-var so you can actually see what they're setting when you add -v -v. Bootstrapped Regtested on aarch64-none-linux-gnu and no issues. Ok for master? Thanks, Tamar gcc/testsuite/ChangeLog: * lib/gcc-dg.exp (dg-set-compiler-env-var, dg-set-target-env-var): Add verbose output. diff --git a/gcc/testsuite/lib/gcc-dg.exp b/gcc/testsuite/lib/gcc-dg.exp index 27cc7c19625d8bff12268de16ec0c20d558394b7..ccf6b7cc70b1d4268c0b0c65f960fb42deab0d88 100644 --- a/gcc/testsuite/lib/gcc-dg.exp +++ b/gcc/testsuite/lib/gcc-dg.exp @@ -477,7 +477,10 @@ proc dg-set-target-env-var { args } { error "dg-set-target-env-var: need two arguments" return } - lappend set_target_env_var [list [lindex $args 1] [lindex $args 2]] + set var [lindex $args 1] + set value [lindex $args 2] + verbose "dg-set-compiler-env-var $var $value" 2 + lappend set_target_env_var [list $var $value] } proc set-target-env-var { } { @@ -518,6 +521,7 @@ proc dg-set-compiler-env-var { args } { } set var [lindex $args 1] set value [lindex $args 2] + verbose "dg-set-compiler-env-var $var $value" 2 if [info exists ::env($var)] { lappend saved_compiler_env_var [list $var 1 $::env($var)] } else { From patchwork Thu Jul 9 09:57:41 2020 Content-Type: text/plain; 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Bootstrapped Regtested on aarch64-none-linux-gnu and no issues. Ok for master? Thanks, Tamar gcc/ChangeLog: * doc/sourcebuild.texi (dg-set-compiler-env-var, dg-set-target-env-var): Document. diff --git a/gcc/doc/sourcebuild.texi b/gcc/doc/sourcebuild.texi index 5b5b845afe6e8c8836bad73872797a10b4921cea..b025b3de186ce135d029bf0874ef420a90bb8fc2 100644 --- a/gcc/doc/sourcebuild.texi +++ b/gcc/doc/sourcebuild.texi @@ -1244,6 +1244,18 @@ This DejaGnu directive compares @var{regexp} to the combined output that the test executable writes to @file{stdout} and @file{stderr}. @end table +@subsubsection Specify environment variables for a test + +@table @code +@item @{ dg-set-compiler-env-var @var{var_name} "@var{var_value}" @} +Specify that the environment variable @var{var_name} needs to be set +to @var{var_value} before invoking the compiler on the test file. + +@item @{ dg-set-target-env-var @var{var_name} "@var{var_value}" @} +Specify that the environment variable @var{var_name} needs to be set +to @var{var_value} before execution of the program created by the test. +@end table + @subsubsection Specify additional files for a test @table @code From patchwork Thu Jul 9 09:58:11 2020 Content-Type: text/plain; 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X-Microsoft-Antispam-Message-Info: gHp2Zj/NB+f0sw5Na8jnzS2Wox5V43mlNk/jbsP5WfinllA5Gueql4v7Qou3leLdpa+Ggbp+JNEgdc9mY4xHJN9mFh68cGImAm6xJ5ttT0+BLD+DFQRPYMJBSSwYpQ6r8IoIIOzbvJQMxTze18W6ZRSZy+/h0+urjssmWZ7JZuFKnFSo0CIKUetKHifTq2PMldCRytNY2I+ea7Mi7p4I55I374iTyuOQgpzVTqanCw+yXWYSySm4x0KkDSVJQMWYUX+UvDIifzMQ7/RUBRl8kv8zzaxCQtibhbGhe3MMSmLplTNHacmAlJxoLuwZ+xKtqV7OCQyMfnlcRk55C3llAuCrKIsdgyXHEfPt5TRP4aXRkFfmD9YILtm+bMFmJy7VlgPDOhtTGn/OGQW/ASna2hPpPIxtNpTqtvddjONqqWQ= X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Jul 2020 09:58:21.0184 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 93069890-d62c-4ceb-1a3e-08d823ee9cb6 X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d; Ip=[63.35.35.123]; Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: VE1EUR03FT032.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: HE1PR08MB2843 X-Spam-Status: No, score=-16.0 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, GIT_PATCH_0, KAM_LOTSOFHASH, KAM_SHORT, MSGID_FROM_MTA_HEADER, RCVD_IN_DNSWL_LOW, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_PASS, TXREP, UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard.Earnshaw@arm.com, nd@arm.com, Marcus.Shawcroft@arm.com Errors-To: gcc-patches-bounces@gcc.gnu.org Sender: "Gcc-patches" Hi All, This adds some tests to the GCC testsuite for testing the -mcpu=native code. Bootstrapped Regtested on aarch64-none-linux-gnu and no issues. Ok for master, GCC 10, 9 and 8? Thanks, Tamar gcc/testsuite/ChangeLog: * gcc.target/aarch64/cpunative/aarch64-cpunative.exp: New test. * gcc.target/aarch64/cpunative/info_0: New test. * gcc.target/aarch64/cpunative/info_1: New test. * gcc.target/aarch64/cpunative/info_10: New test. * gcc.target/aarch64/cpunative/info_11: New test. * gcc.target/aarch64/cpunative/info_12: New test. * gcc.target/aarch64/cpunative/info_13: New test. * gcc.target/aarch64/cpunative/info_14: New test. * gcc.target/aarch64/cpunative/info_15: New test. * gcc.target/aarch64/cpunative/info_2: New test. * gcc.target/aarch64/cpunative/info_3: New test. * gcc.target/aarch64/cpunative/info_4: New test. * gcc.target/aarch64/cpunative/info_5: New test. * gcc.target/aarch64/cpunative/info_6: New test. * gcc.target/aarch64/cpunative/info_7: New test. * gcc.target/aarch64/cpunative/info_8: New test. * gcc.target/aarch64/cpunative/info_9: New test. * gcc.target/aarch64/cpunative/native_cpu_0.c: New test. * gcc.target/aarch64/cpunative/native_cpu_1.c: New test. * gcc.target/aarch64/cpunative/native_cpu_10.c: New test. * gcc.target/aarch64/cpunative/native_cpu_11.c: New test. * gcc.target/aarch64/cpunative/native_cpu_12.c: New test. * gcc.target/aarch64/cpunative/native_cpu_13.c: New test. * gcc.target/aarch64/cpunative/native_cpu_14.c: New test. * gcc.target/aarch64/cpunative/native_cpu_15.c: New test. * gcc.target/aarch64/cpunative/native_cpu_2.c: New test. * gcc.target/aarch64/cpunative/native_cpu_3.c: New test. * gcc.target/aarch64/cpunative/native_cpu_4.c: New test. * gcc.target/aarch64/cpunative/native_cpu_5.c: New test. * gcc.target/aarch64/cpunative/native_cpu_6.c: New test. * gcc.target/aarch64/cpunative/native_cpu_7.c: New test. * gcc.target/aarch64/cpunative/native_cpu_8.c: New test. * gcc.target/aarch64/cpunative/native_cpu_9.c: New test. diff --git a/gcc/testsuite/gcc.target/aarch64/cpunative/aarch64-cpunative.exp b/gcc/testsuite/gcc.target/aarch64/cpunative/aarch64-cpunative.exp new file mode 100644 index 0000000000000000000000000000000000000000..ce80ca04b8d095c96acf0bda4d5b16a6460c4cbd --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/cpunative/aarch64-cpunative.exp @@ -0,0 +1,35 @@ +# Copyright (C) 2014-2020 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with GCC; see the file COPYING3. If not see +# . + +# GCC testsuite that uses the `dg.exp' driver. + +# Exit immediately if this isn't an AArch64 target. +if ![istarget aarch64*-*-*] then { + return +} + +# Load support procs. +load_lib gcc-dg.exp + +# Initialize `dg'. +dg-init + +# Main loop. +dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.\[cCS\]]] \ + "" "" + +# All done. +dg-finish diff --git a/gcc/testsuite/gcc.target/aarch64/cpunative/info_0 b/gcc/testsuite/gcc.target/aarch64/cpunative/info_0 new file mode 100644 index 0000000000000000000000000000000000000000..ef4a3f606fa56bc7ef1e951c1896737f013f78a6 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/cpunative/info_0 @@ -0,0 +1,8 @@ +processor : 0 +BogoMIPS : 100.00 +Features : fp asimd evtstrm aes pmull sha1 sha2 crc32 asimddp +CPU implementer : 0x41 +CPU architecture: 8 +CPU variant : 0x0 +CPU part : 0xd08 +CPU revision : 2 diff --git a/gcc/testsuite/gcc.target/aarch64/cpunative/info_1 b/gcc/testsuite/gcc.target/aarch64/cpunative/info_1 new file mode 100644 index 0000000000000000000000000000000000000000..0f434bca28521f678bcee9f407f34ef813e7f1f1 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/cpunative/info_1 @@ -0,0 +1,8 @@ +processor : 0 +BogoMIPS : 100.00 +Features : fp +CPU implementer : 0x41 +CPU architecture: 8 +CPU variant : 0x0 +CPU part : 0xd08 +CPU revision : 2 diff --git a/gcc/testsuite/gcc.target/aarch64/cpunative/info_10 b/gcc/testsuite/gcc.target/aarch64/cpunative/info_10 new file mode 100644 index 0000000000000000000000000000000000000000..c6e9d7ca9e274a0be8a75bd7056dad958aa53cb4 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/cpunative/info_10 @@ -0,0 +1,8 @@ +processor : 0 +BogoMIPS : 100.00 +Features : +CPU implementer : 0x41 +CPU architecture: 8 +CPU variant : 0x0 +CPU part : 0xd08 +CPU revision : 2 diff --git a/gcc/testsuite/gcc.target/aarch64/cpunative/info_11 b/gcc/testsuite/gcc.target/aarch64/cpunative/info_11 new file mode 100644 index 0000000000000000000000000000000000000000..fb76f7d45bcd8238e49d3dedb1dab5265cbae982 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/cpunative/info_11 @@ -0,0 +1,8 @@ +processor : 0 +BogoMIPS : 100.00 +Features : asimd fp sb +CPU implementer : 0x41 +CPU architecture: 8 +CPU variant : 0x0 +CPU part : 0xd08 +CPU revision : 2 diff --git a/gcc/testsuite/gcc.target/aarch64/cpunative/info_12 b/gcc/testsuite/gcc.target/aarch64/cpunative/info_12 new file mode 100644 index 0000000000000000000000000000000000000000..9b6aa7bc248530eb794dad5d874a78dc9c06851b --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/cpunative/info_12 @@ -0,0 +1,8 @@ +processor : 0 +BogoMIPS : 100.00 +Features : asimd fp ssbs +CPU implementer : 0x41 +CPU architecture: 8 +CPU variant : 0x0 +CPU part : 0xd08 +CPU revision : 2 diff --git a/gcc/testsuite/gcc.target/aarch64/cpunative/info_13 b/gcc/testsuite/gcc.target/aarch64/cpunative/info_13 new file mode 100644 index 0000000000000000000000000000000000000000..ef4a3f606fa56bc7ef1e951c1896737f013f78a6 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/cpunative/info_13 @@ -0,0 +1,8 @@ +processor : 0 +BogoMIPS : 100.00 +Features : fp asimd evtstrm aes pmull sha1 sha2 crc32 asimddp +CPU implementer : 0x41 +CPU architecture: 8 +CPU variant : 0x0 +CPU part : 0xd08 +CPU revision : 2 diff --git a/gcc/testsuite/gcc.target/aarch64/cpunative/info_14 b/gcc/testsuite/gcc.target/aarch64/cpunative/info_14 new file mode 100644 index 0000000000000000000000000000000000000000..338975715132ed6e55c2d34514ad20294b7018ee --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/cpunative/info_14 @@ -0,0 +1,8 @@ +processor : 0 +BogoMIPS : 100.00 +Features : Lorem ipsum dolor sit ametd rebum expetendis per at Dolor lucilius referrentur ei mei virtute eruditi eum ne Iisque verterem tacimates eu mea ei autem asimd fp asimddp +CPU implementer : 0x41 +CPU architecture: 8 +CPU variant : 0x0 +CPU part : 0xd08 +CPU revision : 2 diff --git a/gcc/testsuite/gcc.target/aarch64/cpunative/info_15 b/gcc/testsuite/gcc.target/aarch64/cpunative/info_15 new file mode 100644 index 0000000000000000000000000000000000000000..bc6453945561044ab09ec2dba851eb88829c483b --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/cpunative/info_15 @@ -0,0 +1,8 @@ +processor : 0 +BogoMIPS : 100.00 +Features : Lorem ipsum dolor sit ametd rebum expetendis per at Dolor lucilius referrentur ei mei virtute eruditi eum ne Iisque verter svesm4 asimd fp +CPU implementer : 0x41 +CPU architecture: 8 +CPU variant : 0x0 +CPU part : 0xd08 +CPU revision : 2 diff --git a/gcc/testsuite/gcc.target/aarch64/cpunative/info_2 b/gcc/testsuite/gcc.target/aarch64/cpunative/info_2 new file mode 100644 index 0000000000000000000000000000000000000000..965d37760ac34a456a6463c9e1baae152e966040 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/cpunative/info_2 @@ -0,0 +1,8 @@ +processor : 0 +BogoMIPS : 100.00 +Features : asimd +CPU implementer : 0x41 +CPU architecture: 8 +CPU variant : 0x0 +CPU part : 0xd08 +CPU revision : 2 diff --git a/gcc/testsuite/gcc.target/aarch64/cpunative/info_3 b/gcc/testsuite/gcc.target/aarch64/cpunative/info_3 new file mode 100644 index 0000000000000000000000000000000000000000..0c276f884a8365b8aa66b7c08f12f3e6cfead497 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/cpunative/info_3 @@ -0,0 +1,8 @@ +processor : 0 +BogoMIPS : 100.00 +Features : asimd fp +CPU implementer : 0x41 +CPU architecture: 8 +CPU variant : 0x0 +CPU part : 0xd08 +CPU revision : 2 diff --git a/gcc/testsuite/gcc.target/aarch64/cpunative/info_4 b/gcc/testsuite/gcc.target/aarch64/cpunative/info_4 new file mode 100644 index 0000000000000000000000000000000000000000..716210c14175ef5af956af2e40ecd188451bf54b --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/cpunative/info_4 @@ -0,0 +1,8 @@ +processor : 0 +BogoMIPS : 100.00 +Features : asimd fp aes pmull sha1 sha2 +CPU implementer : 0x41 +CPU architecture: 8 +CPU variant : 0x0 +CPU part : 0xd08 +CPU revision : 2 diff --git a/gcc/testsuite/gcc.target/aarch64/cpunative/info_5 b/gcc/testsuite/gcc.target/aarch64/cpunative/info_5 new file mode 100644 index 0000000000000000000000000000000000000000..7a002e1c4c8192fcb541de8f90603bd27e793e72 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/cpunative/info_5 @@ -0,0 +1,8 @@ +processor : 0 +BogoMIPS : 100.00 +Features : asimd fp fphp asimdhp +CPU implementer : 0x41 +CPU architecture: 8 +CPU variant : 0x0 +CPU part : 0xd08 +CPU revision : 2 diff --git a/gcc/testsuite/gcc.target/aarch64/cpunative/info_6 b/gcc/testsuite/gcc.target/aarch64/cpunative/info_6 new file mode 100644 index 0000000000000000000000000000000000000000..d341dfe86f4c6d68a085389954197d29f32d5992 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/cpunative/info_6 @@ -0,0 +1,8 @@ +processor : 0 +BogoMIPS : 100.00 +Features : asimd fp aes pmull sha1 sha2 fphp asimdhp +CPU implementer : 0x41 +CPU architecture: 8 +CPU variant : 0x0 +CPU part : 0xd08 +CPU revision : 2 diff --git a/gcc/testsuite/gcc.target/aarch64/cpunative/info_7 b/gcc/testsuite/gcc.target/aarch64/cpunative/info_7 new file mode 100644 index 0000000000000000000000000000000000000000..ccb784915d517b44cdfba7dec01047ad085e685b --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/cpunative/info_7 @@ -0,0 +1,8 @@ +processor : 0 +BogoMIPS : 100.00 +Features : asimd pmull sha1 fp aes sha2 fphp asimdhp +CPU implementer : 0x41 +CPU architecture: 8 +CPU variant : 0x0 +CPU part : 0xd08 +CPU revision : 2 diff --git a/gcc/testsuite/gcc.target/aarch64/cpunative/info_8 b/gcc/testsuite/gcc.target/aarch64/cpunative/info_8 new file mode 100644 index 0000000000000000000000000000000000000000..d6d9d03a2a26c2196ddae770411479bf71725d59 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/cpunative/info_8 @@ -0,0 +1,8 @@ +processor : 0 +BogoMIPS : 100.00 +Features : asimd sve fp +CPU implementer : 0x41 +CPU architecture: 8 +CPU variant : 0x0 +CPU part : 0xd08 +CPU revision : 2 diff --git a/gcc/testsuite/gcc.target/aarch64/cpunative/info_9 b/gcc/testsuite/gcc.target/aarch64/cpunative/info_9 new file mode 100644 index 0000000000000000000000000000000000000000..c9aa4a9a07df4df4a7a4642fed6f664cdf8da4b3 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/cpunative/info_9 @@ -0,0 +1,8 @@ +processor : 0 +BogoMIPS : 100.00 +Features : asimd fp svesm4 +CPU implementer : 0x41 +CPU architecture: 8 +CPU variant : 0x0 +CPU part : 0xd08 +CPU revision : 2 diff --git a/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_0.c b/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_0.c new file mode 100644 index 0000000000000000000000000000000000000000..f155f51bae734a62b39867fc1a0adec65fb552de --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_0.c @@ -0,0 +1,12 @@ +/* { dg-do compile { target { { aarch64*-*-linux*} && native } } } */ +/* { dg-set-compiler-env-var GCC_CPUINFO "$srcdir/gcc.target/aarch64/cpunative/info_0" } */ +/* { dg-additional-options "-mcpu=native" } */ + +int main() +{ + return 0; +} + +/* { dg-final { scan-assembler {\.arch armv8-a\+crypto\+crc\+dotprod} } } */ + +/* Test a normal looking procinfo. */ diff --git a/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_1.c b/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_1.c new file mode 100644 index 0000000000000000000000000000000000000000..2cf0e89994b1cc0dc9fac67f4dc431c003498048 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_1.c @@ -0,0 +1,12 @@ +/* { dg-do compile { target { { aarch64*-*-linux*} && native } } } */ +/* { dg-set-compiler-env-var GCC_CPUINFO "$srcdir/gcc.target/aarch64/cpunative/info_1" } */ +/* { dg-additional-options "-mcpu=native" } */ + +int main() +{ + return 0; +} + +/* { dg-final { scan-assembler {\.arch armv8-a\+nosimd} } } */ + +/* Test one where fp is on by default so turn off simd. */ diff --git a/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_10.c b/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_10.c new file mode 100644 index 0000000000000000000000000000000000000000..6a753965c527fd7f27851c5e8e474ec900a1a75a --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_10.c @@ -0,0 +1,12 @@ +/* { dg-do compile { target { { aarch64*-*-linux*} && native } } } */ +/* { dg-set-compiler-env-var GCC_CPUINFO "$srcdir/gcc.target/aarch64/cpunative/info_10" } */ +/* { dg-additional-options "-mcpu=native" } */ + +int main() +{ + return 0; +} + +/* { dg-final { scan-assembler {\.arch armv8-a\+nofp\+nosimd} } } */ + +/* Test one with no entry in feature list. */ diff --git a/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_11.c b/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_11.c new file mode 100644 index 0000000000000000000000000000000000000000..96b9ca434ebbf007ddaa45d55a8c2b8e7a19a715 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_11.c @@ -0,0 +1,12 @@ +/* { dg-do compile { target { { aarch64*-*-linux*} && native } } } */ +/* { dg-set-compiler-env-var GCC_CPUINFO "$srcdir/gcc.target/aarch64/cpunative/info_11" } */ +/* { dg-additional-options "-mcpu=native" } */ + +int main() +{ + return 0; +} + +/* { dg-final { scan-assembler {\.arch armv8-a\+sb} } } */ + +/* Test one with a feature name that overlaps with another one. */ diff --git a/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_12.c b/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_12.c new file mode 100644 index 0000000000000000000000000000000000000000..c3b44adbf6c8a02c5003049eed2ed453587b8ad4 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_12.c @@ -0,0 +1,12 @@ +/* { dg-do compile { target { { aarch64*-*-linux*} && native } } } */ +/* { dg-set-compiler-env-var GCC_CPUINFO "$srcdir/gcc.target/aarch64/cpunative/info_12" } */ +/* { dg-additional-options "-mcpu=native" } */ + +int main() +{ + return 0; +} + +/* { dg-final { scan-assembler {\.arch armv8-a\+ssbs} } } */ + +/* Test one where the longer feature overlaps with a shorter one. */ diff --git a/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_13.c b/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_13.c new file mode 100644 index 0000000000000000000000000000000000000000..b7b3a8e13dfbda887f80b9e5c8f5416c153e0d65 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_13.c @@ -0,0 +1,12 @@ +/* { dg-do compile { target { { aarch64*-*-linux*} && native } } } */ +/* { dg-set-compiler-env-var GCC_CPUINFO "$srcdir/gcc.target/aarch64/cpunative/info_13" } */ +/* { dg-additional-options "-mcpu=native" } */ + +int main() +{ + return 0; +} + +/* { dg-final { scan-assembler {\.arch armv8-a\+crypto\+crc\+dotprod} } } */ + +/* Test one with mixed order of feature bits. */ diff --git a/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_14.c b/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_14.c new file mode 100644 index 0000000000000000000000000000000000000000..781ab1ebbfb46901ea38cd0063d984e372839ecd --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_14.c @@ -0,0 +1,12 @@ +/* { dg-do compile { target { { aarch64*-*-linux*} && native } } } */ +/* { dg-set-compiler-env-var GCC_CPUINFO "$srcdir/gcc.target/aarch64/cpunative/info_14" } */ +/* { dg-additional-options "-mcpu=native" } */ + +int main() +{ + return 0; +} + +/* { dg-final { scan-assembler {\.arch armv8-a\+dotprod} } } */ + +/* Test one where valid feature bits are at a boundary > buffer size. */ diff --git a/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_15.c b/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_15.c new file mode 100644 index 0000000000000000000000000000000000000000..c9205d95b793c27cd61982b9262bbbcc4912ec6d --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_15.c @@ -0,0 +1,15 @@ +/* { dg-do compile { target { { aarch64*-*-linux*} && native } } } */ +/* { dg-set-compiler-env-var GCC_CPUINFO "$srcdir/gcc.target/aarch64/cpunative/info_15" } */ +/* { dg-additional-options "-mcpu=native" } */ + +int main() +{ + return 0; +} + +/* { dg-final { scan-assembler {\.arch armv8-a\+sve2-sm4} } } */ + +/* Test one where the bounary of buffer size would cut off and leave + a valid feature in the first full buffer. e.g. this will cut off at + sve leaving 2-sm4 to yet be read. Check that this doesn't enable + +sve by mistake. */ diff --git a/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_2.c b/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_2.c new file mode 100644 index 0000000000000000000000000000000000000000..aad71f4347d2f8e8bb7270db2f8534bf3a198e9e --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_2.c @@ -0,0 +1,12 @@ +/* { dg-do compile { target { { aarch64*-*-linux*} && native } } } */ +/* { dg-set-compiler-env-var GCC_CPUINFO "$srcdir/gcc.target/aarch64/cpunative/info_2" } */ +/* { dg-additional-options "-mcpu=native" } */ + +int main() +{ + return 0; +} + +/* { dg-final { scan-assembler {\.arch armv8-a\+nofp\+nosimd} } } */ + +/* Test one where asimd is provided byt no fp. */ diff --git a/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_3.c b/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_3.c new file mode 100644 index 0000000000000000000000000000000000000000..50685c297dbd7549ee1ea190dbfdb9dd90f3af12 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_3.c @@ -0,0 +1,13 @@ +/* { dg-do compile { target { { aarch64*-*-linux*} && native } } } */ +/* { dg-set-compiler-env-var GCC_CPUINFO "$srcdir/gcc.target/aarch64/cpunative/info_3" } */ +/* { dg-additional-options "-mcpu=native" } */ + +int main() +{ + return 0; +} + +/* { dg-final { scan-assembler {\.arch armv8-a} } } */ + +/* Test where asimd and fp are the only ones provided, these are default + and so shouldn't emit anything. */ diff --git a/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_4.c b/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_4.c new file mode 100644 index 0000000000000000000000000000000000000000..91ae809757a4e31bf946fc27ec33f51001b0d3e8 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_4.c @@ -0,0 +1,12 @@ +/* { dg-do compile { target { { aarch64*-*-linux*} && native } } } */ +/* { dg-set-compiler-env-var GCC_CPUINFO "$srcdir/gcc.target/aarch64/cpunative/info_4" } */ +/* { dg-additional-options "-mcpu=native" } */ + +int main() +{ + return 0; +} + +/* { dg-final { scan-assembler {\.arch armv8-a\+crypto} } } */ + +/* Test one where all crypto bits are given so crypto should be enabled. */ diff --git a/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_5.c b/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_5.c new file mode 100644 index 0000000000000000000000000000000000000000..84139e58ee0000816c4ea24f27bc28f5f6563bac --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_5.c @@ -0,0 +1,12 @@ +/* { dg-do compile { target { { aarch64*-*-linux*} && native } } } */ +/* { dg-set-compiler-env-var GCC_CPUINFO "$srcdir/gcc.target/aarch64/cpunative/info_5" } */ +/* { dg-additional-options "-mcpu=native" } */ + +int main() +{ + return 0; +} + +/* { dg-final { scan-assembler {\.arch armv8-a\+fp16} } } */ + +/* Test one where fp16 is available and so should be emitted. */ diff --git a/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_6.c b/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_6.c new file mode 100644 index 0000000000000000000000000000000000000000..da72052e62385c9251d25f792b679263a18d9e61 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_6.c @@ -0,0 +1,13 @@ +/* { dg-do compile { target { { aarch64*-*-linux*} && native } } } */ +/* { dg-set-compiler-env-var GCC_CPUINFO "$srcdir/gcc.target/aarch64/cpunative/info_6" } */ +/* { dg-additional-options "-mcpu=native" } */ + +int main() +{ + return 0; +} + +/* { dg-final { scan-assembler {\.arch armv8-a\+crypto\+fp16} } } */ + +/* Test one where the feature bits for crypto and fp16 are given in + same order as declared in options file. */ diff --git a/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_7.c b/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_7.c new file mode 100644 index 0000000000000000000000000000000000000000..96ad4c14db16468df30cc0a00d709ed5e2f32ed9 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_7.c @@ -0,0 +1,13 @@ +/* { dg-do compile { target { { aarch64*-*-linux*} && native } } } */ +/* { dg-set-compiler-env-var GCC_CPUINFO "$srcdir/gcc.target/aarch64/cpunative/info_7" } */ +/* { dg-additional-options "-mcpu=native" } */ + +int main() +{ + return 0; +} + +/* { dg-final { scan-assembler {\.arch armv8-a\+crypto\+fp16} } } */ + +/* Test one where the crypto and fp16 options are specified in different + order from what is in the options file. */ diff --git a/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_8.c b/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_8.c new file mode 100644 index 0000000000000000000000000000000000000000..7a5a2144a3973406b9ba7d268029a6940fb0be48 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_8.c @@ -0,0 +1,12 @@ +/* { dg-do compile { target { { aarch64*-*-linux*} && native } } } */ +/* { dg-set-compiler-env-var GCC_CPUINFO "$srcdir/gcc.target/aarch64/cpunative/info_8" } */ +/* { dg-additional-options "-mcpu=native" } */ + +int main() +{ + return 0; +} + +/* { dg-final { scan-assembler {\.arch armv8-a\+sve} } } */ + +/* Test one where sve is enabled. */ diff --git a/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_9.c b/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_9.c new file mode 100644 index 0000000000000000000000000000000000000000..528b5d029f1a21c8388a30120590c1b8d5b4a81f --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_9.c @@ -0,0 +1,14 @@ +/* { dg-do compile { target { { aarch64*-*-linux*} && native } } } */ +/* { dg-set-compiler-env-var GCC_CPUINFO "$srcdir/gcc.target/aarch64/cpunative/info_9" } */ +/* { dg-additional-options "-mcpu=native" } */ + +int main() +{ + return 0; +} + +/* { dg-final { scan-assembler {\.arch armv8-a\+sve2-sm4} } } */ + +/* Test one here a feature that is a prefix of another is enabled. + In this case sve is a prefix to svesm4, but sve2-sm4 should be + enabled. */