From patchwork Thu Jun 4 13:21:16 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?C=C3=A9dric_Le_Goater?= X-Patchwork-Id: 1303544 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 49d6Ct1G3bz9sSf for ; Thu, 4 Jun 2020 23:32:58 +1000 (AEST) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=kaod.org Received: from bilbo.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 49d6Cs6BMNzDqtR for ; Thu, 4 Jun 2020 23:32:57 +1000 (AEST) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=kaod.org (client-ip=178.33.251.19; helo=14.mo7.mail-out.ovh.net; envelope-from=clg@kaod.org; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=none (p=none dis=none) header.from=kaod.org Received: from 14.mo7.mail-out.ovh.net (14.mo7.mail-out.ovh.net [178.33.251.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 49d69p2MqmzDqdh for ; Thu, 4 Jun 2020 23:31:10 +1000 (AEST) Received: from player739.ha.ovh.net (unknown [10.110.103.115]) by mo7.mail-out.ovh.net (Postfix) with ESMTP id 914D7168558 for ; Thu, 4 Jun 2020 15:21:36 +0200 (CEST) Received: from kaod.org (82-64-250-170.subs.proxad.net [82.64.250.170]) (Authenticated sender: clg@kaod.org) by player739.ha.ovh.net (Postfix) with ESMTPSA id D7A14F0261B2; Thu, 4 Jun 2020 13:21:31 +0000 (UTC) Authentication-Results: garm.ovh; auth=pass (GARM-105G00683ced65e-83de-4119-84c3-10315e3c0f9d, 2E0AA79A099E542C5FE1C9A79F210F9E9C727315) smtp.auth=clg@kaod.org From: =?utf-8?q?C=C3=A9dric_Le_Goater?= To: skiboot@lists.ozlabs.org Date: Thu, 4 Jun 2020 15:21:16 +0200 Message-Id: <20200604132126.750999-2-clg@kaod.org> X-Mailer: git-send-email 2.25.4 In-Reply-To: <20200604132126.750999-1-clg@kaod.org> References: <20200604132126.750999-1-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 17681132138012904409 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgeduhedrudeguddgieduucetufdoteggodetrfdotffvucfrrhhofhhilhgvmecuqfggjfdpvefjgfevmfevgfenuceurghilhhouhhtmecuhedttdenucesvcftvggtihhpihgvnhhtshculddquddttddmnecujfgurhephffvufffkffojghfgggtgfesthekredtredtjeenucfhrhhomhepveorughrihgtucfnvgcuifhorghtvghruceotghlgheskhgrohgurdhorhhgqeenucggtffrrghtthgvrhhnpefgieetvdefudeghedvveejudeihfeiteffjeetjeeukefhgffgvedugedugedugfenucfkpheptddrtddrtddrtddpkedvrdeigedrvdehtddrudejtdenucevlhhushhtvghrufhiiigvpedtnecurfgrrhgrmhepmhhouggvpehsmhhtphdqohhuthdphhgvlhhopehplhgrhigvrhejfeelrdhhrgdrohhvhhdrnhgvthdpihhnvghtpedtrddtrddtrddtpdhmrghilhhfrhhomheptghlgheskhgrohgurdhorhhgpdhrtghpthhtohepshhkihgsohhotheslhhishhtshdrohiilhgrsghsrdhorhhg Subject: [Skiboot] [PATCH 01/11] xive/p9: Introduce XIVE_INT_ORDER X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" The size of the interrupt number space is constrained by the block and index fields of the trigger data exchanged between source units and the XIVE IC. These are respectively 4 and 28 bits, which gives us a 32 bits interrupt number space. But the XICS emulation requires 8 bits to encode the CPPR value. The system interrupt number space is therefore constrained to 24 bits and on a chip, to 20 bits because the XIVE driver configures the HW to use one block per chip. XIVE_INT_ORDER defines the size of the interrupt number space : 1M per chip. To control these interrupts, the driver defines in the VC BAR of the controller a range of 384G of ESB pages giving access to 3M interrupts. The VSD for the memory table is smaller than the index and accesses to some ESB pages are not backed by a memory table structure. If such an access occurred, it would result in a FIR. It never happened but this is something to fix with a finer configuration of the VC BAR. Signed-off-by: Cédric Le Goater --- hw/xive.c | 32 ++++++++++++++++++-------------- 1 file changed, 18 insertions(+), 14 deletions(-) /* Reset IPI allocation */ xive_dbg(x, "freeing alloc map %p/%p\n", x->ipi_alloc_map, *x->ipi_alloc_map); - memset(x->ipi_alloc_map, 0, BITMAP_BYTES(MAX_INT_ENTRIES)); + memset(x->ipi_alloc_map, 0, BITMAP_BYTES(XIVE_INT_COUNT)); xive_dbg(x, "Resetting EQs...\n"); diff --git a/hw/xive.c b/hw/xive.c index 9a36f1ab2111..b9cdc4b0e317 100644 --- a/hw/xive.c +++ b/hw/xive.c @@ -146,18 +146,22 @@ * so we could potentially make the IVT size twice as big, but for now * we will simply share it and ensure we don't hand out IPIs that * overlap the HW interrupts. + * + * TODO: adjust the VC BAR range for IPI ESBs on this value */ -#define MAX_INT_ENTRIES (1 * 1024 * 1024) + +#define XIVE_INT_ORDER 20 /* 1M interrupts */ +#define XIVE_INT_COUNT (1ul << XIVE_INT_ORDER) /* * First interrupt number, also the first logical interrupt number - * allocated by Linux + * allocated by Linux (the first numbers are reserved for ISA) */ #define XIVE_INT_FIRST 0x10 /* Corresponding direct table sizes */ -#define SBE_SIZE (MAX_INT_ENTRIES / 4) -#define IVT_SIZE (MAX_INT_ENTRIES * 8) +#define SBE_SIZE (XIVE_INT_COUNT / 4) +#define IVT_SIZE (XIVE_INT_COUNT * 8) /* Max number of EQs. We allocate an indirect table big enough so * that when fully populated we can have that many EQs. @@ -376,7 +380,7 @@ struct xive { * and partially populated. * * Currently, the ESB/SBE and the EAS/IVT tables are direct and - * fully pre-allocated based on MAX_INT_ENTRIES. + * fully pre-allocated based on XIVE_INT_COUNT. * * The other tables are indirect, we thus pre-allocate the indirect * table (ie, pages of pointers) and populate enough of the pages @@ -760,7 +764,7 @@ static struct xive_ive *xive_get_ive(struct xive *x, unsigned int isn) xive_err(x, "xive_get_ive, ISN 0x%x not on right chip\n", isn); return NULL; } - assert (idx < MAX_INT_ENTRIES); + assert (idx < XIVE_INT_COUNT); /* If we support >1 block per chip, this should still work as * we are likely to make the table contiguous anyway @@ -1624,7 +1628,7 @@ static bool xive_prealloc_tables(struct xive *x) } /* SBEs are initialized to 0b01 which corresponds to "ints off" */ memset(x->sbe_base, 0x55, SBE_SIZE); - xive_dbg(x, "SBE at %p size 0x%x\n", x->sbe_base, SBE_SIZE); + xive_dbg(x, "SBE at %p size 0x%lx\n", x->sbe_base, SBE_SIZE); /* EAS/IVT entries are 8 bytes */ x->ivt_base = local_alloc(x->chip_id, IVT_SIZE, IVT_SIZE); @@ -1636,7 +1640,7 @@ static bool xive_prealloc_tables(struct xive *x) * when actually used */ memset(x->ivt_base, 0, IVT_SIZE); - xive_dbg(x, "IVT at %p size 0x%x\n", x->ivt_base, IVT_SIZE); + xive_dbg(x, "IVT at %p size 0x%lx\n", x->ivt_base, IVT_SIZE); /* Indirect EQ table. (XXX Align to 64K until I figure out the * HW requirements) @@ -2595,7 +2599,7 @@ static struct xive *init_one_xive(struct dt_node *np) * so that HW sources land outside of ESB space... */ x->int_base = BLKIDX_TO_GIRQ(x->block_id, 0); - x->int_max = x->int_base + MAX_INT_ENTRIES; + x->int_max = x->int_base + XIVE_INT_COUNT; x->int_hw_bot = x->int_max; x->int_ipi_top = x->int_base; @@ -2611,9 +2615,9 @@ static struct xive *init_one_xive(struct dt_node *np) /* Make sure we don't hand out 0 */ bitmap_set_bit(*x->eq_map, 0); - x->int_enabled_map = zalloc(BITMAP_BYTES(MAX_INT_ENTRIES)); + x->int_enabled_map = zalloc(BITMAP_BYTES(XIVE_INT_COUNT)); assert(x->int_enabled_map); - x->ipi_alloc_map = zalloc(BITMAP_BYTES(MAX_INT_ENTRIES)); + x->ipi_alloc_map = zalloc(BITMAP_BYTES(XIVE_INT_COUNT)); assert(x->ipi_alloc_map); xive_dbg(x, "Handling interrupts [%08x..%08x]\n", @@ -3382,7 +3386,7 @@ static bool check_misrouted_ipi(struct cpu_thread *me, uint32_t irq) if (!x) continue; ive = x->ivt_base; - for (i = 0; i < MAX_INT_ENTRIES; i++) { + for (i = 0; i < XIVE_INT_COUNT; i++) { if (xive_get_field64(IVE_EQ_DATA, ive[i].w) == irq) { eq_blk = xive_get_field64(IVE_EQ_BLOCK, ive[i].w); eq_idx = xive_get_field64(IVE_EQ_INDEX, ive[i].w); @@ -4397,7 +4401,7 @@ static void xive_reset_one(struct xive *x) lock(&x->lock); /* Check all interrupts are disabled */ - i = bitmap_find_one_bit(*x->int_enabled_map, 0, MAX_INT_ENTRIE334 V+ i = bitmap_find_one_bit(*x->int_enabled_map, 0, XIVE_INT_COUNT); if (i >= 0) xive_warn(x, "Interrupt %d (and maybe more) not disabled" " at reset !\n", i); @@ -4405,7 +4409,7 @@ static void xive_reset_one(struct xive *x) From patchwork Thu Jun 4 13:21:17 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?C=C3=A9dric_Le_Goater?= X-Patchwork-Id: 1303565 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 49d6z45Wcfz9sSy for ; Fri, 5 Jun 2020 00:06:56 +1000 (AEST) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=kaod.org Received: from bilbo.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 49d6z33hXVzDqLM for ; Fri, 5 Jun 2020 00:06:55 +1000 (AEST) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=kaod.org (client-ip=46.105.77.114; helo=8.mo7.mail-out.ovh.net; envelope-from=clg@kaod.org; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=none (p=none dis=none) header.from=kaod.org X-Greylist: delayed 2367 seconds by postgrey-1.36 at bilbo; Fri, 05 Jun 2020 00:01:08 AEST Received: from 8.mo7.mail-out.ovh.net (8.mo7.mail-out.ovh.net [46.105.77.114]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 49d6rP3VVSzDqkB for ; Fri, 5 Jun 2020 00:01:08 +1000 (AEST) Received: from player739.ha.ovh.net (unknown [10.110.115.5]) by mo7.mail-out.ovh.net (Postfix) with ESMTP id 753DB169A08 for ; Thu, 4 Jun 2020 15:21:40 +0200 (CEST) Received: from kaod.org (82-64-250-170.subs.proxad.net [82.64.250.170]) (Authenticated sender: clg@kaod.org) by player739.ha.ovh.net (Postfix) with ESMTPSA id 2A380F026202; Thu, 4 Jun 2020 13:21:36 +0000 (UTC) Authentication-Results: garm.ovh; auth=pass (GARM-105G0067dbe3ae2-0c60-4360-9fe2-147b6e3f07b1, 2E0AA79A099E542C5FE1C9A79F210F9E9C727315) smtp.auth=clg@kaod.org From: =?utf-8?q?C=C3=A9dric_Le_Goater?= To: skiboot@lists.ozlabs.org Date: Thu, 4 Jun 2020 15:21:17 +0200 Message-Id: <20200604132126.750999-3-clg@kaod.org> X-Mailer: git-send-email 2.25.4 In-Reply-To: <20200604132126.750999-1-clg@kaod.org> References: <20200604132126.750999-1-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 17682258039502572505 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgeduhedrudeguddgieduucetufdoteggodetrfdotffvucfrrhhofhhilhgvmecuqfggjfdpvefjgfevmfevgfenuceurghilhhouhhtmecuhedttdenucesvcftvggtihhpihgvnhhtshculddquddttddmnecujfgurhephffvufffkffojghfgggtgfesthekredtredtjeenucfhrhhomhepveorughrihgtucfnvgcuifhorghtvghruceotghlgheskhgrohgurdhorhhgqeenucggtffrrghtthgvrhhnpefgieetvdefudeghedvveejudeihfeiteffjeetjeeukefhgffgvedugedugedugfenucfkpheptddrtddrtddrtddpkedvrdeigedrvdehtddrudejtdenucevlhhushhtvghrufhiiigvpedtnecurfgrrhgrmhepmhhouggvpehsmhhtphdqohhuthdphhgvlhhopehplhgrhigvrhejfeelrdhhrgdrohhvhhdrnhgvthdpihhnvghtpedtrddtrddtrddtpdhmrghilhhfrhhomheptghlgheskhgrohgurdhorhhgpdhrtghpthhtohepshhkihgsohhotheslhhishhtshdrohiilhgrsghsrdhorhhg Subject: [Skiboot] [PATCH 02/11] xive/p9: Clarify the global IRQ number encoding X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" On P9, the global IRQ number is limited to 24 bits because the XICS emulation encodes the CPPR value in the top 8 bits. The following 4 bits are used to encode the XIVE block number, which leaves 20 bits for the interrupt index number. Introduce a definition reflecting the size of this bitfield and check that number of interrupts per chip is not overflowing our encoding. Signed-off-by: Cédric Le Goater --- hw/xive.c | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/hw/xive.c b/hw/xive.c index b9cdc4b0e317..3d016934a96d 100644 --- a/hw/xive.c +++ b/hw/xive.c @@ -498,11 +498,16 @@ static uint32_t xive_chip_to_block(uint32_t chip_id) * Global interrupt numbers for non-escalation interrupts are thus * limited to 24 bits which is necessary for our XICS emulation since * the top 8 bits are reserved for the CPPR value. - * */ -#define GIRQ_TO_BLK(__g) (((__g) >> 20) & 0xf) -#define GIRQ_TO_IDX(__g) ((__g) & 0x000fffff) -#define BLKIDX_TO_GIRQ(__b,__i) (((uint32_t)(__b)) << 20 | (__i)) +#define INT_SHIFT 20 + +#if XIVE_INT_ORDER > INT_SHIFT +#error "Too many ESBs for IRQ encoding" +#endif + +#define GIRQ_TO_BLK(__g) (((__g) >> INT_SHIFT) & 0xf) +#define GIRQ_TO_IDX(__g) ((__g) & ((1 << INT_SHIFT) - 1)) +#define BLKIDX_TO_GIRQ(__b,__i) (((uint32_t)(__b)) << INT_SHIFT | (__i)) #define GIRQ_IS_ESCALATION(__g) ((__g) & 0x01000000) #define MAKE_ESCALATION_GIRQ(__b,__i)(BLKIDX_TO_GIRQ(__b,__i) | 0x01000000) From patchwork Thu Jun 4 13:21:18 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?C=C3=A9dric_Le_Goater?= X-Patchwork-Id: 1303546 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 49d6LC1Zv0z9sSg for ; Thu, 4 Jun 2020 23:38:27 +1000 (AEST) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=kaod.org Received: from bilbo.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 49d6LC0nPzzDql8 for ; Thu, 4 Jun 2020 23:38:27 +1000 (AEST) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=kaod.org (client-ip=46.105.51.53; helo=5.mo178.mail-out.ovh.net; envelope-from=clg@kaod.org; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=none (p=none dis=none) header.from=kaod.org Received: from 5.mo178.mail-out.ovh.net (5.mo178.mail-out.ovh.net [46.105.51.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 49d6L60BJgzDqcM for ; Thu, 4 Jun 2020 23:38:20 +1000 (AEST) Received: from player739.ha.ovh.net (unknown [10.110.171.173]) by mo178.mail-out.ovh.net (Postfix) with ESMTP id C9F85A3371 for ; Thu, 4 Jun 2020 15:21:44 +0200 (CEST) Received: from kaod.org (82-64-250-170.subs.proxad.net [82.64.250.170]) (Authenticated sender: clg@kaod.org) by player739.ha.ovh.net (Postfix) with ESMTPSA id 6E99CF026249; Thu, 4 Jun 2020 13:21:40 +0000 (UTC) Authentication-Results: garm.ovh; auth=pass (GARM-105G006e65ee305-07d2-4f79-bc69-29b97bfdbe0e, 2E0AA79A099E542C5FE1C9A79F210F9E9C727315) smtp.auth=clg@kaod.org From: =?utf-8?q?C=C3=A9dric_Le_Goater?= To: skiboot@lists.ozlabs.org Date: Thu, 4 Jun 2020 15:21:18 +0200 Message-Id: <20200604132126.750999-4-clg@kaod.org> X-Mailer: git-send-email 2.25.4 In-Reply-To: <20200604132126.750999-1-clg@kaod.org> References: <20200604132126.750999-1-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 17683383937871940569 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgeduhedrudeguddgieduucetufdoteggodetrfdotffvucfrrhhofhhilhgvmecuqfggjfdpvefjgfevmfevgfenuceurghilhhouhhtmecuhedttdenucesvcftvggtihhpihgvnhhtshculddquddttddmnecujfgurhephffvufffkffojghfgggtgfesthekredtredtjeenucfhrhhomhepveorughrihgtucfnvgcuifhorghtvghruceotghlgheskhgrohgurdhorhhgqeenucggtffrrghtthgvrhhnpefgieetvdefudeghedvveejudeihfeiteffjeetjeeukefhgffgvedugedugedugfenucfkpheptddrtddrtddrtddpkedvrdeigedrvdehtddrudejtdenucevlhhushhtvghrufhiiigvpedtnecurfgrrhgrmhepmhhouggvpehsmhhtphdqohhuthdphhgvlhhopehplhgrhigvrhejfeelrdhhrgdrohhvhhdrnhgvthdpihhnvghtpedtrddtrddtrddtpdhmrghilhhfrhhomheptghlgheskhgrohgurdhorhhgpdhrtghpthhtohepshhkihgsohhotheslhhishhtshdrohiilhgrsghsrdhorhhg Subject: [Skiboot] [PATCH 03/11] xive/p9: Introduce XIVE_ESB_SHIFT X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" Each interrupt source is associated with a pair of ESB pages. The even page is for trigger and the odd page is for management. Signed-off-by: Cédric Le Goater Reviewed-by: Gustavo Romero --- hw/xive.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/hw/xive.c b/hw/xive.c index 3d016934a96d..9b4ed66f7194 100644 --- a/hw/xive.c +++ b/hw/xive.c @@ -100,7 +100,6 @@ /* Use 64K for everything by default */ #define IC_PAGE_SIZE 0x10000 #define TM_PAGE_SIZE 0x10000 -#define IPI_ESB_SHIFT (16 + 1) #define EQ_ESB_SHIFT (16 + 1) /* VC BAR contains set translations for the ESBs and the EQs. @@ -163,6 +162,9 @@ #define SBE_SIZE (XIVE_INT_COUNT / 4) #define IVT_SIZE (XIVE_INT_COUNT * 8) +/* Use 64K for everything by default */ +#define XIVE_ESB_SHIFT (16 + 1) /* trigger + mgmt pages */ + /* Max number of EQs. We allocate an indirect table big enough so * that when fully populated we can have that many EQs. * @@ -2555,8 +2557,8 @@ void xive_register_ipi_source(uint32_t base, uint32_t count, void *data, /* Callbacks assume the MMIO base corresponds to the first * interrupt of that source structure so adjust it */ - mmio_base = x->esb_mmio + (1ul << IPI_ESB_SHIFT) * base_idx; - __xive_register_source(x, s, base, count, IPI_ESB_SHIFT, mmio_base, + mmio_base = x->esb_mmio + (1ul << XIVE_ESB_SHIFT) * base_idx; + __xive_register_source(x, s, base, count, XIVE_ESB_SHIFT, mmio_base, flags, false, data, ops); } @@ -2658,7 +2660,7 @@ static struct xive *init_one_xive(struct dt_node *np) if (XIVE_CAN_STORE_EOI(x)) flags |= XIVE_SRC_STORE_EOI; __xive_register_source(x, &x->ipis, x->int_base, - x->int_hw_bot - x->int_base, IPI_ESB_SHIFT, + x->int_hw_bot - x->int_base, XIVE_ESB_SHIFT, x->esb_mmio, flags, true, NULL, NULL); /* Register escalation sources */ From patchwork Thu Jun 4 13:21:19 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?C=C3=A9dric_Le_Goater?= X-Patchwork-Id: 1303562 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [203.11.71.2]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 49d6pr71Tqz9sSf for ; Thu, 4 Jun 2020 23:59:48 +1000 (AEST) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=kaod.org Received: from bilbo.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 49d6pr4GMnzDqlY for ; Thu, 4 Jun 2020 23:59:48 +1000 (AEST) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=kaod.org (client-ip=178.33.251.8; helo=13.mo4.mail-out.ovh.net; envelope-from=clg@kaod.org; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=none (p=none dis=none) header.from=kaod.org Received: from 13.mo4.mail-out.ovh.net (13.mo4.mail-out.ovh.net [178.33.251.8]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 49d6pW0PM8zDqk9 for ; Thu, 4 Jun 2020 23:59:27 +1000 (AEST) Received: from player739.ha.ovh.net (unknown [10.108.42.192]) by mo4.mail-out.ovh.net (Postfix) with ESMTP id 7723623CD84 for ; Thu, 4 Jun 2020 15:21:49 +0200 (CEST) Received: from kaod.org (82-64-250-170.subs.proxad.net [82.64.250.170]) (Authenticated sender: clg@kaod.org) by player739.ha.ovh.net (Postfix) with ESMTPSA id B146CF0262B7; Thu, 4 Jun 2020 13:21:44 +0000 (UTC) Authentication-Results: garm.ovh; auth=pass (GARM-105G00669403bd7-5a9b-4362-ae23-194389c6533b, 2E0AA79A099E542C5FE1C9A79F210F9E9C727315) smtp.auth=clg@kaod.org From: =?utf-8?q?C=C3=A9dric_Le_Goater?= To: skiboot@lists.ozlabs.org Date: Thu, 4 Jun 2020 15:21:19 +0200 Message-Id: <20200604132126.750999-5-clg@kaod.org> X-Mailer: git-send-email 2.25.4 In-Reply-To: <20200604132126.750999-1-clg@kaod.org> References: <20200604132126.750999-1-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 17684509840941288409 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgeduhedrudeguddgieduucetufdoteggodetrfdotffvucfrrhhofhhilhgvmecuqfggjfdpvefjgfevmfevgfenuceurghilhhouhhtmecuhedttdenucesvcftvggtihhpihgvnhhtshculddquddttddmnecujfgurhephffvufffkffojghfgggtgfesthekredtredtjeenucfhrhhomhepveorughrihgtucfnvgcuifhorghtvghruceotghlgheskhgrohgurdhorhhgqeenucggtffrrghtthgvrhhnpefgieetvdefudeghedvveejudeihfeiteffjeetjeeukefhgffgvedugedugedugfenucfkpheptddrtddrtddrtddpkedvrdeigedrvdehtddrudejtdenucevlhhushhtvghrufhiiigvpedtnecurfgrrhgrmhepmhhouggvpehsmhhtphdqohhuthdphhgvlhhopehplhgrhigvrhejfeelrdhhrgdrohhvhhdrnhgvthdpihhnvghtpedtrddtrddtrddtpdhmrghilhhfrhhomheptghlgheskhgrohgurdhorhhgpdhrtghpthhtohepshhkihgsohhotheslhhishhtshdrohiilhgrsghsrdhorhhg Subject: [Skiboot] [PATCH 04/11] xive/p9: Introduce XIVE_EQ_ORDER X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" XIVE_EQ_ORDER defines the number of EQ descriptors per chip the system can use. The EQ descriptors can be controlled by ESB pages also and the driver defines in the VC BAR of the controller a range of 128G of ESB pages giving access to 1M EQs. All ESB pages are backed by a memory table, so we are fine but we could improve the configuration. Signed-off-by: Cédric Le Goater Reviewed-by: Gustavo Romero --- hw/xive.c | 17 +++++++++-------- 1 file changed, 9 insertions(+), 8 deletions(-) diff --git a/hw/xive.c b/hw/xive.c index 9b4ed66f7194..2a132ce87f3b 100644 --- a/hw/xive.c +++ b/hw/xive.c @@ -173,11 +173,12 @@ * 2K EQs. We need 512 pointers, ie, 4K of memory for the indirect * table. * - * XXX Adjust that based on BAR value ? + * TODO: adjust the VC BAR range for END ESBs on this value */ -#define MAX_EQ_COUNT (1 * 1024 * 1024) +#define XIVE_EQ_ORDER 20 /* 1M ENDs */ +#define XIVE_EQ_COUNT (1ul << XIVE_EQ_ORDER) #define EQ_PER_PAGE (0x10000 / 32) // Use sizeof ? -#define IND_EQ_TABLE_SIZE ((MAX_EQ_COUNT / EQ_PER_PAGE) * 8) +#define IND_EQ_TABLE_SIZE ((XIVE_EQ_COUNT / EQ_PER_PAGE) * 8) /* Number of priorities (and thus EQDs) we allocate for each VP */ #define NUM_INT_PRIORITIES 8 @@ -389,7 +390,7 @@ struct xive { * for our basic setup using 64K pages. * * The size of the indirect tables are driven by MAX_VP_COUNT and - * MAX_EQ_COUNT. The number of pre-allocated ones are driven by + * XIVE_EQ_COUNT. The number of pre-allocated ones are driven by * INITIAL_VP_COUNT (number of EQ depends on number of VP) in block * mode, otherwise we only preallocate INITIAL_BLK0_VP_COUNT on * block 0. @@ -865,7 +866,7 @@ static uint32_t xive_alloc_eq_set(struct xive *x, bool alloc_indirect) assert(x->eq_map); /* Allocate from the EQ bitmap. Each bit is 8 EQs */ - idx = bitmap_find_zero_bit(*x->eq_map, 0, MAX_EQ_COUNT >> 3); + idx = bitmap_find_zero_bit(*x->eq_map, 0, XIVE_EQ_COUNT >> 3); if (idx < 0) { xive_dbg(x, "Allocation from EQ bitmap failed !\n"); return XIVE_ALLOC_NO_SPACE; @@ -2617,7 +2618,7 @@ static struct xive *init_one_xive(struct dt_node *np) x->int_ipi_top = XIVE_INT_FIRST; /* Allocate a few bitmaps */ - x->eq_map = zalloc(BITMAP_BYTES(MAX_EQ_COUNT >> 3)); + x->eq_map = zalloc(BITMAP_BYTES(XIVE_EQ_COUNT >> 3)); assert(x->eq_map); /* Make sure we don't hand out 0 */ bitmap_set_bit(*x->eq_map, 0); @@ -2666,7 +2667,7 @@ static struct xive *init_one_xive(struct dt_node *np) /* Register escalation sources */ __xive_register_source(x, &x->esc_irqs, MAKE_ESCALATION_GIRQ(x->block_id, 0), - MAX_EQ_COUNT, EQ_ESB_SHIFT, + XIVE_EQ_COUNT, EQ_ESB_SHIFT, x->eq_mmio, XIVE_SRC_EOI_PAGE1, false, NULL, NULL); @@ -4421,7 +4422,7 @@ static void xive_reset_one(struct xive *x) xive_dbg(x, "Resetting EQs...\n"); /* Reset all allocated EQs and free the user ones */ - bitmap_for_each_one(*x->eq_map, MAX_EQ_COUNT >> 3, i) { + bitmap_for_each_one(*x->eq_map, XIVE_EQ_COUNT >> 3, i) { struct xive_eq eq0; struct xive_eq *eq; int j; From patchwork Thu Jun 4 13:21:20 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?C=C3=A9dric_Le_Goater?= X-Patchwork-Id: 1303636 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [203.11.71.2]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 49dBsM6q8Rz9sPF for ; Fri, 5 Jun 2020 03:02:15 +1000 (AEST) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=kaod.org Received: from bilbo.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 49dBsM39qgzDqnv for ; Fri, 5 Jun 2020 03:02:15 +1000 (AEST) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=kaod.org (client-ip=46.105.56.76; helo=6.mo179.mail-out.ovh.net; envelope-from=clg@kaod.org; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=none (p=none dis=none) header.from=kaod.org X-Greylist: delayed 10802 seconds by postgrey-1.36 at bilbo; Fri, 05 Jun 2020 03:00:00 AEST Received: from 6.mo179.mail-out.ovh.net (6.mo179.mail-out.ovh.net [46.105.56.76]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 49dBpn01sWzDqnk for ; Fri, 5 Jun 2020 02:59:59 +1000 (AEST) Received: from player739.ha.ovh.net (unknown [10.110.115.215]) by mo179.mail-out.ovh.net (Postfix) with ESMTP id 6785616C93A for ; Thu, 4 Jun 2020 15:21:53 +0200 (CEST) Received: from kaod.org (82-64-250-170.subs.proxad.net [82.64.250.170]) (Authenticated sender: clg@kaod.org) by player739.ha.ovh.net (Postfix) with ESMTPSA id 0A4BFF02633D; Thu, 4 Jun 2020 13:21:49 +0000 (UTC) Authentication-Results: garm.ovh; auth=pass (GARM-105G00668ee0c84-fc45-4421-aa54-f466ef51d220, 2E0AA79A099E542C5FE1C9A79F210F9E9C727315) smtp.auth=clg@kaod.org From: =?utf-8?q?C=C3=A9dric_Le_Goater?= To: skiboot@lists.ozlabs.org Date: Thu, 4 Jun 2020 15:21:20 +0200 Message-Id: <20200604132126.750999-6-clg@kaod.org> X-Mailer: git-send-email 2.25.4 In-Reply-To: <20200604132126.750999-1-clg@kaod.org> References: <20200604132126.750999-1-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 17685917212856323033 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgeduhedrudeguddgieduucetufdoteggodetrfdotffvucfrrhhofhhilhgvmecuqfggjfdpvefjgfevmfevgfenuceurghilhhouhhtmecuhedttdenucesvcftvggtihhpihgvnhhtshculddquddttddmnecujfgurhephffvufffkffojghfgggtgfesthekredtredtjeenucfhrhhomhepveorughrihgtucfnvgcuifhorghtvghruceotghlgheskhgrohgurdhorhhgqeenucggtffrrghtthgvrhhnpefgieetvdefudeghedvveejudeihfeiteffjeetjeeukefhgffgvedugedugedugfenucfkpheptddrtddrtddrtddpkedvrdeigedrvdehtddrudejtdenucevlhhushhtvghrufhiiigvpedtnecurfgrrhgrmhepmhhouggvpehsmhhtphdqohhuthdphhgvlhhopehplhgrhigvrhejfeelrdhhrgdrohhvhhdrnhgvthdpihhnvghtpedtrddtrddtrddtpdhmrghilhhfrhhomheptghlgheskhgrohgurdhorhhgpdhrtghpthhtohepshhkihgsohhotheslhhishhtshdrohiilhgrsghsrdhorhhg Subject: [Skiboot] [PATCH 05/11] xive/p9: Clarify the escalation IRQ encoding X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" When an interrupt can not be delivered, an escalation interrupt can be triggered. The EQ descriptor of the pending interrupt should be configured to generate an escalation event, 'e' bit, and words 4 and 5 of the EQ descriptor should contain an IVE pointing to the escalation EQ to trigger. This is why EQs are considered as interrupt sources and registered as such when initializing the interrupt controller. These interrupts are identified as escalations by setting a special bit in their global interrupt number. Clarify that and check that the number of EQDs is not overflowing the global interrupt encoding. Signed-off-by: Cédric Le Goater Reviewed-by: Gustavo Romero --- hw/xive.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/hw/xive.c b/hw/xive.c index 2a132ce87f3b..4a029c3e97db 100644 --- a/hw/xive.c +++ b/hw/xive.c @@ -503,16 +503,21 @@ static uint32_t xive_chip_to_block(uint32_t chip_id) * the top 8 bits are reserved for the CPPR value. */ #define INT_SHIFT 20 +#define INT_ESC_SHIFT (INT_SHIFT + 4) /* 4bits block id */ #if XIVE_INT_ORDER > INT_SHIFT #error "Too many ESBs for IRQ encoding" #endif +#if XIVE_EQ_ORDER > INT_SHIFT +#error "Too many EQs for escalation IRQ number encoding" +#endif + #define GIRQ_TO_BLK(__g) (((__g) >> INT_SHIFT) & 0xf) #define GIRQ_TO_IDX(__g) ((__g) & ((1 << INT_SHIFT) - 1)) #define BLKIDX_TO_GIRQ(__b,__i) (((uint32_t)(__b)) << INT_SHIFT | (__i)) -#define GIRQ_IS_ESCALATION(__g) ((__g) & 0x01000000) -#define MAKE_ESCALATION_GIRQ(__b,__i)(BLKIDX_TO_GIRQ(__b,__i) | 0x01000000) +#define GIRQ_IS_ESCALATION(__g) ((__g) & (1 << INT_ESC_SHIFT)) +#define MAKE_ESCALATION_GIRQ(__b,__i)(BLKIDX_TO_GIRQ(__b,__i) | (1 << INT_ESC_SHIFT)) /* Block/IRQ to chip# conversions */ #define PC_BLK_TO_CHIP(__b) (xive_block_to_chip[__b]) From patchwork Thu Jun 4 13:21:21 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?C=C3=A9dric_Le_Goater?= X-Patchwork-Id: 1303564 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [203.11.71.2]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 49d6xY5XQ0z9sSy for ; Fri, 5 Jun 2020 00:05:37 +1000 (AEST) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=kaod.org Received: from bilbo.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 49d6xV5HN1zDqRn for ; Fri, 5 Jun 2020 00:05:34 +1000 (AEST) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=kaod.org (client-ip=46.105.36.149; helo=4.mo179.mail-out.ovh.net; envelope-from=clg@kaod.org; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=none (p=none dis=none) header.from=kaod.org Received: from 4.mo179.mail-out.ovh.net (4.mo179.mail-out.ovh.net [46.105.36.149]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 49d6q61Ml9zDqlc for ; Fri, 5 Jun 2020 00:00:01 +1000 (AEST) Received: from player739.ha.ovh.net (unknown [10.108.54.87]) by mo179.mail-out.ovh.net (Postfix) with ESMTP id A25C516DE2E for ; Thu, 4 Jun 2020 15:21:57 +0200 (CEST) Received: from kaod.org (82-64-250-170.subs.proxad.net [82.64.250.170]) (Authenticated sender: clg@kaod.org) by player739.ha.ovh.net (Postfix) with ESMTPSA id 4C89BF0263AB; Thu, 4 Jun 2020 13:21:53 +0000 (UTC) Authentication-Results: garm.ovh; auth=pass (GARM-105G0069636143a-bde0-4bbe-8041-a399a305dee8, 2E0AA79A099E542C5FE1C9A79F210F9E9C727315) smtp.auth=clg@kaod.org From: =?utf-8?q?C=C3=A9dric_Le_Goater?= To: skiboot@lists.ozlabs.org Date: Thu, 4 Jun 2020 15:21:21 +0200 Message-Id: <20200604132126.750999-7-clg@kaod.org> X-Mailer: git-send-email 2.25.4 In-Reply-To: <20200604132126.750999-1-clg@kaod.org> References: <20200604132126.750999-1-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 17687043115540843481 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgeduhedrudeguddgieduucetufdoteggodetrfdotffvucfrrhhofhhilhgvmecuqfggjfdpvefjgfevmfevgfenuceurghilhhouhhtmecuhedttdenucesvcftvggtihhpihgvnhhtshculddquddttddmnecujfgurhephffvufffkffojghfgggtgfesthekredtredtjeenucfhrhhomhepveorughrihgtucfnvgcuifhorghtvghruceotghlgheskhgrohgurdhorhhgqeenucggtffrrghtthgvrhhnpefgieetvdefudeghedvveejudeihfeiteffjeetjeeukefhgffgvedugedugedugfenucfkpheptddrtddrtddrtddpkedvrdeigedrvdehtddrudejtdenucevlhhushhtvghrufhiiigvpedunecurfgrrhgrmhepmhhouggvpehsmhhtphdqohhuthdphhgvlhhopehplhgrhigvrhejfeelrdhhrgdrohhvhhdrnhgvthdpihhnvghtpedtrddtrddtrddtpdhmrghilhhfrhhomheptghlgheskhgrohgurdhorhhgpdhrtghpthhtohepshhkihgsohhotheslhhishhtshdrohiilhgrsghsrdhorhhg Subject: [Skiboot] [PATCH 06/11] xive/p9: Introduce XIVE_EQ_SHIFT X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" Each EQ descriptor is associated with a pair of ESB pages. The even page controls the ESn PQ bits and the odd page controls the ESe PQ bits. Signed-off-by: Cédric Le Goater Reviewed-by: Gustavo Romero --- hw/xive.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/hw/xive.c b/hw/xive.c index 4a029c3e97db..3fce079d2721 100644 --- a/hw/xive.c +++ b/hw/xive.c @@ -100,7 +100,6 @@ /* Use 64K for everything by default */ #define IC_PAGE_SIZE 0x10000 #define TM_PAGE_SIZE 0x10000 -#define EQ_ESB_SHIFT (16 + 1) /* VC BAR contains set translations for the ESBs and the EQs. * @@ -180,6 +179,8 @@ #define EQ_PER_PAGE (0x10000 / 32) // Use sizeof ? #define IND_EQ_TABLE_SIZE ((XIVE_EQ_COUNT / EQ_PER_PAGE) * 8) +#define XIVE_EQ_SHIFT (16 + 1) /* ESn + ESe pages */ + /* Number of priorities (and thus EQDs) we allocate for each VP */ #define NUM_INT_PRIORITIES 8 @@ -2672,7 +2673,7 @@ static struct xive *init_one_xive(struct dt_node *np) /* Register escalation sources */ __xive_register_source(x, &x->esc_irqs, MAKE_ESCALATION_GIRQ(x->block_id, 0), - XIVE_EQ_COUNT, EQ_ESB_SHIFT, + XIVE_EQ_COUNT, XIVE_EQ_SHIFT, x->eq_mmio, XIVE_SRC_EOI_PAGE1, false, NULL, NULL); From patchwork Thu Jun 4 13:21:22 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?C=C3=A9dric_Le_Goater?= X-Patchwork-Id: 1303540 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 49d69203ddz9sSg for ; Thu, 4 Jun 2020 23:30:30 +1000 (AEST) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=kaod.org Received: from bilbo.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 49d6905BKkzDqpB for ; Thu, 4 Jun 2020 23:30:28 +1000 (AEST) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=kaod.org (client-ip=46.105.61.94; helo=7.mo179.mail-out.ovh.net; envelope-from=clg@kaod.org; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=none (p=none dis=none) header.from=kaod.org X-Greylist: delayed 492 seconds by postgrey-1.36 at bilbo; Thu, 04 Jun 2020 23:30:11 AEST Received: from 7.mo179.mail-out.ovh.net (7.mo179.mail-out.ovh.net [46.105.61.94]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 49d68g2xMBzDqnT for ; Thu, 4 Jun 2020 23:30:10 +1000 (AEST) Received: from player739.ha.ovh.net (unknown [10.108.54.237]) by mo179.mail-out.ovh.net (Postfix) with ESMTP id EDCD916DE3D for ; Thu, 4 Jun 2020 15:22:02 +0200 (CEST) Received: from kaod.org (82-64-250-170.subs.proxad.net [82.64.250.170]) (Authenticated sender: clg@kaod.org) by player739.ha.ovh.net (Postfix) with ESMTPSA id 9697DF0263E1; Thu, 4 Jun 2020 13:21:57 +0000 (UTC) Authentication-Results: garm.ovh; auth=pass (GARM-105G0064ac0283f-c490-4e9c-bfb0-d1a528b97bb4, 2E0AA79A099E542C5FE1C9A79F210F9E9C727315) smtp.auth=clg@kaod.org From: =?utf-8?q?C=C3=A9dric_Le_Goater?= To: skiboot@lists.ozlabs.org Date: Thu, 4 Jun 2020 15:21:22 +0200 Message-Id: <20200604132126.750999-8-clg@kaod.org> X-Mailer: git-send-email 2.25.4 In-Reply-To: <20200604132126.750999-1-clg@kaod.org> References: <20200604132126.750999-1-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 17688169013199342553 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgeduhedrudeguddgieduucetufdoteggodetrfdotffvucfrrhhofhhilhgvmecuqfggjfdpvefjgfevmfevgfenuceurghilhhouhhtmecuhedttdenucesvcftvggtihhpihgvnhhtshculddquddttddmnecujfgurhephffvufffkffojghfgggtgfesthekredtredtjeenucfhrhhomhepveorughrihgtucfnvgcuifhorghtvghruceotghlgheskhgrohgurdhorhhgqeenucggtffrrghtthgvrhhnpefgieetvdefudeghedvveejudeihfeiteffjeetjeeukefhgffgvedugedugedugfenucfkpheptddrtddrtddrtddpkedvrdeigedrvdehtddrudejtdenucevlhhushhtvghrufhiiigvpedvnecurfgrrhgrmhepmhhouggvpehsmhhtphdqohhuthdphhgvlhhopehplhgrhigvrhejfeelrdhhrgdrohhvhhdrnhgvthdpihhnvghtpedtrddtrddtrddtpdhmrghilhhfrhhomheptghlgheskhgrohgurdhorhhgpdhrtghpthhtohepshhkihgsohhotheslhhishhtshdrohiilhgrsghsrdhorhhg Subject: [Skiboot] [PATCH 07/11] xive/p9: Use sizeof() instead of hardcoded values X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" Signed-off-by: Cédric Le Goater Reviewed-by: Gustavo Romero --- hw/xive.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/hw/xive.c b/hw/xive.c index 3fce079d2721..a3a8eb05776b 100644 --- a/hw/xive.c +++ b/hw/xive.c @@ -174,9 +174,10 @@ * * TODO: adjust the VC BAR range for END ESBs on this value */ +#define EQ_PER_PAGE (0x10000 / sizeof(struct xive_eq)) + #define XIVE_EQ_ORDER 20 /* 1M ENDs */ #define XIVE_EQ_COUNT (1ul << XIVE_EQ_ORDER) -#define EQ_PER_PAGE (0x10000 / 32) // Use sizeof ? #define IND_EQ_TABLE_SIZE ((XIVE_EQ_COUNT / EQ_PER_PAGE) * 8) #define XIVE_EQ_SHIFT (16 + 1) /* ESn + ESe pages */ @@ -208,12 +209,12 @@ * * XXX Adjust that based on BAR value ? */ +#define VP_PER_PAGE (0x10000 / sizeof(struct xive_vp)) #define NVT_SHIFT 19 /* in sync with EQ_W6_NVT_INDEX */ #define MAX_VP_ORDER NVT_SHIFT /* 512k */ #define MAX_VP_COUNT (1ul << MAX_VP_ORDER) -#define VP_PER_PAGE (0x10000 / 64) // Use sizeof ? #define IND_VP_TABLE_SIZE ((MAX_VP_COUNT / VP_PER_PAGE) * 8) /* Initial number of VPs (XXX Make it a variable ?). Round things From patchwork Thu Jun 4 13:21:23 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?C=C3=A9dric_Le_Goater?= X-Patchwork-Id: 1303542 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 49d6B53Cscz9sSy for ; Thu, 4 Jun 2020 23:31:25 +1000 (AEST) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=kaod.org Received: from bilbo.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 49d6B15NcqzDqdh for ; Thu, 4 Jun 2020 23:31:21 +1000 (AEST) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=kaod.org (client-ip=178.33.251.19; helo=14.mo7.mail-out.ovh.net; envelope-from=clg@kaod.org; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=none (p=none dis=none) header.from=kaod.org X-Greylist: delayed 555 seconds by postgrey-1.36 at bilbo; Thu, 04 Jun 2020 23:31:05 AEST Received: from 14.mo7.mail-out.ovh.net (14.mo7.mail-out.ovh.net [178.33.251.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 49d69j1hwBzDqT2 for ; Thu, 4 Jun 2020 23:31:04 +1000 (AEST) Received: from player739.ha.ovh.net (unknown [10.110.103.195]) by mo7.mail-out.ovh.net (Postfix) with ESMTP id 31D5816ABBE for ; Thu, 4 Jun 2020 15:22:06 +0200 (CEST) Received: from kaod.org (82-64-250-170.subs.proxad.net [82.64.250.170]) (Authenticated sender: clg@kaod.org) by player739.ha.ovh.net (Postfix) with ESMTPSA id D9A49F026489; Thu, 4 Jun 2020 13:22:01 +0000 (UTC) Authentication-Results: garm.ovh; auth=pass (GARM-105G00672097798-518d-4627-bff9-1b5df08b70c1, 2E0AA79A099E542C5FE1C9A79F210F9E9C727315) smtp.auth=clg@kaod.org From: =?utf-8?q?C=C3=A9dric_Le_Goater?= To: skiboot@lists.ozlabs.org Date: Thu, 4 Jun 2020 15:21:23 +0200 Message-Id: <20200604132126.750999-9-clg@kaod.org> X-Mailer: git-send-email 2.25.4 In-Reply-To: <20200604132126.750999-1-clg@kaod.org> References: <20200604132126.750999-1-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 17689576387654224857 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgeduhedrudeguddgieduucetufdoteggodetrfdotffvucfrrhhofhhilhgvmecuqfggjfdpvefjgfevmfevgfenuceurghilhhouhhtmecuhedttdenucesvcftvggtihhpihgvnhhtshculddquddttddmnecujfgurhephffvufffkffojghfgggtgfesthekredtredtjeenucfhrhhomhepveorughrihgtucfnvgcuifhorghtvghruceotghlgheskhgrohgurdhorhhgqeenucggtffrrghtthgvrhhnpefgieetvdefudeghedvveejudeihfeiteffjeetjeeukefhgffgvedugedugedugfenucfkpheptddrtddrtddrtddpkedvrdeigedrvdehtddrudejtdenucevlhhushhtvghrufhiiigvpedvnecurfgrrhgrmhepmhhouggvpehsmhhtphdqohhuthdphhgvlhhopehplhgrhigvrhejfeelrdhhrgdrohhvhhdrnhgvthdpihhnvghtpedtrddtrddtrddtpdhmrghilhhfrhhomheptghlgheskhgrohgurdhorhhgpdhrtghpthhtohepshhkihgsohhotheslhhishhtshdrohiilhgrsghsrdhorhhg Subject: [Skiboot] [PATCH 08/11] xive/p9: Clarify indirect table allocation X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" The XIVE interrupt controller uses a set of Virtualization Structure Tables (VST) which characteristics, type, address, size, are described by Virtual Structure Descriptors (VSD). A VSD is 64bit wide. The EQ and VP tables are indirect tables. The VSD points to a single page of VSDs each pointing to a page of virtual structures. Indirect tables are limited to a single top page which is enough to cover the whole range of EQs (24 bits) and VPs (19bits). Signed-off-by: Cédric Le Goater --- hw/xive.c | 29 +++++++++++++++++------------ 1 file changed, 17 insertions(+), 12 deletions(-) diff --git a/hw/xive.c b/hw/xive.c index a3a8eb05776b..6703a6b913bc 100644 --- a/hw/xive.c +++ b/hw/xive.c @@ -91,6 +91,7 @@ * local block of that chip */ +#define XIVE_VSD_SIZE sizeof(u64) /* BAR default values (should be initialized by HostBoot but for * now we do it). Based on the memory map document by Dave Larson @@ -178,7 +179,7 @@ #define XIVE_EQ_ORDER 20 /* 1M ENDs */ #define XIVE_EQ_COUNT (1ul << XIVE_EQ_ORDER) -#define IND_EQ_TABLE_SIZE ((XIVE_EQ_COUNT / EQ_PER_PAGE) * 8) +#define XIVE_EQ_TABLE_SIZE ((XIVE_EQ_COUNT / EQ_PER_PAGE) * XIVE_VSD_SIZE) #define XIVE_EQ_SHIFT (16 + 1) /* ESn + ESe pages */ @@ -215,7 +216,7 @@ #define MAX_VP_ORDER NVT_SHIFT /* 512k */ #define MAX_VP_COUNT (1ul << MAX_VP_ORDER) -#define IND_VP_TABLE_SIZE ((MAX_VP_COUNT / VP_PER_PAGE) * 8) +#define XIVE_VP_TABLE_SIZE ((MAX_VP_COUNT / VP_PER_PAGE) * XIVE_VSD_SIZE) /* Initial number of VPs (XXX Make it a variable ?). Round things * up to a max of 32 cores per chip @@ -1657,10 +1658,12 @@ static bool xive_prealloc_tables(struct xive *x) memset(x->ivt_base, 0, IVT_SIZE); xive_dbg(x, "IVT at %p size 0x%lx\n", x->ivt_base, IVT_SIZE); - /* Indirect EQ table. (XXX Align to 64K until I figure out the - * HW requirements) - */ - al = (IND_EQ_TABLE_SIZE + 0xffff) & ~0xffffull; + /* Indirect EQ table. Limited to one top page. */ + al = ALIGN_UP(XIVE_EQ_TABLE_SIZE, 0x10000); + if (al > 0x10000) { + xive_err(x, "EQ indirect table is too big !\n"); + return false; + } x->eq_ind_base = local_alloc(x->chip_id, al, al); if (!x->eq_ind_base) { xive_err(x, "Failed to allocate EQ indirect table\n"); @@ -1668,19 +1671,21 @@ static bool xive_prealloc_tables(struct xive *x) } memset(x->eq_ind_base, 0, al); xive_dbg(x, "EQi at %p size 0x%llx\n", x->eq_ind_base, al); - x->eq_ind_count = IND_EQ_TABLE_SIZE / 8; + x->eq_ind_count = XIVE_EQ_TABLE_SIZE / 8; - /* Indirect VP table. (XXX Align to 64K until I figure out the - * HW requirements) - */ - al = (IND_VP_TABLE_SIZE + 0xffff) & ~0xffffull; + /* Indirect VP table. Limited to one top page. */ + al = ALIGN_UP(XIVE_VP_TABLE_SIZE, 0x10000); + if (al > 0x10000) { + xive_err(x, "VP indirect table is too big !\n"); + return false; + } x->vp_ind_base = local_alloc(x->chip_id, al, al); if (!x->vp_ind_base) { xive_err(x, "Failed to allocate VP indirect table\n"); return false; } xive_dbg(x, "VPi at %p size 0x%llx\n", x->vp_ind_base, al); - x->vp_ind_count = IND_VP_TABLE_SIZE / 8; + x->vp_ind_count = XIVE_VP_TABLE_SIZE / 8; memset(x->vp_ind_base, 0, al); /* Populate/initialize VP/EQs indirect backing */ From patchwork Thu Jun 4 13:21:24 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?C=C3=A9dric_Le_Goater?= X-Patchwork-Id: 1303543 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [203.11.71.2]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 49d6C11XJWz9sSg for ; Thu, 4 Jun 2020 23:32:13 +1000 (AEST) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=kaod.org Received: from bilbo.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 49d6Bz40P4zDqnp for ; Thu, 4 Jun 2020 23:32:11 +1000 (AEST) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=kaod.org (client-ip=46.105.36.172; helo=3.mo177.mail-out.ovh.net; envelope-from=clg@kaod.org; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=none (p=none dis=none) header.from=kaod.org X-Greylist: delayed 67 seconds by postgrey-1.36 at bilbo; Thu, 04 Jun 2020 23:31:09 AEST Received: from 3.mo177.mail-out.ovh.net (3.mo177.mail-out.ovh.net [46.105.36.172]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 49d69n3L7tzDqK1 for ; Thu, 4 Jun 2020 23:31:08 +1000 (AEST) Received: from player739.ha.ovh.net (unknown [10.110.103.115]) by mo177.mail-out.ovh.net (Postfix) with ESMTP id 8C7791368B1 for ; Thu, 4 Jun 2020 15:22:10 +0200 (CEST) Received: from kaod.org (82-64-250-170.subs.proxad.net [82.64.250.170]) (Authenticated sender: clg@kaod.org) by player739.ha.ovh.net (Postfix) with ESMTPSA id 2BB2EF0264EB; Thu, 4 Jun 2020 13:22:06 +0000 (UTC) Authentication-Results: garm.ovh; auth=pass (GARM-105G006afe942c5-799c-4d5e-aed8-7a312444a88c, 2E0AA79A099E542C5FE1C9A79F210F9E9C727315) smtp.auth=clg@kaod.org From: =?utf-8?q?C=C3=A9dric_Le_Goater?= To: skiboot@lists.ozlabs.org Date: Thu, 4 Jun 2020 15:21:24 +0200 Message-Id: <20200604132126.750999-10-clg@kaod.org> X-Mailer: git-send-email 2.25.4 In-Reply-To: <20200604132126.750999-1-clg@kaod.org> References: <20200604132126.750999-1-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 17690702290453367769 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgeduhedrudeguddgiedvucetufdoteggodetrfdotffvucfrrhhofhhilhgvmecuqfggjfdpvefjgfevmfevgfenuceurghilhhouhhtmecuhedttdenucesvcftvggtihhpihgvnhhtshculddquddttddmnecujfgurhephffvufffkffojghfgggtgfesthekredtredtjeenucfhrhhomhepveorughrihgtucfnvgcuifhorghtvghruceotghlgheskhgrohgurdhorhhgqeenucggtffrrghtthgvrhhnpefgieetvdefudeghedvveejudeihfeiteffjeetjeeukefhgffgvedugedugedugfenucfkpheptddrtddrtddrtddpkedvrdeigedrvdehtddrudejtdenucevlhhushhtvghrufhiiigvpedvnecurfgrrhgrmhepmhhouggvpehsmhhtphdqohhuthdphhgvlhhopehplhgrhigvrhejfeelrdhhrgdrohhvhhdrnhgvthdpihhnvghtpedtrddtrddtrddtpdhmrghilhhfrhhomheptghlgheskhgrohgurdhorhhgpdhrtghpthhtohepshhkihgsohhotheslhhishhtshdrohiilhgrsghsrdhorhhg Subject: [Skiboot] [PATCH 09/11] xive/p9: Force 64K page size on the IC and TM BARs X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" It is possible to configure the IC and TM BAR mappings using 4k pages but we never do. Remove the code doing so. Signed-off-by: Cédric Le Goater Reviewed-by: Gustavo Romero --- hw/xive.c | 27 ++++++--------------------- 1 file changed, 6 insertions(+), 21 deletions(-) diff --git a/hw/xive.c b/hw/xive.c index 6703a6b913bc..0820ee357772 100644 --- a/hw/xive.c +++ b/hw/xive.c @@ -93,15 +93,6 @@ #define XIVE_VSD_SIZE sizeof(u64) -/* BAR default values (should be initialized by HostBoot but for - * now we do it). Based on the memory map document by Dave Larson - * - * Fixed IC and TM BARs first. - */ -/* Use 64K for everything by default */ -#define IC_PAGE_SIZE 0x10000 -#define TM_PAGE_SIZE 0x10000 - /* VC BAR contains set translations for the ESBs and the EQs. * * It's divided in 64 sets, each of which can be either ESB pages or EQ pages. @@ -1417,12 +1408,9 @@ static bool xive_configure_bars(struct xive *x) /* IC BAR */ phys_map_get(chip_id, XIVE_IC, 0, (uint64_t *)&x->ic_base, &x->ic_size); - val = (uint64_t)x->ic_base | CQ_IC_BAR_VALID; - if (IC_PAGE_SIZE == 0x10000) { - val |= CQ_IC_BAR_64K; - x->ic_shift = 16; - } else - x->ic_shift = 12; + val = (uint64_t)x->ic_base | CQ_IC_BAR_VALID | CQ_IC_BAR_64K; + x->ic_shift = 16; + xive_regwx(x, CQ_IC_BAR, val); if (x->last_reg_error) return false; @@ -1432,12 +1420,9 @@ static bool xive_configure_bars(struct xive *x) * all phys_map_get(XIVE_TM) calls. */ phys_map_get(0, XIVE_TM, 0, (uint64_t *)&x->tm_base, &x->tm_size); - val = (uint64_t)x->tm_base | CQ_TM_BAR_VALID; - if (TM_PAGE_SIZE == 0x10000) { - x->tm_shift = 16; - val |= CQ_TM_BAR_64K; - } else - x->tm_shift = 12; + val = (uint64_t)x->tm_base | CQ_TM_BAR_VALID | CQ_TM_BAR_64K; + x->tm_shift = 16; + xive_regwx(x, CQ_TM1_BAR, val); if (x->last_reg_error) return false; From patchwork Thu Jun 4 13:21:25 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?C=C3=A9dric_Le_Goater?= X-Patchwork-Id: 1303548 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 49d6Nd30yTz9sSy for ; Thu, 4 Jun 2020 23:40:33 +1000 (AEST) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=kaod.org Received: from bilbo.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 49d6Nd24CmzDql8 for ; Thu, 4 Jun 2020 23:40:33 +1000 (AEST) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=kaod.org (client-ip=178.33.251.173; helo=1.mo69.mail-out.ovh.net; envelope-from=clg@kaod.org; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=none (p=none dis=none) header.from=kaod.org Received: from 1.mo69.mail-out.ovh.net (1.mo69.mail-out.ovh.net [178.33.251.173]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 49d6NW2n21zDqcM for ; Thu, 4 Jun 2020 23:40:27 +1000 (AEST) Received: from player739.ha.ovh.net (unknown [10.110.171.54]) by mo69.mail-out.ovh.net (Postfix) with ESMTP id D9E34946D1 for ; Thu, 4 Jun 2020 15:22:14 +0200 (CEST) Received: from kaod.org (82-64-250-170.subs.proxad.net [82.64.250.170]) (Authenticated sender: clg@kaod.org) by player739.ha.ovh.net (Postfix) with ESMTPSA id 7599FF026545; Thu, 4 Jun 2020 13:22:10 +0000 (UTC) Authentication-Results: garm.ovh; auth=pass (GARM-105G006f01cb32f-ac0c-45a9-b2ff-869d51169309, 2E0AA79A099E542C5FE1C9A79F210F9E9C727315) smtp.auth=clg@kaod.org From: =?utf-8?q?C=C3=A9dric_Le_Goater?= To: skiboot@lists.ozlabs.org Date: Thu, 4 Jun 2020 15:21:25 +0200 Message-Id: <20200604132126.750999-11-clg@kaod.org> X-Mailer: git-send-email 2.25.4 In-Reply-To: <20200604132126.750999-1-clg@kaod.org> References: <20200604132126.750999-1-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 17691828187429374937 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgeduhedrudeguddgiedvucetufdoteggodetrfdotffvucfrrhhofhhilhgvmecuqfggjfdpvefjgfevmfevgfenuceurghilhhouhhtmecuhedttdenucesvcftvggtihhpihgvnhhtshculddquddttddmnecujfgurhephffvufffkffojghfgggtgfesthekredtredtjeenucfhrhhomhepveorughrihgtucfnvgcuifhorghtvghruceotghlgheskhgrohgurdhorhhgqeenucggtffrrghtthgvrhhnpefgieetvdefudeghedvveejudeihfeiteffjeetjeeukefhgffgvedugedugedugfenucfkpheptddrtddrtddrtddpkedvrdeigedrvdehtddrudejtdenucevlhhushhtvghrufhiiigvpedtnecurfgrrhgrmhepmhhouggvpehsmhhtphdqohhuthdphhgvlhhopehplhgrhigvrhejfeelrdhhrgdrohhvhhdrnhgvthdpihhnvghtpedtrddtrddtrddtpdhmrghilhhfrhhomheptghlgheskhgrohgurdhorhhgpdhrtghpthhtohepshhkihgsohhotheslhhishhtshdrohiilhgrsghsrdhorhhg Subject: [Skiboot] [PATCH 10/11] xive/p9: Modify the size of the VP space X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" The VP space is 19bits wide but the number of XIVE VPs software can use depends on the configured number of EQs. We have 1M EQs and we use 8 priorities per VP. Therefore, our VP space is limited to 128k. Signed-off-by: Cédric Le Goater --- hw/xive.c | 20 ++++++++++++-------- 1 file changed, 12 insertions(+), 8 deletions(-) diff --git a/hw/xive.c b/hw/xive.c index 0820ee357772..594c14306439 100644 --- a/hw/xive.c +++ b/hw/xive.c @@ -199,15 +199,19 @@ * we will allocate half of the above. We might add support for * 2 blocks per chip later if necessary. * - * XXX Adjust that based on BAR value ? + * TODO: adjust the PC BAR range */ #define VP_PER_PAGE (0x10000 / sizeof(struct xive_vp)) #define NVT_SHIFT 19 /* in sync with EQ_W6_NVT_INDEX */ -#define MAX_VP_ORDER NVT_SHIFT /* 512k */ -#define MAX_VP_COUNT (1ul << MAX_VP_ORDER) -#define XIVE_VP_TABLE_SIZE ((MAX_VP_COUNT / VP_PER_PAGE) * XIVE_VSD_SIZE) +/* + * We use 8 priorities per VP and the number of EQs is configured to + * 1M. Therefore, our VP space is limited to 128k. + */ +#define XIVE_VP_ORDER (XIVE_EQ_ORDER - 3) /* 128k */ +#define XIVE_VP_COUNT (1ul << XIVE_VP_ORDER) +#define XIVE_VP_TABLE_SIZE ((XIVE_VP_COUNT / VP_PER_PAGE) * XIVE_VSD_SIZE) /* Initial number of VPs (XXX Make it a variable ?). Round things * up to a max of 32 cores per chip @@ -383,7 +387,7 @@ struct xive { * table (ie, pages of pointers) and populate enough of the pages * for our basic setup using 64K pages. * - * The size of the indirect tables are driven by MAX_VP_COUNT and + * The size of the indirect tables are driven by XIVE_VP_COUNT and * XIVE_EQ_COUNT. The number of pre-allocated ones are driven by * INITIAL_VP_COUNT (number of EQ depends on number of VP) in block * mode, otherwise we only preallocate INITIAL_BLK0_VP_COUNT on @@ -967,12 +971,12 @@ static void xive_init_vp_allocator(void) prlog(PR_INFO, "XIVE: %d chips considered for VP allocations\n", 1 << xive_chips_alloc_bits); - /* Allocate a buddy big enough for MAX_VP_ORDER allocations. + /* Allocate a buddy big enough for XIVE_VP_ORDER allocations. * * each bit in the buddy represents 1 << xive_chips_alloc_bits * VPs. */ - xive_vp_buddy = buddy_create(MAX_VP_ORDER); + xive_vp_buddy = buddy_create(XIVE_VP_ORDER); assert(xive_vp_buddy); /* We reserve the whole range of VPs representing HW chips. @@ -4466,7 +4470,7 @@ static void xive_reset_one(struct xive *x) * either keep a bitmap of allocated VPs or add an iterator to * the buddy which is trickier but doable. */ - for (i = 0; i < MAX_VP_COUNT; i++) { + for (i = 0; i < XIVE_VP_COUNT; i++) { struct xive_vp *vp; struct xive_vp vp0 = {0}; From patchwork Thu Jun 4 13:21:26 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?C=C3=A9dric_Le_Goater?= X-Patchwork-Id: 1303550 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [203.11.71.2]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 49d6PL0c5Pz9sSy for ; Thu, 4 Jun 2020 23:41:10 +1000 (AEST) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=kaod.org Received: from bilbo.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 49d6PK6WgZzDql6 for ; Thu, 4 Jun 2020 23:41:09 +1000 (AEST) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=kaod.org (client-ip=46.105.60.248; helo=9.mo7.mail-out.ovh.net; envelope-from=clg@kaod.org; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=none (p=none dis=none) header.from=kaod.org X-Greylist: delayed 593 seconds by postgrey-1.36 at bilbo; Thu, 04 Jun 2020 23:41:00 AEST Received: from 9.mo7.mail-out.ovh.net (9.mo7.mail-out.ovh.net [46.105.60.248]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 49d6P86Q78zDqF7 for ; Thu, 4 Jun 2020 23:41:00 +1000 (AEST) Received: from player739.ha.ovh.net (unknown [10.110.171.30]) by mo7.mail-out.ovh.net (Postfix) with ESMTP id 13F6F16A11A for ; Thu, 4 Jun 2020 15:22:19 +0200 (CEST) Received: from kaod.org (82-64-250-170.subs.proxad.net [82.64.250.170]) (Authenticated sender: clg@kaod.org) by player739.ha.ovh.net (Postfix) with ESMTPSA id C20E0F0265BC; Thu, 4 Jun 2020 13:22:14 +0000 (UTC) Authentication-Results: garm.ovh; auth=pass (GARM-105G006fb15480f-35cb-48ce-8135-5fedcf0d6ec2, 2E0AA79A099E542C5FE1C9A79F210F9E9C727315) smtp.auth=clg@kaod.org From: =?utf-8?q?C=C3=A9dric_Le_Goater?= To: skiboot@lists.ozlabs.org Date: Thu, 4 Jun 2020 15:21:26 +0200 Message-Id: <20200604132126.750999-12-clg@kaod.org> X-Mailer: git-send-email 2.25.4 In-Reply-To: <20200604132126.750999-1-clg@kaod.org> References: <20200604132126.750999-1-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 17693235563214900185 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgeduhedrudeguddgiedvucetufdoteggodetrfdotffvucfrrhhofhhilhgvmecuqfggjfdpvefjgfevmfevgfenuceurghilhhouhhtmecuhedttdenucesvcftvggtihhpihgvnhhtshculddquddttddmnecujfgurhephffvufffkffojghfgggtgfesthekredtredtjeenucfhrhhomhepveorughrihgtucfnvgcuifhorghtvghruceotghlgheskhgrohgurdhorhhgqeenucggtffrrghtthgvrhhnpefgieetvdefudeghedvveejudeihfeiteffjeetjeeukefhgffgvedugedugedugfenucfkpheptddrtddrtddrtddpkedvrdeigedrvdehtddrudejtdenucevlhhushhtvghrufhiiigvpedtnecurfgrrhgrmhepmhhouggvpehsmhhtphdqohhuthdphhgvlhhopehplhgrhigvrhejfeelrdhhrgdrohhvhhdrnhgvthdpihhnvghtpedtrddtrddtrddtpdhmrghilhhfrhhomheptghlgheskhgrohgurdhorhhgpdhrtghpthhtohepshhkihgsohhotheslhhishhtshdrohiilhgrsghsrdhorhhg Subject: [Skiboot] [PATCH 11/11] xive/p9: Introduce definitions for VP ids of HW threads X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" The CAM line of the HW context is 23bits wide and its value is hardcoded in the XIVE IC presenter with : |chip|000000000001|thrdid | To make sure that we won't assign a VP id overlapping with the HW CAM line, we reserve range 0x80..0xff in our VP allocator. Make that clear. Signed-off-by: Cédric Le Goater --- hw/xive.c | 35 ++++++++++++++++++++++------------- 1 file changed, 22 insertions(+), 13 deletions(-) diff --git a/hw/xive.c b/hw/xive.c index 594c14306439..be489f144ef8 100644 --- a/hw/xive.c +++ b/hw/xive.c @@ -213,11 +213,18 @@ #define XIVE_VP_COUNT (1ul << XIVE_VP_ORDER) #define XIVE_VP_TABLE_SIZE ((XIVE_VP_COUNT / VP_PER_PAGE) * XIVE_VSD_SIZE) -/* Initial number of VPs (XXX Make it a variable ?). Round things - * up to a max of 32 cores per chip +/* + * VP ids for HW threads. + * + * These values are hardcoded in the CAM line of the HW context and + * they depend on the thread id bits of the chip, 7bit for p9. + * + * HW CAM Line |chip|000000000001|thrdid | + * 23bits 4 12 7 */ -#define INITIAL_VP_BASE 0x80 -#define INITIAL_VP_COUNT 0x80 +#define XIVE_THREADID_SHIFT 7 +#define XIVE_HW_VP_BASE (1 << XIVE_THREADID_SHIFT) +#define XIVE_HW_VP_COUNT (1 << XIVE_THREADID_SHIFT) /* The xive operation mode indicates the active "API" and corresponds * to the "mode" parameter of the opal_xive_reset() call @@ -389,7 +396,7 @@ struct xive { * * The size of the indirect tables are driven by XIVE_VP_COUNT and * XIVE_EQ_COUNT. The number of pre-allocated ones are driven by - * INITIAL_VP_COUNT (number of EQ depends on number of VP) in block + * XIVE_HW_VP_COUNT (number of EQ depends on number of VP) in block * mode, otherwise we only preallocate INITIAL_BLK0_VP_COUNT on * block 0. */ @@ -523,7 +530,7 @@ static uint32_t xive_chip_to_block(uint32_t chip_id) #define GIRQ_TO_CHIP(__isn) (VC_BLK_TO_CHIP(GIRQ_TO_BLK(__isn))) /* Routing of physical processors to VPs */ -#define PIR2VP_IDX(__pir) (0x80 | P9_PIR2LOCALCPU(__pir)) +#define PIR2VP_IDX(__pir) (XIVE_HW_VP_BASE | P9_PIR2LOCALCPU(__pir)) #define PIR2VP_BLK(__pir) (xive_chip_to_block(P9_PIR2GCID(__pir))) #define VP2PIR(__blk, __idx) (P9_PIRFROMLOCALCPU(VC_BLK_TO_CHIP(__blk), (__idx) & 0x7f)) @@ -984,7 +991,8 @@ static void xive_init_vp_allocator(void) * These are 0x80..0xff, so order 7 starting at 0x80. This will * reserve that range on each chip. */ - assert(buddy_reserve(xive_vp_buddy, 0x80, 7)); + assert(buddy_reserve(xive_vp_buddy, XIVE_HW_VP_BASE, + XIVE_THREADID_SHIFT)); } static uint32_t xive_alloc_vps(uint32_t order) @@ -1078,7 +1086,7 @@ static void xive_scrub_workaround_vp(struct xive *x, uint32_t block, uint32_t id * Note: This means the workaround only works for block group * mode. */ - __xive_cache_watch(x, xive_cache_vpc, block, INITIAL_VP_BASE, 0, + __xive_cache_watch(x, xive_cache_vpc, block, XIVE_HW_VP_BASE, 0, 0, NULL, true, false); } @@ -1678,8 +1686,8 @@ static bool xive_prealloc_tables(struct xive *x) memset(x->vp_ind_base, 0, al); /* Populate/initialize VP/EQs indirect backing */ - vp_init_count = INITIAL_VP_COUNT; - vp_init_base = INITIAL_VP_BASE; + vp_init_count = XIVE_HW_VP_COUNT; + vp_init_base = XIVE_HW_VP_BASE; /* Allocate pages for some VPs in indirect mode */ pbase = vp_init_base / VP_PER_PAGE; @@ -4475,8 +4483,8 @@ static void xive_reset_one(struct xive *x) struct xive_vp vp0 = {0}; /* Ignore the physical CPU VPs */ - if (i >= INITIAL_VP_BASE && - i < (INITIAL_VP_BASE + INITIAL_VP_COUNT)) + if (i >= XIVE_HW_VP_BASE && + i < (XIVE_HW_VP_BASE + XIVE_HW_VP_COUNT)) continue; /* Is the VP valid ? */ @@ -4583,7 +4591,8 @@ static int64_t __xive_reset(uint64_t version) * These are 0x80..0xff, so order 7 starting at 0x80. This will * reserve that range on each chip. */ - assert(buddy_reserve(xive_vp_buddy, 0x80, 7)); + assert(buddy_reserve(xive_vp_buddy, XIVE_HW_VP_BASE, + XIVE_THREADID_SHIFT)); return OPAL_SUCCESS; }