From patchwork Tue Jun 2 10:09:16 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Serge Semin X-Patchwork-Id: 1302318 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=baikalelectronics.ru Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 49bnqT2fzDz9sSd for ; Tue, 2 Jun 2020 20:10:45 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726856AbgFBKJo (ORCPT ); Tue, 2 Jun 2020 06:09:44 -0400 Received: from mail.baikalelectronics.com ([87.245.175.226]:54824 "EHLO mail.baikalelectronics.ru" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726198AbgFBKJl (ORCPT ); Tue, 2 Jun 2020 06:09:41 -0400 Received: from localhost (unknown [127.0.0.1]) by mail.baikalelectronics.ru (Postfix) with ESMTP id 09B438030808; Tue, 2 Jun 2020 10:09:39 +0000 (UTC) X-Virus-Scanned: amavisd-new at baikalelectronics.ru Received: from mail.baikalelectronics.ru ([127.0.0.1]) by localhost (mail.baikalelectronics.ru [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id scbwbYtlcY9J; Tue, 2 Jun 2020 13:09:37 +0300 (MSK) From: Serge Semin To: Thomas Bogendoerfer , Thomas Gleixner , Greg Kroah-Hartman , Paul Burton , Rob Herring CC: Serge Semin , Serge Semin , Alexey Malahov , Paul Burton , Arnd Bergmann , Jason Cooper , Marc Zyngier , "Rafael J. Wysocki" , Daniel Lezcano , James Hogan , , , , Rob Herring Subject: [PATCH v3 1/6] dt-bindings: power: Convert mti,mips-cpc to DT schema Date: Tue, 2 Jun 2020 13:09:16 +0300 Message-ID: <20200602100921.1155-2-Sergey.Semin@baikalelectronics.ru> In-Reply-To: <20200602100921.1155-1-Sergey.Semin@baikalelectronics.ru> References: <20200602100921.1155-1-Sergey.Semin@baikalelectronics.ru> MIME-Version: 1.0 X-ClientProxiedBy: MAIL.baikal.int (192.168.51.25) To mail (192.168.51.25) Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org It's a Cluster Power Controller embedded into the MIPS IP cores. Currently the corresponding dts node is supposed to have compatible and reg properties. Signed-off-by: Serge Semin Reviewed-by: Rob Herring --- Changelog prev: - Reword the changelog summary - use shorter version. - Lowercase the example hex'es. --- .../bindings/power/mti,mips-cpc.txt | 8 ----- .../bindings/power/mti,mips-cpc.yaml | 35 +++++++++++++++++++ 2 files changed, 35 insertions(+), 8 deletions(-) delete mode 100644 Documentation/devicetree/bindings/power/mti,mips-cpc.txt create mode 100644 Documentation/devicetree/bindings/power/mti,mips-cpc.yaml diff --git a/Documentation/devicetree/bindings/power/mti,mips-cpc.txt b/Documentation/devicetree/bindings/power/mti,mips-cpc.txt deleted file mode 100644 index c6b82511ae8a..000000000000 --- a/Documentation/devicetree/bindings/power/mti,mips-cpc.txt +++ /dev/null @@ -1,8 +0,0 @@ -Binding for MIPS Cluster Power Controller (CPC). - -This binding allows a system to specify where the CPC registers are -located. - -Required properties: -compatible : Should be "mti,mips-cpc". -regs: Should describe the address & size of the CPC register region. diff --git a/Documentation/devicetree/bindings/power/mti,mips-cpc.yaml b/Documentation/devicetree/bindings/power/mti,mips-cpc.yaml new file mode 100644 index 000000000000..9cd92a57130c --- /dev/null +++ b/Documentation/devicetree/bindings/power/mti,mips-cpc.yaml @@ -0,0 +1,35 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/power/mti,mips-cpc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MIPS Cluster Power Controller + +description: | + Defines a location of the MIPS Cluster Power Controller registers. + +maintainers: + - Paul Burton + +properties: + compatible: + const: mti,mips-cpc + + reg: + description: | + Base address and size of an unoccupied memory region, which will be + used to map the MIPS CPC registers block. + maxItems: 1 + +required: + - compatible + - reg + +examples: + - | + cpc@1bde0000 { + compatible = "mti,mips-cpc"; + reg = <0 0x1bde0000 0 0x8000>; + }; +... From patchwork Tue Jun 2 10:09:17 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Serge Semin X-Patchwork-Id: 1302316 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=baikalelectronics.ru Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 49bnqD66Dtz9sSd for ; Tue, 2 Jun 2020 20:10:32 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728294AbgFBKKb (ORCPT ); Tue, 2 Jun 2020 06:10:31 -0400 Received: from mail.baikalelectronics.com ([87.245.175.226]:54844 "EHLO mail.baikalelectronics.ru" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726785AbgFBKJq (ORCPT ); Tue, 2 Jun 2020 06:09:46 -0400 Received: from localhost (unknown [127.0.0.1]) by mail.baikalelectronics.ru (Postfix) with ESMTP id 2E5048030836; Tue, 2 Jun 2020 10:09:40 +0000 (UTC) X-Virus-Scanned: amavisd-new at baikalelectronics.ru Received: from mail.baikalelectronics.ru ([127.0.0.1]) by localhost (mail.baikalelectronics.ru [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id TtgB5ZNz8eqX; Tue, 2 Jun 2020 13:09:38 +0300 (MSK) From: Serge Semin To: Thomas Bogendoerfer , Thomas Gleixner , Greg Kroah-Hartman , Jason Cooper , Marc Zyngier , Rob Herring CC: Serge Semin , Serge Semin , Alexey Malahov , Paul Burton , Arnd Bergmann , "Rafael J. Wysocki" , Daniel Lezcano , James Hogan , , , , Rob Herring Subject: [PATCH v3 2/6] dt-bindings: interrupt-controller: Convert mti,gic to DT schema Date: Tue, 2 Jun 2020 13:09:17 +0300 Message-ID: <20200602100921.1155-3-Sergey.Semin@baikalelectronics.ru> In-Reply-To: <20200602100921.1155-1-Sergey.Semin@baikalelectronics.ru> References: <20200602100921.1155-1-Sergey.Semin@baikalelectronics.ru> MIME-Version: 1.0 X-ClientProxiedBy: MAIL.baikal.int (192.168.51.25) To mail (192.168.51.25) Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Modern device tree bindings are supposed to be created as YAML-files in accordance with DT schema. This commit replaces MIPS GIC legacy bare text binding with YAML file. As before the binding file states that the corresponding dts node is supposed to be compatible with MIPS Global Interrupt Controller indicated by the "mti,gic" compatible string and to provide a mandatory interrupt-controller and '#interrupt-cells' properties. There might be optional registers memory range, "mti,reserved-cpu-vectors" and "mti,reserved-ipi-vectors" properties specified. MIPS GIC also includes a free-running global timer, per-CPU count/compare timers, and a watchdog. Since currently the GIC Timer is only supported the DT schema expects an IRQ and clock-phandler charged timer sub-node with "mti,mips-gic-timer" compatible string. Signed-off-by: Serge Semin Reviewed-by: Rob Herring --- I don't really know who is the corresponding driver maintainer, so I added Paul to the maintainers property since he used to be looking for the MIPS arch and Thomas looking after it now. Any idea what email should be specified there instead? Changelog prev: - Since timer sub-node has no unit-address, the node shouldn't be named with one. So alter the MIPS GIC bindings to have a pure "timer" sub-node. - Discard allOf: [ $ref: /schemas/interrupt-controller.yaml# ]. - Since it's a conversion patch use GPL-2.0-only SPDX header. --- .../interrupt-controller/mips-gic.txt | 67 -------- .../interrupt-controller/mti,gic.yaml | 148 ++++++++++++++++++ 2 files changed, 148 insertions(+), 67 deletions(-) delete mode 100644 Documentation/devicetree/bindings/interrupt-controller/mips-gic.txt create mode 100644 Documentation/devicetree/bindings/interrupt-controller/mti,gic.yaml diff --git a/Documentation/devicetree/bindings/interrupt-controller/mips-gic.txt b/Documentation/devicetree/bindings/interrupt-controller/mips-gic.txt deleted file mode 100644 index 173595305e26..000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/mips-gic.txt +++ /dev/null @@ -1,67 +0,0 @@ -MIPS Global Interrupt Controller (GIC) - -The MIPS GIC routes external interrupts to individual VPEs and IRQ pins. -It also supports local (per-processor) interrupts and software-generated -interrupts which can be used as IPIs. The GIC also includes a free-running -global timer, per-CPU count/compare timers, and a watchdog. - -Required properties: -- compatible : Should be "mti,gic". -- interrupt-controller : Identifies the node as an interrupt controller -- #interrupt-cells : Specifies the number of cells needed to encode an - interrupt specifier. Should be 3. - - The first cell is the type of interrupt, local or shared. - See . - - The second cell is the GIC interrupt number. - - The third cell encodes the interrupt flags. - See for a list of valid - flags. - -Optional properties: -- reg : Base address and length of the GIC registers. If not present, - the base address reported by the hardware GCR_GIC_BASE will be used. -- mti,reserved-cpu-vectors : Specifies the list of CPU interrupt vectors - to which the GIC may not route interrupts. Valid values are 2 - 7. - This property is ignored if the CPU is started in EIC mode. -- mti,reserved-ipi-vectors : Specifies the range of GIC interrupts that are - reserved for IPIs. - It accepts 2 values, the 1st is the starting interrupt and the 2nd is the size - of the reserved range. - If not specified, the driver will allocate the last 2 * number of VPEs in the - system. - -Required properties for timer sub-node: -- compatible : Should be "mti,gic-timer". -- interrupts : Interrupt for the GIC local timer. - -Optional properties for timer sub-node: -- clocks : GIC timer operating clock. -- clock-frequency : Clock frequency at which the GIC timers operate. - -Note that one of clocks or clock-frequency must be specified. - -Example: - - gic: interrupt-controller@1bdc0000 { - compatible = "mti,gic"; - reg = <0x1bdc0000 0x20000>; - - interrupt-controller; - #interrupt-cells = <3>; - - mti,reserved-cpu-vectors = <7>; - mti,reserved-ipi-vectors = <40 8>; - - timer { - compatible = "mti,gic-timer"; - interrupts = ; - clock-frequency = <50000000>; - }; - }; - - uart@18101400 { - ... - interrupt-parent = <&gic>; - interrupts = ; - ... - }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/mti,gic.yaml b/Documentation/devicetree/bindings/interrupt-controller/mti,gic.yaml new file mode 100644 index 000000000000..9f0eb3addac4 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/mti,gic.yaml @@ -0,0 +1,148 @@ +# SPDX-License-Identifier: GPL-2.0-only +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/mti,gic.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MIPS Global Interrupt Controller + +maintainers: + - Paul Burton + - Thomas Bogendoerfer + +description: | + The MIPS GIC routes external interrupts to individual VPEs and IRQ pins. + It also supports local (per-processor) interrupts and software-generated + interrupts which can be used as IPIs. The GIC also includes a free-running + global timer, per-CPU count/compare timers, and a watchdog. + +properties: + compatible: + const: mti,gic + + "#interrupt-cells": + const: 3 + description: | + The 1st cell is the type of interrupt: local or shared defined in the + file 'dt-bindings/interrupt-controller/mips-gic.h'. The 2nd cell is the + GIC interrupt number. The 3d cell encodes the interrupt flags setting up + the IRQ trigger modes, which are defined in the file + 'dt-bindings/interrupt-controller/irq.h'. + + reg: + description: | + Base address and length of the GIC registers space. If not present, + the base address reported by the hardware GCR_GIC_BASE will be used. + maxItems: 1 + + interrupt-controller: true + + mti,reserved-cpu-vectors: + description: | + Specifies the list of CPU interrupt vectors to which the GIC may not + route interrupts. This property is ignored if the CPU is started in EIC + mode. + allOf: + - $ref: /schemas/types.yaml#definitions/uint32-array + - minItems: 1 + maxItems: 6 + uniqueItems: true + items: + minimum: 2 + maximum: 7 + + mti,reserved-ipi-vectors: + description: | + Specifies the range of GIC interrupts that are reserved for IPIs. + It accepts two values: the 1st is the starting interrupt and the 2nd is + the size of the reserved range. If not specified, the driver will + allocate the last (2 * number of VPEs in the system). + allOf: + - $ref: /schemas/types.yaml#definitions/uint32-array + - items: + - minimum: 0 + maximum: 254 + - minimum: 2 + maximum: 254 + + timer: + type: object + description: | + MIPS GIC includes a free-running global timer, per-CPU count/compare + timers, and a watchdog. Currently only the GIC Timer is supported. + properties: + compatible: + const: mti,gic-timer + + interrupts: + description: | + Interrupt for the GIC local timer, so normally it's suppose to be of + format. + maxItems: 1 + + clocks: + maxItems: 1 + + clock-frequency: true + + required: + - compatible + - interrupts + + oneOf: + - required: + - clocks + - required: + - clock-frequency + + additionalProperties: false + +unevaluatedProperties: false + +required: + - compatible + - "#interrupt-cells" + - interrupt-controller + +examples: + - | + #include + #include + + interrupt-controller@1bdc0000 { + compatible = "mti,gic"; + reg = <0x1bdc0000 0x20000>; + interrupt-controller; + #interrupt-cells = <3>; + mti,reserved-cpu-vectors = <7>; + mti,reserved-ipi-vectors = <40 8>; + + timer { + compatible = "mti,gic-timer"; + interrupts = ; + clock-frequency = <50000000>; + }; + }; + - | + #include + #include + + interrupt-controller@1bdc0000 { + compatible = "mti,gic"; + reg = <0x1bdc0000 0x20000>; + interrupt-controller; + #interrupt-cells = <3>; + + timer { + compatible = "mti,gic-timer"; + interrupts = ; + clocks = <&cpu_pll>; + }; + }; + - | + interrupt-controller { + compatible = "mti,gic"; + interrupt-controller; + #interrupt-cells = <3>; + }; +... From patchwork Tue Jun 2 10:09:18 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Serge Semin X-Patchwork-Id: 1302320 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=baikalelectronics.ru Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 49bnqb0CsGz9sSn for ; Tue, 2 Jun 2020 20:10:51 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728338AbgFBKKm (ORCPT ); Tue, 2 Jun 2020 06:10:42 -0400 Received: from mail.baikalelectronics.com ([87.245.175.226]:54902 "EHLO mail.baikalelectronics.ru" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726817AbgFBKJo (ORCPT ); Tue, 2 Jun 2020 06:09:44 -0400 Received: from localhost (unknown [127.0.0.1]) by mail.baikalelectronics.ru (Postfix) with ESMTP id 215F4803083D; Tue, 2 Jun 2020 10:09:41 +0000 (UTC) X-Virus-Scanned: amavisd-new at baikalelectronics.ru Received: from mail.baikalelectronics.ru ([127.0.0.1]) by localhost (mail.baikalelectronics.ru [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id vbeNukD9DW12; Tue, 2 Jun 2020 13:09:39 +0300 (MSK) From: Serge Semin To: Thomas Bogendoerfer , Thomas Gleixner , Greg Kroah-Hartman , Rob Herring CC: Serge Semin , Serge Semin , Alexey Malahov , Paul Burton , Arnd Bergmann , Jason Cooper , Marc Zyngier , "Rafael J. Wysocki" , Daniel Lezcano , James Hogan , , , , Rob Herring Subject: [PATCH v3 3/6] dt-bindings: bus: Add MIPS CDMM controller Date: Tue, 2 Jun 2020 13:09:18 +0300 Message-ID: <20200602100921.1155-4-Sergey.Semin@baikalelectronics.ru> In-Reply-To: <20200602100921.1155-1-Sergey.Semin@baikalelectronics.ru> References: <20200602100921.1155-1-Sergey.Semin@baikalelectronics.ru> MIME-Version: 1.0 X-ClientProxiedBy: MAIL.baikal.int (192.168.51.25) To mail (192.168.51.25) Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org It's a Common Device Memory Map controller embedded into the MIPS IP cores, which dts node is supposed to have compatible and reg properties. Signed-off-by: Serge Semin Reviewed-by: Rob Herring --- Changelog prev: - Lowercase the example hex'es. --- .../bindings/bus/mti,mips-cdmm.yaml | 35 +++++++++++++++++++ 1 file changed, 35 insertions(+) create mode 100644 Documentation/devicetree/bindings/bus/mti,mips-cdmm.yaml diff --git a/Documentation/devicetree/bindings/bus/mti,mips-cdmm.yaml b/Documentation/devicetree/bindings/bus/mti,mips-cdmm.yaml new file mode 100644 index 000000000000..b3ba98515cbe --- /dev/null +++ b/Documentation/devicetree/bindings/bus/mti,mips-cdmm.yaml @@ -0,0 +1,35 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/bus/mti,mips-cdmm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MIPS Common Device Memory Map + +description: | + Defines a location of the MIPS Common Device Memory Map registers. + +maintainers: + - James Hogan + +properties: + compatible: + const: mti,mips-cdmm + + reg: + description: | + Base address and size of an unoccupied memory region, which will be + used to map the MIPS CDMM registers block. + maxItems: 1 + +required: + - compatible + - reg + +examples: + - | + cdmm@1bde8000 { + compatible = "mti,mips-cdmm"; + reg = <0 0x1bde8000 0 0x8000>; + }; +...