From patchwork Fri May 29 23:07:50 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Segher Boessenkool X-Patchwork-Id: 1301076 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=8.43.85.97; helo=sourceware.org; envelope-from=gcc-patches-bounces@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=kernel.crashing.org Received: from sourceware.org (server2.sourceware.org [8.43.85.97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 49YgGB01Z7z9sSF for ; Sat, 30 May 2020 09:08:00 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 5329D386F816; Fri, 29 May 2020 23:07:57 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from gcc1-power7.osuosl.org (gcc1-power7.osuosl.org [140.211.15.137]) by sourceware.org (Postfix) with ESMTP id 4C1F7386EC5C for ; Fri, 29 May 2020 23:07:54 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.3.2 sourceware.org 4C1F7386EC5C Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=kernel.crashing.org Authentication-Results: sourceware.org; spf=none smtp.mailfrom=segher@gcc1-power7.osuosl.org Received: by gcc1-power7.osuosl.org (Postfix, from userid 10019) id 4D4F412402F1; Fri, 29 May 2020 23:07:53 +0000 (UTC) From: Segher Boessenkool To: gcc-patches@gcc.gnu.org Subject: [PATCH] rs6000: Prefer VSX insns over VMX ones (part 1: perm and mrg) Date: Fri, 29 May 2020 23:07:50 +0000 Message-Id: <562cc4b13dbb33037e5a1c318dbdab00a1a8bfec.1590792592.git.segher@kernel.crashing.org> X-Mailer: git-send-email 1.8.3.1 X-Spam-Status: No, score=-14.0 required=5.0 tests=BAYES_00, GIT_PATCH_0, HEADER_FROM_DIFFERENT_DOMAINS, KAM_DMARC_STATUS, KAM_LAZY_DOMAIN_SECURITY, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Segher Boessenkool , dje.gcc@gmail.com Errors-To: gcc-patches-bounces@gcc.gnu.org Sender: "Gcc-patches" There are various VSX insns that do the same job as (older) AltiVec insns, just with a wider range of possible registers. Many patterns for such insns have the "v" alternative before the "wa" alternative, which makes the output less readable than possible (since vs32 is v0, and most insns before or after this insn will be VSX as well). This changes the define_insns for the mrg and perm machine instructions to prefer the VSX form. No behaviour change. Only one testcase needed a little adjustment as well. Tested on powerpc64-linux {-m32,-m64}. Applying to trunk. Segher 2020-05-29 Segher Boessenkool * config/rs6000/altivec.md (altivec_vmrghw_direct): Prefer VSX form. (altivec_vmrglw_direct): Ditto. (altivec_vperm__direct): Ditto. (altivec_vperm_v8hiv16qi): Ditto. (*altivec_vperm__uns_internal): Ditto. (*altivec_vpermr__internal): Ditto. (vperm_v8hiv4si): Ditto. (vperm_v16qiv8hi): Ditto. testsuite/ * gcc.target/powerpc/vsx-vector-6.p9.c: Allow xxperm as perm as well. --- gcc/config/rs6000/altivec.md | 104 ++++++++++----------- gcc/testsuite/gcc.target/powerpc/vsx-vector-6.p9.c | 2 +- 2 files changed, 53 insertions(+), 53 deletions(-) diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md index 792ca4f..159f24e 100644 --- a/gcc/config/rs6000/altivec.md +++ b/gcc/config/rs6000/altivec.md @@ -1216,14 +1216,14 @@ (define_insn "*altivec_vmrghw_internal" [(set_attr "type" "vecperm")]) (define_insn "altivec_vmrghw_direct" - [(set (match_operand:V4SI 0 "register_operand" "=v,wa") - (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v,wa") - (match_operand:V4SI 2 "register_operand" "v,wa")] + [(set (match_operand:V4SI 0 "register_operand" "=wa,v") + (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "wa,v") + (match_operand:V4SI 2 "register_operand" "wa,v")] UNSPEC_VMRGH_DIRECT))] "TARGET_ALTIVEC" "@ - vmrghw %0,%1,%2 - xxmrghw %x0,%x1,%x2" + xxmrghw %x0,%x1,%x2 + vmrghw %0,%1,%2" [(set_attr "type" "vecperm")]) (define_insn "*altivec_vmrghsf" @@ -1364,14 +1364,14 @@ (define_insn "*altivec_vmrglw_internal" [(set_attr "type" "vecperm")]) (define_insn "altivec_vmrglw_direct" - [(set (match_operand:V4SI 0 "register_operand" "=v,wa") - (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v,wa") - (match_operand:V4SI 2 "register_operand" "v,wa")] + [(set (match_operand:V4SI 0 "register_operand" "=wa,v") + (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "wa,v") + (match_operand:V4SI 2 "register_operand" "wa,v")] UNSPEC_VMRGL_DIRECT))] "TARGET_ALTIVEC" "@ - vmrglw %0,%1,%2 - xxmrglw %x0,%x1,%x2" + xxmrglw %x0,%x1,%x2 + vmrglw %0,%1,%2" [(set_attr "type" "vecperm")]) (define_insn "*altivec_vmrglsf" @@ -2193,30 +2193,30 @@ (define_expand "altivec_vperm_" ;; Slightly prefer vperm, since the target does not overlap the source (define_insn "altivec_vperm__direct" - [(set (match_operand:VM 0 "register_operand" "=v,?wa") - (unspec:VM [(match_operand:VM 1 "register_operand" "v,wa") - (match_operand:VM 2 "register_operand" "v,0") - (match_operand:V16QI 3 "register_operand" "v,wa")] + [(set (match_operand:VM 0 "register_operand" "=?wa,v") + (unspec:VM [(match_operand:VM 1 "register_operand" "wa,v") + (match_operand:VM 2 "register_operand" "0,v") + (match_operand:V16QI 3 "register_operand" "wa,v")] UNSPEC_VPERM))] "TARGET_ALTIVEC" "@ - vperm %0,%1,%2,%3 - xxperm %x0,%x1,%x3" + xxperm %x0,%x1,%x3 + vperm %0,%1,%2,%3" [(set_attr "type" "vecperm") - (set_attr "isa" "*,p9v")]) + (set_attr "isa" "p9v,*")]) (define_insn "altivec_vperm_v8hiv16qi" - [(set (match_operand:V16QI 0 "register_operand" "=v,?wa") - (unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v,wa") - (match_operand:V8HI 2 "register_operand" "v,0") - (match_operand:V16QI 3 "register_operand" "v,wa")] + [(set (match_operand:V16QI 0 "register_operand" "=?wa,v") + (unspec:V16QI [(match_operand:V8HI 1 "register_operand" "wa,v") + (match_operand:V8HI 2 "register_operand" "0,v") + (match_operand:V16QI 3 "register_operand" "wa,v")] UNSPEC_VPERM))] "TARGET_ALTIVEC" "@ - vperm %0,%1,%2,%3 - xxperm %x0,%x1,%x3" + xxperm %x0,%x1,%x3 + vperm %0,%1,%2,%3" [(set_attr "type" "vecperm") - (set_attr "isa" "*,p9v")]) + (set_attr "isa" "p9v,*")]) (define_expand "altivec_vperm__uns" [(set (match_operand:VM 0 "register_operand") @@ -2234,17 +2234,17 @@ (define_expand "altivec_vperm__uns" }) (define_insn "*altivec_vperm__uns_internal" - [(set (match_operand:VM 0 "register_operand" "=v,?wa") - (unspec:VM [(match_operand:VM 1 "register_operand" "v,wa") - (match_operand:VM 2 "register_operand" "v,0") - (match_operand:V16QI 3 "register_operand" "v,wa")] + [(set (match_operand:VM 0 "register_operand" "=?wa,v") + (unspec:VM [(match_operand:VM 1 "register_operand" "wa,v") + (match_operand:VM 2 "register_operand" "0,v") + (match_operand:V16QI 3 "register_operand" "wa,v")] UNSPEC_VPERM_UNS))] "TARGET_ALTIVEC" "@ - vperm %0,%1,%2,%3 - xxperm %x0,%x1,%x3" + xxperm %x0,%x1,%x3 + vperm %0,%1,%2,%3" [(set_attr "type" "vecperm") - (set_attr "isa" "*,p9v")]) + (set_attr "isa" "p9v,*")]) (define_expand "vec_permv16qi" [(set (match_operand:V16QI 0 "register_operand") @@ -2261,17 +2261,17 @@ (define_expand "vec_permv16qi" }) (define_insn "*altivec_vpermr__internal" - [(set (match_operand:VM 0 "register_operand" "=v,?wa") - (unspec:VM [(match_operand:VM 1 "register_operand" "v,wa") - (match_operand:VM 2 "register_operand" "v,0") - (match_operand:V16QI 3 "register_operand" "v,wa")] + [(set (match_operand:VM 0 "register_operand" "=?wa,v") + (unspec:VM [(match_operand:VM 1 "register_operand" "wa,v") + (match_operand:VM 2 "register_operand" "0,v") + (match_operand:V16QI 3 "register_operand" "wa,v")] UNSPEC_VPERMR))] "TARGET_P9_VECTOR" "@ - vpermr %0,%1,%2,%3 - xxpermr %x0,%x1,%x3" + xxpermr %x0,%x1,%x3 + vpermr %0,%1,%2,%3" [(set_attr "type" "vecperm") - (set_attr "isa" "*,p9v")]) + (set_attr "isa" "p9v,*")]) (define_insn "altivec_vrfip" ; ceil [(set (match_operand:V4SF 0 "register_operand" "=v") @@ -3414,30 +3414,30 @@ (define_expand "vec_unpacks_lo_" "") (define_insn "vperm_v8hiv4si" - [(set (match_operand:V4SI 0 "register_operand" "=v,?wa") - (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v,wa") - (match_operand:V4SI 2 "register_operand" "v,0") - (match_operand:V16QI 3 "register_operand" "v,wa")] + [(set (match_operand:V4SI 0 "register_operand" "=?wa,v") + (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "wa,v") + (match_operand:V4SI 2 "register_operand" "0,v") + (match_operand:V16QI 3 "register_operand" "wa,v")] UNSPEC_VPERMSI))] "TARGET_ALTIVEC" "@ - vperm %0,%1,%2,%3 - xxperm %x0,%x1,%x3" + xxperm %x0,%x1,%x3 + vperm %0,%1,%2,%3" [(set_attr "type" "vecperm") - (set_attr "isa" "*,p9v")]) + (set_attr "isa" "p9v,*")]) (define_insn "vperm_v16qiv8hi" - [(set (match_operand:V8HI 0 "register_operand" "=v,?wa") - (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v,wa") - (match_operand:V8HI 2 "register_operand" "v,0") - (match_operand:V16QI 3 "register_operand" "v,wa")] + [(set (match_operand:V8HI 0 "register_operand" "=?wa,v") + (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "wa,v") + (match_operand:V8HI 2 "register_operand" "0,v") + (match_operand:V16QI 3 "register_operand" "wa,v")] UNSPEC_VPERMHI))] "TARGET_ALTIVEC" "@ - vperm %0,%1,%2,%3 - xxperm %x0,%x1,%x3" + xxperm %x0,%x1,%x3 + vperm %0,%1,%2,%3" [(set_attr "type" "vecperm") - (set_attr "isa" "*,p9v")]) + (set_attr "isa" "p9v,*")]) (define_insn "xxeval" [(set (match_operand:V2DI 0 "register_operand" "=wa") diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-vector-6.p9.c b/gcc/testsuite/gcc.target/powerpc/vsx-vector-6.p9.c index eabdf71..43d2e85 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsx-vector-6.p9.c +++ b/gcc/testsuite/gcc.target/powerpc/vsx-vector-6.p9.c @@ -9,7 +9,7 @@ /* { dg-final { scan-assembler-times {\mvmaxub\M} 1 } } */ /* { dg-final { scan-assembler-times {\mvmsumshs\M} 1 } } */ /* { dg-final { scan-assembler-times {\mvmsumuhs\M} 1 } } */ -/* { dg-final { scan-assembler-times {\mvpermr?\M} 1 } } */ +/* { dg-final { scan-assembler-times {\m(?:vpermr?|xxperm)\M} 1 } } */ /* { dg-final { scan-assembler-times {\mxvabsdp\M} 1 } } */ /* { dg-final { scan-assembler-times {\mxvadddp\M} 1 } } */ /* { dg-final { scan-assembler-times {\mxvcmpeqdp\M} 9 } } */