From patchwork Fri May 8 08:29:31 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Roger Quadros X-Patchwork-Id: 1285912 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=ti.com header.i=@ti.com header.a=rsa-sha256 header.s=ti-com-17Q1 header.b=yFRDlehr; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 49JNn41xp6z9sSy for ; Fri, 8 May 2020 18:30:16 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726797AbgEHI3q (ORCPT ); Fri, 8 May 2020 04:29:46 -0400 Received: from fllv0015.ext.ti.com ([198.47.19.141]:49582 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726598AbgEHI3q (ORCPT ); Fri, 8 May 2020 04:29:46 -0400 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 0488Tido023273; Fri, 8 May 2020 03:29:44 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1588926584; bh=nAlvTGsJH+rs2JUDiU2G2Y01gpAIibR+kM4znZi5wVA=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=yFRDlehr15XZcdpOmPVA/p5UXlpUpyMFS/KcF/8xGTygTBkpoTwobCxrtZEMvFFnf 9cdctCi5r3lcQkau5N8SpMCfLWNlUGTdEkh/3lD38o/gF48b/KvqkhIsWN2V2t3A1E KPMOo9eT4KNF4H4lzklbK4FFgWPaCM30Bsl9H6tM= Received: from DFLE100.ent.ti.com (dfle100.ent.ti.com [10.64.6.21]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTP id 0488TiM8099863; Fri, 8 May 2020 03:29:44 -0500 Received: from DFLE113.ent.ti.com (10.64.6.34) by DFLE100.ent.ti.com (10.64.6.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Fri, 8 May 2020 03:29:44 -0500 Received: from fllv0039.itg.ti.com (10.64.41.19) by DFLE113.ent.ti.com (10.64.6.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Fri, 8 May 2020 03:29:44 -0500 Received: from lta0400828a.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id 0488TdnA073953; Fri, 8 May 2020 03:29:42 -0500 From: Roger Quadros To: CC: , , , , , , Subject: [PATCH v3 1/7] dt-bindings: syscon: Add TI's J721E specific compatible string Date: Fri, 8 May 2020 11:29:31 +0300 Message-ID: <20200508082937.14171-2-rogerq@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200508082937.14171-1-rogerq@ti.com> References: <20200508082937.14171-1-rogerq@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Kishon Vijay Abraham I Add TI's J721E SoC specific compatible string. Signed-off-by: Kishon Vijay Abraham I --- Documentation/devicetree/bindings/mfd/syscon.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/mfd/syscon.yaml b/Documentation/devicetree/bindings/mfd/syscon.yaml index 39375e4313d2..f9aac75d423a 100644 --- a/Documentation/devicetree/bindings/mfd/syscon.yaml +++ b/Documentation/devicetree/bindings/mfd/syscon.yaml @@ -38,6 +38,7 @@ properties: - allwinner,sun8i-h3-system-controller - allwinner,sun8i-v3s-system-controller - allwinner,sun50i-a64-system-controller + - ti,j721e-system-controller - const: syscon From patchwork Fri May 8 08:29:32 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Roger Quadros X-Patchwork-Id: 1285911 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=ti.com header.i=@ti.com header.a=rsa-sha256 header.s=ti-com-17Q1 header.b=MT+praZI; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 49JNn31cmZz9sSr for ; Fri, 8 May 2020 18:30:15 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726926AbgEHI3t (ORCPT ); Fri, 8 May 2020 04:29:49 -0400 Received: from fllv0015.ext.ti.com ([198.47.19.141]:49590 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726598AbgEHI3t (ORCPT ); Fri, 8 May 2020 04:29:49 -0400 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 0488Tl2n023283; Fri, 8 May 2020 03:29:47 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1588926587; bh=G8AEr6yO/8wQ/72kKdriOSTyiW/u5Zm0KpMdh2r29ME=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=MT+praZIYsz7gB41jWDMpUry0zi8239P4bj9hzsy5INL0bVCQCkcOhrfWWJuEsdwf mD/o3+YsqhkzrTk79AcNsjBuv4unqsRLkeJzFXYfgM1ITOfmjT70WKDIXOhsBpzGIw 22a3FeWOeN2ULU0sx/rnFuTVBXOSe36HSxtK9Q7Q= Received: from DLEE112.ent.ti.com (dlee112.ent.ti.com [157.170.170.23]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 0488Tlnv118636 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 8 May 2020 03:29:47 -0500 Received: from DLEE113.ent.ti.com (157.170.170.24) by DLEE112.ent.ti.com (157.170.170.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Fri, 8 May 2020 03:29:47 -0500 Received: from fllv0039.itg.ti.com (10.64.41.19) by DLEE113.ent.ti.com (157.170.170.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Fri, 8 May 2020 03:29:47 -0500 Received: from lta0400828a.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id 0488TdnB073953; Fri, 8 May 2020 03:29:45 -0500 From: Roger Quadros To: CC: , , , , , , , Roger Quadros Subject: [PATCH v3 2/7] dt-bindings: mdf: ti,j721e-syscon.yaml: Add J721e system controller Date: Fri, 8 May 2020 11:29:32 +0300 Message-ID: <20200508082937.14171-3-rogerq@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200508082937.14171-1-rogerq@ti.com> References: <20200508082937.14171-1-rogerq@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add DT binding schema for J721e system controller. Signed-off-by: Roger Quadros Signed-off-by: Roger Quadros --- .../bindings/mfd/ti,j721e-syscon.yaml | 69 +++++++++++++++++++ 1 file changed, 69 insertions(+) create mode 100644 Documentation/devicetree/bindings/mfd/ti,j721e-syscon.yaml diff --git a/Documentation/devicetree/bindings/mfd/ti,j721e-syscon.yaml b/Documentation/devicetree/bindings/mfd/ti,j721e-syscon.yaml new file mode 100644 index 000000000000..e832fb43f884 --- /dev/null +++ b/Documentation/devicetree/bindings/mfd/ti,j721e-syscon.yaml @@ -0,0 +1,69 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/ +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mfd/ti,j721e-syscon.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: TI J721e System Controller Registers R/W Device Tree Bindings + +description: | + This represents the Control Module registers (CTRL_MMR0) on the SoC. + System controller node represents a register region containing a set + of miscellaneous registers. The registers are not cohesive enough to + represent as any specific type of device. The typical use-case is + for some other node's driver, or platform-specific code, to acquire + a reference to the syscon node (e.g. by phandle, node path, or + search using a specific compatible value), interrogate the node (or + associated OS driver) to determine the location of the registers, + and access the registers directly. + +maintainers: + - Kishon Vijay Abraham I + - Roger Quadros ; + #address-cells = <1>; + #size-cells = <1>; + + serdes_ln_ctrl: serdes-ln-ctrl@4080 { + compatible = "mmio-mux"; + reg = <0x00004080 0x50>; + }; + }; +... From patchwork Fri May 8 08:29:34 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Roger Quadros X-Patchwork-Id: 1285910 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=ti.com header.i=@ti.com header.a=rsa-sha256 header.s=ti-com-17Q1 header.b=OZO8R7FO; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 49JNmh5gGRz9sSr for ; Fri, 8 May 2020 18:29:56 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727067AbgEHI3y (ORCPT ); Fri, 8 May 2020 04:29:54 -0400 Received: from fllv0015.ext.ti.com ([198.47.19.141]:49608 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727097AbgEHI3y (ORCPT ); Fri, 8 May 2020 04:29:54 -0400 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 0488TqOe023311; Fri, 8 May 2020 03:29:52 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1588926592; bh=jcALnYcXc5HLiGeqGLSuje+R1aeUc2Rm5kp1+8sNXV0=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=OZO8R7FOwJpFCLeaHL0PiGLKCT1iMfT0oxmnbTn3oURgt+e8gCMA1b9N3X4ohNZHG H4dJIn92nkpf8c+XgVmBlq5cY6S2n9i8tGEMIEAS0VtCNNaoEiS4/UgE7GYqgb69qR hj3IDVzlkQPQ0c7Ft5fdXCehWWbBMOKvgcFKauDQ= Received: from DFLE104.ent.ti.com (dfle104.ent.ti.com [10.64.6.25]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 0488TqAW103060 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 8 May 2020 03:29:52 -0500 Received: from DFLE102.ent.ti.com (10.64.6.23) by DFLE104.ent.ti.com (10.64.6.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Fri, 8 May 2020 03:29:51 -0500 Received: from fllv0039.itg.ti.com (10.64.41.19) by DFLE102.ent.ti.com (10.64.6.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Fri, 8 May 2020 03:29:51 -0500 Received: from lta0400828a.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id 0488TdnD073953; Fri, 8 May 2020 03:29:49 -0500 From: Roger Quadros To: CC: , , , , , , , Roger Quadros Subject: [PATCH v3 4/7] arm64: dts: ti: k3-j721e-main: Add system controller node and SERDES lane mux Date: Fri, 8 May 2020 11:29:34 +0300 Message-ID: <20200508082937.14171-5-rogerq@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200508082937.14171-1-rogerq@ti.com> References: <20200508082937.14171-1-rogerq@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Kishon Vijay Abraham I The system controller node manages the CTRL_MMR0 region. Add serdes_ln_ctrl node which is used for controlling the SERDES lane mux. Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Roger Quadros --- arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 27 ++++++++++++ include/dt-bindings/mux/mux-j721e-wiz.h | 53 +++++++++++++++++++++++ 2 files changed, 80 insertions(+) create mode 100644 include/dt-bindings/mux/mux-j721e-wiz.h diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi index cbaadee5bfdc..b8b68951771b 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi @@ -5,6 +5,8 @@ * Copyright (C) 2016-2019 Texas Instruments Incorporated - http://www.ti.com/ */ #include +#include +#include &cbass_main { msmc_ram: sram@70000000 { @@ -19,6 +21,31 @@ }; }; + scm_conf: scm-conf@100000 { + compatible = "ti,j721e-system-controller", "syscon", "simple-mfd"; + reg = <0 0x00100000 0 0x1c000>; /* excludes pinctrl region */ + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x00100000 0x1c000>; + + serdes_ln_ctrl: serdes-ln-ctrl@4080 { + compatible = "mmio-mux"; + reg = <0x00004080 0x50>; + #mux-control-cells = <1>; + mux-reg-masks = <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */ + <0x4090 0x3>, <0x4094 0x3>, /* SERDES1 lane0/1 select */ + <0x40a0 0x3>, <0x40a4 0x3>, /* SERDES2 lane0/1 select */ + <0x40b0 0x3>, <0x40b4 0x3>, /* SERDES3 lane0/1 select */ + <0x40c0 0x3>, <0x40c4 0x3>, <0x40c8 0x3>, <0x40cc 0x3>; + /* SERDES4 lane0/1/2/3 select */ + idle-states = , , + , , + , , + , , + , , , ; + }; + }; + gic500: interrupt-controller@1800000 { compatible = "arm,gic-v3"; #address-cells = <2>; diff --git a/include/dt-bindings/mux/mux-j721e-wiz.h b/include/dt-bindings/mux/mux-j721e-wiz.h new file mode 100644 index 000000000000..fd1c4ea9fc7f --- /dev/null +++ b/include/dt-bindings/mux/mux-j721e-wiz.h @@ -0,0 +1,53 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * This header provides constants for J721E WIZ. + */ + +#ifndef _DT_BINDINGS_J721E_WIZ +#define _DT_BINDINGS_J721E_WIZ + +#define SERDES0_LANE0_QSGMII_LANE1 0x0 +#define SERDES0_LANE0_PCIE0_LANE0 0x1 +#define SERDES0_LANE0_USB3_0_SWAP 0x2 + +#define SERDES0_LANE1_QSGMII_LANE2 0x0 +#define SERDES0_LANE1_PCIE0_LANE1 0x1 +#define SERDES0_LANE1_USB3_0 0x2 + +#define SERDES1_LANE0_QSGMII_LANE3 0x0 +#define SERDES1_LANE0_PCIE1_LANE0 0x1 +#define SERDES1_LANE0_USB3_1_SWAP 0x2 +#define SERDES1_LANE0_SGMII_LANE0 0x3 + +#define SERDES1_LANE1_QSGMII_LANE4 0x0 +#define SERDES1_LANE1_PCIE1_LANE1 0x1 +#define SERDES1_LANE1_USB3_1 0x2 +#define SERDES1_LANE1_SGMII_LANE1 0x3 + +#define SERDES2_LANE0_PCIE2_LANE0 0x1 +#define SERDES2_LANE0_SGMII_LANE0 0x3 +#define SERDES2_LANE0_USB3_1_SWAP 0x2 + +#define SERDES2_LANE1_PCIE2_LANE1 0x1 +#define SERDES2_LANE1_USB3_1 0x2 +#define SERDES2_LANE1_SGMII_LANE1 0x3 + +#define SERDES3_LANE0_PCIE3_LANE0 0x1 +#define SERDES3_LANE0_USB3_0_SWAP 0x2 + +#define SERDES3_LANE1_PCIE3_LANE1 0x1 +#define SERDES3_LANE1_USB3_0 0x2 + +#define SERDES4_LANE0_EDP_LANE0 0x0 +#define SERDES4_LANE0_QSGMII_LANE5 0x2 + +#define SERDES4_LANE1_EDP_LANE1 0x0 +#define SERDES4_LANE1_QSGMII_LANE6 0x2 + +#define SERDES4_LANE2_EDP_LANE2 0x0 +#define SERDES4_LANE2_QSGMII_LANE7 0x2 + +#define SERDES4_LANE3_EDP_LANE3 0x0 +#define SERDES4_LANE3_QSGMII_LANE8 0x2 + +#endif /* _DT_BINDINGS_J721E_WIZ */