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Mon, 4 May 2020 12:45:39 +0000 (GMT) From: Sylwester Nawrocki To: u-boot@lists.denx.de, mbrugger@suse.com, marex@denx.de, bmeng.cn@gmail.com Cc: nsaenzjulienne@suse.de, sjg@chromium.org, jh80.chung@samsung.com, m.szyprowski@samsung.com, b.zolnierkie@samsung.com, Sylwester Nawrocki Subject: [PATCH v2 01/10] usb: xhci: Add missing cache flush in the scratchpad array initialization Date: Mon, 4 May 2020 14:45:14 +0200 Message-Id: <20200504124523.23484-2-s.nawrocki@samsung.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200504124523.23484-1-s.nawrocki@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprKKsWRmVeSWpSXmKPExsWy7djP87olfBviDOb9UbTYOGM9q8XUnniL G7/aWC3WHrnLbvGmrZHRYsHkJ6wW22YtZ7M4/Kad1eLblm2MFm/3drI7cHnMbrjI4jFv1gkW j52z7rJ7nL2zg9Gjb8sqRo/1W66yeGw+XR3AHsVlk5Kak1mWWqRvl8CVcXfVa8aCKZwVH5ce YGpgPMvexcjJISFgIrFq5Twgm4tDSGAFo8TG9mlsEM4XRokVa7YwQzifGSW2fTvJDNNy6vNF qMRyRokJDxvY4VqWfbjFCFLFJmAo0Xu0D8wWEQiQuPZzGiNIEbPASkaJD/e+gW0XFkiVeH3j HJDNwcEioCoxea0hSJhXwFpiw/P3UNvkJVZvOABmcwrYSLxp+sQCMkdCYDq7xPG2k4wQRS4S R99/YIKwhSVeHd8C9Z2MxOnJPVANzYwSPbtvs0M4Exgl7h9fANVtLXHn3C82kCuYBTQl1u/S hwg7SpzseA0WlhDgk7jxVhAkzAxkTto2nRkizCvR0SYEUa0i8XvVdKgTpCS6n/xngbA9JKas 3cQKCaB+Rol7768wTmCUn4WwbAEj4ypG8dTS4tz01GLjvNRyveLE3OLSvHS95PzcTYzAxHL6 3/GvOxj3/Uk6xCjAwajEwxvxeX2cEGtiWXFl7iFGCQ5mJRHeHS1AId6UxMqq1KL8+KLSnNTi Q4zSHCxK4rzGi17GCgmkJ5akZqemFqQWwWSZODilGhgncJpsWq/8Ttz7VU1+ZYE9c9er6QdS XvCyfw6qWfppY46wjH+kmNrq2+tXPY5SOZESlmcz6VGZTtUHP85cPaGDIsKti747L+f8LyV8 W60mRzaZsWx3Yn5USxWDu1LhI58ZBWs+7F4jKBJpe3Pd3ZIdf6JmL7glI3z2vfzTZb9KyprN 8ng2nFdiKc5INNRiLipOBABfGKXUKAMAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrCLMWRmVeSWpSXmKPExsVy+t/xe7olfBviDPqOc1psnLGe1WJqT7zF jV9trBZrj9xlt3jT1shosWDyE1aLbbOWs1kcftPOavFtyzZGi7d7O9kduDxmN1xk8Zg36wSL x85Zd9k9zt7ZwejRt2UVo8f6LVdZPDafrg5gj9KzKcovLUlVyMgvLrFVija0MNIztLTQMzKx 1DM0No+1MjJV0rezSUnNySxLLdK3S9DLuLvqNWPBFM6Kj0sPMDUwnmXvYuTkkBAwkTj1+SJz FyMXh5DAUkaJW8sOsXUxcgAlpCTmtyhB1AhL/LnWxQZR84lRYsurZ8wgCTYBQ4neo32MILaI QIjEi6NXmECKmAXWM0pcPD8frEhYIFmi49EjZpChLAKqEpPXGoKEeQWsJTY8f88MsUBeYvWG A2A2p4CNxJumTywgthBQzd4fx9gmMPItYGRYxSiSWlqcm55bbKRXnJhbXJqXrpecn7uJERji 24793LKDsetd8CFGAQ5GJR7eDV/XxwmxJpYVV+YeYpTgYFYS4d3RAhTiTUmsrEotyo8vKs1J LT7EaAp000RmKdHkfGD85ZXEG5oamltYGpobmxubWSiJ83YIHIwREkhPLEnNTk0tSC2C6WPi 4JRqYJQ6l5OeW6M546DL013rfO1bbxVvCeusOzvZueWA4J2269xbN56rSpPSSDipxLjzw9mV qz+aON1vOGwcI+tyOOZIi+EEzve6u69vj6kzr3r84EJX2TGViQf2Tn16/sOUbWkz/Ur0M5Uu izY1632c5pEg9Ux3S05WyP3snCkG1+zLf0znkjPT36DEUpyRaKjFXFScCACQRspohwIAAA== X-CMS-MailID: 20200504124540eucas1p13de235cf0014249e420eaa6502d57e93 X-Msg-Generator: CA X-RootMTR: 20200504124540eucas1p13de235cf0014249e420eaa6502d57e93 X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20200504124540eucas1p13de235cf0014249e420eaa6502d57e93 References: <20200504124523.23484-1-s.nawrocki@samsung.com> X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.30rc1 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.2 at phobos.denx.de X-Virus-Status: Clean In current code there is no cache flush after initializing the scratchpad buffer array with the scratchpad buffer pointers. This leads to a failure of the "slot enable" command on the rpi4 board (Broadcom STB PCIe controller + VL805 USB hub) - the very first TRB transfer on the command ring fails and there is a timeout while waiting for the command completion event. After adding the missing cache flush everything seems to be working as expected. Signed-off-by: Sylwester Nawrocki Reviewed-by: Bin Meng Reviewed-by: Nicolas Saenz Julienne --- Changes since v1: - none. --- drivers/usb/host/xhci-mem.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/usb/host/xhci-mem.c b/drivers/usb/host/xhci-mem.c index 93450ee..729bdc3 100644 --- a/drivers/usb/host/xhci-mem.c +++ b/drivers/usb/host/xhci-mem.c @@ -393,6 +393,9 @@ static int xhci_scratchpad_alloc(struct xhci_ctrl *ctrl) scratchpad->sp_array[i] = cpu_to_le64(ptr); } + xhci_flush_cache((uintptr_t)scratchpad->sp_array, + sizeof(u64) * num_sp); + return 0; fail_sp3: From patchwork Mon May 4 12:45:15 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sylwester Nawrocki X-Patchwork-Id: 1282595 X-Patchwork-Delegate: matthias.bgg@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; 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Mon, 4 May 2020 12:45:43 +0000 (GMT) Received: from eusmgms2.samsung.com (unknown [182.198.249.180]) by eusmtrp1.samsung.com (KnoxPortal) with ESMTP id 20200504124543eusmtrp159bbc0912f42a5de45c3430ab455f207~L0-Uyw61g1936819368eusmtrp13; Mon, 4 May 2020 12:45:43 +0000 (GMT) X-AuditID: cbfec7f4-0cbff7000001ed07-66-5eb00e784974 Received: from eusmtip2.samsung.com ( [203.254.199.222]) by eusmgms2.samsung.com (EUCPMTA) with SMTP id 81.E4.07950.77E00BE5; Mon, 4 May 2020 13:45:43 +0100 (BST) Received: from AMDC3061.digital.local (unknown [106.120.51.75]) by eusmtip2.samsung.com (KnoxPortal) with ESMTPA id 20200504124543eusmtip2215f8e4b4179359eca5b04c79a63d836~L0-UQaW1y3047630476eusmtip2r; Mon, 4 May 2020 12:45:43 +0000 (GMT) From: Sylwester Nawrocki To: u-boot@lists.denx.de, mbrugger@suse.com, marex@denx.de, bmeng.cn@gmail.com Cc: nsaenzjulienne@suse.de, sjg@chromium.org, jh80.chung@samsung.com, m.szyprowski@samsung.com, b.zolnierkie@samsung.com, Sylwester Nawrocki , Sergey Temerkhanov Subject: [PATCH v2 02/10] usb: xhci: Use only 32-bit accesses in xhci_writeq/xhci_readq Date: Mon, 4 May 2020 14:45:15 +0200 Message-Id: <20200504124523.23484-3-s.nawrocki@samsung.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200504124523.23484-1-s.nawrocki@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA0WSa0hTYRjHeXfO2TkzJ8ep+HgJYxSUoGZJHFIio2L0IfxoQdrUg4puyo6a ZpeVury1ZmbWarE0MSxx6hjeCtPKUrTCS+I1xcLLLFMLNNGcZ9a33/N//v/3eXh4KUyiJzyp eGUKq1LKE6VCB9zyduWDX7qTKWK/cYxgau/VEExJYSQzuKohmOrXoyRj1VxDjLF4imAs+koh 0269QTAV+pck89tsQcz8izzy6A7ZA/UnXPZI/w6XNepHSVn3SAOSac1VSFZj7sdl9V2ZYeRZ h5AYNjE+jVUFHDnvENdY/JhIXqLTf+aWC9VoQpyPRBTQQVAw3i/IRw6UhH6KoCJ7AfHFMgJ1 34S9s4SgfOG9YDvSW9dvd1UiMFWXEP8iw7o5oc0lpAPh5hstsrErHQYDK3e3Ehj9GUH993XC 1nChz4Dpo36TKQqn98BkQYBNFtPBoLFm26f5wDNTK2ZjER0C1uuLuO0doEtJ6P42jfGm49Db WYZ4doHZDjPJszd0FRfaA1kICpuHSb7QIRjvMNoTwTDSsyq0bYHR+6CmKYCXQyG7aG5LBtoJ BuedbTK2ibctpRgviyFXI+Hdu+FPVal9Z08omNrAeZbBQs6G/UC3EDRrjQId8tH/H2ZEqAq5 s6mcIpblDijZC/6cXMGlKmP9o5MUdWjzx3Stdyw3oKa1qDZEU0jqKA5fqomQEPI0LkPRhoDC pK7ihuxNSRwjz7jIqpIiVamJLNeGvChc6i4+WDZzTkLHylPYBJZNZlXbXQEl8lSjY/Ha6ZlO TeSYd1a4owHyQqUebhVVK4yIbDIEzbMlylpdZkDuVzfuF7pjJRN2hixcbZ2MDorwn30+Mcu2 04pLgpMP+wiPAcY3eDwlem+OT4vlcLAKvVpcK4t6Yl4vE3xR+526YihJLzrtet+zsGX5sq9h aJfzkEH+44TXoR4pzsXJA30xFSf/C/aOpRstAwAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrBLMWRmVeSWpSXmKPExsVy+t/xe7rlfBviDK7vV7TYOGM9q8XUnniL G7/aWC3WHrnLbvGmrZHRYsHkJ6wW22YtZ7M4/Kad1WLprH3sFt+2bGO0eLu3k92B22N2w0UW j3mzTrB47Jx1l93j7J0djB59W1YxeqzfcpXFY/Pp6gD2KD2bovzSklSFjPziElulaEMLIz1D Sws9IxNLPUNj81grI1MlfTublNSczLLUIn27BL2MnZMXshZ8Fqj42LGYrYHxIW8XIyeHhICJ xOVNVxlBbCGBpYwSy7endTFyAMWlJOa3KEGUCEv8udbF1sXIBVTyCajkw3xWkASbgKFE79E+ sF4RgRCJF0evMIEUMQvcZ5To6voDViQsEC4xcfVnRpChLAKqEo+69UHCvALWEm1vWpggFshL rN5wgBnE5hSwkXjT9IkF4h5rib0/jrFNYORbwMiwilEktbQ4Nz232EivODG3uDQvXS85P3cT IzDUtx37uWUHY9e74EOMAhyMSjy8G76ujxNiTSwrrsw9xCjBwawkwrujBSjEm5JYWZValB9f VJqTWnyI0RToponMUqLJ+cA4zCuJNzQ1NLewNDQ3Njc2s1AS5+0QOBgjJJCeWJKanZpakFoE 08fEwSnVwLg64R7DoYubNvw+nJjifjw74/5kz7VdzE/WlTvuPaoenHTnuGSqaOXzvxlOTybN 2H4vq03vYWjJyS1RWwJXqDrp5Gclc8bpzDEUaw0MVn7AnH8r6q7w54uGClf1+879d3dev/9g 717e9bpZ6SERVSnzjpcKJgrdnzO72Mb8gOXdjiCWCQIVvkosxRmJhlrMRcWJAKD0RsCLAgAA X-CMS-MailID: 20200504124543eucas1p12dd4bca4b6b65593027c63485c659191 X-Msg-Generator: CA X-RootMTR: 20200504124543eucas1p12dd4bca4b6b65593027c63485c659191 X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20200504124543eucas1p12dd4bca4b6b65593027c63485c659191 References: <20200504124523.23484-1-s.nawrocki@samsung.com> X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.30rc1 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.2 at phobos.denx.de X-Virus-Status: Clean There might be hardware configurations where 64-bit data accesses to XHCI registers are not supported properly. This patch removes the readq/writeq so always two 32-bit accesses are used to read/write 64-bit XHCI registers, similarly as it is done in Linux kernel. This patch fixes operation of the XHCI controller on RPI4 Broadcom BCM2711 SoC based board, where the VL805 USB XHCI controller is connected to the PCIe Root Complex, which is attached to the system through the SCB bridge. Even though the architecture is 64-bit the PCIe BAR is 32-bit and likely the 64-bit wide register accesses initiated by the CPU are not properly translated to a sequence of 32-bit PCIe accesses. xhci_readq(), for example, always returns same value in upper and lower 32-bits, e.g. 0xabcd1234abcd1234 instead of 0x00000000abcd1234. Cc: Sergey Temerkhanov Signed-off-by: Sylwester Nawrocki Reviewed-by: Bin Meng Reviewed-by: Nicolas Saenz Julienne --- Changes since v1: - none. Changes since RFC: - dropped Kconfig option, switched to not using readq/writeq unconditionally. --- include/usb/xhci.h | 8 -------- 1 file changed, 8 deletions(-) diff --git a/include/usb/xhci.h b/include/usb/xhci.h index 6017504..c16106a 100644 --- a/include/usb/xhci.h +++ b/include/usb/xhci.h @@ -1111,28 +1111,20 @@ static inline void xhci_writel(uint32_t volatile *regs, const unsigned int val) */ static inline u64 xhci_readq(__le64 volatile *regs) { -#if BITS_PER_LONG == 64 - return readq(regs); -#else __u32 *ptr = (__u32 *)regs; u64 val_lo = readl(ptr); u64 val_hi = readl(ptr + 1); return val_lo + (val_hi << 32); -#endif } static inline void xhci_writeq(__le64 volatile *regs, const u64 val) { -#if BITS_PER_LONG == 64 - writeq(val, regs); -#else __u32 *ptr = (__u32 *)regs; u32 val_lo = lower_32_bits(val); /* FIXME */ u32 val_hi = upper_32_bits(val); writel(val_lo, ptr); writel(val_hi, ptr + 1); -#endif } int xhci_hcd_init(int index, struct xhci_hccr **ret_hccr, From patchwork Mon May 4 12:45:16 2020 Content-Type: text/plain; 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Mon, 4 May 2020 12:45:43 +0000 (GMT) From: Sylwester Nawrocki To: u-boot@lists.denx.de, mbrugger@suse.com, marex@denx.de, bmeng.cn@gmail.com Cc: nsaenzjulienne@suse.de, sjg@chromium.org, jh80.chung@samsung.com, m.szyprowski@samsung.com, b.zolnierkie@samsung.com, Sylwester Nawrocki Subject: [PATCH v2 03/10] pci: Move some PCIe register offset definitions to a common header Date: Mon, 4 May 2020 14:45:16 +0200 Message-Id: <20200504124523.23484-4-s.nawrocki@samsung.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200504124523.23484-1-s.nawrocki@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA0WSXUhTYRzGez1nO2ej2Wku/GeROI1KaGZFHFCiwot550WBJH5MPai0zbGj 84vANKyW+TVtalImhkutuVybWWGuTGlqZRaGWheakGxQaQM/0jaP1t3v/zz/5314X14SExt4 QWSWOofRqhVKKV+I214vjR7O9+9KOjJwQ0Jb6s08uq48mZ5YLuPRD15NE7Sr7BKimw2zPNrW 2ManX7qu8GiP1YZo9/NrxCmh/Fbxe1x+u3EIlz9pnCbkI1M9SF5hbUdys/UjLu92FsUR54XR 6YwyS8doI06mCDMNTSEa4+78mbvrqBjNSfRIQAJ1HKanWnk+FlMmBD/6zuiR0MuLCPqr+/jc sICg6bcFbSUs9j84Z7QhaLF70L/IuGNu4yw+FQk3Bio2EhIqDj4t3dxYwqj73o4vHsJnBFBJ MDw54edjnNoP6xNuTI9IUkRFQd/ndK4tGDq6XmA+FlDR4Cr5tdEMlIGAqp8fCG4pBtytTozj AJgftG7qe8FpKN8MlCIofzpJcEMVgq+DzZsXioKp0WW+rxmjDoG5N4KTT8PanVLCJwPlDxPu nT4Z82KNzYhxsgiulom57TBYaTf6cRwE12fXcY7l0F3/kMc9UCWCTv0MqkLBjf/LmhFqR4FM LqvKYNijaiZPxipUbK46Q5aWrXqEvF/FuTa42IN6V1MdiCKRdLsofsGcJOYpdGyByoGAxKQS Uc9lryRKVxQUMtrsZG2ukmEdaA+JSwNFx1q+J4qpDEUOc4FhNIx2y/UjBUHFKKHorTKv5OKY s7ywuP/xwmznaoJt27dRmgitTQRT+ErICUnSsiYhNN7KDxVEDmfJPA2uXfpxpfFZPr/u3YKJ VIWtmC12ie2eqbA7NuSAYyY1boxNTDHFqtMWGY9gR1xlx9nCfVntDUNT9phaSqMbqA5/c/Cc riZ4fKRBNi/F2UxFZDimZRV/AdJpF3MmAwAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrELMWRmVeSWpSXmKPExsVy+t/xe7oVfBviDN4fYrTYOGM9q8XUnniL G7/aWC3WHrnLbvGmrZHRYsHkJ6wW22YtZ7M4/Kad1eLblm2MFm/3drI7cHnMbrjI4jFv1gkW j52z7rJ7nL2zg9Gjb8sqRo/1W66yeGw+XR3AHqVnU5RfWpKqkJFfXGKrFG1oYaRnaGmhZ2Ri qWdobB5rZWSqpG9nk5Kak1mWWqRvl6CXMXmOYsF0yYrHC/8zNjA+E+li5OSQEDCR2Lj9L0sX IxeHkMBSRonl078DORxACSmJ+S1KEDXCEn+udbFB1HxilHg78wczSIJNwFCi92gfI4gtIhAi 8eLoFSaQImaB9YwSF8/PZwYZJCwQI3GzxwGkhkVAVeL/jbdgYV4Ba4n9N1Mg5stLrN5wAGwk p4CNxJumTywgthBQyd4fx9gmMPItYGRYxSiSWlqcm55bbKRXnJhbXJqXrpecn7uJERje2479 3LKDsetd8CFGAQ5GJR7eDV/XxwmxJpYVV+YeYpTgYFYS4d3RAhTiTUmsrEotyo8vKs1JLT7E aAp000RmKdHkfGDs5ZXEG5oamltYGpobmxubWSiJ83YIHIwREkhPLEnNTk0tSC2C6WPi4JRq YNSfyxdjq7P0oZTNxsxNRfNyV71/k34ydv2FB280Z6avTjbxXnte56TF+6OzdVOPfY5iit0S dk120Zp8+8biTeuM57H9O5PKdma7in/kjftnQiKOPrx/U/lY43VbtbjU9q6O2On6XyUZTNLe aCkePPTj9EW3x1O9gu6IqzaKHxF/sOlE82cPCQMlluKMREMt5qLiRACvvGZThQIAAA== X-CMS-MailID: 20200504124544eucas1p1dff0bc65bd0cdab0de2662c2671d49b3 X-Msg-Generator: CA X-RootMTR: 20200504124544eucas1p1dff0bc65bd0cdab0de2662c2671d49b3 X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20200504124544eucas1p1dff0bc65bd0cdab0de2662c2671d49b3 References: <20200504124523.23484-1-s.nawrocki@samsung.com> X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.30rc1 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.2 at phobos.denx.de X-Virus-Status: Clean Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki Reviewed-by: Bin Meng Reviewed-by: Nicolas Saenz Julienne --- Changes since v1: - none. Changes since RFC: - whitespace clean up. --- drivers/pci/pci-rcar-gen3.c | 8 -------- drivers/pci/pcie_intel_fpga.c | 3 --- include/pci.h | 13 +++++++++++-- 3 files changed, 11 insertions(+), 13 deletions(-) diff --git a/drivers/pci/pci-rcar-gen3.c b/drivers/pci/pci-rcar-gen3.c index 30eff67..393f1c9 100644 --- a/drivers/pci/pci-rcar-gen3.c +++ b/drivers/pci/pci-rcar-gen3.c @@ -117,14 +117,6 @@ #define RCAR_PCI_MAX_RESOURCES 4 #define MAX_NR_INBOUND_MAPS 6 -#define PCI_EXP_FLAGS 2 /* Capabilities register */ -#define PCI_EXP_FLAGS_TYPE 0x00f0 /* Device/Port type */ -#define PCI_EXP_TYPE_ROOT_PORT 0x4 /* Root Port */ -#define PCI_EXP_LNKCAP 12 /* Link Capabilities */ -#define PCI_EXP_LNKCAP_DLLLARC 0x00100000 /* Data Link Layer Link Active Reporting Capable */ -#define PCI_EXP_SLTCAP 20 /* Slot Capabilities */ -#define PCI_EXP_SLTCAP_PSN 0xfff80000 /* Physical Slot Number */ - enum { RCAR_PCI_ACCESS_READ, RCAR_PCI_ACCESS_WRITE, diff --git a/drivers/pci/pcie_intel_fpga.c b/drivers/pci/pcie_intel_fpga.c index 6a9f29c..69363a0 100644 --- a/drivers/pci/pcie_intel_fpga.c +++ b/drivers/pci/pcie_intel_fpga.c @@ -65,9 +65,6 @@ #define IS_ROOT_PORT(pcie, bdf) \ ((PCI_BUS(bdf) == pcie->first_busno) ? true : false) -#define PCI_EXP_LNKSTA 18 /* Link Status */ -#define PCI_EXP_LNKSTA_DLLLA 0x2000 /* Data Link Layer Link Active */ - /** * struct intel_fpga_pcie - Intel FPGA PCIe controller state * @bus: Pointer to the PCI bus diff --git a/include/pci.h b/include/pci.h index aff56b2..dfdbb32 100644 --- a/include/pci.h +++ b/include/pci.h @@ -471,10 +471,19 @@ #define PCI_EA_FIELD_MASK 0xfffffffc /* For Base & Max Offset */ /* PCI Express capabilities */ +#define PCI_EXP_FLAGS 2 /* Capabilities register */ +#define PCI_EXP_FLAGS_TYPE 0x00f0 /* Device/Port type */ +#define PCI_EXP_TYPE_ROOT_PORT 0x4 /* Root Port */ #define PCI_EXP_DEVCAP 4 /* Device capabilities */ -#define PCI_EXP_DEVCAP_FLR 0x10000000 /* Function Level Reset */ +#define PCI_EXP_DEVCAP_FLR 0x10000000 /* Function Level Reset */ #define PCI_EXP_DEVCTL 8 /* Device Control */ -#define PCI_EXP_DEVCTL_BCR_FLR 0x8000 /* Bridge Configuration Retry / FLR */ +#define PCI_EXP_DEVCTL_BCR_FLR 0x8000 /* Bridge Configuration Retry / FLR */ +#define PCI_EXP_LNKCAP 12 /* Link Capabilities */ +#define PCI_EXP_LNKCAP_DLLLARC 0x00100000 /* Data Link Layer Link Active Reporting Capable */ +#define PCI_EXP_LNKSTA 18 /* Link Status */ +#define PCI_EXP_LNKSTA_DLLLA 0x2000 /* Data Link Layer Link Active */ +#define PCI_EXP_SLTCAP 20 /* Slot Capabilities */ +#define PCI_EXP_SLTCAP_PSN 0xfff80000 /* Physical Slot Number */ /* Include the ID list */ From patchwork Mon May 4 12:45:17 2020 Content-Type: text/plain; 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Mon, 4 May 2020 12:45:44 +0000 (GMT) From: Sylwester Nawrocki To: u-boot@lists.denx.de, mbrugger@suse.com, marex@denx.de, bmeng.cn@gmail.com Cc: nsaenzjulienne@suse.de, sjg@chromium.org, jh80.chung@samsung.com, m.szyprowski@samsung.com, b.zolnierkie@samsung.com, Sylwester Nawrocki Subject: [PATCH v2 04/10] rpi4: shorten a mapping for the DRAM Date: Mon, 4 May 2020 14:45:17 +0200 Message-Id: <20200504124523.23484-5-s.nawrocki@samsung.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200504124523.23484-1-s.nawrocki@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA0WSa0hTYRjHeXfOzjkOJ8cp+TKTaOSHZGli0AnN1PpwviVdIITUpQcV3bQd r101xXTeZ2msi1Msa2rOS8tLhZg3sikKpSyXQYaVEzXTmIq24+ny7fc8z///XF5eApFUCKVE giqVUasUSTJMhJoG7WMHMl2MkQdnNo5QrXdahNTt4ihqaj1fSDX3W3HKlp8DKH3lrJAy6Row 6rXtppBa6zABauFlIR4iou9mj6P0A90wSnfprDhtnu4EdGmHAdAtHe9Qun3kcjgeIQqKZZIS 0hm1X3C0KH5tU4+mfMIy7dslWDYwCzXAiYDkIfiruwHTABEhIR8DuJwzhvPBTwDzbG8EnEpC rgBYsHpdA4gdh2Urgtc0ADjQ/RX7Zyg2NqOcASP9YclAKeDYnQyH7+1VgBMh5BMAlz6u4VzB jQyGhQ/Hdwwo6Q3HepoE3AQxGQjXnqfw6+2BjcZehGMnMgjabvxAuT6QrMThfGcxwotOwH5z M8azG/w+1IHzvBtud9UIeEOuY7ueDzgflAM4M6QHvCoQTo+uY9xkhNwPW7r9NAB3pEPhkoI/ 2AVOLbhyWsSBWlM1wqfFsCBfwrfYBzcM1QKepbBodhvlmYYzrXV/3rMMwIm2RWE52KP7P0oP gAF4MGmsMo5hA1RMhi+rULJpqjjfmGRlG3B8lJGtodVO8GrzQh8gCSBzFp9baYmUCBXpbJay D0ACkbmLO/McKXGsIusSo06OUqclMWwf8CRQmYc4oO7beQkZp0hlEhkmhVH/rQoIJ2k20H2u 1Ur31prnnTJ2eRrYGjjaOJc6mHPf+/RTe1XYkNbw9mTDsMHZeio0OoxunNy2ROfq7k1YfF6U a+Tm+qNXz/Q+Mz7yQrzOHq61pVpiFivKrsn9Qqa+BNe12+VX1HN+lEgea7SMT1rXjyVn4E3S +mFtUb1rYeJF/a2248veMpSNV/j7IGpW8RsvPoutJAMAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrMLMWRmVeSWpSXmKPExsVy+t/xe7oVfBviDL4tULDYOGM9q8XUnniL G7/aWC3WHrnLbvGmrZHRYsHkJ6wW22YtZ7M4/Kad1eLblm2MFm/3drI7cHnMbrjI4jFv1gkW j52z7rJ7nL2zg9Gjb8sqRo/1W66yeGw+XR3AHqVnU5RfWpKqkJFfXGKrFG1oYaRnaGmhZ2Ri qWdobB5rZWSqpG9nk5Kak1mWWqRvl6CX8e3PApaCB2wVP//3sjUwnmXtYuTgkBAwkbj1L6qL kYtDSGApo8TKrvUsEHEpifktSl2MnECmsMSfa11sEDWfGCU2ve1jAkmwCRhK9B7tYwSxRQRC JF4cvcIEUsQssJ5R4uL5+cwgCWEBO4nOpRdZQGwWAVWJ87vXMIEs4BWwlvi2vQBigbzE6g0H wMo5BWwk3jR9AisXAirZ++MY2wRGvgWMDKsYRVJLi3PTc4sN9YoTc4tL89L1kvNzNzECA3zb sZ+bdzBe2hh8iFGAg1GJhzfi8/o4IdbEsuLK3EOMEhzMSiK8O1qAQrwpiZVVqUX58UWlOanF hxhNgW6ayCwlmpwPjL68knhDU0NzC0tDc2NzYzMLJXHeDoGDMUIC6YklqdmpqQWpRTB9TByc Ug2MXv3znffuiPqnbPP55d1QtQKzzf+NtFouXDWfc+2+Vkbr/hsxbBcVjPqsLS/Yhogdj7u/ xOamcZi8gUwva8h7nZaKtfNlYnRrA9n9lyfGWUrqP2IM+u/TqM9jekdAxUuoX0+3137ltW+a x45yzZzr4GlZeShc6GjOnW3Fxv9UkwOeS5ZVGyqxFGckGmoxFxUnAgDK72E9hgIAAA== X-CMS-MailID: 20200504124544eucas1p2e7763e292144e3f8a7828f014209c770 X-Msg-Generator: CA X-RootMTR: 20200504124544eucas1p2e7763e292144e3f8a7828f014209c770 X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20200504124544eucas1p2e7763e292144e3f8a7828f014209c770 References: <20200504124523.23484-1-s.nawrocki@samsung.com> X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.30rc1 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.2 at phobos.denx.de X-Virus-Status: Clean From: Marek Szyprowski Remove the overlap between DRAM and device's IO area. Signed-off-by: Marek Szyprowski Signed-off-by: Sylwester Nawrocki Reviewed-by: Nicolas Saenz Julienne --- Changes since v1: - none. --- arch/arm/mach-bcm283x/init.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-bcm283x/init.c b/arch/arm/mach-bcm283x/init.c index 9966d6c..4295356 100644 --- a/arch/arm/mach-bcm283x/init.c +++ b/arch/arm/mach-bcm283x/init.c @@ -38,7 +38,7 @@ static struct mm_region bcm2711_mem_map[] = { { .virt = 0x00000000UL, .phys = 0x00000000UL, - .size = 0xfe000000UL, + .size = 0xfc000000UL, .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_INNER_SHARE }, { From patchwork Mon May 4 12:45:18 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sylwester Nawrocki X-Patchwork-Id: 1282596 X-Patchwork-Delegate: matthias.bgg@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; 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Mon, 4 May 2020 12:45:44 +0000 (GMT) From: Sylwester Nawrocki To: u-boot@lists.denx.de, mbrugger@suse.com, marex@denx.de, bmeng.cn@gmail.com Cc: nsaenzjulienne@suse.de, sjg@chromium.org, jh80.chung@samsung.com, m.szyprowski@samsung.com, b.zolnierkie@samsung.com, Sylwester Nawrocki Subject: [PATCH v2 05/10] rpi4: add a mapping for the PCIe XHCI controller MMIO registers (ARM 64bit) Date: Mon, 4 May 2020 14:45:18 +0200 Message-Id: <20200504124523.23484-6-s.nawrocki@samsung.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200504124523.23484-1-s.nawrocki@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprMKsWRmVeSWpSXmKPExsWy7djPc7qVfBviDOYsVbTYOGM9q8XUnniL G7/aWC3WHrnLbvGmrZHRYsHkJ6wW22YtZ7M4/Kad1eLblm2MFm/3drI7cHnMbrjI4jFv1gkW j52z7rJ7nL2zg9Gjb8sqRo/1W66yeGw+XR3AHsVlk5Kak1mWWqRvl8CVsfZqSMETgYq7L9+y NzDe5+1i5OSQEDCR2LjsAWMXIxeHkMAKRomZLzvZIZwvjBKnDhxlg3A+M0q8WT6NBablc89m ZhBbSGA5o8SOZmm4jpnXT7GCJNgEDCV6j/YxgtgiAgES135OA9vBLLCSUeLDvW/sIAlhgXSJ NXfnMYHYLAKqEr92fACzeQWsJbZNXcoGsU1eYvWGA2DbOAVsJN40fWIBGSQhMJld4sb8Q8wQ RS4SW1s3Q9nCEq+Ob2GHsGUk/u+czwTR0Mwo0bP7NjuEM4FR4v7xBYwQVdYSd879AlrHAXSf psT6XfoQYUeJPztWMYOEJQT4JG68FQQJMwOZk7ZNhwrzSnS0CUFUq0j8XjWdCcKWkuh+8h8a Wh4SN55cZYKEVj+jxO73cRMY5Wch7FrAyLiKUTy1tDg3PbXYOC+1XK84Mbe4NC9dLzk/dxMj MKmc/nf86w7GfX+SDjEKcDAq8fBGfF4fJ8SaWFZcmXuIUYKDWUmEd0cLUIg3JbGyKrUoP76o NCe1+BCjNAeLkjiv8aKXsUIC6YklqdmpqQWpRTBZJg5OqQbG/T+9O/cn/T/3c+Pq2+2Lbxte /V0gI97zyeNhxT27dbrqfTE3dXSWHDq/U+FG6VWnBJmkrdt/i/Oev2lYrCz4I85K5O8efvN5 vYK34zO47jw6mTlR8tDZh2be25mkf7iIJ+kuWWDMtJadb+NmUVHVN/fKVQIeHPoQu/Pl5kpN nyfSl3qMfybaK7EUZyQaajEXFScCACnL9wgmAwAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrMLMWRmVeSWpSXmKPExsVy+t/xe7qVfBviDFY7W2ycsZ7VYmpPvMWN X22sFmuP3GW3eNPWyGixYPITVotts5azWRx+085q8W3LNkaLt3s72R24PGY3XGTxmDfrBIvH zll32T3O3tnB6NG3ZRWjx/otV1k8Np+uDmCP0rMpyi8tSVXIyC8usVWKNrQw0jO0tNAzMrHU MzQ2j7UyMlXSt7NJSc3JLEst0rdL0MtYezWk4IlAxd2Xb9kbGO/zdjFyckgImEh87tnM3MXI xSEksJRRYuqym4xdjBxACSmJ+S1KEDXCEn+udbFB1HxilPixfiMjSIJNwFCi92gfmC0iECLx 4ugVJpAiZoH1jBIXz89nBkkIC6RKTL91ngnEZhFQlfi14wOYzStgLbFt6lI2iA3yEqs3HACr 5xSwkXjT9IkFxBYCqtn74xjbBEa+BYwMqxhFUkuLc9Nziw31ihNzi0vz0vWS83M3MQIDfNux n5t3MF7aGHyIUYCDUYmHN+Lz+jgh1sSy4srcQ4wSHMxKIrw7WoBCvCmJlVWpRfnxRaU5qcWH GE2BjprILCWanA+MvrySeENTQ3MLS0NzY3NjMwslcd4OgYMxQgLpiSWp2ampBalFMH1MHJxS DYyK3Jm7lW1W/z48k3M6a0OC4ITLmlk3izl546/7TDO/zSPX6LIrVG2ibiOn1a2bX54UTgra 5HHScX7v1pDojVMWvvwSe0n18N192p7vz/TMqGv4vHCPl3/bh0a/YP6Iiwcuf5yVYL/886zt C9bmd639zvUsUZM1odzAJni5/K6tylEKzx6GHHBUYinOSDTUYi4qTgQAz9tcgoYCAAA= X-CMS-MailID: 20200504124545eucas1p1532613e2c1558cb043f3b32946c748ea X-Msg-Generator: CA X-RootMTR: 20200504124545eucas1p1532613e2c1558cb043f3b32946c748ea X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20200504124545eucas1p1532613e2c1558cb043f3b32946c748ea References: <20200504124523.23484-1-s.nawrocki@samsung.com> X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.30rc1 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.2 at phobos.denx.de X-Virus-Status: Clean From: Marek Szyprowski Create a non-cacheable mapping for the 0x600000000 physical memory region, where MMIO registers for the PCIe XHCI controller are instantiated by the PCIe bridge. Signed-off-by: Marek Szyprowski Signed-off-by: Sylwester Nawrocki Reviewed-by: Nicolas Saenz Julienne --- Changes since v1: - none. --- arch/arm/mach-bcm283x/init.c | 18 +++++++++++++++--- 1 file changed, 15 insertions(+), 3 deletions(-) diff --git a/arch/arm/mach-bcm283x/init.c b/arch/arm/mach-bcm283x/init.c index 4295356..6a748da 100644 --- a/arch/arm/mach-bcm283x/init.c +++ b/arch/arm/mach-bcm283x/init.c @@ -11,10 +11,15 @@ #include #include +#define BCM2711_RPI4_PCIE_XHCI_MMIO_PHYS 0x600000000UL +#define BCM2711_RPI4_PCIE_XHCI_MMIO_SIZE 0x800000UL + #ifdef CONFIG_ARM64 #include -static struct mm_region bcm283x_mem_map[] = { +#define MAX_MAP_MAX_ENTRIES (4) + +static struct mm_region bcm283x_mem_map[MAX_MAP_MAX_ENTRIES] = { { .virt = 0x00000000UL, .phys = 0x00000000UL, @@ -34,7 +39,7 @@ static struct mm_region bcm283x_mem_map[] = { } }; -static struct mm_region bcm2711_mem_map[] = { +static struct mm_region bcm2711_mem_map[MAX_MAP_MAX_ENTRIES] = { { .virt = 0x00000000UL, .phys = 0x00000000UL, @@ -49,6 +54,13 @@ static struct mm_region bcm2711_mem_map[] = { PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, { + .virt = BCM2711_RPI4_PCIE_XHCI_MMIO_PHYS, + .phys = BCM2711_RPI4_PCIE_XHCI_MMIO_PHYS, + .size = BCM2711_RPI4_PCIE_XHCI_MMIO_SIZE, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { /* List terminator */ 0, } @@ -71,7 +83,7 @@ static void _rpi_update_mem_map(struct mm_region *pd) { int i; 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Mon, 4 May 2020 12:45:45 +0000 (GMT) From: Sylwester Nawrocki To: u-boot@lists.denx.de, mbrugger@suse.com, marex@denx.de, bmeng.cn@gmail.com Cc: nsaenzjulienne@suse.de, sjg@chromium.org, jh80.chung@samsung.com, m.szyprowski@samsung.com, b.zolnierkie@samsung.com, Sylwester Nawrocki Subject: [PATCH v2 06/10] rpi4: add a mapping for the PCIe XHCI controller MMIO registers (ARM 32bit) Date: Mon, 4 May 2020 14:45:19 +0200 Message-Id: <20200504124523.23484-7-s.nawrocki@samsung.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200504124523.23484-1-s.nawrocki@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprEKsWRmVeSWpSXmKPExsWy7djP87qVfBviDA4+sLbYOGM9q8XUnniL G7/aWC3WHrnLbvGmrZHRYsHkJ6wW22YtZ7M4/Kad1eLblm2MFm/3drI7cHnMbrjI4jFv1gkW j52z7rJ7nL2zg9Gjb8sqRo/1W66yeGw+XR3AHsVlk5Kak1mWWqRvl8CVceDtDJaCSVIVZ7/5 NDBeE+1i5OSQEDCReNv0jLGLkYtDSGAFo8ShOZvZIJwvjBKtV3+wglQJCXxmlLjxJh2mY9Xp 01BFyxklll2bzgzX8X7mN0aQKjYBQ4neo31gtohAgMS1n9PAdjALrGSU+HDvGztIQlggXWLJ 9CVAKzg4WARUJfav0QQJ8wpYS3x93ssEsU1eYvWGA8wgNqeAjcSbpk8sIHMkBPrZJY53vYAq cpH4/OY4K4QtLPHq+BZ2CFtG4v/O+UwQDc2MEj27b7NDOBMYJe4fX8AIUWUtcefcLzaQK5gF NCXW79KHCDtKbFl9lB0kLCHAJ3HjrSBImBnInLQN5GOQMK9ER5sQRLWKxO9V06HOkZLofvKf BaLEQ2LucQdI+PQzSmxYO4tlAqP8LIRdCxgZVzGKp5YW56anFhvlpZbrFSfmFpfmpesl5+du YgSmlNP/jn/ZwbjrT9IhRgEORiUe3ojP6+OEWBPLiitzDzFKcDArifDuaAEK8aYkVlalFuXH F5XmpBYfYpTmYFES5zVe9DJWSCA9sSQ1OzW1ILUIJsvEwSnVwFj/NuFaeIfV5i8V73VT9sj/ OZXzkSnH5ISk/HKzG5lzNZ0TCzl/Xart6hFYEnZp7eZ10Y2xuj9WKosfnBrb/Wdb9bzZffl+ qS7ie9PSuj4zuwgUL+i/yi5vv3mn9PQf7KFxs3kWKj56uqRDUK+p4rzUx+hLHJtMGDR3FR8/ lXt2Y1ZlZoLoISWW4oxEQy3mouJEAEY0vEwlAwAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrILMWRmVeSWpSXmKPExsVy+t/xe7qVfBviDJZ1yltsnLGe1WJqT7zF jV9trBZrj9xlt3jT1shosWDyE1aLbbOWs1kcftPOavFtyzZGi7d7O9kduDxmN1xk8Zg36wSL x85Zd9k9zt7ZwejRt2UVo8f6LVdZPDafrg5gj9KzKcovLUlVyMgvLrFVija0MNIztLTQMzKx 1DM0No+1MjJV0rezSUnNySxLLdK3S9DLOPB2BkvBJKmKs998GhiviXYxcnJICJhIrDp9mg3E FhJYyigxodevi5EDKC4lMb9FCaJEWOLPtS6okk+MEo0T+UFsNgFDid6jfYwgtohAiMSLo1eY uhi5OJgF1jNKXDw/nxkkISyQKrHp7B5GkJksAqoS+9dogoR5Bawlvj7vZYKYLy+xesMBsHJO ARuJN02fWCB2WUvs/XGMbQIj3wJGhlWMIqmlxbnpucWGesWJucWleel6yfm5mxiBwb3t2M/N OxgvbQw+xCjAwajEwxvxeX2cEGtiWXFl7iFGCQ5mJRHeHS1AId6UxMqq1KL8+KLSnNTiQ4ym QDdNZJYSTc4HRl5eSbyhqaG5haWhubG5sZmFkjhvh8DBGCGB9MSS1OzU1ILUIpg+Jg5OqQbG CV2ir2acnsu93fvfSf3H7ucv2318Zvaz7nCmfHJzerlXVGtZi+PmjcF2n8U2iHw68uzEbDeH 3ZzHVH+4vdqw/f2H3mNBOy+4vpb71TK7eO3SC6XWsvXX/3EwrLscvvtx8alZWZOPBHt+c5np MtnL8LxuydbWHn5vISl3jY1Hpj55bO1w6jPHISWW4oxEQy3mouJEAB1F9U+EAgAA X-CMS-MailID: 20200504124545eucas1p2d8fcb6cfbd2204d171dad747cb6f9cd1 X-Msg-Generator: CA X-RootMTR: 20200504124545eucas1p2d8fcb6cfbd2204d171dad747cb6f9cd1 X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20200504124545eucas1p2d8fcb6cfbd2204d171dad747cb6f9cd1 References: <20200504124523.23484-1-s.nawrocki@samsung.com> X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.30rc1 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.2 at phobos.denx.de X-Virus-Status: Clean From: Marek Szyprowski Create a non-cacheable mapping for the 0x600000000 physical memory region, where MMIO registers for the PCIe XHCI controller are instantiated by the PCIe bridge. Due to 32bit limit in the CPU virtual address space in ARM 32bit mode, this region is mapped at 0xff800000 CPU virtual address. Signed-off-by: Marek Szyprowski Signed-off-by: Sylwester Nawrocki --- Changes since v1: - none. --- arch/arm/mach-bcm283x/Kconfig | 1 + arch/arm/mach-bcm283x/include/mach/base.h | 7 +++++ arch/arm/mach-bcm283x/init.c | 52 +++++++++++++++++++++++++++++++ 3 files changed, 60 insertions(+) diff --git a/arch/arm/mach-bcm283x/Kconfig b/arch/arm/mach-bcm283x/Kconfig index 00419bf..bcb7f1d 100644 --- a/arch/arm/mach-bcm283x/Kconfig +++ b/arch/arm/mach-bcm283x/Kconfig @@ -36,6 +36,7 @@ config BCM2711_32B select BCM2711 select ARMV7_LPAE select CPU_V7A + select PHYS_64BIT config BCM2711_64B bool "Broadcom BCM2711 SoC 64-bit support" diff --git a/arch/arm/mach-bcm283x/include/mach/base.h b/arch/arm/mach-bcm283x/include/mach/base.h index c4ae398..1d10dc9 100644 --- a/arch/arm/mach-bcm283x/include/mach/base.h +++ b/arch/arm/mach-bcm283x/include/mach/base.h @@ -6,6 +6,13 @@ #ifndef _BCM283x_BASE_H_ #define _BCM283x_BASE_H_ +#include + extern unsigned long rpi_bcm283x_base; +#ifdef CONFIG_ARMV7_LPAE +extern void *rpi4_phys_to_virt(phys_addr_t paddr); +#define phys_to_virt(x) rpi4_phys_to_virt(x) +#endif + #endif diff --git a/arch/arm/mach-bcm283x/init.c b/arch/arm/mach-bcm283x/init.c index 6a748da..5d0d160 100644 --- a/arch/arm/mach-bcm283x/init.c +++ b/arch/arm/mach-bcm283x/init.c @@ -145,6 +145,58 @@ int mach_cpu_init(void) } #ifdef CONFIG_ARMV7_LPAE + +#define BCM2711_RPI4_PCIE_XHCI_MMIO_VIRT 0xff800000UL + +void *rpi4_phys_to_virt(phys_addr_t paddr) +{ + if (paddr >= BCM2711_RPI4_PCIE_XHCI_MMIO_PHYS) + paddr = paddr - BCM2711_RPI4_PCIE_XHCI_MMIO_PHYS + + BCM2711_RPI4_PCIE_XHCI_MMIO_VIRT; + return (void *)(unsigned long)paddr; +} + +static void set_section_phys(unsigned int section, phys_addr_t phys, + enum dcache_option option) +{ + u64 *page_table = (u64 *)gd->arch.tlb_addr; + /* Need to set the access flag to not fault */ + u64 value = TTB_SECT_AP | TTB_SECT_AF; + + /* Add the page offset */ + value |= (phys); + + /* Add caching bits */ + value |= option; + + /* Set PTE */ + page_table[section] = value; +} + +static void rpi4_create_pcie_xhci_mapping(void) +{ + unsigned sect = BCM2711_RPI4_PCIE_XHCI_MMIO_VIRT >> MMU_SECTION_SHIFT; + phys_addr_t phys_addr = BCM2711_RPI4_PCIE_XHCI_MMIO_PHYS; + unsigned int size = BCM2711_RPI4_PCIE_XHCI_MMIO_SIZE; + + while (size) { + set_section_phys(sect, phys_addr, DCACHE_OFF); + sect++; + phys_addr += MMU_SECTION_SIZE; + size -= MMU_SECTION_SIZE; + } +} + +void arm_init_domains(void) +{ + /* + * Hijack this function to prepare a mappings for the PCIe MMIO + * region for the XHCI controller on RPi4 board. + * This code is called before enabling the MMU in ARM 32bit mode. + */ + rpi4_create_pcie_xhci_mapping(); +} + void enable_caches(void) { dcache_enable(); From patchwork Mon May 4 12:45:20 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sylwester Nawrocki X-Patchwork-Id: 1282601 X-Patchwork-Delegate: matthias.bgg@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; 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Mon, 4 May 2020 12:45:46 +0000 (GMT) Received: from eusmgms1.samsung.com (unknown [182.198.249.179]) by eusmtrp2.samsung.com (KnoxPortal) with ESMTP id 20200504124546eusmtrp2274ce82573229082bc19ec2a40fbc6df~L0-XAi6R82443524435eusmtrp2d; Mon, 4 May 2020 12:45:46 +0000 (GMT) X-AuditID: cbfec7f4-0cbff7000001ed07-72-5eb00e7a90cb Received: from eusmtip2.samsung.com ( [203.254.199.222]) by eusmgms1.samsung.com (EUCPMTA) with SMTP id C4.38.08375.97E00BE5; Mon, 4 May 2020 13:45:45 +0100 (BST) Received: from AMDC3061.digital.local (unknown [106.120.51.75]) by eusmtip2.samsung.com (KnoxPortal) with ESMTPA id 20200504124545eusmtip2f3bd7848892509bf1c8f484cc2089ca9~L0-WhEFMq3050430504eusmtip2B; Mon, 4 May 2020 12:45:45 +0000 (GMT) From: Sylwester Nawrocki To: u-boot@lists.denx.de, mbrugger@suse.com, marex@denx.de, bmeng.cn@gmail.com Cc: nsaenzjulienne@suse.de, sjg@chromium.org, jh80.chung@samsung.com, m.szyprowski@samsung.com, b.zolnierkie@samsung.com, Sylwester Nawrocki Subject: [PATCH v2 07/10] linux/bitfield.h: Add primitives for manipulating bitfields both in host- and fixed-endian Date: Mon, 4 May 2020 14:45:20 +0200 Message-Id: <20200504124523.23484-8-s.nawrocki@samsung.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200504124523.23484-1-s.nawrocki@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprKKsWRmVeSWpSXmKPExsWy7djPc7pVfBviDO6+5bPYOGM9q8XUnniL G7/aWC3WHrnLbvGmrZHRYsHkJ6wW22YtZ7M4/Kad1eLblm2MFm/3drI7cHnMbrjI4jFv1gkW j52z7rJ7nL2zg9Gjb8sqRo/1W66yeGw+XR3AHsVlk5Kak1mWWqRvl8CV8f76X+aCuSIVm193 sjUwHhfoYuTkkBAwkXh5ZwVbFyMXh5DACkaJz/POskI4XxglZjfMhHI+M0rMetnBBNOyd8sZ qJbljBKvO6awwbU83d7MDlLFJmAo0Xu0jxHEFhEIkLj2cxojSBGzwEpGiQ/3voEVCQuUScxr /gtWxCKgKrHuYwtYnFfAWqJn9g5miHXyEqs3HACzOQVsJN40fWKBiE9ml3jWFQphu0h8+f6G DcIWlnh1fAs7hC0j8X/nfCaQxRICzYwSPbtvs0M4Exgl7h9fwAhRZS1x59wvoG4OoPM0Jdbv 0ocIO0qca7jKCBKWEOCTuPFWECTMDGRO2jadGSLMK9HRJgRRrSLxe9V0aAhJSXQ/+Q91pofE m2NPoMHYzyhxYMZmlgmM8rMQli1gZFzFKJ5aWpybnlpslJdarlecmFtcmpeul5yfu4kRmFhO /zv+ZQfjrj9JhxgFOBiVeHgjPq+PE2JNLCuuzD3EKMHBrCTCu6MFKMSbklhZlVqUH19UmpNa fIhRmoNFSZzXeNHLWCGB9MSS1OzU1ILUIpgsEwenVANjYqls2N0HB5lEwisYdvDz2O+OFWLa Nc/euXv9Gb/SM/HP+0Uux+qc+7yTszPVSSSiYedaHbd0qeg3FubNHa1TZY6XPzs++9mmr/f5 F67K5jmVaNfwbI3f1F/PTMTtj3VkSJ5sD1324PQbvnWuVkwrJ+TX63oLayy6K7k6o2T54/zn 66ri9z5RYinOSDTUYi4qTgQAkko47CgDAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrKLMWRmVeSWpSXmKPExsVy+t/xe7qVfBviDB7vsrTYOGM9q8XUnniL G7/aWC3WHrnLbvGmrZHRYsHkJ6wW22YtZ7M4/Kad1eLblm2MFm/3drI7cHnMbrjI4jFv1gkW j52z7rJ7nL2zg9Gjb8sqRo/1W66yeGw+XR3AHqVnU5RfWpKqkJFfXGKrFG1oYaRnaGmhZ2Ri qWdobB5rZWSqpG9nk5Kak1mWWqRvl6CX8f76X+aCuSIVm193sjUwHhfoYuTkkBAwkdi75Qxb FyMXh5DAUkaJL+0PWbsYOYASUhLzW5QgaoQl/lzrgqr5xChxfMUqFpAEm4ChRO/RPkYQW0Qg ROLF0StMIEXMAusZJS6en88MkhAWKJGYdeEnG4jNIqAqse5jCzuIzStgLdEzewczxAZ5idUb DoDZnAI2Em+aPoEtEAKq2fvjGNsERr4FjAyrGEVSS4tz03OLDfWKE3OLS/PS9ZLzczcxAoN8 27Gfm3cwXtoYfIhRgINRiYc34vP6OCHWxLLiytxDjBIczEoivDtagEK8KYmVValF+fFFpTmp xYcYTYGOmsgsJZqcD4zAvJJ4Q1NDcwtLQ3Njc2MzCyVx3g6BgzFCAumJJanZqakFqUUwfUwc nFINjGLv7kyevILfW22fhP1dffM5lUrP2Hfv4YkVV96opc2VeqJ4qu9O/hyet8oKj32br185 nnrvfpbuoa9P3SIcKrWy1vzOuMTYtadvRqTw+2nt+S+2BHe0F3Zsr7h+9Z5kYoy0+NS4Tm8F 62v/S33Yp0eHGRt4z1DmPqPnGfdQVf6qU0V758+bSizFGYmGWsxFxYkAf6IubogCAAA= X-CMS-MailID: 20200504124546eucas1p186af18875a3f6acb19b06880efefee30 X-Msg-Generator: CA X-RootMTR: 20200504124546eucas1p186af18875a3f6acb19b06880efefee30 X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20200504124546eucas1p186af18875a3f6acb19b06880efefee30 References: <20200504124523.23484-1-s.nawrocki@samsung.com> X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.30rc1 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.2 at phobos.denx.de X-Virus-Status: Clean From: Nicolas Saenz Julienne Imports Al Viro's original Linux commit 00b0c9b82663a, which contains an in depth explanation and two fixes from Johannes Berg: e7d4a95da86e0 "bitfield: fix *_encode_bits()", 37a3862e12382 "bitfield: add u8 helpers". Signed-off-by: Nicolas Saenz Julienne [s.nawrocki: added empty lines between functions and macros] Signed-off-by: Sylwester Nawrocki Reviewed-by: Bin Meng --- Changes since v1: - added empty lines between functions and macros. Changes since RFC: - new patch. --- include/linux/bitfield.h | 50 ++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 50 insertions(+) diff --git a/include/linux/bitfield.h b/include/linux/bitfield.h index 8b9d6ff..7acba4c 100644 --- a/include/linux/bitfield.h +++ b/include/linux/bitfield.h @@ -103,4 +103,54 @@ (typeof(_mask))(((_reg) & (_mask)) >> __bf_shf(_mask)); \ }) +extern void __compiletime_error("value doesn't fit into mask") +__field_overflow(void); +extern void __compiletime_error("bad bitfield mask") +__bad_mask(void); +static __always_inline u64 field_multiplier(u64 field) +{ + if ((field | (field - 1)) & ((field | (field - 1)) + 1)) + __bad_mask(); + return field & -field; +} +static __always_inline u64 field_mask(u64 field) +{ + return field / field_multiplier(field); +} + +#define ____MAKE_OP(type,base,to,from) \ +static __always_inline __##type type##_encode_bits(base v, base field) \ +{ \ + if (__builtin_constant_p(v) && (v & ~field_mask(field))) \ + __field_overflow(); \ + return to((v & field_mask(field)) * field_multiplier(field)); \ +} \ +static __always_inline __##type type##_replace_bits(__##type old, \ + base val, base field) \ +{ \ + return (old & ~to(field)) | type##_encode_bits(val, field); \ +} \ +static __always_inline void type##p_replace_bits(__##type *p, \ + base val, base field) \ +{ \ + *p = (*p & ~to(field)) | type##_encode_bits(val, field); \ +} \ +static __always_inline base type##_get_bits(__##type v, base field) \ +{ \ + return (from(v) & field)/field_multiplier(field); \ +} + +#define __MAKE_OP(size) \ + ____MAKE_OP(le##size,u##size,cpu_to_le##size,le##size##_to_cpu) \ + ____MAKE_OP(be##size,u##size,cpu_to_be##size,be##size##_to_cpu) \ + ____MAKE_OP(u##size,u##size,,) + +____MAKE_OP(u8,u8,,) +__MAKE_OP(16) +__MAKE_OP(32) +__MAKE_OP(64) + +#undef __MAKE_OP +#undef ____MAKE_OP + #endif From patchwork Mon May 4 12:45:21 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sylwester Nawrocki X-Patchwork-Id: 1282600 X-Patchwork-Delegate: matthias.bgg@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; 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Mon, 4 May 2020 12:45:45 +0000 (GMT) From: Sylwester Nawrocki To: u-boot@lists.denx.de, mbrugger@suse.com, marex@denx.de, bmeng.cn@gmail.com Cc: nsaenzjulienne@suse.de, sjg@chromium.org, jh80.chung@samsung.com, m.szyprowski@samsung.com, b.zolnierkie@samsung.com, Sylwester Nawrocki Subject: [PATCH v2 08/10] pci: Add some PCI Express capability register offset definitions Date: Mon, 4 May 2020 14:45:21 +0200 Message-Id: <20200504124523.23484-9-s.nawrocki@samsung.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200504124523.23484-1-s.nawrocki@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA0WSWUhUURzGOXNXJ0duo+DJBGFaoCiXLLikSUIP9yFICMustFEvao6jzHUs tQfNNXNDKWO0cUNcQsZyGnXEMHOrSXPLXaNcQlOzFEkzzevVevv+3/l95/tzOCQizcFsyGBl BKtSyhUyXIwa2tY+nIy2qPZxNC0cpZ8/0WH0ozRfemg9CaOrWsYJej4pDtCFOVMYbdCU4fSb +WSMXtUbAL3Q+IA4L2byYntQRqvpQJl6zTjBdI7VASZDXwkYnf4jytSYYjwIb7FrAKsIjmRV Dm63xEHvO3uxcK353bSGbjwWJIpTgRkJqdPwjymPSAViUkqVA/ilpUkkDCsAanozMZ6SUssA Di977iX6q7pwASoDsHTShPxLjKb04jyFU04wvTUD8NqK8oADa48BDyFUBYBLE6vbhSRpSd2A ycZAnkGpIzBDO7qTlVAu8FvfV0Ros4PPqpt2tBnlCufv/0T5eyCVS8Dc2WkgQBdgbcp3VNCW cK5dTwjaFm7VF4iEQDyAaQ2jhDBkAfipvXA37QLHutZxfiOEOgZ1RgfBdoczEzki3oaUBRxa 2M/byLbMNuQigi2BKUlSgT4Mf1fmigRtAx9Obe2uw8CSHxuo8IqZAHaX4FnATvO/qxCASmDN qrnQQJY7pWTv2HPyUE6tDLT3Dwt9Aba/immzfaUOGDf8mgFFApm5xGtZ5yPF5JFcVGgzgCQi s5LUJWxbkgB5VDSrCvNVqRUs1wwOkqjMWuJcPHtTSgXKI9gQlg1nVXunItLMJhaoYlacq23z FkPeZas/L53rkIRHbt7TDsdfaf2VsGihHWDslQXp05GvbxfPvHKs7ecMROL0xaL+/OtzJ/y8 BztXSy8vnjlb7t5QdHWsxrVRNnktwVgYMzLuNqtoy/f1Lw8+8HL4Uty+QR+s/Sk+cshz0ik5 LN5LAvQVScq3fak9ChnKBcmdjiMqTv4X5BqOXyYDAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrKLMWRmVeSWpSXmKPExsVy+t/xe7pVfBviDL5dl7DYOGM9q8XUnniL G7/aWC3WHrnLbvGmrZHRYsHkJ6wW22YtZ7M4/Kad1eLblm2MFm/3drI7cHnMbrjI4jFv1gkW j52z7rJ7nL2zg9Gjb8sqRo/1W66yeGw+XR3AHqVnU5RfWpKqkJFfXGKrFG1oYaRnaGmhZ2Ri qWdobB5rZWSqpG9nk5Kak1mWWqRvl6CXcebsJdaCeTwVPbsvsDUwtnJ1MXJySAiYSFxZe46t i5GLQ0hgKaPEpPlPWLsYOYASUhLzW5QgaoQl/lzrgqr5xCjxatpLFpAEm4ChRO/RPkYQW0Qg ROLF0StMIEXMAusZJS6en88MkhAWiJKY1XuUCcRmEVCV6Jt3mw3E5hWwlnh9+TkzxAZ5idUb DoDZnAI2Em+aPoEtEAKq2fvjGNsERr4FjAyrGEVSS4tz03OLDfWKE3OLS/PS9ZLzczcxAoN8 27Gfm3cwXtoYfIhRgINRiYc34vP6OCHWxLLiytxDjBIczEoivDtagEK8KYmVValF+fFFpTmp xYcYTYGOmsgsJZqcD4zAvJJ4Q1NDcwtLQ3Njc2MzCyVx3g6BgzFCAumJJanZqakFqUUwfUwc nFINjKGZJ1gSU05cd01meNbhfPi3/2pv1811DAmH/v2b8OKlO5P946DmQwLtSUvnPNrxaY9C SGsqt4f6ms5MawmzqbPmmU7tZxex+e877cLlm3/WHPlt/6alTFnh2X3ZdHmHj4/OLTz2ppJT VeL7zXextbEfHW/J5J+JkIpmiQrqfKr+/PGkqzd/3FNiKc5INNRiLipOBADmgB8uiAIAAA== X-CMS-MailID: 20200504124546eucas1p19294ad098a72837a08ce74cb00b99253 X-Msg-Generator: CA X-RootMTR: 20200504124546eucas1p19294ad098a72837a08ce74cb00b99253 X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20200504124546eucas1p19294ad098a72837a08ce74cb00b99253 References: <20200504124523.23484-1-s.nawrocki@samsung.com> X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.30rc1 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.2 at phobos.denx.de X-Virus-Status: Clean Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki Reviewed-by: Bin Meng Reviewed-by: Nicolas Saenz Julienne --- Changes since v1: - none. Changes since RFC: - ensure the entries are added in order, sorted by ascending address values. --- include/pci.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/include/pci.h b/include/pci.h index dfdbb32..66676c0 100644 --- a/include/pci.h +++ b/include/pci.h @@ -479,11 +479,17 @@ #define PCI_EXP_DEVCTL 8 /* Device Control */ #define PCI_EXP_DEVCTL_BCR_FLR 0x8000 /* Bridge Configuration Retry / FLR */ #define PCI_EXP_LNKCAP 12 /* Link Capabilities */ +#define PCI_EXP_LNKCAP_SLS 0x0000000f /* Supported Link Speeds */ +#define PCI_EXP_LNKCAP_MLW 0x000003f0 /* Maximum Link Width */ #define PCI_EXP_LNKCAP_DLLLARC 0x00100000 /* Data Link Layer Link Active Reporting Capable */ #define PCI_EXP_LNKSTA 18 /* Link Status */ +#define PCI_EXP_LNKSTA_CLS 0x000f /* Current Link Speed */ +#define PCI_EXP_LNKSTA_NLW 0x03f0 /* Negotiated Link Width */ +#define PCI_EXP_LNKSTA_NLW_SHIFT 4 /* start of NLW mask in link status */ #define PCI_EXP_LNKSTA_DLLLA 0x2000 /* Data Link Layer Link Active */ #define PCI_EXP_SLTCAP 20 /* Slot Capabilities */ #define PCI_EXP_SLTCAP_PSN 0xfff80000 /* Physical Slot Number */ +#define PCI_EXP_LNKCTL2 48 /* Link Control 2 */ /* Include the ID list */ From patchwork Mon May 4 12:45:22 2020 Content-Type: text/plain; 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Mon, 4 May 2020 12:45:46 +0000 (GMT) From: Sylwester Nawrocki To: u-boot@lists.denx.de, mbrugger@suse.com, marex@denx.de, bmeng.cn@gmail.com Cc: nsaenzjulienne@suse.de, sjg@chromium.org, jh80.chung@samsung.com, m.szyprowski@samsung.com, b.zolnierkie@samsung.com, Sylwester Nawrocki Subject: [PATCH v2 09/10] pci: Add driver for Broadcom STB PCIe controller Date: Mon, 4 May 2020 14:45:22 +0200 Message-Id: <20200504124523.23484-10-s.nawrocki@samsung.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200504124523.23484-1-s.nawrocki@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprBKsWRmVeSWpSXmKPExsWy7djPc7rVfBviDLacFLPYOGM9q8XUnniL G7/aWC3WHrnLbvGmrZHRYsHkJ6wW22YtZ7M4/Kad1eLblm2MFm/3drI7cHnMbrjI4jFv1gkW j52z7rJ7nL2zg9Gjb8sqRo/1W66yeGw+XR3AHsVlk5Kak1mWWqRvl8CVsWHmZZaCHUsZK75v W8PawPi+g7GLkZNDQsBE4vyOLpYuRi4OIYEVjBLvr/xignC+MErM+POYGcL5zChxdcNUuJbW NyugqpYzSjyZ9Z0RruXtxFXMIFVsAoYSvUf7wDpEBAIkrv2cBlbELLCSUeLDvW/sIAlhAS+J 1807wGwWAVWJa9cngdm8AjYSC/9tY4ZYJy+xesMBMJsTKP6m6RPYtRIC09klPkw6wAZR5CIx o/8+1H3CEq+Ob2GHsGUkTk/ugWpoZpTo2X2bHcKZwChx//gCqA5riTvnfgFN4gC6T1Ni/S59 iLCjxPWeWywgYQkBPokbbwVBwsxA5qRt05khwrwSHW1CENUqEr9XTWeCsKUkup/8Z4GwPSQ6 7r1lhYRQP6PEpw+zWCYwys9CWLaAkXEVo3hqaXFuemqxUV5quV5xYm5xaV66XnJ+7iZGYHo5 /e/4lx2Mu/4kHWIU4GBU4uGN+Lw+Tog1say4MvcQowQHs5II744WoBBvSmJlVWpRfnxRaU5q 8SFGaQ4WJXFe40UvY4UE0hNLUrNTUwtSi2CyTBycUg2MIdWvOTNqs+dXLl7A9Cg+7PKfnz/2 OIjr3Z5+7/8Ld58bkzZ+tZ+5dWVHTqIMi+JmldhVtw86b9iXyfH0qKWWyJpS/sxTzPPXFe/6 xz7VPmHLhV/cGi+V+l5r/Hw4YcOGW+7X+4J+pqx7fFNxt+jbBN09akyTpRVPZkfE/5s5o6wg g3Fh6JYN2UosxRmJhlrMRcWJAKZhkX8rAwAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrOLMWRmVeSWpSXmKPExsVy+t/xe7pVfBviDPZcN7fYOGM9q8XUnniL G7/aWC3WHrnLbvGmrZHRYsHkJ6wW22YtZ7M4/Kad1eLblm2MFm/3drI7cHnMbrjI4jFv1gkW j52z7rJ7nL2zg9Gjb8sqRo/1W66yeGw+XR3AHqVnU5RfWpKqkJFfXGKrFG1oYaRnaGmhZ2Ri qWdobB5rZWSqpG9nk5Kak1mWWqRvl6CXsWHmZZaCHUsZK75vW8PawPi+g7GLkZNDQsBEovXN CqYuRi4OIYGljBJTpjWxdTFyACWkJOa3KEHUCEv8udbFBlHziVFi34QuFpAEm4ChRO/RPrBB IgIhEi+OXgEbxCywnlHi4vn5zCAJYQEvidfNO9hBbBYBVYlr1yeB2bwCNhIL/21jhtggL7F6 wwEwmxMo/qbpE9gCIQFrib0/jrFNYORbwMiwilEktbQ4Nz232EivODG3uDQvXS85P3cTIzDQ tx37uWUHY9e74EOMAhyMSjy8G76ujxNiTSwrrsw9xCjBwawkwrujBSjEm5JYWZValB9fVJqT WnyI0RToqInMUqLJ+cAozCuJNzQ1NLewNDQ3Njc2s1AS5+0QOBgjJJCeWJKanZpakFoE08fE wSnVwJju/sE/yejYWv8cR2mW/9z/S6Tfmxx80nnVamsG95LtM/5+fjCH89ZRDoulUQllT/rW BoqcPjL5r9R/W//388v4JjCnc55sKBDTFrkYMWu1jdnky1fKN+xZes77zuezW58ekap3qcy9 w+6Z/ejq719n+tcrsDDN3L36insDU8qrTSJa7L7F9alKLMUZiYZazEXFiQDXZmAyigIAAA== X-CMS-MailID: 20200504124546eucas1p2bf8a243666eee66b1ef480558113a740 X-Msg-Generator: CA X-RootMTR: 20200504124546eucas1p2bf8a243666eee66b1ef480558113a740 X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20200504124546eucas1p2bf8a243666eee66b1ef480558113a740 References: <20200504124523.23484-1-s.nawrocki@samsung.com> X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.30rc1 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.2 at phobos.denx.de X-Virus-Status: Clean This patch adds basic driver for the Broadcom STB PCIe host controller. The code is based on Linux upstream driver (pcie-brcmstb.c) with MSI handling removed. The inbound access memory region is not currently parsed from dma-ranges DT property and a fixed 4GB region is used. The patch has been tested on RPI4 board, i.e. on BCM2711 SoC with VL805 USB Host Controller. Signed-off-by: Nicolas Saenz Julienne Signed-off-by: Sylwester Nawrocki Reviewed-by: Nicolas Saenz Julienne --- Changes since v1: - fixed argument in brcm_pcie_set_ssc() function call - changed rc_bar2_size assignment to value 0xC0000000, as in upstream devicetre Changes since RFC: - reworked to align with current Linux mainline version and u-boot driver by Nicolas Saenz Julienne brcmstb pcie --- drivers/pci/Kconfig | 6 + drivers/pci/Makefile | 1 + drivers/pci/pcie_brcmstb.c | 594 +++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 601 insertions(+) create mode 100644 drivers/pci/pcie_brcmstb.c diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig index 437cd9a..056a021 100644 --- a/drivers/pci/Kconfig +++ b/drivers/pci/Kconfig @@ -197,4 +197,10 @@ config PCIE_MEDIATEK Say Y here if you want to enable Gen2 PCIe controller, which could be found on MT7623 SoC family. +config PCI_BRCMSTB + bool "Broadcom STB PCIe controller" + depends on DM_PCI + depends on ARCH_BCM283X + help + Say Y here if you want to enable Broadcom STB PCIe controller support. endif diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile index c051ecc..3e53b1f 100644 --- a/drivers/pci/Makefile +++ b/drivers/pci/Makefile @@ -43,3 +43,4 @@ obj-$(CONFIG_PCI_PHYTIUM) += pcie_phytium.o obj-$(CONFIG_PCIE_INTEL_FPGA) += pcie_intel_fpga.o obj-$(CONFIG_PCI_KEYSTONE) += pcie_dw_ti.o obj-$(CONFIG_PCIE_MEDIATEK) += pcie_mediatek.o +obj-$(CONFIG_PCI_BRCMSTB) += pcie_brcmstb.o diff --git a/drivers/pci/pcie_brcmstb.c b/drivers/pci/pcie_brcmstb.c new file mode 100644 index 0000000..c6ddf92 --- /dev/null +++ b/drivers/pci/pcie_brcmstb.c @@ -0,0 +1,594 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Broadcom STB PCIe controller driver + * + * Copyright (C) 2020 Samsung Electronics Co., Ltd. + * + * Based on upstream Linux kernel driver: + * drivers/pci/controller/pcie-brcmstb.c + * Copyright (C) 2009 - 2017 Broadcom + * + * Based driver by Nicolas Saenz Julienne + * Copyright (C) 2020 Nicolas Saenz Julienne + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +/* BRCM_PCIE_CAP_REGS - Offset for the mandatory capability config regs */ +#define BRCM_PCIE_CAP_REGS 0x00ac + +/* Broadcom STB PCIe Register Offsets */ +#define PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1 0x0188 +#define PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR2_MASK 0xc +#define PCIE_RC_CFG_VENDOR_SPCIFIC_REG1_LITTLE_ENDIAN 0x0 + +#define PCIE_RC_CFG_PRIV1_ID_VAL3 0x043c +#define PCIE_RC_CFG_PRIV1_ID_VAL3_CLASS_CODE_MASK 0xffffff + +#define PCIE_RC_DL_MDIO_ADDR 0x1100 +#define PCIE_RC_DL_MDIO_WR_DATA 0x1104 +#define PCIE_RC_DL_MDIO_RD_DATA 0x1108 + +#define PCIE_MISC_MISC_CTRL 0x4008 +#define PCIE_MISC_MISC_CTRL_SCB_ACCESS_EN_MASK 0x1000 +#define PCIE_MISC_MISC_CTRL_CFG_READ_UR_MODE_MASK 0x2000 +#define PCIE_MISC_MISC_CTRL_MAX_BURST_SIZE_MASK 0x300000 +#define PCIE_MISC_MISC_CTRL_MAX_BURST_SIZE_128 0x0 +#define PCIE_MISC_MISC_CTRL_SCB0_SIZE_MASK 0xf8000000 + +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO 0x400c +#define PCIE_MEM_WIN0_LO(win) \ + PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO + ((win) * 4) + +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_HI 0x4010 +#define PCIE_MEM_WIN0_HI(win) \ + PCIE_MISC_CPU_2_PCIE_MEM_WIN0_HI + ((win) * 4) + +#define PCIE_MISC_RC_BAR1_CONFIG_LO 0x402c +#define PCIE_MISC_RC_BAR1_CONFIG_LO_SIZE_MASK 0x1f + +#define PCIE_MISC_RC_BAR2_CONFIG_LO 0x4034 +#define PCIE_MISC_RC_BAR2_CONFIG_LO_SIZE_MASK 0x1f +#define PCIE_MISC_RC_BAR2_CONFIG_HI 0x4038 + +#define PCIE_MISC_RC_BAR3_CONFIG_LO 0x403c +#define PCIE_MISC_RC_BAR3_CONFIG_LO_SIZE_MASK 0x1f + +#define PCIE_MISC_PCIE_STATUS 0x4068 +#define PCIE_MISC_PCIE_STATUS_PCIE_PORT_MASK 0x80 +#define PCIE_MISC_PCIE_STATUS_PCIE_DL_ACTIVE_MASK 0x20 +#define PCIE_MISC_PCIE_STATUS_PCIE_PHYLINKUP_MASK 0x10 +#define PCIE_MISC_PCIE_STATUS_PCIE_LINK_IN_L23_MASK 0x40 + +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT 0x4070 +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_LIMIT_MASK 0xfff00000 +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_BASE_MASK 0xfff0 +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_BASE_HI_SHIFT 12 +#define PCIE_MEM_WIN0_BASE_LIMIT(win) \ + PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT + ((win) * 4) + +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI 0x4080 +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI_BASE_MASK 0xff +#define PCIE_MEM_WIN0_BASE_HI(win) \ + PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI + ((win) * 8) + +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI 0x4084 +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI_LIMIT_MASK 0xff +#define PCIE_MEM_WIN0_LIMIT_HI(win) \ + PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI + ((win) * 8) + +#define PCIE_MISC_HARD_PCIE_HARD_DEBUG 0x4204 +#define PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_MASK 0x2 +#define PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK 0x08000000 + +#define PCIE_MSI_INTR2_CLR 0x4508 +#define PCIE_MSI_INTR2_MASK_SET 0x4510 + +#define PCIE_EXT_CFG_DATA 0x8000 + +#define PCIE_EXT_CFG_INDEX 0x9000 +#define PCIE_EXT_BUSNUM_SHIFT 20 +#define PCIE_EXT_SLOT_SHIFT 15 +#define PCIE_EXT_FUNC_SHIFT 12 + +#define PCIE_RGR1_SW_INIT_1 0x9210 +#define PCIE_RGR1_SW_INIT_1_PERST_MASK 0x1 +#define PCIE_RGR1_SW_INIT_1_INIT_MASK 0x2 + +/* PCIe parameters */ +#define BRCM_NUM_PCIE_OUT_WINS 0x4 + +/* MDIO registers */ +#define MDIO_PORT0 0x0 +#define MDIO_DATA_MASK 0x7fffffff +#define MDIO_PORT_MASK 0xf0000 +#define MDIO_REGAD_MASK 0xffff +#define MDIO_CMD_MASK 0xfff00000 +#define MDIO_CMD_READ 0x1 +#define MDIO_CMD_WRITE 0x0 +#define MDIO_DATA_DONE_MASK 0x80000000 +#define MDIO_RD_DONE(x) (((x) & MDIO_DATA_DONE_MASK) ? 1 : 0) +#define MDIO_WT_DONE(x) (((x) & MDIO_DATA_DONE_MASK) ? 0 : 1) +#define SSC_REGS_ADDR 0x1100 +#define SET_ADDR_OFFSET 0x1f +#define SSC_CNTL_OFFSET 0x2 +#define SSC_CNTL_OVRD_EN_MASK 0x8000 +#define SSC_CNTL_OVRD_VAL_MASK 0x4000 +#define SSC_STATUS_OFFSET 0x1 +#define SSC_STATUS_SSC_MASK 0x400 +#define SSC_STATUS_PLL_LOCK_MASK 0x800 + +struct brcm_pcie { + void __iomem *base; + + int gen; + bool ssc; +}; + +#define msleep(a) udelay((a) * 1000) + +/* + * This is to convert the size of the inbound "BAR" region to the + * non-linear values of PCIE_X_MISC_RC_BAR[123]_CONFIG_LO.SIZE + */ +static int brcm_pcie_encode_ibar_size(u64 size) +{ + int log2_in = ilog2(size); + + if (log2_in >= 12 && log2_in <= 15) + /* Covers 4KB to 32KB (inclusive) */ + return (log2_in - 12) + 0x1c; + else if (log2_in >= 16 && log2_in <= 37) + /* Covers 64KB to 32GB, (inclusive) */ + return log2_in - 15; + /* Something is awry so disable */ + return 0; +} + +/* Configuration space read/write support */ +static inline int brcm_pcie_cfg_index(pci_dev_t bdf, int reg) +{ + return (PCI_DEV(bdf) << PCIE_EXT_SLOT_SHIFT) + | (PCI_FUNC(bdf) << PCIE_EXT_FUNC_SHIFT) + | (PCI_BUS(bdf) << PCIE_EXT_BUSNUM_SHIFT) + | (reg & ~3); +} + +/* The controller is capable of serving in both RC and EP roles */ +static bool brcm_pcie_rc_mode(struct brcm_pcie *pcie) +{ + u32 val = readl(pcie->base + PCIE_MISC_PCIE_STATUS); + + return !!FIELD_GET(PCIE_MISC_PCIE_STATUS_PCIE_PORT_MASK, val); +} + +static bool brcm_pcie_link_up(struct brcm_pcie *pcie) +{ + u32 val = readl(pcie->base + PCIE_MISC_PCIE_STATUS); + u32 dla = FIELD_GET(PCIE_MISC_PCIE_STATUS_PCIE_DL_ACTIVE_MASK, val); + u32 plu = FIELD_GET(PCIE_MISC_PCIE_STATUS_PCIE_PHYLINKUP_MASK, val); + + return dla && plu; +} + +static int brcm_pcie_config_address(const struct udevice *udev, pci_dev_t bdf, + uint offset, void **paddress) +{ + struct brcm_pcie *pcie = dev_get_priv(udev); + unsigned int bus = PCI_BUS(bdf); + unsigned int dev = PCI_DEV(bdf); + int idx; + + /* + * Busses 0 (host PCIe bridge) and 1 (its immediate child) + * are limited to a single device each + */ + if ((bus == (udev->seq + 1)) && dev > 0) + return -ENODEV; + + /* Accesses to the RC go right to the RC registers if PCI device == 0 */ + if (bus == udev->seq) { + if (PCI_DEV(bdf)) + return -ENODEV; + + *paddress = pcie->base + offset; + return 0; + } + + /* For devices, write to the config space index register */ + idx = brcm_pcie_cfg_index(bdf, 0); + + writel(idx, pcie->base + PCIE_EXT_CFG_INDEX); + *paddress = pcie->base + PCIE_EXT_CFG_DATA + offset; + + return 0; +} + +static int brcm_pcie_read_config(const struct udevice *bus, pci_dev_t bdf, + uint offset, ulong *valuep, + enum pci_size_t size) +{ + return pci_generic_mmap_read_config(bus, brcm_pcie_config_address, + bdf, offset, valuep, size); +} + +static int brcm_pcie_write_config(struct udevice *bus, pci_dev_t bdf, + uint offset, ulong value, + enum pci_size_t size) +{ + return pci_generic_mmap_write_config(bus, brcm_pcie_config_address, + bdf, offset, value, size); +} + +static const char *link_speed_to_str(unsigned int s) +{ + static const char * const speed_str[] = { "??", "2.5", "5.0", "8.0" }; + + if (s >= ARRAY_SIZE(speed_str)) + s = 0; + + return speed_str[s]; +} + +static inline void brcm_pcie_bridge_sw_init_set(struct brcm_pcie *pcie, u32 val) +{ + u32 tmp; + + tmp = readl(pcie->base + PCIE_RGR1_SW_INIT_1); + u32p_replace_bits(&tmp, val, PCIE_RGR1_SW_INIT_1_INIT_MASK); + writel(tmp, pcie->base + PCIE_RGR1_SW_INIT_1); +} + +static inline void brcm_pcie_perst_set(struct brcm_pcie *pcie, u32 val) +{ + u32 tmp; + + tmp = readl(pcie->base + PCIE_RGR1_SW_INIT_1); + u32p_replace_bits(&tmp, val, PCIE_RGR1_SW_INIT_1_PERST_MASK); + writel(tmp, pcie->base + PCIE_RGR1_SW_INIT_1); +} + +static u32 brcm_pcie_mdio_form_pkt(int port, int regad, int cmd) +{ + u32 pkt = 0; + + pkt |= FIELD_PREP(MDIO_PORT_MASK, port); + pkt |= FIELD_PREP(MDIO_REGAD_MASK, regad); + pkt |= FIELD_PREP(MDIO_CMD_MASK, cmd); + + return pkt; +} + +/* Negative return value indicates error */ +static int brcm_pcie_mdio_read(void __iomem *base, u8 port, u8 regad, u32 *val) +{ + int tries; + u32 data; + + writel(brcm_pcie_mdio_form_pkt(port, regad, MDIO_CMD_READ), + base + PCIE_RC_DL_MDIO_ADDR); + readl(base + PCIE_RC_DL_MDIO_ADDR); + + data = readl(base + PCIE_RC_DL_MDIO_RD_DATA); + for (tries = 0; !MDIO_RD_DONE(data) && tries < 10; tries++) { + udelay(10); + data = readl(base + PCIE_RC_DL_MDIO_RD_DATA); + } + + *val = FIELD_GET(MDIO_DATA_MASK, data); + return MDIO_RD_DONE(data) ? 0 : -EIO; +} + +/* Negative return value indicates error */ +static int brcm_pcie_mdio_write(void __iomem *base, u8 port, + u8 regad, u16 wrdata) +{ + int tries; + u32 data; + + writel(brcm_pcie_mdio_form_pkt(port, regad, MDIO_CMD_WRITE), + base + PCIE_RC_DL_MDIO_ADDR); + readl(base + PCIE_RC_DL_MDIO_ADDR); + writel(MDIO_DATA_DONE_MASK | wrdata, base + PCIE_RC_DL_MDIO_WR_DATA); + + data = readl(base + PCIE_RC_DL_MDIO_WR_DATA); + for (tries = 0; !MDIO_WT_DONE(data) && tries < 10; tries++) { + udelay(10); + data = readl(base + PCIE_RC_DL_MDIO_WR_DATA); + } + + return MDIO_WT_DONE(data) ? 0 : -EIO; +} + +/* + * Configures device for Spread Spectrum Clocking (SSC) mode; negative + * return value indicates error. + */ +static int brcm_pcie_set_ssc(struct brcm_pcie *pcie) +{ + void __iomem *base = pcie->base; + int pll, ssc; + int ret; + u32 tmp; + + ret = brcm_pcie_mdio_write(base, MDIO_PORT0, SET_ADDR_OFFSET, + SSC_REGS_ADDR); + if (ret < 0) + return ret; + + ret = brcm_pcie_mdio_read(base, MDIO_PORT0, SSC_CNTL_OFFSET, &tmp); + if (ret < 0) + return ret; + + u32p_replace_bits(&tmp, 1, SSC_CNTL_OVRD_EN_MASK); + u32p_replace_bits(&tmp, 1, SSC_CNTL_OVRD_VAL_MASK); + ret = brcm_pcie_mdio_write(base, MDIO_PORT0, SSC_CNTL_OFFSET, tmp); + if (ret < 0) + return ret; + + udelay(1000); + ret = brcm_pcie_mdio_read(base, MDIO_PORT0, SSC_STATUS_OFFSET, &tmp); + if (ret < 0) + return ret; + + ssc = FIELD_GET(SSC_STATUS_SSC_MASK, tmp); + pll = FIELD_GET(SSC_STATUS_PLL_LOCK_MASK, tmp); + + return ssc && pll ? 0 : -EIO; +} + +/* Limits operation to a specific generation (1, 2, or 3) */ +static void brcm_pcie_set_gen(struct brcm_pcie *pcie, int gen) +{ + void __iomem *base = pcie->base; + + u16 lnkctl2 = readw(base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKCTL2); + u32 lnkcap = readl(base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKCAP); + + lnkcap = (lnkcap & ~PCI_EXP_LNKCAP_SLS) | gen; + writel(lnkcap, base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKCAP); + + lnkctl2 = (lnkctl2 & ~0xf) | gen; + writew(lnkctl2, base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKCTL2); +} + +static void brcm_pcie_set_outbound_win(struct brcm_pcie *pcie, + unsigned int win, u64 phys_addr, + u64 pcie_addr, u64 size) +{ + void __iomem *base = pcie->base; + u32 phys_addr_mb_high, limit_addr_mb_high; + phys_addr_t phys_addr_mb, limit_addr_mb; + int high_addr_shift; + u32 tmp; + + /* Set the base of the pcie_addr window */ + writel(lower_32_bits(pcie_addr), base + PCIE_MEM_WIN0_LO(win)); + writel(upper_32_bits(pcie_addr), base + PCIE_MEM_WIN0_HI(win)); + + /* Write the addr base & limit lower bits (in MBs) */ + phys_addr_mb = phys_addr / SZ_1M; + limit_addr_mb = (phys_addr + size - 1) / SZ_1M; + + tmp = readl(base + PCIE_MEM_WIN0_BASE_LIMIT(win)); + u32p_replace_bits(&tmp, phys_addr_mb, + PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_BASE_MASK); + u32p_replace_bits(&tmp, limit_addr_mb, + PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_LIMIT_MASK); + writel(tmp, base + PCIE_MEM_WIN0_BASE_LIMIT(win)); + + /* Write the cpu & limit addr upper bits */ + high_addr_shift = PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_BASE_HI_SHIFT; + phys_addr_mb_high = phys_addr_mb >> high_addr_shift; + tmp = readl(base + PCIE_MEM_WIN0_BASE_HI(win)); + u32p_replace_bits(&tmp, phys_addr_mb_high, + PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI_BASE_MASK); + writel(tmp, base + PCIE_MEM_WIN0_BASE_HI(win)); + + limit_addr_mb_high = limit_addr_mb >> high_addr_shift; + tmp = readl(base + PCIE_MEM_WIN0_LIMIT_HI(win)); + u32p_replace_bits(&tmp, limit_addr_mb_high, + PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI_LIMIT_MASK); + writel(tmp, base + PCIE_MEM_WIN0_LIMIT_HI(win)); +} + +static int brcm_pcie_probe(struct udevice *dev) +{ + struct udevice *ctlr = pci_get_controller(dev); + struct pci_controller *hose = dev_get_uclass_priv(ctlr); + struct brcm_pcie *pcie = dev_get_priv(dev); + void __iomem *base = pcie->base; + bool ssc_good = false; + int num_out_wins = 0; + u64 rc_bar2_offset, rc_bar2_size; + unsigned int scb_size_val; + int i, ret; + u16 nlw, cls, lnksta; + u32 tmp; + + /* Reset the bridge */ + brcm_pcie_bridge_sw_init_set(pcie, 1); + + udelay(150); + + /* Take the bridge out of reset */ + brcm_pcie_bridge_sw_init_set(pcie, 0); + + tmp = readl(base + PCIE_MISC_HARD_PCIE_HARD_DEBUG); + tmp &= ~PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK; + writel(tmp, base + PCIE_MISC_HARD_PCIE_HARD_DEBUG); + /* Wait for SerDes to be stable */ + udelay(150); + + /* Set SCB_MAX_BURST_SIZE, CFG_READ_UR_MODE, SCB_ACCESS_EN */ + u32p_replace_bits(&tmp, 1, PCIE_MISC_MISC_CTRL_SCB_ACCESS_EN_MASK); + u32p_replace_bits(&tmp, 1, PCIE_MISC_MISC_CTRL_CFG_READ_UR_MODE_MASK); + u32p_replace_bits(&tmp, PCIE_MISC_MISC_CTRL_MAX_BURST_SIZE_128, + PCIE_MISC_MISC_CTRL_MAX_BURST_SIZE_MASK); + writel(tmp, base + PCIE_MISC_MISC_CTRL); + + /* + * TODO: When support for other SoCs than BCM2711 is added we may + * need to use the base address and size(s) provided in the dma-ranges + * property. + */ + rc_bar2_offset = 0; + rc_bar2_size = 0xc0000000; + + tmp = lower_32_bits(rc_bar2_offset); + u32p_replace_bits(&tmp, brcm_pcie_encode_ibar_size(rc_bar2_size), + PCIE_MISC_RC_BAR2_CONFIG_LO_SIZE_MASK); + writel(tmp, base + PCIE_MISC_RC_BAR2_CONFIG_LO); + writel(upper_32_bits(rc_bar2_offset), + base + PCIE_MISC_RC_BAR2_CONFIG_HI); + + scb_size_val = rc_bar2_size ? + ilog2(rc_bar2_size) - 15 : 0xf; /* 0xf is 1GB */ + tmp = readl(base + PCIE_MISC_MISC_CTRL); + u32p_replace_bits(&tmp, scb_size_val, + PCIE_MISC_MISC_CTRL_SCB0_SIZE_MASK); + writel(tmp, base + PCIE_MISC_MISC_CTRL); + + /* Disable the PCIe->GISB memory window (RC_BAR1) */ + tmp = readl(base + PCIE_MISC_RC_BAR1_CONFIG_LO); + tmp &= ~PCIE_MISC_RC_BAR1_CONFIG_LO_SIZE_MASK; + writel(tmp, base + PCIE_MISC_RC_BAR1_CONFIG_LO); + + /* Disable the PCIe->SCB memory window (RC_BAR3) */ + tmp = readl(base + PCIE_MISC_RC_BAR3_CONFIG_LO); + tmp &= ~PCIE_MISC_RC_BAR3_CONFIG_LO_SIZE_MASK; + writel(tmp, base + PCIE_MISC_RC_BAR3_CONFIG_LO); + + /* Mask all interrupts since we are not handling any yet */ + writel(0xffffffff, base + PCIE_MSI_INTR2_MASK_SET); + + /* Clear any interrupts we find on boot */ + writel(0xffffffff, base + PCIE_MSI_INTR2_CLR); + + if (pcie->gen) + brcm_pcie_set_gen(pcie, pcie->gen); + + /* Unassert the fundamental reset */ + brcm_pcie_perst_set(pcie, 0); + + /* Give the RC/EP time to wake up, before trying to configure RC. + * Intermittently check status for link-up, up to a total of 100ms. + */ + for (i = 0; i < 100 && !brcm_pcie_link_up(pcie); i += 5) + msleep(5); + + if (!brcm_pcie_link_up(pcie)) { + printf("PCIe BRCM: link down\n"); + return -ENODEV; + } + + if (!brcm_pcie_rc_mode(pcie)) { + printf("PCIe misconfigured; is in EP mode\n"); + return -EINVAL; + } + + for (i = 0; i < hose->region_count; i++) { + struct pci_region *reg = &hose->regions[i]; + + if (reg->flags != PCI_REGION_MEM) + continue; + + if (num_out_wins >= BRCM_NUM_PCIE_OUT_WINS) + return -EINVAL; + + brcm_pcie_set_outbound_win(pcie, num_out_wins, reg->phys_start, + reg->bus_start, reg->size); + + num_out_wins++; + } + + /* + * For config space accesses on the RC, show the right class for + * a PCIe-PCIe bridge (the default setting is to be EP mode). + */ + tmp = readl(base + PCIE_RC_CFG_PRIV1_ID_VAL3); + u32p_replace_bits(&tmp, 0x060400, + PCIE_RC_CFG_PRIV1_ID_VAL3_CLASS_CODE_MASK); + writel(tmp, base + PCIE_RC_CFG_PRIV1_ID_VAL3); + + if (pcie->ssc) { + ret = brcm_pcie_set_ssc(pcie); + if (ret == 0) + ssc_good = true; + else + printf("PCIe BRCM: failed attempt to enter SSC mode\n"); + } + + lnksta = readw(base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKSTA); + cls = FIELD_GET(PCI_EXP_LNKSTA_CLS, lnksta); + nlw = FIELD_GET(PCI_EXP_LNKSTA_NLW, lnksta); + + printf("PCIe BRCM: link up, %s Gbps x%u %s\n", link_speed_to_str(cls), + nlw, ssc_good ? "(SSC)" : "(!SSC)"); + + /* PCIe->SCB endian mode for BAR */ + tmp = readl(base + PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1); + u32p_replace_bits(&tmp, PCIE_RC_CFG_VENDOR_SPCIFIC_REG1_LITTLE_ENDIAN, + PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR2_MASK); + writel(tmp, base + PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1); + + /* + * Refclk from RC should be gated with CLKREQ# input when ASPM L0s,L1 + * is enabled => setting the CLKREQ_DEBUG_ENABLE field to 1. + */ + tmp = readl(base + PCIE_MISC_HARD_PCIE_HARD_DEBUG); + tmp |= PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_MASK; + writel(tmp, base + PCIE_MISC_HARD_PCIE_HARD_DEBUG); + + return 0; +} + +static int brcm_pcie_ofdata_to_platdata(struct udevice *dev) +{ + struct brcm_pcie *pcie = dev_get_priv(dev); + ofnode dn = dev_ofnode(dev); + u32 max_link_speed; + int ret; + + /* Get the controller base address */ + pcie->base = dev_read_addr_ptr(dev); + if (!pcie->base) + return -EINVAL; + + pcie->ssc = ofnode_read_bool(dn, "brcm,enable-ssc"); + + ret = ofnode_read_u32(dn, "max-link-speed", &max_link_speed); + if (ret < 0 || max_link_speed > 4) + pcie->gen = 0; + else + pcie->gen = max_link_speed; + + return 0; +} + +static const struct dm_pci_ops brcm_pcie_ops = { + .read_config = brcm_pcie_read_config, + .write_config = brcm_pcie_write_config, +}; + +static const struct udevice_id brcm_pcie_ids[] = { + { .compatible = "brcm,bcm2711-pcie" }, + { } +}; + +U_BOOT_DRIVER(pcie_brcm_base) = { + .name = "pcie_brcm", + .id = UCLASS_PCI, + .ops = &brcm_pcie_ops, + .of_match = brcm_pcie_ids, + .probe = brcm_pcie_probe, + .ofdata_to_platdata = brcm_pcie_ofdata_to_platdata, + .priv_auto_alloc_size = sizeof(struct brcm_pcie), +}; From patchwork Mon May 4 12:45:23 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sylwester Nawrocki X-Patchwork-Id: 1282602 X-Patchwork-Delegate: matthias.bgg@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; 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Mon, 4 May 2020 12:45:46 +0000 (GMT) From: Sylwester Nawrocki To: u-boot@lists.denx.de, mbrugger@suse.com, marex@denx.de, bmeng.cn@gmail.com Cc: nsaenzjulienne@suse.de, sjg@chromium.org, jh80.chung@samsung.com, m.szyprowski@samsung.com, b.zolnierkie@samsung.com, Sylwester Nawrocki Subject: [PATCH v2 10/10] config: Enable support for the XHCI controller on RPI4 board Date: Mon, 4 May 2020 14:45:23 +0200 Message-Id: <20200504124523.23484-11-s.nawrocki@samsung.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200504124523.23484-1-s.nawrocki@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprEKsWRmVeSWpSXmKPExsWy7djP87rVfBviDOac07bYOGM9q8XUnniL G7/aWC3WHrnLbvGmrZHRYsHkJ6wW22YtZ7M4/Kad1eLblm2MFm/3drI7cHnMbrjI4jFv1gkW j52z7rJ7nL2zg9Gjb8sqRo/1W66yeGw+XR3AHsVlk5Kak1mWWqRvl8CVsezNBOaCtwoVH57s Y2tgXC3TxcjJISFgIvHr70m2LkYuDiGBFYwSm+fuZ4VwvjBKrPyxAcr5zChx4dgMxi5GDrCW no8CIN1CAssZJTY8YodraGz8ywSSYBMwlOg92scIYosIBEhc+zmNEaSIWWAlo8SHe9/YQRLC AhESi29eBytiEVCVmL92LzPIAl4BG4n7L00hzpOXWL3hADOIzQkUftP0iQUiPp1d4sbPQgjb RWLGwq3sELawxKvjW6BsGYnTk3tYQPZKCDQzSvTsvs0O4UxglLh/fAEjRJW1xJ1zv9hAFjML aEqs36UPEXaUmLbiDTvEw3wSN94KgoSZgcxJ26YzQ4R5JTrahCCqVSR+r5rOBGFLSXQ/+Q91 pofE35OXoOHTzyjR23+ddQKj/CyEZQsYGVcxiqeWFuempxYb5qWW6xUn5haX5qXrJefnbmIE ppTT/45/2sH49VLSIUYBDkYlHt6Iz+vjhFgTy4orcw8xSnAwK4nw7mgBCvGmJFZWpRblxxeV 5qQWH2KU5mBREuc1XvQyVkggPbEkNTs1tSC1CCbLxMEp1cC4v7Wp71hSJHPDqbo78375r1bq vHw9RYF9kvCuXX5r/xcyON7pcGntijwRVStePlW+6PPGVU+nBK1XjPz6ZefqtUarF2unnfnI sfN7rdfUR8+Wm9k1RlT7u4R/EY4XPXPqwC6tb8t27ym89OvBMbmAW1yZ+xPWf9dXmd5//H6L 4sbi+rS9853PKbEUZyQaajEXFScCAF6oWbElAwAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrMLMWRmVeSWpSXmKPExsVy+t/xe7rVfBviDI6eFrfYOGM9q8XUnniL G7/aWC3WHrnLbvGmrZHRYsHkJ6wW22YtZ7M4/Kad1eLblm2MFm/3drI7cHnMbrjI4jFv1gkW j52z7rJ7nL2zg9Gjb8sqRo/1W66yeGw+XR3AHqVnU5RfWpKqkJFfXGKrFG1oYaRnaGmhZ2Ri qWdobB5rZWSqpG9nk5Kak1mWWqRvl6CXsezNBOaCtwoVH57sY2tgXC3TxcjBISFgItHzUaCL kYtDSGApo8TUO3sZIeJSEvNblLoYOYFMYYk/17rYIGo+MUqc+9fNBpJgEzCU6D3axwhiiwiE SLw4eoUJpIhZYD2jxMXz85lBEsICYRJ7r7UygdgsAqoS89fuZQZZwCtgI3H/pSnEAnmJ1RsO gJVzAoXfNH1iAbGFBKwl9v44xjaBkW8BI8MqRpHU0uLc9NxiI73ixNzi0rx0veT83E2MwADf duznlh2MXe+CDzEKcDAq8fBu+Lo+Tog1say4MvcQowQHs5II744WoBBvSmJlVWpRfnxRaU5q 8SFGU6CbJjJLiSbnA6MvryTe0NTQ3MLS0NzY3NjMQkmct0PgYIyQQHpiSWp2ampBahFMHxMH p1QD41S+Mw7rHeLeu/SKT390K/UNp29zV+uP9G3/nHuvvd4+QenEhYj8tiOFWzdNPqA878eq kD8LF6YeVkg09Zsf+c225KHflAkGVZPKgp8psMxe3vvw5LnK1plHC77Ebq3RXb/7ase9XGez h7oZS7LN9j6PtYj2klg5lVXuSfbsJRftNp2dHWKw4KsSS3FGoqEWc1FxIgC8EytGhgIAAA== X-CMS-MailID: 20200504124547eucas1p12650f3069a692bcbfae1080b1cda060e X-Msg-Generator: CA X-RootMTR: 20200504124547eucas1p12650f3069a692bcbfae1080b1cda060e X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20200504124547eucas1p12650f3069a692bcbfae1080b1cda060e References: <20200504124523.23484-1-s.nawrocki@samsung.com> X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.30rc1 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.2 at phobos.denx.de X-Virus-Status: Clean From: Marek Szyprowski This requires enabling BRCMSTB PCIe and XHCI_PCI drivers as well as PCI and USB commands. To get it working one has to call the following commands: "pci enum; usb start;", thus such commands have been added to the default "preboot" environment variable. One has to update their environment if it is already configured to get this feature working out of the box. Signed-off-by: Marek Szyprowski Signed-off-by: Sylwester Nawrocki --- Changes since v1: - removed unneeded CONFIG_XHCI_64BIT_DWORD_ACCESS_ONLY entry. Changes since RFC: - none. --- configs/rpi_4_32b_defconfig | 9 +++++++++ configs/rpi_4_defconfig | 9 +++++++++ configs/rpi_arm64_defconfig | 8 +++++++- 3 files changed, 25 insertions(+), 1 deletion(-) diff --git a/configs/rpi_4_32b_defconfig b/configs/rpi_4_32b_defconfig index 72cda5d..0dd763f 100644 --- a/configs/rpi_4_32b_defconfig +++ b/configs/rpi_4_32b_defconfig @@ -8,6 +8,8 @@ CONFIG_NR_DRAM_BANKS=2 CONFIG_DISTRO_DEFAULTS=y CONFIG_OF_BOARD_SETUP=y # CONFIG_ARCH_FIXUP_FDT_MEMORY is not set +CONFIG_USE_PREBOOT=y +CONFIG_PREBOOT="pci enum; usb start;" CONFIG_MISC_INIT_R=y # CONFIG_DISPLAY_CPUINFO is not set # CONFIG_DISPLAY_BOARDINFO is not set @@ -15,6 +17,8 @@ CONFIG_SYS_PROMPT="U-Boot> " CONFIG_CMD_DFU=y CONFIG_CMD_GPIO=y CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y +CONFIG_CMD_USB=y CONFIG_CMD_FS_UUID=y CONFIG_OF_BOARD=y CONFIG_ENV_FAT_INTERFACE="mmc" @@ -28,12 +32,17 @@ CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_BCM2835=y CONFIG_DM_ETH=y CONFIG_BCMGENET=y +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_PCI_BRCMSTB=y CONFIG_PINCTRL=y # CONFIG_PINCTRL_GENERIC is not set # CONFIG_REQUIRE_SERIAL_CONSOLE is not set CONFIG_USB=y CONFIG_DM_USB=y CONFIG_DM_USB_GADGET=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_PCI=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="FSL" CONFIG_USB_GADGET_VENDOR_NUM=0x0525 diff --git a/configs/rpi_4_defconfig b/configs/rpi_4_defconfig index 6d148da..3f1a1b5 100644 --- a/configs/rpi_4_defconfig +++ b/configs/rpi_4_defconfig @@ -8,6 +8,8 @@ CONFIG_NR_DRAM_BANKS=2 CONFIG_DISTRO_DEFAULTS=y CONFIG_OF_BOARD_SETUP=y # CONFIG_ARCH_FIXUP_FDT_MEMORY is not set +CONFIG_USE_PREBOOT=y +CONFIG_PREBOOT="pci enum; usb start;" CONFIG_MISC_INIT_R=y # CONFIG_DISPLAY_CPUINFO is not set # CONFIG_DISPLAY_BOARDINFO is not set @@ -15,6 +17,8 @@ CONFIG_SYS_PROMPT="U-Boot> " CONFIG_CMD_DFU=y CONFIG_CMD_GPIO=y CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y +CONFIG_CMD_USB=y CONFIG_CMD_FS_UUID=y CONFIG_OF_BOARD=y CONFIG_ENV_FAT_INTERFACE="mmc" @@ -28,12 +32,17 @@ CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_BCM2835=y CONFIG_DM_ETH=y CONFIG_BCMGENET=y +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_PCI_BRCMSTB=y CONFIG_PINCTRL=y # CONFIG_PINCTRL_GENERIC is not set # CONFIG_REQUIRE_SERIAL_CONSOLE is not set CONFIG_USB=y CONFIG_DM_USB=y CONFIG_DM_USB_GADGET=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_PCI=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="FSL" CONFIG_USB_GADGET_VENDOR_NUM=0x0525 diff --git a/configs/rpi_arm64_defconfig b/configs/rpi_arm64_defconfig index fea86be..f12d1e3 100644 --- a/configs/rpi_arm64_defconfig +++ b/configs/rpi_arm64_defconfig @@ -7,13 +7,14 @@ CONFIG_NR_DRAM_BANKS=2 CONFIG_DISTRO_DEFAULTS=y CONFIG_OF_BOARD_SETUP=y CONFIG_USE_PREBOOT=y -CONFIG_PREBOOT="usb start" +CONFIG_PREBOOT="pci enum; usb start;" CONFIG_MISC_INIT_R=y # CONFIG_DISPLAY_CPUINFO is not set # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SYS_PROMPT="U-Boot> " CONFIG_CMD_GPIO=y CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y CONFIG_CMD_USB=y CONFIG_CMD_FS_UUID=y CONFIG_OF_BOARD=y @@ -26,11 +27,16 @@ CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_BCM2835=y CONFIG_DM_ETH=y CONFIG_BCMGENET=y +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_PCI_BRCMSTB=y CONFIG_PINCTRL=y # CONFIG_PINCTRL_GENERIC is not set # CONFIG_REQUIRE_SERIAL_CONSOLE is not set CONFIG_USB=y CONFIG_DM_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_PCI=y CONFIG_USB_DWC2=y CONFIG_USB_KEYBOARD=y CONFIG_USB_HOST_ETHER=y