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Fri, 24 Apr 2020 16:51:54 +0000 (GMT) From: Sylwester Nawrocki To: u-boot@lists.denx.de, mbrugger@suse.com, marex@denx.de, bmeng.cn@gmail.com Cc: sjg@chromium.org, nsaenzjulienne@suse.de, jh80.chung@samsung.com, m.szyprowski@samsung.com, b.zolnierkie@samsung.com, Sylwester Nawrocki Subject: [PATCH v1 01/10] usb: xhci: Add missing cache flush in the scratchpad array initialization Date: Fri, 24 Apr 2020 18:50:03 +0200 Message-Id: <20200424165012.31915-2-s.nawrocki@samsung.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200424165012.31915-1-s.nawrocki@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprGKsWRmVeSWpSXmKPExsWy7djPc7rakovjDDrnqVhsnLGe1WJqT7zF jV9trBZrj9xlt3jT1shosWDyE1aLbbOWs1kcftPOavFtyzZGi7d7O9kduDxmN1xk8Zg36wSL x85Zd9k9zt7ZwejRt2UVo8f6LVdZPDafrg5gj+KySUnNySxLLdK3S+DKODjvIHvBdY6KRQu2 sDQwTmPvYuTkkBAwkbh9ZwtbFyMXh5DACkaJlskdUM4XRolDu38yQTifGSVmX7vNBNNy/eZ3 FojEckaJrZPOM8G1vGzaAjaYTcBQovdoHyOILSIQIHHt5zRGkCJmgZWMEt/6zoElhAVSJR4/ vAdmswioSszqm84GYvMKWEv8eLIXap28xOoNB5hBbE4BG4nGs6/AVksITGaXmH7oHytEkYvE hWudLBC2sMSr41ug3pOROD25B6qhmVGiZ/dtdghnAqPE/eMLGCGqrCXunPsFtJoD6D5NifW7 9CHCjhIXNs1kBwlLCPBJ3HgrCBJmBjInbZvODBHmlehoE4KoVpH4vWo61M1SEt1P/kOd4yFx 48FeVkgI9TNKnG9+yDqBUX4WwrIFjIyrGMVTS4tz01OLDfNSy/WKE3OLS/PS9ZLzczcxAlPL 6X/HP+1g/Hop6RCjAAejEg9vxJFFcUKsiWXFlbmHGCU4mJVEeGNKgEK8KYmVValF+fFFpTmp xYcYpTlYlMR5jRe9jBUSSE8sSc1OTS1ILYLJMnFwSjUwFtpVZM17VclaksruJCB49eqSaykH tp23CVz3zu7bhggV1fNHD0xPKAwX3OjvJ3zZrTA9elH62/o/DD22Bc5HyiaLK96LCjbKjn/+ RSvfcZ1CytJGkyOWVy3Z7f93B17q/FXeoq6mUGjO8kmd+/2u0wqu6UfX9ga49vbeK5URfGOz 0ugJ40UlluKMREMt5qLiRACo4SvBKQMAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrCLMWRmVeSWpSXmKPExsVy+t/xe7rakovjDG5s5bLYOGM9q8XUnniL G7/aWC3WHrnLbvGmrZHRYsHkJ6wW22YtZ7M4/Kad1eLblm2MFm/3drI7cHnMbrjI4jFv1gkW j52z7rJ7nL2zg9Gjb8sqRo/1W66yeGw+XR3AHqVnU5RfWpKqkJFfXGKrFG1oYaRnaGmhZ2Ri qWdobB5rZWSqpG9nk5Kak1mWWqRvl6CXcXDeQfaC6xwVixZsYWlgnMbexcjJISFgInH95ncW EFtIYCmjxOIztV2MHEBxKYn5LUoQJcISf651sXUxcgGVfGKUmHHvOTNIgk3AUKL3aB8jiC0i ECLx4ugVJpAiZoH1jBIbbsxkA0kICyRL/Pi5mQnEZhFQlZjVNx0szitgLfHjyV4miA3yEqs3 HAAbyilgI9F49hXUQdYS22Y+Z5nAyLeAkWEVo0hqaXFuem6xoV5xYm5xaV66XnJ+7iZGYIhv O/Zz8w7GSxuDDzEKcDAq8fBGHFkUJ8SaWFZcmXuIUYKDWUmEN6YEKMSbklhZlVqUH19UmpNa fIjRFOioicxSosn5wPjLK4k3NDU0t7A0NDc2NzazUBLn7RA4GCMkkJ5YkpqdmlqQWgTTx8TB KdXAqPav4WPwngPfMipspTa5a1VvnJ9xTcogrq2k/ujfrqCiSIaNk923zO/4v2T37r9PtVM3 e3B0TJ2wav97wW9zH85IenH+puCu3TpTnton8qokLjJXeCIgspX3fv5e3/SGowaeXZGNHf1N Mt+i/fb8/FfXuWzq12YRJv20vXOKj07Yd3PWh4kzIpVYijMSDbWYi4oTAeczg0CHAgAA X-CMS-MailID: 20200424165155eucas1p10c63e5efe95bf1dc4a430442fcb23178 X-Msg-Generator: CA X-RootMTR: 20200424165155eucas1p10c63e5efe95bf1dc4a430442fcb23178 X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20200424165155eucas1p10c63e5efe95bf1dc4a430442fcb23178 References: <20200424165012.31915-1-s.nawrocki@samsung.com> X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.30rc1 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.2 at phobos.denx.de X-Virus-Status: Clean In current code there is no cache flush after initializing the scratchpad buffer array with the scratchpad buffer pointers. This leads to a failure of the "slot enable" command on the rpi4 board (Broadcom STB PCIe controller + VL805 USB hub) - the very first TRB transfer on the command ring fails and there is a timeout while waiting for the command completion event. After adding the missing cache flush everything seems to be working as expected. Reviewed-by: Bin Meng Signed-off-by: Sylwester Nawrocki Reviewed-by: Nicolas Saenz Julienne --- Changes since RFC: - none. --- drivers/usb/host/xhci-mem.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/usb/host/xhci-mem.c b/drivers/usb/host/xhci-mem.c index 93450ee..729bdc3 100644 --- a/drivers/usb/host/xhci-mem.c +++ b/drivers/usb/host/xhci-mem.c @@ -393,6 +393,9 @@ static int xhci_scratchpad_alloc(struct xhci_ctrl *ctrl) scratchpad->sp_array[i] = cpu_to_le64(ptr); } + xhci_flush_cache((uintptr_t)scratchpad->sp_array, + sizeof(u64) * num_sp); + return 0; fail_sp3: From patchwork Fri Apr 24 16:50:04 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sylwester Nawrocki X-Patchwork-Id: 1276514 X-Patchwork-Delegate: matthias.bgg@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; 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Fri, 24 Apr 2020 16:51:57 +0000 (GMT) Received: from eusmgms1.samsung.com (unknown [182.198.249.179]) by eusmtrp1.samsung.com (KnoxPortal) with ESMTP id 20200424165157eusmtrp14cf77ab5ca721c5f1f51cc8490a53f5e~Iz5deFp9s1224212242eusmtrp1D; Fri, 24 Apr 2020 16:51:57 +0000 (GMT) X-AuditID: cbfec7f4-0e5ff7000001ed07-90-5ea3192eab1c Received: from eusmtip2.samsung.com ( [203.254.199.222]) by eusmgms1.samsung.com (EUCPMTA) with SMTP id 2E.3F.08375.D2913AE5; Fri, 24 Apr 2020 17:51:57 +0100 (BST) Received: from AMDC3061.digital.local (unknown [106.120.51.75]) by eusmtip2.samsung.com (KnoxPortal) with ESMTPA id 20200424165156eusmtip2a64a79e11bd3a28fbbeb5ae27c182675~Iz5cz7ssj1549415494eusmtip2Y; Fri, 24 Apr 2020 16:51:56 +0000 (GMT) From: Sylwester Nawrocki To: u-boot@lists.denx.de, mbrugger@suse.com, marex@denx.de, bmeng.cn@gmail.com Cc: sjg@chromium.org, nsaenzjulienne@suse.de, jh80.chung@samsung.com, m.szyprowski@samsung.com, b.zolnierkie@samsung.com, Sylwester Nawrocki , Sergey Temerkhanov Subject: [PATCH v1 02/10] usb: xhci: Use only 32-bit accesses in xhci_writeq/xhci_readq Date: Fri, 24 Apr 2020 18:50:04 +0200 Message-Id: <20200424165012.31915-3-s.nawrocki@samsung.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200424165012.31915-1-s.nawrocki@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprGKsWRmVeSWpSXmKPExsWy7djP87p6kovjDPZtlLTYOGM9q8XUnniL G7/aWC3WHrnLbvGmrZHRYsHkJ6wW22YtZ7M4/Kad1WLprH3sFt+2bGO0eLu3k92B22N2w0UW j3mzTrB47Jx1l93j7J0djB59W1YxeqzfcpXFY/Pp6gD2KC6blNSczLLUIn27BK6ML5trC97w V9w89pmpgfEtTxcjB4eEgInE8QfiXYxcHEICKxglzl3tZoZwvjBKXPm6nAnC+cwo0fOjm72L kROsY9mnJVBVyxkl3m2ZwgKSAGtZeT8IxGYTMJToPdrHCGKLCARIXPs5jRGkgVngOqPEgk/P wBLCApESU25ATGURUJV4+bKNFeQmXgFrian7UyCWyUus3nCAGcTmFLCRaDz7igVkjoTAPHaJ jz8PskD84CLxtSEVol5Y4tXxLVCHykicntwDVd8M9MHu2+wQzgRGifvHFzBCVFlL3Dn3iw1k ELOApsT6XfoQYUeJ+f/Os0LM55O48VYQJMwMZE7aNp0ZIswr0dEmBFGtIvF71XQmCFtKovvJ fxYI20Piz5Mt7JCw6meUWPF8OtMERvlZCMsWMDKuYhRPLS3OTU8tNspLLdcrTswtLs1L10vO z93ECEwtp/8d/7KDcdefpEOMAhyMSjy8DIcWxQmxJpYVV+YeYpTgYFYS4Y0pAQrxpiRWVqUW 5ccXleakFh9ilOZgURLnNV70MlZIID2xJDU7NbUgtQgmy8TBKdXAuNorSL6NY+Viu8dnFPrV uhhL73ILbLef9T5pQpnL/tn/V65r1BPjdX6ZrjihzXPqa99NtY+PtW883FA1d+rqaJV7jGm9 RjHfk3+JTfjr0xxk2fqWocRi9qS3Vnyaey/vaRc7OfuUr9KOO51rWfO/br66c/FMHr4anTdh 4W0XShovh/YasjUcVWIpzkg01GIuKk4EACkt8RcpAwAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrBLMWRmVeSWpSXmKPExsVy+t/xe7q6kovjDC4/VbLYOGM9q8XUnniL G7/aWC3WHrnLbvGmrZHRYsHkJ6wW22YtZ7M4/Kad1WLprH3sFt+2bGO0eLu3k92B22N2w0UW j3mzTrB47Jx1l93j7J0djB59W1YxeqzfcpXFY/Pp6gD2KD2bovzSklSFjPziElulaEMLIz1D Sws9IxNLPUNj81grI1MlfTublNSczLLUIn27BL2ML5trC97wV9w89pmpgfEtTxcjJ4eEgInE sk9LmLsYuTiEBJYySkz9c4q9i5EDKCElMb9FCaJGWOLPtS42iJpPjBK/X7UxgiTYBAwleo/2 gdkiAiESL45eYQIpYha4zyixqnE2E0hCWCBcYuOcf2wgNouAqsTLl22sIAt4Bawlpu5PgVgg L7F6wwFmEJtTwEai8ewrFhBbCKhk28znLBMY+RYwMqxiFEktLc5Nzy021CtOzC0uzUvXS87P 3cQIDPVtx35u3sF4aWPwIUYBDkYlHt6II4vihFgTy4orcw8xSnAwK4nwxpQAhXhTEiurUovy 44tKc1KLDzGaAt00kVlKNDkfGId5JfGGpobmFpaG5sbmxmYWSuK8HQIHY4QE0hNLUrNTUwtS i2D6mDg4pRoYvc0k89IWR3y+zzQxRLlEcOXEP4HngxVjf76+dac6dnFSSFq2jfScg/6bZWfu mLHu6duwU3N+N00+6dHg/evkmVXu56UUZvjy7rVeX7hB/8vTmO6XRpx6BWfeVfK1b7uu3jbd Ofa2iKuaaJmR0p25l2ao7KrUKShJW7zi6f1+w5Mvl8hMfXM6UImlOCPRUIu5qDgRAP3RdD6L AgAA X-CMS-MailID: 20200424165157eucas1p2b0a0eb386fd9304d4cbf1e23248849d9 X-Msg-Generator: CA X-RootMTR: 20200424165157eucas1p2b0a0eb386fd9304d4cbf1e23248849d9 X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20200424165157eucas1p2b0a0eb386fd9304d4cbf1e23248849d9 References: <20200424165012.31915-1-s.nawrocki@samsung.com> X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.30rc1 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.2 at phobos.denx.de X-Virus-Status: Clean There might be hardware configurations where 64-bit data accesses to XHCI registers are not supported properly. This patch removes the readq/writeq so always two 32-bit accesses are used to read/write 64-bit XHCI registers, similarly as it is done in Linux kernel. This patch fixes operation of the XHCI controller on RPI4 Broadcom BCM2711 SoC based board, where the VL805 USB XHCI controller is connected to the PCIe Root Complex, which is attached to the system through the SCB bridge. Even though the architecture is 64-bit the PCIe BAR is 32-bit and likely the 64-bit wide register accesses initiated by the CPU are not properly translated to a sequence of 32-bit PCIe accesses. xhci_readq(), for example, always returns same value in upper and lower 32-bits, e.g. 0xabcd1234abcd1234 instead of 0x00000000abcd1234. Cc: Sergey Temerkhanov Signed-off-by: Sylwester Nawrocki Reviewed-by: Bin Meng Reviewed-by: Nicolas Saenz Julienne --- Changes since RFC: - dropped Kconfig option, switched to not using readq/writeq unconditionally. --- include/usb/xhci.h | 8 -------- 1 file changed, 8 deletions(-) diff --git a/include/usb/xhci.h b/include/usb/xhci.h index 6017504..c16106a 100644 --- a/include/usb/xhci.h +++ b/include/usb/xhci.h @@ -1111,28 +1111,20 @@ static inline void xhci_writel(uint32_t volatile *regs, const unsigned int val) */ static inline u64 xhci_readq(__le64 volatile *regs) { -#if BITS_PER_LONG == 64 - return readq(regs); -#else __u32 *ptr = (__u32 *)regs; u64 val_lo = readl(ptr); u64 val_hi = readl(ptr + 1); return val_lo + (val_hi << 32); -#endif } static inline void xhci_writeq(__le64 volatile *regs, const u64 val) { -#if BITS_PER_LONG == 64 - writeq(val, regs); -#else __u32 *ptr = (__u32 *)regs; u32 val_lo = lower_32_bits(val); /* FIXME */ u32 val_hi = upper_32_bits(val); writel(val_lo, ptr); writel(val_hi, ptr + 1); -#endif } int xhci_hcd_init(int index, struct xhci_hccr **ret_hccr, From patchwork Fri Apr 24 16:50:05 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sylwester Nawrocki X-Patchwork-Id: 1276516 X-Patchwork-Delegate: matthias.bgg@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=samsung.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=samsung.com header.i=@samsung.com header.a=rsa-sha256 header.s=mail20170921 header.b=dSYUWKeP; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4980Zz1k9wz9sSK for ; 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Fri, 24 Apr 2020 16:52:00 +0000 (GMT) From: Sylwester Nawrocki To: u-boot@lists.denx.de, mbrugger@suse.com, marex@denx.de, bmeng.cn@gmail.com Cc: sjg@chromium.org, nsaenzjulienne@suse.de, jh80.chung@samsung.com, m.szyprowski@samsung.com, b.zolnierkie@samsung.com, Sylwester Nawrocki Subject: [PATCH v1 03/10] pci: Move some PCIe register offset definitions to a common header Date: Fri, 24 Apr 2020 18:50:05 +0200 Message-Id: <20200424165012.31915-4-s.nawrocki@samsung.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200424165012.31915-1-s.nawrocki@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprCKsWRmVeSWpSXmKPExsWy7djP87qGkovjDD6eFbDYOGM9q8XUnniL G7/aWC3WHrnLbvGmrZHRYsHkJ6wW22YtZ7M4/Kad1eLblm2MFm/3drI7cHnMbrjI4jFv1gkW j52z7rJ7nL2zg9Gjb8sqRo/1W66yeGw+XR3AHsVlk5Kak1mWWqRvl8CV8WHSXLaCPRIVHz7F NzDOFOli5OSQEDCReP90MlMXIxeHkMAKRokJt+6yQThfGCX2P3/JCuF8ZpQ4/babGablZ9ci qMRyRokPDb3scC2vvuxgAaliEzCU6D3axwhiiwgESFz7OY0RpIhZYCWjxLe+c2AJYYE4iRvv JoKNZRFQlfg/8w1QnIODV8Ba4v9bGYht8hKrNxwAK+EUsJFoPPuKBWSOhMBkdokj144xQRS5 SGxo/MgCYQtLvDq+hR3ClpH4v3M+E0RDM6NEz+7b7BDOBEaJ+8cXMEJUWUvcOfeLDWQzs4Cm xPpd+hBhR4nPz+cygYQlBPgkbrwVBAkzA5mTtk1nhgjzSnS0CUFUq0j8XjUd6hwpie4n/6HO 8ZDYues6IySA+hkl3m68yDiBUX4WwrIFjIyrGMVTS4tz01OLjfNSy/WKE3OLS/PS9ZLzczcx AtPK6X/Hv+5g3Pcn6RCjAAejEg9vxJFFcUKsiWXFlbmHGCU4mJVEeGNKgEK8KYmVValF+fFF pTmpxYcYpTlYlMR5jRe9jBUSSE8sSc1OTS1ILYLJMnFwSjUwcu+8HvfgdsfuE34K0WeOVUf2 vHQR+D1pYW5mwUlr6bMRZg41j7jtYn7kCPlddtR3e6TB4J21X2mSmqcDzyZWScM7P24Z82oc XfJI5/66tJ+bNAMaDU3frl57YpLGdGPjWYE+EQ9ZxEyY7fc9m8dot0Zt0vZvaW8/d1946Cyq pm4X/fPje+YgJZbijERDLeai4kQA6iiVEScDAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrMLMWRmVeSWpSXmKPExsVy+t/xe7oGkovjDGae0LTYOGM9q8XUnniL G7/aWC3WHrnLbvGmrZHRYsHkJ6wW22YtZ7M4/Kad1eLblm2MFm/3drI7cHnMbrjI4jFv1gkW j52z7rJ7nL2zg9Gjb8sqRo/1W66yeGw+XR3AHqVnU5RfWpKqkJFfXGKrFG1oYaRnaGmhZ2Ri qWdobB5rZWSqpG9nk5Kak1mWWqRvl6CX8WHSXLaCPRIVHz7FNzDOFOli5OSQEDCR+Nm1iLWL kYtDSGApo0Tzry9sXYwcQAkpifktShA1whJ/rnWxQdR8YpTYsauNESTBJmAo0Xu0D8wWEQiR eHH0ChNIEbPAekaJDTdmsoEkhAViJF6um8QCYrMIqEr8n/mGEWQBr4C1xP+3MhAL5CVWbzjA DGJzCthINJ59BVYuBFSybeZzlgmMfAsYGVYxiqSWFuem5xYb6RUn5haX5qXrJefnbmIEBvi2 Yz+37GDsehd8iFGAg1GJhzfiyKI4IdbEsuLK3EOMEhzMSiK8MSVAId6UxMqq1KL8+KLSnNTi Q4ymQDdNZJYSTc4HRl9eSbyhqaG5haWhubG5sZmFkjhvh8DBGCGB9MSS1OzU1ILUIpg+Jg5O qQbGbUkMBpWX85u+pCi++3r//rYAnZmrm/f93vNpNZu077b0tfxP9Sfp39v3IzVHUjFOfVPM h1ualrLyEdc5tkbnHirTdZDKEmkzX/FaL3Stz4eYBN1Loe0bVUvt9bcwzn0a8Ny0vubHXTMG V6/btwJtsy7dbJ7oxii8eyLfBcV5C0W8Mlz3HXVQYinOSDTUYi4qTgQAyUXvoYYCAAA= X-CMS-MailID: 20200424165200eucas1p20975344302a9a3086cf38738f32d287f X-Msg-Generator: CA X-RootMTR: 20200424165200eucas1p20975344302a9a3086cf38738f32d287f X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20200424165200eucas1p20975344302a9a3086cf38738f32d287f References: <20200424165012.31915-1-s.nawrocki@samsung.com> X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.30rc1 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.2 at phobos.denx.de X-Virus-Status: Clean Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Reviewed-by: Bin Meng Signed-off-by: Sylwester Nawrocki Reviewed-by: Nicolas Saenz Julienne --- Changes since RFC: - whitespace clean up. --- drivers/pci/pci-rcar-gen3.c | 8 -------- drivers/pci/pcie_intel_fpga.c | 3 --- include/pci.h | 13 +++++++++++-- 3 files changed, 11 insertions(+), 13 deletions(-) diff --git a/drivers/pci/pci-rcar-gen3.c b/drivers/pci/pci-rcar-gen3.c index 30eff67..393f1c9 100644 --- a/drivers/pci/pci-rcar-gen3.c +++ b/drivers/pci/pci-rcar-gen3.c @@ -117,14 +117,6 @@ #define RCAR_PCI_MAX_RESOURCES 4 #define MAX_NR_INBOUND_MAPS 6 -#define PCI_EXP_FLAGS 2 /* Capabilities register */ -#define PCI_EXP_FLAGS_TYPE 0x00f0 /* Device/Port type */ -#define PCI_EXP_TYPE_ROOT_PORT 0x4 /* Root Port */ -#define PCI_EXP_LNKCAP 12 /* Link Capabilities */ -#define PCI_EXP_LNKCAP_DLLLARC 0x00100000 /* Data Link Layer Link Active Reporting Capable */ -#define PCI_EXP_SLTCAP 20 /* Slot Capabilities */ -#define PCI_EXP_SLTCAP_PSN 0xfff80000 /* Physical Slot Number */ - enum { RCAR_PCI_ACCESS_READ, RCAR_PCI_ACCESS_WRITE, diff --git a/drivers/pci/pcie_intel_fpga.c b/drivers/pci/pcie_intel_fpga.c index 6a9f29c..69363a0 100644 --- a/drivers/pci/pcie_intel_fpga.c +++ b/drivers/pci/pcie_intel_fpga.c @@ -65,9 +65,6 @@ #define IS_ROOT_PORT(pcie, bdf) \ ((PCI_BUS(bdf) == pcie->first_busno) ? true : false) -#define PCI_EXP_LNKSTA 18 /* Link Status */ -#define PCI_EXP_LNKSTA_DLLLA 0x2000 /* Data Link Layer Link Active */ - /** * struct intel_fpga_pcie - Intel FPGA PCIe controller state * @bus: Pointer to the PCI bus diff --git a/include/pci.h b/include/pci.h index 174ddd4..5bf91a4 100644 --- a/include/pci.h +++ b/include/pci.h @@ -471,10 +471,19 @@ #define PCI_EA_FIELD_MASK 0xfffffffc /* For Base & Max Offset */ /* PCI Express capabilities */ +#define PCI_EXP_FLAGS 2 /* Capabilities register */ +#define PCI_EXP_FLAGS_TYPE 0x00f0 /* Device/Port type */ +#define PCI_EXP_TYPE_ROOT_PORT 0x4 /* Root Port */ #define PCI_EXP_DEVCAP 4 /* Device capabilities */ -#define PCI_EXP_DEVCAP_FLR 0x10000000 /* Function Level Reset */ +#define PCI_EXP_DEVCAP_FLR 0x10000000 /* Function Level Reset */ #define PCI_EXP_DEVCTL 8 /* Device Control */ -#define PCI_EXP_DEVCTL_BCR_FLR 0x8000 /* Bridge Configuration Retry / FLR */ +#define PCI_EXP_DEVCTL_BCR_FLR 0x8000 /* Bridge Configuration Retry / FLR */ +#define PCI_EXP_LNKCAP 12 /* Link Capabilities */ +#define PCI_EXP_LNKCAP_DLLLARC 0x00100000 /* Data Link Layer Link Active Reporting Capable */ +#define PCI_EXP_LNKSTA 18 /* Link Status */ +#define PCI_EXP_LNKSTA_DLLLA 0x2000 /* Data Link Layer Link Active */ +#define PCI_EXP_SLTCAP 20 /* Slot Capabilities */ +#define PCI_EXP_SLTCAP_PSN 0xfff80000 /* Physical Slot Number */ /* Include the ID list */ From patchwork Fri Apr 24 16:50:06 2020 Content-Type: text/plain; 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Fri, 24 Apr 2020 16:52:03 +0000 (GMT) From: Sylwester Nawrocki To: u-boot@lists.denx.de, mbrugger@suse.com, marex@denx.de, bmeng.cn@gmail.com Cc: sjg@chromium.org, nsaenzjulienne@suse.de, jh80.chung@samsung.com, m.szyprowski@samsung.com, b.zolnierkie@samsung.com Subject: [PATCH v1 04/10] rpi4: shorten a mapping for the DRAM Date: Fri, 24 Apr 2020 18:50:06 +0200 Message-Id: <20200424165012.31915-5-s.nawrocki@samsung.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200424165012.31915-1-s.nawrocki@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFuplleLIzCtJLcpLzFFi42LZduzneV1TycVxBgfO8VhsnLGe1WJqT7zF jV9trBZrj9xlt3jT1shosWDyE1aLbbOWs1l827KN0eLt3k52B06P2Q0XWTzmzTrB4rFz1l12 j7N3djB69G1ZxeixfstVFo/Np6sD2KO4bFJSczLLUov07RK4Mh5t2sNW8Jy14sy5c+wNjPdZ uhg5OSQETCTO9k1m72Lk4hASWMEoMWnhJDYI5wujxImDK5lAqoQEPjNKvFkgDdexewUTRNFy Rokrj1cwwnU8PvCQEaSKTcBQovdoH5gtIhAgce3nNDCbWaBK4nr7U7DdwgJ2Es82/ADazcHB IqAqcemRD0iYV8BaonXuXajz5CVWbzjADGJzCthINJ59BRXvZ5fo3CAPYbtI9DWvY4SwhSVe Hd/CDmHLSJye3MMCcpuEQDOjRM/u2+wQzgRGifvHF0B1WEvcOfeLDeQIZgFNifW79CHCjhIN i/cwg4QlBPgkbrwVhDifT2LStulQYV6JjjYhiGoVid+rpjNB2FIS3U/+Q53pIfF4zkNmSPD0 M0qc6TjOMoFRfhbCsgWMjKsYxVNLi3PTU4sN81LL9YoTc4tL89L1kvNzNzECE8npf8c/7WD8 einpEKMAB6MSD2/EkUVxQqyJZcWVuYcYJTiYlUR4Y0qAQrwpiZVVqUX58UWlOanFhxilOViU xHmNF72MFRJITyxJzU5NLUgtgskycXBKNTDyZb8pljj9fvaMa/YXdLs+7evgNPstrb99k953 rUXfPa4nMupudtuo03ZhOl+iguPbLUe0bK/1LruocnDBTZc5R3Vjp/z2LvzweS/Lrc/zy23l 4wK+Pw8OmuP2u89PNNKbqS+cO9nm8Nf3E66En0kT35dY7iXrM2v//ZDms763Z3q13xa5KiKg xFKckWioxVxUnAgAPeFmrSADAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrPLMWRmVeSWpSXmKPExsVy+t/xe7omkovjDCY9Z7TYOGM9q8XUnniL G7/aWC3WHrnLbvGmrZHRYsHkJ6wW22YtZ7P4tmUbo8XbvZ3sDpwesxsusnjMm3WCxWPnrLvs Hmfv7GD06NuyitFj/ZarLB6bT1cHsEfp2RTll5akKmTkF5fYKkUbWhjpGVpa6BmZWOoZGpvH WhmZKunb2aSk5mSWpRbp2yXoZTzatIet4DlrxZlz59gbGO+zdDFyckgImEic3b2CqYuRi0NI YCmjxMcTj9i7GDmAElIS81uUIGqEJf5c62KDqPnEKNHVfI8dJMEmYCjRe7SPEcQWEQiReHH0 CtggZoEGRol7R+ewgiSEBewknm34ATaURUBV4tIjH5Awr4C1ROvcu1BHyEus3nCAGcTmFLCR aDz7CiwuBFSzbeZzlgmMfAsYGVYxiqSWFuem5xYb6hUn5haX5qXrJefnbmIEBva2Yz8372C8 tDH4EKMAB6MSD2/EkUVxQqyJZcWVuYcYJTiYlUR4Y0qAQrwpiZVVqUX58UWlOanFhxhNgW6a yCwlmpwPjLq8knhDU0NzC0tDc2NzYzMLJXHeDoGDMUIC6YklqdmpqQWpRTB9TBycUg2MWXmu O9e98phr9fPoc/NZO8/ErbFTe55gorS1UOLMat9LC09+uht2Z5fmMv5M9fyz9xzvzDXM3u5b Gtfv17J+eVtGxBlfh38HPkzfcFH5i/TL2btqZ77VbnqU9WKGiM2lBaIrfxzY9Pnct6YFMmGn y5/fsDpWO2XL2T+z/i7T2CHH9PLG7s+nddSVWIozEg21mIuKEwELnx7EggIAAA== X-CMS-MailID: 20200424165204eucas1p2e95cb0680a72ef2547b1e44b137905b4 X-Msg-Generator: CA X-RootMTR: 20200424165204eucas1p2e95cb0680a72ef2547b1e44b137905b4 X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20200424165204eucas1p2e95cb0680a72ef2547b1e44b137905b4 References: <20200424165012.31915-1-s.nawrocki@samsung.com> X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.30rc1 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.2 at phobos.denx.de X-Virus-Status: Clean From: Marek Szyprowski Remove the overlap between DRAM and device's IO area. Signed-off-by: Marek Szyprowski Reviewed-by: Nicolas Saenz Julienne --- Changes since RFC: - none. --- arch/arm/mach-bcm283x/init.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-bcm283x/init.c b/arch/arm/mach-bcm283x/init.c index 9966d6c..4295356 100644 --- a/arch/arm/mach-bcm283x/init.c +++ b/arch/arm/mach-bcm283x/init.c @@ -38,7 +38,7 @@ static struct mm_region bcm2711_mem_map[] = { { .virt = 0x00000000UL, .phys = 0x00000000UL, - .size = 0xfe000000UL, + .size = 0xfc000000UL, .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_INNER_SHARE }, { From patchwork Fri Apr 24 16:50:07 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sylwester Nawrocki X-Patchwork-Id: 1276518 X-Patchwork-Delegate: matthias.bgg@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; 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Fri, 24 Apr 2020 16:52:06 +0000 (GMT) Received: from eusmgms2.samsung.com (unknown [182.198.249.180]) by eusmtrp2.samsung.com (KnoxPortal) with ESMTP id 20200424165206eusmtrp2bc313e71c556d9f2a006313fddf52a9a~Iz5lZ7GDE3157231572eusmtrp2J; Fri, 24 Apr 2020 16:52:06 +0000 (GMT) X-AuditID: cbfec7f2-f0bff7000001ef66-d3-5ea319365d75 Received: from eusmtip2.samsung.com ( [203.254.199.222]) by eusmgms2.samsung.com (EUCPMTA) with SMTP id 3D.1C.07950.63913AE5; Fri, 24 Apr 2020 17:52:06 +0100 (BST) Received: from AMDC3061.digital.local (unknown [106.120.51.75]) by eusmtip2.samsung.com (KnoxPortal) with ESMTPA id 20200424165205eusmtip2143bf21d7a3be95e1415d7c7dff34a35~Iz5k5LlNZ1549415494eusmtip2Z; Fri, 24 Apr 2020 16:52:05 +0000 (GMT) From: Sylwester Nawrocki To: u-boot@lists.denx.de, mbrugger@suse.com, marex@denx.de, bmeng.cn@gmail.com Cc: sjg@chromium.org, nsaenzjulienne@suse.de, jh80.chung@samsung.com, m.szyprowski@samsung.com, b.zolnierkie@samsung.com Subject: [PATCH v1 05/10] rpi4: add a mapping for the PCIe XHCI controller MMIO registers (ARM 64bit) Date: Fri, 24 Apr 2020 18:50:07 +0200 Message-Id: <20200424165012.31915-6-s.nawrocki@samsung.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200424165012.31915-1-s.nawrocki@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFuphleLIzCtJLcpLzFFi42LZduzneV0zycVxBs8OqFhsnLGe1WJqT7zF jV9trBZrj9xlt3jT1shosWDyE1aLbbOWs1l827KN0eLt3k52B06P2Q0XWTzmzTrB4rFz1l12 j7N3djB69G1ZxeixfstVFo/Np6sD2KO4bFJSczLLUov07RK4MvZ8iyp4zV8xfeoepgbGjzxd jJwcEgImErMnLWXvYuTiEBJYwSjxb8sMFgjnC6PEgQeTmCGcz4wSR56fZIZpeXP2FVTLckaJ 9oVbWeFapmybywhSxSZgKNF7tA/MFhEIkLj2cxqYzSxQJXG9/SkLiC0skC4x88pZVhCbRUBV Yum2C0BTOTh4BawlLj6UgVgmL7F6wwGwxZwCNhKNZ1+BnSch0M0ucWHJJRaQegkBF4ktf0wh 6oUlXh3fwg5hy0j83zmfCaK+mVGiZ/dtdghnAqPE/eMLGCGqrCXunPvFBjKIWUBTYv0ufYiw o8TXWesZIebzSdx4KwhxPp/EpG3TmSHCvBIdbUIQ1SoSv1dNZ4KwpSS6n/yHusxD4uVRK0jo 9DNKrDr6k30Co/wshF0LGBlXMYqnlhbnpqcWG+allusVJ+YWl+al6yXn525iBKaR0/+Of9rB +PVS0iFGAQ5GJR7eiCOL4oRYE8uKK3MPMUpwMCuJ8MaUAIV4UxIrq1KL8uOLSnNSiw8xSnOw KInzGi96GSskkJ5YkpqdmlqQWgSTZeLglGpg5NobL/Qj+OkRJnX3y0xihU07DjoX9NX6xYQE Sr76ffzsbuV5c205RNZ9a3rLeFSB98Dr07P3/mm+2aqqXOApff5JsMVOQ63orhmOzA0123ti 46u+Sc+6uMZ0T9kzVXPlzbOf3Crrfyc3fz/rLZHrN/ZdtFxsr7U0p/bIWfbnG71y1t2K33f6 qBJLcUaioRZzUXEiAII98JgfAwAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrHLMWRmVeSWpSXmKPExsVy+t/xe7pmkovjDL5u5rTYOGM9q8XUnniL G7/aWC3WHrnLbvGmrZHRYsHkJ6wW22YtZ7P4tmUbo8XbvZ3sDpwesxsusnjMm3WCxWPnrLvs Hmfv7GD06NuyitFj/ZarLB6bT1cHsEfp2RTll5akKmTkF5fYKkUbWhjpGVpa6BmZWOoZGpvH WhmZKunb2aSk5mSWpRbp2yXoZez5FlXwmr9i+tQ9TA2MH3m6GDk5JARMJN6cfcXexcjFISSw lFFi69+rTF2MHEAJKYn5LUoQNcISf651sUHUfGKU2DW5jxUkwSZgKNF7tI8RxBYRCJF4cfQK E0gRs0ADo8S9o3PAioQFUiVWff/FDmKzCKhKLN12gR1kAa+AtcTFhzIQC+QlVm84wAxicwrY SDSefcUCYgsBlWyb+ZxlAiPfAkaGVYwiqaXFuem5xUZ6xYm5xaV56XrJ+bmbGIFhve3Yzy07 GLveBR9iFOBgVOLhjTiyKE6INbGsuDL3EKMEB7OSCG9MCVCINyWxsiq1KD++qDQntfgQoynQ TROZpUST84Exl1cSb2hqaG5haWhubG5sZqEkztshcDBGSCA9sSQ1OzW1ILUIpo+Jg1OqgbH9 nEVptbJV/rQ8hZkTFP4HerPcqM3wmPb0tf66olquZwftb+60r/hjcN01JSa0LHHXlBO1se1L z1wr59Aq61gl/3OP8rZdjZ85d1RnV+pO0zd6qMbfJ2WsO4s1aboMLxOH5NSq/K479qv3Jjdc X5IvO4Ot6UqywoyN0XbdBwq0Ok4+zY63U2Ipzkg01GIuKk4EAE74c4aBAgAA X-CMS-MailID: 20200424165206eucas1p2b1977ef1a7b0b81ff934efe8f8154299 X-Msg-Generator: CA X-RootMTR: 20200424165206eucas1p2b1977ef1a7b0b81ff934efe8f8154299 X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20200424165206eucas1p2b1977ef1a7b0b81ff934efe8f8154299 References: <20200424165012.31915-1-s.nawrocki@samsung.com> X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.30rc1 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.2 at phobos.denx.de X-Virus-Status: Clean From: Marek Szyprowski Create a non-cacheable mapping for the 0x600000000 physical memory region, where MMIO registers for the PCIe XHCI controller are instantiated by the PCIe bridge. Signed-off-by: Marek Szyprowski Reviewed-by: Nicolas Saenz Julienne --- Changes since RFC: - none. --- arch/arm/mach-bcm283x/init.c | 18 +++++++++++++++--- 1 file changed, 15 insertions(+), 3 deletions(-) diff --git a/arch/arm/mach-bcm283x/init.c b/arch/arm/mach-bcm283x/init.c index 4295356..6a748da 100644 --- a/arch/arm/mach-bcm283x/init.c +++ b/arch/arm/mach-bcm283x/init.c @@ -11,10 +11,15 @@ #include #include +#define BCM2711_RPI4_PCIE_XHCI_MMIO_PHYS 0x600000000UL +#define BCM2711_RPI4_PCIE_XHCI_MMIO_SIZE 0x800000UL + #ifdef CONFIG_ARM64 #include -static struct mm_region bcm283x_mem_map[] = { +#define MAX_MAP_MAX_ENTRIES (4) + +static struct mm_region bcm283x_mem_map[MAX_MAP_MAX_ENTRIES] = { { .virt = 0x00000000UL, .phys = 0x00000000UL, @@ -34,7 +39,7 @@ static struct mm_region bcm283x_mem_map[] = { } }; -static struct mm_region bcm2711_mem_map[] = { +static struct mm_region bcm2711_mem_map[MAX_MAP_MAX_ENTRIES] = { { .virt = 0x00000000UL, .phys = 0x00000000UL, @@ -49,6 +54,13 @@ static struct mm_region bcm2711_mem_map[] = { PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, { + .virt = BCM2711_RPI4_PCIE_XHCI_MMIO_PHYS, + .phys = BCM2711_RPI4_PCIE_XHCI_MMIO_PHYS, + .size = BCM2711_RPI4_PCIE_XHCI_MMIO_SIZE, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { /* List terminator */ 0, } @@ -71,7 +83,7 @@ static void _rpi_update_mem_map(struct mm_region *pd) { int i; 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Fri, 24 Apr 2020 16:52:07 +0000 (GMT) From: Sylwester Nawrocki To: u-boot@lists.denx.de, mbrugger@suse.com, marex@denx.de, bmeng.cn@gmail.com Cc: sjg@chromium.org, nsaenzjulienne@suse.de, jh80.chung@samsung.com, m.szyprowski@samsung.com, b.zolnierkie@samsung.com Subject: [PATCH v1 06/10] rpi4: add a mapping for the PCIe XHCI controller MMIO registers (ARM 32bit) Date: Fri, 24 Apr 2020 18:50:08 +0200 Message-Id: <20200424165012.31915-7-s.nawrocki@samsung.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200424165012.31915-1-s.nawrocki@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFupileLIzCtJLcpLzFFi42LZduzneV1LycVxBuumcllsnLGe1WJqT7zF jV9trBZrj9xlt3jT1shosWDyE1aLbbOWs1l827KN0eLt3k52B06P2Q0XWTzmzTrB4rFz1l12 j7N3djB69G1ZxeixfstVFo/Np6sD2KO4bFJSczLLUov07RK4Mq4sUiu4Llnx6fRe5gbGBaJd jBwcEgImEt8WRHYxcnEICaxglFgw5wwLhPOFUeL+5g/sXYycQM5nRonerdogNkjDsY17mSGK ljNK7Dq4mhWuY+H0zawgVWwChhK9R/sYQWwRgQCJaz+ngdnMAlUS19ufsoDYwgLpEq1Hl4LF WQRUJRZsfwhm8wpYS/xtOsQKsU1eYvWGA8wgNqeAjUTj2Vdg50kIdLNL/D/QxQbxg4vEvSXh EPXCEq+Ob2GHsGUkTk/ugapvZpTo2X2bHcKZAPTb8QWMEFXWEnfO/QIbxCygKbF+lz7ETEeJ b8d0IEw+iRtvBSHO55OYtG06M0SYV6KjTQhihorE71XTmSBsKYnuJ/9ZIEo8JDa3x0FCp59R Ys7S6UwTGOVnIaxawMi4ilE8tbQ4Nz212DgvtVyvODG3uDQvXS85P3cTIzCFnP53/OsOxn1/ kg4xCnAwKvHwRhxZFCfEmlhWXJl7iFGCg1lJhDemBCjEm5JYWZValB9fVJqTWnyIUZqDRUmc 13jRy1ghgfTEktTs1NSC1CKYLBMHp1QD46aLfYeY7TyTnrmzFOn8s4t64nBh7XefvK7SzrC9 d+48OOcetXbG1knm0z+su1K4cEYFk0uowKujWaaTjl2bbLdgilHUyd+LZ08KXXQouHvl5vif Dbc3qV964OOWIsslW6s1XebHmiCrD0/MPmntnZ2295FSVE1cn8+bp3euHi/RvP+jtaLwb6gS S3FGoqEWc1FxIgAUAtMEHQMAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrPLMWRmVeSWpSXmKPExsVy+t/xe7oWkovjDHq2yFhsnLGe1WJqT7zF jV9trBZrj9xlt3jT1shosWDyE1aLbbOWs1l827KN0eLt3k52B06P2Q0XWTzmzTrB4rFz1l12 j7N3djB69G1ZxeixfstVFo/Np6sD2KP0bIryS0tSFTLyi0tslaINLYz0DC0t9IxMLPUMjc1j rYxMlfTtbFJSczLLUov07RL0Mq4sUiu4Llnx6fRe5gbGBaJdjJwcEgImEsc27mXuYuTiEBJY yihxZUoLaxcjB1BCSmJ+ixJEjbDEn2tdbBA1nxgl1m38zwSSYBMwlOg92scIYosIhEi8OHqF CaSIWaCBUeLe0TmsIAlhgVSJexM+ghWxCKhKLNj+EMzmFbCW+Nt0iBVig7zE6g0HmEFsTgEb icazr1hAbCGgmm0zn7NMYORbwMiwilEktbQ4Nz232FCvODG3uDQvXS85P3cTIzCwtx37uXkH 46WNwYcYBTgYlXh4I44sihNiTSwrrsw9xCjBwawkwhtTAhTiTUmsrEotyo8vKs1JLT7EaAp0 1ERmKdHkfGDU5ZXEG5oamltYGpobmxubWSiJ83YIHIwREkhPLEnNTk0tSC2C6WPi4JRqYJx8 eZcGv/D8Xy/v1uZJqczekrFe6WYJy3OVpeHBq9+LHfTdNovPqEqSvdsnuLe29eJshblS9zk3 HK+zamyUcKzLE9q1InOt34eGJ/NlKyf+Wxy72kurmm9jiU9sneOxkk2dS7a3b147y9znCevt V6dPZxy0W5T8ymdqLevUyLW5ReZdLfoFd5VYijMSDbWYi4oTAWa/WtmCAgAA X-CMS-MailID: 20200424165208eucas1p23af382ac8bdacf0bc94b2b0f027e4541 X-Msg-Generator: CA X-RootMTR: 20200424165208eucas1p23af382ac8bdacf0bc94b2b0f027e4541 X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20200424165208eucas1p23af382ac8bdacf0bc94b2b0f027e4541 References: <20200424165012.31915-1-s.nawrocki@samsung.com> X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.30rc1 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.2 at phobos.denx.de X-Virus-Status: Clean From: Marek Szyprowski Create a non-cacheable mapping for the 0x600000000 physical memory region, where MMIO registers for the PCIe XHCI controller are instantiated by the PCIe bridge. Due to 32bit limit in the CPU virtual address space in ARM 32bit mode, this region is mapped at 0xff800000 CPU virtual address. Signed-off-by: Marek Szyprowski --- Changes since RFC: - none. --- arch/arm/mach-bcm283x/Kconfig | 1 + arch/arm/mach-bcm283x/include/mach/base.h | 7 +++++ arch/arm/mach-bcm283x/init.c | 52 +++++++++++++++++++++++++++++++ 3 files changed, 60 insertions(+) diff --git a/arch/arm/mach-bcm283x/Kconfig b/arch/arm/mach-bcm283x/Kconfig index 00419bf..bcb7f1d 100644 --- a/arch/arm/mach-bcm283x/Kconfig +++ b/arch/arm/mach-bcm283x/Kconfig @@ -36,6 +36,7 @@ config BCM2711_32B select BCM2711 select ARMV7_LPAE select CPU_V7A + select PHYS_64BIT config BCM2711_64B bool "Broadcom BCM2711 SoC 64-bit support" diff --git a/arch/arm/mach-bcm283x/include/mach/base.h b/arch/arm/mach-bcm283x/include/mach/base.h index c4ae398..1d10dc9 100644 --- a/arch/arm/mach-bcm283x/include/mach/base.h +++ b/arch/arm/mach-bcm283x/include/mach/base.h @@ -6,6 +6,13 @@ #ifndef _BCM283x_BASE_H_ #define _BCM283x_BASE_H_ +#include + extern unsigned long rpi_bcm283x_base; +#ifdef CONFIG_ARMV7_LPAE +extern void *rpi4_phys_to_virt(phys_addr_t paddr); +#define phys_to_virt(x) rpi4_phys_to_virt(x) +#endif + #endif diff --git a/arch/arm/mach-bcm283x/init.c b/arch/arm/mach-bcm283x/init.c index 6a748da..5d0d160 100644 --- a/arch/arm/mach-bcm283x/init.c +++ b/arch/arm/mach-bcm283x/init.c @@ -145,6 +145,58 @@ int mach_cpu_init(void) } #ifdef CONFIG_ARMV7_LPAE + +#define BCM2711_RPI4_PCIE_XHCI_MMIO_VIRT 0xff800000UL + +void *rpi4_phys_to_virt(phys_addr_t paddr) +{ + if (paddr >= BCM2711_RPI4_PCIE_XHCI_MMIO_PHYS) + paddr = paddr - BCM2711_RPI4_PCIE_XHCI_MMIO_PHYS + + BCM2711_RPI4_PCIE_XHCI_MMIO_VIRT; + return (void *)(unsigned long)paddr; +} + +static void set_section_phys(unsigned int section, phys_addr_t phys, + enum dcache_option option) +{ + u64 *page_table = (u64 *)gd->arch.tlb_addr; + /* Need to set the access flag to not fault */ + u64 value = TTB_SECT_AP | TTB_SECT_AF; + + /* Add the page offset */ + value |= (phys); + + /* Add caching bits */ + value |= option; + + /* Set PTE */ + page_table[section] = value; +} + +static void rpi4_create_pcie_xhci_mapping(void) +{ + unsigned sect = BCM2711_RPI4_PCIE_XHCI_MMIO_VIRT >> MMU_SECTION_SHIFT; + phys_addr_t phys_addr = BCM2711_RPI4_PCIE_XHCI_MMIO_PHYS; + unsigned int size = BCM2711_RPI4_PCIE_XHCI_MMIO_SIZE; + + while (size) { + set_section_phys(sect, phys_addr, DCACHE_OFF); + sect++; + phys_addr += MMU_SECTION_SIZE; + size -= MMU_SECTION_SIZE; + } +} + +void arm_init_domains(void) +{ + /* + * Hijack this function to prepare a mappings for the PCIe MMIO + * region for the XHCI controller on RPi4 board. + * This code is called before enabling the MMU in ARM 32bit mode. + */ + rpi4_create_pcie_xhci_mapping(); +} + void enable_caches(void) { dcache_enable(); From patchwork Fri Apr 24 16:50:09 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sylwester Nawrocki X-Patchwork-Id: 1276520 X-Patchwork-Delegate: matthias.bgg@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; 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Date: Fri, 24 Apr 2020 18:50:09 +0200 Message-Id: <20200424165012.31915-8-s.nawrocki@samsung.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200424165012.31915-1-s.nawrocki@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprGKsWRmVeSWpSXmKPExsWy7djPc7pWkovjDG43SlhsnLGe1WJqT7zF jV9trBZrj9xlt3jT1shosWDyE1aLbbOWs1kcftPOavFtyzZGi7d7O9kduDxmN1xk8Zg36wSL x85Zd9k9zt7ZwejRt2UVo8f6LVdZPDafrg5gj+KySUnNySxLLdK3S+DK+DRxFmtBh3BFz+4L bA2Ml/m7GDk5JARMJCZ3NjF1MXJxCAmsYJSYeOsKG4TzhVHiePsrRgjnM6PEid5pzDAtv6Y+ YYFILGeUuLl4LTNcy99fm8Cq2AQMJXqP9jGC2CICARLXfk4DG8UssJJR4lvfObCEsEC5xKu1 7WA2i4CqxLm7y9lBbF4Ba4l1z2dCrZOXWL3hAJjNKWAj0Xj2FdhqCYHJ7BInDh1ghyhykbh7 9C8LhC0s8er4Fqi4jMTpyT1QDc2MEj27b7NDOBMYJe4fX8AIUWUtcefcL6C/OYDu05RYv0sf IuwosXDfPlaQsIQAn8SNt4IgYWYgc9K26cwQYV6JjjYhiGoVid+rpjNB2FIS3U/+Q53jIXF6 51NooPYzSuyZv4t5AqP8LIRlCxgZVzGKp5YW56anFhvmpZbrFSfmFpfmpesl5+duYgSmltP/ jn/awfj1UtIhRgEORiUe3ogji+KEWBPLiitzDzFKcDArifDGlACFeFMSK6tSi/Lji0pzUosP MUpzsCiJ8xovehkrJJCeWJKanZpakFoEk2Xi4JRqYNTii+MO/M27M/B1YZFtvtkHaVnRGRKr xYPXZNxqvWm24NYbFd85M3SXbsxYl+mYIX10+uq6GZ2nLLrvep5rkw6rl2oqNvWRXj8z1lRQ 7uw5N1/tyLgpT+4vMNPbx6Tzs+ZhyNzimu0f5+iv15vA47lpzmvruNZpfRVnjrQe25GXX6DE a6ZWpcRSnJFoqMVcVJwIAOV1idEpAwAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrKLMWRmVeSWpSXmKPExsVy+t/xe7pWkovjDKa8YbbYOGM9q8XUnniL G7/aWC3WHrnLbvGmrZHRYsHkJ6wW22YtZ7M4/Kad1eLblm2MFm/3drI7cHnMbrjI4jFv1gkW j52z7rJ7nL2zg9Gjb8sqRo/1W66yeGw+XR3AHqVnU5RfWpKqkJFfXGKrFG1oYaRnaGmhZ2Ri qWdobB5rZWSqpG9nk5Kak1mWWqRvl6CX8WniLNaCDuGKnt0X2BoYL/N3MXJySAiYSPya+oSl i5GLQ0hgKaPEuus3WLsYOYASUhLzW5QgaoQl/lzrYoOo+cQo8eDdFWaQBJuAoUTv0T5GEFtE IETixdErTCBFzALrGSU23JjJBpIQFiiVWLXiFpjNIqAqce7ucnYQm1fAWmLd85nMEBvkJVZv OABmcwrYSDSefcUCYgsB1Wyb+ZxlAiPfAkaGVYwiqaXFuem5xYZ6xYm5xaV56XrJ+bmbGIFB vu3Yz807GC9tDD7EKMDBqMTDG3FkUZwQa2JZcWXuIUYJDmYlEd6YEqAQb0piZVVqUX58UWlO avEhRlOgoyYyS4km5wMjMK8k3tDU0NzC0tDc2NzYzEJJnLdD4GCMkEB6YklqdmpqQWoRTB8T B6dUA2MVd8jXY7Of3rzleeOc8Hdn6WId79B9+h3hb+7vD5uzVv3KlB3+yq1Jxssm6NgomJbz 7M0viQjWfnCLOfBxfbLx6n09Rju3vFzX4f5hovxfuzNuBcpR3CbRfCZ9XB/VHGe68/TFT9Bk m7uceQ2L0+2E5fbxu89tSfeRynyjrGof3frKuveggBJLcUaioRZzUXEiAOzJFh+IAgAA X-CMS-MailID: 20200424165210eucas1p2f371c116aa8354550009512c6d55cd52 X-Msg-Generator: CA X-RootMTR: 20200424165210eucas1p2f371c116aa8354550009512c6d55cd52 X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20200424165210eucas1p2f371c116aa8354550009512c6d55cd52 References: <20200424165012.31915-1-s.nawrocki@samsung.com> X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.30rc1 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.2 at phobos.denx.de X-Virus-Status: Clean From: Nicolas Saenz Julienne Imports Al Viro's original Linux commit 00b0c9b82663a, which contains an in depth explanation and two fixes from Johannes Berg: e7d4a95da86e0 "bitfield: fix *_encode_bits()", 37a3862e12382 "bitfield: add u8 helpers". Signed-off-by: Nicolas Saenz Julienne Signed-off-by: Sylwester Nawrocki --- Changes since RFC: - new patch. --- include/linux/bitfield.h | 46 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 46 insertions(+) diff --git a/include/linux/bitfield.h b/include/linux/bitfield.h index 8b9d6ff..4964213 100644 --- a/include/linux/bitfield.h +++ b/include/linux/bitfield.h @@ -103,4 +103,50 @@ (typeof(_mask))(((_reg) & (_mask)) >> __bf_shf(_mask)); \ }) +extern void __compiletime_error("value doesn't fit into mask") +__field_overflow(void); +extern void __compiletime_error("bad bitfield mask") +__bad_mask(void); +static __always_inline u64 field_multiplier(u64 field) +{ + if ((field | (field - 1)) & ((field | (field - 1)) + 1)) + __bad_mask(); + return field & -field; +} +static __always_inline u64 field_mask(u64 field) +{ + return field / field_multiplier(field); +} +#define ____MAKE_OP(type,base,to,from) \ +static __always_inline __##type type##_encode_bits(base v, base field) \ +{ \ + if (__builtin_constant_p(v) && (v & ~field_mask(field))) \ + __field_overflow(); \ + return to((v & field_mask(field)) * field_multiplier(field)); \ +} \ +static __always_inline __##type type##_replace_bits(__##type old, \ + base val, base field) \ +{ \ + return (old & ~to(field)) | type##_encode_bits(val, field); \ +} \ +static __always_inline void type##p_replace_bits(__##type *p, \ + base val, base field) \ +{ \ + *p = (*p & ~to(field)) | type##_encode_bits(val, field); \ +} \ +static __always_inline base type##_get_bits(__##type v, base field) \ +{ \ + return (from(v) & field)/field_multiplier(field); \ +} +#define __MAKE_OP(size) \ + ____MAKE_OP(le##size,u##size,cpu_to_le##size,le##size##_to_cpu) \ + ____MAKE_OP(be##size,u##size,cpu_to_be##size,be##size##_to_cpu) \ + ____MAKE_OP(u##size,u##size,,) +____MAKE_OP(u8,u8,,) +__MAKE_OP(16) +__MAKE_OP(32) +__MAKE_OP(64) +#undef __MAKE_OP +#undef ____MAKE_OP + #endif From patchwork Fri Apr 24 16:50:10 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sylwester Nawrocki X-Patchwork-Id: 1276521 X-Patchwork-Delegate: matthias.bgg@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; 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Fri, 24 Apr 2020 16:52:12 +0000 (GMT) From: Sylwester Nawrocki To: u-boot@lists.denx.de, mbrugger@suse.com, marex@denx.de, bmeng.cn@gmail.com Cc: sjg@chromium.org, nsaenzjulienne@suse.de, jh80.chung@samsung.com, m.szyprowski@samsung.com, b.zolnierkie@samsung.com, Sylwester Nawrocki Subject: [PATCH v1 08/10] pci: Add some PCI Express capability register offset definitions Date: Fri, 24 Apr 2020 18:50:10 +0200 Message-Id: <20200424165012.31915-9-s.nawrocki@samsung.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200424165012.31915-1-s.nawrocki@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprEKsWRmVeSWpSXmKPExsWy7djPc7o2kovjDK5Pt7TYOGM9q8XUnniL G7/aWC3WHrnLbvGmrZHRYsHkJ6wW22YtZ7M4/Kad1eLblm2MFm/3drI7cHnMbrjI4jFv1gkW j52z7rJ7nL2zg9Gjb8sqRo/1W66yeGw+XR3AHsVlk5Kak1mWWqRvl8CV0fHxNWPBYe6KyQ// sjQw7uDsYuTkkBAwkdjfc5Kli5GLQ0hgBaPEgsZfUM4XRomf27azQzifGSU2Pf7MDtNy/Npv NojEckaJ08vvIrTMujqPFaSKTcBQovdoHyOILSIQIHHt5zRGkCJmgZWMEt/6zoElhAViJN6f 3MrUxcjBwSKgKjH9pzyIyStgLfFlQg3EMnmJ1RsOMIPYnAI2Eo1nX4HtkhCYzC6x5fJ8VpB6 CQEXifWPTSHqhSVeHd8CdaiMxOnJPVD1zYwSPbtvs0M4Exgl7h9fwAhRZS1x59wvNpBBzAKa Eut36UOEHSVu73vMAjGfT+LGW0GQMDOQOWnbdGaIMK9ER5sQRLWKxO9V05kgbCmJ7if/oTo9 JDb8D4SETj+jxNsHM1knMMrPQti1gJFxFaN4amlxbnpqsVFearlecWJucWleul5yfu4mRmBK Of3v+JcdjLv+JB1iFOBgVOLhZTi0KE6INbGsuDL3EKMEB7OSCG9MCVCINyWxsiq1KD++qDQn tfgQozQHi5I4r/Gil7FCAumJJanZqakFqUUwWSYOTqkGxu5nU8ymGDDMrVi0SWF1xno/k88T mfxaS5YJLBedHOe96YXDx55LjzMV+gqD/usa1beU6KfF2pfK6OnNSdn29vOF1VF9W1Y/riyd 17Qop4Lpk8xJvjnHrK21dGoVfYt3fTFcXvxi3c+s6HD782uYq5bzCmmcOJNyJy2zv3z/PYEf Nq2sJb+PKrEUZyQaajEXFScCAFfMu5QlAwAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrMLMWRmVeSWpSXmKPExsVy+t/xe7o2kovjDL5cVbfYOGM9q8XUnniL G7/aWC3WHrnLbvGmrZHRYsHkJ6wW22YtZ7M4/Kad1eLblm2MFm/3drI7cHnMbrjI4jFv1gkW j52z7rJ7nL2zg9Gjb8sqRo/1W66yeGw+XR3AHqVnU5RfWpKqkJFfXGKrFG1oYaRnaGmhZ2Ri qWdobB5rZWSqpG9nk5Kak1mWWqRvl6CX0fHxNWPBYe6KyQ//sjQw7uDsYuTkkBAwkTh+7Tdb FyMXh5DAUkaJU7PmsnQxcgAlpCTmtyhB1AhL/LnWBVXziVFiyveZ7CAJNgFDid6jfYwgtohA iMSLo1eYQIqYBdYzSmy4MZMNJCEsECWx/OpEsKEsAqoS03/Kg5i8AtYSXybUQMyXl1i94QAz iM0pYCPRePYVC4gtBFSybeZzlgmMfAsYGVYxiqSWFuem5xYb6hUn5haX5qXrJefnbmIEBvi2 Yz8372C8tDH4EKMAB6MSD2/EkUVxQqyJZcWVuYcYJTiYlUR4Y0qAQrwpiZVVqUX58UWlOanF hxhNgU6ayCwlmpwPjL68knhDU0NzC0tDc2NzYzMLJXHeDoGDMUIC6YklqdmpqQWpRTB9TByc Ug2MPfOu7bCerVkndjLgkH6L058zm/WyJ7oa9Z9dduzR1x6B6UnMuhzb7jlv0D3bfy/mwin1 pScd9BX+FB3/sqeTYSFHWeWR3k1/Du8SCvEqbQjs33qi92b67xrlZev1tnnOv3JkbsLNoDOr vvp37Zv04sLbwzP155n4Ksk2Zy8/t+zIOkPL3dOlNZVYijMSDbWYi4oTASDD5GWGAgAA X-CMS-MailID: 20200424165212eucas1p20c518701a911a7aaeed857330a7bc030 X-Msg-Generator: CA X-RootMTR: 20200424165212eucas1p20c518701a911a7aaeed857330a7bc030 X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20200424165212eucas1p20c518701a911a7aaeed857330a7bc030 References: <20200424165012.31915-1-s.nawrocki@samsung.com> X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.30rc1 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.2 at phobos.denx.de X-Virus-Status: Clean Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Reviewed-by: Bin Meng Signed-off-by: Sylwester Nawrocki Reviewed-by: Nicolas Saenz Julienne --- Changes since RFC: - ensure the entries are added in order, sorted by ascending address values. --- include/pci.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/include/pci.h b/include/pci.h index 5bf91a4..5307478 100644 --- a/include/pci.h +++ b/include/pci.h @@ -479,11 +479,17 @@ #define PCI_EXP_DEVCTL 8 /* Device Control */ #define PCI_EXP_DEVCTL_BCR_FLR 0x8000 /* Bridge Configuration Retry / FLR */ #define PCI_EXP_LNKCAP 12 /* Link Capabilities */ +#define PCI_EXP_LNKCAP_SLS 0x0000000f /* Supported Link Speeds */ +#define PCI_EXP_LNKCAP_MLW 0x000003f0 /* Maximum Link Width */ #define PCI_EXP_LNKCAP_DLLLARC 0x00100000 /* Data Link Layer Link Active Reporting Capable */ #define PCI_EXP_LNKSTA 18 /* Link Status */ +#define PCI_EXP_LNKSTA_CLS 0x000f /* Current Link Speed */ +#define PCI_EXP_LNKSTA_NLW 0x03f0 /* Negotiated Link Width */ +#define PCI_EXP_LNKSTA_NLW_SHIFT 4 /* start of NLW mask in link status */ #define PCI_EXP_LNKSTA_DLLLA 0x2000 /* Data Link Layer Link Active */ #define PCI_EXP_SLTCAP 20 /* Slot Capabilities */ #define PCI_EXP_SLTCAP_PSN 0xfff80000 /* Physical Slot Number */ +#define PCI_EXP_LNKCTL2 48 /* Link Control 2 */ /* Include the ID list */ From patchwork Fri Apr 24 16:50:11 2020 Content-Type: text/plain; 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Fri, 24 Apr 2020 16:52:37 +0000 (GMT) From: Sylwester Nawrocki To: u-boot@lists.denx.de, mbrugger@suse.com, marex@denx.de, bmeng.cn@gmail.com Cc: sjg@chromium.org, nsaenzjulienne@suse.de, jh80.chung@samsung.com, m.szyprowski@samsung.com, b.zolnierkie@samsung.com, Sylwester Nawrocki Subject: [PATCH v1 09/10] pci: Add driver for Broadcom STB PCIe controller Date: Fri, 24 Apr 2020 18:50:11 +0200 Message-Id: <20200424165012.31915-10-s.nawrocki@samsung.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200424165012.31915-1-s.nawrocki@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA0VSa0hTYRjuc+fsHEer0zR8m5ExkshQs4QOKM3I8uCfosAfXlt6mKabtnnt 6gVmqXlNJ6vMW5lGLG0sWwhDLYMxoygvqdSPGWlTxMtADW3zTPr3XN6H93k/PpInqsfFZJoy m1UpZRkSvgAzflj9FBizry3x2IztAN3dqMfp+ookemxNg9MvB6cI2q4pQnRznQ2njboOPj1g L8Vph8GI6Lm+e0SEgHlY+BljmnQfMeatbopgrJO9iKk0dCFGb/iGMa8tNy4QsYLwFDYjLZdV BZ+6LEhdeWL1yDK3ofyWSSO/EHWWojLkSQIVCkXtb/hlSECKqOcIftVsYBxZRtBeOYhzZAlB 4cg0sR0ZnTS5jQ4E1toyvsvYijy2+bswnwqB++8rt3Z4UxdgZLUBuQI8qhOBo3LYSUjSi4qG gd+3XTMY5Q8rxVVb80IqHMzPij24ZX7w4pWZ58KeTr3IOotxupYAa7kvhyNh1O5w3+MFs0MG d9H9YKmr2DoHqBIEFe8mCI5UI/gx1OxOhMHk8BrfVYhHHQG9KZiTT8OCY5xwyUDtgrG5PS6Z 54S1Ri2Pk4VwVyPipg/BepfWXVkM5bZNd00GTGaN+3mrELTp5/Fq5Kf7v6wZoS7kw+aoFXJW fVzJ5gWpZQp1jlIelJyp6EHOz2LZGFruRaa/V/oRRSLJTuGO/tZEES7LVRco+hGQPIm3MD7b KQlTZAXXWVVmkiong1X3I18Sk/gIT7TOJIgouSybTWfZLFa17XqQnuJCFJRh/JmmCj14Jkza eAtaIuXagHkDnr9ufyA+7x9jmTA0fJ2+VLNQGrU463W42v7oC8QkX3TsjSuXBka1N2kCKGke o024Ixi86bd6djD9ZF/on+6Y3SWxuoGl7EbN5kK8nT1n744YF8l6hVT0U8JXIfX9vhFnW7za c+3oZiaSYOpUWUgAT6WW/QPM3XMjKAMAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrGLMWRmVeSWpSXmKPExsVy+t/xe7qhkovjDC6fsbTYOGM9q8XUnniL G7/aWC3WHrnLbvGmrZHRYsHkJ6wW22YtZ7M4/Kad1eLblm2MFm/3drI7cHnMbrjI4jFv1gkW j52z7rJ7nL2zg9Gjb8sqRo/1W66yeGw+XR3AHqVnU5RfWpKqkJFfXGKrFG1oYaRnaGmhZ2Ri qWdobB5rZWSqpG9nk5Kak1mWWqRvl6CX8XX+WaaCA4sZKxbe2cbWwLiynbGLkZNDQsBE4vqd XaxdjFwcQgJLGSUunNzO1sXIAZSQkpjfogRRIyzx51oXG0TNJ0aJA7OusYEk2AQMJXqP9oEN EhEIkXhx9AoTSBGzwHpGiQ03ZoINEhbwkjj8og6khkVAVeJrUz9YPa+AjcSBZU1MEAvkJVZv OMAMYnMCxRvPvmIBsYUErCW2zXzOMoGRbwEjwypGkdTS4tz03GJDveLE3OLSvHS95PzcTYzA MN927OfmHYyXNgYfYhTgYFTi4Y04sihOiDWxrLgy9xCjBAezkghvTAlQiDclsbIqtSg/vqg0 J7X4EKMp0FETmaVEk/OBMZhXEm9oamhuYWlobmxubGahJM7bIXAwRkggPbEkNTs1tSC1CKaP iYNTqoGx+sE2qajozPZXwu7px7UZZY2OLP/QUnxt4SQnvkSJrb9C3UN/79rLsbHN+avC7o7d jpvmbDNSM/cpeHM7a5Lf37r0hvSnn7e/8M6P6Q47+iG2Mm0628KSmyzedxKjpYyvXzq5u7Rg 1lGW55HbtB1+3erp8vHbXdG0X63XoqPCqUE5apb66YdKLMUZiYZazEXFiQD6mf4FiQIAAA== X-CMS-MailID: 20200424165238eucas1p152fb12730cb0d1450fd7e6d7c0dbdfb3 X-Msg-Generator: CA X-RootMTR: 20200424165238eucas1p152fb12730cb0d1450fd7e6d7c0dbdfb3 X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20200424165238eucas1p152fb12730cb0d1450fd7e6d7c0dbdfb3 References: <20200424165012.31915-1-s.nawrocki@samsung.com> X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.30rc1 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.2 at phobos.denx.de X-Virus-Status: Clean This patch adds basic driver for the Broadcom STB PCIe host controller. The code is based on Linux upstream driver (pcie-brcmstb.c) with MSI handling removed. The inbound access memory region is not currently parsed from dma-ranges DT property and a fixed 4GB region is used. The patch has been tested on RPI4 board, i.e. on BCM2711 SoC with VL805 USB Host Controller. Signed-off-by: Nicolas Saenz Julienne Signed-off-by: Sylwester Nawrocki --- Changes since RFC: - reworked to align with current Linux mainline version and u-boot driver by Nicolas Saenz Julienne --- drivers/pci/Kconfig | 6 + drivers/pci/Makefile | 1 + drivers/pci/pcie_brcmstb.c | 593 +++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 600 insertions(+) create mode 100644 drivers/pci/pcie_brcmstb.c diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig index 437cd9a..056a021 100644 --- a/drivers/pci/Kconfig +++ b/drivers/pci/Kconfig @@ -197,4 +197,10 @@ config PCIE_MEDIATEK Say Y here if you want to enable Gen2 PCIe controller, which could be found on MT7623 SoC family. +config PCI_BRCMSTB + bool "Broadcom STB PCIe controller" + depends on DM_PCI + depends on ARCH_BCM283X + help + Say Y here if you want to enable Broadcom STB PCIe controller support. endif diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile index c051ecc..3e53b1f 100644 --- a/drivers/pci/Makefile +++ b/drivers/pci/Makefile @@ -43,3 +43,4 @@ obj-$(CONFIG_PCI_PHYTIUM) += pcie_phytium.o obj-$(CONFIG_PCIE_INTEL_FPGA) += pcie_intel_fpga.o obj-$(CONFIG_PCI_KEYSTONE) += pcie_dw_ti.o obj-$(CONFIG_PCIE_MEDIATEK) += pcie_mediatek.o +obj-$(CONFIG_PCI_BRCMSTB) += pcie_brcmstb.o diff --git a/drivers/pci/pcie_brcmstb.c b/drivers/pci/pcie_brcmstb.c new file mode 100644 index 0000000..dfe9833 --- /dev/null +++ b/drivers/pci/pcie_brcmstb.c @@ -0,0 +1,593 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Broadcom STB PCIe controller driver + * + * Copyright (C) 2020 Samsung Electronics Co., Ltd. + * + * Based on upstream Linux kernel driver: + * drivers/pci/controller/pcie-brcmstb.c + * Copyright (C) 2009 - 2017 Broadcom + * + * Based driver by Nicolas Saenz Julienne + * Copyright (C) 2020 Nicolas Saenz Julienne + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +/* BRCM_PCIE_CAP_REGS - Offset for the mandatory capability config regs */ +#define BRCM_PCIE_CAP_REGS 0x00ac + +/* Broadcom STB PCIe Register Offsets */ +#define PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1 0x0188 +#define PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR2_MASK 0xc +#define PCIE_RC_CFG_VENDOR_SPCIFIC_REG1_LITTLE_ENDIAN 0x0 + +#define PCIE_RC_CFG_PRIV1_ID_VAL3 0x043c +#define PCIE_RC_CFG_PRIV1_ID_VAL3_CLASS_CODE_MASK 0xffffff + +#define PCIE_RC_DL_MDIO_ADDR 0x1100 +#define PCIE_RC_DL_MDIO_WR_DATA 0x1104 +#define PCIE_RC_DL_MDIO_RD_DATA 0x1108 + +#define PCIE_MISC_MISC_CTRL 0x4008 +#define PCIE_MISC_MISC_CTRL_SCB_ACCESS_EN_MASK 0x1000 +#define PCIE_MISC_MISC_CTRL_CFG_READ_UR_MODE_MASK 0x2000 +#define PCIE_MISC_MISC_CTRL_MAX_BURST_SIZE_MASK 0x300000 +#define PCIE_MISC_MISC_CTRL_MAX_BURST_SIZE_128 0x0 +#define PCIE_MISC_MISC_CTRL_SCB0_SIZE_MASK 0xf8000000 + +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO 0x400c +#define PCIE_MEM_WIN0_LO(win) \ + PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO + ((win) * 4) + +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_HI 0x4010 +#define PCIE_MEM_WIN0_HI(win) \ + PCIE_MISC_CPU_2_PCIE_MEM_WIN0_HI + ((win) * 4) + +#define PCIE_MISC_RC_BAR1_CONFIG_LO 0x402c +#define PCIE_MISC_RC_BAR1_CONFIG_LO_SIZE_MASK 0x1f + +#define PCIE_MISC_RC_BAR2_CONFIG_LO 0x4034 +#define PCIE_MISC_RC_BAR2_CONFIG_LO_SIZE_MASK 0x1f +#define PCIE_MISC_RC_BAR2_CONFIG_HI 0x4038 + +#define PCIE_MISC_RC_BAR3_CONFIG_LO 0x403c +#define PCIE_MISC_RC_BAR3_CONFIG_LO_SIZE_MASK 0x1f + +#define PCIE_MISC_PCIE_STATUS 0x4068 +#define PCIE_MISC_PCIE_STATUS_PCIE_PORT_MASK 0x80 +#define PCIE_MISC_PCIE_STATUS_PCIE_DL_ACTIVE_MASK 0x20 +#define PCIE_MISC_PCIE_STATUS_PCIE_PHYLINKUP_MASK 0x10 +#define PCIE_MISC_PCIE_STATUS_PCIE_LINK_IN_L23_MASK 0x40 + +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT 0x4070 +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_LIMIT_MASK 0xfff00000 +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_BASE_MASK 0xfff0 +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_BASE_HI_SHIFT 12 +#define PCIE_MEM_WIN0_BASE_LIMIT(win) \ + PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT + ((win) * 4) + +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI 0x4080 +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI_BASE_MASK 0xff +#define PCIE_MEM_WIN0_BASE_HI(win) \ + PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI + ((win) * 8) + +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI 0x4084 +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI_LIMIT_MASK 0xff +#define PCIE_MEM_WIN0_LIMIT_HI(win) \ + PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI + ((win) * 8) + +#define PCIE_MISC_HARD_PCIE_HARD_DEBUG 0x4204 +#define PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_MASK 0x2 +#define PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK 0x08000000 + +#define PCIE_MSI_INTR2_CLR 0x4508 +#define PCIE_MSI_INTR2_MASK_SET 0x4510 + +#define PCIE_EXT_CFG_DATA 0x8000 + +#define PCIE_EXT_CFG_INDEX 0x9000 +#define PCIE_EXT_BUSNUM_SHIFT 20 +#define PCIE_EXT_SLOT_SHIFT 15 +#define PCIE_EXT_FUNC_SHIFT 12 + +#define PCIE_RGR1_SW_INIT_1 0x9210 +#define PCIE_RGR1_SW_INIT_1_PERST_MASK 0x1 +#define PCIE_RGR1_SW_INIT_1_INIT_MASK 0x2 + +/* PCIe parameters */ +#define BRCM_NUM_PCIE_OUT_WINS 0x4 + +/* MDIO registers */ +#define MDIO_PORT0 0x0 +#define MDIO_DATA_MASK 0x7fffffff +#define MDIO_PORT_MASK 0xf0000 +#define MDIO_REGAD_MASK 0xffff +#define MDIO_CMD_MASK 0xfff00000 +#define MDIO_CMD_READ 0x1 +#define MDIO_CMD_WRITE 0x0 +#define MDIO_DATA_DONE_MASK 0x80000000 +#define MDIO_RD_DONE(x) (((x) & MDIO_DATA_DONE_MASK) ? 1 : 0) +#define MDIO_WT_DONE(x) (((x) & MDIO_DATA_DONE_MASK) ? 0 : 1) +#define SSC_REGS_ADDR 0x1100 +#define SET_ADDR_OFFSET 0x1f +#define SSC_CNTL_OFFSET 0x2 +#define SSC_CNTL_OVRD_EN_MASK 0x8000 +#define SSC_CNTL_OVRD_VAL_MASK 0x4000 +#define SSC_STATUS_OFFSET 0x1 +#define SSC_STATUS_SSC_MASK 0x400 +#define SSC_STATUS_PLL_LOCK_MASK 0x800 + +struct brcm_pcie { + void __iomem *base; + + int gen; + bool ssc; +}; + +#define msleep(a) udelay((a) * 1000) + +/* + * This is to convert the size of the inbound "BAR" region to the + * non-linear values of PCIE_X_MISC_RC_BAR[123]_CONFIG_LO.SIZE + */ +static int brcm_pcie_encode_ibar_size(u64 size) +{ + int log2_in = ilog2(size); + + if (log2_in >= 12 && log2_in <= 15) + /* Covers 4KB to 32KB (inclusive) */ + return (log2_in - 12) + 0x1c; + else if (log2_in >= 16 && log2_in <= 37) + /* Covers 64KB to 32GB, (inclusive) */ + return log2_in - 15; + /* Something is awry so disable */ + return 0; +} + +/* Configuration space read/write support */ +static inline int brcm_pcie_cfg_index(pci_dev_t bdf, int reg) +{ + return (PCI_DEV(bdf) << PCIE_EXT_SLOT_SHIFT) + | (PCI_FUNC(bdf) << PCIE_EXT_FUNC_SHIFT) + | (PCI_BUS(bdf) << PCIE_EXT_BUSNUM_SHIFT) + | (reg & ~3); +} + +/* The controller is capable of serving in both RC and EP roles */ +static bool brcm_pcie_rc_mode(struct brcm_pcie *pcie) +{ + u32 val = readl(pcie->base + PCIE_MISC_PCIE_STATUS); + + return !!FIELD_GET(PCIE_MISC_PCIE_STATUS_PCIE_PORT_MASK, val); +} + +static bool brcm_pcie_link_up(struct brcm_pcie *pcie) +{ + u32 val = readl(pcie->base + PCIE_MISC_PCIE_STATUS); + u32 dla = FIELD_GET(PCIE_MISC_PCIE_STATUS_PCIE_DL_ACTIVE_MASK, val); + u32 plu = FIELD_GET(PCIE_MISC_PCIE_STATUS_PCIE_PHYLINKUP_MASK, val); + + return dla && plu; +} + +static int brcm_pcie_config_address(const struct udevice *udev, pci_dev_t bdf, + uint offset, void **paddress) +{ + struct brcm_pcie *pcie = dev_get_priv(udev); + unsigned int bus = PCI_BUS(bdf); + unsigned int dev = PCI_DEV(bdf); + int idx; + + /* + * Busses 0 (host PCIe bridge) and 1 (its immediate child) + * are limited to a single device each + */ + if ((bus == (udev->seq + 1)) && dev > 0) + return -ENODEV; + + /* Accesses to the RC go right to the RC registers if PCI device == 0 */ + if (bus == udev->seq) { + if (PCI_DEV(bdf)) + return -ENODEV; + + *paddress = pcie->base + offset; + return 0; + } + + /* For devices, write to the config space index register */ + idx = brcm_pcie_cfg_index(bdf, 0); + + writel(idx, pcie->base + PCIE_EXT_CFG_INDEX); + *paddress = pcie->base + PCIE_EXT_CFG_DATA + offset; + + return 0; +} + +static int brcm_pcie_read_config(const struct udevice *bus, pci_dev_t bdf, + uint offset, ulong *valuep, + enum pci_size_t size) +{ + return pci_generic_mmap_read_config(bus, brcm_pcie_config_address, + bdf, offset, valuep, size); +} + +static int brcm_pcie_write_config(struct udevice *bus, pci_dev_t bdf, + uint offset, ulong value, + enum pci_size_t size) +{ + return pci_generic_mmap_write_config(bus, brcm_pcie_config_address, + bdf, offset, value, size); +} + +static const char *link_speed_to_str(unsigned int s) +{ + static const char * const speed_str[] = { "??", "2.5", "5.0", "8.0" }; + + if (s >= ARRAY_SIZE(speed_str)) + s = 0; + + return speed_str[s]; +} + +static inline void brcm_pcie_bridge_sw_init_set(struct brcm_pcie *pcie, u32 val) +{ + u32 tmp; + + tmp = readl(pcie->base + PCIE_RGR1_SW_INIT_1); + u32p_replace_bits(&tmp, val, PCIE_RGR1_SW_INIT_1_INIT_MASK); + writel(tmp, pcie->base + PCIE_RGR1_SW_INIT_1); +} + +static inline void brcm_pcie_perst_set(struct brcm_pcie *pcie, u32 val) +{ + u32 tmp; + + tmp = readl(pcie->base + PCIE_RGR1_SW_INIT_1); + u32p_replace_bits(&tmp, val, PCIE_RGR1_SW_INIT_1_PERST_MASK); + writel(tmp, pcie->base + PCIE_RGR1_SW_INIT_1); +} + +static u32 brcm_pcie_mdio_form_pkt(int port, int regad, int cmd) +{ + u32 pkt = 0; + + pkt |= FIELD_PREP(MDIO_PORT_MASK, port); + pkt |= FIELD_PREP(MDIO_REGAD_MASK, regad); + pkt |= FIELD_PREP(MDIO_CMD_MASK, cmd); + + return pkt; +} + +/* Negative return value indicates error */ +static int brcm_pcie_mdio_read(void __iomem *base, u8 port, u8 regad, u32 *val) +{ + int tries; + u32 data; + + writel(brcm_pcie_mdio_form_pkt(port, regad, MDIO_CMD_READ), + base + PCIE_RC_DL_MDIO_ADDR); + readl(base + PCIE_RC_DL_MDIO_ADDR); + + data = readl(base + PCIE_RC_DL_MDIO_RD_DATA); + for (tries = 0; !MDIO_RD_DONE(data) && tries < 10; tries++) { + udelay(10); + data = readl(base + PCIE_RC_DL_MDIO_RD_DATA); + } + + *val = FIELD_GET(MDIO_DATA_MASK, data); + return MDIO_RD_DONE(data) ? 0 : -EIO; +} + +/* Negative return value indicates error */ +static int brcm_pcie_mdio_write(void __iomem *base, u8 port, + u8 regad, u16 wrdata) +{ + int tries; + u32 data; + + writel(brcm_pcie_mdio_form_pkt(port, regad, MDIO_CMD_WRITE), + base + PCIE_RC_DL_MDIO_ADDR); + readl(base + PCIE_RC_DL_MDIO_ADDR); + writel(MDIO_DATA_DONE_MASK | wrdata, base + PCIE_RC_DL_MDIO_WR_DATA); + + data = readl(base + PCIE_RC_DL_MDIO_WR_DATA); + for (tries = 0; !MDIO_WT_DONE(data) && tries < 10; tries++) { + udelay(10); + data = readl(base + PCIE_RC_DL_MDIO_WR_DATA); + } + + return MDIO_WT_DONE(data) ? 0 : -EIO; +} + +/* + * Configures device for Spread Spectrum Clocking (SSC) mode; negative + * return value indicates error. + */ +static int brcm_pcie_set_ssc(struct brcm_pcie *pcie) +{ + void __iomem *base = pcie->base; + int pll, ssc; + int ret; + u32 tmp; + + ret = brcm_pcie_mdio_write(base, MDIO_PORT0, SET_ADDR_OFFSET, + SSC_REGS_ADDR); + if (ret < 0) + return ret; + + ret = brcm_pcie_mdio_read(base, MDIO_PORT0, SSC_CNTL_OFFSET, &tmp); + if (ret < 0) + return ret; + + u32p_replace_bits(&tmp, 1, SSC_CNTL_OVRD_EN_MASK); + u32p_replace_bits(&tmp, 1, SSC_CNTL_OVRD_VAL_MASK); + ret = brcm_pcie_mdio_write(base, MDIO_PORT0, SSC_CNTL_OFFSET, tmp); + if (ret < 0) + return ret; + + udelay(1000); + ret = brcm_pcie_mdio_read(base, MDIO_PORT0, SSC_STATUS_OFFSET, &tmp); + if (ret < 0) + return ret; + + ssc = FIELD_GET(SSC_STATUS_SSC_MASK, tmp); + pll = FIELD_GET(SSC_STATUS_PLL_LOCK_MASK, tmp); + + return ssc && pll ? 0 : -EIO; +} + +/* Limits operation to a specific generation (1, 2, or 3) */ +static void brcm_pcie_set_gen(struct brcm_pcie *pcie, int gen) +{ + void __iomem *base = pcie->base; + + u16 lnkctl2 = readw(base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKCTL2); + u32 lnkcap = readl(base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKCAP); + + lnkcap = (lnkcap & ~PCI_EXP_LNKCAP_SLS) | gen; + writel(lnkcap, base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKCAP); + + lnkctl2 = (lnkctl2 & ~0xf) | gen; + writew(lnkctl2, base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKCTL2); +} + +static void brcm_pcie_set_outbound_win(struct brcm_pcie *pcie, + unsigned int win, u64 phys_addr, + u64 pcie_addr, u64 size) +{ + void __iomem *base = pcie->base; + u32 phys_addr_mb_high, limit_addr_mb_high; + phys_addr_t phys_addr_mb, limit_addr_mb; + int high_addr_shift; + u32 tmp; + + /* Set the base of the pcie_addr window */ + writel(lower_32_bits(pcie_addr), base + PCIE_MEM_WIN0_LO(win)); + writel(upper_32_bits(pcie_addr), base + PCIE_MEM_WIN0_HI(win)); + + /* Write the addr base & limit lower bits (in MBs) */ + phys_addr_mb = phys_addr / SZ_1M; + limit_addr_mb = (phys_addr + size - 1) / SZ_1M; + + tmp = readl(base + PCIE_MEM_WIN0_BASE_LIMIT(win)); + u32p_replace_bits(&tmp, phys_addr_mb, + PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_BASE_MASK); + u32p_replace_bits(&tmp, limit_addr_mb, + PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_LIMIT_MASK); + writel(tmp, base + PCIE_MEM_WIN0_BASE_LIMIT(win)); + + /* Write the cpu & limit addr upper bits */ + high_addr_shift = PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_BASE_HI_SHIFT; + phys_addr_mb_high = phys_addr_mb >> high_addr_shift; + tmp = readl(base + PCIE_MEM_WIN0_BASE_HI(win)); + u32p_replace_bits(&tmp, phys_addr_mb_high, + PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI_BASE_MASK); + writel(tmp, base + PCIE_MEM_WIN0_BASE_HI(win)); + + limit_addr_mb_high = limit_addr_mb >> high_addr_shift; + tmp = readl(base + PCIE_MEM_WIN0_LIMIT_HI(win)); + u32p_replace_bits(&tmp, limit_addr_mb_high, + PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI_LIMIT_MASK); + writel(tmp, base + PCIE_MEM_WIN0_LIMIT_HI(win)); +} + +static int brcm_pcie_probe(struct udevice *dev) +{ + struct udevice *ctlr = pci_get_controller(dev); + struct pci_controller *hose = dev_get_uclass_priv(ctlr); + struct brcm_pcie *pcie = dev_get_priv(dev); + void __iomem *base = pcie->base; + bool ssc_good = false; + int num_out_wins = 0; + u64 rc_bar2_offset, rc_bar2_size; + unsigned int scb_size_val; + int i, ret; + u16 nlw, cls, lnksta; + u32 tmp; + + /* Reset the bridge */ + brcm_pcie_bridge_sw_init_set(pcie, 1); + + udelay(150); + + /* Take the bridge out of reset */ + brcm_pcie_bridge_sw_init_set(pcie, 0); + + tmp = readl(base + PCIE_MISC_HARD_PCIE_HARD_DEBUG); + tmp &= ~PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK; + writel(tmp, base + PCIE_MISC_HARD_PCIE_HARD_DEBUG); + /* Wait for SerDes to be stable */ + udelay(150); + + /* Set SCB_MAX_BURST_SIZE, CFG_READ_UR_MODE, SCB_ACCESS_EN */ + u32p_replace_bits(&tmp, 1, PCIE_MISC_MISC_CTRL_SCB_ACCESS_EN_MASK); + u32p_replace_bits(&tmp, 1, PCIE_MISC_MISC_CTRL_CFG_READ_UR_MODE_MASK); + u32p_replace_bits(&tmp, PCIE_MISC_MISC_CTRL_MAX_BURST_SIZE_128, + PCIE_MISC_MISC_CTRL_MAX_BURST_SIZE_MASK); + writel(tmp, base + PCIE_MISC_MISC_CTRL); + + /* + * TODO: Use the base address and size(s) provided in the dma-ranges + * property. + */ + rc_bar2_offset = 0; + rc_bar2_size = 1ULL << 32; + + tmp = lower_32_bits(rc_bar2_offset); + u32p_replace_bits(&tmp, brcm_pcie_encode_ibar_size(rc_bar2_size), + PCIE_MISC_RC_BAR2_CONFIG_LO_SIZE_MASK); + writel(tmp, base + PCIE_MISC_RC_BAR2_CONFIG_LO); + writel(upper_32_bits(rc_bar2_offset), + base + PCIE_MISC_RC_BAR2_CONFIG_HI); + + scb_size_val = rc_bar2_size ? + ilog2(rc_bar2_size) - 15 : 0xf; /* 0xf is 1GB */ + tmp = readl(base + PCIE_MISC_MISC_CTRL); + u32p_replace_bits(&tmp, scb_size_val, + PCIE_MISC_MISC_CTRL_SCB0_SIZE_MASK); + writel(tmp, base + PCIE_MISC_MISC_CTRL); + + /* Disable the PCIe->GISB memory window (RC_BAR1) */ + tmp = readl(base + PCIE_MISC_RC_BAR1_CONFIG_LO); + tmp &= ~PCIE_MISC_RC_BAR1_CONFIG_LO_SIZE_MASK; + writel(tmp, base + PCIE_MISC_RC_BAR1_CONFIG_LO); + + /* Disable the PCIe->SCB memory window (RC_BAR3) */ + tmp = readl(base + PCIE_MISC_RC_BAR3_CONFIG_LO); + tmp &= ~PCIE_MISC_RC_BAR3_CONFIG_LO_SIZE_MASK; + writel(tmp, base + PCIE_MISC_RC_BAR3_CONFIG_LO); + + /* Mask all interrupts since we are not handling any yet */ + writel(0xffffffff, base + PCIE_MSI_INTR2_MASK_SET); + + /* Clear any interrupts we find on boot */ + writel(0xffffffff, base + PCIE_MSI_INTR2_CLR); + + if (pcie->gen) + brcm_pcie_set_gen(pcie, pcie->gen); + + /* Unassert the fundamental reset */ + brcm_pcie_perst_set(pcie, 0); + + /* Give the RC/EP time to wake up, before trying to configure RC. + * Intermittently check status for link-up, up to a total of 100ms. + */ + for (i = 0; i < 100 && !brcm_pcie_link_up(pcie); i += 5) + msleep(5); + + if (!brcm_pcie_link_up(pcie)) { + printf("PCIe BRCM: link down\n"); + return -ENODEV; + } + + if (!brcm_pcie_rc_mode(pcie)) { + printf("PCIe misconfigured; is in EP mode\n"); + return -EINVAL; + } + + for (i = 0; i < hose->region_count; i++) { + struct pci_region *reg = &hose->regions[i]; + + if (reg->flags != PCI_REGION_MEM) + continue; + + if (num_out_wins >= BRCM_NUM_PCIE_OUT_WINS) + return -EINVAL; + + brcm_pcie_set_outbound_win(pcie, num_out_wins, reg->phys_start, + reg->bus_start, reg->size); + + num_out_wins++; + } + + /* + * For config space accesses on the RC, show the right class for + * a PCIe-PCIe bridge (the default setting is to be EP mode). + */ + tmp = readl(base + PCIE_RC_CFG_PRIV1_ID_VAL3); + u32p_replace_bits(&tmp, 0x060400, + PCIE_RC_CFG_PRIV1_ID_VAL3_CLASS_CODE_MASK); + writel(tmp, base + PCIE_RC_CFG_PRIV1_ID_VAL3); + + if (pcie->ssc) { + ret = brcm_pcie_set_ssc(base); + if (ret == 0) + ssc_good = true; + else + printf("PCIe BRCM: failed attempt to enter SSC mode\n"); + } + + lnksta = readw(base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKSTA); + cls = FIELD_GET(PCI_EXP_LNKSTA_CLS, lnksta); + nlw = FIELD_GET(PCI_EXP_LNKSTA_NLW, lnksta); + + printf("PCIe BRCM: link up, %s Gbps x%u %s\n", link_speed_to_str(cls), + nlw, ssc_good ? "(SSC)" : "(!SSC)"); + + /* PCIe->SCB endian mode for BAR */ + tmp = readl(base + PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1); + u32p_replace_bits(&tmp, PCIE_RC_CFG_VENDOR_SPCIFIC_REG1_LITTLE_ENDIAN, + PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR2_MASK); + writel(tmp, base + PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1); + + /* + * Refclk from RC should be gated with CLKREQ# input when ASPM L0s,L1 + * is enabled => setting the CLKREQ_DEBUG_ENABLE field to 1. + */ + tmp = readl(base + PCIE_MISC_HARD_PCIE_HARD_DEBUG); + tmp |= PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_MASK; + writel(tmp, base + PCIE_MISC_HARD_PCIE_HARD_DEBUG); + + return 0; +} + +static int brcm_pcie_ofdata_to_platdata(struct udevice *dev) +{ + struct brcm_pcie *pcie = dev_get_priv(dev); + ofnode dn = dev_ofnode(dev); + u32 max_link_speed; + int ret; + + /* Get the controller base address */ + pcie->base = dev_read_addr_ptr(dev); + if (!pcie->base) + return -EINVAL; + + pcie->ssc = ofnode_read_bool(dn, "brcm,enable-ssc"); + + ret = ofnode_read_u32(dn, "max-link-speed", &max_link_speed); + if (ret < 0 || max_link_speed > 4) + pcie->gen = 0; + else + pcie->gen = max_link_speed; + + return 0; +} + +static const struct dm_pci_ops brcm_pcie_ops = { + .read_config = brcm_pcie_read_config, + .write_config = brcm_pcie_write_config, +}; + +static const struct udevice_id brcm_pcie_ids[] = { + { .compatible = "brcm,bcm2711-pcie" }, + { } +}; + +U_BOOT_DRIVER(pcie_brcm_base) = { + .name = "pcie_brcm", + .id = UCLASS_PCI, + .ops = &brcm_pcie_ops, + .of_match = brcm_pcie_ids, + .probe = brcm_pcie_probe, + .ofdata_to_platdata = brcm_pcie_ofdata_to_platdata, + .priv_auto_alloc_size = sizeof(struct brcm_pcie), +}; From patchwork Fri Apr 24 16:50:12 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sylwester Nawrocki X-Patchwork-Id: 1276524 X-Patchwork-Delegate: matthias.bgg@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; 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Fri, 24 Apr 2020 16:52:45 +0000 (GMT) From: Sylwester Nawrocki To: u-boot@lists.denx.de, mbrugger@suse.com, marex@denx.de, bmeng.cn@gmail.com Cc: sjg@chromium.org, nsaenzjulienne@suse.de, jh80.chung@samsung.com, m.szyprowski@samsung.com, b.zolnierkie@samsung.com Subject: [PATCH v1 10/10] config: Enable support for the XHCI controller on RPI4 board Date: Fri, 24 Apr 2020 18:50:12 +0200 Message-Id: <20200424165012.31915-11-s.nawrocki@samsung.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200424165012.31915-1-s.nawrocki@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA0WSa0hTcRjG+buznbPp7DQN36m0GJpYeMOEA0lUCA1EWN8svE09bOamsqOW RuAlzNZS0UyZEEs/OKbibc1bRppmNjQTMu9KGahkVpqk4sp5tL793ud9Hp6XP3+CIyrlehIp aZm0Nk2hlvIEmPX19ruAeHFdXPBKr5BqrW7mUpX6eGpyp4hLNQ3M4dTXonxEGSuWuJTVUM+j tixWRK313scv8mU1ee8x2RPDG0zWZZjDZSOznUhWYjEjWbPlAyZrt92W49cF4cm0OiWb1gZd SBCo3k784GW0nrq10WHH89Culw7xCSDPQUtNt5MOCQgRaULwbdt0OGwiaJ9a5LLDBoL5sVXu UaRnqhqxi3oETUtP0b/I84W7uMPFI0Pg4WAJcrA7KYeJ7ccHzCFz4eO9L5iD3choKJjc4zgY I32hs2pmv5sghGQ4lHWcYMsk0NDy8sDC35fzR1YxRxeQpThYh+cRa4qA398XD9kNVocsOMve YKvQHwYKEeh7ZnB2KEOwMGQ8TJyH2dEdnqOZQ/pDc3cQK1+Czw0G5JCBdIXJtePs/a5Qbq3i sLIQiotErNsHds1VTix7woOlPxjLMqjeWuSw71OKYKyxDy9DEsP/MiNCZuRBZzEaJc2EpNE3 AxmFhslKUwYmpWva0P43sdmHfnaiX+OJ/YgkkNRFGD1QGyfiKrKZHE0/AoIjdRfGZO5LwmRF Ti6tTY/XZqlpph95EZjUQxhauxIrIpWKTDqVpjNo7dHWieB75qGTLfykWDF/fjpxuPuYpHi9 tyxh2iiv3HQO7WqeVlE+xqjlFxli/5GSs3U6T9z1hmDdvU8utlkwj0eNyYGvri6PegeUm2Yv X0vs0o9H1Cj9BlcKncOi7uytNJpPp4YRpj21n9XQE3Ol7ZN985m9wNdFWRgZ7DwM5arIAJ1k WIoxKkXIGY6WUfwFioI5ASIDAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrPLMWRmVeSWpSXmKPExsVy+t/xe7pxkovjDA7f4LXYOGM9q8XUnniL G7/aWC3WHrnLbvGmrZHRYsHkJ6wW22YtZ7P4tmUbo8XbvZ3sDpwesxsusnjMm3WCxWPnrLvs Hmfv7GD06NuyitFj/ZarLB6bT1cHsEfp2RTll5akKmTkF5fYKkUbWhjpGVpa6BmZWOoZGpvH WhmZKunb2aSk5mSWpRbp2yXoZZy69pGtYKNCxeft/9gbGH9LdzFyckgImEjsvjmDsYuRi0NI YCmjxJK2KyxdjBxACSmJ+S1KEDXCEn+udbFB1HxilHiz6wArSIJNwFCi92gfI4gtIhAi8eLo FSaQImaBBkaJe0fngBUJC4RJvP1/jw3EZhFQldgx/TYTyAJeARuJCdtFIRbIS6zecIAZxOYE CjeefcUCYgsJWEtsm/mcZQIj3wJGhlWMIqmlxbnpucWGesWJucWleel6yfm5mxiBgb3t2M/N OxgvbQw+xCjAwajEwxtxZFGcEGtiWXFl7iFGCQ5mJRHemBKgEG9KYmVValF+fFFpTmrxIUZT oJsmMkuJJucDoy6vJN7Q1NDcwtLQ3Njc2MxCSZy3Q+BgjJBAemJJanZqakFqEUwfEwenVAPj jFqnu4dmX63tLO+9uGlmplrik/qQJbJ5tVud9yxJqLvttfZxw/K/a3Mlg8P2SzywMOWvaHD8 OX3ytUTXO0aXTh3riDp0SfJwEY/1Vl0js3iGXEPxJ2uN307RXWzQq7s7k3WO8vlj2js+SAkG uB/+bPtbZLqPstgMp8d338mWL9hcuWxpzYFKJZbijERDLeai4kQAy1soioICAAA= X-CMS-MailID: 20200424165246eucas1p2a031b3a0f71800ea2b5812ce0ece799f X-Msg-Generator: CA X-RootMTR: 20200424165246eucas1p2a031b3a0f71800ea2b5812ce0ece799f X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20200424165246eucas1p2a031b3a0f71800ea2b5812ce0ece799f References: <20200424165012.31915-1-s.nawrocki@samsung.com> X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.30rc1 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.2 at phobos.denx.de X-Virus-Status: Clean From: Marek Szyprowski This requires enabling BRCMSTB PCIe and XHCI_PCI drivers as well as PCI and USB commands. To get it working one has to call the following commands: "pci enum; usb start;", thus such commands have been added to the default "preboot" environment variable. One has to update their environment if it is already configured to get this feature working out of the box. Signed-off-by: Marek Szyprowski --- Changes since RFC: - none. --- configs/rpi_4_32b_defconfig | 9 +++++++++ configs/rpi_4_defconfig | 10 ++++++++++ configs/rpi_arm64_defconfig | 9 ++++++++- 3 files changed, 27 insertions(+), 1 deletion(-) diff --git a/configs/rpi_4_32b_defconfig b/configs/rpi_4_32b_defconfig index 72cda5d..0dd763f 100644 --- a/configs/rpi_4_32b_defconfig +++ b/configs/rpi_4_32b_defconfig @@ -8,6 +8,8 @@ CONFIG_NR_DRAM_BANKS=2 CONFIG_DISTRO_DEFAULTS=y CONFIG_OF_BOARD_SETUP=y # CONFIG_ARCH_FIXUP_FDT_MEMORY is not set +CONFIG_USE_PREBOOT=y +CONFIG_PREBOOT="pci enum; usb start;" CONFIG_MISC_INIT_R=y # CONFIG_DISPLAY_CPUINFO is not set # CONFIG_DISPLAY_BOARDINFO is not set @@ -15,6 +17,8 @@ CONFIG_SYS_PROMPT="U-Boot> " CONFIG_CMD_DFU=y CONFIG_CMD_GPIO=y CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y +CONFIG_CMD_USB=y CONFIG_CMD_FS_UUID=y CONFIG_OF_BOARD=y CONFIG_ENV_FAT_INTERFACE="mmc" @@ -28,12 +32,17 @@ CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_BCM2835=y CONFIG_DM_ETH=y CONFIG_BCMGENET=y +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_PCI_BRCMSTB=y CONFIG_PINCTRL=y # CONFIG_PINCTRL_GENERIC is not set # CONFIG_REQUIRE_SERIAL_CONSOLE is not set CONFIG_USB=y CONFIG_DM_USB=y CONFIG_DM_USB_GADGET=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_PCI=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="FSL" CONFIG_USB_GADGET_VENDOR_NUM=0x0525 diff --git a/configs/rpi_4_defconfig b/configs/rpi_4_defconfig index 6d148da..f80e5da 100644 --- a/configs/rpi_4_defconfig +++ b/configs/rpi_4_defconfig @@ -8,6 +8,8 @@ CONFIG_NR_DRAM_BANKS=2 CONFIG_DISTRO_DEFAULTS=y CONFIG_OF_BOARD_SETUP=y # CONFIG_ARCH_FIXUP_FDT_MEMORY is not set +CONFIG_USE_PREBOOT=y +CONFIG_PREBOOT="pci enum; usb start;" CONFIG_MISC_INIT_R=y # CONFIG_DISPLAY_CPUINFO is not set # CONFIG_DISPLAY_BOARDINFO is not set @@ -15,6 +17,8 @@ CONFIG_SYS_PROMPT="U-Boot> " CONFIG_CMD_DFU=y CONFIG_CMD_GPIO=y CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y +CONFIG_CMD_USB=y CONFIG_CMD_FS_UUID=y CONFIG_OF_BOARD=y CONFIG_ENV_FAT_INTERFACE="mmc" @@ -28,12 +32,18 @@ CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_BCM2835=y CONFIG_DM_ETH=y CONFIG_BCMGENET=y +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_PCI_BRCMSTB=y CONFIG_PINCTRL=y # CONFIG_PINCTRL_GENERIC is not set # CONFIG_REQUIRE_SERIAL_CONSOLE is not set CONFIG_USB=y CONFIG_DM_USB=y CONFIG_DM_USB_GADGET=y +CONFIG_USB_XHCI_HCD=y +CONFIG_XHCI_64BIT_DWORD_ACCESS_ONLY=y +CONFIG_USB_XHCI_PCI=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="FSL" CONFIG_USB_GADGET_VENDOR_NUM=0x0525 diff --git a/configs/rpi_arm64_defconfig b/configs/rpi_arm64_defconfig index fea86be..926dfc3 100644 --- a/configs/rpi_arm64_defconfig +++ b/configs/rpi_arm64_defconfig @@ -7,13 +7,14 @@ CONFIG_NR_DRAM_BANKS=2 CONFIG_DISTRO_DEFAULTS=y CONFIG_OF_BOARD_SETUP=y CONFIG_USE_PREBOOT=y -CONFIG_PREBOOT="usb start" +CONFIG_PREBOOT="pci enum; usb start;" CONFIG_MISC_INIT_R=y # CONFIG_DISPLAY_CPUINFO is not set # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SYS_PROMPT="U-Boot> " CONFIG_CMD_GPIO=y CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y CONFIG_CMD_USB=y CONFIG_CMD_FS_UUID=y CONFIG_OF_BOARD=y @@ -26,11 +27,17 @@ CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_BCM2835=y CONFIG_DM_ETH=y CONFIG_BCMGENET=y +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_PCI_BRCMSTB=y CONFIG_PINCTRL=y # CONFIG_PINCTRL_GENERIC is not set # CONFIG_REQUIRE_SERIAL_CONSOLE is not set CONFIG_USB=y CONFIG_DM_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_XHCI_64BIT_DWORD_ACCESS_ONLY=y +CONFIG_USB_XHCI_PCI=y CONFIG_USB_DWC2=y CONFIG_USB_KEYBOARD=y CONFIG_USB_HOST_ETHER=y