From patchwork Tue Apr 21 21:53:53 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aaron Sawdey X-Patchwork-Id: 1274539 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=8.43.85.97; helo=sourceware.org; envelope-from=gcc-patches-bounces@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=gcc.gnu.org Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.a=rsa-sha256 header.s=default header.b=xdwC3qkI; dkim-atps=neutral Received: from sourceware.org (server2.sourceware.org [8.43.85.97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 496HQV6ylJz9sSb for ; Wed, 22 Apr 2020 07:54:10 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id B3827386F460; Tue, 21 Apr 2020 21:54:06 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org B3827386F460 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1587506046; bh=zkOAYZJEneeQa4F5YPNjdsICEV8+1gJmSsY2jUIOIBU=; h=To:Subject:Date:In-Reply-To:List-Id:List-Unsubscribe:List-Archive: List-Post:List-Help:List-Subscribe:From:Reply-To:Cc:From; b=xdwC3qkIOakezJOqqVTLcfB2xTowkvCYsG4TKNz3/dnCBebPUjoF6oD2UG02lgEqh stCztMpbUklU/4w48jE9IC0vtG5n+K2KriGHfR/2AIRvyx8KWlwx4GJyv6tFO+VRLs ytSt4uTls5T4Z6Z0nECqmcNOzKE6OVCBcAqxnark= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com [148.163.156.1]) by sourceware.org (Postfix) with ESMTPS id 3ADCA386F02B for ; Tue, 21 Apr 2020 21:54:03 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.3.2 sourceware.org 3ADCA386F02B Received: from pps.filterd (m0098404.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id 03LLW0Yv084520; Tue, 21 Apr 2020 17:54:02 -0400 Received: from ppma02dal.us.ibm.com (a.bd.3ea9.ip4.static.sl-reverse.com [169.62.189.10]) by mx0a-001b2d01.pphosted.com with ESMTP id 30gmu8jhs9-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 21 Apr 2020 17:54:02 -0400 Received: from pps.filterd (ppma02dal.us.ibm.com [127.0.0.1]) by ppma02dal.us.ibm.com (8.16.0.27/8.16.0.27) with SMTP id 03LLpFrW017346; Tue, 21 Apr 2020 21:54:01 GMT Received: from b03cxnp08028.gho.boulder.ibm.com (b03cxnp08028.gho.boulder.ibm.com [9.17.130.20]) by ppma02dal.us.ibm.com with ESMTP id 30fs66upbg-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 21 Apr 2020 21:54:01 +0000 Received: from b03ledav004.gho.boulder.ibm.com (b03ledav004.gho.boulder.ibm.com [9.17.130.235]) by b03cxnp08028.gho.boulder.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 03LLrxIK63570340 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Tue, 21 Apr 2020 21:53:59 GMT Received: from b03ledav004.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 79BA67805E; Tue, 21 Apr 2020 21:53:59 +0000 (GMT) Received: from b03ledav004.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 5AD437805C; Tue, 21 Apr 2020 21:53:59 +0000 (GMT) Received: from marlin.aus.stglabs.ibm.com (unknown [9.40.194.84]) by b03ledav004.gho.boulder.ibm.com (Postfix) with ESMTPS; Tue, 21 Apr 2020 21:53:59 +0000 (GMT) Received: from marlin.aus.stglabs.ibm.com (localhost [127.0.0.1]) by marlin.aus.stglabs.ibm.com (8.15.2/8.15.2/Debian-10) with ESMTP id 03LLrwHh068470; Tue, 21 Apr 2020 16:53:58 -0500 Received: (from sawdey@localhost) by marlin.aus.stglabs.ibm.com (8.15.2/8.15.2/Submit) id 03LLrwUt068466; Tue, 21 Apr 2020 16:53:58 -0500 To: gcc-patches@gcc.gnu.org Subject: [PATCH][v3], rs6000: Use plq/pstq for atomic_{load, store} (PR94622) Date: Tue, 21 Apr 2020 16:53:53 -0500 Message-Id: <20200421215354.68412-1-acsawdey@linux.ibm.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200421113028.GS26902@gate.crashing.org> X-TM-AS-GCONF: 00 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.138, 18.0.676 definitions=2020-04-21_08:2020-04-21, 2020-04-21 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 priorityscore=1501 spamscore=0 lowpriorityscore=0 adultscore=0 impostorscore=0 mlxscore=0 malwarescore=0 suspectscore=1 mlxlogscore=999 clxscore=1015 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2003020000 definitions=main-2004210153 X-Spam-Status: No, score=-31.9 required=5.0 tests=BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, KAM_DMARC_STATUS, KAM_LAZY_DOMAIN_SECURITY, RCVD_IN_DNSWL_LOW, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Aaron Sawdey via Gcc-patches From: Aaron Sawdey Reply-To: Aaron Sawdey Cc: meissner@linux.ibm.com, wschmidt@linux.ibm.com, segher@kernel.crashing.org Errors-To: gcc-patches-bounces@gcc.gnu.org Sender: "Gcc-patches" For future architecture with prefix instructions, always use plq/pstq rather than lq/stq for atomic load of quadword. Then we never have to do the doubleword swap on little endian. Before this fix, -mno-pcrel would generate lq with the doubleword swap (which was ok) and -mpcrel would generate plq, also with the doubleword swap, which was wrong. While adding comments I realized we have exactly the same problem with pstq/stq so I have added fixes for that as well. Assuming that regstrap passes, OK for trunk? Thanks, Aaron 2020-04-20 Aaron Sawdey PR target/94622 * config/rs6000/sync.md (load_quadpti): Add attr "prefixed" if TARGET_PREFIXED. (store_quadpti): Ditto. (atomic_load): Do not swap doublewords if TARGET_PREFIXED as plq will be used and doesn't need it. (atomic_store): Ditto, for pstq. --- gcc/config/rs6000/sync.md | 27 ++++++++++++++++++++++----- 1 file changed, 22 insertions(+), 5 deletions(-) diff --git a/gcc/config/rs6000/sync.md b/gcc/config/rs6000/sync.md index f27edc77b6a..bf529fc8268 100644 --- a/gcc/config/rs6000/sync.md +++ b/gcc/config/rs6000/sync.md @@ -122,6 +122,7 @@ (define_insn "loadsync_" [(set_attr "type" "isync") (set_attr "length" "12")]) +;; If TARGET_PREFIXED, always use plq rather than lq. (define_insn "load_quadpti" [(set (match_operand:PTI 0 "quad_int_reg_operand" "=&r") (unspec:PTI @@ -129,8 +130,18 @@ (define_insn "load_quadpti" "TARGET_SYNC_TI && !reg_mentioned_p (operands[0], operands[1])" "lq %0,%1" - [(set_attr "type" "load")]) - + [(set_attr "type" "load") + (set (attr "prefixed") (if_then_else (match_test "TARGET_PREFIXED") + (const_string "yes") + (const_string "no")))]) + +;; Pattern load_quadpti will always use plq for atomic TImode if +;; TARGET_PREFIXED. It has the correct doubleword ordering on either LE +;; or BE, so we can just move the result into the output register and +;; do not need to do the doubleword swap for LE. Also this avoids any +;; confusion about whether the lq vs plq might be used based on whether +;; op1 has PC-relative addressing. We could potentially allow BE to +;; use lq because it doesn't have the doubleword ordering problem. (define_expand "atomic_load" [(set (match_operand:AINT 0 "register_operand") ;; output (match_operand:AINT 1 "memory_operand")) ;; memory @@ -162,7 +173,7 @@ (define_expand "atomic_load" emit_insn (gen_load_quadpti (pti_reg, op1)); - if (WORDS_BIG_ENDIAN) + if (WORDS_BIG_ENDIAN || TARGET_PREFIXED) emit_move_insn (op0, gen_lowpart (TImode, pti_reg)); else { @@ -186,14 +197,20 @@ (define_expand "atomic_load" DONE; }) +;; If TARGET_PREFIXED, always use pstq rather than stq. (define_insn "store_quadpti" [(set (match_operand:PTI 0 "quad_memory_operand" "=wQ") (unspec:PTI [(match_operand:PTI 1 "quad_int_reg_operand" "r")] UNSPEC_LSQ))] "TARGET_SYNC_TI" "stq %1,%0" - [(set_attr "type" "store")]) + [(set_attr "type" "store") + (set (attr "prefixed") (if_then_else (match_test "TARGET_PREFIXED") + (const_string "yes") + (const_string "no")))]) +;; Pattern store_quadpti will always use pstq if TARGET_PREFIXED, +;; so the doubleword swap is never needed in that case. (define_expand "atomic_store" [(set (match_operand:AINT 0 "memory_operand") ;; memory (match_operand:AINT 1 "register_operand")) ;; input @@ -232,7 +249,7 @@ (define_expand "atomic_store" operands[0] = op0 = replace_equiv_address (op0, new_addr); } - if (WORDS_BIG_ENDIAN) + if (WORDS_BIG_ENDIAN || TARGET_PREFIXED) emit_move_insn (pti_reg, gen_lowpart (PTImode, op1)); else {