From patchwork Mon Apr 13 15:35:25 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sean V Kelley X-Patchwork-Id: 1269860 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.intel.com Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 491CPR75Ncz9s71 for ; Tue, 14 Apr 2020 01:35:39 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728797AbgDMPfj (ORCPT ); Mon, 13 Apr 2020 11:35:39 -0400 Received: from mga03.intel.com ([134.134.136.65]:64941 "EHLO mga03.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728808AbgDMPfi (ORCPT ); Mon, 13 Apr 2020 11:35:38 -0400 IronPort-SDR: ROgvgSpM7+UHvLa8uYd4LbzJzUCHXKaM+Ag3WI3fjI8veMs9U758lv/8TNF/nyzsUD4KG6EHQQ bNRoyX8TOX0g== X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga006.jf.intel.com ([10.7.209.51]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Apr 2020 08:35:29 -0700 IronPort-SDR: Kos9f4HmiJYVCU+mQWuxdE+CIn7I3VWlQH3BF2Me1ZJ1ceMCDacc5ig8WidYYI6r5A1iW4rskG ny/aTGSXTYDg== X-IronPort-AV: E=Sophos;i="5.72,378,1580803200"; d="scan'208";a="256209892" Received: from erickaal-mobl.amr.corp.intel.com (HELO arch-ashland-svkelley.intel.com) ([10.135.57.115]) by orsmga006-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Apr 2020 08:35:28 -0700 From: Sean V Kelley To: mj@ucw.cz, bhelgaas@google.com Cc: linux-pci@vger.kernel.org, Sean V Kelley Subject: [PATCH v4 1/2] pciutils: Decode available DVSEC details Date: Mon, 13 Apr 2020 08:35:25 -0700 Message-Id: <20200413153526.805776-2-sean.v.kelley@linux.intel.com> X-Mailer: git-send-email 2.26.0 In-Reply-To: <20200413153526.805776-1-sean.v.kelley@linux.intel.com> References: <20200413153526.805776-1-sean.v.kelley@linux.intel.com> MIME-Version: 1.0 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Instead of current generic 'unknown' output for DVSEC, decode details on Vendor ID, Rev, etc. Suggested-by: Bjorn Helgaas Signed-off-by: Sean V Kelley --- lib/header.h | 4 + ls-ecaps.c | 25 +++- tests/cap-dvsec | 340 ++++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 368 insertions(+), 1 deletion(-) create mode 100644 tests/cap-dvsec diff --git a/lib/header.h b/lib/header.h index bfdcc80..daeddeb 100644 --- a/lib/header.h +++ b/lib/header.h @@ -1042,6 +1042,10 @@ #define PCI_EVNDR_HEADER 4 /* Vendor-Specific Header */ #define PCI_EVNDR_REGISTERS 8 /* Vendor-Specific Registers */ +/* PCIe Designated Vendor-Specific Capability */ +#define PCI_DVSEC_HEADER1 4 /* Designated Vendor-Specific Header 1 */ +#define PCI_DVSEC_HEADER2 8 /* Designated Vendor-Specific Header 2 */ + /* Access Control Services */ #define PCI_ACS_CAP 0x04 /* ACS Capability Register */ #define PCI_ACS_CAP_VALID 0x0001 /* ACS Source Validation */ diff --git a/ls-ecaps.c b/ls-ecaps.c index 0021734..b82d37e 100644 --- a/ls-ecaps.c +++ b/ls-ecaps.c @@ -634,6 +634,29 @@ cap_rclink(struct device *d, int where) } } +static void +cap_dvsec(struct device *d, int where) +{ + u32 hdr; + + printf("Designated Vendor-Specific:\n"); + if (!config_fetch(d, where + PCI_DVSEC_HEADER1, 8)) + { + printf("\n"); + return; + } + + hdr = get_conf_long(d, where + PCI_DVSEC_HEADER1); + printf("\t\tDVSEC Vendor ID=%04x Rev=%d Len=%03x \n", + BITS(hdr, 0, 16), + BITS(hdr, 16, 4), + BITS(hdr, 20, 12)); + + hdr = get_conf_long(d, where + PCI_DVSEC_HEADER2); + printf("\t\tDVSEC ID=%04x \n", + BITS(hdr, 0, 16)); +} + static void cap_evendor(struct device *d, int where) { @@ -924,7 +947,7 @@ show_ext_caps(struct device *d, int type) printf("Readiness Time Reporting \n"); break; case PCI_EXT_CAP_ID_DVSEC: - printf("Designated Vendor-Specific \n"); + cap_dvsec(d, where); break; case PCI_EXT_CAP_ID_VF_REBAR: printf("VF Resizable BAR \n"); diff --git a/tests/cap-dvsec b/tests/cap-dvsec new file mode 100644 index 0000000..3b3558c --- /dev/null +++ b/tests/cap-dvsec @@ -0,0 +1,340 @@ +4e:00.0 Unassigned class [ff00]: Intel Corporation Device 0d93 + Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- + Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- SERR- + Capabilities: [300 v1] Virtual Channel + Caps: LPEVC=0 RefClk=100ns PATEntryBits=1 + Arb: Fixed- WRR32- WRR64- WRR128- + Ctrl: ArbSelect=Fixed + Status: InProgress- + VC0: Caps: PATOffset=00 MaxTimeSlots=1 RejSnoopTrans- + Arb: Fixed- WRR32- WRR64- WRR128- TWRR128- WRR256- + Ctrl: Enable+ ID=0 ArbSelect=Fixed TC/VC=ff + Status: NegoPending- InProgress- + Capabilities: [550 v1] Multicast + McastCap: MaxGroups 64, WindowSz 1 (2 bytes) McastCtl: NumGroups 1, Enable- + McastBAR: IndexPos 0, BaseAddr 0000000000000000 + McastReceiveVec: 0000000000000000 + McastBlockAllVec: 0000000000000000 + McastBlockUntransVec: 0000000000000000 + Capabilities: [588 v1] Latency Tolerance Reporting + Max snoop latency: 0ns + Max no snoop latency: 0ns + Capabilities: [5b0 v1] Transaction Processing Hints + Extended requester support + Steering table in TPH capability structure + Capabilities: [6e0 v1] Address Translation Service (ATS) + ATSCap: Invalidate Queue Depth: 00 + ATSCtl: Enable-, Smallest Translation Unit: 00 + Capabilities: [700 v1] Resizable BAR + Capabilities: [714 v1] Secondary PCI Express + LnkCtl3: LnkEquIntrruptEn-, PerformEqu- + LaneErrStat: 0 + Capabilities: [b20 v1] Page Request Interface (PRI) + PRICtl: Enable- Reset- + PRISta: RF- UPRGI- Stopped+ + Page Request Capacity: 00000000, Page Request Allocation: 00000000 + Capabilities: [b40 v1] Process Address Space ID (PASID) + PASIDCap: Exec+ Priv+, Max PASID Width: 14 + PASIDCtl: Enable- Exec- Priv- + Capabilities: [b50 v1] Precision Time Measurement + PTMCap: Requester:- Responder:- Root:- + PTMClockGranularity: Unimplemented + PTMControl: Enabled:- RootSelected:- + PTMEffectiveGranularity: Unknown + Capabilities: [d00 v1] Vendor Specific Information: ID=0040 Rev=1 Len=04c + Capabilities: [e00 v1] Designated Vendor Specific Extended Capability: + DVSEC Vendor ID=8086 Rev=0 Len=038 + DVSEC ID=0000 + Capabilities: [e38 v1] Device Serial Number 12-34-56-78-90-00-00-00 +00: 86 80 93 0d 00 00 10 00 00 00 00 ff 00 00 80 00 +10: 00 00 10 b3 00 00 00 00 01 a4 00 00 00 00 00 00 +20: 08 00 00 b1 00 00 00 00 00 00 00 00 00 00 00 00 +30: 00 00 00 00 40 00 00 00 00 00 00 00 ff 01 00 00 +40: 10 80 92 00 e1 8f 00 10 10 21 00 00 00 00 00 00 +50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +50: 00 00 00 00 00 00 00 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00 00 00 00 90 +e40: 78 56 34 12 00 00 00 00 00 00 00 00 00 00 00 00 +e50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +e60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +e70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +e80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +e90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +ea0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +eb0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +ec0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +ed0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +ee0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +ef0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +f00: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +f10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +f20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +f30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +f40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +f50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +f60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +f70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +f80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +f90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +fa0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +fb0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +fc0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +fd0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +fe0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +ff0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 From patchwork Mon Apr 13 15:35:26 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sean V Kelley X-Patchwork-Id: 1269858 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.intel.com Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 491CPM2rRXz9s71 for ; Tue, 14 Apr 2020 01:35:35 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730504AbgDMPfe (ORCPT ); Mon, 13 Apr 2020 11:35:34 -0400 Received: from mga03.intel.com ([134.134.136.65]:64936 "EHLO mga03.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728797AbgDMPfd (ORCPT ); Mon, 13 Apr 2020 11:35:33 -0400 IronPort-SDR: vXcuMi8+pUGLo2xhGVTEf7dg1BdSBRQRevDxv0hi64cwjomtNEd9oASRrQZRX3QbfzVSOH8pTB L14kO2FfFvOg== X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga006.jf.intel.com ([10.7.209.51]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Apr 2020 08:35:32 -0700 IronPort-SDR: AGHlKx1Fmu3b1LkwLdA6Ooy7qHNG0q6uh6oN/jvmcdf1GfnWYENqdU6fLA4IyxbuCiRTX0QNyp w2Plz1g8RLpw== X-IronPort-AV: E=Sophos;i="5.72,378,1580803200"; d="scan'208";a="256209909" Received: from erickaal-mobl.amr.corp.intel.com (HELO arch-ashland-svkelley.intel.com) ([10.135.57.115]) by orsmga006-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Apr 2020 08:35:31 -0700 From: Sean V Kelley To: mj@ucw.cz, bhelgaas@google.com Cc: linux-pci@vger.kernel.org, Sean V Kelley Subject: [PATCH v4 2/2] pciutils: Decode Compute eXpress Link DVSEC Date: Mon, 13 Apr 2020 08:35:26 -0700 Message-Id: <20200413153526.805776-3-sean.v.kelley@linux.intel.com> X-Mailer: git-send-email 2.26.0 In-Reply-To: <20200413153526.805776-1-sean.v.kelley@linux.intel.com> References: <20200413153526.805776-1-sean.v.kelley@linux.intel.com> MIME-Version: 1.0 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Compute eXpress Link[1] is a new CPU interconnect created with workload accelerators in mind. The interconnect relies on PCIe electrical and physical interconnect for communication via a Flex Bus port which allows designs to choose between providing PCIe or CXL. This patch introduces basic support for lspci decode of CXL and builds upon the existing Designated Vendor-Specific support in lspci through identification of a Flex Bus capable Vendor ID. [1] https://www.computeexpresslink.org/ Signed-off-by: Sean V Kelley --- lib/header.h | 20 +++ ls-ecaps.c | 50 ++++++- tests/cap-dvsec-cxl | 340 ++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 409 insertions(+), 1 deletion(-) create mode 100644 tests/cap-dvsec-cxl diff --git a/lib/header.h b/lib/header.h index daeddeb..30b4eba 100644 --- a/lib/header.h +++ b/lib/header.h @@ -1045,6 +1045,26 @@ /* PCIe Designated Vendor-Specific Capability */ #define PCI_DVSEC_HEADER1 4 /* Designated Vendor-Specific Header 1 */ #define PCI_DVSEC_HEADER2 8 /* Designated Vendor-Specific Header 2 */ +#define PCI_DVSEC_FLEXBUS_ID 0 /* Flex Bus feature capability ID */ + +/* PCIe CXL Designated Vendor-Specific Capabilities, Control, Status */ +#define PCI_CXL_CAP 0x0a +#define PCI_CXL_CAP_CACHE 0x0001 +#define PCI_CXL_CAP_IO 0x0002 +#define PCI_CXL_CAP_MEM 0x0004 +#define PCI_CXL_CAP_MEM_HWINIT 0x0008 +#define PCI_CXL_CAP_HDM_CNT(x) (((x) & (3 << 4)) >> 4) +#define PCI_CXL_CAP_VIRAL 0x4000 +#define PCI_CXL_CTRL 0x0c +#define PCI_CXL_CTRL_CACHE 0x0001 +#define PCI_CXL_CTRL_IO 0x0002 +#define PCI_CXL_CTRL_MEM 0x0004 +#define PCI_CXL_CTRL_CACHE_SF_COV(x) (((x) & (0x1f << 3)) >> 3) +#define PCI_CXL_CTRL_CACHE_SF_GRAN(x) (((x) & (0x7 << 8)) >> 8) +#define PCI_CXL_CTRL_CACHE_CLN 0x0800 +#define PCI_CXL_CTRL_VIRAL 0x4000 +#define PCI_CXL_STATUS 0x0e +#define PCI_CXL_STATUS_VIRAL 0x4000 /* Access Control Services */ #define PCI_ACS_CAP 0x04 /* ACS Capability Register */ diff --git a/ls-ecaps.c b/ls-ecaps.c index b82d37e..57f649c 100644 --- a/ls-ecaps.c +++ b/ls-ecaps.c @@ -634,6 +634,51 @@ cap_rclink(struct device *d, int where) } } +static void +cap_cxl(struct device *d, int where) +{ + u16 l; + + printf("CXL Designated Vendor-Specific:\n"); + if (verbose < 2) + return; + + if (!config_fetch(d, where + PCI_CXL_CAP, 12)) + return; + + l = get_conf_word(d, where + PCI_CXL_CAP); + printf("\t\tCXLCap:\tCache%c IO%c Mem%c Mem HW Init%c HDMCount %d Viral%c\n", + FLAG(l, PCI_CXL_CAP_CACHE), FLAG(l, PCI_CXL_CAP_IO), FLAG(l, PCI_CXL_CAP_MEM), + FLAG(l, PCI_CXL_CAP_MEM_HWINIT), PCI_CXL_CAP_HDM_CNT(l), FLAG(l, PCI_CXL_CAP_VIRAL)); + + l = get_conf_word(d, where + PCI_CXL_CTRL); + printf("\t\tCXLCtl:\tCache%c IO%c Mem%c Cache SF Cov %d Cache SF Gran %d Cache Clean%c Viral%c\n", + FLAG(l, PCI_CXL_CTRL_CACHE), FLAG(l, PCI_CXL_CTRL_IO), FLAG(l, PCI_CXL_CTRL_MEM), + PCI_CXL_CTRL_CACHE_SF_COV(l), PCI_CXL_CTRL_CACHE_SF_GRAN(l), FLAG(l, PCI_CXL_CTRL_CACHE_CLN), + FLAG(l, PCI_CXL_CTRL_VIRAL)); + + l = get_conf_word(d, where + PCI_CXL_STATUS); + printf("\t\tCXLSta:\tViral%c\n", FLAG(l, PCI_CXL_STATUS_VIRAL)); +} + +static int +is_flexbus_cap(struct device *d, int where) +{ + u32 hdr; + u16 w; + + if (!config_fetch(d, where + PCI_DVSEC_HEADER1, 8)) + return 0; + + /* Check for Designated Vendor-Specific Flex Bus Capable ID */ + hdr = get_conf_long(d, where + PCI_DVSEC_HEADER2); + w = BITS(hdr, 0, 16); + if (w == PCI_DVSEC_FLEXBUS_ID) + return 1; + + return 0; +} + static void cap_dvsec(struct device *d, int where) { @@ -947,7 +992,10 @@ show_ext_caps(struct device *d, int type) printf("Readiness Time Reporting \n"); break; case PCI_EXT_CAP_ID_DVSEC: - cap_dvsec(d, where); + if (is_flexbus_cap(d, where)) + cap_cxl(d, where); + else + cap_dvsec(d, where); break; case PCI_EXT_CAP_ID_VF_REBAR: printf("VF Resizable BAR \n"); diff --git a/tests/cap-dvsec-cxl b/tests/cap-dvsec-cxl new file mode 100644 index 0000000..e5d2745 --- /dev/null +++ b/tests/cap-dvsec-cxl @@ -0,0 +1,340 @@ +6b:00.0 Unassigned class [ff00]: Intel Corporation Device 0d93 + Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr+ Stepping- SERR+ FastB2B- DisINTx- + Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- SERR- + Capabilities: [300 v1] Virtual Channel + Caps: LPEVC=0 RefClk=100ns PATEntryBits=1 + Arb: Fixed- WRR32- WRR64- WRR128- + Ctrl: ArbSelect=Fixed + Status: InProgress- + VC0: Caps: PATOffset=00 MaxTimeSlots=1 RejSnoopTrans- + Arb: Fixed- WRR32- WRR64- WRR128- TWRR128- WRR256- + Ctrl: Enable+ ID=0 ArbSelect=Fixed TC/VC=ff + Status: NegoPending- InProgress- + Capabilities: [550 v1] Multicast + McastCap: MaxGroups 64, WindowSz 1 (2 bytes) McastCtl: NumGroups 1, Enable- + McastBAR: IndexPos 0, BaseAddr 0000000000000000 + McastReceiveVec: 0000000000000000 + McastBlockAllVec: 0000000000000000 + McastBlockUntransVec: 0000000000000000 + Capabilities: [588 v1] Latency Tolerance Reporting + Max snoop latency: 0ns + Max no snoop latency: 0ns + Capabilities: [5b0 v1] Transaction Processing Hints + Extended requester support + Steering table in TPH capability structure + Capabilities: [6e0 v1] Address Translation Service (ATS) + ATSCap: Invalidate Queue Depth: 00 + ATSCtl: Enable-, Smallest Translation Unit: 00 + Capabilities: [700 v1] Resizable BAR + Capabilities: [714 v1] Secondary PCI Express + LnkCtl3: LnkEquIntrruptEn-, PerformEqu- + LaneErrStat: 0 + Capabilities: [b20 v1] Page Request Interface (PRI) + PRICtl: Enable- Reset- + PRISta: RF- UPRGI- Stopped+ + Page Request Capacity: 00000000, Page Request Allocation: 00000000 + Capabilities: [b40 v1] Process Address Space ID (PASID) + PASIDCap: Exec+ Priv+, Max PASID Width: 14 + PASIDCtl: Enable- Exec- Priv- + Capabilities: [b50 v1] Precision Time Measurement + PTMCap: Requester:- Responder:- Root:- + PTMClockGranularity: Unimplemented + PTMControl: Enabled:- RootSelected:- + PTMEffectiveGranularity: Unknown + Capabilities: [d00 v1] Vendor Specific Information: ID=0040 Rev=1 Len=04c + Capabilities: [e00 v1] CXL Designated Vendor-Specific: + CXLCap: Cache+ IO+ Mem+ Mem HW Init+ HDMCount 1 Viral- + CXLCtl: Cache+ IO+ Mem- Cache SF Cov 0 Cache SF Gran 0 Cache Clean- Viral- + CXLSta: Viral- + Capabilities: [e38 v1] Device Serial Number 12-34-56-78-90-00-00-00 +00: 86 80 93 0d 40 01 10 00 00 00 00 ff 00 00 80 00 +10: 00 00 10 b3 00 00 00 00 01 a4 00 00 00 00 00 00 +20: 08 00 00 b1 00 00 00 00 00 00 00 00 00 00 00 00 +30: 00 00 00 00 40 00 00 00 00 00 00 00 ff 01 00 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