From patchwork Tue Mar 31 10:33:39 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jon Hunter X-Patchwork-Id: 1264648 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.a=rsa-sha256 header.s=n1 header.b=SZjSHxaZ; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 48s5KQ3hDVz9sPJ for ; Tue, 31 Mar 2020 21:34:02 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730217AbgCaKeB (ORCPT ); Tue, 31 Mar 2020 06:34:01 -0400 Received: from hqnvemgate25.nvidia.com ([216.228.121.64]:1199 "EHLO hqnvemgate25.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729955AbgCaKeB (ORCPT ); Tue, 31 Mar 2020 06:34:01 -0400 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate25.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Tue, 31 Mar 2020 03:33:11 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Tue, 31 Mar 2020 03:34:00 -0700 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Tue, 31 Mar 2020 03:34:00 -0700 Received: from HQMAIL101.nvidia.com (172.20.187.10) by HQMAIL111.nvidia.com (172.20.187.18) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Tue, 31 Mar 2020 10:33:59 +0000 Received: from hqnvemgw03.nvidia.com (10.124.88.68) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Tue, 31 Mar 2020 10:33:59 +0000 Received: from moonraker.nvidia.com (Not Verified[10.26.72.141]) by hqnvemgw03.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Tue, 31 Mar 2020 03:33:59 -0700 From: Jon Hunter To: Thierry Reding CC: , , Jon Hunter Subject: [PATCH V2 1/3] soc/tegra: fuse: Add custom SoC attributes Date: Tue, 31 Mar 2020 11:33:39 +0100 Message-ID: <20200331103341.19571-1-jonathanh@nvidia.com> X-Mailer: git-send-email 2.17.1 X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1585650791; bh=qFWE9zolmdQM2J8Nj3r5beOLH+FBFxp93xzvODPAXQw=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: X-NVConfidentiality:MIME-Version:Content-Type; b=SZjSHxaZoL0mxcZjvs9FOxQN7vMbg+SMrJvDF926o3apt+czre+3RnzZ6kvwG0hj8 /9zorMrqS9bxlVKNx5CBlHDGMsrhoJMoh9vWsezOEWF46/apgzMAeDT6UM0AM1ZiNw 9pe9DchyjX6bNi0WyDWoZQ5ANm50Wo7yJonpc0o5BwTd75zliOBcqZ6kWmaQc9I3b3 5idjywo7QVBV5hzEmzOJdn57PF3pVMrd63butW7qWrPAhuyQFn9FpoiRnCsWxj0CjP G0akhgjhU5+8zHMBzvAkH9bRrGOVWxD5gCIs6b5YSCPMUgnbGTAjuhm3HQpsFf5av6 RMFx/B/kYi21A== Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Add a custom SoC attribute for Tegra to expose the HIDREV register fields to userspace via the sysfs. This register provides additional details about the type of device (eg, silicon, FPGA, etc) as well as revision. Exposing this information is useful for identifying the exact device revision and device type. For Tegra devices up until Tegra186, the majorrev and minorrev fields of the HIDREV register are used to determine the device revision and device type. For Tegra194, the majorrev and minorrev fields only determine the revision. Starting with Tegra194, there is an additional field, pre_si_platform (which occupies bits 20-23), that now determines device type. Therefore, for all Tegra devices, add a custom SoC attribute for the majorrev and minorrev fields and for Tegra194 add an additional attribute for the pre_si_platform field. Signed-off-by: Jon Hunter --- drivers/soc/tegra/fuse/fuse-tegra.c | 51 ++++++++++++++++++++++++++ drivers/soc/tegra/fuse/fuse-tegra20.c | 1 + drivers/soc/tegra/fuse/fuse-tegra30.c | 6 +++ drivers/soc/tegra/fuse/fuse.h | 8 ++++ drivers/soc/tegra/fuse/tegra-apbmisc.c | 10 +++++ 5 files changed, 76 insertions(+) diff --git a/drivers/soc/tegra/fuse/fuse-tegra.c b/drivers/soc/tegra/fuse/fuse-tegra.c index 802717b9f6a3..639734dca5df 100644 --- a/drivers/soc/tegra/fuse/fuse-tegra.c +++ b/drivers/soc/tegra/fuse/fuse-tegra.c @@ -300,6 +300,56 @@ static void tegra_enable_fuse_clk(void __iomem *base) writel(reg, base + 0x14); } +static ssize_t tegra_soc_majorrev_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + return sprintf(buf, "%d\n", tegra_get_major_rev()); +} + +static DEVICE_ATTR(majorrev, S_IRUGO, tegra_soc_majorrev_show, NULL); + +static ssize_t tegra_soc_minorrev_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + return sprintf(buf, "%d\n", tegra_get_minor_rev()); +} + +static DEVICE_ATTR(minorrev, S_IRUGO, tegra_soc_minorrev_show, NULL); + +static struct attribute *tegra_soc_attr[] = { + &dev_attr_majorrev.attr, + &dev_attr_minorrev.attr, + NULL, +}; + +const struct attribute_group tegra_soc_attr_group = { + .attrs = tegra_soc_attr, +}; + +#ifdef CONFIG_ARCH_TEGRA_194_SOC +static ssize_t tegra_soc_pre_si_plat_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + return sprintf(buf, "%d\n", (tegra_read_chipid() >> 20) & 0xf); +} + +static DEVICE_ATTR(pre_si_platform, S_IRUGO, tegra_soc_pre_si_plat_show, NULL); + +static struct attribute *tegra194_soc_attr[] = { + &dev_attr_majorrev.attr, + &dev_attr_minorrev.attr, + &dev_attr_pre_si_platform.attr, + NULL, +}; + +const struct attribute_group tegra194_soc_attr_group = { + .attrs = tegra194_soc_attr, +}; +#endif + struct device * __init tegra_soc_device_register(void) { struct soc_device_attribute *attr; @@ -312,6 +362,7 @@ struct device * __init tegra_soc_device_register(void) attr->family = kasprintf(GFP_KERNEL, "Tegra"); attr->revision = kasprintf(GFP_KERNEL, "%d", tegra_sku_info.revision); attr->soc_id = kasprintf(GFP_KERNEL, "%u", tegra_get_chip_id()); + attr->custom_attr_group = fuse->soc->soc_attr_group; dev = soc_device_register(attr); if (IS_ERR(dev)) { diff --git a/drivers/soc/tegra/fuse/fuse-tegra20.c b/drivers/soc/tegra/fuse/fuse-tegra20.c index d4aef9c4a94c..16aaa28573ac 100644 --- a/drivers/soc/tegra/fuse/fuse-tegra20.c +++ b/drivers/soc/tegra/fuse/fuse-tegra20.c @@ -164,4 +164,5 @@ const struct tegra_fuse_soc tegra20_fuse_soc = { .speedo_init = tegra20_init_speedo_data, .probe = tegra20_fuse_probe, .info = &tegra20_fuse_info, + .soc_attr_group = &tegra_soc_attr_group, }; diff --git a/drivers/soc/tegra/fuse/fuse-tegra30.c b/drivers/soc/tegra/fuse/fuse-tegra30.c index e6037f900fb7..85accef41fa1 100644 --- a/drivers/soc/tegra/fuse/fuse-tegra30.c +++ b/drivers/soc/tegra/fuse/fuse-tegra30.c @@ -111,6 +111,7 @@ const struct tegra_fuse_soc tegra30_fuse_soc = { .init = tegra30_fuse_init, .speedo_init = tegra30_init_speedo_data, .info = &tegra30_fuse_info, + .soc_attr_group = &tegra_soc_attr_group, }; #endif @@ -125,6 +126,7 @@ const struct tegra_fuse_soc tegra114_fuse_soc = { .init = tegra30_fuse_init, .speedo_init = tegra114_init_speedo_data, .info = &tegra114_fuse_info, + .soc_attr_group = &tegra_soc_attr_group, }; #endif @@ -205,6 +207,7 @@ const struct tegra_fuse_soc tegra124_fuse_soc = { .info = &tegra124_fuse_info, .lookups = tegra124_fuse_lookups, .num_lookups = ARRAY_SIZE(tegra124_fuse_lookups), + .soc_attr_group = &tegra_soc_attr_group, }; #endif @@ -290,6 +293,7 @@ const struct tegra_fuse_soc tegra210_fuse_soc = { .info = &tegra210_fuse_info, .lookups = tegra210_fuse_lookups, .num_lookups = ARRAY_SIZE(tegra210_fuse_lookups), + .soc_attr_group = &tegra_soc_attr_group, }; #endif @@ -319,6 +323,7 @@ const struct tegra_fuse_soc tegra186_fuse_soc = { .info = &tegra186_fuse_info, .lookups = tegra186_fuse_lookups, .num_lookups = ARRAY_SIZE(tegra186_fuse_lookups), + .soc_attr_group = &tegra_soc_attr_group, }; #endif @@ -348,5 +353,6 @@ const struct tegra_fuse_soc tegra194_fuse_soc = { .info = &tegra194_fuse_info, .lookups = tegra194_fuse_lookups, .num_lookups = ARRAY_SIZE(tegra194_fuse_lookups), + .soc_attr_group = &tegra194_soc_attr_group, }; #endif diff --git a/drivers/soc/tegra/fuse/fuse.h b/drivers/soc/tegra/fuse/fuse.h index 94a059e577a1..9d4fc315a007 100644 --- a/drivers/soc/tegra/fuse/fuse.h +++ b/drivers/soc/tegra/fuse/fuse.h @@ -32,6 +32,8 @@ struct tegra_fuse_soc { const struct nvmem_cell_lookup *lookups; unsigned int num_lookups; + + const struct attribute_group *soc_attr_group; }; struct tegra_fuse { @@ -64,6 +66,11 @@ void tegra_init_apbmisc(void); bool __init tegra_fuse_read_spare(unsigned int spare); u32 __init tegra_fuse_read_early(unsigned int offset); +u8 tegra_get_major_rev(void); +u8 tegra_get_minor_rev(void); + +extern const struct attribute_group tegra_soc_attr_group; + #ifdef CONFIG_ARCH_TEGRA_2x_SOC void tegra20_init_speedo_data(struct tegra_sku_info *sku_info); #endif @@ -110,6 +117,7 @@ extern const struct tegra_fuse_soc tegra186_fuse_soc; #ifdef CONFIG_ARCH_TEGRA_194_SOC extern const struct tegra_fuse_soc tegra194_fuse_soc; +extern const struct attribute_group tegra194_soc_attr_group; #endif #endif diff --git a/drivers/soc/tegra/fuse/tegra-apbmisc.c b/drivers/soc/tegra/fuse/tegra-apbmisc.c index 089d9340564b..44a154ca16b5 100644 --- a/drivers/soc/tegra/fuse/tegra-apbmisc.c +++ b/drivers/soc/tegra/fuse/tegra-apbmisc.c @@ -37,6 +37,16 @@ u8 tegra_get_chip_id(void) return (tegra_read_chipid() >> 8) & 0xff; } +u8 tegra_get_major_rev(void) +{ + return (tegra_read_chipid() >> 4) & 0xf; +} + +u8 tegra_get_minor_rev(void) +{ + return (tegra_read_chipid() >> 16) & 0xf; +} + u32 tegra_read_straps(void) { WARN(!chipid, "Tegra ABP MISC not yet available\n"); From patchwork Tue Mar 31 10:33:40 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jon Hunter X-Patchwork-Id: 1264650 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.a=rsa-sha256 header.s=n1 header.b=Ktp1j6+z; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 48s5Kb47mgz9sR4 for ; Tue, 31 Mar 2020 21:34:11 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730182AbgCaKeD (ORCPT ); Tue, 31 Mar 2020 06:34:03 -0400 Received: from hqnvemgate24.nvidia.com ([216.228.121.143]:6102 "EHLO hqnvemgate24.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729955AbgCaKeD (ORCPT ); Tue, 31 Mar 2020 06:34:03 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate24.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Tue, 31 Mar 2020 03:32:26 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Tue, 31 Mar 2020 03:34:02 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Tue, 31 Mar 2020 03:34:02 -0700 Received: from HQMAIL107.nvidia.com (172.20.187.13) by HQMAIL111.nvidia.com (172.20.187.18) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Tue, 31 Mar 2020 10:34:01 +0000 Received: from hqnvemgw03.nvidia.com (10.124.88.68) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Tue, 31 Mar 2020 10:34:01 +0000 Received: from moonraker.nvidia.com (Not Verified[10.26.72.141]) by hqnvemgw03.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Tue, 31 Mar 2020 03:34:01 -0700 From: Jon Hunter To: Thierry Reding CC: , , Jon Hunter Subject: [PATCH V2 2/3] soc/tegra: fuse: Correct Tegra194 revision Date: Tue, 31 Mar 2020 11:33:40 +0100 Message-ID: <20200331103341.19571-2-jonathanh@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200331103341.19571-1-jonathanh@nvidia.com> References: <20200331103341.19571-1-jonathanh@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1585650746; bh=BOpF4d4lG8wL2VaatutEQmw90UMrqfjLPHpA/upHK5c=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=Ktp1j6+zfUNqav2bzpC1klF8ZpDepj/+7ajvcLutj1cVemE6LKAuB6B3zk7QPV37J 5XsjkOyUNXALihjg4yyNT5fA4WOtmTnrdPRenZMP2XiEKtiaW29jF8TsBwcnQZNX/g Ls5VwAcAiLecaSLcsjj2XJjCv47fgox15Twxoy8AtDP3PfX8MOx+VUmr/3SgyptGFX 6UjYkNuQmkN4OJg628Wcy7fw0yHI8snKig1sECO2tZYlnZdqj504AFInwrFQ61biJ2 /PKikhUtIF+vj4rwUqFACVH1RBlFQA6kPU1L0d0MwIZ2mzJYH9ZfA22lGf9D7RjXgK Do68KTbQtoMZQ== Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Determining the revision for Tegra194 devices is slightly different from previous generations. For Tegra194, the majorrev field of the HIDREV register determines if the major revision is A, B, C, etc and the minorrev field determines if the minorrev is 01, 02, 03, etc. For Tegra194, there are two main revisions which are A01 and A02. Therefore, add a new function to correctly identify the revision for Tegra194 devices. Signed-off-by: Jon Hunter --- drivers/soc/tegra/fuse/fuse-tegra20.c | 3 ++- drivers/soc/tegra/fuse/fuse-tegra30.c | 8 ++++++- drivers/soc/tegra/fuse/fuse.h | 2 ++ drivers/soc/tegra/fuse/tegra-apbmisc.c | 29 ++++++++++++++++++++++++++ 4 files changed, 40 insertions(+), 2 deletions(-) diff --git a/drivers/soc/tegra/fuse/fuse-tegra20.c b/drivers/soc/tegra/fuse/fuse-tegra20.c index 16aaa28573ac..d2838503e146 100644 --- a/drivers/soc/tegra/fuse/fuse-tegra20.c +++ b/drivers/soc/tegra/fuse/fuse-tegra20.c @@ -154,13 +154,14 @@ static void __init tegra20_fuse_init(struct tegra_fuse *fuse) { fuse->read_early = tegra20_fuse_read_early; - tegra_init_revision(); + fuse->soc->revision_init(); fuse->soc->speedo_init(&tegra_sku_info); tegra20_fuse_add_randomness(); } const struct tegra_fuse_soc tegra20_fuse_soc = { .init = tegra20_fuse_init, + .revision_init = tegra_init_revision, .speedo_init = tegra20_init_speedo_data, .probe = tegra20_fuse_probe, .info = &tegra20_fuse_info, diff --git a/drivers/soc/tegra/fuse/fuse-tegra30.c b/drivers/soc/tegra/fuse/fuse-tegra30.c index 85accef41fa1..9804b0a6e328 100644 --- a/drivers/soc/tegra/fuse/fuse-tegra30.c +++ b/drivers/soc/tegra/fuse/fuse-tegra30.c @@ -91,7 +91,7 @@ static void __init tegra30_fuse_init(struct tegra_fuse *fuse) fuse->read_early = tegra30_fuse_read_early; fuse->read = tegra30_fuse_read; - tegra_init_revision(); + fuse->soc->revision_init(); if (fuse->soc->speedo_init) fuse->soc->speedo_init(&tegra_sku_info); @@ -110,6 +110,7 @@ static const struct tegra_fuse_info tegra30_fuse_info = { const struct tegra_fuse_soc tegra30_fuse_soc = { .init = tegra30_fuse_init, .speedo_init = tegra30_init_speedo_data, + .revision_init = tegra_init_revision, .info = &tegra30_fuse_info, .soc_attr_group = &tegra_soc_attr_group, }; @@ -125,6 +126,7 @@ static const struct tegra_fuse_info tegra114_fuse_info = { const struct tegra_fuse_soc tegra114_fuse_soc = { .init = tegra30_fuse_init, .speedo_init = tegra114_init_speedo_data, + .revision_init = tegra_init_revision, .info = &tegra114_fuse_info, .soc_attr_group = &tegra_soc_attr_group, }; @@ -204,6 +206,7 @@ static const struct tegra_fuse_info tegra124_fuse_info = { const struct tegra_fuse_soc tegra124_fuse_soc = { .init = tegra30_fuse_init, .speedo_init = tegra124_init_speedo_data, + .revision_init = tegra_init_revision, .info = &tegra124_fuse_info, .lookups = tegra124_fuse_lookups, .num_lookups = ARRAY_SIZE(tegra124_fuse_lookups), @@ -290,6 +293,7 @@ static const struct tegra_fuse_info tegra210_fuse_info = { const struct tegra_fuse_soc tegra210_fuse_soc = { .init = tegra30_fuse_init, .speedo_init = tegra210_init_speedo_data, + .revision_init = tegra_init_revision, .info = &tegra210_fuse_info, .lookups = tegra210_fuse_lookups, .num_lookups = ARRAY_SIZE(tegra210_fuse_lookups), @@ -320,6 +324,7 @@ static const struct tegra_fuse_info tegra186_fuse_info = { const struct tegra_fuse_soc tegra186_fuse_soc = { .init = tegra30_fuse_init, + .revision_init = tegra_init_revision, .info = &tegra186_fuse_info, .lookups = tegra186_fuse_lookups, .num_lookups = ARRAY_SIZE(tegra186_fuse_lookups), @@ -350,6 +355,7 @@ static const struct tegra_fuse_info tegra194_fuse_info = { const struct tegra_fuse_soc tegra194_fuse_soc = { .init = tegra30_fuse_init, + .revision_init = tegra194_init_revision, .info = &tegra194_fuse_info, .lookups = tegra194_fuse_lookups, .num_lookups = ARRAY_SIZE(tegra194_fuse_lookups), diff --git a/drivers/soc/tegra/fuse/fuse.h b/drivers/soc/tegra/fuse/fuse.h index 9d4fc315a007..49b38d934ef7 100644 --- a/drivers/soc/tegra/fuse/fuse.h +++ b/drivers/soc/tegra/fuse/fuse.h @@ -26,6 +26,7 @@ struct tegra_fuse_info { struct tegra_fuse_soc { void (*init)(struct tegra_fuse *fuse); void (*speedo_init)(struct tegra_sku_info *info); + void (*revision_init)(void); int (*probe)(struct tegra_fuse *fuse); const struct tegra_fuse_info *info; @@ -61,6 +62,7 @@ struct tegra_fuse { }; void tegra_init_revision(void); +void tegra194_init_revision(void); void tegra_init_apbmisc(void); bool __init tegra_fuse_read_spare(unsigned int spare); diff --git a/drivers/soc/tegra/fuse/tegra-apbmisc.c b/drivers/soc/tegra/fuse/tegra-apbmisc.c index 44a154ca16b5..08a2522bd4de 100644 --- a/drivers/soc/tegra/fuse/tegra-apbmisc.c +++ b/drivers/soc/tegra/fuse/tegra-apbmisc.c @@ -108,6 +108,35 @@ void __init tegra_init_revision(void) tegra_sku_info.sku_id = tegra_fuse_read_early(FUSE_SKU_INFO); } +void __init tegra194_init_revision(void) +{ + u8 major_rev, minor_rev; + + major_rev = tegra_get_major_rev(); + minor_rev = tegra_get_minor_rev(); + + switch (major_rev) { + case 1: + switch (minor_rev) { + case 1: + tegra_sku_info.revision = TEGRA_REVISION_A01; + break; + case 2: + tegra_sku_info.revision = TEGRA_REVISION_A02; + break; + default: + tegra_sku_info.revision = TEGRA_REVISION_UNKNOWN; + break; + } + break; + default: + tegra_sku_info.revision = TEGRA_REVISION_UNKNOWN; + break; + } + + tegra_sku_info.sku_id = tegra_fuse_read_early(FUSE_SKU_INFO); +} + void __init tegra_init_apbmisc(void) { void __iomem *apbmisc_base, *strapping_base; From patchwork Tue Mar 31 10:33:41 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jon Hunter X-Patchwork-Id: 1264649 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.a=rsa-sha256 header.s=n1 header.b=rTTGFtf2; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 48s5KW5pM8z9sR4 for ; Tue, 31 Mar 2020 21:34:07 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730408AbgCaKeG (ORCPT ); Tue, 31 Mar 2020 06:34:06 -0400 Received: from hqnvemgate26.nvidia.com ([216.228.121.65]:14019 "EHLO hqnvemgate26.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730076AbgCaKeE (ORCPT ); Tue, 31 Mar 2020 06:34:04 -0400 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate26.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Tue, 31 Mar 2020 03:33:50 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Tue, 31 Mar 2020 03:34:03 -0700 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Tue, 31 Mar 2020 03:34:03 -0700 Received: from HQMAIL105.nvidia.com (172.20.187.12) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Tue, 31 Mar 2020 10:34:03 +0000 Received: from hqnvemgw03.nvidia.com (10.124.88.68) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Tue, 31 Mar 2020 10:34:02 +0000 Received: from moonraker.nvidia.com (Not Verified[10.26.72.141]) by hqnvemgw03.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Tue, 31 Mar 2020 03:34:02 -0700 From: Jon Hunter To: Thierry Reding CC: , , Jon Hunter Subject: [PATCH V2 3/3] soc/tegra: fuse: Trivial clean-up of tegra_init_revision() Date: Tue, 31 Mar 2020 11:33:41 +0100 Message-ID: <20200331103341.19571-3-jonathanh@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200331103341.19571-1-jonathanh@nvidia.com> References: <20200331103341.19571-1-jonathanh@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1585650830; bh=Ch98wVkeNDBu45J5iyMXFZdcYJMhALREZUPAvteVPdw=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=rTTGFtf2o6qXmQqa/jmaE4BrcHBdOYQjoxGUTD7l5WZuhZmRLuiiJpljHbstpF61t JuKfu1i772yYMQI50xme4gLxcUceDJejXnhFPXpYCiv3erPelks3VfzHGvAZ4/2dCg uFR9jxD/uODZb0vRapCiJemobXPIVdrnf7FrBIAd0EL7mkxtF0Mf6tTM92v7kjM1uI OM4m40wJaKfSkirKm1G3pVUOKTUerJ1x72PZEvTyyqvS52Zgisoc9VsvbFj+EsH2n0 QMFp5ymo8xhoIOgAM4tkmG1oiNmZbvMxE0RAbYApturPuhuiLpLQoU1WzI93PGyXWe ypHE7BGLtJbYg== Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Clean-up the tegra_init_revision() function by removing the 'rev' variable which is not needed and use the newly added helper function tegra_get_minor_rev() to get the minor revision. Signed-off-by: Jon Hunter --- drivers/soc/tegra/fuse/tegra-apbmisc.c | 22 +++++++++------------- 1 file changed, 9 insertions(+), 13 deletions(-) diff --git a/drivers/soc/tegra/fuse/tegra-apbmisc.c b/drivers/soc/tegra/fuse/tegra-apbmisc.c index 08a2522bd4de..5b1238c2b187 100644 --- a/drivers/soc/tegra/fuse/tegra-apbmisc.c +++ b/drivers/soc/tegra/fuse/tegra-apbmisc.c @@ -75,36 +75,32 @@ static const struct of_device_id apbmisc_match[] __initconst = { void __init tegra_init_revision(void) { - u32 id, chip_id, minor_rev; - int rev; + u8 chip_id, minor_rev; - id = tegra_read_chipid(); - chip_id = (id >> 8) & 0xff; - minor_rev = (id >> 16) & 0xf; + chip_id = tegra_get_chip_id(); + minor_rev = tegra_get_minor_rev(); switch (minor_rev) { case 1: - rev = TEGRA_REVISION_A01; + tegra_sku_info.revision = TEGRA_REVISION_A01; break; case 2: - rev = TEGRA_REVISION_A02; + tegra_sku_info.revision = TEGRA_REVISION_A02; break; case 3: if (chip_id == TEGRA20 && (tegra_fuse_read_spare(18) || tegra_fuse_read_spare(19))) - rev = TEGRA_REVISION_A03p; + tegra_sku_info.revision = TEGRA_REVISION_A03p; else - rev = TEGRA_REVISION_A03; + tegra_sku_info.revision = TEGRA_REVISION_A03; break; case 4: - rev = TEGRA_REVISION_A04; + tegra_sku_info.revision = TEGRA_REVISION_A04; break; default: - rev = TEGRA_REVISION_UNKNOWN; + tegra_sku_info.revision = TEGRA_REVISION_UNKNOWN; } - tegra_sku_info.revision = rev; - tegra_sku_info.sku_id = tegra_fuse_read_early(FUSE_SKU_INFO); }