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[58.96.106.158]) by smtp.gmail.com with ESMTPSA id 15sm47025339pfp.125.2020.03.11.19.48.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Mar 2020 19:48:54 -0700 (PDT) Received: by bubble.grove.modra.org (Postfix, from userid 1000) id 0F25D81DCC; Thu, 12 Mar 2020 13:18:51 +1030 (ACDT) Date: Thu, 12 Mar 2020 13:18:50 +1030 To: gcc-patches@gcc.gnu.org Subject: [RS6000] make PLT loads volatile Message-ID: <20200312024850.GE5384@bubble.grove.modra.org> MIME-Version: 1.0 Content-Disposition: inline User-Agent: Mutt/1.9.4 (2018-02-28) X-Spam-Status: No, score=-27.1 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Alan Modra via Gcc-patches From: "Li, Pan2 via Gcc-patches" Reply-To: Alan Modra Cc: Segher Boessenkool Errors-To: gcc-patches-bounces@gcc.gnu.org Sender: "Gcc-patches" With lazy PLT resolution the first load of a PLT entry may be a value pointing at a resolver stub. gcc's loop processing can result in the PLT load in inline PLT calls being hoisted out of a loop in the mistaken idea that this is an optimisation. It isn't. If the value hoisted was that for a resolver stub then every call to that function in the loop will go via the resolver, slowing things down quite dramatically. The PLT really is volatile, so teach gcc about that. Bootstrapped and regression tested on powerpc64le-linux and tested with a spec build using -mlongcalls. OK for mainline? * config/rs6000/rs6000.c (rs6000_longcall_ref): Use unspec_volatile for PLT16_LO and PLT_PCREL. * config/rs6000/rs6000.md (UNSPEC_PLT16_LO, UNSPEC_PLT_PCREL): Remove. (UNSPECV_PLT16_LO, UNSPECV_PLT_PCREL): Define. (pltseq_plt16_lo_, pltseq_plt_pcrel): Use unspec_volatile. diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index 46b7dec2abd..2d6790877fa 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -19264,8 +19264,9 @@ rs6000_longcall_ref (rtx call_ref, rtx arg) if (rs6000_pcrel_p (cfun)) { rtx reg = gen_rtx_REG (Pmode, regno); - rtx u = gen_rtx_UNSPEC (Pmode, gen_rtvec (3, base, call_ref, arg), - UNSPEC_PLT_PCREL); + rtx u = gen_rtx_UNSPEC_VOLATILE (Pmode, + gen_rtvec (3, base, call_ref, arg), + UNSPECV_PLT_PCREL); emit_insn (gen_rtx_SET (reg, u)); return reg; } @@ -19284,8 +19285,9 @@ rs6000_longcall_ref (rtx call_ref, rtx arg) rtx reg = gen_rtx_REG (Pmode, regno); rtx hi = gen_rtx_UNSPEC (Pmode, gen_rtvec (3, base, call_ref, arg), UNSPEC_PLT16_HA); - rtx lo = gen_rtx_UNSPEC (Pmode, gen_rtvec (3, reg, call_ref, arg), - UNSPEC_PLT16_LO); + rtx lo = gen_rtx_UNSPEC_VOLATILE (Pmode, + gen_rtvec (3, reg, call_ref, arg), + UNSPECV_PLT16_LO); emit_insn (gen_rtx_SET (reg, hi)); emit_insn (gen_rtx_SET (reg, lo)); return reg; diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index ad88b6783af..5a8e9de670b 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -148,8 +148,6 @@ UNSPEC_SI_FROM_SF UNSPEC_PLTSEQ UNSPEC_PLT16_HA - UNSPEC_PLT16_LO - UNSPEC_PLT_PCREL ]) ;; @@ -178,6 +176,8 @@ UNSPECV_MTFSB1 ; Set FPSCR Field bit to 1 UNSPECV_SPLIT_STACK_RETURN ; A camouflaged return UNSPECV_SPEC_BARRIER ; Speculation barrier + UNSPECV_PLT16_LO + UNSPECV_PLT_PCREL ]) ; The three different kinds of epilogue. @@ -10359,10 +10359,10 @@ (define_insn "*pltseq_plt16_lo_" [(set (match_operand:P 0 "gpc_reg_operand" "=r") - (unspec:P [(match_operand:P 1 "gpc_reg_operand" "b") - (match_operand:P 2 "symbol_ref_operand" "s") - (match_operand:P 3 "" "")] - UNSPEC_PLT16_LO))] + (unspec_volatile:P [(match_operand:P 1 "gpc_reg_operand" "b") + (match_operand:P 2 "symbol_ref_operand" "s") + (match_operand:P 3 "" "")] + UNSPECV_PLT16_LO))] "TARGET_PLTSEQ" { return rs6000_pltseq_template (operands, RS6000_PLTSEQ_PLT16_LO); @@ -10382,10 +10382,10 @@ (define_insn "*pltseq_plt_pcrel" [(set (match_operand:P 0 "gpc_reg_operand" "=r") - (unspec:P [(match_operand:P 1 "" "") - (match_operand:P 2 "symbol_ref_operand" "s") - (match_operand:P 3 "" "")] - UNSPEC_PLT_PCREL))] + (unspec_volatile:P [(match_operand:P 1 "" "") + (match_operand:P 2 "symbol_ref_operand" "s") + (match_operand:P 3 "" "")] + UNSPECV_PLT_PCREL))] "HAVE_AS_PLTSEQ && TARGET_ELF && rs6000_pcrel_p (cfun)" {