From patchwork Sun Mar 1 12:12:30 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hauke Mehrtens X-Patchwork-Id: 1247279 X-Patchwork-Delegate: hauke@hauke-m.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.openwrt.org (client-ip=2607:7c80:54:e::133; helo=bombadil.infradead.org; envelope-from=openwrt-devel-bounces+incoming=patchwork.ozlabs.org@lists.openwrt.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=hauke-m.de Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=lists.infradead.org header.i=@lists.infradead.org header.a=rsa-sha256 header.s=bombadil.20170209 header.b=H+sd5DJ+; dkim-atps=neutral Received: from bombadil.infradead.org (bombadil.infradead.org [IPv6:2607:7c80:54:e::133]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 48Vhxk5jRGz9sSH for ; Sun, 1 Mar 2020 23:13:14 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Subject:MIME-Version:References: In-Reply-To:Message-Id:Date:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=qtevSULsJQFZsGXVCohBUpBTeKQ38qQ9DWgw0CQ3uEY=; b=H+sd5DJ+T/2AOY /a8SH99Pki+Oa3buahhE5DzDAWZZh4i9Qg/vucf+R/p5MeZ5BVumPDoaAQ1R3w1LCs0W4y1mK1r18 zs86rNNx9ZJO+5XQ95dt2DheU9OmlpXr/YZaMGC5a2gSSjxvmaRfk5npXA213LWcvLO+Ba1HVTQiT 2d9SQMgR/1WJ931r4kDfJj5+zc4HRZno2gAFnYyffi7oaTpnDPeiB6YEANKv8EcRGhITy11yWfMvk +dGUOOn4vNQuSAZrmfByQtVeoIFMDJbCaOVQucApcmnBa33iE89UMYT/A+KdKwNdtSWvSSFiiWbzO VzfO+hBZ59hKV1VLu/gA==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1j8NT4-0006ri-Dw; Sun, 01 Mar 2020 12:13:10 +0000 Received: from mout-p-101.mailbox.org ([80.241.56.151]) by bombadil.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1j8NSl-0006cc-PM for openwrt-devel@lists.openwrt.org; Sun, 01 Mar 2020 12:12:54 +0000 Received: from smtp2.mailbox.org (smtp2.mailbox.org [80.241.60.241]) (using TLSv1.2 with cipher ECDHE-RSA-CHACHA20-POLY1305 (256/256 bits)) (No client certificate requested) by mout-p-101.mailbox.org (Postfix) with ESMTPS id 48VhxF30K1zKmVC; Sun, 1 Mar 2020 13:12:49 +0100 (CET) X-Virus-Scanned: amavisd-new at heinlein-support.de Received: from smtp2.mailbox.org ([80.241.60.241]) by hefe.heinlein-support.de (hefe.heinlein-support.de [91.198.250.172]) (amavisd-new, port 10030) with ESMTP id ogVdCWqt6jvm; Sun, 1 Mar 2020 13:12:47 +0100 (CET) From: Hauke Mehrtens To: openwrt-devel@lists.openwrt.org Date: Sun, 1 Mar 2020 13:12:30 +0100 Message-Id: <20200301121241.5545-2-hauke@hauke-m.de> In-Reply-To: <20200301121241.5545-1-hauke@hauke-m.de> References: <20200301121241.5545-1-hauke@hauke-m.de> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200301_041252_171724_030EF1CD X-CRM114-Status: GOOD ( 10.78 ) X-Spam-Score: 0.5 (/) X-Spam-Report: SpamAssassin version 3.4.3 on bombadil.infradead.org summary: Content analysis details: (0.5 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at https://www.dnswl.org/, low trust [80.241.56.151 listed in list.dnswl.org] 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.0 SPF_PASS SPF: sender matches SPF record 1.2 UPPERCASE_75_100 message body is 75-100% uppercase Subject: [OpenWrt-Devel] [PATCH 01/12] armvirt: Remove kernel 4.14 support X-BeenThere: openwrt-devel@lists.openwrt.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: hauke@hauke-m.de Sender: "openwrt-devel" Errors-To: openwrt-devel-bounces+incoming=patchwork.ozlabs.org@lists.openwrt.org This target was switched to kernel 4.19 more than 6 months ago in commit f342ffd300da ("treewide: kernel: bump some targets to 4.19") and now with kernel 5.4 support being added it gets harder to support kernel 4.14 in addition to kernel 4.19 and 5.4. Signed-off-by: Hauke Mehrtens Acked-by: Yousong Zhou --- target/linux/armvirt/32/config-4.14 | 121 ------------------- target/linux/armvirt/64/config-4.14 | 179 --------------------------- target/linux/armvirt/config-4.14 | 181 ---------------------------- 3 files changed, 481 deletions(-) delete mode 100644 target/linux/armvirt/32/config-4.14 delete mode 100644 target/linux/armvirt/64/config-4.14 delete mode 100644 target/linux/armvirt/config-4.14 diff --git a/target/linux/armvirt/32/config-4.14 b/target/linux/armvirt/32/config-4.14 deleted file mode 100644 index a31488749cc5..000000000000 --- a/target/linux/armvirt/32/config-4.14 +++ /dev/null @@ -1,121 +0,0 @@ -CONFIG_ALIGNMENT_TRAP=y -# CONFIG_ARCH_AXXIA is not set -CONFIG_ARCH_HAS_DEBUG_VIRTUAL=y -CONFIG_ARCH_HAS_SET_MEMORY=y -CONFIG_ARCH_HAS_STRICT_KERNEL_RWX=y -CONFIG_ARCH_HAS_STRICT_MODULE_RWX=y -CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y -CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y -CONFIG_ARCH_MULTIPLATFORM=y -# CONFIG_ARCH_MULTI_CPU_AUTO is not set -CONFIG_ARCH_MULTI_V6_V7=y -CONFIG_ARCH_MULTI_V7=y -CONFIG_ARCH_NR_GPIO=0 -CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y -CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y -CONFIG_ARCH_PHYS_ADDR_T_64BIT=y -# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set -# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set -CONFIG_ARCH_SUPPORTS_UPROBES=y -CONFIG_ARCH_USE_BUILTIN_BSWAP=y -CONFIG_ARCH_VIRT=y -CONFIG_ARCH_WANT_GENERAL_HUGETLB=y -CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y -CONFIG_ARM=y -CONFIG_ARM_CPU_SUSPEND=y -CONFIG_ARM_GIC_V3_ITS=y -CONFIG_ARM_HAS_SG_CHAIN=y -CONFIG_ARM_HEAVY_MB=y -CONFIG_ARM_L1_CACHE_SHIFT=6 -CONFIG_ARM_L1_CACHE_SHIFT_6=y -CONFIG_ARM_LPAE=y -CONFIG_ARM_PATCH_IDIV=y -CONFIG_ARM_PATCH_PHYS_VIRT=y -CONFIG_ARM_PSCI=y -CONFIG_ARM_THUMB=y -# CONFIG_ARM_THUMBEE is not set -CONFIG_ARM_VIRT_EXT=y -CONFIG_AUTO_ZRELADDR=y -CONFIG_BLK_MQ_VIRTIO=y -CONFIG_BLK_SCSI_REQUEST=y -CONFIG_CACHE_L2X0=y -CONFIG_CPU_32v6K=y -CONFIG_CPU_32v7=y -CONFIG_CPU_ABRT_EV7=y -# CONFIG_CPU_BPREDICT_DISABLE is not set -CONFIG_CPU_CACHE_V7=y -CONFIG_CPU_CACHE_VIPT=y -CONFIG_CPU_COPY_V6=y -CONFIG_CPU_CP15=y -CONFIG_CPU_CP15_MMU=y -CONFIG_CPU_HAS_ASID=y -# CONFIG_CPU_ICACHE_DISABLE is not set -CONFIG_CPU_PABRT_V7=y -CONFIG_CPU_SPECTRE=y -CONFIG_CPU_THUMB_CAPABLE=y -CONFIG_CPU_TLB_V7=y -CONFIG_CPU_V7=y -CONFIG_DEBUG_BUGVERBOSE=y -CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" -# CONFIG_DEBUG_UART_8250 is not set -# CONFIG_DEBUG_USER is not set -CONFIG_EDAC_ATOMIC_SCRUB=y -CONFIG_GENERIC_ARCH_TOPOLOGY=y -CONFIG_GENERIC_CPU_AUTOPROBE=y -CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y -# CONFIG_GRO_CELLS is not set -CONFIG_HARDEN_BRANCH_PREDICTOR=y -CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE=y -CONFIG_HAVE_ARM_ARCH_TIMER=y -CONFIG_HAVE_DYNAMIC_FTRACE_WITH_REGS=y -CONFIG_HAVE_EBPF_JIT=y -CONFIG_HAVE_GENERIC_GUP=y -CONFIG_HAVE_IDE=y -CONFIG_HAVE_MOD_ARCH_SPECIFIC=y -CONFIG_HAVE_OPROFILE=y -CONFIG_HAVE_OPTPROBES=y -CONFIG_HAVE_PROC_CPU=y -CONFIG_HAVE_RCU_TABLE_FREE=y -CONFIG_HAVE_SMP=y -# CONFIG_HUGETLBFS is not set -CONFIG_HZ_FIXED=0 -CONFIG_HZ_PERIODIC=y -# CONFIG_MDIO_BUS is not set -CONFIG_MIGHT_HAVE_CACHE_L2X0=y -CONFIG_MIGHT_HAVE_PCI=y -CONFIG_MIGRATION=y -CONFIG_MODULES_USE_ELF_REL=y -CONFIG_MULTI_IRQ_HANDLER=y -CONFIG_NEON=y -CONFIG_OLD_SIGACTION=y -CONFIG_OUTER_CACHE=y -CONFIG_OUTER_CACHE_SYNC=y -CONFIG_PAGE_OFFSET=0xC0000000 -CONFIG_PERF_USE_VMALLOC=y -CONFIG_PGTABLE_LEVELS=3 -CONFIG_PHYS_ADDR_T_64BIT=y -# CONFIG_PL310_ERRATA_588369 is not set -# CONFIG_PL310_ERRATA_727915 is not set -# CONFIG_PL310_ERRATA_753970 is not set -# CONFIG_PL310_ERRATA_769419 is not set -CONFIG_RCU_NEED_SEGCBLIST=y -CONFIG_RTC_MC146818_LIB=y -CONFIG_SERIAL_OF_PLATFORM=y -CONFIG_SG_POOL=y -CONFIG_SMP_ON_UP=y -CONFIG_SWP_EMULATE=y -CONFIG_SYS_SUPPORTS_APM_EMULATION=y -CONFIG_SYS_SUPPORTS_HUGETLBFS=y -# CONFIG_THUMB2_KERNEL is not set -CONFIG_TIMER_OF=y -CONFIG_TIMER_PROBE=y -CONFIG_TREE_SRCU=y -CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" -CONFIG_USE_OF=y -CONFIG_VECTORS_BASE=0xffff0000 -CONFIG_VFP=y -CONFIG_VFPv3=y -CONFIG_XZ_DEC_ARM=y -CONFIG_XZ_DEC_BCJ=y -CONFIG_ZBOOT_ROM_BSS=0 -CONFIG_ZBOOT_ROM_TEXT=0 diff --git a/target/linux/armvirt/64/config-4.14 b/target/linux/armvirt/64/config-4.14 deleted file mode 100644 index a70cd20f7efe..000000000000 --- a/target/linux/armvirt/64/config-4.14 +++ /dev/null @@ -1,179 +0,0 @@ -CONFIG_64BIT=y -# CONFIG_ACPI is not set -CONFIG_ARCH_DMA_ADDR_T_64BIT=y -CONFIG_ARCH_HAS_CACHE_LINE_SIZE=y -CONFIG_ARCH_HAS_GIGANTIC_PAGE=y -CONFIG_ARCH_HAS_HOLES_MEMORYMODEL=y -CONFIG_ARCH_HAS_KCOV=y -CONFIG_ARCH_MMAP_RND_BITS=18 -CONFIG_ARCH_MMAP_RND_BITS_MAX=24 -CONFIG_ARCH_MMAP_RND_BITS_MIN=18 -CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11 -CONFIG_ARCH_PHYS_ADDR_T_64BIT=y -CONFIG_ARCH_SELECT_MEMORY_MODEL=y -CONFIG_ARCH_SPARSEMEM_DEFAULT=y -CONFIG_ARCH_SPARSEMEM_ENABLE=y -CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y -CONFIG_ARCH_SUPPORTS_NUMA_BALANCING=y -CONFIG_ARCH_VEXPRESS=y -CONFIG_ARCH_WANT_COMPAT_IPC_PARSE_VERSION=y -CONFIG_ARCH_WANT_FRAME_POINTERS=y -CONFIG_ARCH_WANT_HUGE_PMD_SHARE=y -CONFIG_ARM64=y -# CONFIG_ARM64_16K_PAGES is not set -CONFIG_ARM64_4K_PAGES=y -# CONFIG_ARM64_64K_PAGES is not set -CONFIG_ARM64_CONT_SHIFT=4 -CONFIG_ARM64_CRYPTO=y -CONFIG_ARM64_ERRATUM_819472=y -CONFIG_ARM64_ERRATUM_824069=y -CONFIG_ARM64_ERRATUM_826319=y -CONFIG_ARM64_ERRATUM_827319=y -CONFIG_ARM64_ERRATUM_832075=y -CONFIG_ARM64_ERRATUM_843419=y -CONFIG_ARM64_HW_AFDBM=y -# CONFIG_ARM64_LSE_ATOMICS is not set -CONFIG_ARM64_MODULE_CMODEL_LARGE=y -CONFIG_ARM64_PAGE_SHIFT=12 -CONFIG_ARM64_PAN=y -# CONFIG_ARM64_PMEM is not set -# CONFIG_ARM64_PTDUMP is not set -# CONFIG_ARM64_PTDUMP_DEBUGFS is not set -# CONFIG_ARM64_RANDOMIZE_TEXT_OFFSET is not set -CONFIG_ARM64_SSBD=y -CONFIG_ARM64_UAO=y -CONFIG_ARM64_VA_BITS=39 -CONFIG_ARM64_VA_BITS_39=y -# CONFIG_ARM64_VA_BITS_48 is not set -CONFIG_ARM64_VHE=y -CONFIG_ARM_GIC_V3_ITS=y -CONFIG_ARM_PMU=y -# CONFIG_ARM_SBSA_WATCHDOG is not set -CONFIG_ATOMIC64_SELFTEST=y -CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y -CONFIG_BACKLIGHT_CLASS_DEVICE=y -CONFIG_BACKLIGHT_LCD_SUPPORT=y -CONFIG_BOUNCE=y -CONFIG_CLKSRC_MMIO=y -CONFIG_CLKSRC_VERSATILE=y -CONFIG_CLK_SP810=y -CONFIG_CLK_VEXPRESS_OSC=y -CONFIG_COMMON_CLK_VERSATILE=y -# CONFIG_COMMON_CLK_XGENE is not set -# CONFIG_CPU_BIG_ENDIAN is not set -CONFIG_CPU_IDLE=y -# CONFIG_CPU_IDLE_GOV_LADDER is not set -CONFIG_CPU_IDLE_GOV_MENU=y -CONFIG_CPU_PM=y -CONFIG_CRYPTO_ABLK_HELPER=y -CONFIG_CRYPTO_AES_ARM64_BS=y -CONFIG_CRYPTO_AES_ARM64_CE=y -CONFIG_CRYPTO_AES_ARM64_CE_BLK=y -CONFIG_CRYPTO_AES_ARM64_CE_CCM=y -CONFIG_CRYPTO_AES_ARM64_NEON_BLK=y -CONFIG_CRYPTO_CHACHA20_NEON=y -CONFIG_CRYPTO_CRC32_ARM64=y -CONFIG_CRYPTO_CRC32_ARM64_CE=y -CONFIG_CRYPTO_CRYPTD=y -# CONFIG_CRYPTO_DEV_CAVIUM_ZIP is not set -CONFIG_CRYPTO_GHASH_ARM64_CE=y -CONFIG_CRYPTO_SHA1_ARM64_CE=y -CONFIG_CRYPTO_SHA2_ARM64_CE=y -CONFIG_CRYPTO_SHA512_ARM64=y -# CONFIG_DEBUG_ALIGN_RODATA is not set -CONFIG_DEBUG_BUGVERBOSE=y -CONFIG_DEBUG_RODATA=y -CONFIG_DRM=y -CONFIG_DRM_QXL=y -CONFIG_DRM_BOCHS=y -CONFIG_DRM_VIRTIO_GPU=y -CONFIG_FB=y -CONFIG_FB_ARMCLCD=y -CONFIG_FB_CFB_COPYAREA=y -CONFIG_FB_CFB_FILLRECT=y -CONFIG_FB_CFB_IMAGEBLIT=y -CONFIG_FB_CMDLINE=y -CONFIG_FB_MODE_HELPERS=y -CONFIG_FSL_ERRATUM_A008585=y -# CONFIG_FSL_MC_BUS is not set -CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y -CONFIG_GENERIC_CPU_AUTOPROBE=y -CONFIG_GENERIC_CSUM=y -CONFIG_GENERIC_TIME_VSYSCALL=y -CONFIG_GPIO_GENERIC=y -CONFIG_GPIO_GENERIC_PLATFORM=y -CONFIG_HARDEN_BRANCH_PREDICTOR=y -CONFIG_HAVE_ALIGNED_STRUCT_PAGE=y -CONFIG_HAVE_ARCH_HUGE_VMAP=y -CONFIG_HAVE_ARCH_KASAN=y -CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE=y -CONFIG_HAVE_CMPXCHG_DOUBLE=y -CONFIG_HAVE_CMPXCHG_LOCAL=y -CONFIG_HAVE_DEBUG_BUGVERBOSE=y -CONFIG_HAVE_EBPF_JIT=y -CONFIG_HAVE_GENERIC_RCU_GUP=y -CONFIG_HAVE_MEMORY_PRESENT=y -CONFIG_HAVE_PATA_PLATFORM=y -CONFIG_HAVE_RCU_TABLE_FREE=y -# CONFIG_HUGETLBFS is not set -CONFIG_HW_RANDOM=y -# CONFIG_HW_RANDOM_CAVIUM is not set -CONFIG_HW_RANDOM_VIRTIO=y -CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000 -CONFIG_LCD_CLASS_DEVICE=m -# CONFIG_LCD_PLATFORM is not set -# CONFIG_LIQUIDIO is not set -CONFIG_LZO_COMPRESS=y -CONFIG_LZO_DECOMPRESS=y -CONFIG_MFD_CORE=y -CONFIG_MFD_SYSCON=y -CONFIG_MFD_VEXPRESS_SYSREG=y -CONFIG_MMC=y -CONFIG_MMC_ARMMMCI=y -# CONFIG_MMC_CAVIUM_THUNDERX is not set -# CONFIG_MMC_TIFM_SD is not set -CONFIG_MODULES_USE_ELF_RELA=y -# CONFIG_MTD_PHYSMAP_OF is not set -CONFIG_NEED_SG_DMA_LENGTH=y -CONFIG_NO_HZ=y -CONFIG_NO_HZ_COMMON=y -CONFIG_NO_HZ_IDLE=y -CONFIG_NR_CPUS=64 -# CONFIG_NUMA is not set -# CONFIG_PCIE_KIRIN is not set -CONFIG_PCI_BUS_ADDR_T_64BIT=y -# CONFIG_PCI_HISI is not set -# CONFIG_PCI_HOST_THUNDER_ECAM is not set -# CONFIG_PCI_HOST_THUNDER_PEM is not set -# CONFIG_PCI_XGENE is not set -CONFIG_PGTABLE_LEVELS=3 -CONFIG_PHYS_ADDR_T_64BIT=y -# CONFIG_PHY_XGENE is not set -CONFIG_PM=y -CONFIG_PM_CLK=y -# CONFIG_PM_DEBUG is not set -CONFIG_PM_GENERIC_DOMAINS=y -CONFIG_PM_GENERIC_DOMAINS_OF=y -CONFIG_POWER_RESET=y -CONFIG_POWER_RESET_VEXPRESS=y -CONFIG_POWER_SUPPLY=y -# CONFIG_RANDOMIZE_BASE is not set -CONFIG_REGMAP=y -CONFIG_REGMAP_MMIO=y -CONFIG_SMC91X=y -CONFIG_SPARSEMEM=y -CONFIG_SPARSEMEM_EXTREME=y -CONFIG_SPARSEMEM_MANUAL=y -CONFIG_SPARSEMEM_VMEMMAP=y -CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y -CONFIG_SYSCTL_EXCEPTION_TRACE=y -CONFIG_SYS_SUPPORTS_HUGETLBFS=y -# CONFIG_THUNDER_NIC_BGX is not set -# CONFIG_THUNDER_NIC_PF is not set -# CONFIG_THUNDER_NIC_RGX is not set -# CONFIG_THUNDER_NIC_VF is not set -CONFIG_UNMAP_KERNEL_AT_EL0=y -CONFIG_VEXPRESS_CONFIG=y -CONFIG_VEXPRESS_SYSCFG=y -CONFIG_VIDEOMODE_HELPERS=y -CONFIG_VMAP_STACK=y diff --git a/target/linux/armvirt/config-4.14 b/target/linux/armvirt/config-4.14 deleted file mode 100644 index a2d8bb4f20b7..000000000000 --- a/target/linux/armvirt/config-4.14 +++ /dev/null @@ -1,181 +0,0 @@ -CONFIG_9P_FS=y -# CONFIG_9P_FS_POSIX_ACL is not set -# CONFIG_9P_FS_SECURITY is not set -CONFIG_ARCH_CLOCKSOURCE_DATA=y -CONFIG_ARCH_HAS_ELF_RANDOMIZE=y -CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y -CONFIG_ARCH_HAS_SG_CHAIN=y -CONFIG_ARCH_HAS_TICK_BROADCAST=y -CONFIG_ARCH_HIBERNATION_POSSIBLE=y -CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y -CONFIG_ARCH_SUSPEND_POSSIBLE=y -CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y -CONFIG_ARM_AMBA=y -CONFIG_ARM_ARCH_TIMER=y -CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y -CONFIG_ARM_GIC=y -CONFIG_ARM_GIC_V2M=y -CONFIG_ARM_GIC_V3=y -CONFIG_ARM_PSCI_FW=y -# CONFIG_ARM_SP805_WATCHDOG is not set -CONFIG_BALLOON_COMPACTION=y -CONFIG_BLK_MQ_PCI=y -CONFIG_CLKDEV_LOOKUP=y -CONFIG_CLKSRC_OF=y -CONFIG_CLKSRC_PROBE=y -CONFIG_CLONE_BACKWARDS=y -CONFIG_COMMON_CLK=y -# CONFIG_CPU_HOTPLUG_STATE_CONTROL is not set -CONFIG_CPU_RMAP=y -CONFIG_CRC16=y -CONFIG_CRYPTO_AEAD=y -CONFIG_CRYPTO_AEAD2=y -CONFIG_CRYPTO_CRC32C=y -CONFIG_CRYPTO_HASH=y -CONFIG_CRYPTO_HASH2=y -CONFIG_CRYPTO_MANAGER=y -CONFIG_CRYPTO_MANAGER2=y -CONFIG_CRYPTO_NULL2=y -CONFIG_CRYPTO_RNG2=y -CONFIG_CRYPTO_WORKQUEUE=y -CONFIG_DCACHE_WORD_ACCESS=y -CONFIG_DTC=y -CONFIG_EDAC_SUPPORT=y -CONFIG_EXT4_FS=y -CONFIG_FIX_EARLYCON_MEM=y -CONFIG_FRAME_POINTER=y -CONFIG_FS_MBCACHE=y -CONFIG_GENERIC_ALLOCATOR=y -CONFIG_GENERIC_BUG=y -CONFIG_GENERIC_CLOCKEVENTS=y -CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y -CONFIG_GENERIC_EARLY_IOREMAP=y -CONFIG_GENERIC_IDLE_POLL_SETUP=y -CONFIG_GENERIC_IO=y -CONFIG_GENERIC_IRQ_MIGRATION=y -CONFIG_GENERIC_IRQ_SHOW=y -CONFIG_GENERIC_IRQ_SHOW_LEVEL=y -CONFIG_GENERIC_MSI_IRQ=y -CONFIG_GENERIC_MSI_IRQ_DOMAIN=y -CONFIG_GENERIC_PCI_IOMAP=y -CONFIG_GENERIC_SCHED_CLOCK=y -CONFIG_GENERIC_SMP_IDLE_THREAD=y -CONFIG_GENERIC_STRNCPY_FROM_USER=y -CONFIG_GENERIC_STRNLEN_USER=y -CONFIG_GPIOLIB=y -CONFIG_GPIOLIB_IRQCHIP=y -CONFIG_GPIO_PL061=y -CONFIG_HANDLE_DOMAIN_IRQ=y -CONFIG_HARDIRQS_SW_RESEND=y -CONFIG_HAS_DMA=y -CONFIG_HAS_IOMEM=y -CONFIG_HAS_IOPORT_MAP=y -# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set -CONFIG_HAVE_ARCH_AUDITSYSCALL=y -CONFIG_HAVE_ARCH_BITREVERSE=y -CONFIG_HAVE_ARCH_JUMP_LABEL=y -CONFIG_HAVE_ARCH_KGDB=y -CONFIG_HAVE_ARCH_PFN_VALID=y -CONFIG_HAVE_ARCH_SECCOMP_FILTER=y -CONFIG_HAVE_ARCH_TRACEHOOK=y -CONFIG_HAVE_ARM_SMCCC=y -# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set -CONFIG_HAVE_CC_STACKPROTECTOR=y -CONFIG_HAVE_CLK=y -CONFIG_HAVE_CLK_PREPARE=y -CONFIG_HAVE_CONTEXT_TRACKING=y -CONFIG_HAVE_C_RECORDMCOUNT=y -CONFIG_HAVE_DEBUG_KMEMLEAK=y -CONFIG_HAVE_DMA_API_DEBUG=y -CONFIG_HAVE_DMA_CONTIGUOUS=y -CONFIG_HAVE_DYNAMIC_FTRACE=y -CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y -CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y -CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y -CONFIG_HAVE_FUNCTION_TRACER=y -CONFIG_HAVE_GENERIC_DMA_COHERENT=y -CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y -CONFIG_HAVE_MEMBLOCK=y -CONFIG_HAVE_NET_DSA=y -CONFIG_HAVE_PERF_EVENTS=y -CONFIG_HAVE_PERF_REGS=y -CONFIG_HAVE_PERF_USER_STACK_DUMP=y -CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y -CONFIG_HAVE_SYSCALL_TRACEPOINTS=y -CONFIG_HAVE_UID16=y -CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y -CONFIG_HOTPLUG_CPU=y -CONFIG_HVC_DRIVER=y -CONFIG_INITRAMFS_SOURCE="" -CONFIG_IOMMU_HELPER=y -CONFIG_IRQCHIP=y -CONFIG_IRQ_DOMAIN=y -CONFIG_IRQ_DOMAIN_HIERARCHY=y -CONFIG_IRQ_FORCED_THREADING=y -CONFIG_IRQ_WORK=y -CONFIG_JBD2=y -CONFIG_LIBFDT=y -CONFIG_LOCK_SPIN_ON_OWNER=y -CONFIG_MEMORY_BALLOON=y -CONFIG_MUTEX_SPIN_ON_OWNER=y -CONFIG_NEED_DMA_MAP_STATE=y -CONFIG_NET_9P=y -# CONFIG_NET_9P_DEBUG is not set -CONFIG_NET_9P_VIRTIO=y -CONFIG_NET_FLOW_LIMIT=y -CONFIG_NO_BOOTMEM=y -CONFIG_NR_CPUS=4 -CONFIG_OF=y -CONFIG_OF_ADDRESS=y -CONFIG_OF_ADDRESS_PCI=y -CONFIG_OF_EARLY_FLATTREE=y -CONFIG_OF_FLATTREE=y -CONFIG_OF_GPIO=y -CONFIG_OF_IRQ=y -CONFIG_OF_NET=y -CONFIG_OF_PCI=y -CONFIG_OF_PCI_IRQ=y -CONFIG_OF_RESERVED_MEM=y -CONFIG_OLD_SIGSUSPEND3=y -CONFIG_PADATA=y -CONFIG_PARTITION_PERCPU=y -CONFIG_PCI=y -CONFIG_PCI_DOMAINS=y -CONFIG_PCI_DOMAINS_GENERIC=y -CONFIG_PCI_ECAM=y -CONFIG_PCI_HOST_COMMON=y -CONFIG_PCI_HOST_GENERIC=y -CONFIG_PCI_MSI=y -CONFIG_PCI_MSI_IRQ_DOMAIN=y -CONFIG_RATIONAL=y -CONFIG_RCU_STALL_COMMON=y -CONFIG_RFS_ACCEL=y -CONFIG_RPS=y -CONFIG_RTC_CLASS=y -CONFIG_RTC_DRV_PL031=y -CONFIG_RWSEM_SPIN_ON_OWNER=y -CONFIG_RWSEM_XCHGADD_ALGORITHM=y -# CONFIG_SCHED_INFO is not set -CONFIG_SCSI=y -CONFIG_SCSI_VIRTIO=y -CONFIG_SERIAL_8250_FSL=y -# CONFIG_SERIAL_AMBA_PL010 is not set -CONFIG_SERIAL_AMBA_PL011=y -CONFIG_SERIAL_AMBA_PL011_CONSOLE=y -CONFIG_SMP=y -CONFIG_SPARSE_IRQ=y -CONFIG_SRCU=y -CONFIG_SWIOTLB=y -CONFIG_TICK_CPU_ACCOUNTING=y -CONFIG_TREE_RCU=y -CONFIG_USB_SUPPORT=y -CONFIG_VIRTIO=y -CONFIG_VIRTIO_BALLOON=y -CONFIG_VIRTIO_BLK=y -CONFIG_VIRTIO_CONSOLE=y -CONFIG_VIRTIO_MMIO=y -# CONFIG_VIRTIO_MMIO_CMDLINE_DEVICES is not set -CONFIG_VIRTIO_NET=y -CONFIG_VIRTIO_PCI=y -CONFIG_VIRTIO_PCI_LEGACY=y -CONFIG_XPS=y From patchwork Sun Mar 1 12:12:31 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Hauke Mehrtens X-Patchwork-Id: 1247284 X-Patchwork-Delegate: hauke@hauke-m.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.openwrt.org (client-ip=2607:7c80:54:e::133; helo=bombadil.infradead.org; envelope-from=openwrt-devel-bounces+incoming=patchwork.ozlabs.org@lists.openwrt.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=hauke-m.de Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=lists.infradead.org header.i=@lists.infradead.org header.a=rsa-sha256 header.s=bombadil.20170209 header.b=lv2HIOFS; dkim-atps=neutral Received: from bombadil.infradead.org (bombadil.infradead.org [IPv6:2607:7c80:54:e::133]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 48VhzG1xGqz9sSH for ; Sun, 1 Mar 2020 23:14:34 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; 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from mout-p-102.mailbox.org ([2001:67c:2050::465:102]) by bombadil.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1j8NSt-0006jR-82 for openwrt-devel@lists.openwrt.org; Sun, 01 Mar 2020 12:13:12 +0000 Received: from smtp2.mailbox.org (smtp2.mailbox.org [80.241.60.241]) (using TLSv1.2 with cipher ECDHE-RSA-CHACHA20-POLY1305 (256/256 bits)) (No client certificate requested) by mout-p-102.mailbox.org (Postfix) with ESMTPS id 48VhxP3b41zKmbK; Sun, 1 Mar 2020 13:12:57 +0100 (CET) X-Virus-Scanned: amavisd-new at heinlein-support.de Received: from smtp2.mailbox.org ([80.241.60.241]) by spamfilter04.heinlein-hosting.de (spamfilter04.heinlein-hosting.de [80.241.56.122]) (amavisd-new, port 10030) with ESMTP id Wvrsk1CdGE9A; Sun, 1 Mar 2020 13:12:48 +0100 (CET) From: Hauke Mehrtens To: openwrt-devel@lists.openwrt.org Date: Sun, 1 Mar 2020 13:12:31 +0100 Message-Id: <20200301121241.5545-3-hauke@hauke-m.de> In-Reply-To: <20200301121241.5545-1-hauke@hauke-m.de> References: <20200301121241.5545-1-hauke@hauke-m.de> MIME-Version: 1.0 X-Spam-Note: CRM114 run bypassed due to message size (300269 bytes) X-Spam-Score: 0.0 (/) X-Spam-Report: SpamAssassin version 3.4.3 on bombadil.infradead.org summary: Content analysis details: (0.0 points) pts rule name description ---- ---------------------- -------------------------------------------------- 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.0 SPF_PASS SPF: sender matches SPF record Subject: [OpenWrt-Devel] [PATCH 02/12] ath79: Remove kernel 4.14 support X-BeenThere: openwrt-devel@lists.openwrt.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: hauke@hauke-m.de Sender: "openwrt-devel" Errors-To: openwrt-devel-bounces+incoming=patchwork.ozlabs.org@lists.openwrt.org This target was switched to kernel 4.19 more than 6 months ago in commit f342ffd300da ("treewide: kernel: bump some targets to 4.19") and now with kernel 5.4 support being added it gets harder to support kernel 4.14 in addition to kernel 4.19 and 5.4. Signed-off-by: Hauke Mehrtens --- target/linux/ath79/config-4.14 | 242 ---- ...-serial-drop-QCA-pecific-SoC-symbols.patch | 21 - ...2-watchdog-ath79-fix-maximum-timeout.patch | 32 - ...ds-add-reset-controller-based-driver.patch | 186 --- .../0004-phy-add-ath79-usb-phys.patch | 320 ----- ...005-usb-add-more-OF-quirk-properties.patch | 24 - .../0006-usb-drop-deprecated-symbols.patch | 51 - ...9-intc-add-irq-cascade-driver-for-QC.patch | 168 --- ...ip-irq-ath79-cpu-drop-OF-init-helper.patch | 23 - ...-ath79-add-lots-of-missing-registers.patch | 980 ---------------- ...d-support-for-QCA953x-QCA956x-TP9343.patch | 400 ------- ...S-ath79-select-the-PINCTRL-subsystem.patch | 24 - ...14-MIPS-ath79-finetune-cpu-overrides.patch | 42 - ...ath79-enable-uart-during-early_prink.patch | 75 -- ...h79-get-PCIe-controller-out-of-reset.patch | 101 -- ...ngs-PCI-qcom-ar7100-adds-binding-doc.patch | 57 - .../0018-MIPS-pci-ar71xx-convert-to-OF.patch | 202 ---- ...ngs-PCI-qcom-ar7240-adds-binding-doc.patch | 61 - .../0020-MIPS-pci-ar724x-convert-to-OF.patch | 205 ---- ...elpers-for-setting-clocks-and-expose.patch | 243 ---- ...legacy-wdt-and-uart-clock-aliases-ou.patch | 114 -- ...ass-PLL-base-to-clock-init-functions.patch | 242 ---- ...specifying-the-reference-clock-in-DT.patch | 229 ---- ...rt-setting-up-clock-via-DT-on-all-So.patch | 77 -- ...9-export-switch-MDIO-reference-clock.patch | 59 - ...0027-MIPS-ath79-drop-legacy-IRQ-code.patch | 233 ---- .../0028-MIPS-ath79-drop-machfiles.patch | 1042 ----------------- ...0029-MIPS-ath79-drop-legacy-pci-code.patch | 379 ------ ...op-platform-device-registration-code.patch | 933 --------------- .../0031-MIPS-ath79-drop-OF-clock-code.patch | 95 -- .../0032-MIPS-ath79-sanitize-symbols.patch | 93 -- .../0033-spi-ath79-drop-pdata-support.patch | 73 -- .../0034-MIPS-ath79-ath9k-exports.patch | 27 - .../0036-GPIO-add-named-gpio-exports.patch | 165 --- ...-MIPS-ath79-remove-irq-code-from-pci.patch | 139 --- .../patches-4.14/0037-missing-registers.patch | 21 - ...9-add-missing-QCA955x-GMAC-registers.patch | 90 -- .../0038-at803x-disable-delays.patch | 27 - .../004-register_gpio_driver_earlier.patch | 18 - .../404-mtd-cybertan-trx-parser.patch | 19 - .../405-mtd-tp-link-partition-parser.patch | 25 - .../408-mtd-redboot_partition_scan.patch | 44 - .../420-net-ar71xx_mac_driver.patch | 28 - ...425-at803x-allow-sgmii-aneg-override.patch | 16 - .../430-drivers-link-spi-before-mtd.patch | 12 - .../461-spi-ath79-add-fast-flash-read.patch | 60 - ...ath79-swizzle-pci-address-for-ar71xx.patch | 98 -- .../900-mdio_bitbang_ignore_ta_value.patch | 32 - ...-prevent-rescheduling-during-command.patch | 61 - .../910-unaligned_access_hacks.patch | 900 -------------- 50 files changed, 8808 deletions(-) delete mode 100644 target/linux/ath79/config-4.14 delete mode 100644 target/linux/ath79/patches-4.14/0001-tty-serial-drop-QCA-pecific-SoC-symbols.patch delete mode 100644 target/linux/ath79/patches-4.14/0002-watchdog-ath79-fix-maximum-timeout.patch delete mode 100644 target/linux/ath79/patches-4.14/0003-leds-add-reset-controller-based-driver.patch delete mode 100644 target/linux/ath79/patches-4.14/0004-phy-add-ath79-usb-phys.patch delete mode 100644 target/linux/ath79/patches-4.14/0005-usb-add-more-OF-quirk-properties.patch delete mode 100644 target/linux/ath79/patches-4.14/0006-usb-drop-deprecated-symbols.patch delete mode 100644 target/linux/ath79/patches-4.14/0007-irqchip-irq-ath79-intc-add-irq-cascade-driver-for-QC.patch delete mode 100644 target/linux/ath79/patches-4.14/0008-irqchip-irq-ath79-cpu-drop-OF-init-helper.patch delete mode 100644 target/linux/ath79/patches-4.14/0009-MIPS-ath79-add-lots-of-missing-registers.patch delete mode 100644 target/linux/ath79/patches-4.14/0010-MIPS-ath79-add-support-for-QCA953x-QCA956x-TP9343.patch delete mode 100644 target/linux/ath79/patches-4.14/0011-MIPS-ath79-select-the-PINCTRL-subsystem.patch delete mode 100644 target/linux/ath79/patches-4.14/0014-MIPS-ath79-finetune-cpu-overrides.patch delete mode 100644 target/linux/ath79/patches-4.14/0015-MIPS-ath79-enable-uart-during-early_prink.patch delete mode 100644 target/linux/ath79/patches-4.14/0016-MIPS-ath79-get-PCIe-controller-out-of-reset.patch delete mode 100644 target/linux/ath79/patches-4.14/0017-dt-bindings-PCI-qcom-ar7100-adds-binding-doc.patch delete mode 100644 target/linux/ath79/patches-4.14/0018-MIPS-pci-ar71xx-convert-to-OF.patch delete mode 100644 target/linux/ath79/patches-4.14/0019-dt-bindings-PCI-qcom-ar7240-adds-binding-doc.patch delete mode 100644 target/linux/ath79/patches-4.14/0020-MIPS-pci-ar724x-convert-to-OF.patch delete mode 100644 target/linux/ath79/patches-4.14/0021-MIPS-ath79-add-helpers-for-setting-clocks-and-expose.patch delete mode 100644 target/linux/ath79/patches-4.14/0022-MIPS-ath79-move-legacy-wdt-and-uart-clock-aliases-ou.patch delete mode 100644 target/linux/ath79/patches-4.14/0023-MIPS-ath79-pass-PLL-base-to-clock-init-functions.patch delete mode 100644 target/linux/ath79/patches-4.14/0024-MIPS-ath79-make-specifying-the-reference-clock-in-DT.patch delete mode 100644 target/linux/ath79/patches-4.14/0025-MIPS-ath79-support-setting-up-clock-via-DT-on-all-So.patch delete mode 100644 target/linux/ath79/patches-4.14/0026-MIPS-ath79-export-switch-MDIO-reference-clock.patch delete mode 100644 target/linux/ath79/patches-4.14/0027-MIPS-ath79-drop-legacy-IRQ-code.patch delete mode 100644 target/linux/ath79/patches-4.14/0028-MIPS-ath79-drop-machfiles.patch delete mode 100644 target/linux/ath79/patches-4.14/0029-MIPS-ath79-drop-legacy-pci-code.patch delete mode 100644 target/linux/ath79/patches-4.14/0030-MIPS-ath79-drop-platform-device-registration-code.patch delete mode 100644 target/linux/ath79/patches-4.14/0031-MIPS-ath79-drop-OF-clock-code.patch delete mode 100644 target/linux/ath79/patches-4.14/0032-MIPS-ath79-sanitize-symbols.patch delete mode 100644 target/linux/ath79/patches-4.14/0033-spi-ath79-drop-pdata-support.patch delete mode 100644 target/linux/ath79/patches-4.14/0034-MIPS-ath79-ath9k-exports.patch delete mode 100644 target/linux/ath79/patches-4.14/0036-GPIO-add-named-gpio-exports.patch delete mode 100644 target/linux/ath79/patches-4.14/0036-MIPS-ath79-remove-irq-code-from-pci.patch delete mode 100644 target/linux/ath79/patches-4.14/0037-missing-registers.patch delete mode 100644 target/linux/ath79/patches-4.14/0038-MIPS-ath79-add-missing-QCA955x-GMAC-registers.patch delete mode 100644 target/linux/ath79/patches-4.14/0038-at803x-disable-delays.patch delete mode 100644 target/linux/ath79/patches-4.14/004-register_gpio_driver_earlier.patch delete mode 100644 target/linux/ath79/patches-4.14/404-mtd-cybertan-trx-parser.patch delete mode 100644 target/linux/ath79/patches-4.14/405-mtd-tp-link-partition-parser.patch delete mode 100644 target/linux/ath79/patches-4.14/408-mtd-redboot_partition_scan.patch delete mode 100644 target/linux/ath79/patches-4.14/420-net-ar71xx_mac_driver.patch delete mode 100644 target/linux/ath79/patches-4.14/425-at803x-allow-sgmii-aneg-override.patch delete mode 100644 target/linux/ath79/patches-4.14/430-drivers-link-spi-before-mtd.patch delete mode 100644 target/linux/ath79/patches-4.14/461-spi-ath79-add-fast-flash-read.patch delete mode 100644 target/linux/ath79/patches-4.14/470-MIPS-ath79-swizzle-pci-address-for-ar71xx.patch delete mode 100644 target/linux/ath79/patches-4.14/900-mdio_bitbang_ignore_ta_value.patch delete mode 100644 target/linux/ath79/patches-4.14/901-phy-mdio-bitbang-prevent-rescheduling-during-command.patch delete mode 100644 target/linux/ath79/patches-4.14/910-unaligned_access_hacks.patch diff --git a/target/linux/ath79/config-4.14 b/target/linux/ath79/config-4.14 deleted file mode 100644 index 1ff3f1272844..000000000000 --- a/target/linux/ath79/config-4.14 +++ /dev/null @@ -1,242 +0,0 @@ -CONFIG_AG71XX=y -# CONFIG_AG71XX_DEBUG is not set -CONFIG_AG71XX_DEBUG_FS=y -CONFIG_AR8216_PHY=y -CONFIG_AR8216_PHY_LEDS=y -CONFIG_ARCH_BINFMT_ELF_STATE=y -CONFIG_ARCH_CLOCKSOURCE_DATA=y -CONFIG_ARCH_DISCARD_MEMBLOCK=y -CONFIG_ARCH_HAS_ELF_RANDOMIZE=y -# CONFIG_ARCH_HAS_GCOV_PROFILE_ALL is not set -CONFIG_ARCH_HAS_RESET_CONTROLLER=y -# CONFIG_ARCH_HAS_SG_CHAIN is not set -# CONFIG_ARCH_HAS_STRICT_KERNEL_RWX is not set -# CONFIG_ARCH_HAS_STRICT_MODULE_RWX is not set -CONFIG_ARCH_HIBERNATION_POSSIBLE=y -CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y -CONFIG_ARCH_MIGHT_HAVE_PC_SERIO=y -CONFIG_ARCH_MMAP_RND_BITS_MAX=15 -CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=15 -# CONFIG_ARCH_OPTIONAL_KERNEL_RWX is not set -# CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT is not set -CONFIG_ARCH_SUPPORTS_UPROBES=y -CONFIG_ARCH_SUSPEND_POSSIBLE=y -CONFIG_ARCH_USE_BUILTIN_BSWAP=y -CONFIG_ARCH_USE_QUEUED_RWLOCKS=y -CONFIG_ARCH_USE_QUEUED_SPINLOCKS=y -CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y -CONFIG_ATH79=y -CONFIG_ATH79_WDT=y -CONFIG_BLK_MQ_PCI=y -CONFIG_CEVT_R4K=y -CONFIG_CLKDEV_LOOKUP=y -CONFIG_CLONE_BACKWARDS=y -CONFIG_CMDLINE="rootfstype=squashfs,jffs2" -CONFIG_CMDLINE_BOOL=y -# CONFIG_CMDLINE_OVERRIDE is not set -CONFIG_COMMON_CLK=y -# CONFIG_COMMON_CLK_BOSTON is not set -CONFIG_CPU_BIG_ENDIAN=y -CONFIG_CPU_GENERIC_DUMP_TLB=y -CONFIG_CPU_HAS_PREFETCH=y -CONFIG_CPU_HAS_RIXI=y -CONFIG_CPU_HAS_SYNC=y -CONFIG_CPU_MIPS32=y -CONFIG_CPU_MIPS32_R2=y -CONFIG_CPU_MIPSR2=y -CONFIG_CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS=y -CONFIG_CPU_R4K_CACHE_TLB=y -CONFIG_CPU_R4K_FPU=y -CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y -CONFIG_CPU_SUPPORTS_HIGHMEM=y -CONFIG_CPU_SUPPORTS_MSA=y -CONFIG_CRYPTO_RNG2=y -CONFIG_CRYPTO_WORKQUEUE=y -CONFIG_CSRC_R4K=y -CONFIG_DMA_NONCOHERENT=y -CONFIG_DTC=y -CONFIG_EARLY_PRINTK=y -CONFIG_ETHERNET_PACKET_MANGLE=y -CONFIG_FIXED_PHY=y -CONFIG_GENERIC_ATOMIC64=y -CONFIG_GENERIC_CLOCKEVENTS=y -CONFIG_GENERIC_CMOS_UPDATE=y -CONFIG_GENERIC_CPU_AUTOPROBE=y -CONFIG_GENERIC_IO=y -CONFIG_GENERIC_IRQ_CHIP=y -CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y -CONFIG_GENERIC_IRQ_SHOW=y -CONFIG_GENERIC_PCI_IOMAP=y -CONFIG_GENERIC_PHY=y -CONFIG_GENERIC_PINCONF=y -CONFIG_GENERIC_PINCTRL_GROUPS=y -CONFIG_GENERIC_PINMUX_FUNCTIONS=y -CONFIG_GENERIC_SCHED_CLOCK=y -CONFIG_GENERIC_SMP_IDLE_THREAD=y -CONFIG_GENERIC_TIME_VSYSCALL=y -CONFIG_GPIOLIB=y -CONFIG_GPIOLIB_IRQCHIP=y -CONFIG_GPIO_74X164=y -CONFIG_GPIO_ATH79=y -CONFIG_GPIO_GENERIC=y -CONFIG_GPIO_SYSFS=y -# CONFIG_GRO_CELLS is not set -CONFIG_HANDLE_DOMAIN_IRQ=y -CONFIG_HARDWARE_WATCHPOINTS=y -CONFIG_HAS_DMA=y -CONFIG_HAS_IOMEM=y -CONFIG_HAS_IOPORT_MAP=y -# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set -# CONFIG_HAVE_ARCH_BITREVERSE is not set -CONFIG_HAVE_ARCH_JUMP_LABEL=y -CONFIG_HAVE_ARCH_KGDB=y -CONFIG_HAVE_ARCH_SECCOMP_FILTER=y -CONFIG_HAVE_ARCH_TRACEHOOK=y -# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set -CONFIG_HAVE_CBPF_JIT=y -CONFIG_HAVE_CC_STACKPROTECTOR=y -CONFIG_HAVE_CLK=y -CONFIG_HAVE_CLK_PREPARE=y -CONFIG_HAVE_CONTEXT_TRACKING=y -CONFIG_HAVE_COPY_THREAD_TLS=y -CONFIG_HAVE_C_RECORDMCOUNT=y -CONFIG_HAVE_DEBUG_KMEMLEAK=y -CONFIG_HAVE_DEBUG_STACKOVERFLOW=y -CONFIG_HAVE_DMA_API_DEBUG=y -CONFIG_HAVE_DMA_CONTIGUOUS=y -CONFIG_HAVE_DYNAMIC_FTRACE=y -CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y -CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y -CONFIG_HAVE_FUNCTION_TRACER=y -CONFIG_HAVE_GENERIC_DMA_COHERENT=y -CONFIG_HAVE_IDE=y -CONFIG_HAVE_IRQ_EXIT_ON_IRQ_STACK=y -CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y -CONFIG_HAVE_KVM=y -CONFIG_HAVE_LATENCYTOP_SUPPORT=y -CONFIG_HAVE_MEMBLOCK=y -CONFIG_HAVE_MEMBLOCK_NODE_MAP=y -CONFIG_HAVE_MOD_ARCH_SPECIFIC=y -CONFIG_HAVE_NET_DSA=y -CONFIG_HAVE_OPROFILE=y -CONFIG_HAVE_PERF_EVENTS=y -CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y -CONFIG_HAVE_SYSCALL_TRACEPOINTS=y -CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y -CONFIG_HW_HAS_PCI=y -CONFIG_HZ_PERIODIC=y -CONFIG_IMAGE_CMDLINE_HACK=y -CONFIG_INITRAMFS_SOURCE="" -CONFIG_IRQCHIP=y -CONFIG_IRQ_DOMAIN=y -CONFIG_IRQ_FORCED_THREADING=y -CONFIG_IRQ_MIPS_CPU=y -CONFIG_IRQ_WORK=y -CONFIG_LEDS_GPIO=y -# CONFIG_LEDS_RESET is not set -CONFIG_LIBFDT=y -CONFIG_MDIO_BITBANG=y -CONFIG_MDIO_BUS=y -CONFIG_MDIO_DEVICE=y -CONFIG_MDIO_GPIO=y -CONFIG_MFD_SYSCON=y -CONFIG_MIPS=y -CONFIG_MIPS_ASID_BITS=8 -CONFIG_MIPS_ASID_SHIFT=0 -CONFIG_MIPS_CLOCK_VSYSCALL=y -# CONFIG_MIPS_CMDLINE_BUILTIN_EXTEND is not set -# CONFIG_MIPS_CMDLINE_DTB_EXTEND is not set -# CONFIG_MIPS_CMDLINE_FROM_BOOTLOADER is not set -CONFIG_MIPS_CMDLINE_FROM_DTB=y -# CONFIG_MIPS_ELF_APPENDED_DTB is not set -# CONFIG_MIPS_HUGE_TLB_SUPPORT is not set -CONFIG_MIPS_L1_CACHE_SHIFT=5 -# CONFIG_MIPS_MACHINE is not set -# CONFIG_MIPS_NO_APPENDED_DTB is not set -CONFIG_MIPS_RAW_APPENDED_DTB=y -CONFIG_MIPS_SPRAM=y -CONFIG_MODULES_USE_ELF_REL=y -CONFIG_MTD_CFI_ADV_OPTIONS=y -CONFIG_MTD_CFI_GEOMETRY=y -# CONFIG_MTD_CFI_I2 is not set -# CONFIG_MTD_CFI_INTELEXT is not set -CONFIG_MTD_CMDLINE_PARTS=y -CONFIG_MTD_M25P80=y -# CONFIG_MTD_MAP_BANK_WIDTH_1 is not set -# CONFIG_MTD_MAP_BANK_WIDTH_4 is not set -CONFIG_MTD_PARSER_CYBERTAN=y -CONFIG_MTD_PHYSMAP=y -CONFIG_MTD_SPI_NOR=y -CONFIG_MTD_SPLIT_FIRMWARE=y -CONFIG_MTD_SPLIT_LZMA_FW=y -CONFIG_MTD_SPLIT_SEAMA_FW=y -CONFIG_MTD_SPLIT_TPLINK_FW=y -CONFIG_MTD_SPLIT_UIMAGE_FW=y -CONFIG_MTD_TPLINK_PARTS=y -CONFIG_MTD_VIRT_CONCAT=y -CONFIG_NEED_DMA_MAP_STATE=y -CONFIG_NEED_PER_CPU_KM=y -CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y -# CONFIG_NO_IOPORT_MAP is not set -CONFIG_OF=y -CONFIG_OF_ADDRESS=y -CONFIG_OF_ADDRESS_PCI=y -CONFIG_OF_EARLY_FLATTREE=y -CONFIG_OF_FLATTREE=y -CONFIG_OF_GPIO=y -CONFIG_OF_IRQ=y -CONFIG_OF_MDIO=y -CONFIG_OF_NET=y -CONFIG_OF_PCI=y -CONFIG_OF_PCI_IRQ=y -CONFIG_PCI=y -CONFIG_PCI_AR71XX=y -CONFIG_PCI_AR724X=y -CONFIG_PCI_DISABLE_COMMON_QUIRKS=y -CONFIG_PCI_DOMAINS=y -CONFIG_PCI_DRIVERS_LEGACY=y -CONFIG_PERF_USE_VMALLOC=y -CONFIG_PGTABLE_LEVELS=2 -CONFIG_PHYLIB=y -# CONFIG_PHY_AR7100_USB is not set -# CONFIG_PHY_AR7200_USB is not set -CONFIG_PINCTRL=y -CONFIG_RATIONAL=y -# CONFIG_RCU_NEED_SEGCBLIST is not set -# CONFIG_RCU_STALL_COMMON is not set -CONFIG_REGMAP=y -CONFIG_REGMAP_MMIO=y -CONFIG_RESET_ATH79=y -CONFIG_RESET_CONTROLLER=y -# CONFIG_SCHED_INFO is not set -# CONFIG_SCSI_DMA is not set -# CONFIG_SERIAL_8250_FSL is not set -CONFIG_SERIAL_8250_NR_UARTS=1 -CONFIG_SERIAL_8250_RUNTIME_UARTS=1 -CONFIG_SERIAL_AR933X=y -CONFIG_SERIAL_AR933X_CONSOLE=y -CONFIG_SERIAL_AR933X_NR_UARTS=2 -CONFIG_SERIAL_OF_PLATFORM=y -CONFIG_SPI=y -CONFIG_SPI_ATH79=y -CONFIG_SPI_BITBANG=y -CONFIG_SPI_GPIO=y -CONFIG_SPI_MASTER=y -# CONFIG_SPI_RB4XX is not set -CONFIG_SRCU=y -CONFIG_SWCONFIG=y -CONFIG_SWCONFIG_LEDS=y -CONFIG_SWPHY=y -CONFIG_SYSCTL_EXCEPTION_TRACE=y -CONFIG_SYS_HAS_CPU_MIPS32_R2=y -CONFIG_SYS_HAS_EARLY_PRINTK=y -CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y -CONFIG_SYS_SUPPORTS_ARBIT_HZ=y -CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y -CONFIG_SYS_SUPPORTS_MIPS16=y -CONFIG_SYS_SUPPORTS_ZBOOT=y -CONFIG_SYS_SUPPORTS_ZBOOT_UART_PROM=y -CONFIG_TICK_CPU_ACCOUNTING=y -CONFIG_TINY_SRCU=y -CONFIG_USB_SUPPORT=y -CONFIG_USE_OF=y diff --git a/target/linux/ath79/patches-4.14/0001-tty-serial-drop-QCA-pecific-SoC-symbols.patch b/target/linux/ath79/patches-4.14/0001-tty-serial-drop-QCA-pecific-SoC-symbols.patch deleted file mode 100644 index 6c4b907e2201..000000000000 --- a/target/linux/ath79/patches-4.14/0001-tty-serial-drop-QCA-pecific-SoC-symbols.patch +++ /dev/null @@ -1,21 +0,0 @@ -From 58812f6d0f1e11b03ed266038ed3b7274ab6f121 Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Tue, 6 Mar 2018 09:26:32 +0100 -Subject: [PATCH 01/27] tty: serial: drop QCA pecific SoC symbols - -Signed-off-by: John Crispin ---- - drivers/tty/serial/Kconfig | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/drivers/tty/serial/Kconfig -+++ b/drivers/tty/serial/Kconfig -@@ -1463,7 +1463,7 @@ config SERIAL_XILINX_PS_UART_CONSOLE - - config SERIAL_AR933X - tristate "AR933X serial port support" -- depends on HAVE_CLK && SOC_AR933X -+ depends on HAVE_CLK && ATH79 - select SERIAL_CORE - help - If you have an Atheros AR933X SOC based board and want to use the diff --git a/target/linux/ath79/patches-4.14/0002-watchdog-ath79-fix-maximum-timeout.patch b/target/linux/ath79/patches-4.14/0002-watchdog-ath79-fix-maximum-timeout.patch deleted file mode 100644 index 36234d8d83ed..000000000000 --- a/target/linux/ath79/patches-4.14/0002-watchdog-ath79-fix-maximum-timeout.patch +++ /dev/null @@ -1,32 +0,0 @@ -From 5f5c9858af167f842ee8df053920b98387a71af1 Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Mon, 5 Mar 2018 11:41:25 +0100 -Subject: [PATCH 02/27] watchdog: ath79: fix maximum timeout - -If the userland tries to set a timeout higher than the max_timeout, -then we should fallback to max_timeout. - -Signed-off-by: John Crispin ---- - drivers/watchdog/ath79_wdt.c | 8 ++++++-- - 1 file changed, 6 insertions(+), 2 deletions(-) - ---- a/drivers/watchdog/ath79_wdt.c -+++ b/drivers/watchdog/ath79_wdt.c -@@ -115,10 +115,14 @@ static inline void ath79_wdt_disable(voi - - static int ath79_wdt_set_timeout(int val) - { -- if (val < 1 || val > max_timeout) -+ if (val < 1) - return -EINVAL; - -- timeout = val; -+ if (val > max_timeout) -+ timeout = max_timeout; -+ else -+ timeout = val; -+ - ath79_wdt_keepalive(); - - return 0; diff --git a/target/linux/ath79/patches-4.14/0003-leds-add-reset-controller-based-driver.patch b/target/linux/ath79/patches-4.14/0003-leds-add-reset-controller-based-driver.patch deleted file mode 100644 index d15c77a8ddda..000000000000 --- a/target/linux/ath79/patches-4.14/0003-leds-add-reset-controller-based-driver.patch +++ /dev/null @@ -1,186 +0,0 @@ -From ecbd9c87f073f097d9fe56390353e64e963e866a Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Tue, 6 Mar 2018 10:03:03 +0100 -Subject: [PATCH 03/27] leds: add reset-controller based driver - -Signed-off-by: John Crispin ---- - drivers/leds/Kconfig | 11 ++++ - drivers/leds/Makefile | 1 + - drivers/leds/leds-reset.c | 137 ++++++++++++++++++++++++++++++++++++++++++++++ - 3 files changed, 149 insertions(+) - create mode 100644 drivers/leds/leds-reset.c - ---- a/drivers/leds/Kconfig -+++ b/drivers/leds/Kconfig -@@ -696,6 +696,17 @@ config LEDS_NIC78BX - To compile this driver as a module, choose M here: the module - will be called leds-nic78bx. - -+config LEDS_RESET -+ tristate "LED support for reset-controller API" -+ depends on LEDS_CLASS -+ depends on RESET_CONTROLLER -+ help -+ This option enables support for LEDs connected to pins driven by reset -+ controllers. Yes, DNI actual built HW like that. -+ -+ To compile this driver as a module, choose M here: the module -+ will be called leds-reset. -+ - comment "LED Triggers" - source "drivers/leds/trigger/Kconfig" - ---- /dev/null -+++ b/drivers/leds/leds-reset.c -@@ -0,0 +1,140 @@ -+/* -+ * Copyright (C) 2018 John Crispin -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ * -+ */ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+struct reset_led_data { -+ struct led_classdev cdev; -+ struct reset_control *rst; -+}; -+ -+static inline struct reset_led_data * -+ cdev_to_reset_led_data(struct led_classdev *led_cdev) -+{ -+ return container_of(led_cdev, struct reset_led_data, cdev); -+} -+ -+static void reset_led_set(struct led_classdev *led_cdev, -+ enum led_brightness value) -+{ -+ struct reset_led_data *led_dat = cdev_to_reset_led_data(led_cdev); -+ -+ if (value == LED_OFF) -+ reset_control_assert(led_dat->rst); -+ else -+ reset_control_deassert(led_dat->rst); -+} -+ -+struct reset_leds_priv { -+ int num_leds; -+ struct reset_led_data leds[]; -+}; -+ -+static inline int sizeof_reset_leds_priv(int num_leds) -+{ -+ return sizeof(struct reset_leds_priv) + -+ (sizeof(struct reset_led_data) * num_leds); -+} -+ -+static struct reset_leds_priv *reset_leds_create(struct platform_device *pdev) -+{ -+ struct device *dev = &pdev->dev; -+ struct fwnode_handle *child; -+ struct reset_leds_priv *priv; -+ int count, ret; -+ -+ count = device_get_child_node_count(dev); -+ if (!count) -+ return ERR_PTR(-ENODEV); -+ -+ priv = devm_kzalloc(dev, sizeof_reset_leds_priv(count), GFP_KERNEL); -+ if (!priv) -+ return ERR_PTR(-ENOMEM); -+ -+ device_for_each_child_node(dev, child) { -+ struct reset_led_data *led = &priv->leds[priv->num_leds]; -+ struct device_node *np = to_of_node(child); -+ -+ ret = fwnode_property_read_string(child, "label", &led->cdev.name); -+ if (!led->cdev.name) { -+ fwnode_handle_put(child); -+ return ERR_PTR(-EINVAL); -+ } -+ led->rst = __of_reset_control_get(np, NULL, 0, 0, 0); -+ if (IS_ERR(led->rst)) -+ return ERR_PTR(-EINVAL); -+ -+ fwnode_property_read_string(child, "linux,default-trigger", -+ &led->cdev.default_trigger); -+ -+ led->cdev.brightness_set = reset_led_set; -+ ret = devm_of_led_classdev_register(&pdev->dev, np, &led->cdev); -+ if (ret < 0) -+ return ERR_PTR(ret); -+ led->cdev.dev->of_node = np; -+ priv->num_leds++; -+ } -+ -+ return priv; -+} -+ -+static const struct of_device_id of_reset_leds_match[] = { -+ { .compatible = "reset-leds", }, -+ {}, -+}; -+ -+MODULE_DEVICE_TABLE(of, of_reset_leds_match); -+ -+static int reset_led_probe(struct platform_device *pdev) -+{ -+ struct reset_leds_priv *priv; -+ -+ priv = reset_leds_create(pdev); -+ if (IS_ERR(priv)) -+ return PTR_ERR(priv); -+ -+ platform_set_drvdata(pdev, priv); -+ -+ return 0; -+} -+ -+static void reset_led_shutdown(struct platform_device *pdev) -+{ -+ struct reset_leds_priv *priv = platform_get_drvdata(pdev); -+ int i; -+ -+ for (i = 0; i < priv->num_leds; i++) { -+ struct reset_led_data *led = &priv->leds[i]; -+ -+ if (!(led->cdev.flags & LED_RETAIN_AT_SHUTDOWN)) -+ reset_led_set(&led->cdev, LED_OFF); -+ } -+} -+ -+static struct platform_driver reset_led_driver = { -+ .probe = reset_led_probe, -+ .shutdown = reset_led_shutdown, -+ .driver = { -+ .name = "leds-reset", -+ .of_match_table = of_reset_leds_match, -+ }, -+}; -+ -+module_platform_driver(reset_led_driver); -+ -+MODULE_AUTHOR("John Crispin "); -+MODULE_DESCRIPTION("reset controller LED driver"); -+MODULE_LICENSE("GPL"); -+MODULE_ALIAS("platform:leds-reset"); ---- a/drivers/leds/Makefile -+++ b/drivers/leds/Makefile -@@ -73,6 +73,7 @@ obj-$(CONFIG_LEDS_PM8058) += leds-pm805 - obj-$(CONFIG_LEDS_MLXCPLD) += leds-mlxcpld.o - obj-$(CONFIG_LEDS_NIC78BX) += leds-nic78bx.o - obj-$(CONFIG_LEDS_MT6323) += leds-mt6323.o -+obj-$(CONFIG_LEDS_RESET) += leds-reset.o - - # LED SPI Drivers - obj-$(CONFIG_LEDS_DAC124S085) += leds-dac124s085.o diff --git a/target/linux/ath79/patches-4.14/0004-phy-add-ath79-usb-phys.patch b/target/linux/ath79/patches-4.14/0004-phy-add-ath79-usb-phys.patch deleted file mode 100644 index 6280baf913ff..000000000000 --- a/target/linux/ath79/patches-4.14/0004-phy-add-ath79-usb-phys.patch +++ /dev/null @@ -1,320 +0,0 @@ -From 08c9d6ceef01893678a5d2e8a15517c745417f21 Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Tue, 6 Mar 2018 10:04:05 +0100 -Subject: [PATCH 04/27] phy: add ath79 usb phys - -Signed-off-by: John Crispin ---- - drivers/phy/Kconfig | 16 ++++++ - drivers/phy/Makefile | 2 + - drivers/phy/phy-ar7100-usb.c | 124 +++++++++++++++++++++++++++++++++++++++++++ - drivers/phy/phy-ar7200-usb.c | 108 +++++++++++++++++++++++++++++++++++++ - 4 files changed, 250 insertions(+) - create mode 100644 drivers/phy/phy-ar7100-usb.c - create mode 100644 drivers/phy/phy-ar7200-usb.c - ---- a/drivers/phy/Kconfig -+++ b/drivers/phy/Kconfig -@@ -15,6 +15,22 @@ config GENERIC_PHY - phy users can obtain reference to the PHY. All the users of this - framework should select this config. - -+config PHY_AR7100_USB -+ tristate "Atheros AR7100 USB PHY driver" -+ depends on ATH79 || COMPILE_TEST -+ default y if USB_EHCI_HCD_PLATFORM -+ select PHY_SIMPLE -+ help -+ Enable this to support the USB PHY on Atheros AR7100 SoCs. -+ -+config PHY_AR7200_USB -+ tristate "Atheros AR7200 USB PHY driver" -+ depends on ATH79 || COMPILE_TEST -+ default y if USB_EHCI_HCD_PLATFORM -+ select PHY_SIMPLE -+ help -+ Enable this to support the USB PHY on Atheros AR7200 SoCs. -+ - config PHY_LPC18XX_USB_OTG - tristate "NXP LPC18xx/43xx SoC USB OTG PHY driver" - depends on OF && (ARCH_LPC18XX || COMPILE_TEST) ---- a/drivers/phy/Makefile -+++ b/drivers/phy/Makefile -@@ -4,6 +4,8 @@ - # - - obj-$(CONFIG_GENERIC_PHY) += phy-core.o -+obj-$(CONFIG_PHY_AR7100_USB) += phy-ar7100-usb.o -+obj-$(CONFIG_PHY_AR7200_USB) += phy-ar7200-usb.o - obj-$(CONFIG_PHY_LPC18XX_USB_OTG) += phy-lpc18xx-usb-otg.o - obj-$(CONFIG_PHY_XGENE) += phy-xgene.o - obj-$(CONFIG_PHY_PISTACHIO_USB) += phy-pistachio-usb.o ---- /dev/null -+++ b/drivers/phy/phy-ar7100-usb.c -@@ -0,0 +1,140 @@ -+/* -+ * Copyright (C) 2018 John Crispin -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+ -+struct ar7100_usb_phy { -+ struct reset_control *rst_phy; -+ struct reset_control *rst_host; -+ struct reset_control *rst_ohci_dll; -+ void __iomem *io_base; -+ struct phy *phy; -+ int gpio; -+}; -+ -+static int ar7100_usb_phy_power_off(struct phy *phy) -+{ -+ struct ar7100_usb_phy *priv = phy_get_drvdata(phy); -+ int err = 0; -+ -+ err |= reset_control_assert(priv->rst_host); -+ err |= reset_control_assert(priv->rst_phy); -+ err |= reset_control_assert(priv->rst_ohci_dll); -+ -+ return err; -+} -+ -+static int ar7100_usb_phy_power_on(struct phy *phy) -+{ -+ struct ar7100_usb_phy *priv = phy_get_drvdata(phy); -+ int err = 0; -+ -+ err |= ar7100_usb_phy_power_off(phy); -+ mdelay(100); -+ err |= reset_control_deassert(priv->rst_ohci_dll); -+ err |= reset_control_deassert(priv->rst_phy); -+ err |= reset_control_deassert(priv->rst_host); -+ mdelay(500); -+ iowrite32(0xf0000, priv->io_base + AR71XX_USB_CTRL_REG_CONFIG); -+ iowrite32(0x20c00, priv->io_base + AR71XX_USB_CTRL_REG_FLADJ); -+ -+ return err; -+} -+ -+static const struct phy_ops ar7100_usb_phy_ops = { -+ .power_on = ar7100_usb_phy_power_on, -+ .power_off = ar7100_usb_phy_power_off, -+ .owner = THIS_MODULE, -+}; -+ -+static int ar7100_usb_phy_probe(struct platform_device *pdev) -+{ -+ struct phy_provider *phy_provider; -+ struct resource *res; -+ struct ar7100_usb_phy *priv; -+ -+ priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); -+ if (!priv) -+ return -ENOMEM; -+ -+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); -+ priv->io_base = devm_ioremap_resource(&pdev->dev, res); -+ if (IS_ERR(priv->io_base)) -+ return PTR_ERR(priv->io_base); -+ -+ priv->rst_phy = devm_reset_control_get(&pdev->dev, "usb-phy"); -+ if (IS_ERR(priv->rst_phy)) { -+ dev_err(&pdev->dev, "phy reset is missing\n"); -+ return PTR_ERR(priv->rst_phy); -+ } -+ -+ priv->rst_host = devm_reset_control_get(&pdev->dev, "usb-host"); -+ if (IS_ERR(priv->rst_host)) { -+ dev_err(&pdev->dev, "host reset is missing\n"); -+ return PTR_ERR(priv->rst_host); -+ } -+ -+ priv->rst_ohci_dll = devm_reset_control_get(&pdev->dev, "usb-ohci-dll"); -+ if (IS_ERR(priv->rst_ohci_dll)) { -+ dev_err(&pdev->dev, "ohci-dll reset is missing\n"); -+ return PTR_ERR(priv->rst_host); -+ } -+ -+ priv->phy = devm_phy_create(&pdev->dev, NULL, &ar7100_usb_phy_ops); -+ if (IS_ERR(priv->phy)) { -+ dev_err(&pdev->dev, "failed to create PHY\n"); -+ return PTR_ERR(priv->phy); -+ } -+ -+ priv->gpio = of_get_gpio(pdev->dev.of_node, 0); -+ if (priv->gpio >= 0) { -+ int ret = devm_gpio_request(&pdev->dev, priv->gpio, dev_name(&pdev->dev)); -+ -+ if (ret) { -+ dev_err(&pdev->dev, "failed to request gpio\n"); -+ return ret; -+ } -+ gpio_export_with_name(priv->gpio, 0, dev_name(&pdev->dev)); -+ gpio_set_value(priv->gpio, 1); -+ } -+ -+ phy_set_drvdata(priv->phy, priv); -+ -+ phy_provider = devm_of_phy_provider_register(&pdev->dev, of_phy_simple_xlate); -+ -+ -+ return PTR_ERR_OR_ZERO(phy_provider); -+} -+ -+static const struct of_device_id ar7100_usb_phy_of_match[] = { -+ { .compatible = "qca,ar7100-usb-phy" }, -+ {} -+}; -+MODULE_DEVICE_TABLE(of, ar7100_usb_phy_of_match); -+ -+static struct platform_driver ar7100_usb_phy_driver = { -+ .probe = ar7100_usb_phy_probe, -+ .driver = { -+ .of_match_table = ar7100_usb_phy_of_match, -+ .name = "ar7100-usb-phy", -+ } -+}; -+module_platform_driver(ar7100_usb_phy_driver); -+ -+MODULE_DESCRIPTION("ATH79 USB PHY driver"); -+MODULE_AUTHOR("Alban Bedel "); -+MODULE_LICENSE("GPL"); ---- /dev/null -+++ b/drivers/phy/phy-ar7200-usb.c -@@ -0,0 +1,123 @@ -+/* -+ * Copyright (C) 2015 Alban Bedel -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+ -+struct ar7200_usb_phy { -+ struct reset_control *rst_phy; -+ struct reset_control *suspend_override; -+ struct phy *phy; -+ int gpio; -+}; -+ -+static int ar7200_usb_phy_power_on(struct phy *phy) -+{ -+ struct ar7200_usb_phy *priv = phy_get_drvdata(phy); -+ int err = 0; -+ -+ if (priv->rst_phy) -+ err = reset_control_deassert(priv->rst_phy); -+ if (!err && priv->suspend_override) -+ err = reset_control_assert(priv->suspend_override); -+ if (err && priv->rst_phy) -+ err = reset_control_assert(priv->rst_phy); -+ -+ return err; -+} -+ -+static int ar7200_usb_phy_power_off(struct phy *phy) -+{ -+ struct ar7200_usb_phy *priv = phy_get_drvdata(phy); -+ int err = 0; -+ -+ if (priv->suspend_override) -+ err = reset_control_deassert(priv->suspend_override); -+ if (priv->rst_phy) -+ err |= reset_control_assert(priv->rst_phy); -+ -+ return err; -+} -+ -+static const struct phy_ops ar7200_usb_phy_ops = { -+ .power_on = ar7200_usb_phy_power_on, -+ .power_off = ar7200_usb_phy_power_off, -+ .owner = THIS_MODULE, -+}; -+ -+static int ar7200_usb_phy_probe(struct platform_device *pdev) -+{ -+ struct phy_provider *phy_provider; -+ struct ar7200_usb_phy *priv; -+ -+ priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); -+ if (!priv) -+ return -ENOMEM; -+ -+ priv->rst_phy = devm_reset_control_get(&pdev->dev, "usb-phy"); -+ if (IS_ERR(priv->rst_phy)) { -+ dev_err(&pdev->dev, "phy reset is missing\n"); -+ return PTR_ERR(priv->rst_phy); -+ } -+ -+ priv->suspend_override = devm_reset_control_get_optional( -+ &pdev->dev, "usb-suspend-override"); -+ if (IS_ERR(priv->suspend_override)) { -+ if (PTR_ERR(priv->suspend_override) == -ENOENT) -+ priv->suspend_override = NULL; -+ else -+ return PTR_ERR(priv->suspend_override); -+ } -+ -+ priv->phy = devm_phy_create(&pdev->dev, NULL, &ar7200_usb_phy_ops); -+ if (IS_ERR(priv->phy)) { -+ dev_err(&pdev->dev, "failed to create PHY\n"); -+ return PTR_ERR(priv->phy); -+ } -+ -+ priv->gpio = of_get_gpio(pdev->dev.of_node, 0); -+ if (priv->gpio >= 0) { -+ int ret = devm_gpio_request(&pdev->dev, priv->gpio, dev_name(&pdev->dev)); -+ -+ if (ret) { -+ dev_err(&pdev->dev, "failed to request gpio\n"); -+ return ret; -+ } -+ gpio_export_with_name(priv->gpio, 0, dev_name(&pdev->dev)); -+ gpio_set_value(priv->gpio, 1); -+ } -+ -+ phy_set_drvdata(priv->phy, priv); -+ -+ phy_provider = devm_of_phy_provider_register(&pdev->dev, of_phy_simple_xlate); -+ -+ return PTR_ERR_OR_ZERO(phy_provider); -+} -+ -+static const struct of_device_id ar7200_usb_phy_of_match[] = { -+ { .compatible = "qca,ar7200-usb-phy" }, -+ {} -+}; -+MODULE_DEVICE_TABLE(of, ar7200_usb_phy_of_match); -+ -+static struct platform_driver ar7200_usb_phy_driver = { -+ .probe = ar7200_usb_phy_probe, -+ .driver = { -+ .of_match_table = ar7200_usb_phy_of_match, -+ .name = "ar7200-usb-phy", -+ } -+}; -+module_platform_driver(ar7200_usb_phy_driver); -+ -+MODULE_DESCRIPTION("ATH79 USB PHY driver"); -+MODULE_AUTHOR("Alban Bedel "); -+MODULE_LICENSE("GPL"); diff --git a/target/linux/ath79/patches-4.14/0005-usb-add-more-OF-quirk-properties.patch b/target/linux/ath79/patches-4.14/0005-usb-add-more-OF-quirk-properties.patch deleted file mode 100644 index ec1bc3f7f706..000000000000 --- a/target/linux/ath79/patches-4.14/0005-usb-add-more-OF-quirk-properties.patch +++ /dev/null @@ -1,24 +0,0 @@ -From 2201818e5bd33f389beceb3943fdfcf5a698fc5b Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Tue, 6 Mar 2018 10:01:43 +0100 -Subject: [PATCH 05/27] usb: add more OF/quirk properties - -Signed-off-by: John Crispin ---- - drivers/usb/host/ehci-platform.c | 5 +++++ - 1 file changed, 5 insertions(+) - ---- a/drivers/usb/host/ehci-platform.c -+++ b/drivers/usb/host/ehci-platform.c -@@ -187,6 +187,11 @@ static int ehci_platform_probe(struct pl - ehci = hcd_to_ehci(hcd); - - if (pdata == &ehci_platform_defaults && dev->dev.of_node) { -+ of_property_read_u32(dev->dev.of_node, "caps-offset", &pdata->caps_offset); -+ -+ if (of_property_read_bool(dev->dev.of_node, "has-synopsys-hc-bug")) -+ pdata->has_synopsys_hc_bug = 1; -+ - if (of_property_read_bool(dev->dev.of_node, "big-endian-regs")) - ehci->big_endian_mmio = 1; - diff --git a/target/linux/ath79/patches-4.14/0006-usb-drop-deprecated-symbols.patch b/target/linux/ath79/patches-4.14/0006-usb-drop-deprecated-symbols.patch deleted file mode 100644 index a97fab71f49a..000000000000 --- a/target/linux/ath79/patches-4.14/0006-usb-drop-deprecated-symbols.patch +++ /dev/null @@ -1,51 +0,0 @@ -From bd17da5b6297e0e52b787049292d076ad415362a Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Tue, 6 Mar 2018 10:04:54 +0100 -Subject: [PATCH 06/27] usb: drop deprecated symbols - -Signed-off-by: John Crispin ---- - drivers/usb/host/Kconfig | 25 ------------------------- - 1 file changed, 25 deletions(-) - ---- a/drivers/usb/host/Kconfig -+++ b/drivers/usb/host/Kconfig -@@ -297,19 +297,6 @@ config USB_CNS3XXX_EHCI - It is needed for high-speed (480Mbit/sec) USB 2.0 device - support. - --config USB_EHCI_ATH79 -- bool "EHCI support for AR7XXX/AR9XXX SoCs (DEPRECATED)" -- depends on (SOC_AR71XX || SOC_AR724X || SOC_AR913X || SOC_AR933X) -- select USB_EHCI_ROOT_HUB_TT -- select USB_EHCI_HCD_PLATFORM -- default y -- ---help--- -- This option is deprecated now and the driver was removed, use -- USB_EHCI_HCD_PLATFORM instead. -- -- Enables support for the built-in EHCI controller present -- on the Atheros AR7XXX/AR9XXX SoCs. -- - config USB_EHCI_HCD_PLATFORM - tristate "Generic EHCI driver for a platform device" - default n -@@ -493,18 +480,6 @@ config USB_OHCI_HCD_DAVINCI - controller. This driver cannot currently be a loadable - module because it lacks a proper PHY abstraction. - --config USB_OHCI_ATH79 -- bool "USB OHCI support for the Atheros AR71XX/AR7240 SoCs (DEPRECATED)" -- depends on (SOC_AR71XX || SOC_AR724X) -- select USB_OHCI_HCD_PLATFORM -- default y -- help -- This option is deprecated now and the driver was removed, use -- USB_OHCI_HCD_PLATFORM instead. -- -- Enables support for the built-in OHCI controller present on the -- Atheros AR71XX/AR7240 SoCs. -- - config USB_OHCI_HCD_PPC_OF_BE - bool "OHCI support for OF platform bus (big endian)" - depends on PPC diff --git a/target/linux/ath79/patches-4.14/0007-irqchip-irq-ath79-intc-add-irq-cascade-driver-for-QC.patch b/target/linux/ath79/patches-4.14/0007-irqchip-irq-ath79-intc-add-irq-cascade-driver-for-QC.patch deleted file mode 100644 index bd26107af528..000000000000 --- a/target/linux/ath79/patches-4.14/0007-irqchip-irq-ath79-intc-add-irq-cascade-driver-for-QC.patch +++ /dev/null @@ -1,168 +0,0 @@ -From f3eacff2310a60348a755c50a8da6fc251fc8587 Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Tue, 6 Mar 2018 09:55:13 +0100 -Subject: [PATCH 07/33] irqchip/irq-ath79-intc: add irq cascade driver for - QCA9556 SoCs - -Signed-off-by: John Crispin ---- - drivers/irqchip/Makefile | 1 + - drivers/irqchip/irq-ath79-intc.c | 142 +++++++++++++++++++++++++++++++++++++++ - 2 files changed, 143 insertions(+) - create mode 100644 drivers/irqchip/irq-ath79-intc.c - ---- a/drivers/irqchip/Makefile -+++ b/drivers/irqchip/Makefile -@@ -3,6 +3,7 @@ obj-$(CONFIG_IRQCHIP) += irqchip.o - - obj-$(CONFIG_ALPINE_MSI) += irq-alpine-msi.o - obj-$(CONFIG_ATH79) += irq-ath79-cpu.o -+obj-$(CONFIG_ATH79) += irq-ath79-intc.o - obj-$(CONFIG_ATH79) += irq-ath79-misc.o - obj-$(CONFIG_ARCH_BCM2835) += irq-bcm2835.o - obj-$(CONFIG_ARCH_BCM2835) += irq-bcm2836.o ---- /dev/null -+++ b/drivers/irqchip/irq-ath79-intc.c -@@ -0,0 +1,142 @@ -+/* -+ * Atheros AR71xx/AR724x/AR913x specific interrupt handling -+ * -+ * Copyright (C) 2018 John Crispin -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+#include -+ -+#define ATH79_MAX_INTC_CASCADE 3 -+ -+struct ath79_intc { -+ struct irq_chip chip; -+ u32 irq; -+ u32 pending_mask; -+ u32 int_status; -+ u32 irq_mask[ATH79_MAX_INTC_CASCADE]; -+ u32 irq_wb_chan[ATH79_MAX_INTC_CASCADE]; -+}; -+ -+static void ath79_intc_irq_handler(struct irq_desc *desc) -+{ -+ struct irq_domain *domain = irq_desc_get_handler_data(desc); -+ struct ath79_intc *intc = domain->host_data; -+ u32 pending; -+ -+ pending = ath79_reset_rr(intc->int_status); -+ pending &= intc->pending_mask; -+ -+ if (pending) { -+ int i; -+ -+ for (i = 0; i < domain->hwirq_max; i++) -+ if (pending & intc->irq_mask[i]) { -+ if (intc->irq_wb_chan[i] != 0xffffffff) -+ ath79_ddr_wb_flush(intc->irq_wb_chan[i]); -+ generic_handle_irq(irq_find_mapping(domain, i)); -+ } -+ } else { -+ spurious_interrupt(); -+ } -+} -+ -+static void ath79_intc_irq_enable(struct irq_data *d) -+{ -+ struct ath79_intc *intc = d->domain->host_data; -+ enable_irq(intc->irq); -+} -+ -+static void ath79_intc_irq_disable(struct irq_data *d) -+{ -+ struct ath79_intc *intc = d->domain->host_data; -+ disable_irq(intc->irq); -+} -+ -+static int ath79_intc_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw) -+{ -+ struct ath79_intc *intc = d->host_data; -+ -+ irq_set_chip_and_handler(irq, &intc->chip, handle_level_irq); -+ -+ return 0; -+} -+ -+static const struct irq_domain_ops ath79_irq_domain_ops = { -+ .xlate = irq_domain_xlate_onecell, -+ .map = ath79_intc_map, -+}; -+ -+static int __init ath79_intc_of_init( -+ struct device_node *node, struct device_node *parent) -+{ -+ struct irq_domain *domain; -+ struct ath79_intc *intc; -+ int cnt, cntwb, i, err; -+ -+ cnt = of_property_count_u32_elems(node, "qca,pending-bits"); -+ if (cnt > ATH79_MAX_INTC_CASCADE) -+ panic("Too many INTC pending bits\n"); -+ -+ intc = kzalloc(sizeof(*intc), GFP_KERNEL); -+ if (!intc) -+ panic("Failed to allocate INTC memory\n"); -+ intc->chip = dummy_irq_chip; -+ intc->chip.name = "INTC"; -+ intc->chip.irq_disable = ath79_intc_irq_disable; -+ intc->chip.irq_enable = ath79_intc_irq_enable; -+ -+ if (of_property_read_u32(node, "qca,int-status-addr", &intc->int_status) < 0) { -+ panic("Missing address of interrupt status register\n"); -+ } -+ -+ of_property_read_u32_array(node, "qca,pending-bits", intc->irq_mask, cnt); -+ for (i = 0; i < cnt; i++) { -+ intc->pending_mask |= intc->irq_mask[i]; -+ intc->irq_wb_chan[i] = 0xffffffff; -+ } -+ -+ cntwb = of_count_phandle_with_args( -+ node, "qca,ddr-wb-channels", "#qca,ddr-wb-channel-cells"); -+ -+ for (i = 0; i < cntwb; i++) { -+ struct of_phandle_args args; -+ u32 irq = i; -+ -+ of_property_read_u32_index( -+ node, "qca,ddr-wb-channel-interrupts", i, &irq); -+ if (irq >= ATH79_MAX_INTC_CASCADE) -+ continue; -+ -+ err = of_parse_phandle_with_args( -+ node, "qca,ddr-wb-channels", -+ "#qca,ddr-wb-channel-cells", -+ i, &args); -+ if (err) -+ return err; -+ -+ intc->irq_wb_chan[irq] = args.args[0]; -+ } -+ -+ intc->irq = irq_of_parse_and_map(node, 0); -+ if (!intc->irq) -+ panic("Failed to get INTC IRQ"); -+ -+ domain = irq_domain_add_linear(node, cnt, &ath79_irq_domain_ops, intc); -+ irq_set_chained_handler_and_data(intc->irq, ath79_intc_irq_handler, domain); -+ -+ return 0; -+} -+IRQCHIP_DECLARE(ath79_intc, "qca,ar9340-intc", -+ ath79_intc_of_init); diff --git a/target/linux/ath79/patches-4.14/0008-irqchip-irq-ath79-cpu-drop-OF-init-helper.patch b/target/linux/ath79/patches-4.14/0008-irqchip-irq-ath79-cpu-drop-OF-init-helper.patch deleted file mode 100644 index b5ad731d06d6..000000000000 --- a/target/linux/ath79/patches-4.14/0008-irqchip-irq-ath79-cpu-drop-OF-init-helper.patch +++ /dev/null @@ -1,23 +0,0 @@ -From e029f998594f151008ecbfa024e2957edd2a5189 Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Tue, 6 Mar 2018 09:58:19 +0100 -Subject: [PATCH 08/33] irqchip/irq-ath79-cpu: drop !OF init helper - -Signed-off-by: John Crispin ---- - drivers/irqchip/irq-ath79-cpu.c | 7 ------- - 1 file changed, 7 deletions(-) - ---- a/drivers/irqchip/irq-ath79-cpu.c -+++ b/drivers/irqchip/irq-ath79-cpu.c -@@ -88,10 +88,3 @@ static int __init ar79_cpu_intc_of_init( - } - IRQCHIP_DECLARE(ar79_cpu_intc, "qca,ar7100-cpu-intc", - ar79_cpu_intc_of_init); -- --void __init ath79_cpu_irq_init(unsigned irq_wb_chan2, unsigned irq_wb_chan3) --{ -- irq_wb_chan[2] = irq_wb_chan2; -- irq_wb_chan[3] = irq_wb_chan3; -- mips_cpu_irq_init(); --} diff --git a/target/linux/ath79/patches-4.14/0009-MIPS-ath79-add-lots-of-missing-registers.patch b/target/linux/ath79/patches-4.14/0009-MIPS-ath79-add-lots-of-missing-registers.patch deleted file mode 100644 index a8092177b414..000000000000 --- a/target/linux/ath79/patches-4.14/0009-MIPS-ath79-add-lots-of-missing-registers.patch +++ /dev/null @@ -1,980 +0,0 @@ -From e93fe20529aeb8738b87533f66c46e2c21524530 Mon Sep 17 00:00:00 2001 -From: Gabor Juhos -Date: Tue, 6 Mar 2018 10:06:10 +0100 -Subject: [PATCH 09/33] MIPS: ath79: add lots of missing registers - -This patch adds many new registers for various QCA MIPS SoCs. The patch is -an aggragate of many contributions made to OpenWrt. - -Signed-off-by: Gabor Juhos -Signed-off-by: Henryk Heisig -Signed-off-by: Matthias Schiffer -Signed-off-by: Weijie Gao -Signed-off-by: Felix Fietkau -Signed-off-by: Julien Dusser -Signed-off-by: John Crispin ---- - arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 771 ++++++++++++++++++++++++- - 1 file changed, 770 insertions(+), 1 deletion(-) - ---- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h -+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h -@@ -20,6 +20,10 @@ - #include - - #define AR71XX_APB_BASE 0x18000000 -+#define AR71XX_GE0_BASE 0x19000000 -+#define AR71XX_GE0_SIZE 0x10000 -+#define AR71XX_GE1_BASE 0x1a000000 -+#define AR71XX_GE1_SIZE 0x10000 - #define AR71XX_EHCI_BASE 0x1b000000 - #define AR71XX_EHCI_SIZE 0x1000 - #define AR71XX_OHCI_BASE 0x1c000000 -@@ -39,6 +43,8 @@ - #define AR71XX_PLL_SIZE 0x100 - #define AR71XX_RESET_BASE (AR71XX_APB_BASE + 0x00060000) - #define AR71XX_RESET_SIZE 0x100 -+#define AR71XX_MII_BASE (AR71XX_APB_BASE + 0x00070000) -+#define AR71XX_MII_SIZE 0x100 - - #define AR71XX_PCI_MEM_BASE 0x10000000 - #define AR71XX_PCI_MEM_SIZE 0x07000000 -@@ -81,18 +87,39 @@ - - #define AR933X_UART_BASE (AR71XX_APB_BASE + 0x00020000) - #define AR933X_UART_SIZE 0x14 -+#define AR933X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000) -+#define AR933X_GMAC_SIZE 0x04 - #define AR933X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000) - #define AR933X_WMAC_SIZE 0x20000 - #define AR933X_EHCI_BASE 0x1b000000 - #define AR933X_EHCI_SIZE 0x1000 - -+#define AR934X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000) -+#define AR934X_GMAC_SIZE 0x14 - #define AR934X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000) - #define AR934X_WMAC_SIZE 0x20000 - #define AR934X_EHCI_BASE 0x1b000000 - #define AR934X_EHCI_SIZE 0x200 -+#define AR934X_NFC_BASE 0x1b000200 -+#define AR934X_NFC_SIZE 0xb8 - #define AR934X_SRIF_BASE (AR71XX_APB_BASE + 0x00116000) - #define AR934X_SRIF_SIZE 0x1000 - -+#define QCA953X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000) -+#define QCA953X_GMAC_SIZE 0x14 -+#define QCA953X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000) -+#define QCA953X_WMAC_SIZE 0x20000 -+#define QCA953X_EHCI_BASE 0x1b000000 -+#define QCA953X_EHCI_SIZE 0x200 -+#define QCA953X_SRIF_BASE (AR71XX_APB_BASE + 0x00116000) -+#define QCA953X_SRIF_SIZE 0x1000 -+ -+#define QCA953X_PCI_CFG_BASE0 0x14000000 -+#define QCA953X_PCI_CTRL_BASE0 (AR71XX_APB_BASE + 0x000f0000) -+#define QCA953X_PCI_CRP_BASE0 (AR71XX_APB_BASE + 0x000c0000) -+#define QCA953X_PCI_MEM_BASE0 0x10000000 -+#define QCA953X_PCI_MEM_SIZE 0x02000000 -+ - #define QCA955X_PCI_MEM_BASE0 0x10000000 - #define QCA955X_PCI_MEM_BASE1 0x12000000 - #define QCA955X_PCI_MEM_SIZE 0x02000000 -@@ -106,11 +133,72 @@ - #define QCA955X_PCI_CTRL_BASE1 (AR71XX_APB_BASE + 0x00280000) - #define QCA955X_PCI_CTRL_SIZE 0x100 - -+#define QCA955X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000) -+#define QCA955X_GMAC_SIZE 0x40 - #define QCA955X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000) - #define QCA955X_WMAC_SIZE 0x20000 - #define QCA955X_EHCI0_BASE 0x1b000000 - #define QCA955X_EHCI1_BASE 0x1b400000 - #define QCA955X_EHCI_SIZE 0x1000 -+#define QCA955X_NFC_BASE 0x1b800200 -+#define QCA955X_NFC_SIZE 0xb8 -+ -+#define QCA956X_PCI_MEM_BASE1 0x12000000 -+#define QCA956X_PCI_MEM_SIZE 0x02000000 -+#define QCA956X_PCI_CFG_BASE1 0x16000000 -+#define QCA956X_PCI_CFG_SIZE 0x1000 -+#define QCA956X_PCI_CRP_BASE1 (AR71XX_APB_BASE + 0x00250000) -+#define QCA956X_PCI_CRP_SIZE 0x1000 -+#define QCA956X_PCI_CTRL_BASE1 (AR71XX_APB_BASE + 0x00280000) -+#define QCA956X_PCI_CTRL_SIZE 0x100 -+ -+#define QCA956X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000) -+#define QCA956X_WMAC_SIZE 0x20000 -+#define QCA956X_EHCI0_BASE 0x1b000000 -+#define QCA956X_EHCI1_BASE 0x1b400000 -+#define QCA956X_EHCI_SIZE 0x200 -+#define QCA956X_GMAC_SGMII_BASE (AR71XX_APB_BASE + 0x00070000) -+#define QCA956X_GMAC_SGMII_SIZE 0x64 -+#define QCA956X_PLL_BASE (AR71XX_APB_BASE + 0x00050000) -+#define QCA956X_PLL_SIZE 0x50 -+#define QCA956X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000) -+#define QCA956X_GMAC_SIZE 0x64 -+ -+/* -+ * Hidden Registers -+ */ -+#define QCA956X_MAC_CFG_BASE 0xb9000000 -+#define QCA956X_MAC_CFG_SIZE 0x64 -+ -+#define QCA956X_MAC_CFG1_REG 0x00 -+#define QCA956X_MAC_CFG1_SOFT_RST BIT(31) -+#define QCA956X_MAC_CFG1_RX_RST BIT(19) -+#define QCA956X_MAC_CFG1_TX_RST BIT(18) -+#define QCA956X_MAC_CFG1_LOOPBACK BIT(8) -+#define QCA956X_MAC_CFG1_RX_EN BIT(2) -+#define QCA956X_MAC_CFG1_TX_EN BIT(0) -+ -+#define QCA956X_MAC_CFG2_REG 0x04 -+#define QCA956X_MAC_CFG2_IF_1000 BIT(9) -+#define QCA956X_MAC_CFG2_IF_10_100 BIT(8) -+#define QCA956X_MAC_CFG2_HUGE_FRAME_EN BIT(5) -+#define QCA956X_MAC_CFG2_LEN_CHECK BIT(4) -+#define QCA956X_MAC_CFG2_PAD_CRC_EN BIT(2) -+#define QCA956X_MAC_CFG2_FDX BIT(0) -+ -+#define QCA956X_MAC_MII_MGMT_CFG_REG 0x20 -+#define QCA956X_MGMT_CFG_CLK_DIV_20 0x07 -+ -+#define QCA956X_MAC_FIFO_CFG0_REG 0x48 -+#define QCA956X_MAC_FIFO_CFG1_REG 0x4c -+#define QCA956X_MAC_FIFO_CFG2_REG 0x50 -+#define QCA956X_MAC_FIFO_CFG3_REG 0x54 -+#define QCA956X_MAC_FIFO_CFG4_REG 0x58 -+#define QCA956X_MAC_FIFO_CFG5_REG 0x5c -+ -+#define QCA956X_DAM_RESET_OFFSET 0xb90001bc -+#define QCA956X_DAM_RESET_SIZE 0x4 -+#define QCA956X_INLINE_CHKSUM_ENG BIT(27) - - /* - * DDR_CTRL block -@@ -149,6 +237,12 @@ - #define AR934X_DDR_REG_FLUSH_PCIE 0xa8 - #define AR934X_DDR_REG_FLUSH_WMAC 0xac - -+#define QCA953X_DDR_REG_FLUSH_GE0 0x9c -+#define QCA953X_DDR_REG_FLUSH_GE1 0xa0 -+#define QCA953X_DDR_REG_FLUSH_USB 0xa4 -+#define QCA953X_DDR_REG_FLUSH_PCIE 0xa8 -+#define QCA953X_DDR_REG_FLUSH_WMAC 0xac -+ - /* - * PLL block - */ -@@ -166,9 +260,15 @@ - #define AR71XX_AHB_DIV_SHIFT 20 - #define AR71XX_AHB_DIV_MASK 0x7 - -+#define AR71XX_ETH0_PLL_SHIFT 17 -+#define AR71XX_ETH1_PLL_SHIFT 19 -+ - #define AR724X_PLL_REG_CPU_CONFIG 0x00 - #define AR724X_PLL_REG_PCIE_CONFIG 0x10 - -+#define AR724X_PLL_REG_PCIE_CONFIG_PPL_BYPASS BIT(16) -+#define AR724X_PLL_REG_PCIE_CONFIG_PPL_RESET BIT(25) -+ - #define AR724X_PLL_FB_SHIFT 0 - #define AR724X_PLL_FB_MASK 0x3ff - #define AR724X_PLL_REF_DIV_SHIFT 10 -@@ -178,6 +278,8 @@ - #define AR724X_DDR_DIV_SHIFT 22 - #define AR724X_DDR_DIV_MASK 0x3 - -+#define AR7242_PLL_REG_ETH0_INT_CLOCK 0x2c -+ - #define AR913X_PLL_REG_CPU_CONFIG 0x00 - #define AR913X_PLL_REG_ETH_CONFIG 0x04 - #define AR913X_PLL_REG_ETH0_INT_CLOCK 0x14 -@@ -190,6 +292,9 @@ - #define AR913X_AHB_DIV_SHIFT 19 - #define AR913X_AHB_DIV_MASK 0x1 - -+#define AR913X_ETH0_PLL_SHIFT 20 -+#define AR913X_ETH1_PLL_SHIFT 22 -+ - #define AR933X_PLL_CPU_CONFIG_REG 0x00 - #define AR933X_PLL_CLOCK_CTRL_REG 0x08 - -@@ -211,6 +316,8 @@ - #define AR934X_PLL_CPU_CONFIG_REG 0x00 - #define AR934X_PLL_DDR_CONFIG_REG 0x04 - #define AR934X_PLL_CPU_DDR_CLK_CTRL_REG 0x08 -+#define AR934X_PLL_SWITCH_CLOCK_CONTROL_REG 0x24 -+#define AR934X_PLL_ETH_XMII_CONTROL_REG 0x2c - - #define AR934X_PLL_CPU_CONFIG_NFRAC_SHIFT 0 - #define AR934X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f -@@ -243,9 +350,52 @@ - #define AR934X_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21) - #define AR934X_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24) - -+#define AR934X_PLL_SWITCH_CLOCK_CONTROL_MDIO_CLK_SEL BIT(6) -+ -+#define QCA953X_PLL_CPU_CONFIG_REG 0x00 -+#define QCA953X_PLL_DDR_CONFIG_REG 0x04 -+#define QCA953X_PLL_CLK_CTRL_REG 0x08 -+#define QCA953X_PLL_SWITCH_CLOCK_CONTROL_REG 0x24 -+#define QCA953X_PLL_ETH_XMII_CONTROL_REG 0x2c -+#define QCA953X_PLL_ETH_SGMII_CONTROL_REG 0x48 -+ -+#define QCA953X_PLL_CPU_CONFIG_NFRAC_SHIFT 0 -+#define QCA953X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f -+#define QCA953X_PLL_CPU_CONFIG_NINT_SHIFT 6 -+#define QCA953X_PLL_CPU_CONFIG_NINT_MASK 0x3f -+#define QCA953X_PLL_CPU_CONFIG_REFDIV_SHIFT 12 -+#define QCA953X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f -+#define QCA953X_PLL_CPU_CONFIG_OUTDIV_SHIFT 19 -+#define QCA953X_PLL_CPU_CONFIG_OUTDIV_MASK 0x7 -+ -+#define QCA953X_PLL_DDR_CONFIG_NFRAC_SHIFT 0 -+#define QCA953X_PLL_DDR_CONFIG_NFRAC_MASK 0x3ff -+#define QCA953X_PLL_DDR_CONFIG_NINT_SHIFT 10 -+#define QCA953X_PLL_DDR_CONFIG_NINT_MASK 0x3f -+#define QCA953X_PLL_DDR_CONFIG_REFDIV_SHIFT 16 -+#define QCA953X_PLL_DDR_CONFIG_REFDIV_MASK 0x1f -+#define QCA953X_PLL_DDR_CONFIG_OUTDIV_SHIFT 23 -+#define QCA953X_PLL_DDR_CONFIG_OUTDIV_MASK 0x7 -+ -+#define QCA953X_PLL_CLK_CTRL_CPU_PLL_BYPASS BIT(2) -+#define QCA953X_PLL_CLK_CTRL_DDR_PLL_BYPASS BIT(3) -+#define QCA953X_PLL_CLK_CTRL_AHB_PLL_BYPASS BIT(4) -+#define QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT 5 -+#define QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_MASK 0x1f -+#define QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT 10 -+#define QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_MASK 0x1f -+#define QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT 15 -+#define QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_MASK 0x1f -+#define QCA953X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL BIT(20) -+#define QCA953X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21) -+#define QCA953X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24) -+ - #define QCA955X_PLL_CPU_CONFIG_REG 0x00 - #define QCA955X_PLL_DDR_CONFIG_REG 0x04 - #define QCA955X_PLL_CLK_CTRL_REG 0x08 -+#define QCA955X_PLL_ETH_XMII_CONTROL_REG 0x28 -+#define QCA955X_PLL_ETH_SGMII_CONTROL_REG 0x48 -+#define QCA955X_PLL_ETH_SGMII_SERDES_REG 0x4c - - #define QCA955X_PLL_CPU_CONFIG_NFRAC_SHIFT 0 - #define QCA955X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f -@@ -278,6 +428,81 @@ - #define QCA955X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21) - #define QCA955X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24) - -+#define QCA955X_PLL_ETH_SGMII_SERDES_LOCK_DETECT BIT(2) -+#define QCA955X_PLL_ETH_SGMII_SERDES_PLL_REFCLK BIT(1) -+#define QCA955X_PLL_ETH_SGMII_SERDES_EN_PLL BIT(0) -+ -+#define QCA956X_PLL_CPU_CONFIG_REG 0x00 -+#define QCA956X_PLL_CPU_CONFIG1_REG 0x04 -+#define QCA956X_PLL_DDR_CONFIG_REG 0x08 -+#define QCA956X_PLL_DDR_CONFIG1_REG 0x0c -+#define QCA956X_PLL_CLK_CTRL_REG 0x10 -+#define QCA956X_PLL_SWITCH_CLOCK_CONTROL_REG 0x28 -+#define QCA956X_PLL_ETH_XMII_CONTROL_REG 0x30 -+#define QCA956X_PLL_ETH_SGMII_SERDES_REG 0x4c -+ -+#define QCA956X_PLL_CPU_CONFIG_REFDIV_SHIFT 12 -+#define QCA956X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f -+#define QCA956X_PLL_CPU_CONFIG_OUTDIV_SHIFT 19 -+#define QCA956X_PLL_CPU_CONFIG_OUTDIV_MASK 0x7 -+ -+#define QCA956X_PLL_CPU_CONFIG1_NFRAC_L_SHIFT 0 -+#define QCA956X_PLL_CPU_CONFIG1_NFRAC_L_MASK 0x1f -+#define QCA956X_PLL_CPU_CONFIG1_NFRAC_H_SHIFT 5 -+#define QCA956X_PLL_CPU_CONFIG1_NFRAC_H_MASK 0x1fff -+#define QCA956X_PLL_CPU_CONFIG1_NINT_SHIFT 18 -+#define QCA956X_PLL_CPU_CONFIG1_NINT_MASK 0x1ff -+ -+#define QCA956X_PLL_DDR_CONFIG_REFDIV_SHIFT 16 -+#define QCA956X_PLL_DDR_CONFIG_REFDIV_MASK 0x1f -+#define QCA956X_PLL_DDR_CONFIG_OUTDIV_SHIFT 23 -+#define QCA956X_PLL_DDR_CONFIG_OUTDIV_MASK 0x7 -+ -+#define QCA956X_PLL_DDR_CONFIG1_NFRAC_L_SHIFT 0 -+#define QCA956X_PLL_DDR_CONFIG1_NFRAC_L_MASK 0x1f -+#define QCA956X_PLL_DDR_CONFIG1_NFRAC_H_SHIFT 5 -+#define QCA956X_PLL_DDR_CONFIG1_NFRAC_H_MASK 0x1fff -+#define QCA956X_PLL_DDR_CONFIG1_NINT_SHIFT 18 -+#define QCA956X_PLL_DDR_CONFIG1_NINT_MASK 0x1ff -+ -+#define QCA956X_PLL_CLK_CTRL_CPU_PLL_BYPASS BIT(2) -+#define QCA956X_PLL_CLK_CTRL_DDR_PLL_BYPASS BIT(3) -+#define QCA956X_PLL_CLK_CTRL_AHB_PLL_BYPASS BIT(4) -+#define QCA956X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT 5 -+#define QCA956X_PLL_CLK_CTRL_CPU_POST_DIV_MASK 0x1f -+#define QCA956X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT 10 -+#define QCA956X_PLL_CLK_CTRL_DDR_POST_DIV_MASK 0x1f -+#define QCA956X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT 15 -+#define QCA956X_PLL_CLK_CTRL_AHB_POST_DIV_MASK 0x1f -+#define QCA956X_PLL_CLK_CTRL_CPU_DDRCLK_FROM_DDRPLL BIT(20) -+#define QCA956X_PLL_CLK_CTRL_CPU_DDRCLK_FROM_CPUPLL BIT(21) -+#define QCA956X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24) -+ -+#define QCA956X_PLL_SWITCH_CLOCK_SPARE_I2C_CLK_SELB BIT(5) -+#define QCA956X_PLL_SWITCH_CLOCK_SPARE_MDIO_CLK_SEL0_1 BIT(6) -+#define QCA956X_PLL_SWITCH_CLOCK_SPARE_UART1_CLK_SEL BIT(7) -+#define QCA956X_PLL_SWITCH_CLOCK_SPARE_USB_REFCLK_FREQ_SEL_SHIFT 8 -+#define QCA956X_PLL_SWITCH_CLOCK_SPARE_USB_REFCLK_FREQ_SEL_MASK 0xf -+#define QCA956X_PLL_SWITCH_CLOCK_SPARE_EN_PLL_TOP BIT(12) -+#define QCA956X_PLL_SWITCH_CLOCK_SPARE_MDIO_CLK_SEL0_2 BIT(13) -+#define QCA956X_PLL_SWITCH_CLOCK_SPARE_MDIO_CLK_SEL1_1 BIT(14) -+#define QCA956X_PLL_SWITCH_CLOCK_SPARE_MDIO_CLK_SEL1_2 BIT(15) -+#define QCA956X_PLL_SWITCH_CLOCK_SPARE_SWITCH_FUNC_TST_MODE BIT(16) -+#define QCA956X_PLL_SWITCH_CLOCK_SPARE_EEE_ENABLE BIT(17) -+#define QCA956X_PLL_SWITCH_CLOCK_SPARE_OEN_CLK125M_PLL BIT(18) -+#define QCA956X_PLL_SWITCH_CLOCK_SPARE_SWITCHCLK_SEL BIT(19) -+ -+#define QCA956X_PLL_ETH_XMII_TX_INVERT BIT(1) -+#define QCA956X_PLL_ETH_XMII_GIGE BIT(25) -+#define QCA956X_PLL_ETH_XMII_RX_DELAY_SHIFT 28 -+#define QCA956X_PLL_ETH_XMII_RX_DELAY_MASK 0x3 -+#define QCA956X_PLL_ETH_XMII_TX_DELAY_SHIFT 26 -+#define QCA956X_PLL_ETH_XMII_TX_DELAY_MASK 3 -+ -+#define QCA956X_PLL_ETH_SGMII_SERDES_LOCK_DETECT BIT(2) -+#define QCA956X_PLL_ETH_SGMII_SERDES_PLL_REFCLK BIT(1) -+#define QCA956X_PLL_ETH_SGMII_SERDES_EN_PLL BIT(0) -+ - /* - * USB_CONFIG block - */ -@@ -317,10 +542,19 @@ - #define AR934X_RESET_REG_BOOTSTRAP 0xb0 - #define AR934X_RESET_REG_PCIE_WMAC_INT_STATUS 0xac - -+#define QCA953X_RESET_REG_RESET_MODULE 0x1c -+#define QCA953X_RESET_REG_BOOTSTRAP 0xb0 -+#define QCA953X_RESET_REG_PCIE_WMAC_INT_STATUS 0xac -+ - #define QCA955X_RESET_REG_RESET_MODULE 0x1c - #define QCA955X_RESET_REG_BOOTSTRAP 0xb0 - #define QCA955X_RESET_REG_EXT_INT_STATUS 0xac - -+#define QCA956X_RESET_REG_RESET_MODULE 0x1c -+#define QCA956X_RESET_REG_BOOTSTRAP 0xb0 -+#define QCA956X_RESET_REG_EXT_INT_STATUS 0xac -+ -+#define MISC_INT_MIPS_SI_TIMERINT_MASK BIT(28) - #define MISC_INT_ETHSW BIT(12) - #define MISC_INT_TIMER4 BIT(10) - #define MISC_INT_TIMER3 BIT(9) -@@ -370,16 +604,123 @@ - #define AR913X_RESET_USB_HOST BIT(5) - #define AR913X_RESET_USB_PHY BIT(4) - -+#define AR933X_RESET_GE1_MDIO BIT(23) -+#define AR933X_RESET_GE0_MDIO BIT(22) -+#define AR933X_RESET_GE1_MAC BIT(13) - #define AR933X_RESET_WMAC BIT(11) -+#define AR933X_RESET_GE0_MAC BIT(9) - #define AR933X_RESET_USB_HOST BIT(5) - #define AR933X_RESET_USB_PHY BIT(4) - #define AR933X_RESET_USBSUS_OVERRIDE BIT(3) - -+#define AR934X_RESET_HOST BIT(31) -+#define AR934X_RESET_SLIC BIT(30) -+#define AR934X_RESET_HDMA BIT(29) -+#define AR934X_RESET_EXTERNAL BIT(28) -+#define AR934X_RESET_RTC BIT(27) -+#define AR934X_RESET_PCIE_EP_INT BIT(26) -+#define AR934X_RESET_CHKSUM_ACC BIT(25) -+#define AR934X_RESET_FULL_CHIP BIT(24) -+#define AR934X_RESET_GE1_MDIO BIT(23) -+#define AR934X_RESET_GE0_MDIO BIT(22) -+#define AR934X_RESET_CPU_NMI BIT(21) -+#define AR934X_RESET_CPU_COLD BIT(20) -+#define AR934X_RESET_HOST_RESET_INT BIT(19) -+#define AR934X_RESET_PCIE_EP BIT(18) -+#define AR934X_RESET_UART1 BIT(17) -+#define AR934X_RESET_DDR BIT(16) -+#define AR934X_RESET_USB_PHY_PLL_PWD_EXT BIT(15) -+#define AR934X_RESET_NANDF BIT(14) -+#define AR934X_RESET_GE1_MAC BIT(13) -+#define AR934X_RESET_ETH_SWITCH_ANALOG BIT(12) - #define AR934X_RESET_USB_PHY_ANALOG BIT(11) -+#define AR934X_RESET_HOST_DMA_INT BIT(10) -+#define AR934X_RESET_GE0_MAC BIT(9) -+#define AR934X_RESET_ETH_SWITCH BIT(8) -+#define AR934X_RESET_PCIE_PHY BIT(7) -+#define AR934X_RESET_PCIE BIT(6) - #define AR934X_RESET_USB_HOST BIT(5) - #define AR934X_RESET_USB_PHY BIT(4) - #define AR934X_RESET_USBSUS_OVERRIDE BIT(3) -+#define AR934X_RESET_LUT BIT(2) -+#define AR934X_RESET_MBOX BIT(1) -+#define AR934X_RESET_I2S BIT(0) -+ -+#define QCA953X_RESET_USB_EXT_PWR BIT(29) -+#define QCA953X_RESET_EXTERNAL BIT(28) -+#define QCA953X_RESET_RTC BIT(27) -+#define QCA953X_RESET_FULL_CHIP BIT(24) -+#define QCA953X_RESET_GE1_MDIO BIT(23) -+#define QCA953X_RESET_GE0_MDIO BIT(22) -+#define QCA953X_RESET_CPU_NMI BIT(21) -+#define QCA953X_RESET_CPU_COLD BIT(20) -+#define QCA953X_RESET_DDR BIT(16) -+#define QCA953X_RESET_USB_PHY_PLL_PWD_EXT BIT(15) -+#define QCA953X_RESET_GE1_MAC BIT(13) -+#define QCA953X_RESET_ETH_SWITCH_ANALOG BIT(12) -+#define QCA953X_RESET_USB_PHY_ANALOG BIT(11) -+#define QCA953X_RESET_GE0_MAC BIT(9) -+#define QCA953X_RESET_ETH_SWITCH BIT(8) -+#define QCA953X_RESET_PCIE_PHY BIT(7) -+#define QCA953X_RESET_PCIE BIT(6) -+#define QCA953X_RESET_USB_HOST BIT(5) -+#define QCA953X_RESET_USB_PHY BIT(4) -+#define QCA953X_RESET_USBSUS_OVERRIDE BIT(3) -+ -+#define QCA955X_RESET_HOST BIT(31) -+#define QCA955X_RESET_SLIC BIT(30) -+#define QCA955X_RESET_HDMA BIT(29) -+#define QCA955X_RESET_EXTERNAL BIT(28) -+#define QCA955X_RESET_RTC BIT(27) -+#define QCA955X_RESET_PCIE_EP_INT BIT(26) -+#define QCA955X_RESET_CHKSUM_ACC BIT(25) -+#define QCA955X_RESET_FULL_CHIP BIT(24) -+#define QCA955X_RESET_GE1_MDIO BIT(23) -+#define QCA955X_RESET_GE0_MDIO BIT(22) -+#define QCA955X_RESET_CPU_NMI BIT(21) -+#define QCA955X_RESET_CPU_COLD BIT(20) -+#define QCA955X_RESET_HOST_RESET_INT BIT(19) -+#define QCA955X_RESET_PCIE_EP BIT(18) -+#define QCA955X_RESET_UART1 BIT(17) -+#define QCA955X_RESET_DDR BIT(16) -+#define QCA955X_RESET_USB_PHY_PLL_PWD_EXT BIT(15) -+#define QCA955X_RESET_NANDF BIT(14) -+#define QCA955X_RESET_GE1_MAC BIT(13) -+#define QCA955X_RESET_SGMII_ANALOG BIT(12) -+#define QCA955X_RESET_USB_PHY_ANALOG BIT(11) -+#define QCA955X_RESET_HOST_DMA_INT BIT(10) -+#define QCA955X_RESET_GE0_MAC BIT(9) -+#define QCA955X_RESET_SGMII BIT(8) -+#define QCA955X_RESET_PCIE_PHY BIT(7) -+#define QCA955X_RESET_PCIE BIT(6) -+#define QCA955X_RESET_USB_HOST BIT(5) -+#define QCA955X_RESET_USB_PHY BIT(4) -+#define QCA955X_RESET_USBSUS_OVERRIDE BIT(3) -+#define QCA955X_RESET_LUT BIT(2) -+#define QCA955X_RESET_MBOX BIT(1) -+#define QCA955X_RESET_I2S BIT(0) -+ -+#define QCA956X_RESET_EXTERNAL BIT(28) -+#define QCA956X_RESET_FULL_CHIP BIT(24) -+#define QCA956X_RESET_GE1_MDIO BIT(23) -+#define QCA956X_RESET_GE0_MDIO BIT(22) -+#define QCA956X_RESET_CPU_NMI BIT(21) -+#define QCA956X_RESET_CPU_COLD BIT(20) -+#define QCA956X_RESET_DMA BIT(19) -+#define QCA956X_RESET_DDR BIT(16) -+#define QCA956X_RESET_GE1_MAC BIT(13) -+#define QCA956X_RESET_SGMII_ANALOG BIT(12) -+#define QCA956X_RESET_USB_PHY_ANALOG BIT(11) -+#define QCA956X_RESET_GE0_MAC BIT(9) -+#define QCA956X_RESET_SGMII BIT(8) -+#define QCA956X_RESET_USB_HOST BIT(5) -+#define QCA956X_RESET_USB_PHY BIT(4) -+#define QCA956X_RESET_USBSUS_OVERRIDE BIT(3) -+#define QCA956X_RESET_SWITCH_ANALOG BIT(2) -+#define QCA956X_RESET_SWITCH BIT(0) - -+#define AR933X_BOOTSTRAP_MDIO_GPIO_EN BIT(18) -+#define AR933X_BOOTSTRAP_EEPBUSY BIT(4) - #define AR933X_BOOTSTRAP_REF_CLK_40 BIT(0) - - #define AR934X_BOOTSTRAP_SW_OPTION8 BIT(23) -@@ -398,8 +739,17 @@ - #define AR934X_BOOTSTRAP_SDRAM_DISABLED BIT(1) - #define AR934X_BOOTSTRAP_DDR1 BIT(0) - -+#define QCA953X_BOOTSTRAP_SW_OPTION2 BIT(12) -+#define QCA953X_BOOTSTRAP_SW_OPTION1 BIT(11) -+#define QCA953X_BOOTSTRAP_EJTAG_MODE BIT(5) -+#define QCA953X_BOOTSTRAP_REF_CLK_40 BIT(4) -+#define QCA953X_BOOTSTRAP_SDRAM_DISABLED BIT(1) -+#define QCA953X_BOOTSTRAP_DDR1 BIT(0) -+ - #define QCA955X_BOOTSTRAP_REF_CLK_40 BIT(4) - -+#define QCA956X_BOOTSTRAP_REF_CLK_40 BIT(2) -+ - #define AR934X_PCIE_WMAC_INT_WMAC_MISC BIT(0) - #define AR934X_PCIE_WMAC_INT_WMAC_TX BIT(1) - #define AR934X_PCIE_WMAC_INT_WMAC_RXLP BIT(2) -@@ -418,6 +768,24 @@ - AR934X_PCIE_WMAC_INT_PCIE_RC1 | AR934X_PCIE_WMAC_INT_PCIE_RC2 | \ - AR934X_PCIE_WMAC_INT_PCIE_RC3) - -+#define QCA953X_PCIE_WMAC_INT_WMAC_MISC BIT(0) -+#define QCA953X_PCIE_WMAC_INT_WMAC_TX BIT(1) -+#define QCA953X_PCIE_WMAC_INT_WMAC_RXLP BIT(2) -+#define QCA953X_PCIE_WMAC_INT_WMAC_RXHP BIT(3) -+#define QCA953X_PCIE_WMAC_INT_PCIE_RC BIT(4) -+#define QCA953X_PCIE_WMAC_INT_PCIE_RC0 BIT(5) -+#define QCA953X_PCIE_WMAC_INT_PCIE_RC1 BIT(6) -+#define QCA953X_PCIE_WMAC_INT_PCIE_RC2 BIT(7) -+#define QCA953X_PCIE_WMAC_INT_PCIE_RC3 BIT(8) -+#define QCA953X_PCIE_WMAC_INT_WMAC_ALL \ -+ (QCA953X_PCIE_WMAC_INT_WMAC_MISC | QCA953X_PCIE_WMAC_INT_WMAC_TX | \ -+ QCA953X_PCIE_WMAC_INT_WMAC_RXLP | QCA953X_PCIE_WMAC_INT_WMAC_RXHP) -+ -+#define QCA953X_PCIE_WMAC_INT_PCIE_ALL \ -+ (QCA953X_PCIE_WMAC_INT_PCIE_RC | QCA953X_PCIE_WMAC_INT_PCIE_RC0 | \ -+ QCA953X_PCIE_WMAC_INT_PCIE_RC1 | QCA953X_PCIE_WMAC_INT_PCIE_RC2 | \ -+ QCA953X_PCIE_WMAC_INT_PCIE_RC3) -+ - #define QCA955X_EXT_INT_WMAC_MISC BIT(0) - #define QCA955X_EXT_INT_WMAC_TX BIT(1) - #define QCA955X_EXT_INT_WMAC_RXLP BIT(2) -@@ -449,6 +817,37 @@ - QCA955X_EXT_INT_PCIE_RC2_INT1 | QCA955X_EXT_INT_PCIE_RC2_INT2 | \ - QCA955X_EXT_INT_PCIE_RC2_INT3) - -+#define QCA956X_EXT_INT_WMAC_MISC BIT(0) -+#define QCA956X_EXT_INT_WMAC_TX BIT(1) -+#define QCA956X_EXT_INT_WMAC_RXLP BIT(2) -+#define QCA956X_EXT_INT_WMAC_RXHP BIT(3) -+#define QCA956X_EXT_INT_PCIE_RC1 BIT(4) -+#define QCA956X_EXT_INT_PCIE_RC1_INT0 BIT(5) -+#define QCA956X_EXT_INT_PCIE_RC1_INT1 BIT(6) -+#define QCA956X_EXT_INT_PCIE_RC1_INT2 BIT(7) -+#define QCA956X_EXT_INT_PCIE_RC1_INT3 BIT(8) -+#define QCA956X_EXT_INT_PCIE_RC2 BIT(12) -+#define QCA956X_EXT_INT_PCIE_RC2_INT0 BIT(13) -+#define QCA956X_EXT_INT_PCIE_RC2_INT1 BIT(14) -+#define QCA956X_EXT_INT_PCIE_RC2_INT2 BIT(15) -+#define QCA956X_EXT_INT_PCIE_RC2_INT3 BIT(16) -+#define QCA956X_EXT_INT_USB1 BIT(24) -+#define QCA956X_EXT_INT_USB2 BIT(28) -+ -+#define QCA956X_EXT_INT_WMAC_ALL \ -+ (QCA956X_EXT_INT_WMAC_MISC | QCA956X_EXT_INT_WMAC_TX | \ -+ QCA956X_EXT_INT_WMAC_RXLP | QCA956X_EXT_INT_WMAC_RXHP) -+ -+#define QCA956X_EXT_INT_PCIE_RC1_ALL \ -+ (QCA956X_EXT_INT_PCIE_RC1 | QCA956X_EXT_INT_PCIE_RC1_INT0 | \ -+ QCA956X_EXT_INT_PCIE_RC1_INT1 | QCA956X_EXT_INT_PCIE_RC1_INT2 | \ -+ QCA956X_EXT_INT_PCIE_RC1_INT3) -+ -+#define QCA956X_EXT_INT_PCIE_RC2_ALL \ -+ (QCA956X_EXT_INT_PCIE_RC2 | QCA956X_EXT_INT_PCIE_RC2_INT0 | \ -+ QCA956X_EXT_INT_PCIE_RC2_INT1 | QCA956X_EXT_INT_PCIE_RC2_INT2 | \ -+ QCA956X_EXT_INT_PCIE_RC2_INT3) -+ - #define REV_ID_MAJOR_MASK 0xfff0 - #define REV_ID_MAJOR_AR71XX 0x00a0 - #define REV_ID_MAJOR_AR913X 0x00b0 -@@ -460,8 +859,12 @@ - #define REV_ID_MAJOR_AR9341 0x0120 - #define REV_ID_MAJOR_AR9342 0x1120 - #define REV_ID_MAJOR_AR9344 0x2120 -+#define REV_ID_MAJOR_QCA9533 0x0140 -+#define REV_ID_MAJOR_QCA9533_V2 0x0160 - #define REV_ID_MAJOR_QCA9556 0x0130 - #define REV_ID_MAJOR_QCA9558 0x1130 -+#define REV_ID_MAJOR_TP9343 0x0150 -+#define REV_ID_MAJOR_QCA956X 0x1150 - - #define AR71XX_REV_ID_MINOR_MASK 0x3 - #define AR71XX_REV_ID_MINOR_AR7130 0x0 -@@ -482,8 +885,12 @@ - - #define AR934X_REV_ID_REVISION_MASK 0xf - -+#define QCA953X_REV_ID_REVISION_MASK 0xf -+ - #define QCA955X_REV_ID_REVISION_MASK 0xf - -+#define QCA956X_REV_ID_REVISION_MASK 0xf -+ - /* - * SPI block - */ -@@ -521,15 +928,63 @@ - #define AR71XX_GPIO_REG_INT_ENABLE 0x24 - #define AR71XX_GPIO_REG_FUNC 0x28 - -+#define AR934X_GPIO_REG_OUT_FUNC0 0x2c -+#define AR934X_GPIO_REG_OUT_FUNC1 0x30 -+#define AR934X_GPIO_REG_OUT_FUNC2 0x34 -+#define AR934X_GPIO_REG_OUT_FUNC3 0x38 -+#define AR934X_GPIO_REG_OUT_FUNC4 0x3c -+#define AR934X_GPIO_REG_OUT_FUNC5 0x40 - #define AR934X_GPIO_REG_FUNC 0x6c - -+#define QCA953X_GPIO_REG_OUT_FUNC0 0x2c -+#define QCA953X_GPIO_REG_OUT_FUNC1 0x30 -+#define QCA953X_GPIO_REG_OUT_FUNC2 0x34 -+#define QCA953X_GPIO_REG_OUT_FUNC3 0x38 -+#define QCA953X_GPIO_REG_OUT_FUNC4 0x3c -+#define QCA953X_GPIO_REG_IN_ENABLE0 0x44 -+#define QCA953X_GPIO_REG_FUNC 0x6c -+ -+#define QCA953X_GPIO_OUT_MUX_SPI_CS1 10 -+#define QCA953X_GPIO_OUT_MUX_SPI_CS2 11 -+#define QCA953X_GPIO_OUT_MUX_SPI_CS0 9 -+#define QCA953X_GPIO_OUT_MUX_SPI_CLK 8 -+#define QCA953X_GPIO_OUT_MUX_SPI_MOSI 12 -+#define QCA953X_GPIO_OUT_MUX_LED_LINK1 41 -+#define QCA953X_GPIO_OUT_MUX_LED_LINK2 42 -+#define QCA953X_GPIO_OUT_MUX_LED_LINK3 43 -+#define QCA953X_GPIO_OUT_MUX_LED_LINK4 44 -+#define QCA953X_GPIO_OUT_MUX_LED_LINK5 45 -+ -+#define QCA955X_GPIO_REG_OUT_FUNC0 0x2c -+#define QCA955X_GPIO_REG_OUT_FUNC1 0x30 -+#define QCA955X_GPIO_REG_OUT_FUNC2 0x34 -+#define QCA955X_GPIO_REG_OUT_FUNC3 0x38 -+#define QCA955X_GPIO_REG_OUT_FUNC4 0x3c -+#define QCA955X_GPIO_REG_OUT_FUNC5 0x40 -+#define QCA955X_GPIO_REG_FUNC 0x6c -+ -+#define QCA956X_GPIO_REG_OUT_FUNC0 0x2c -+#define QCA956X_GPIO_REG_OUT_FUNC1 0x30 -+#define QCA956X_GPIO_REG_OUT_FUNC2 0x34 -+#define QCA956X_GPIO_REG_OUT_FUNC3 0x38 -+#define QCA956X_GPIO_REG_OUT_FUNC4 0x3c -+#define QCA956X_GPIO_REG_OUT_FUNC5 0x40 -+#define QCA956X_GPIO_REG_IN_ENABLE0 0x44 -+#define QCA956X_GPIO_REG_IN_ENABLE3 0x50 -+#define QCA956X_GPIO_REG_FUNC 0x6c -+ -+#define QCA956X_GPIO_OUT_MUX_GE0_MDO 32 -+#define QCA956X_GPIO_OUT_MUX_GE0_MDC 33 -+ - #define AR71XX_GPIO_COUNT 16 - #define AR7240_GPIO_COUNT 18 - #define AR7241_GPIO_COUNT 20 - #define AR913X_GPIO_COUNT 22 - #define AR933X_GPIO_COUNT 30 - #define AR934X_GPIO_COUNT 23 -+#define QCA953X_GPIO_COUNT 18 - #define QCA955X_GPIO_COUNT 24 -+#define QCA956X_GPIO_COUNT 23 - - /* - * SRIF block -@@ -552,4 +1007,318 @@ - #define AR934X_SRIF_DPLL2_OUTDIV_SHIFT 13 - #define AR934X_SRIF_DPLL2_OUTDIV_MASK 0x7 - -+#define QCA953X_SRIF_CPU_DPLL1_REG 0x1c0 -+#define QCA953X_SRIF_CPU_DPLL2_REG 0x1c4 -+#define QCA953X_SRIF_CPU_DPLL3_REG 0x1c8 -+ -+#define QCA953X_SRIF_DDR_DPLL1_REG 0x240 -+#define QCA953X_SRIF_DDR_DPLL2_REG 0x244 -+#define QCA953X_SRIF_DDR_DPLL3_REG 0x248 -+ -+#define QCA953X_SRIF_DPLL1_REFDIV_SHIFT 27 -+#define QCA953X_SRIF_DPLL1_REFDIV_MASK 0x1f -+#define QCA953X_SRIF_DPLL1_NINT_SHIFT 18 -+#define QCA953X_SRIF_DPLL1_NINT_MASK 0x1ff -+#define QCA953X_SRIF_DPLL1_NFRAC_MASK 0x0003ffff -+ -+#define QCA953X_SRIF_DPLL2_LOCAL_PLL BIT(30) -+#define QCA953X_SRIF_DPLL2_OUTDIV_SHIFT 13 -+#define QCA953X_SRIF_DPLL2_OUTDIV_MASK 0x7 -+ -+#define AR71XX_GPIO_FUNC_STEREO_EN BIT(17) -+#define AR71XX_GPIO_FUNC_SLIC_EN BIT(16) -+#define AR71XX_GPIO_FUNC_SPI_CS2_EN BIT(13) -+#define AR71XX_GPIO_FUNC_SPI_CS1_EN BIT(12) -+#define AR71XX_GPIO_FUNC_UART_EN BIT(8) -+#define AR71XX_GPIO_FUNC_USB_OC_EN BIT(4) -+#define AR71XX_GPIO_FUNC_USB_CLK_EN BIT(0) -+ -+#define AR724X_GPIO_FUNC_GE0_MII_CLK_EN BIT(19) -+#define AR724X_GPIO_FUNC_SPI_EN BIT(18) -+#define AR724X_GPIO_FUNC_SPI_CS_EN2 BIT(14) -+#define AR724X_GPIO_FUNC_SPI_CS_EN1 BIT(13) -+#define AR724X_GPIO_FUNC_CLK_OBS5_EN BIT(12) -+#define AR724X_GPIO_FUNC_CLK_OBS4_EN BIT(11) -+#define AR724X_GPIO_FUNC_CLK_OBS3_EN BIT(10) -+#define AR724X_GPIO_FUNC_CLK_OBS2_EN BIT(9) -+#define AR724X_GPIO_FUNC_CLK_OBS1_EN BIT(8) -+#define AR724X_GPIO_FUNC_ETH_SWITCH_LED4_EN BIT(7) -+#define AR724X_GPIO_FUNC_ETH_SWITCH_LED3_EN BIT(6) -+#define AR724X_GPIO_FUNC_ETH_SWITCH_LED2_EN BIT(5) -+#define AR724X_GPIO_FUNC_ETH_SWITCH_LED1_EN BIT(4) -+#define AR724X_GPIO_FUNC_ETH_SWITCH_LED0_EN BIT(3) -+#define AR724X_GPIO_FUNC_UART_RTS_CTS_EN BIT(2) -+#define AR724X_GPIO_FUNC_UART_EN BIT(1) -+#define AR724X_GPIO_FUNC_JTAG_DISABLE BIT(0) -+ -+#define AR913X_GPIO_FUNC_WMAC_LED_EN BIT(22) -+#define AR913X_GPIO_FUNC_EXP_PORT_CS_EN BIT(21) -+#define AR913X_GPIO_FUNC_I2S_REFCLKEN BIT(20) -+#define AR913X_GPIO_FUNC_I2S_MCKEN BIT(19) -+#define AR913X_GPIO_FUNC_I2S1_EN BIT(18) -+#define AR913X_GPIO_FUNC_I2S0_EN BIT(17) -+#define AR913X_GPIO_FUNC_SLIC_EN BIT(16) -+#define AR913X_GPIO_FUNC_UART_RTSCTS_EN BIT(9) -+#define AR913X_GPIO_FUNC_UART_EN BIT(8) -+#define AR913X_GPIO_FUNC_USB_CLK_EN BIT(4) -+ -+#define AR933X_GPIO_FUNC_SPDIF2TCK BIT(31) -+#define AR933X_GPIO_FUNC_SPDIF_EN BIT(30) -+#define AR933X_GPIO_FUNC_I2SO_22_18_EN BIT(29) -+#define AR933X_GPIO_FUNC_I2S_MCK_EN BIT(27) -+#define AR933X_GPIO_FUNC_I2SO_EN BIT(26) -+#define AR933X_GPIO_FUNC_ETH_SWITCH_LED_DUPL BIT(25) -+#define AR933X_GPIO_FUNC_ETH_SWITCH_LED_COLL BIT(24) -+#define AR933X_GPIO_FUNC_ETH_SWITCH_LED_ACT BIT(23) -+#define AR933X_GPIO_FUNC_SPI_EN BIT(18) -+#define AR933X_GPIO_FUNC_SPI_CS_EN2 BIT(14) -+#define AR933X_GPIO_FUNC_SPI_CS_EN1 BIT(13) -+#define AR933X_GPIO_FUNC_ETH_SWITCH_LED4_EN BIT(7) -+#define AR933X_GPIO_FUNC_ETH_SWITCH_LED3_EN BIT(6) -+#define AR933X_GPIO_FUNC_ETH_SWITCH_LED2_EN BIT(5) -+#define AR933X_GPIO_FUNC_ETH_SWITCH_LED1_EN BIT(4) -+#define AR933X_GPIO_FUNC_ETH_SWITCH_LED0_EN BIT(3) -+#define AR933X_GPIO_FUNC_UART_RTS_CTS_EN BIT(2) -+#define AR933X_GPIO_FUNC_UART_EN BIT(1) -+#define AR933X_GPIO_FUNC_JTAG_DISABLE BIT(0) -+ -+#define AR934X_GPIO_FUNC_CLK_OBS7_EN BIT(9) -+#define AR934X_GPIO_FUNC_CLK_OBS6_EN BIT(8) -+#define AR934X_GPIO_FUNC_CLK_OBS5_EN BIT(7) -+#define AR934X_GPIO_FUNC_CLK_OBS4_EN BIT(6) -+#define AR934X_GPIO_FUNC_CLK_OBS3_EN BIT(5) -+#define AR934X_GPIO_FUNC_CLK_OBS2_EN BIT(4) -+#define AR934X_GPIO_FUNC_CLK_OBS1_EN BIT(3) -+#define AR934X_GPIO_FUNC_CLK_OBS0_EN BIT(2) -+#define AR934X_GPIO_FUNC_JTAG_DISABLE BIT(1) -+ -+#define AR934X_GPIO_OUT_GPIO 0 -+#define AR934X_GPIO_OUT_SPI_CS1 7 -+#define AR934X_GPIO_OUT_LED_LINK0 41 -+#define AR934X_GPIO_OUT_LED_LINK1 42 -+#define AR934X_GPIO_OUT_LED_LINK2 43 -+#define AR934X_GPIO_OUT_LED_LINK3 44 -+#define AR934X_GPIO_OUT_LED_LINK4 45 -+#define AR934X_GPIO_OUT_EXT_LNA0 46 -+#define AR934X_GPIO_OUT_EXT_LNA1 47 -+ -+#define QCA955X_GPIO_FUNC_CLK_OBS7_EN BIT(9) -+#define QCA955X_GPIO_FUNC_CLK_OBS6_EN BIT(8) -+#define QCA955X_GPIO_FUNC_CLK_OBS5_EN BIT(7) -+#define QCA955X_GPIO_FUNC_CLK_OBS4_EN BIT(6) -+#define QCA955X_GPIO_FUNC_CLK_OBS3_EN BIT(5) -+#define QCA955X_GPIO_FUNC_CLK_OBS2_EN BIT(4) -+#define QCA955X_GPIO_FUNC_CLK_OBS1_EN BIT(3) -+#define QCA955X_GPIO_FUNC_JTAG_DISABLE BIT(1) -+ -+#define QCA955X_GPIO_OUT_GPIO 0 -+#define QCA955X_MII_EXT_MDI 1 -+#define QCA955X_SLIC_DATA_OUT 3 -+#define QCA955X_SLIC_PCM_FS 4 -+#define QCA955X_SLIC_PCM_CLK 5 -+#define QCA955X_SPI_CLK 8 -+#define QCA955X_SPI_CS_0 9 -+#define QCA955X_SPI_CS_1 10 -+#define QCA955X_SPI_CS_2 11 -+#define QCA955X_SPI_MISO 12 -+#define QCA955X_I2S_CLK 13 -+#define QCA955X_I2S_WS 14 -+#define QCA955X_I2S_SD 15 -+#define QCA955X_I2S_MCK 16 -+#define QCA955X_SPDIF_OUT 17 -+#define QCA955X_UART1_TD 18 -+#define QCA955X_UART1_RTS 19 -+#define QCA955X_UART1_RD 20 -+#define QCA955X_UART1_CTS 21 -+#define QCA955X_UART0_SOUT 22 -+#define QCA955X_SPDIF2_OUT 23 -+#define QCA955X_LED_SGMII_SPEED0 24 -+#define QCA955X_LED_SGMII_SPEED1 25 -+#define QCA955X_LED_SGMII_DUPLEX 26 -+#define QCA955X_LED_SGMII_LINK_UP 27 -+#define QCA955X_SGMII_SPEED0_INVERT 28 -+#define QCA955X_SGMII_SPEED1_INVERT 29 -+#define QCA955X_SGMII_DUPLEX_INVERT 30 -+#define QCA955X_SGMII_LINK_UP_INVERT 31 -+#define QCA955X_GE1_MII_MDO 32 -+#define QCA955X_GE1_MII_MDC 33 -+#define QCA955X_SWCOM2 38 -+#define QCA955X_SWCOM3 39 -+#define QCA955X_MAC2_GPIO 40 -+#define QCA955X_MAC3_GPIO 41 -+#define QCA955X_ATT_LED 42 -+#define QCA955X_PWR_LED 43 -+#define QCA955X_TX_FRAME 44 -+#define QCA955X_RX_CLEAR_EXTERNAL 45 -+#define QCA955X_LED_NETWORK_EN 46 -+#define QCA955X_LED_POWER_EN 47 -+#define QCA955X_WMAC_GLUE_WOW 68 -+#define QCA955X_RX_CLEAR_EXTENSION 70 -+#define QCA955X_CP_NAND_CS1 73 -+#define QCA955X_USB_SUSPEND 74 -+#define QCA955X_ETH_TX_ERR 75 -+#define QCA955X_DDR_DQ_OE 76 -+#define QCA955X_CLKREQ_N_EP 77 -+#define QCA955X_CLKREQ_N_RC 78 -+#define QCA955X_CLK_OBS0 79 -+#define QCA955X_CLK_OBS1 80 -+#define QCA955X_CLK_OBS2 81 -+#define QCA955X_CLK_OBS3 82 -+#define QCA955X_CLK_OBS4 83 -+#define QCA955X_CLK_OBS5 84 -+ -+/* -+ * MII_CTRL block -+ */ -+#define AR71XX_MII_REG_MII0_CTRL 0x00 -+#define AR71XX_MII_REG_MII1_CTRL 0x04 -+ -+#define AR71XX_MII_CTRL_IF_MASK 3 -+#define AR71XX_MII_CTRL_SPEED_SHIFT 4 -+#define AR71XX_MII_CTRL_SPEED_MASK 3 -+#define AR71XX_MII_CTRL_SPEED_10 0 -+#define AR71XX_MII_CTRL_SPEED_100 1 -+#define AR71XX_MII_CTRL_SPEED_1000 2 -+ -+#define AR71XX_MII0_CTRL_IF_GMII 0 -+#define AR71XX_MII0_CTRL_IF_MII 1 -+#define AR71XX_MII0_CTRL_IF_RGMII 2 -+#define AR71XX_MII0_CTRL_IF_RMII 3 -+ -+#define AR71XX_MII1_CTRL_IF_RGMII 0 -+#define AR71XX_MII1_CTRL_IF_RMII 1 -+ -+/* -+ * AR933X GMAC interface -+ */ -+#define AR933X_GMAC_REG_ETH_CFG 0x00 -+ -+#define AR933X_ETH_CFG_RGMII_GE0 BIT(0) -+#define AR933X_ETH_CFG_MII_GE0 BIT(1) -+#define AR933X_ETH_CFG_GMII_GE0 BIT(2) -+#define AR933X_ETH_CFG_MII_GE0_MASTER BIT(3) -+#define AR933X_ETH_CFG_MII_GE0_SLAVE BIT(4) -+#define AR933X_ETH_CFG_MII_GE0_ERR_EN BIT(5) -+#define AR933X_ETH_CFG_SW_PHY_SWAP BIT(7) -+#define AR933X_ETH_CFG_SW_PHY_ADDR_SWAP BIT(8) -+#define AR933X_ETH_CFG_RMII_GE0 BIT(9) -+#define AR933X_ETH_CFG_RMII_GE0_SPD_10 0 -+#define AR933X_ETH_CFG_RMII_GE0_SPD_100 BIT(10) -+ -+/* -+ * AR934X GMAC Interface -+ */ -+#define AR934X_GMAC_REG_ETH_CFG 0x00 -+ -+#define AR934X_ETH_CFG_RGMII_GMAC0 BIT(0) -+#define AR934X_ETH_CFG_MII_GMAC0 BIT(1) -+#define AR934X_ETH_CFG_GMII_GMAC0 BIT(2) -+#define AR934X_ETH_CFG_MII_GMAC0_MASTER BIT(3) -+#define AR934X_ETH_CFG_MII_GMAC0_SLAVE BIT(4) -+#define AR934X_ETH_CFG_MII_GMAC0_ERR_EN BIT(5) -+#define AR934X_ETH_CFG_SW_ONLY_MODE BIT(6) -+#define AR934X_ETH_CFG_SW_PHY_SWAP BIT(7) -+#define AR934X_ETH_CFG_SW_APB_ACCESS BIT(9) -+#define AR934X_ETH_CFG_RMII_GMAC0 BIT(10) -+#define AR933X_ETH_CFG_MII_CNTL_SPEED BIT(11) -+#define AR934X_ETH_CFG_RMII_GMAC0_MASTER BIT(12) -+#define AR933X_ETH_CFG_SW_ACC_MSB_FIRST BIT(13) -+#define AR934X_ETH_CFG_RXD_DELAY BIT(14) -+#define AR934X_ETH_CFG_RXD_DELAY_MASK 0x3 -+#define AR934X_ETH_CFG_RXD_DELAY_SHIFT 14 -+#define AR934X_ETH_CFG_RDV_DELAY BIT(16) -+#define AR934X_ETH_CFG_RDV_DELAY_MASK 0x3 -+#define AR934X_ETH_CFG_RDV_DELAY_SHIFT 16 -+ -+/* -+ * QCA953X GMAC Interface -+ */ -+#define QCA953X_GMAC_REG_ETH_CFG 0x00 -+ -+#define QCA953X_ETH_CFG_SW_ONLY_MODE BIT(6) -+#define QCA953X_ETH_CFG_SW_PHY_SWAP BIT(7) -+#define QCA953X_ETH_CFG_SW_APB_ACCESS BIT(9) -+#define QCA953X_ETH_CFG_SW_ACC_MSB_FIRST BIT(13) -+ -+/* -+ * QCA955X GMAC Interface -+ */ -+ -+#define QCA955X_GMAC_REG_ETH_CFG 0x00 -+#define QCA955X_GMAC_REG_SGMII_SERDES 0x18 -+ -+#define QCA955X_ETH_CFG_RGMII_EN BIT(0) -+#define QCA955X_ETH_CFG_MII_GE0 BIT(1) -+#define QCA955X_ETH_CFG_GMII_GE0 BIT(2) -+#define QCA955X_ETH_CFG_MII_GE0_MASTER BIT(3) -+#define QCA955X_ETH_CFG_MII_GE0_SLAVE BIT(4) -+#define QCA955X_ETH_CFG_GE0_ERR_EN BIT(5) -+#define QCA955X_ETH_CFG_GE0_SGMII BIT(6) -+#define QCA955X_ETH_CFG_RMII_GE0 BIT(10) -+#define QCA955X_ETH_CFG_MII_CNTL_SPEED BIT(11) -+#define QCA955X_ETH_CFG_RMII_GE0_MASTER BIT(12) -+#define QCA955X_ETH_CFG_RXD_DELAY_MASK 0x3 -+#define QCA955X_ETH_CFG_RXD_DELAY_SHIFT 14 -+#define QCA955X_ETH_CFG_RDV_DELAY BIT(16) -+#define QCA955X_ETH_CFG_RDV_DELAY_MASK 0x3 -+#define QCA955X_ETH_CFG_RDV_DELAY_SHIFT 16 -+#define QCA955X_ETH_CFG_TXD_DELAY_MASK 0x3 -+#define QCA955X_ETH_CFG_TXD_DELAY_SHIFT 18 -+#define QCA955X_ETH_CFG_TXE_DELAY_MASK 0x3 -+#define QCA955X_ETH_CFG_TXE_DELAY_SHIFT 20 -+ -+#define QCA955X_SGMII_SERDES_LOCK_DETECT_STATUS BIT(15) -+#define QCA955X_SGMII_SERDES_RES_CALIBRATION_SHIFT 23 -+#define QCA955X_SGMII_SERDES_RES_CALIBRATION_MASK 0xf -+/* -+ * QCA956X GMAC Interface -+ */ -+ -+#define QCA956X_GMAC_REG_ETH_CFG 0x00 -+#define QCA956X_GMAC_REG_SGMII_RESET 0x14 -+#define QCA956X_GMAC_REG_SGMII_SERDES 0x18 -+#define QCA956X_GMAC_REG_MR_AN_CONTROL 0x1c -+#define QCA956X_GMAC_REG_SGMII_CONFIG 0x34 -+#define QCA956X_GMAC_REG_SGMII_DEBUG 0x58 -+ -+#define QCA956X_ETH_CFG_RGMII_EN BIT(0) -+#define QCA956X_ETH_CFG_GE0_SGMII BIT(6) -+#define QCA956X_ETH_CFG_SW_ONLY_MODE BIT(7) -+#define QCA956X_ETH_CFG_SW_PHY_SWAP BIT(8) -+#define QCA956X_ETH_CFG_SW_PHY_ADDR_SWAP BIT(9) -+#define QCA956X_ETH_CFG_SW_APB_ACCESS BIT(10) -+#define QCA956X_ETH_CFG_SW_ACC_MSB_FIRST BIT(13) -+#define QCA956X_ETH_CFG_RXD_DELAY_MASK 0x3 -+#define QCA956X_ETH_CFG_RXD_DELAY_SHIFT 14 -+#define QCA956X_ETH_CFG_RDV_DELAY_MASK 0x3 -+#define QCA956X_ETH_CFG_RDV_DELAY_SHIFT 16 -+ -+#define QCA956X_SGMII_RESET_RX_CLK_N_RESET 0x0 -+#define QCA956X_SGMII_RESET_RX_CLK_N BIT(0) -+#define QCA956X_SGMII_RESET_TX_CLK_N BIT(1) -+#define QCA956X_SGMII_RESET_RX_125M_N BIT(2) -+#define QCA956X_SGMII_RESET_TX_125M_N BIT(3) -+#define QCA956X_SGMII_RESET_HW_RX_125M_N BIT(4) -+ -+#define QCA956X_SGMII_SERDES_CDR_BW_MASK 0x3 -+#define QCA956X_SGMII_SERDES_CDR_BW_SHIFT 1 -+#define QCA956X_SGMII_SERDES_TX_DR_CTRL_MASK 0x7 -+#define QCA956X_SGMII_SERDES_TX_DR_CTRL_SHIFT 4 -+#define QCA956X_SGMII_SERDES_PLL_BW BIT(8) -+#define QCA956X_SGMII_SERDES_VCO_FAST BIT(9) -+#define QCA956X_SGMII_SERDES_VCO_SLOW BIT(10) -+#define QCA956X_SGMII_SERDES_LOCK_DETECT_STATUS BIT(15) -+#define QCA956X_SGMII_SERDES_EN_SIGNAL_DETECT BIT(16) -+#define QCA956X_SGMII_SERDES_FIBER_SDO BIT(17) -+#define QCA956X_SGMII_SERDES_RES_CALIBRATION_SHIFT 23 -+#define QCA956X_SGMII_SERDES_RES_CALIBRATION_MASK 0xf -+#define QCA956X_SGMII_SERDES_VCO_REG_SHIFT 27 -+#define QCA956X_SGMII_SERDES_VCO_REG_MASK 0xf -+ -+#define QCA956X_MR_AN_CONTROL_AN_ENABLE BIT(12) -+#define QCA956X_MR_AN_CONTROL_PHY_RESET BIT(15) -+ -+#define QCA956X_SGMII_CONFIG_MODE_CTRL_SHIFT 0 -+#define QCA956X_SGMII_CONFIG_MODE_CTRL_MASK 0x7 -+ - #endif /* __ASM_MACH_AR71XX_REGS_H */ diff --git a/target/linux/ath79/patches-4.14/0010-MIPS-ath79-add-support-for-QCA953x-QCA956x-TP9343.patch b/target/linux/ath79/patches-4.14/0010-MIPS-ath79-add-support-for-QCA953x-QCA956x-TP9343.patch deleted file mode 100644 index 1a87f52d1872..000000000000 --- a/target/linux/ath79/patches-4.14/0010-MIPS-ath79-add-support-for-QCA953x-QCA956x-TP9343.patch +++ /dev/null @@ -1,400 +0,0 @@ -From 2741304648dbdab7697d7758166a582b5291c53d Mon Sep 17 00:00:00 2001 -From: Matthias Schiffer -Date: Sat, 23 Jun 2018 15:08:56 +0200 -Subject: [PATCH 10/33] MIPS: ath79: add support for QCA953x QCA956x TP9343 - -This patch adds support for 2 new types of QCA silicon. TP9343 is -essentially the same as the QCA956X but is licensed by TPLink. - -Signed-off-by: Weijie Gao -Signed-off-by: Matthias Schiffer -Signed-off-by: John Crispin ---- - arch/mips/ath79/clock.c | 193 +++++++++++++++++++++++++++++++ - arch/mips/ath79/common.c | 8 ++ - arch/mips/ath79/early_printk.c | 4 + - arch/mips/ath79/setup.c | 34 +++++- - arch/mips/include/asm/mach-ath79/ath79.h | 33 ++++++ - 5 files changed, 269 insertions(+), 3 deletions(-) - ---- a/arch/mips/ath79/clock.c -+++ b/arch/mips/ath79/clock.c -@@ -355,6 +355,91 @@ static void __init ar934x_clocks_init(vo - iounmap(dpll_base); - } - -+static void __init qca953x_clocks_init(void) -+{ -+ unsigned long ref_rate; -+ unsigned long cpu_rate; -+ unsigned long ddr_rate; -+ unsigned long ahb_rate; -+ u32 pll, out_div, ref_div, nint, frac, clk_ctrl, postdiv; -+ u32 cpu_pll, ddr_pll; -+ u32 bootstrap; -+ -+ bootstrap = ath79_reset_rr(QCA953X_RESET_REG_BOOTSTRAP); -+ if (bootstrap & QCA953X_BOOTSTRAP_REF_CLK_40) -+ ref_rate = 40 * 1000 * 1000; -+ else -+ ref_rate = 25 * 1000 * 1000; -+ -+ pll = ath79_pll_rr(QCA953X_PLL_CPU_CONFIG_REG); -+ out_div = (pll >> QCA953X_PLL_CPU_CONFIG_OUTDIV_SHIFT) & -+ QCA953X_PLL_CPU_CONFIG_OUTDIV_MASK; -+ ref_div = (pll >> QCA953X_PLL_CPU_CONFIG_REFDIV_SHIFT) & -+ QCA953X_PLL_CPU_CONFIG_REFDIV_MASK; -+ nint = (pll >> QCA953X_PLL_CPU_CONFIG_NINT_SHIFT) & -+ QCA953X_PLL_CPU_CONFIG_NINT_MASK; -+ frac = (pll >> QCA953X_PLL_CPU_CONFIG_NFRAC_SHIFT) & -+ QCA953X_PLL_CPU_CONFIG_NFRAC_MASK; -+ -+ cpu_pll = nint * ref_rate / ref_div; -+ cpu_pll += frac * (ref_rate >> 6) / ref_div; -+ cpu_pll /= (1 << out_div); -+ -+ pll = ath79_pll_rr(QCA953X_PLL_DDR_CONFIG_REG); -+ out_div = (pll >> QCA953X_PLL_DDR_CONFIG_OUTDIV_SHIFT) & -+ QCA953X_PLL_DDR_CONFIG_OUTDIV_MASK; -+ ref_div = (pll >> QCA953X_PLL_DDR_CONFIG_REFDIV_SHIFT) & -+ QCA953X_PLL_DDR_CONFIG_REFDIV_MASK; -+ nint = (pll >> QCA953X_PLL_DDR_CONFIG_NINT_SHIFT) & -+ QCA953X_PLL_DDR_CONFIG_NINT_MASK; -+ frac = (pll >> QCA953X_PLL_DDR_CONFIG_NFRAC_SHIFT) & -+ QCA953X_PLL_DDR_CONFIG_NFRAC_MASK; -+ -+ ddr_pll = nint * ref_rate / ref_div; -+ ddr_pll += frac * (ref_rate >> 6) / (ref_div << 4); -+ ddr_pll /= (1 << out_div); -+ -+ clk_ctrl = ath79_pll_rr(QCA953X_PLL_CLK_CTRL_REG); -+ -+ postdiv = (clk_ctrl >> QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT) & -+ QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_MASK; -+ -+ if (clk_ctrl & QCA953X_PLL_CLK_CTRL_CPU_PLL_BYPASS) -+ cpu_rate = ref_rate; -+ else if (clk_ctrl & QCA953X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL) -+ cpu_rate = cpu_pll / (postdiv + 1); -+ else -+ cpu_rate = ddr_pll / (postdiv + 1); -+ -+ postdiv = (clk_ctrl >> QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT) & -+ QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_MASK; -+ -+ if (clk_ctrl & QCA953X_PLL_CLK_CTRL_DDR_PLL_BYPASS) -+ ddr_rate = ref_rate; -+ else if (clk_ctrl & QCA953X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL) -+ ddr_rate = ddr_pll / (postdiv + 1); -+ else -+ ddr_rate = cpu_pll / (postdiv + 1); -+ -+ postdiv = (clk_ctrl >> QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT) & -+ QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_MASK; -+ -+ if (clk_ctrl & QCA953X_PLL_CLK_CTRL_AHB_PLL_BYPASS) -+ ahb_rate = ref_rate; -+ else if (clk_ctrl & QCA953X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL) -+ ahb_rate = ddr_pll / (postdiv + 1); -+ else -+ ahb_rate = cpu_pll / (postdiv + 1); -+ -+ ath79_add_sys_clkdev("ref", ref_rate); -+ ath79_add_sys_clkdev("cpu", cpu_rate); -+ ath79_add_sys_clkdev("ddr", ddr_rate); -+ ath79_add_sys_clkdev("ahb", ahb_rate); -+ -+ clk_add_alias("wdt", NULL, "ref", NULL); -+ clk_add_alias("uart", NULL, "ref", NULL); -+} -+ - static void __init qca955x_clocks_init(void) - { - unsigned long ref_rate; -@@ -440,6 +525,110 @@ static void __init qca955x_clocks_init(v - clk_add_alias("uart", NULL, "ref", NULL); - } - -+static void __init qca956x_clocks_init(void) -+{ -+ unsigned long ref_rate; -+ unsigned long cpu_rate; -+ unsigned long ddr_rate; -+ unsigned long ahb_rate; -+ u32 pll, out_div, ref_div, nint, hfrac, lfrac, clk_ctrl, postdiv; -+ u32 cpu_pll, ddr_pll; -+ u32 bootstrap; -+ -+ /* -+ * QCA956x timer init workaround has to be applied right before setting -+ * up the clock. Else, there will be no jiffies -+ */ -+ u32 misc; -+ -+ misc = ath79_reset_rr(AR71XX_RESET_REG_MISC_INT_ENABLE); -+ misc |= MISC_INT_MIPS_SI_TIMERINT_MASK; -+ ath79_reset_wr(AR71XX_RESET_REG_MISC_INT_ENABLE, misc); -+ -+ bootstrap = ath79_reset_rr(QCA956X_RESET_REG_BOOTSTRAP); -+ if (bootstrap & QCA956X_BOOTSTRAP_REF_CLK_40) -+ ref_rate = 40 * 1000 * 1000; -+ else -+ ref_rate = 25 * 1000 * 1000; -+ -+ pll = ath79_pll_rr(QCA956X_PLL_CPU_CONFIG_REG); -+ out_div = (pll >> QCA956X_PLL_CPU_CONFIG_OUTDIV_SHIFT) & -+ QCA956X_PLL_CPU_CONFIG_OUTDIV_MASK; -+ ref_div = (pll >> QCA956X_PLL_CPU_CONFIG_REFDIV_SHIFT) & -+ QCA956X_PLL_CPU_CONFIG_REFDIV_MASK; -+ -+ pll = ath79_pll_rr(QCA956X_PLL_CPU_CONFIG1_REG); -+ nint = (pll >> QCA956X_PLL_CPU_CONFIG1_NINT_SHIFT) & -+ QCA956X_PLL_CPU_CONFIG1_NINT_MASK; -+ hfrac = (pll >> QCA956X_PLL_CPU_CONFIG1_NFRAC_H_SHIFT) & -+ QCA956X_PLL_CPU_CONFIG1_NFRAC_H_MASK; -+ lfrac = (pll >> QCA956X_PLL_CPU_CONFIG1_NFRAC_L_SHIFT) & -+ QCA956X_PLL_CPU_CONFIG1_NFRAC_L_MASK; -+ -+ cpu_pll = nint * ref_rate / ref_div; -+ cpu_pll += (lfrac * ref_rate) / ((ref_div * 25) << 13); -+ cpu_pll += (hfrac >> 13) * ref_rate / ref_div; -+ cpu_pll /= (1 << out_div); -+ -+ pll = ath79_pll_rr(QCA956X_PLL_DDR_CONFIG_REG); -+ out_div = (pll >> QCA956X_PLL_DDR_CONFIG_OUTDIV_SHIFT) & -+ QCA956X_PLL_DDR_CONFIG_OUTDIV_MASK; -+ ref_div = (pll >> QCA956X_PLL_DDR_CONFIG_REFDIV_SHIFT) & -+ QCA956X_PLL_DDR_CONFIG_REFDIV_MASK; -+ pll = ath79_pll_rr(QCA956X_PLL_DDR_CONFIG1_REG); -+ nint = (pll >> QCA956X_PLL_DDR_CONFIG1_NINT_SHIFT) & -+ QCA956X_PLL_DDR_CONFIG1_NINT_MASK; -+ hfrac = (pll >> QCA956X_PLL_DDR_CONFIG1_NFRAC_H_SHIFT) & -+ QCA956X_PLL_DDR_CONFIG1_NFRAC_H_MASK; -+ lfrac = (pll >> QCA956X_PLL_DDR_CONFIG1_NFRAC_L_SHIFT) & -+ QCA956X_PLL_DDR_CONFIG1_NFRAC_L_MASK; -+ -+ ddr_pll = nint * ref_rate / ref_div; -+ ddr_pll += (lfrac * ref_rate) / ((ref_div * 25) << 13); -+ ddr_pll += (hfrac >> 13) * ref_rate / ref_div; -+ ddr_pll /= (1 << out_div); -+ -+ clk_ctrl = ath79_pll_rr(QCA956X_PLL_CLK_CTRL_REG); -+ -+ postdiv = (clk_ctrl >> QCA956X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT) & -+ QCA956X_PLL_CLK_CTRL_CPU_POST_DIV_MASK; -+ -+ if (clk_ctrl & QCA956X_PLL_CLK_CTRL_CPU_PLL_BYPASS) -+ cpu_rate = ref_rate; -+ else if (clk_ctrl & QCA956X_PLL_CLK_CTRL_CPU_DDRCLK_FROM_CPUPLL) -+ cpu_rate = ddr_pll / (postdiv + 1); -+ else -+ cpu_rate = cpu_pll / (postdiv + 1); -+ -+ postdiv = (clk_ctrl >> QCA956X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT) & -+ QCA956X_PLL_CLK_CTRL_DDR_POST_DIV_MASK; -+ -+ if (clk_ctrl & QCA956X_PLL_CLK_CTRL_DDR_PLL_BYPASS) -+ ddr_rate = ref_rate; -+ else if (clk_ctrl & QCA956X_PLL_CLK_CTRL_CPU_DDRCLK_FROM_DDRPLL) -+ ddr_rate = cpu_pll / (postdiv + 1); -+ else -+ ddr_rate = ddr_pll / (postdiv + 1); -+ -+ postdiv = (clk_ctrl >> QCA956X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT) & -+ QCA956X_PLL_CLK_CTRL_AHB_POST_DIV_MASK; -+ -+ if (clk_ctrl & QCA956X_PLL_CLK_CTRL_AHB_PLL_BYPASS) -+ ahb_rate = ref_rate; -+ else if (clk_ctrl & QCA956X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL) -+ ahb_rate = ddr_pll / (postdiv + 1); -+ else -+ ahb_rate = cpu_pll / (postdiv + 1); -+ -+ ath79_add_sys_clkdev("ref", ref_rate); -+ ath79_add_sys_clkdev("cpu", cpu_rate); -+ ath79_add_sys_clkdev("ddr", ddr_rate); -+ ath79_add_sys_clkdev("ahb", ahb_rate); -+ -+ clk_add_alias("wdt", NULL, "ref", NULL); -+ clk_add_alias("uart", NULL, "ref", NULL); -+} -+ - void __init ath79_clocks_init(void) - { - if (soc_is_ar71xx()) -@@ -450,8 +639,12 @@ void __init ath79_clocks_init(void) - ar933x_clocks_init(); - else if (soc_is_ar934x()) - ar934x_clocks_init(); -+ else if (soc_is_qca953x()) -+ qca953x_clocks_init(); - else if (soc_is_qca955x()) - qca955x_clocks_init(); -+ else if (soc_is_qca956x() || soc_is_tp9343()) -+ qca956x_clocks_init(); - else - BUG(); - } ---- a/arch/mips/ath79/common.c -+++ b/arch/mips/ath79/common.c -@@ -103,8 +103,12 @@ void ath79_device_reset_set(u32 mask) - reg = AR933X_RESET_REG_RESET_MODULE; - else if (soc_is_ar934x()) - reg = AR934X_RESET_REG_RESET_MODULE; -+ else if (soc_is_qca953x()) -+ reg = QCA953X_RESET_REG_RESET_MODULE; - else if (soc_is_qca955x()) - reg = QCA955X_RESET_REG_RESET_MODULE; -+ else if (soc_is_qca956x() || soc_is_tp9343()) -+ reg = QCA956X_RESET_REG_RESET_MODULE; - else - BUG(); - -@@ -131,8 +135,12 @@ void ath79_device_reset_clear(u32 mask) - reg = AR933X_RESET_REG_RESET_MODULE; - else if (soc_is_ar934x()) - reg = AR934X_RESET_REG_RESET_MODULE; -+ else if (soc_is_qca953x()) -+ reg = QCA953X_RESET_REG_RESET_MODULE; - else if (soc_is_qca955x()) - reg = QCA955X_RESET_REG_RESET_MODULE; -+ else if (soc_is_qca956x() || soc_is_tp9343()) -+ reg = QCA956X_RESET_REG_RESET_MODULE; - else - BUG(); - ---- a/arch/mips/ath79/early_printk.c -+++ b/arch/mips/ath79/early_printk.c -@@ -76,8 +76,12 @@ static void prom_putchar_init(void) - case REV_ID_MAJOR_AR9341: - case REV_ID_MAJOR_AR9342: - case REV_ID_MAJOR_AR9344: -+ case REV_ID_MAJOR_QCA9533: -+ case REV_ID_MAJOR_QCA9533_V2: - case REV_ID_MAJOR_QCA9556: - case REV_ID_MAJOR_QCA9558: -+ case REV_ID_MAJOR_TP9343: -+ case REV_ID_MAJOR_QCA956X: - _prom_putchar = prom_putchar_ar71xx; - break; - ---- a/arch/mips/ath79/setup.c -+++ b/arch/mips/ath79/setup.c -@@ -60,6 +60,7 @@ static void __init ath79_detect_sys_type - u32 major; - u32 minor; - u32 rev = 0; -+ u32 ver = 1; - - id = ath79_reset_rr(AR71XX_RESET_REG_REV_ID); - major = id & REV_ID_MAJOR_MASK; -@@ -152,6 +153,17 @@ static void __init ath79_detect_sys_type - rev = id & AR934X_REV_ID_REVISION_MASK; - break; - -+ case REV_ID_MAJOR_QCA9533_V2: -+ ver = 2; -+ ath79_soc_rev = 2; -+ /* drop through */ -+ -+ case REV_ID_MAJOR_QCA9533: -+ ath79_soc = ATH79_SOC_QCA9533; -+ chip = "9533"; -+ rev = id & QCA953X_REV_ID_REVISION_MASK; -+ break; -+ - case REV_ID_MAJOR_QCA9556: - ath79_soc = ATH79_SOC_QCA9556; - chip = "9556"; -@@ -164,14 +176,30 @@ static void __init ath79_detect_sys_type - rev = id & QCA955X_REV_ID_REVISION_MASK; - break; - -+ case REV_ID_MAJOR_QCA956X: -+ ath79_soc = ATH79_SOC_QCA956X; -+ chip = "956X"; -+ rev = id & QCA956X_REV_ID_REVISION_MASK; -+ break; -+ -+ case REV_ID_MAJOR_TP9343: -+ ath79_soc = ATH79_SOC_TP9343; -+ chip = "9343"; -+ rev = id & QCA956X_REV_ID_REVISION_MASK; -+ break; -+ - default: - panic("ath79: unknown SoC, id:0x%08x", id); - } - -- ath79_soc_rev = rev; -+ if (ver == 1) -+ ath79_soc_rev = rev; - -- if (soc_is_qca955x()) -- sprintf(ath79_sys_type, "Qualcomm Atheros QCA%s rev %u", -+ if (soc_is_qca953x() || soc_is_qca955x() || soc_is_qca956x()) -+ sprintf(ath79_sys_type, "Qualcomm Atheros QCA%s ver %u rev %u", -+ chip, ver, rev); -+ else if (soc_is_tp9343()) -+ sprintf(ath79_sys_type, "Qualcomm Atheros TP%s rev %u", - chip, rev); - else - sprintf(ath79_sys_type, "Atheros AR%s rev %u", chip, rev); ---- a/arch/mips/include/asm/mach-ath79/ath79.h -+++ b/arch/mips/include/asm/mach-ath79/ath79.h -@@ -32,8 +32,11 @@ enum ath79_soc_type { - ATH79_SOC_AR9341, - ATH79_SOC_AR9342, - ATH79_SOC_AR9344, -+ ATH79_SOC_QCA9533, - ATH79_SOC_QCA9556, - ATH79_SOC_QCA9558, -+ ATH79_SOC_TP9343, -+ ATH79_SOC_QCA956X, - }; - - extern enum ath79_soc_type ath79_soc; -@@ -100,6 +103,16 @@ static inline int soc_is_ar934x(void) - return soc_is_ar9341() || soc_is_ar9342() || soc_is_ar9344(); - } - -+static inline int soc_is_qca9533(void) -+{ -+ return ath79_soc == ATH79_SOC_QCA9533; -+} -+ -+static inline int soc_is_qca953x(void) -+{ -+ return soc_is_qca9533(); -+} -+ - static inline int soc_is_qca9556(void) - { - return ath79_soc == ATH79_SOC_QCA9556; -@@ -115,6 +128,26 @@ static inline int soc_is_qca955x(void) - return soc_is_qca9556() || soc_is_qca9558(); - } - -+static inline int soc_is_tp9343(void) -+{ -+ return ath79_soc == ATH79_SOC_TP9343; -+} -+ -+static inline int soc_is_qca9561(void) -+{ -+ return ath79_soc == ATH79_SOC_QCA956X; -+} -+ -+static inline int soc_is_qca9563(void) -+{ -+ return ath79_soc == ATH79_SOC_QCA956X; -+} -+ -+static inline int soc_is_qca956x(void) -+{ -+ return soc_is_qca9561() || soc_is_qca9563(); -+} -+ - void ath79_ddr_wb_flush(unsigned int reg); - void ath79_ddr_set_pci_windows(void); - diff --git a/target/linux/ath79/patches-4.14/0011-MIPS-ath79-select-the-PINCTRL-subsystem.patch b/target/linux/ath79/patches-4.14/0011-MIPS-ath79-select-the-PINCTRL-subsystem.patch deleted file mode 100644 index c50a473307c9..000000000000 --- a/target/linux/ath79/patches-4.14/0011-MIPS-ath79-select-the-PINCTRL-subsystem.patch +++ /dev/null @@ -1,24 +0,0 @@ -From 0c8856211d26f84277f7fcb0b9595e5c646bc464 Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Tue, 6 Mar 2018 10:00:55 +0100 -Subject: [PATCH 11/33] MIPS: ath79: select the PINCTRL subsystem - -The pinmux on QCA SoCs is controlled by a single register. The -"pinctrl-single" driver can be used but requires the target -to select PINCTRL. - -Signed-off-by: John Crispin ---- - arch/mips/Kconfig | 1 + - 1 file changed, 1 insertion(+) - ---- a/arch/mips/Kconfig -+++ b/arch/mips/Kconfig -@@ -192,6 +192,7 @@ config ATH79 - select CSRC_R4K - select DMA_NONCOHERENT - select GPIOLIB -+ select PINCTRL - select HAVE_CLK - select COMMON_CLK - select CLKDEV_LOOKUP diff --git a/target/linux/ath79/patches-4.14/0014-MIPS-ath79-finetune-cpu-overrides.patch b/target/linux/ath79/patches-4.14/0014-MIPS-ath79-finetune-cpu-overrides.patch deleted file mode 100644 index 534111c2b0ed..000000000000 --- a/target/linux/ath79/patches-4.14/0014-MIPS-ath79-finetune-cpu-overrides.patch +++ /dev/null @@ -1,42 +0,0 @@ -From 30dc99e95ac4410072850ae466f696cb56097bb4 Mon Sep 17 00:00:00 2001 -From: Felix Fietkau -Date: Mon, 5 Mar 2018 11:35:29 +0100 -Subject: [PATCH 14/33] MIPS: ath79: finetune cpu-overrides - -This patch adds a few additional cpu feature overrides so that they do not -need to be probed at runtime. - -Signed-off-by: Felix Fietkau -Signed-off-by: John Crispin ---- - arch/mips/include/asm/mach-ath79/cpu-feature-overrides.h | 6 ++++++ - 1 file changed, 6 insertions(+) - ---- a/arch/mips/include/asm/mach-ath79/cpu-feature-overrides.h -+++ b/arch/mips/include/asm/mach-ath79/cpu-feature-overrides.h -@@ -36,6 +36,7 @@ - #define cpu_has_mdmx 0 - #define cpu_has_mips3d 0 - #define cpu_has_smartmips 0 -+#define cpu_has_rixi 0 - - #define cpu_has_mips32r1 1 - #define cpu_has_mips32r2 1 -@@ -43,6 +44,7 @@ - #define cpu_has_mips64r2 0 - - #define cpu_has_mipsmt 0 -+#define cpu_has_userlocal 0 - - #define cpu_has_64bits 0 - #define cpu_has_64bit_zero_reg 0 -@@ -51,5 +53,9 @@ - - #define cpu_dcache_line_size() 32 - #define cpu_icache_line_size() 32 -+#define cpu_has_vtag_icache 0 -+#define cpu_has_dc_aliases 1 -+#define cpu_has_ic_fills_f_dc 0 -+#define cpu_has_pindexed_dcache 0 - - #endif /* __ASM_MACH_ATH79_CPU_FEATURE_OVERRIDES_H */ diff --git a/target/linux/ath79/patches-4.14/0015-MIPS-ath79-enable-uart-during-early_prink.patch b/target/linux/ath79/patches-4.14/0015-MIPS-ath79-enable-uart-during-early_prink.patch deleted file mode 100644 index eaa960a6e679..000000000000 --- a/target/linux/ath79/patches-4.14/0015-MIPS-ath79-enable-uart-during-early_prink.patch +++ /dev/null @@ -1,75 +0,0 @@ -From f55a400f4a691f3750eaf7bfcd6ecbf7ed1622f0 Mon Sep 17 00:00:00 2001 -From: Gabor Juhos -Date: Mon, 5 Mar 2018 11:38:21 +0100 -Subject: [PATCH 15/33] MIPS: ath79: enable uart during early_prink - -This patch ensures, that the poinmux register is properly setup for the -boot console uart when early_printk is enabled. - -Signed-off-by: Gabor Juhos -Signed-off-by: John Crispin ---- - arch/mips/ath79/early_printk.c | 44 +++++++++++++++++++++++++++++++++++++++++- - 1 file changed, 43 insertions(+), 1 deletion(-) - ---- a/arch/mips/ath79/early_printk.c -+++ b/arch/mips/ath79/early_printk.c -@@ -58,6 +58,46 @@ static void prom_putchar_dummy(unsigned - /* nothing to do */ - } - -+static void prom_enable_uart(u32 id) -+{ -+ void __iomem *gpio_base; -+ u32 uart_en; -+ u32 t; -+ -+ switch (id) { -+ case REV_ID_MAJOR_AR71XX: -+ uart_en = AR71XX_GPIO_FUNC_UART_EN; -+ break; -+ -+ case REV_ID_MAJOR_AR7240: -+ case REV_ID_MAJOR_AR7241: -+ case REV_ID_MAJOR_AR7242: -+ uart_en = AR724X_GPIO_FUNC_UART_EN; -+ break; -+ -+ case REV_ID_MAJOR_AR913X: -+ uart_en = AR913X_GPIO_FUNC_UART_EN; -+ break; -+ -+ case REV_ID_MAJOR_AR9330: -+ case REV_ID_MAJOR_AR9331: -+ uart_en = AR933X_GPIO_FUNC_UART_EN; -+ break; -+ -+ case REV_ID_MAJOR_AR9341: -+ case REV_ID_MAJOR_AR9342: -+ case REV_ID_MAJOR_AR9344: -+ /* TODO */ -+ default: -+ return; -+ } -+ -+ gpio_base = (void __iomem *)(KSEG1ADDR(AR71XX_GPIO_BASE)); -+ t = __raw_readl(gpio_base + AR71XX_GPIO_REG_FUNC); -+ t |= uart_en; -+ __raw_writel(t, gpio_base + AR71XX_GPIO_REG_FUNC); -+} -+ - static void prom_putchar_init(void) - { - void __iomem *base; -@@ -92,8 +132,10 @@ static void prom_putchar_init(void) - - default: - _prom_putchar = prom_putchar_dummy; -- break; -+ return; - } -+ -+ prom_enable_uart(id); - } - - void prom_putchar(unsigned char ch) diff --git a/target/linux/ath79/patches-4.14/0016-MIPS-ath79-get-PCIe-controller-out-of-reset.patch b/target/linux/ath79/patches-4.14/0016-MIPS-ath79-get-PCIe-controller-out-of-reset.patch deleted file mode 100644 index 05f15b1df7ec..000000000000 --- a/target/linux/ath79/patches-4.14/0016-MIPS-ath79-get-PCIe-controller-out-of-reset.patch +++ /dev/null @@ -1,101 +0,0 @@ -From d3fa9694bc71338161ae2b9c7ee08b57b8140f93 Mon Sep 17 00:00:00 2001 -From: Mathias Kresin -Date: Tue, 6 Mar 2018 08:37:43 +0100 -Subject: [PATCH 16/33] MIPS: ath79: get PCIe controller out of reset - -The ar724x pci driver expects the PCIe controller to be brought out of -reset by the bootloader. - -At least the AVM Fritz 300E bootloader doesn't take care of releasing -the different PCIe controller related resets which causes an endless -hang as soon as either the PCIE Reset register (0x180f0018) or the PCI -Application Control register (0x180f0000) is read from. - -Do the full "PCIE Root Complex Initialization Sequence" if the PCIe -host controller is still in reset during probing. - -The QCA u-boot sleeps 10ms after the PCIE Application Control bit is -set to ready. It has been shown that 10ms might not be enough time if -PCIe should be used right after setting the bit. During my tests it -took up to 20ms till the link was up. Giving the link up to 100ms -should work for all cases. - -Signed-off-by: Mathias Kresin -Signed-off-by: John Crispin ---- - arch/mips/pci/pci-ar724x.c | 42 ++++++++++++++++++++++++++++++++++++++++++ - 1 file changed, 42 insertions(+) - ---- a/arch/mips/pci/pci-ar724x.c -+++ b/arch/mips/pci/pci-ar724x.c -@@ -12,14 +12,18 @@ - #include - #include - #include -+#include - #include - #include - #include - -+#define AR724X_PCI_REG_APP 0x00 - #define AR724X_PCI_REG_RESET 0x18 - #define AR724X_PCI_REG_INT_STATUS 0x4c - #define AR724X_PCI_REG_INT_MASK 0x50 - -+#define AR724X_PCI_APP_LTSSM_ENABLE BIT(0) -+ - #define AR724X_PCI_RESET_LINK_UP BIT(0) - - #define AR724X_PCI_INT_DEV0 BIT(14) -@@ -325,6 +329,37 @@ static void ar724x_pci_irq_init(struct a - apc); - } - -+static void ar724x_pci_hw_init(struct ar724x_pci_controller *apc) -+{ -+ u32 ppl, app; -+ int wait = 0; -+ -+ /* deassert PCIe host controller and PCIe PHY reset */ -+ ath79_device_reset_clear(AR724X_RESET_PCIE); -+ ath79_device_reset_clear(AR724X_RESET_PCIE_PHY); -+ -+ /* remove the reset of the PCIE PLL */ -+ ppl = ath79_pll_rr(AR724X_PLL_REG_PCIE_CONFIG); -+ ppl &= ~AR724X_PLL_REG_PCIE_CONFIG_PPL_RESET; -+ ath79_pll_wr(AR724X_PLL_REG_PCIE_CONFIG, ppl); -+ -+ /* deassert bypass for the PCIE PLL */ -+ ppl = ath79_pll_rr(AR724X_PLL_REG_PCIE_CONFIG); -+ ppl &= ~AR724X_PLL_REG_PCIE_CONFIG_PPL_BYPASS; -+ ath79_pll_wr(AR724X_PLL_REG_PCIE_CONFIG, ppl); -+ -+ /* set PCIE Application Control to ready */ -+ app = __raw_readl(apc->ctrl_base + AR724X_PCI_REG_APP); -+ app |= AR724X_PCI_APP_LTSSM_ENABLE; -+ __raw_writel(app, apc->ctrl_base + AR724X_PCI_REG_APP); -+ -+ /* wait up to 100ms for PHY link up */ -+ do { -+ mdelay(10); -+ wait++; -+ } while (wait < 10 && !ar724x_pci_check_link(apc)); -+} -+ - static int ar724x_pci_probe(struct platform_device *pdev) - { - struct ar724x_pci_controller *apc; -@@ -383,6 +418,13 @@ static int ar724x_pci_probe(struct platf - apc->pci_controller.io_resource = &apc->io_res; - apc->pci_controller.mem_resource = &apc->mem_res; - -+ /* -+ * Do the full PCIE Root Complex Initialization Sequence if the PCIe -+ * host controller is in reset. -+ */ -+ if (ath79_reset_rr(AR724X_RESET_REG_RESET_MODULE) & AR724X_RESET_PCIE) -+ ar724x_pci_hw_init(apc); -+ - apc->link_up = ar724x_pci_check_link(apc); - if (!apc->link_up) - dev_warn(&pdev->dev, "PCIe link is down\n"); diff --git a/target/linux/ath79/patches-4.14/0017-dt-bindings-PCI-qcom-ar7100-adds-binding-doc.patch b/target/linux/ath79/patches-4.14/0017-dt-bindings-PCI-qcom-ar7100-adds-binding-doc.patch deleted file mode 100644 index bf7eb691a5db..000000000000 --- a/target/linux/ath79/patches-4.14/0017-dt-bindings-PCI-qcom-ar7100-adds-binding-doc.patch +++ /dev/null @@ -1,57 +0,0 @@ -From 4a4f869ec58ed8910b9b2e68d0eee50957e9bb20 Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Mon, 25 Jun 2018 15:52:10 +0200 -Subject: [PATCH 17/33] dt-bindings: PCI: qcom,ar7100: adds binding doc - -With the driver being converted from platform_data to pure OF, we need to -also add some docs. - -Cc: Rob Herring -Cc: devicetree@vger.kernel.org -Signed-off-by: John Crispin ---- - .../devicetree/bindings/pci/qcom,ar7100-pci.txt | 38 ++++++++++++++++++++++ - 1 file changed, 38 insertions(+) - create mode 100644 Documentation/devicetree/bindings/pci/qcom,ar7100-pci.txt - ---- /dev/null -+++ b/Documentation/devicetree/bindings/pci/qcom,ar7100-pci.txt -@@ -0,0 +1,38 @@ -+* Qualcomm Atheros AR7100 PCI express root complex -+ -+Required properties: -+- compatible: should contain "qcom,ar7100-pci" to identify the core. -+- reg: Should contain the register ranges as listed in the reg-names property. -+- reg-names: Definition: Must include the following entries -+ - "cfg_base" IO Memory -+- #address-cells: set to <3> -+- #size-cells: set to <2> -+- ranges: ranges for the PCI memory and I/O regions -+- interrupt-map-mask and interrupt-map: standard PCI -+ properties to define the mapping of the PCIe interface to interrupt -+ numbers. -+- #interrupt-cells: set to <1> -+- interrupt-controller: define to enable the builtin IRQ cascade. -+ -+Optional properties: -+- interrupt-parent: phandle to the MIPS IRQ controller -+ -+* Example for ar7100 -+ pcie-controller@180c0000 { -+ compatible = "qca,ar7100-pci"; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ bus-range = <0x0 0x0>; -+ reg = <0x17010000 0x100>; -+ reg-names = "cfg_base"; -+ ranges = <0x2000000 0 0x10000000 0x10000000 0 0x07000000 -+ 0x1000000 0 0x00000000 0x00000000 0 0x00000001>; -+ interrupt-parent = <&cpuintc>; -+ interrupts = <2>; -+ -+ interrupt-controller; -+ #interrupt-cells = <1>; -+ -+ interrupt-map-mask = <0 0 0 1>; -+ interrupt-map = <0 0 0 0 &pcie0 0>; -+ }; diff --git a/target/linux/ath79/patches-4.14/0018-MIPS-pci-ar71xx-convert-to-OF.patch b/target/linux/ath79/patches-4.14/0018-MIPS-pci-ar71xx-convert-to-OF.patch deleted file mode 100644 index 91796a12f049..000000000000 --- a/target/linux/ath79/patches-4.14/0018-MIPS-pci-ar71xx-convert-to-OF.patch +++ /dev/null @@ -1,202 +0,0 @@ -From 1855ab6b1d27f5b38a648baf57ff6a534afec26d Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Sat, 23 Jun 2018 15:07:23 +0200 -Subject: [PATCH 18/33] MIPS: pci-ar71xx: convert to OF - -With the ath79 target getting converted to pure OF, we can drop all the -platform data code and add the missing OF bits to the driver. We also add -a irq domain for the PCI/e controllers cascade, thus making it usable from -dts files. - -Signed-off-by: John Crispin ---- - arch/mips/pci/pci-ar71xx.c | 82 +++++++++++++++++++++++----------------------- - 1 file changed, 41 insertions(+), 41 deletions(-) - ---- a/arch/mips/pci/pci-ar71xx.c -+++ b/arch/mips/pci/pci-ar71xx.c -@@ -18,8 +18,11 @@ - #include - #include - #include -+#include - #include - #include -+#include -+#include - - #include - #include -@@ -49,12 +52,13 @@ - #define AR71XX_PCI_IRQ_COUNT 5 - - struct ar71xx_pci_controller { -+ struct device_node *np; - void __iomem *cfg_base; - int irq; -- int irq_base; - struct pci_controller pci_ctrl; - struct resource io_res; - struct resource mem_res; -+ struct irq_domain *domain; - }; - - /* Byte lane enable bits */ -@@ -228,29 +232,30 @@ static struct pci_ops ar71xx_pci_ops = { - - static void ar71xx_pci_irq_handler(struct irq_desc *desc) - { -- struct ar71xx_pci_controller *apc; - void __iomem *base = ath79_reset_base; -+ struct irq_chip *chip = irq_desc_get_chip(desc); -+ struct ar71xx_pci_controller *apc = irq_desc_get_handler_data(desc); - u32 pending; - -- apc = irq_desc_get_handler_data(desc); -- -+ chained_irq_enter(chip, desc); - pending = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_STATUS) & - __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE); - - if (pending & AR71XX_PCI_INT_DEV0) -- generic_handle_irq(apc->irq_base + 0); -+ generic_handle_irq(irq_linear_revmap(apc->domain, 1)); - - else if (pending & AR71XX_PCI_INT_DEV1) -- generic_handle_irq(apc->irq_base + 1); -+ generic_handle_irq(irq_linear_revmap(apc->domain, 2)); - - else if (pending & AR71XX_PCI_INT_DEV2) -- generic_handle_irq(apc->irq_base + 2); -+ generic_handle_irq(irq_linear_revmap(apc->domain, 3)); - - else if (pending & AR71XX_PCI_INT_CORE) -- generic_handle_irq(apc->irq_base + 4); -+ generic_handle_irq(irq_linear_revmap(apc->domain, 4)); - - else - spurious_interrupt(); -+ chained_irq_exit(chip, desc); - } - - static void ar71xx_pci_irq_unmask(struct irq_data *d) -@@ -261,7 +266,7 @@ static void ar71xx_pci_irq_unmask(struct - u32 t; - - apc = irq_data_get_irq_chip_data(d); -- irq = d->irq - apc->irq_base; -+ irq = irq_linear_revmap(apc->domain, d->irq); - - t = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE); - __raw_writel(t | (1 << irq), base + AR71XX_RESET_REG_PCI_INT_ENABLE); -@@ -278,7 +283,7 @@ static void ar71xx_pci_irq_mask(struct i - u32 t; - - apc = irq_data_get_irq_chip_data(d); -- irq = d->irq - apc->irq_base; -+ irq = irq_linear_revmap(apc->domain, d->irq); - - t = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE); - __raw_writel(t & ~(1 << irq), base + AR71XX_RESET_REG_PCI_INT_ENABLE); -@@ -294,24 +299,31 @@ static struct irq_chip ar71xx_pci_irq_ch - .irq_mask_ack = ar71xx_pci_irq_mask, - }; - -+static int ar71xx_pci_irq_map(struct irq_domain *d, -+ unsigned int irq, irq_hw_number_t hw) -+{ -+ struct ar71xx_pci_controller *apc = d->host_data; -+ -+ irq_set_chip_and_handler(irq, &ar71xx_pci_irq_chip, handle_level_irq); -+ irq_set_chip_data(irq, apc); -+ -+ return 0; -+} -+ -+static const struct irq_domain_ops ar71xx_pci_domain_ops = { -+ .xlate = irq_domain_xlate_onecell, -+ .map = ar71xx_pci_irq_map, -+}; -+ - static void ar71xx_pci_irq_init(struct ar71xx_pci_controller *apc) - { - void __iomem *base = ath79_reset_base; -- int i; - - __raw_writel(0, base + AR71XX_RESET_REG_PCI_INT_ENABLE); - __raw_writel(0, base + AR71XX_RESET_REG_PCI_INT_STATUS); - -- BUILD_BUG_ON(ATH79_PCI_IRQ_COUNT < AR71XX_PCI_IRQ_COUNT); -- -- apc->irq_base = ATH79_PCI_IRQ_BASE; -- for (i = apc->irq_base; -- i < apc->irq_base + AR71XX_PCI_IRQ_COUNT; i++) { -- irq_set_chip_and_handler(i, &ar71xx_pci_irq_chip, -- handle_level_irq); -- irq_set_chip_data(i, apc); -- } -- -+ apc->domain = irq_domain_add_linear(apc->np, AR71XX_PCI_IRQ_COUNT, -+ &ar71xx_pci_domain_ops, apc); - irq_set_chained_handler_and_data(apc->irq, ar71xx_pci_irq_handler, - apc); - } -@@ -328,6 +340,11 @@ static void ar71xx_pci_reset(void) - mdelay(100); - } - -+static const struct of_device_id ar71xx_pci_ids[] = { -+ { .compatible = "qca,ar7100-pci" }, -+ {}, -+}; -+ - static int ar71xx_pci_probe(struct platform_device *pdev) - { - struct ar71xx_pci_controller *apc; -@@ -348,26 +365,6 @@ static int ar71xx_pci_probe(struct platf - if (apc->irq < 0) - return -EINVAL; - -- res = platform_get_resource_byname(pdev, IORESOURCE_IO, "io_base"); -- if (!res) -- return -EINVAL; -- -- apc->io_res.parent = res; -- apc->io_res.name = "PCI IO space"; -- apc->io_res.start = res->start; -- apc->io_res.end = res->end; -- apc->io_res.flags = IORESOURCE_IO; -- -- res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mem_base"); -- if (!res) -- return -EINVAL; -- -- apc->mem_res.parent = res; -- apc->mem_res.name = "PCI memory space"; -- apc->mem_res.start = res->start; -- apc->mem_res.end = res->end; -- apc->mem_res.flags = IORESOURCE_MEM; -- - ar71xx_pci_reset(); - - /* setup COMMAND register */ -@@ -380,9 +377,11 @@ static int ar71xx_pci_probe(struct platf - - ar71xx_pci_irq_init(apc); - -+ apc->np = pdev->dev.of_node; - apc->pci_ctrl.pci_ops = &ar71xx_pci_ops; - apc->pci_ctrl.mem_resource = &apc->mem_res; - apc->pci_ctrl.io_resource = &apc->io_res; -+ pci_load_of_ranges(&apc->pci_ctrl, pdev->dev.of_node); - - register_pci_controller(&apc->pci_ctrl); - -@@ -393,6 +392,7 @@ static struct platform_driver ar71xx_pci - .probe = ar71xx_pci_probe, - .driver = { - .name = "ar71xx-pci", -+ .of_match_table = of_match_ptr(ar71xx_pci_ids), - }, - }; - diff --git a/target/linux/ath79/patches-4.14/0019-dt-bindings-PCI-qcom-ar7240-adds-binding-doc.patch b/target/linux/ath79/patches-4.14/0019-dt-bindings-PCI-qcom-ar7240-adds-binding-doc.patch deleted file mode 100644 index a0af79cb4da9..000000000000 --- a/target/linux/ath79/patches-4.14/0019-dt-bindings-PCI-qcom-ar7240-adds-binding-doc.patch +++ /dev/null @@ -1,61 +0,0 @@ -From ea27764bc3ef2a05decf3ae05edffc289cd0d93c Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Mon, 25 Jun 2018 15:52:02 +0200 -Subject: [PATCH 19/33] dt-bindings: PCI: qcom,ar7240: adds binding doc - -With the driver being converted from platform_data to pure OF, we need to -also add some docs. - -Cc: Rob Herring -Cc: devicetree@vger.kernel.org -Signed-off-by: John Crispin ---- - .../devicetree/bindings/pci/qcom,ar7240-pci.txt | 42 ++++++++++++++++++++++ - 1 file changed, 42 insertions(+) - create mode 100644 Documentation/devicetree/bindings/pci/qcom,ar7240-pci.txt - ---- /dev/null -+++ b/Documentation/devicetree/bindings/pci/qcom,ar7240-pci.txt -@@ -0,0 +1,42 @@ -+* Qualcomm Atheros AR724X PCI express root complex -+ -+Required properties: -+- compatible: should contain "qcom,ar7240-pci" to identify the core. -+- reg: Should contain the register ranges as listed in the reg-names property. -+- reg-names: Definition: Must include the following entries -+ - "crp_base" Configuration registers -+ - "ctrl_base" Control registers -+ - "cfg_base" IO Memory -+- #address-cells: set to <3> -+- #size-cells: set to <2> -+- ranges: ranges for the PCI memory and I/O regions -+- interrupt-map-mask and interrupt-map: standard PCI -+ properties to define the mapping of the PCIe interface to interrupt -+ numbers. -+- #interrupt-cells: set to <1> -+- interrupt-parent: phandle to the MIPS IRQ controller -+ -+Optional properties: -+- interrupt-controller: define to enable the builtin IRQ cascade. -+ -+* Example for qca9557 -+ pcie-controller@180c0000 { -+ compatible = "qcom,ar7240-pci"; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ bus-range = <0x0 0x0>; -+ reg = <0x180c0000 0x1000>, -+ <0x180f0000 0x100>, -+ <0x14000000 0x1000>; -+ reg-names = "crp_base", "ctrl_base", "cfg_base"; -+ ranges = <0x2000000 0 0x10000000 0x10000000 0 0x04000000 -+ 0x1000000 0 0x00000000 0x00000000 0 0x00000001>; -+ interrupt-parent = <&intc2>; -+ interrupts = <1>; -+ -+ interrupt-controller; -+ #interrupt-cells = <1>; -+ -+ interrupt-map-mask = <0 0 0 1>; -+ interrupt-map = <0 0 0 0 &pcie0 0>; -+ }; diff --git a/target/linux/ath79/patches-4.14/0020-MIPS-pci-ar724x-convert-to-OF.patch b/target/linux/ath79/patches-4.14/0020-MIPS-pci-ar724x-convert-to-OF.patch deleted file mode 100644 index 936bfd48164f..000000000000 --- a/target/linux/ath79/patches-4.14/0020-MIPS-pci-ar724x-convert-to-OF.patch +++ /dev/null @@ -1,205 +0,0 @@ -From a522ee0199d5d3ea114ca2e211f6ac398d3e8e0b Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Sat, 23 Jun 2018 15:07:37 +0200 -Subject: [PATCH 20/33] MIPS: pci-ar724x: convert to OF - -With the ath79 target getting converted to pure OF, we can drop all the -platform data code and add the missing OF bits to the driver. We also add -a irq domain for the PCI/e controllers cascade, thus making it usable from -dts files. - -Signed-off-by: John Crispin ---- - arch/mips/pci/pci-ar724x.c | 88 ++++++++++++++++++++++------------------------ - 1 file changed, 42 insertions(+), 46 deletions(-) - ---- a/arch/mips/pci/pci-ar724x.c -+++ b/arch/mips/pci/pci-ar724x.c -@@ -14,8 +14,11 @@ - #include - #include - #include -+#include - #include - #include -+#include -+#include - - #define AR724X_PCI_REG_APP 0x00 - #define AR724X_PCI_REG_RESET 0x18 -@@ -45,17 +48,20 @@ struct ar724x_pci_controller { - void __iomem *crp_base; - - int irq; -- int irq_base; - - bool link_up; - bool bar0_is_cached; - u32 bar0_value; - -+ struct device_node *np; - struct pci_controller pci_controller; -+ struct irq_domain *domain; - struct resource io_res; - struct resource mem_res; - }; - -+static struct irq_chip ar724x_pci_irq_chip; -+ - static inline bool ar724x_pci_check_link(struct ar724x_pci_controller *apc) - { - u32 reset; -@@ -231,35 +237,31 @@ static struct pci_ops ar724x_pci_ops = { - - static void ar724x_pci_irq_handler(struct irq_desc *desc) - { -- struct ar724x_pci_controller *apc; -- void __iomem *base; -+ struct irq_chip *chip = irq_desc_get_chip(desc); -+ struct ar724x_pci_controller *apc = irq_desc_get_handler_data(desc); - u32 pending; - -- apc = irq_desc_get_handler_data(desc); -- base = apc->ctrl_base; -- -- pending = __raw_readl(base + AR724X_PCI_REG_INT_STATUS) & -- __raw_readl(base + AR724X_PCI_REG_INT_MASK); -+ chained_irq_enter(chip, desc); -+ pending = __raw_readl(apc->ctrl_base + AR724X_PCI_REG_INT_STATUS) & -+ __raw_readl(apc->ctrl_base + AR724X_PCI_REG_INT_MASK); - - if (pending & AR724X_PCI_INT_DEV0) -- generic_handle_irq(apc->irq_base + 0); -- -+ generic_handle_irq(irq_linear_revmap(apc->domain, 1)); - else - spurious_interrupt(); -+ chained_irq_exit(chip, desc); - } - - static void ar724x_pci_irq_unmask(struct irq_data *d) - { - struct ar724x_pci_controller *apc; - void __iomem *base; -- int offset; - u32 t; - - apc = irq_data_get_irq_chip_data(d); - base = apc->ctrl_base; -- offset = apc->irq_base - d->irq; - -- switch (offset) { -+ switch (irq_linear_revmap(apc->domain, d->irq)) { - case 0: - t = __raw_readl(base + AR724X_PCI_REG_INT_MASK); - __raw_writel(t | AR724X_PCI_INT_DEV0, -@@ -273,14 +275,12 @@ static void ar724x_pci_irq_mask(struct i - { - struct ar724x_pci_controller *apc; - void __iomem *base; -- int offset; - u32 t; - - apc = irq_data_get_irq_chip_data(d); - base = apc->ctrl_base; -- offset = apc->irq_base - d->irq; - -- switch (offset) { -+ switch (irq_linear_revmap(apc->domain, d->irq)) { - case 0: - t = __raw_readl(base + AR724X_PCI_REG_INT_MASK); - __raw_writel(t & ~AR724X_PCI_INT_DEV0, -@@ -305,26 +305,34 @@ static struct irq_chip ar724x_pci_irq_ch - .irq_mask_ack = ar724x_pci_irq_mask, - }; - -+static int ar724x_pci_irq_map(struct irq_domain *d, -+ unsigned int irq, irq_hw_number_t hw) -+{ -+ struct ar724x_pci_controller *apc = d->host_data; -+ -+ irq_set_chip_and_handler(irq, &ar724x_pci_irq_chip, handle_level_irq); -+ irq_set_chip_data(irq, apc); -+ -+ return 0; -+} -+ -+static const struct irq_domain_ops ar724x_pci_domain_ops = { -+ .xlate = irq_domain_xlate_onecell, -+ .map = ar724x_pci_irq_map, -+}; -+ - static void ar724x_pci_irq_init(struct ar724x_pci_controller *apc, - int id) - { - void __iomem *base; -- int i; - - base = apc->ctrl_base; - - __raw_writel(0, base + AR724X_PCI_REG_INT_MASK); - __raw_writel(0, base + AR724X_PCI_REG_INT_STATUS); - -- apc->irq_base = ATH79_PCI_IRQ_BASE + (id * AR724X_PCI_IRQ_COUNT); -- -- for (i = apc->irq_base; -- i < apc->irq_base + AR724X_PCI_IRQ_COUNT; i++) { -- irq_set_chip_and_handler(i, &ar724x_pci_irq_chip, -- handle_level_irq); -- irq_set_chip_data(i, apc); -- } -- -+ apc->domain = irq_domain_add_linear(apc->np, 2, -+ &ar724x_pci_domain_ops, apc); - irq_set_chained_handler_and_data(apc->irq, ar724x_pci_irq_handler, - apc); - } -@@ -394,29 +402,11 @@ static int ar724x_pci_probe(struct platf - if (apc->irq < 0) - return -EINVAL; - -- res = platform_get_resource_byname(pdev, IORESOURCE_IO, "io_base"); -- if (!res) -- return -EINVAL; -- -- apc->io_res.parent = res; -- apc->io_res.name = "PCI IO space"; -- apc->io_res.start = res->start; -- apc->io_res.end = res->end; -- apc->io_res.flags = IORESOURCE_IO; -- -- res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mem_base"); -- if (!res) -- return -EINVAL; -- -- apc->mem_res.parent = res; -- apc->mem_res.name = "PCI memory space"; -- apc->mem_res.start = res->start; -- apc->mem_res.end = res->end; -- apc->mem_res.flags = IORESOURCE_MEM; -- -+ apc->np = pdev->dev.of_node; - apc->pci_controller.pci_ops = &ar724x_pci_ops; - apc->pci_controller.io_resource = &apc->io_res; - apc->pci_controller.mem_resource = &apc->mem_res; -+ pci_load_of_ranges(&apc->pci_controller, pdev->dev.of_node); - - /* - * Do the full PCIE Root Complex Initialization Sequence if the PCIe -@@ -438,10 +428,16 @@ static int ar724x_pci_probe(struct platf - return 0; - } - -+static const struct of_device_id ar724x_pci_ids[] = { -+ { .compatible = "qcom,ar7240-pci" }, -+ {}, -+}; -+ - static struct platform_driver ar724x_pci_driver = { - .probe = ar724x_pci_probe, - .driver = { - .name = "ar724x-pci", -+ .of_match_table = of_match_ptr(ar724x_pci_ids), - }, - }; - diff --git a/target/linux/ath79/patches-4.14/0021-MIPS-ath79-add-helpers-for-setting-clocks-and-expose.patch b/target/linux/ath79/patches-4.14/0021-MIPS-ath79-add-helpers-for-setting-clocks-and-expose.patch deleted file mode 100644 index c273140dfc43..000000000000 --- a/target/linux/ath79/patches-4.14/0021-MIPS-ath79-add-helpers-for-setting-clocks-and-expose.patch +++ /dev/null @@ -1,243 +0,0 @@ -From 288a8eb0d41f09fda242e05f8a7bd1f5b3489477 Mon Sep 17 00:00:00 2001 -From: Felix Fietkau -Date: Tue, 6 Mar 2018 13:19:26 +0100 -Subject: [PATCH 21/33] MIPS: ath79: add helpers for setting clocks and expose - the ref clock - -Preparation for transitioning the legacy clock setup code over -to OF. - -Signed-off-by: Felix Fietkau -Signed-off-by: John Crispin ---- - arch/mips/ath79/clock.c | 128 ++++++++++++++++++---------------- - include/dt-bindings/clock/ath79-clk.h | 3 +- - 2 files changed, 68 insertions(+), 63 deletions(-) - ---- a/arch/mips/ath79/clock.c -+++ b/arch/mips/ath79/clock.c -@@ -37,20 +37,46 @@ static struct clk_onecell_data clk_data - .clk_num = ARRAY_SIZE(clks), - }; - --static struct clk *__init ath79_add_sys_clkdev( -- const char *id, unsigned long rate) -+static const char * const clk_names[ATH79_CLK_END] = { -+ [ATH79_CLK_CPU] = "cpu", -+ [ATH79_CLK_DDR] = "ddr", -+ [ATH79_CLK_AHB] = "ahb", -+ [ATH79_CLK_REF] = "ref", -+}; -+ -+static const char * __init ath79_clk_name(int type) - { -- struct clk *clk; -- int err; -+ BUG_ON(type >= ARRAY_SIZE(clk_names) || !clk_names[type]); -+ return clk_names[type]; -+} - -- clk = clk_register_fixed_rate(NULL, id, NULL, 0, rate); -+static void __init __ath79_set_clk(int type, const char *name, struct clk *clk) -+{ - if (IS_ERR(clk)) -- panic("failed to allocate %s clock structure", id); -+ panic("failed to allocate %s clock structure", clk_names[type]); - -- err = clk_register_clkdev(clk, id, NULL); -- if (err) -- panic("unable to register %s clock device", id); -+ clks[type] = clk; -+ clk_register_clkdev(clk, name, NULL); -+} - -+static struct clk * __init ath79_set_clk(int type, unsigned long rate) -+{ -+ const char *name = ath79_clk_name(type); -+ struct clk *clk; -+ -+ clk = clk_register_fixed_rate(NULL, name, NULL, 0, rate); -+ __ath79_set_clk(type, name, clk); -+ return clk; -+} -+ -+static struct clk * __init ath79_set_ff_clk(int type, const char *parent, -+ unsigned int mult, unsigned int div) -+{ -+ const char *name = ath79_clk_name(type); -+ struct clk *clk; -+ -+ clk = clk_register_fixed_factor(NULL, name, parent, 0, mult, div); -+ __ath79_set_clk(type, name, clk); - return clk; - } - -@@ -80,27 +106,15 @@ static void __init ar71xx_clocks_init(vo - div = (((pll >> AR71XX_AHB_DIV_SHIFT) & AR71XX_AHB_DIV_MASK) + 1) * 2; - ahb_rate = cpu_rate / div; - -- ath79_add_sys_clkdev("ref", ref_rate); -- clks[ATH79_CLK_CPU] = ath79_add_sys_clkdev("cpu", cpu_rate); -- clks[ATH79_CLK_DDR] = ath79_add_sys_clkdev("ddr", ddr_rate); -- clks[ATH79_CLK_AHB] = ath79_add_sys_clkdev("ahb", ahb_rate); -+ ath79_set_clk(ATH79_CLK_REF, ref_rate); -+ ath79_set_clk(ATH79_CLK_CPU, cpu_rate); -+ ath79_set_clk(ATH79_CLK_DDR, ddr_rate); -+ ath79_set_clk(ATH79_CLK_AHB, ahb_rate); - - clk_add_alias("wdt", NULL, "ahb", NULL); - clk_add_alias("uart", NULL, "ahb", NULL); - } - --static struct clk * __init ath79_reg_ffclk(const char *name, -- const char *parent_name, unsigned int mult, unsigned int div) --{ -- struct clk *clk; -- -- clk = clk_register_fixed_factor(NULL, name, parent_name, 0, mult, div); -- if (IS_ERR(clk)) -- panic("failed to allocate %s clock structure", name); -- -- return clk; --} -- - static void __init ar724x_clk_init(struct clk *ref_clk, void __iomem *pll_base) - { - u32 pll; -@@ -114,24 +128,19 @@ static void __init ar724x_clk_init(struc - ddr_div = ((pll >> AR724X_DDR_DIV_SHIFT) & AR724X_DDR_DIV_MASK) + 1; - ahb_div = (((pll >> AR724X_AHB_DIV_SHIFT) & AR724X_AHB_DIV_MASK) + 1) * 2; - -- clks[ATH79_CLK_CPU] = ath79_reg_ffclk("cpu", "ref", mult, div); -- clks[ATH79_CLK_DDR] = ath79_reg_ffclk("ddr", "ref", mult, div * ddr_div); -- clks[ATH79_CLK_AHB] = ath79_reg_ffclk("ahb", "ref", mult, div * ahb_div); -+ ath79_set_ff_clk(ATH79_CLK_CPU, "ref", mult, div); -+ ath79_set_ff_clk(ATH79_CLK_DDR, "ref", mult, div * ddr_div); -+ ath79_set_ff_clk(ATH79_CLK_AHB, "ref", mult, div * ahb_div); - } - - static void __init ar724x_clocks_init(void) - { - struct clk *ref_clk; - -- ref_clk = ath79_add_sys_clkdev("ref", AR724X_BASE_FREQ); -+ ref_clk = ath79_set_clk(ATH79_CLK_REF, AR724X_BASE_FREQ); - - ar724x_clk_init(ref_clk, ath79_pll_base); - -- /* just make happy plat_time_init() from arch/mips/ath79/setup.c */ -- clk_register_clkdev(clks[ATH79_CLK_CPU], "cpu", NULL); -- clk_register_clkdev(clks[ATH79_CLK_DDR], "ddr", NULL); -- clk_register_clkdev(clks[ATH79_CLK_AHB], "ahb", NULL); -- - clk_add_alias("wdt", NULL, "ahb", NULL); - clk_add_alias("uart", NULL, "ahb", NULL); - } -@@ -186,12 +195,12 @@ static void __init ar9330_clk_init(struc - AR933X_PLL_CLOCK_CTRL_AHB_DIV_MASK) + 1; - } - -- clks[ATH79_CLK_CPU] = ath79_reg_ffclk("cpu", "ref", -- ninit_mul, ref_div * out_div * cpu_div); -- clks[ATH79_CLK_DDR] = ath79_reg_ffclk("ddr", "ref", -- ninit_mul, ref_div * out_div * ddr_div); -- clks[ATH79_CLK_AHB] = ath79_reg_ffclk("ahb", "ref", -- ninit_mul, ref_div * out_div * ahb_div); -+ ath79_set_ff_clk(ATH79_CLK_CPU, "ref", ninit_mul, -+ ref_div * out_div * cpu_div); -+ ath79_set_ff_clk(ATH79_CLK_DDR, "ref", ninit_mul, -+ ref_div * out_div * ddr_div); -+ ath79_set_ff_clk(ATH79_CLK_AHB, "ref", ninit_mul, -+ ref_div * out_div * ahb_div); - } - - static void __init ar933x_clocks_init(void) -@@ -206,15 +215,10 @@ static void __init ar933x_clocks_init(vo - else - ref_rate = (25 * 1000 * 1000); - -- ref_clk = ath79_add_sys_clkdev("ref", ref_rate); -+ ref_clk = ath79_set_clk(ATH79_CLK_REF, ref_rate); - - ar9330_clk_init(ref_clk, ath79_pll_base); - -- /* just make happy plat_time_init() from arch/mips/ath79/setup.c */ -- clk_register_clkdev(clks[ATH79_CLK_CPU], "cpu", NULL); -- clk_register_clkdev(clks[ATH79_CLK_DDR], "ddr", NULL); -- clk_register_clkdev(clks[ATH79_CLK_AHB], "ahb", NULL); -- - clk_add_alias("wdt", NULL, "ahb", NULL); - clk_add_alias("uart", NULL, "ref", NULL); - } -@@ -344,10 +348,10 @@ static void __init ar934x_clocks_init(vo - else - ahb_rate = cpu_pll / (postdiv + 1); - -- ath79_add_sys_clkdev("ref", ref_rate); -- clks[ATH79_CLK_CPU] = ath79_add_sys_clkdev("cpu", cpu_rate); -- clks[ATH79_CLK_DDR] = ath79_add_sys_clkdev("ddr", ddr_rate); -- clks[ATH79_CLK_AHB] = ath79_add_sys_clkdev("ahb", ahb_rate); -+ ath79_set_clk(ATH79_CLK_REF, ref_rate); -+ ath79_set_clk(ATH79_CLK_CPU, cpu_rate); -+ ath79_set_clk(ATH79_CLK_DDR, ddr_rate); -+ ath79_set_clk(ATH79_CLK_AHB, ahb_rate); - - clk_add_alias("wdt", NULL, "ref", NULL); - clk_add_alias("uart", NULL, "ref", NULL); -@@ -431,10 +435,10 @@ static void __init qca953x_clocks_init(v - else - ahb_rate = cpu_pll / (postdiv + 1); - -- ath79_add_sys_clkdev("ref", ref_rate); -- ath79_add_sys_clkdev("cpu", cpu_rate); -- ath79_add_sys_clkdev("ddr", ddr_rate); -- ath79_add_sys_clkdev("ahb", ahb_rate); -+ ath79_set_clk(ATH79_CLK_REF, ref_rate); -+ ath79_set_clk(ATH79_CLK_CPU, cpu_rate); -+ ath79_set_clk(ATH79_CLK_DDR, ddr_rate); -+ ath79_set_clk(ATH79_CLK_AHB, ahb_rate); - - clk_add_alias("wdt", NULL, "ref", NULL); - clk_add_alias("uart", NULL, "ref", NULL); -@@ -516,10 +520,10 @@ static void __init qca955x_clocks_init(v - else - ahb_rate = cpu_pll / (postdiv + 1); - -- ath79_add_sys_clkdev("ref", ref_rate); -- clks[ATH79_CLK_CPU] = ath79_add_sys_clkdev("cpu", cpu_rate); -- clks[ATH79_CLK_DDR] = ath79_add_sys_clkdev("ddr", ddr_rate); -- clks[ATH79_CLK_AHB] = ath79_add_sys_clkdev("ahb", ahb_rate); -+ ath79_set_clk(ATH79_CLK_REF, ref_rate); -+ ath79_set_clk(ATH79_CLK_CPU, cpu_rate); -+ ath79_set_clk(ATH79_CLK_DDR, ddr_rate); -+ ath79_set_clk(ATH79_CLK_AHB, ahb_rate); - - clk_add_alias("wdt", NULL, "ref", NULL); - clk_add_alias("uart", NULL, "ref", NULL); -@@ -620,10 +624,10 @@ static void __init qca956x_clocks_init(v - else - ahb_rate = cpu_pll / (postdiv + 1); - -- ath79_add_sys_clkdev("ref", ref_rate); -- ath79_add_sys_clkdev("cpu", cpu_rate); -- ath79_add_sys_clkdev("ddr", ddr_rate); -- ath79_add_sys_clkdev("ahb", ahb_rate); -+ ath79_set_clk(ATH79_CLK_REF, ref_rate); -+ ath79_set_clk(ATH79_CLK_CPU, cpu_rate); -+ ath79_set_clk(ATH79_CLK_DDR, ddr_rate); -+ ath79_set_clk(ATH79_CLK_AHB, ahb_rate); - - clk_add_alias("wdt", NULL, "ref", NULL); - clk_add_alias("uart", NULL, "ref", NULL); ---- a/include/dt-bindings/clock/ath79-clk.h -+++ b/include/dt-bindings/clock/ath79-clk.h -@@ -13,7 +13,8 @@ - #define ATH79_CLK_CPU 0 - #define ATH79_CLK_DDR 1 - #define ATH79_CLK_AHB 2 -+#define ATH79_CLK_REF 3 - --#define ATH79_CLK_END 3 -+#define ATH79_CLK_END 4 - - #endif /* __DT_BINDINGS_ATH79_CLK_H */ diff --git a/target/linux/ath79/patches-4.14/0022-MIPS-ath79-move-legacy-wdt-and-uart-clock-aliases-ou.patch b/target/linux/ath79/patches-4.14/0022-MIPS-ath79-move-legacy-wdt-and-uart-clock-aliases-ou.patch deleted file mode 100644 index 389edc45a840..000000000000 --- a/target/linux/ath79/patches-4.14/0022-MIPS-ath79-move-legacy-wdt-and-uart-clock-aliases-ou.patch +++ /dev/null @@ -1,114 +0,0 @@ -From 339c191a95e978353c9ba3aafab0261e14de109b Mon Sep 17 00:00:00 2001 -From: Felix Fietkau -Date: Tue, 6 Mar 2018 13:22:43 +0100 -Subject: [PATCH 22/33] MIPS: ath79: move legacy "wdt" and "uart" clock aliases - out of soc init - -Preparation for reusing functions for DT - -Signed-off-by: Felix Fietkau -Signed-off-by: John Crispin ---- - arch/mips/ath79/clock.c | 38 +++++++++++++++++--------------------- - 1 file changed, 17 insertions(+), 21 deletions(-) - ---- a/arch/mips/ath79/clock.c -+++ b/arch/mips/ath79/clock.c -@@ -110,9 +110,6 @@ static void __init ar71xx_clocks_init(vo - ath79_set_clk(ATH79_CLK_CPU, cpu_rate); - ath79_set_clk(ATH79_CLK_DDR, ddr_rate); - ath79_set_clk(ATH79_CLK_AHB, ahb_rate); -- -- clk_add_alias("wdt", NULL, "ahb", NULL); -- clk_add_alias("uart", NULL, "ahb", NULL); - } - - static void __init ar724x_clk_init(struct clk *ref_clk, void __iomem *pll_base) -@@ -140,9 +137,6 @@ static void __init ar724x_clocks_init(vo - ref_clk = ath79_set_clk(ATH79_CLK_REF, AR724X_BASE_FREQ); - - ar724x_clk_init(ref_clk, ath79_pll_base); -- -- clk_add_alias("wdt", NULL, "ahb", NULL); -- clk_add_alias("uart", NULL, "ahb", NULL); - } - - static void __init ar9330_clk_init(struct clk *ref_clk, void __iomem *pll_base) -@@ -218,9 +212,6 @@ static void __init ar933x_clocks_init(vo - ref_clk = ath79_set_clk(ATH79_CLK_REF, ref_rate); - - ar9330_clk_init(ref_clk, ath79_pll_base); -- -- clk_add_alias("wdt", NULL, "ahb", NULL); -- clk_add_alias("uart", NULL, "ref", NULL); - } - - static u32 __init ar934x_get_pll_freq(u32 ref, u32 ref_div, u32 nint, u32 nfrac, -@@ -353,9 +344,6 @@ static void __init ar934x_clocks_init(vo - ath79_set_clk(ATH79_CLK_DDR, ddr_rate); - ath79_set_clk(ATH79_CLK_AHB, ahb_rate); - -- clk_add_alias("wdt", NULL, "ref", NULL); -- clk_add_alias("uart", NULL, "ref", NULL); -- - iounmap(dpll_base); - } - -@@ -439,9 +427,6 @@ static void __init qca953x_clocks_init(v - ath79_set_clk(ATH79_CLK_CPU, cpu_rate); - ath79_set_clk(ATH79_CLK_DDR, ddr_rate); - ath79_set_clk(ATH79_CLK_AHB, ahb_rate); -- -- clk_add_alias("wdt", NULL, "ref", NULL); -- clk_add_alias("uart", NULL, "ref", NULL); - } - - static void __init qca955x_clocks_init(void) -@@ -524,9 +509,6 @@ static void __init qca955x_clocks_init(v - ath79_set_clk(ATH79_CLK_CPU, cpu_rate); - ath79_set_clk(ATH79_CLK_DDR, ddr_rate); - ath79_set_clk(ATH79_CLK_AHB, ahb_rate); -- -- clk_add_alias("wdt", NULL, "ref", NULL); -- clk_add_alias("uart", NULL, "ref", NULL); - } - - static void __init qca956x_clocks_init(void) -@@ -628,13 +610,13 @@ static void __init qca956x_clocks_init(v - ath79_set_clk(ATH79_CLK_CPU, cpu_rate); - ath79_set_clk(ATH79_CLK_DDR, ddr_rate); - ath79_set_clk(ATH79_CLK_AHB, ahb_rate); -- -- clk_add_alias("wdt", NULL, "ref", NULL); -- clk_add_alias("uart", NULL, "ref", NULL); - } - - void __init ath79_clocks_init(void) - { -+ const char *wdt; -+ const char *uart; -+ - if (soc_is_ar71xx()) - ar71xx_clocks_init(); - else if (soc_is_ar724x() || soc_is_ar913x()) -@@ -651,6 +633,20 @@ void __init ath79_clocks_init(void) - qca956x_clocks_init(); - else - BUG(); -+ -+ if (soc_is_ar71xx() || soc_is_ar724x() || soc_is_ar913x()) { -+ wdt = "ahb"; -+ uart = "ahb"; -+ } else if (soc_is_ar933x()) { -+ wdt = "ahb"; -+ uart = "ref"; -+ } else { -+ wdt = "ref"; -+ uart = "ref"; -+ } -+ -+ clk_add_alias("wdt", NULL, wdt, NULL); -+ clk_add_alias("uart", NULL, uart, NULL); - } - - unsigned long __init diff --git a/target/linux/ath79/patches-4.14/0023-MIPS-ath79-pass-PLL-base-to-clock-init-functions.patch b/target/linux/ath79/patches-4.14/0023-MIPS-ath79-pass-PLL-base-to-clock-init-functions.patch deleted file mode 100644 index 6c0f2ad54c57..000000000000 --- a/target/linux/ath79/patches-4.14/0023-MIPS-ath79-pass-PLL-base-to-clock-init-functions.patch +++ /dev/null @@ -1,242 +0,0 @@ -From 6350b2c36c522fecbc91a80b63f49319dafd2a72 Mon Sep 17 00:00:00 2001 -From: Felix Fietkau -Date: Tue, 6 Mar 2018 13:23:20 +0100 -Subject: [PATCH 23/33] MIPS: ath79: pass PLL base to clock init functions - -Preparation for passing the mapped base via DT - -Signed-off-by: Felix Fietkau -Signed-off-by: John Crispin ---- - arch/mips/ath79/clock.c | 60 ++++++++++++++++++++++++------------------------- - 1 file changed, 30 insertions(+), 30 deletions(-) - ---- a/arch/mips/ath79/clock.c -+++ b/arch/mips/ath79/clock.c -@@ -80,7 +80,7 @@ static struct clk * __init ath79_set_ff_ - return clk; - } - --static void __init ar71xx_clocks_init(void) -+static void __init ar71xx_clocks_init(void __iomem *pll_base) - { - unsigned long ref_rate; - unsigned long cpu_rate; -@@ -92,7 +92,7 @@ static void __init ar71xx_clocks_init(vo - - ref_rate = AR71XX_BASE_FREQ; - -- pll = ath79_pll_rr(AR71XX_PLL_REG_CPU_CONFIG); -+ pll = __raw_readl(pll_base + AR71XX_PLL_REG_CPU_CONFIG); - - div = ((pll >> AR71XX_PLL_FB_SHIFT) & AR71XX_PLL_FB_MASK) + 1; - freq = div * ref_rate; -@@ -130,13 +130,13 @@ static void __init ar724x_clk_init(struc - ath79_set_ff_clk(ATH79_CLK_AHB, "ref", mult, div * ahb_div); - } - --static void __init ar724x_clocks_init(void) -+static void __init ar724x_clocks_init(void __iomem *pll_base) - { - struct clk *ref_clk; - - ref_clk = ath79_set_clk(ATH79_CLK_REF, AR724X_BASE_FREQ); - -- ar724x_clk_init(ref_clk, ath79_pll_base); -+ ar724x_clk_init(ref_clk, pll_base); - } - - static void __init ar9330_clk_init(struct clk *ref_clk, void __iomem *pll_base) -@@ -197,7 +197,7 @@ static void __init ar9330_clk_init(struc - ref_div * out_div * ahb_div); - } - --static void __init ar933x_clocks_init(void) -+static void __init ar933x_clocks_init(void __iomem *pll_base) - { - struct clk *ref_clk; - unsigned long ref_rate; -@@ -234,7 +234,7 @@ static u32 __init ar934x_get_pll_freq(u3 - return ret; - } - --static void __init ar934x_clocks_init(void) -+static void __init ar934x_clocks_init(void __iomem *pll_base) - { - unsigned long ref_rate; - unsigned long cpu_rate; -@@ -265,7 +265,7 @@ static void __init ar934x_clocks_init(vo - AR934X_SRIF_DPLL1_REFDIV_MASK; - frac = 1 << 18; - } else { -- pll = ath79_pll_rr(AR934X_PLL_CPU_CONFIG_REG); -+ pll = __raw_readl(pll_base + AR934X_PLL_CPU_CONFIG_REG); - out_div = (pll >> AR934X_PLL_CPU_CONFIG_OUTDIV_SHIFT) & - AR934X_PLL_CPU_CONFIG_OUTDIV_MASK; - ref_div = (pll >> AR934X_PLL_CPU_CONFIG_REFDIV_SHIFT) & -@@ -292,7 +292,7 @@ static void __init ar934x_clocks_init(vo - AR934X_SRIF_DPLL1_REFDIV_MASK; - frac = 1 << 18; - } else { -- pll = ath79_pll_rr(AR934X_PLL_DDR_CONFIG_REG); -+ pll = __raw_readl(pll_base + AR934X_PLL_DDR_CONFIG_REG); - out_div = (pll >> AR934X_PLL_DDR_CONFIG_OUTDIV_SHIFT) & - AR934X_PLL_DDR_CONFIG_OUTDIV_MASK; - ref_div = (pll >> AR934X_PLL_DDR_CONFIG_REFDIV_SHIFT) & -@@ -307,7 +307,7 @@ static void __init ar934x_clocks_init(vo - ddr_pll = ar934x_get_pll_freq(ref_rate, ref_div, nint, - nfrac, frac, out_div); - -- clk_ctrl = ath79_pll_rr(AR934X_PLL_CPU_DDR_CLK_CTRL_REG); -+ clk_ctrl = __raw_readl(pll_base + AR934X_PLL_CPU_DDR_CLK_CTRL_REG); - - postdiv = (clk_ctrl >> AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_SHIFT) & - AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_MASK; -@@ -347,7 +347,7 @@ static void __init ar934x_clocks_init(vo - iounmap(dpll_base); - } - --static void __init qca953x_clocks_init(void) -+static void __init qca953x_clocks_init(void __iomem *pll_base) - { - unsigned long ref_rate; - unsigned long cpu_rate; -@@ -363,7 +363,7 @@ static void __init qca953x_clocks_init(v - else - ref_rate = 25 * 1000 * 1000; - -- pll = ath79_pll_rr(QCA953X_PLL_CPU_CONFIG_REG); -+ pll = __raw_readl(pll_base + QCA953X_PLL_CPU_CONFIG_REG); - out_div = (pll >> QCA953X_PLL_CPU_CONFIG_OUTDIV_SHIFT) & - QCA953X_PLL_CPU_CONFIG_OUTDIV_MASK; - ref_div = (pll >> QCA953X_PLL_CPU_CONFIG_REFDIV_SHIFT) & -@@ -377,7 +377,7 @@ static void __init qca953x_clocks_init(v - cpu_pll += frac * (ref_rate >> 6) / ref_div; - cpu_pll /= (1 << out_div); - -- pll = ath79_pll_rr(QCA953X_PLL_DDR_CONFIG_REG); -+ pll = __raw_readl(pll_base + QCA953X_PLL_DDR_CONFIG_REG); - out_div = (pll >> QCA953X_PLL_DDR_CONFIG_OUTDIV_SHIFT) & - QCA953X_PLL_DDR_CONFIG_OUTDIV_MASK; - ref_div = (pll >> QCA953X_PLL_DDR_CONFIG_REFDIV_SHIFT) & -@@ -391,7 +391,7 @@ static void __init qca953x_clocks_init(v - ddr_pll += frac * (ref_rate >> 6) / (ref_div << 4); - ddr_pll /= (1 << out_div); - -- clk_ctrl = ath79_pll_rr(QCA953X_PLL_CLK_CTRL_REG); -+ clk_ctrl = __raw_readl(pll_base + QCA953X_PLL_CLK_CTRL_REG); - - postdiv = (clk_ctrl >> QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT) & - QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_MASK; -@@ -429,7 +429,7 @@ static void __init qca953x_clocks_init(v - ath79_set_clk(ATH79_CLK_AHB, ahb_rate); - } - --static void __init qca955x_clocks_init(void) -+static void __init qca955x_clocks_init(void __iomem *pll_base) - { - unsigned long ref_rate; - unsigned long cpu_rate; -@@ -445,7 +445,7 @@ static void __init qca955x_clocks_init(v - else - ref_rate = 25 * 1000 * 1000; - -- pll = ath79_pll_rr(QCA955X_PLL_CPU_CONFIG_REG); -+ pll = __raw_readl(pll_base + QCA955X_PLL_CPU_CONFIG_REG); - out_div = (pll >> QCA955X_PLL_CPU_CONFIG_OUTDIV_SHIFT) & - QCA955X_PLL_CPU_CONFIG_OUTDIV_MASK; - ref_div = (pll >> QCA955X_PLL_CPU_CONFIG_REFDIV_SHIFT) & -@@ -459,7 +459,7 @@ static void __init qca955x_clocks_init(v - cpu_pll += frac * ref_rate / (ref_div * (1 << 6)); - cpu_pll /= (1 << out_div); - -- pll = ath79_pll_rr(QCA955X_PLL_DDR_CONFIG_REG); -+ pll = __raw_readl(pll_base + QCA955X_PLL_DDR_CONFIG_REG); - out_div = (pll >> QCA955X_PLL_DDR_CONFIG_OUTDIV_SHIFT) & - QCA955X_PLL_DDR_CONFIG_OUTDIV_MASK; - ref_div = (pll >> QCA955X_PLL_DDR_CONFIG_REFDIV_SHIFT) & -@@ -473,7 +473,7 @@ static void __init qca955x_clocks_init(v - ddr_pll += frac * ref_rate / (ref_div * (1 << 10)); - ddr_pll /= (1 << out_div); - -- clk_ctrl = ath79_pll_rr(QCA955X_PLL_CLK_CTRL_REG); -+ clk_ctrl = __raw_readl(pll_base + QCA955X_PLL_CLK_CTRL_REG); - - postdiv = (clk_ctrl >> QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT) & - QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_MASK; -@@ -511,7 +511,7 @@ static void __init qca955x_clocks_init(v - ath79_set_clk(ATH79_CLK_AHB, ahb_rate); - } - --static void __init qca956x_clocks_init(void) -+static void __init qca956x_clocks_init(void __iomem *pll_base) - { - unsigned long ref_rate; - unsigned long cpu_rate; -@@ -537,13 +537,13 @@ static void __init qca956x_clocks_init(v - else - ref_rate = 25 * 1000 * 1000; - -- pll = ath79_pll_rr(QCA956X_PLL_CPU_CONFIG_REG); -+ pll = __raw_readl(pll_base + QCA956X_PLL_CPU_CONFIG_REG); - out_div = (pll >> QCA956X_PLL_CPU_CONFIG_OUTDIV_SHIFT) & - QCA956X_PLL_CPU_CONFIG_OUTDIV_MASK; - ref_div = (pll >> QCA956X_PLL_CPU_CONFIG_REFDIV_SHIFT) & - QCA956X_PLL_CPU_CONFIG_REFDIV_MASK; - -- pll = ath79_pll_rr(QCA956X_PLL_CPU_CONFIG1_REG); -+ pll = __raw_readl(pll_base + QCA956X_PLL_CPU_CONFIG1_REG); - nint = (pll >> QCA956X_PLL_CPU_CONFIG1_NINT_SHIFT) & - QCA956X_PLL_CPU_CONFIG1_NINT_MASK; - hfrac = (pll >> QCA956X_PLL_CPU_CONFIG1_NFRAC_H_SHIFT) & -@@ -556,12 +556,12 @@ static void __init qca956x_clocks_init(v - cpu_pll += (hfrac >> 13) * ref_rate / ref_div; - cpu_pll /= (1 << out_div); - -- pll = ath79_pll_rr(QCA956X_PLL_DDR_CONFIG_REG); -+ pll = __raw_readl(pll_base + QCA956X_PLL_DDR_CONFIG_REG); - out_div = (pll >> QCA956X_PLL_DDR_CONFIG_OUTDIV_SHIFT) & - QCA956X_PLL_DDR_CONFIG_OUTDIV_MASK; - ref_div = (pll >> QCA956X_PLL_DDR_CONFIG_REFDIV_SHIFT) & - QCA956X_PLL_DDR_CONFIG_REFDIV_MASK; -- pll = ath79_pll_rr(QCA956X_PLL_DDR_CONFIG1_REG); -+ pll = __raw_readl(pll_base + QCA956X_PLL_DDR_CONFIG1_REG); - nint = (pll >> QCA956X_PLL_DDR_CONFIG1_NINT_SHIFT) & - QCA956X_PLL_DDR_CONFIG1_NINT_MASK; - hfrac = (pll >> QCA956X_PLL_DDR_CONFIG1_NFRAC_H_SHIFT) & -@@ -574,7 +574,7 @@ static void __init qca956x_clocks_init(v - ddr_pll += (hfrac >> 13) * ref_rate / ref_div; - ddr_pll /= (1 << out_div); - -- clk_ctrl = ath79_pll_rr(QCA956X_PLL_CLK_CTRL_REG); -+ clk_ctrl = __raw_readl(pll_base + QCA956X_PLL_CLK_CTRL_REG); - - postdiv = (clk_ctrl >> QCA956X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT) & - QCA956X_PLL_CLK_CTRL_CPU_POST_DIV_MASK; -@@ -618,19 +618,19 @@ void __init ath79_clocks_init(void) - const char *uart; - - if (soc_is_ar71xx()) -- ar71xx_clocks_init(); -+ ar71xx_clocks_init(ath79_pll_base); - else if (soc_is_ar724x() || soc_is_ar913x()) -- ar724x_clocks_init(); -+ ar724x_clocks_init(ath79_pll_base); - else if (soc_is_ar933x()) -- ar933x_clocks_init(); -+ ar933x_clocks_init(ath79_pll_base); - else if (soc_is_ar934x()) -- ar934x_clocks_init(); -+ ar934x_clocks_init(ath79_pll_base); - else if (soc_is_qca953x()) -- qca953x_clocks_init(); -+ qca953x_clocks_init(ath79_pll_base); - else if (soc_is_qca955x()) -- qca955x_clocks_init(); -+ qca955x_clocks_init(ath79_pll_base); - else if (soc_is_qca956x() || soc_is_tp9343()) -- qca956x_clocks_init(); -+ qca956x_clocks_init(ath79_pll_base); - else - BUG(); - diff --git a/target/linux/ath79/patches-4.14/0024-MIPS-ath79-make-specifying-the-reference-clock-in-DT.patch b/target/linux/ath79/patches-4.14/0024-MIPS-ath79-make-specifying-the-reference-clock-in-DT.patch deleted file mode 100644 index 9ceb64380396..000000000000 --- a/target/linux/ath79/patches-4.14/0024-MIPS-ath79-make-specifying-the-reference-clock-in-DT.patch +++ /dev/null @@ -1,229 +0,0 @@ -From 5fadb2544ed0bb72ddddd846aa303bb9ed2d211c Mon Sep 17 00:00:00 2001 -From: Felix Fietkau -Date: Tue, 6 Mar 2018 13:24:07 +0100 -Subject: [PATCH 24/33] MIPS: ath79: make specifying the reference clock in DT - optional - -It can be autodetected for many SoCs using the strapping options. -If the clock is specified in DT, the autodetected value is ignored - -Signed-off-by: Felix Fietkau -Signed-off-by: John Crispin ---- - arch/mips/ath79/clock.c | 84 +++++++++++++++++++++++-------------------------- - 1 file changed, 40 insertions(+), 44 deletions(-) - ---- a/arch/mips/ath79/clock.c -+++ b/arch/mips/ath79/clock.c -@@ -80,6 +80,18 @@ static struct clk * __init ath79_set_ff_ - return clk; - } - -+static unsigned long __init ath79_setup_ref_clk(unsigned long rate) -+{ -+ struct clk *clk = clks[ATH79_CLK_REF]; -+ -+ if (clk) -+ rate = clk_get_rate(clk); -+ else -+ clk = ath79_set_clk(ATH79_CLK_REF, rate); -+ -+ return rate; -+} -+ - static void __init ar71xx_clocks_init(void __iomem *pll_base) - { - unsigned long ref_rate; -@@ -90,7 +102,7 @@ static void __init ar71xx_clocks_init(vo - u32 freq; - u32 div; - -- ref_rate = AR71XX_BASE_FREQ; -+ ref_rate = ath79_setup_ref_clk(AR71XX_BASE_FREQ); - - pll = __raw_readl(pll_base + AR71XX_PLL_REG_CPU_CONFIG); - -@@ -106,16 +118,17 @@ static void __init ar71xx_clocks_init(vo - div = (((pll >> AR71XX_AHB_DIV_SHIFT) & AR71XX_AHB_DIV_MASK) + 1) * 2; - ahb_rate = cpu_rate / div; - -- ath79_set_clk(ATH79_CLK_REF, ref_rate); - ath79_set_clk(ATH79_CLK_CPU, cpu_rate); - ath79_set_clk(ATH79_CLK_DDR, ddr_rate); - ath79_set_clk(ATH79_CLK_AHB, ahb_rate); - } - --static void __init ar724x_clk_init(struct clk *ref_clk, void __iomem *pll_base) -+static void __init ar724x_clocks_init(void __iomem *pll_base) - { -- u32 pll; - u32 mult, div, ddr_div, ahb_div; -+ u32 pll; -+ -+ ath79_setup_ref_clk(AR71XX_BASE_FREQ); - - pll = __raw_readl(pll_base + AR724X_PLL_REG_CPU_CONFIG); - -@@ -130,17 +143,9 @@ static void __init ar724x_clk_init(struc - ath79_set_ff_clk(ATH79_CLK_AHB, "ref", mult, div * ahb_div); - } - --static void __init ar724x_clocks_init(void __iomem *pll_base) --{ -- struct clk *ref_clk; -- -- ref_clk = ath79_set_clk(ATH79_CLK_REF, AR724X_BASE_FREQ); -- -- ar724x_clk_init(ref_clk, pll_base); --} -- --static void __init ar9330_clk_init(struct clk *ref_clk, void __iomem *pll_base) -+static void __init ar933x_clocks_init(void __iomem *pll_base) - { -+ unsigned long ref_rate; - u32 clock_ctrl; - u32 ref_div; - u32 ninit_mul; -@@ -149,6 +154,15 @@ static void __init ar9330_clk_init(struc - u32 cpu_div; - u32 ddr_div; - u32 ahb_div; -+ u32 t; -+ -+ t = ath79_reset_rr(AR933X_RESET_REG_BOOTSTRAP); -+ if (t & AR933X_BOOTSTRAP_REF_CLK_40) -+ ref_rate = (40 * 1000 * 1000); -+ else -+ ref_rate = (25 * 1000 * 1000); -+ -+ ath79_setup_ref_clk(ref_rate); - - clock_ctrl = __raw_readl(pll_base + AR933X_PLL_CLOCK_CTRL_REG); - if (clock_ctrl & AR933X_PLL_CLOCK_CTRL_BYPASS) { -@@ -197,23 +211,6 @@ static void __init ar9330_clk_init(struc - ref_div * out_div * ahb_div); - } - --static void __init ar933x_clocks_init(void __iomem *pll_base) --{ -- struct clk *ref_clk; -- unsigned long ref_rate; -- u32 t; -- -- t = ath79_reset_rr(AR933X_RESET_REG_BOOTSTRAP); -- if (t & AR933X_BOOTSTRAP_REF_CLK_40) -- ref_rate = (40 * 1000 * 1000); -- else -- ref_rate = (25 * 1000 * 1000); -- -- ref_clk = ath79_set_clk(ATH79_CLK_REF, ref_rate); -- -- ar9330_clk_init(ref_clk, ath79_pll_base); --} -- - static u32 __init ar934x_get_pll_freq(u32 ref, u32 ref_div, u32 nint, u32 nfrac, - u32 frac, u32 out_div) - { -@@ -253,6 +250,8 @@ static void __init ar934x_clocks_init(vo - else - ref_rate = 25 * 1000 * 1000; - -+ ref_rate = ath79_setup_ref_clk(ref_rate); -+ - pll = __raw_readl(dpll_base + AR934X_SRIF_CPU_DPLL2_REG); - if (pll & AR934X_SRIF_DPLL2_LOCAL_PLL) { - out_div = (pll >> AR934X_SRIF_DPLL2_OUTDIV_SHIFT) & -@@ -339,7 +338,6 @@ static void __init ar934x_clocks_init(vo - else - ahb_rate = cpu_pll / (postdiv + 1); - -- ath79_set_clk(ATH79_CLK_REF, ref_rate); - ath79_set_clk(ATH79_CLK_CPU, cpu_rate); - ath79_set_clk(ATH79_CLK_DDR, ddr_rate); - ath79_set_clk(ATH79_CLK_AHB, ahb_rate); -@@ -363,6 +361,8 @@ static void __init qca953x_clocks_init(v - else - ref_rate = 25 * 1000 * 1000; - -+ ref_rate = ath79_setup_ref_clk(ref_rate); -+ - pll = __raw_readl(pll_base + QCA953X_PLL_CPU_CONFIG_REG); - out_div = (pll >> QCA953X_PLL_CPU_CONFIG_OUTDIV_SHIFT) & - QCA953X_PLL_CPU_CONFIG_OUTDIV_MASK; -@@ -423,7 +423,6 @@ static void __init qca953x_clocks_init(v - else - ahb_rate = cpu_pll / (postdiv + 1); - -- ath79_set_clk(ATH79_CLK_REF, ref_rate); - ath79_set_clk(ATH79_CLK_CPU, cpu_rate); - ath79_set_clk(ATH79_CLK_DDR, ddr_rate); - ath79_set_clk(ATH79_CLK_AHB, ahb_rate); -@@ -445,6 +444,8 @@ static void __init qca955x_clocks_init(v - else - ref_rate = 25 * 1000 * 1000; - -+ ref_rate = ath79_setup_ref_clk(ref_rate); -+ - pll = __raw_readl(pll_base + QCA955X_PLL_CPU_CONFIG_REG); - out_div = (pll >> QCA955X_PLL_CPU_CONFIG_OUTDIV_SHIFT) & - QCA955X_PLL_CPU_CONFIG_OUTDIV_MASK; -@@ -505,7 +506,6 @@ static void __init qca955x_clocks_init(v - else - ahb_rate = cpu_pll / (postdiv + 1); - -- ath79_set_clk(ATH79_CLK_REF, ref_rate); - ath79_set_clk(ATH79_CLK_CPU, cpu_rate); - ath79_set_clk(ATH79_CLK_DDR, ddr_rate); - ath79_set_clk(ATH79_CLK_AHB, ahb_rate); -@@ -537,6 +537,8 @@ static void __init qca956x_clocks_init(v - else - ref_rate = 25 * 1000 * 1000; - -+ ref_rate = ath79_setup_ref_clk(ref_rate); -+ - pll = __raw_readl(pll_base + QCA956X_PLL_CPU_CONFIG_REG); - out_div = (pll >> QCA956X_PLL_CPU_CONFIG_OUTDIV_SHIFT) & - QCA956X_PLL_CPU_CONFIG_OUTDIV_MASK; -@@ -606,7 +608,6 @@ static void __init qca956x_clocks_init(v - else - ahb_rate = cpu_pll / (postdiv + 1); - -- ath79_set_clk(ATH79_CLK_REF, ref_rate); - ath79_set_clk(ATH79_CLK_CPU, cpu_rate); - ath79_set_clk(ATH79_CLK_DDR, ddr_rate); - ath79_set_clk(ATH79_CLK_AHB, ahb_rate); -@@ -682,10 +683,8 @@ static void __init ath79_clocks_init_dt_ - void __iomem *pll_base; - - ref_clk = of_clk_get(np, 0); -- if (IS_ERR(ref_clk)) { -- pr_err("%pOF: of_clk_get failed\n", np); -- goto err; -- } -+ if (!IS_ERR(ref_clk)) -+ clks[ATH79_CLK_REF] = ref_clk; - - pll_base = of_iomap(np, 0); - if (!pll_base) { -@@ -694,9 +693,9 @@ static void __init ath79_clocks_init_dt_ - } - - if (of_device_is_compatible(np, "qca,ar9130-pll")) -- ar724x_clk_init(ref_clk, pll_base); -+ ar724x_clocks_init(pll_base); - else if (of_device_is_compatible(np, "qca,ar9330-pll")) -- ar9330_clk_init(ref_clk, pll_base); -+ ar933x_clocks_init(pll_base); - else { - pr_err("%pOF: could not find any appropriate clk_init()\n", np); - goto err_iounmap; -@@ -714,9 +713,6 @@ err_iounmap: - - err_clk: - clk_put(ref_clk); -- --err: -- return; - } - CLK_OF_DECLARE(ar9130_clk, "qca,ar9130-pll", ath79_clocks_init_dt_ng); - CLK_OF_DECLARE(ar9330_clk, "qca,ar9330-pll", ath79_clocks_init_dt_ng); diff --git a/target/linux/ath79/patches-4.14/0025-MIPS-ath79-support-setting-up-clock-via-DT-on-all-So.patch b/target/linux/ath79/patches-4.14/0025-MIPS-ath79-support-setting-up-clock-via-DT-on-all-So.patch deleted file mode 100644 index 13f46a91464f..000000000000 --- a/target/linux/ath79/patches-4.14/0025-MIPS-ath79-support-setting-up-clock-via-DT-on-all-So.patch +++ /dev/null @@ -1,77 +0,0 @@ -From 6325626de001df98aebe51f3008b1aca05798d19 Mon Sep 17 00:00:00 2001 -From: Felix Fietkau -Date: Tue, 6 Mar 2018 13:26:27 +0100 -Subject: [PATCH 25/33] MIPS: ath79: support setting up clock via DT on all SoC - types - -Use the same functions as the legacy code - -Signed-off-by: Felix Fietkau -Signed-off-by: John Crispin ---- - arch/mips/ath79/clock.c | 39 ++++++++++++++++++++++----------------- - 1 file changed, 22 insertions(+), 17 deletions(-) - ---- a/arch/mips/ath79/clock.c -+++ b/arch/mips/ath79/clock.c -@@ -669,16 +669,6 @@ ath79_get_sys_clk_rate(const char *id) - #ifdef CONFIG_OF - static void __init ath79_clocks_init_dt(struct device_node *np) - { -- of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); --} -- --CLK_OF_DECLARE(ar7100, "qca,ar7100-pll", ath79_clocks_init_dt); --CLK_OF_DECLARE(ar7240, "qca,ar7240-pll", ath79_clocks_init_dt); --CLK_OF_DECLARE(ar9340, "qca,ar9340-pll", ath79_clocks_init_dt); --CLK_OF_DECLARE(ar9550, "qca,qca9550-pll", ath79_clocks_init_dt); -- --static void __init ath79_clocks_init_dt_ng(struct device_node *np) --{ - struct clk *ref_clk; - void __iomem *pll_base; - -@@ -692,14 +682,21 @@ static void __init ath79_clocks_init_dt_ - goto err_clk; - } - -- if (of_device_is_compatible(np, "qca,ar9130-pll")) -+ if (of_device_is_compatible(np, "qca,ar7100-pll")) -+ ar71xx_clocks_init(pll_base); -+ else if (of_device_is_compatible(np, "qca,ar7240-pll") || -+ of_device_is_compatible(np, "qca,ar9130-pll")) - ar724x_clocks_init(pll_base); - else if (of_device_is_compatible(np, "qca,ar9330-pll")) - ar933x_clocks_init(pll_base); -- else { -- pr_err("%pOF: could not find any appropriate clk_init()\n", np); -- goto err_iounmap; -- } -+ else if (of_device_is_compatible(np, "qca,ar9340-pll")) -+ ar934x_clocks_init(pll_base); -+ else if (of_device_is_compatible(np, "qca,qca9530-pll")) -+ qca953x_clocks_init(pll_base); -+ else if (of_device_is_compatible(np, "qca,qca9550-pll")) -+ qca955x_clocks_init(pll_base); -+ else if (of_device_is_compatible(np, "qca,qca9560-pll")) -+ qca956x_clocks_init(pll_base); - - if (of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data)) { - pr_err("%pOF: could not register clk provider\n", np); -@@ -714,6 +711,14 @@ err_iounmap: - err_clk: - clk_put(ref_clk); - } --CLK_OF_DECLARE(ar9130_clk, "qca,ar9130-pll", ath79_clocks_init_dt_ng); --CLK_OF_DECLARE(ar9330_clk, "qca,ar9330-pll", ath79_clocks_init_dt_ng); -+ -+CLK_OF_DECLARE(ar7100_clk, "qca,ar7100-pll", ath79_clocks_init_dt); -+CLK_OF_DECLARE(ar7240_clk, "qca,ar7240-pll", ath79_clocks_init_dt); -+CLK_OF_DECLARE(ar9130_clk, "qca,ar9130-pll", ath79_clocks_init_dt); -+CLK_OF_DECLARE(ar9330_clk, "qca,ar9330-pll", ath79_clocks_init_dt); -+CLK_OF_DECLARE(ar9340_clk, "qca,ar9340-pll", ath79_clocks_init_dt); -+CLK_OF_DECLARE(ar9530_clk, "qca,qca9530-pll", ath79_clocks_init_dt); -+CLK_OF_DECLARE(ar9550_clk, "qca,qca9550-pll", ath79_clocks_init_dt); -+CLK_OF_DECLARE(ar9560_clk, "qca,qca9560-pll", ath79_clocks_init_dt); -+ - #endif diff --git a/target/linux/ath79/patches-4.14/0026-MIPS-ath79-export-switch-MDIO-reference-clock.patch b/target/linux/ath79/patches-4.14/0026-MIPS-ath79-export-switch-MDIO-reference-clock.patch deleted file mode 100644 index 27adb56f560c..000000000000 --- a/target/linux/ath79/patches-4.14/0026-MIPS-ath79-export-switch-MDIO-reference-clock.patch +++ /dev/null @@ -1,59 +0,0 @@ -From 78538d673801902108797f2c813e70cfbce280c9 Mon Sep 17 00:00:00 2001 -From: Felix Fietkau -Date: Tue, 6 Mar 2018 13:27:28 +0100 -Subject: [PATCH 26/33] MIPS: ath79: export switch MDIO reference clock - -On AR934x, the MDIO reference clock can be configured to a fixed 100 MHz -clock. If that feature is not used, it defaults to the main reference -clock, like on all other SoC. - -Signed-off-by: Felix Fietkau -Signed-off-by: John Crispin ---- - arch/mips/ath79/clock.c | 8 ++++++++ - include/dt-bindings/clock/ath79-clk.h | 3 ++- - 2 files changed, 10 insertions(+), 1 deletion(-) - ---- a/arch/mips/ath79/clock.c -+++ b/arch/mips/ath79/clock.c -@@ -42,6 +42,7 @@ static const char * const clk_names[ATH7 - [ATH79_CLK_DDR] = "ddr", - [ATH79_CLK_AHB] = "ahb", - [ATH79_CLK_REF] = "ref", -+ [ATH79_CLK_MDIO] = "mdio", - }; - - static const char * __init ath79_clk_name(int type) -@@ -342,6 +343,10 @@ static void __init ar934x_clocks_init(vo - ath79_set_clk(ATH79_CLK_DDR, ddr_rate); - ath79_set_clk(ATH79_CLK_AHB, ahb_rate); - -+ clk_ctrl = __raw_readl(pll_base + AR934X_PLL_SWITCH_CLOCK_CONTROL_REG); -+ if (clk_ctrl & AR934X_PLL_SWITCH_CLOCK_CONTROL_MDIO_CLK_SEL) -+ ath79_set_clk(ATH79_CLK_MDIO, 100 * 1000 * 1000); -+ - iounmap(dpll_base); - } - -@@ -698,6 +703,9 @@ static void __init ath79_clocks_init_dt( - else if (of_device_is_compatible(np, "qca,qca9560-pll")) - qca956x_clocks_init(pll_base); - -+ if (!clks[ATH79_CLK_MDIO]) -+ clks[ATH79_CLK_MDIO] = clks[ATH79_CLK_REF]; -+ - if (of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data)) { - pr_err("%pOF: could not register clk provider\n", np); - goto err_iounmap; ---- a/include/dt-bindings/clock/ath79-clk.h -+++ b/include/dt-bindings/clock/ath79-clk.h -@@ -14,7 +14,8 @@ - #define ATH79_CLK_DDR 1 - #define ATH79_CLK_AHB 2 - #define ATH79_CLK_REF 3 -+#define ATH79_CLK_MDIO 4 - --#define ATH79_CLK_END 4 -+#define ATH79_CLK_END 5 - - #endif /* __DT_BINDINGS_ATH79_CLK_H */ diff --git a/target/linux/ath79/patches-4.14/0027-MIPS-ath79-drop-legacy-IRQ-code.patch b/target/linux/ath79/patches-4.14/0027-MIPS-ath79-drop-legacy-IRQ-code.patch deleted file mode 100644 index 6586f0843141..000000000000 --- a/target/linux/ath79/patches-4.14/0027-MIPS-ath79-drop-legacy-IRQ-code.patch +++ /dev/null @@ -1,233 +0,0 @@ -From 3765b1f79593a0a9098ed15e48074c95403a53ee Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Sat, 23 Jun 2018 15:05:08 +0200 -Subject: [PATCH 27/33] MIPS: ath79: drop legacy IRQ code - -With the target now being fully OF based, we can drop the legacy IRQ code. -All IRQs are now handled via the new irqchip drivers. - -Signed-off-by: John Crispin ---- - arch/mips/ath79/Makefile | 2 +- - arch/mips/ath79/irq.c | 169 ------------------------------- - arch/mips/ath79/setup.c | 6 ++ - arch/mips/include/asm/mach-ath79/ath79.h | 4 - - 4 files changed, 7 insertions(+), 174 deletions(-) - delete mode 100644 arch/mips/ath79/irq.c - ---- a/arch/mips/ath79/Makefile -+++ b/arch/mips/ath79/Makefile -@@ -8,7 +8,7 @@ - # under the terms of the GNU General Public License version 2 as published - # by the Free Software Foundation. - --obj-y := prom.o setup.o irq.o common.o clock.o -+obj-y := prom.o setup.o common.o clock.o - - obj-$(CONFIG_EARLY_PRINTK) += early_printk.o - obj-$(CONFIG_PCI) += pci.o ---- a/arch/mips/ath79/irq.c -+++ /dev/null -@@ -1,169 +0,0 @@ --/* -- * Atheros AR71xx/AR724x/AR913x specific interrupt handling -- * -- * Copyright (C) 2010-2011 Jaiganesh Narayanan -- * Copyright (C) 2008-2011 Gabor Juhos -- * Copyright (C) 2008 Imre Kaloz -- * -- * Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP -- * -- * This program is free software; you can redistribute it and/or modify it -- * under the terms of the GNU General Public License version 2 as published -- * by the Free Software Foundation. -- */ -- --#include --#include --#include --#include --#include -- --#include --#include -- --#include --#include --#include "common.h" --#include "machtypes.h" -- -- --static void ar934x_ip2_irq_dispatch(struct irq_desc *desc) --{ -- u32 status; -- -- status = ath79_reset_rr(AR934X_RESET_REG_PCIE_WMAC_INT_STATUS); -- -- if (status & AR934X_PCIE_WMAC_INT_PCIE_ALL) { -- ath79_ddr_wb_flush(3); -- generic_handle_irq(ATH79_IP2_IRQ(0)); -- } else if (status & AR934X_PCIE_WMAC_INT_WMAC_ALL) { -- ath79_ddr_wb_flush(4); -- generic_handle_irq(ATH79_IP2_IRQ(1)); -- } else { -- spurious_interrupt(); -- } --} -- --static void ar934x_ip2_irq_init(void) --{ -- int i; -- -- for (i = ATH79_IP2_IRQ_BASE; -- i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++) -- irq_set_chip_and_handler(i, &dummy_irq_chip, -- handle_level_irq); -- -- irq_set_chained_handler(ATH79_CPU_IRQ(2), ar934x_ip2_irq_dispatch); --} -- --static void qca955x_ip2_irq_dispatch(struct irq_desc *desc) --{ -- u32 status; -- -- status = ath79_reset_rr(QCA955X_RESET_REG_EXT_INT_STATUS); -- status &= QCA955X_EXT_INT_PCIE_RC1_ALL | QCA955X_EXT_INT_WMAC_ALL; -- -- if (status == 0) { -- spurious_interrupt(); -- return; -- } -- -- if (status & QCA955X_EXT_INT_PCIE_RC1_ALL) { -- /* TODO: flush DDR? */ -- generic_handle_irq(ATH79_IP2_IRQ(0)); -- } -- -- if (status & QCA955X_EXT_INT_WMAC_ALL) { -- /* TODO: flush DDR? */ -- generic_handle_irq(ATH79_IP2_IRQ(1)); -- } --} -- --static void qca955x_ip3_irq_dispatch(struct irq_desc *desc) --{ -- u32 status; -- -- status = ath79_reset_rr(QCA955X_RESET_REG_EXT_INT_STATUS); -- status &= QCA955X_EXT_INT_PCIE_RC2_ALL | -- QCA955X_EXT_INT_USB1 | -- QCA955X_EXT_INT_USB2; -- -- if (status == 0) { -- spurious_interrupt(); -- return; -- } -- -- if (status & QCA955X_EXT_INT_USB1) { -- /* TODO: flush DDR? */ -- generic_handle_irq(ATH79_IP3_IRQ(0)); -- } -- -- if (status & QCA955X_EXT_INT_USB2) { -- /* TODO: flush DDR? */ -- generic_handle_irq(ATH79_IP3_IRQ(1)); -- } -- -- if (status & QCA955X_EXT_INT_PCIE_RC2_ALL) { -- /* TODO: flush DDR? */ -- generic_handle_irq(ATH79_IP3_IRQ(2)); -- } --} -- --static void qca955x_irq_init(void) --{ -- int i; -- -- for (i = ATH79_IP2_IRQ_BASE; -- i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++) -- irq_set_chip_and_handler(i, &dummy_irq_chip, -- handle_level_irq); -- -- irq_set_chained_handler(ATH79_CPU_IRQ(2), qca955x_ip2_irq_dispatch); -- -- for (i = ATH79_IP3_IRQ_BASE; -- i < ATH79_IP3_IRQ_BASE + ATH79_IP3_IRQ_COUNT; i++) -- irq_set_chip_and_handler(i, &dummy_irq_chip, -- handle_level_irq); -- -- irq_set_chained_handler(ATH79_CPU_IRQ(3), qca955x_ip3_irq_dispatch); --} -- --void __init arch_init_irq(void) --{ -- unsigned irq_wb_chan2 = -1; -- unsigned irq_wb_chan3 = -1; -- bool misc_is_ar71xx; -- -- if (mips_machtype == ATH79_MACH_GENERIC_OF) { -- irqchip_init(); -- return; -- } -- -- if (soc_is_ar71xx() || soc_is_ar724x() || -- soc_is_ar913x() || soc_is_ar933x()) { -- irq_wb_chan2 = 3; -- irq_wb_chan3 = 2; -- } else if (soc_is_ar934x()) { -- irq_wb_chan3 = 2; -- } -- -- ath79_cpu_irq_init(irq_wb_chan2, irq_wb_chan3); -- -- if (soc_is_ar71xx() || soc_is_ar913x()) -- misc_is_ar71xx = true; -- else if (soc_is_ar724x() || -- soc_is_ar933x() || -- soc_is_ar934x() || -- soc_is_qca955x()) -- misc_is_ar71xx = false; -- else -- BUG(); -- ath79_misc_irq_init( -- ath79_reset_base + AR71XX_RESET_REG_MISC_INT_STATUS, -- ATH79_CPU_IRQ(6), ATH79_MISC_IRQ_BASE, misc_is_ar71xx); -- -- if (soc_is_ar934x()) -- ar934x_ip2_irq_init(); -- else if (soc_is_qca955x()) -- qca955x_irq_init(); --} ---- a/arch/mips/ath79/setup.c -+++ b/arch/mips/ath79/setup.c -@@ -19,6 +19,7 @@ - #include - #include - #include -+#include - - #include - #include -@@ -305,6 +306,11 @@ void __init plat_time_init(void) - mips_hpt_frequency = cpu_clk_rate / 2; - } - -+void __init arch_init_irq(void) -+{ -+ irqchip_init(); -+} -+ - static int __init ath79_setup(void) - { - if (mips_machtype == ATH79_MACH_GENERIC_OF) ---- a/arch/mips/include/asm/mach-ath79/ath79.h -+++ b/arch/mips/include/asm/mach-ath79/ath79.h -@@ -178,8 +178,4 @@ static inline u32 ath79_reset_rr(unsigne - void ath79_device_reset_set(u32 mask); - void ath79_device_reset_clear(u32 mask); - --void ath79_cpu_irq_init(unsigned irq_wb_chan2, unsigned irq_wb_chan3); --void ath79_misc_irq_init(void __iomem *regs, int irq, -- int irq_base, bool is_ar71xx); -- - #endif /* __ASM_MACH_ATH79_H */ diff --git a/target/linux/ath79/patches-4.14/0028-MIPS-ath79-drop-machfiles.patch b/target/linux/ath79/patches-4.14/0028-MIPS-ath79-drop-machfiles.patch deleted file mode 100644 index bb5acde8bb9f..000000000000 --- a/target/linux/ath79/patches-4.14/0028-MIPS-ath79-drop-machfiles.patch +++ /dev/null @@ -1,1042 +0,0 @@ -From badf28957b6dc400dff27bd23ba2ae75d9514be5 Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Sat, 23 Jun 2018 15:04:09 +0200 -Subject: [PATCH 28/33] MIPS: ath79: drop machfiles - -With the target now being fully OF based, we can drop the legacy mach -files. Boards can now boot fully of devicetree files. - -Signed-off-by: John Crispin ---- - arch/mips/Kconfig | 1 - - arch/mips/ath79/Kconfig | 73 ------------------- - arch/mips/ath79/Makefile | 10 --- - arch/mips/ath79/clock.c | 1 - - arch/mips/ath79/mach-ap121.c | 92 ------------------------ - arch/mips/ath79/mach-ap136.c | 156 ----------------------------------------- - arch/mips/ath79/mach-ap81.c | 100 -------------------------- - arch/mips/ath79/mach-db120.c | 136 ----------------------------------- - arch/mips/ath79/mach-pb44.c | 128 --------------------------------- - arch/mips/ath79/mach-ubnt-xm.c | 126 --------------------------------- - arch/mips/ath79/machtypes.h | 28 -------- - arch/mips/ath79/setup.c | 77 +++----------------- - 12 files changed, 9 insertions(+), 919 deletions(-) - delete mode 100644 arch/mips/ath79/mach-ap121.c - delete mode 100644 arch/mips/ath79/mach-ap136.c - delete mode 100644 arch/mips/ath79/mach-ap81.c - delete mode 100644 arch/mips/ath79/mach-db120.c - delete mode 100644 arch/mips/ath79/mach-pb44.c - delete mode 100644 arch/mips/ath79/mach-ubnt-xm.c - delete mode 100644 arch/mips/ath79/machtypes.h - ---- a/arch/mips/Kconfig -+++ b/arch/mips/Kconfig -@@ -197,7 +197,6 @@ config ATH79 - select COMMON_CLK - select CLKDEV_LOOKUP - select IRQ_MIPS_CPU -- select MIPS_MACHINE - select SYS_HAS_CPU_MIPS32_R2 - select SYS_HAS_EARLY_PRINTK - select SYS_SUPPORTS_32BIT_KERNEL ---- a/arch/mips/ath79/Kconfig -+++ b/arch/mips/ath79/Kconfig -@@ -1,79 +1,6 @@ - # SPDX-License-Identifier: GPL-2.0 - if ATH79 - --menu "Atheros AR71XX/AR724X/AR913X machine selection" -- --config ATH79_MACH_AP121 -- bool "Atheros AP121 reference board" -- select SOC_AR933X -- select ATH79_DEV_GPIO_BUTTONS -- select ATH79_DEV_LEDS_GPIO -- select ATH79_DEV_SPI -- select ATH79_DEV_USB -- select ATH79_DEV_WMAC -- help -- Say 'Y' here if you want your kernel to support the -- Atheros AP121 reference board. -- --config ATH79_MACH_AP136 -- bool "Atheros AP136 reference board" -- select SOC_QCA955X -- select ATH79_DEV_GPIO_BUTTONS -- select ATH79_DEV_LEDS_GPIO -- select ATH79_DEV_SPI -- select ATH79_DEV_USB -- select ATH79_DEV_WMAC -- help -- Say 'Y' here if you want your kernel to support the -- Atheros AP136 reference board. -- --config ATH79_MACH_AP81 -- bool "Atheros AP81 reference board" -- select SOC_AR913X -- select ATH79_DEV_GPIO_BUTTONS -- select ATH79_DEV_LEDS_GPIO -- select ATH79_DEV_SPI -- select ATH79_DEV_USB -- select ATH79_DEV_WMAC -- help -- Say 'Y' here if you want your kernel to support the -- Atheros AP81 reference board. -- --config ATH79_MACH_DB120 -- bool "Atheros DB120 reference board" -- select SOC_AR934X -- select ATH79_DEV_GPIO_BUTTONS -- select ATH79_DEV_LEDS_GPIO -- select ATH79_DEV_SPI -- select ATH79_DEV_USB -- select ATH79_DEV_WMAC -- help -- Say 'Y' here if you want your kernel to support the -- Atheros DB120 reference board. -- --config ATH79_MACH_PB44 -- bool "Atheros PB44 reference board" -- select SOC_AR71XX -- select ATH79_DEV_GPIO_BUTTONS -- select ATH79_DEV_LEDS_GPIO -- select ATH79_DEV_SPI -- select ATH79_DEV_USB -- help -- Say 'Y' here if you want your kernel to support the -- Atheros PB44 reference board. -- --config ATH79_MACH_UBNT_XM -- bool "Ubiquiti Networks XM (rev 1.0) board" -- select SOC_AR724X -- select ATH79_DEV_GPIO_BUTTONS -- select ATH79_DEV_LEDS_GPIO -- select ATH79_DEV_SPI -- help -- Say 'Y' here if you want your kernel to support the -- Ubiquiti Networks XM (rev 1.0) board. -- --endmenu -- - config SOC_AR71XX - select HW_HAS_PCI - def_bool n ---- a/arch/mips/ath79/Makefile -+++ b/arch/mips/ath79/Makefile -@@ -22,13 +22,3 @@ obj-$(CONFIG_ATH79_DEV_LEDS_GPIO) += dev - obj-$(CONFIG_ATH79_DEV_SPI) += dev-spi.o - obj-$(CONFIG_ATH79_DEV_USB) += dev-usb.o - obj-$(CONFIG_ATH79_DEV_WMAC) += dev-wmac.o -- --# --# Machines --# --obj-$(CONFIG_ATH79_MACH_AP121) += mach-ap121.o --obj-$(CONFIG_ATH79_MACH_AP136) += mach-ap136.o --obj-$(CONFIG_ATH79_MACH_AP81) += mach-ap81.o --obj-$(CONFIG_ATH79_MACH_DB120) += mach-db120.o --obj-$(CONFIG_ATH79_MACH_PB44) += mach-pb44.o --obj-$(CONFIG_ATH79_MACH_UBNT_XM) += mach-ubnt-xm.o ---- a/arch/mips/ath79/clock.c -+++ b/arch/mips/ath79/clock.c -@@ -26,7 +26,6 @@ - #include - #include - #include "common.h" --#include "machtypes.h" - - #define AR71XX_BASE_FREQ 40000000 - #define AR724X_BASE_FREQ 40000000 ---- a/arch/mips/ath79/mach-ap121.c -+++ /dev/null -@@ -1,92 +0,0 @@ --/* -- * Atheros AP121 board support -- * -- * Copyright (C) 2011 Gabor Juhos -- * -- * This program is free software; you can redistribute it and/or modify it -- * under the terms of the GNU General Public License version 2 as published -- * by the Free Software Foundation. -- */ -- --#include "machtypes.h" --#include "dev-gpio-buttons.h" --#include "dev-leds-gpio.h" --#include "dev-spi.h" --#include "dev-usb.h" --#include "dev-wmac.h" -- --#define AP121_GPIO_LED_WLAN 0 --#define AP121_GPIO_LED_USB 1 -- --#define AP121_GPIO_BTN_JUMPSTART 11 --#define AP121_GPIO_BTN_RESET 12 -- --#define AP121_KEYS_POLL_INTERVAL 20 /* msecs */ --#define AP121_KEYS_DEBOUNCE_INTERVAL (3 * AP121_KEYS_POLL_INTERVAL) -- --#define AP121_CAL_DATA_ADDR 0x1fff1000 -- --static struct gpio_led ap121_leds_gpio[] __initdata = { -- { -- .name = "ap121:green:usb", -- .gpio = AP121_GPIO_LED_USB, -- .active_low = 0, -- }, -- { -- .name = "ap121:green:wlan", -- .gpio = AP121_GPIO_LED_WLAN, -- .active_low = 0, -- }, --}; -- --static struct gpio_keys_button ap121_gpio_keys[] __initdata = { -- { -- .desc = "jumpstart button", -- .type = EV_KEY, -- .code = KEY_WPS_BUTTON, -- .debounce_interval = AP121_KEYS_DEBOUNCE_INTERVAL, -- .gpio = AP121_GPIO_BTN_JUMPSTART, -- .active_low = 1, -- }, -- { -- .desc = "reset button", -- .type = EV_KEY, -- .code = KEY_RESTART, -- .debounce_interval = AP121_KEYS_DEBOUNCE_INTERVAL, -- .gpio = AP121_GPIO_BTN_RESET, -- .active_low = 1, -- } --}; -- --static struct spi_board_info ap121_spi_info[] = { -- { -- .bus_num = 0, -- .chip_select = 0, -- .max_speed_hz = 25000000, -- .modalias = "mx25l1606e", -- } --}; -- --static struct ath79_spi_platform_data ap121_spi_data = { -- .bus_num = 0, -- .num_chipselect = 1, --}; -- --static void __init ap121_setup(void) --{ -- u8 *cal_data = (u8 *) KSEG1ADDR(AP121_CAL_DATA_ADDR); -- -- ath79_register_leds_gpio(-1, ARRAY_SIZE(ap121_leds_gpio), -- ap121_leds_gpio); -- ath79_register_gpio_keys_polled(-1, AP121_KEYS_POLL_INTERVAL, -- ARRAY_SIZE(ap121_gpio_keys), -- ap121_gpio_keys); -- -- ath79_register_spi(&ap121_spi_data, ap121_spi_info, -- ARRAY_SIZE(ap121_spi_info)); -- ath79_register_usb(); -- ath79_register_wmac(cal_data); --} -- --MIPS_MACHINE(ATH79_MACH_AP121, "AP121", "Atheros AP121 reference board", -- ap121_setup); ---- a/arch/mips/ath79/mach-ap136.c -+++ /dev/null -@@ -1,156 +0,0 @@ --/* -- * Qualcomm Atheros AP136 reference board support -- * -- * Copyright (c) 2012 Qualcomm Atheros -- * Copyright (c) 2012-2013 Gabor Juhos -- * -- * Permission to use, copy, modify, and/or distribute this software for any -- * purpose with or without fee is hereby granted, provided that the above -- * copyright notice and this permission notice appear in all copies. -- * -- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES -- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF -- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR -- * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES -- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN -- * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF -- * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. -- * -- */ -- --#include --#include -- --#include "machtypes.h" --#include "dev-gpio-buttons.h" --#include "dev-leds-gpio.h" --#include "dev-spi.h" --#include "dev-usb.h" --#include "dev-wmac.h" --#include "pci.h" -- --#define AP136_GPIO_LED_STATUS_RED 14 --#define AP136_GPIO_LED_STATUS_GREEN 19 --#define AP136_GPIO_LED_USB 4 --#define AP136_GPIO_LED_WLAN_2G 13 --#define AP136_GPIO_LED_WLAN_5G 12 --#define AP136_GPIO_LED_WPS_RED 15 --#define AP136_GPIO_LED_WPS_GREEN 20 -- --#define AP136_GPIO_BTN_WPS 16 --#define AP136_GPIO_BTN_RFKILL 21 -- --#define AP136_KEYS_POLL_INTERVAL 20 /* msecs */ --#define AP136_KEYS_DEBOUNCE_INTERVAL (3 * AP136_KEYS_POLL_INTERVAL) -- --#define AP136_WMAC_CALDATA_OFFSET 0x1000 --#define AP136_PCIE_CALDATA_OFFSET 0x5000 -- --static struct gpio_led ap136_leds_gpio[] __initdata = { -- { -- .name = "qca:green:status", -- .gpio = AP136_GPIO_LED_STATUS_GREEN, -- .active_low = 1, -- }, -- { -- .name = "qca:red:status", -- .gpio = AP136_GPIO_LED_STATUS_RED, -- .active_low = 1, -- }, -- { -- .name = "qca:green:wps", -- .gpio = AP136_GPIO_LED_WPS_GREEN, -- .active_low = 1, -- }, -- { -- .name = "qca:red:wps", -- .gpio = AP136_GPIO_LED_WPS_RED, -- .active_low = 1, -- }, -- { -- .name = "qca:red:wlan-2g", -- .gpio = AP136_GPIO_LED_WLAN_2G, -- .active_low = 1, -- }, -- { -- .name = "qca:red:usb", -- .gpio = AP136_GPIO_LED_USB, -- .active_low = 1, -- } --}; -- --static struct gpio_keys_button ap136_gpio_keys[] __initdata = { -- { -- .desc = "WPS button", -- .type = EV_KEY, -- .code = KEY_WPS_BUTTON, -- .debounce_interval = AP136_KEYS_DEBOUNCE_INTERVAL, -- .gpio = AP136_GPIO_BTN_WPS, -- .active_low = 1, -- }, -- { -- .desc = "RFKILL button", -- .type = EV_KEY, -- .code = KEY_RFKILL, -- .debounce_interval = AP136_KEYS_DEBOUNCE_INTERVAL, -- .gpio = AP136_GPIO_BTN_RFKILL, -- .active_low = 1, -- }, --}; -- --static struct spi_board_info ap136_spi_info[] = { -- { -- .bus_num = 0, -- .chip_select = 0, -- .max_speed_hz = 25000000, -- .modalias = "mx25l6405d", -- } --}; -- --static struct ath79_spi_platform_data ap136_spi_data = { -- .bus_num = 0, -- .num_chipselect = 1, --}; -- --#ifdef CONFIG_PCI --static struct ath9k_platform_data ap136_ath9k_data; -- --static int ap136_pci_plat_dev_init(struct pci_dev *dev) --{ -- if (dev->bus->number == 1 && (PCI_SLOT(dev->devfn)) == 0) -- dev->dev.platform_data = &ap136_ath9k_data; -- -- return 0; --} -- --static void __init ap136_pci_init(u8 *eeprom) --{ -- memcpy(ap136_ath9k_data.eeprom_data, eeprom, -- sizeof(ap136_ath9k_data.eeprom_data)); -- -- ath79_pci_set_plat_dev_init(ap136_pci_plat_dev_init); -- ath79_register_pci(); --} --#else --static inline void ap136_pci_init(u8 *eeprom) {} --#endif /* CONFIG_PCI */ -- --static void __init ap136_setup(void) --{ -- u8 *art = (u8 *) KSEG1ADDR(0x1fff0000); -- -- ath79_register_leds_gpio(-1, ARRAY_SIZE(ap136_leds_gpio), -- ap136_leds_gpio); -- ath79_register_gpio_keys_polled(-1, AP136_KEYS_POLL_INTERVAL, -- ARRAY_SIZE(ap136_gpio_keys), -- ap136_gpio_keys); -- ath79_register_spi(&ap136_spi_data, ap136_spi_info, -- ARRAY_SIZE(ap136_spi_info)); -- ath79_register_usb(); -- ath79_register_wmac(art + AP136_WMAC_CALDATA_OFFSET); -- ap136_pci_init(art + AP136_PCIE_CALDATA_OFFSET); --} -- --MIPS_MACHINE(ATH79_MACH_AP136_010, "AP136-010", -- "Atheros AP136-010 reference board", -- ap136_setup); ---- a/arch/mips/ath79/mach-ap81.c -+++ /dev/null -@@ -1,100 +0,0 @@ --/* -- * Atheros AP81 board support -- * -- * Copyright (C) 2009-2010 Gabor Juhos -- * Copyright (C) 2009 Imre Kaloz -- * -- * This program is free software; you can redistribute it and/or modify it -- * under the terms of the GNU General Public License version 2 as published -- * by the Free Software Foundation. -- */ -- --#include "machtypes.h" --#include "dev-wmac.h" --#include "dev-gpio-buttons.h" --#include "dev-leds-gpio.h" --#include "dev-spi.h" --#include "dev-usb.h" -- --#define AP81_GPIO_LED_STATUS 1 --#define AP81_GPIO_LED_AOSS 3 --#define AP81_GPIO_LED_WLAN 6 --#define AP81_GPIO_LED_POWER 14 -- --#define AP81_GPIO_BTN_SW4 12 --#define AP81_GPIO_BTN_SW1 21 -- --#define AP81_KEYS_POLL_INTERVAL 20 /* msecs */ --#define AP81_KEYS_DEBOUNCE_INTERVAL (3 * AP81_KEYS_POLL_INTERVAL) -- --#define AP81_CAL_DATA_ADDR 0x1fff1000 -- --static struct gpio_led ap81_leds_gpio[] __initdata = { -- { -- .name = "ap81:green:status", -- .gpio = AP81_GPIO_LED_STATUS, -- .active_low = 1, -- }, { -- .name = "ap81:amber:aoss", -- .gpio = AP81_GPIO_LED_AOSS, -- .active_low = 1, -- }, { -- .name = "ap81:green:wlan", -- .gpio = AP81_GPIO_LED_WLAN, -- .active_low = 1, -- }, { -- .name = "ap81:green:power", -- .gpio = AP81_GPIO_LED_POWER, -- .active_low = 1, -- } --}; -- --static struct gpio_keys_button ap81_gpio_keys[] __initdata = { -- { -- .desc = "sw1", -- .type = EV_KEY, -- .code = BTN_0, -- .debounce_interval = AP81_KEYS_DEBOUNCE_INTERVAL, -- .gpio = AP81_GPIO_BTN_SW1, -- .active_low = 1, -- } , { -- .desc = "sw4", -- .type = EV_KEY, -- .code = BTN_1, -- .debounce_interval = AP81_KEYS_DEBOUNCE_INTERVAL, -- .gpio = AP81_GPIO_BTN_SW4, -- .active_low = 1, -- } --}; -- --static struct spi_board_info ap81_spi_info[] = { -- { -- .bus_num = 0, -- .chip_select = 0, -- .max_speed_hz = 25000000, -- .modalias = "m25p64", -- } --}; -- --static struct ath79_spi_platform_data ap81_spi_data = { -- .bus_num = 0, -- .num_chipselect = 1, --}; -- --static void __init ap81_setup(void) --{ -- u8 *cal_data = (u8 *) KSEG1ADDR(AP81_CAL_DATA_ADDR); -- -- ath79_register_leds_gpio(-1, ARRAY_SIZE(ap81_leds_gpio), -- ap81_leds_gpio); -- ath79_register_gpio_keys_polled(-1, AP81_KEYS_POLL_INTERVAL, -- ARRAY_SIZE(ap81_gpio_keys), -- ap81_gpio_keys); -- ath79_register_spi(&ap81_spi_data, ap81_spi_info, -- ARRAY_SIZE(ap81_spi_info)); -- ath79_register_wmac(cal_data); -- ath79_register_usb(); --} -- --MIPS_MACHINE(ATH79_MACH_AP81, "AP81", "Atheros AP81 reference board", -- ap81_setup); ---- a/arch/mips/ath79/mach-db120.c -+++ /dev/null -@@ -1,136 +0,0 @@ --/* -- * Atheros DB120 reference board support -- * -- * Copyright (c) 2011 Qualcomm Atheros -- * Copyright (c) 2011 Gabor Juhos -- * -- * Permission to use, copy, modify, and/or distribute this software for any -- * purpose with or without fee is hereby granted, provided that the above -- * copyright notice and this permission notice appear in all copies. -- * -- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES -- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF -- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR -- * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES -- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN -- * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF -- * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. -- * -- */ -- --#include --#include -- --#include "machtypes.h" --#include "dev-gpio-buttons.h" --#include "dev-leds-gpio.h" --#include "dev-spi.h" --#include "dev-usb.h" --#include "dev-wmac.h" --#include "pci.h" -- --#define DB120_GPIO_LED_WLAN_5G 12 --#define DB120_GPIO_LED_WLAN_2G 13 --#define DB120_GPIO_LED_STATUS 14 --#define DB120_GPIO_LED_WPS 15 -- --#define DB120_GPIO_BTN_WPS 16 -- --#define DB120_KEYS_POLL_INTERVAL 20 /* msecs */ --#define DB120_KEYS_DEBOUNCE_INTERVAL (3 * DB120_KEYS_POLL_INTERVAL) -- --#define DB120_WMAC_CALDATA_OFFSET 0x1000 --#define DB120_PCIE_CALDATA_OFFSET 0x5000 -- --static struct gpio_led db120_leds_gpio[] __initdata = { -- { -- .name = "db120:green:status", -- .gpio = DB120_GPIO_LED_STATUS, -- .active_low = 1, -- }, -- { -- .name = "db120:green:wps", -- .gpio = DB120_GPIO_LED_WPS, -- .active_low = 1, -- }, -- { -- .name = "db120:green:wlan-5g", -- .gpio = DB120_GPIO_LED_WLAN_5G, -- .active_low = 1, -- }, -- { -- .name = "db120:green:wlan-2g", -- .gpio = DB120_GPIO_LED_WLAN_2G, -- .active_low = 1, -- }, --}; -- --static struct gpio_keys_button db120_gpio_keys[] __initdata = { -- { -- .desc = "WPS button", -- .type = EV_KEY, -- .code = KEY_WPS_BUTTON, -- .debounce_interval = DB120_KEYS_DEBOUNCE_INTERVAL, -- .gpio = DB120_GPIO_BTN_WPS, -- .active_low = 1, -- }, --}; -- --static struct spi_board_info db120_spi_info[] = { -- { -- .bus_num = 0, -- .chip_select = 0, -- .max_speed_hz = 25000000, -- .modalias = "s25sl064a", -- } --}; -- --static struct ath79_spi_platform_data db120_spi_data = { -- .bus_num = 0, -- .num_chipselect = 1, --}; -- --#ifdef CONFIG_PCI --static struct ath9k_platform_data db120_ath9k_data; -- --static int db120_pci_plat_dev_init(struct pci_dev *dev) --{ -- switch (PCI_SLOT(dev->devfn)) { -- case 0: -- dev->dev.platform_data = &db120_ath9k_data; -- break; -- } -- -- return 0; --} -- --static void __init db120_pci_init(u8 *eeprom) --{ -- memcpy(db120_ath9k_data.eeprom_data, eeprom, -- sizeof(db120_ath9k_data.eeprom_data)); -- -- ath79_pci_set_plat_dev_init(db120_pci_plat_dev_init); -- ath79_register_pci(); --} --#else --static inline void db120_pci_init(u8 *eeprom) {} --#endif /* CONFIG_PCI */ -- --static void __init db120_setup(void) --{ -- u8 *art = (u8 *) KSEG1ADDR(0x1fff0000); -- -- ath79_register_leds_gpio(-1, ARRAY_SIZE(db120_leds_gpio), -- db120_leds_gpio); -- ath79_register_gpio_keys_polled(-1, DB120_KEYS_POLL_INTERVAL, -- ARRAY_SIZE(db120_gpio_keys), -- db120_gpio_keys); -- ath79_register_spi(&db120_spi_data, db120_spi_info, -- ARRAY_SIZE(db120_spi_info)); -- ath79_register_usb(); -- ath79_register_wmac(art + DB120_WMAC_CALDATA_OFFSET); -- db120_pci_init(art + DB120_PCIE_CALDATA_OFFSET); --} -- --MIPS_MACHINE(ATH79_MACH_DB120, "DB120", "Atheros DB120 reference board", -- db120_setup); ---- a/arch/mips/ath79/mach-pb44.c -+++ /dev/null -@@ -1,122 +0,0 @@ --/* -- * Atheros PB44 reference board support -- * -- * Copyright (C) 2009-2010 Gabor Juhos -- * -- * This program is free software; you can redistribute it and/or modify it -- * under the terms of the GNU General Public License version 2 as published -- * by the Free Software Foundation. -- */ -- --#include --#include --#include --#include --#include -- --#include "machtypes.h" --#include "dev-gpio-buttons.h" --#include "dev-leds-gpio.h" --#include "dev-spi.h" --#include "dev-usb.h" --#include "pci.h" -- --#define PB44_GPIO_I2C_SCL 0 --#define PB44_GPIO_I2C_SDA 1 -- --#define PB44_GPIO_EXP_BASE 16 --#define PB44_GPIO_SW_RESET (PB44_GPIO_EXP_BASE + 6) --#define PB44_GPIO_SW_JUMP (PB44_GPIO_EXP_BASE + 8) --#define PB44_GPIO_LED_JUMP1 (PB44_GPIO_EXP_BASE + 9) --#define PB44_GPIO_LED_JUMP2 (PB44_GPIO_EXP_BASE + 10) -- --#define PB44_KEYS_POLL_INTERVAL 20 /* msecs */ --#define PB44_KEYS_DEBOUNCE_INTERVAL (3 * PB44_KEYS_POLL_INTERVAL) -- --static struct i2c_gpio_platform_data pb44_i2c_gpio_data = { -- .sda_pin = PB44_GPIO_I2C_SDA, -- .scl_pin = PB44_GPIO_I2C_SCL, --}; -- --static struct platform_device pb44_i2c_gpio_device = { -- .name = "i2c-gpio", -- .id = 0, -- .dev = { -- .platform_data = &pb44_i2c_gpio_data, -- } --}; -- --static struct pcf857x_platform_data pb44_pcf857x_data = { -- .gpio_base = PB44_GPIO_EXP_BASE, --}; -- --static struct i2c_board_info pb44_i2c_board_info[] __initdata = { -- { -- I2C_BOARD_INFO("pcf8575", 0x20), -- .platform_data = &pb44_pcf857x_data, -- }, --}; -- --static struct gpio_led pb44_leds_gpio[] __initdata = { -- { -- .name = "pb44:amber:jump1", -- .gpio = PB44_GPIO_LED_JUMP1, -- .active_low = 1, -- }, { -- .name = "pb44:green:jump2", -- .gpio = PB44_GPIO_LED_JUMP2, -- .active_low = 1, -- }, --}; -- --static struct gpio_keys_button pb44_gpio_keys[] __initdata = { -- { -- .desc = "soft_reset", -- .type = EV_KEY, -- .code = KEY_RESTART, -- .debounce_interval = PB44_KEYS_DEBOUNCE_INTERVAL, -- .gpio = PB44_GPIO_SW_RESET, -- .active_low = 1, -- } , { -- .desc = "jumpstart", -- .type = EV_KEY, -- .code = KEY_WPS_BUTTON, -- .debounce_interval = PB44_KEYS_DEBOUNCE_INTERVAL, -- .gpio = PB44_GPIO_SW_JUMP, -- .active_low = 1, -- } --}; -- --static struct spi_board_info pb44_spi_info[] = { -- { -- .bus_num = 0, -- .chip_select = 0, -- .max_speed_hz = 25000000, -- .modalias = "m25p64", -- }, --}; -- --static struct ath79_spi_platform_data pb44_spi_data = { -- .bus_num = 0, -- .num_chipselect = 1, --}; -- --static void __init pb44_init(void) --{ -- i2c_register_board_info(0, pb44_i2c_board_info, -- ARRAY_SIZE(pb44_i2c_board_info)); -- platform_device_register(&pb44_i2c_gpio_device); -- -- ath79_register_leds_gpio(-1, ARRAY_SIZE(pb44_leds_gpio), -- pb44_leds_gpio); -- ath79_register_gpio_keys_polled(-1, PB44_KEYS_POLL_INTERVAL, -- ARRAY_SIZE(pb44_gpio_keys), -- pb44_gpio_keys); -- ath79_register_spi(&pb44_spi_data, pb44_spi_info, -- ARRAY_SIZE(pb44_spi_info)); -- ath79_register_usb(); -- ath79_register_pci(); --} -- --MIPS_MACHINE(ATH79_MACH_PB44, "PB44", "Atheros PB44 reference board", -- pb44_init); ---- a/arch/mips/ath79/mach-ubnt-xm.c -+++ /dev/null -@@ -1,126 +0,0 @@ --/* -- * Ubiquiti Networks XM (rev 1.0) board support -- * -- * Copyright (C) 2011 René Bolldorf -- * -- * Derived from: mach-pb44.c -- * -- * This program is free software; you can redistribute it and/or modify it -- * under the terms of the GNU General Public License version 2 as published -- * by the Free Software Foundation. -- */ -- --#include --#include --#include -- --#include -- --#include "machtypes.h" --#include "dev-gpio-buttons.h" --#include "dev-leds-gpio.h" --#include "dev-spi.h" --#include "pci.h" -- --#define UBNT_XM_GPIO_LED_L1 0 --#define UBNT_XM_GPIO_LED_L2 1 --#define UBNT_XM_GPIO_LED_L3 11 --#define UBNT_XM_GPIO_LED_L4 7 -- --#define UBNT_XM_GPIO_BTN_RESET 12 -- --#define UBNT_XM_KEYS_POLL_INTERVAL 20 --#define UBNT_XM_KEYS_DEBOUNCE_INTERVAL (3 * UBNT_XM_KEYS_POLL_INTERVAL) -- --#define UBNT_XM_EEPROM_ADDR (u8 *) KSEG1ADDR(0x1fff1000) -- --static struct gpio_led ubnt_xm_leds_gpio[] __initdata = { -- { -- .name = "ubnt-xm:red:link1", -- .gpio = UBNT_XM_GPIO_LED_L1, -- .active_low = 0, -- }, { -- .name = "ubnt-xm:orange:link2", -- .gpio = UBNT_XM_GPIO_LED_L2, -- .active_low = 0, -- }, { -- .name = "ubnt-xm:green:link3", -- .gpio = UBNT_XM_GPIO_LED_L3, -- .active_low = 0, -- }, { -- .name = "ubnt-xm:green:link4", -- .gpio = UBNT_XM_GPIO_LED_L4, -- .active_low = 0, -- }, --}; -- --static struct gpio_keys_button ubnt_xm_gpio_keys[] __initdata = { -- { -- .desc = "reset", -- .type = EV_KEY, -- .code = KEY_RESTART, -- .debounce_interval = UBNT_XM_KEYS_DEBOUNCE_INTERVAL, -- .gpio = UBNT_XM_GPIO_BTN_RESET, -- .active_low = 1, -- } --}; -- --static struct spi_board_info ubnt_xm_spi_info[] = { -- { -- .bus_num = 0, -- .chip_select = 0, -- .max_speed_hz = 25000000, -- .modalias = "mx25l6405d", -- } --}; -- --static struct ath79_spi_platform_data ubnt_xm_spi_data = { -- .bus_num = 0, -- .num_chipselect = 1, --}; -- --#ifdef CONFIG_PCI --static struct ath9k_platform_data ubnt_xm_eeprom_data; -- --static int ubnt_xm_pci_plat_dev_init(struct pci_dev *dev) --{ -- switch (PCI_SLOT(dev->devfn)) { -- case 0: -- dev->dev.platform_data = &ubnt_xm_eeprom_data; -- break; -- } -- -- return 0; --} -- --static void __init ubnt_xm_pci_init(void) --{ -- memcpy(ubnt_xm_eeprom_data.eeprom_data, UBNT_XM_EEPROM_ADDR, -- sizeof(ubnt_xm_eeprom_data.eeprom_data)); -- -- ath79_pci_set_plat_dev_init(ubnt_xm_pci_plat_dev_init); -- ath79_register_pci(); --} --#else --static inline void ubnt_xm_pci_init(void) {} --#endif /* CONFIG_PCI */ -- --static void __init ubnt_xm_init(void) --{ -- ath79_register_leds_gpio(-1, ARRAY_SIZE(ubnt_xm_leds_gpio), -- ubnt_xm_leds_gpio); -- -- ath79_register_gpio_keys_polled(-1, UBNT_XM_KEYS_POLL_INTERVAL, -- ARRAY_SIZE(ubnt_xm_gpio_keys), -- ubnt_xm_gpio_keys); -- -- ath79_register_spi(&ubnt_xm_spi_data, ubnt_xm_spi_info, -- ARRAY_SIZE(ubnt_xm_spi_info)); -- -- ubnt_xm_pci_init(); --} -- --MIPS_MACHINE(ATH79_MACH_UBNT_XM, -- "UBNT-XM", -- "Ubiquiti Networks XM (rev 1.0) board", -- ubnt_xm_init); ---- a/arch/mips/ath79/machtypes.h -+++ /dev/null -@@ -1,28 +0,0 @@ --/* -- * Atheros AR71XX/AR724X/AR913X machine type definitions -- * -- * Copyright (C) 2008-2010 Gabor Juhos -- * Copyright (C) 2008 Imre Kaloz -- * -- * This program is free software; you can redistribute it and/or modify it -- * under the terms of the GNU General Public License version 2 as published -- * by the Free Software Foundation. -- */ -- --#ifndef _ATH79_MACHTYPE_H --#define _ATH79_MACHTYPE_H -- --#include -- --enum ath79_mach_type { -- ATH79_MACH_GENERIC_OF = -1, /* Device tree board */ -- ATH79_MACH_GENERIC = 0, -- ATH79_MACH_AP121, /* Atheros AP121 reference board */ -- ATH79_MACH_AP136_010, /* Atheros AP136-010 reference board */ -- ATH79_MACH_AP81, /* Atheros AP81 reference board */ -- ATH79_MACH_DB120, /* Atheros DB120 reference board */ -- ATH79_MACH_PB44, /* Atheros PB44 reference board */ -- ATH79_MACH_UBNT_XM, /* Ubiquiti Networks XM board rev 1.0 */ --}; -- --#endif /* _ATH79_MACHTYPE_H */ ---- a/arch/mips/ath79/setup.c -+++ b/arch/mips/ath79/setup.c -@@ -33,7 +33,6 @@ - #include - #include "common.h" - #include "dev-common.h" --#include "machtypes.h" - - #define ATH79_SYS_TYPE_LEN 64 - -@@ -230,25 +229,21 @@ void __init plat_mem_setup(void) - else if (fw_passed_dtb) - __dt_setup_arch((void *)KSEG0ADDR(fw_passed_dtb)); - -- if (mips_machtype != ATH79_MACH_GENERIC_OF) { -- ath79_reset_base = ioremap_nocache(AR71XX_RESET_BASE, -- AR71XX_RESET_SIZE); -- ath79_pll_base = ioremap_nocache(AR71XX_PLL_BASE, -- AR71XX_PLL_SIZE); -- ath79_detect_sys_type(); -- ath79_ddr_ctrl_init(); -+ ath79_reset_base = ioremap_nocache(AR71XX_RESET_BASE, -+ AR71XX_RESET_SIZE); -+ ath79_pll_base = ioremap_nocache(AR71XX_PLL_BASE, -+ AR71XX_PLL_SIZE); -+ ath79_detect_sys_type(); -+ ath79_ddr_ctrl_init(); - -- detect_memory_region(0, ATH79_MEM_SIZE_MIN, ATH79_MEM_SIZE_MAX); -- -- /* OF machines should use the reset driver */ -- _machine_restart = ath79_restart; -- } -+ detect_memory_region(0, ATH79_MEM_SIZE_MIN, ATH79_MEM_SIZE_MAX); - -+ _machine_restart = ath79_restart; - _machine_halt = ath79_halt; - pm_power_off = ath79_halt; - } - --static void __init ath79_of_plat_time_init(void) -+void __init plat_time_init(void) - { - struct device_node *np; - struct clk *clk; -@@ -278,66 +273,12 @@ static void __init ath79_of_plat_time_in - clk_put(clk); - } - --void __init plat_time_init(void) --{ -- unsigned long cpu_clk_rate; -- unsigned long ahb_clk_rate; -- unsigned long ddr_clk_rate; -- unsigned long ref_clk_rate; -- -- if (IS_ENABLED(CONFIG_OF) && mips_machtype == ATH79_MACH_GENERIC_OF) { -- ath79_of_plat_time_init(); -- return; -- } -- -- ath79_clocks_init(); -- -- cpu_clk_rate = ath79_get_sys_clk_rate("cpu"); -- ahb_clk_rate = ath79_get_sys_clk_rate("ahb"); -- ddr_clk_rate = ath79_get_sys_clk_rate("ddr"); -- ref_clk_rate = ath79_get_sys_clk_rate("ref"); -- -- pr_info("Clocks: CPU:%lu.%03luMHz, DDR:%lu.%03luMHz, AHB:%lu.%03luMHz, Ref:%lu.%03luMHz\n", -- cpu_clk_rate / 1000000, (cpu_clk_rate / 1000) % 1000, -- ddr_clk_rate / 1000000, (ddr_clk_rate / 1000) % 1000, -- ahb_clk_rate / 1000000, (ahb_clk_rate / 1000) % 1000, -- ref_clk_rate / 1000000, (ref_clk_rate / 1000) % 1000); -- -- mips_hpt_frequency = cpu_clk_rate / 2; --} -- - void __init arch_init_irq(void) - { - irqchip_init(); - } - --static int __init ath79_setup(void) --{ -- if (mips_machtype == ATH79_MACH_GENERIC_OF) -- return 0; -- -- ath79_gpio_init(); -- ath79_register_uart(); -- ath79_register_wdt(); -- -- mips_machine_setup(); -- -- return 0; --} -- --arch_initcall(ath79_setup); -- - void __init device_tree_init(void) - { - unflatten_and_copy_device_tree(); - } -- --MIPS_MACHINE(ATH79_MACH_GENERIC, -- "Generic", -- "Generic AR71XX/AR724X/AR913X based board", -- NULL); -- --MIPS_MACHINE(ATH79_MACH_GENERIC_OF, -- "DTB", -- "Generic AR71XX/AR724X/AR913X based board (DT)", -- NULL); diff --git a/target/linux/ath79/patches-4.14/0029-MIPS-ath79-drop-legacy-pci-code.patch b/target/linux/ath79/patches-4.14/0029-MIPS-ath79-drop-legacy-pci-code.patch deleted file mode 100644 index 254f2f925342..000000000000 --- a/target/linux/ath79/patches-4.14/0029-MIPS-ath79-drop-legacy-pci-code.patch +++ /dev/null @@ -1,379 +0,0 @@ -From d0f1420702ed47a82572aaf39e7407055518d14e Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Sat, 23 Jun 2018 15:05:19 +0200 -Subject: [PATCH 29/33] MIPS: ath79: drop legacy pci code - -With the target now being fully OF based, we can drop the legacy pci -platform code. The only bits that we need to keep is the fixup code -which we move to its own code file. - -Signed-off-by: John Crispin ---- - arch/mips/ath79/Makefile | 1 - - arch/mips/ath79/pci.c | 273 -------------------------------------------- - arch/mips/ath79/pci.h | 35 ------ - arch/mips/pci/Makefile | 1 + - arch/mips/pci/fixup-ath79.c | 21 ++++ - 5 files changed, 22 insertions(+), 309 deletions(-) - delete mode 100644 arch/mips/ath79/pci.c - delete mode 100644 arch/mips/ath79/pci.h - create mode 100644 arch/mips/pci/fixup-ath79.c - ---- a/arch/mips/ath79/Makefile -+++ b/arch/mips/ath79/Makefile -@@ -11,7 +11,6 @@ - obj-y := prom.o setup.o common.o clock.o - - obj-$(CONFIG_EARLY_PRINTK) += early_printk.o --obj-$(CONFIG_PCI) += pci.o - - # - # Devices ---- a/arch/mips/ath79/pci.c -+++ /dev/null -@@ -1,273 +0,0 @@ --/* -- * Atheros AR71XX/AR724X specific PCI setup code -- * -- * Copyright (C) 2011 René Bolldorf -- * Copyright (C) 2008-2011 Gabor Juhos -- * Copyright (C) 2008 Imre Kaloz -- * -- * Parts of this file are based on Atheros' 2.6.15 BSP -- * -- * This program is free software; you can redistribute it and/or modify it -- * under the terms of the GNU General Public License version 2 as published -- * by the Free Software Foundation. -- */ -- --#include --#include --#include --#include --#include --#include --#include --#include "pci.h" -- --static int (*ath79_pci_plat_dev_init)(struct pci_dev *dev); --static const struct ath79_pci_irq *ath79_pci_irq_map; --static unsigned ath79_pci_nr_irqs; -- --static const struct ath79_pci_irq ar71xx_pci_irq_map[] = { -- { -- .slot = 17, -- .pin = 1, -- .irq = ATH79_PCI_IRQ(0), -- }, { -- .slot = 18, -- .pin = 1, -- .irq = ATH79_PCI_IRQ(1), -- }, { -- .slot = 19, -- .pin = 1, -- .irq = ATH79_PCI_IRQ(2), -- } --}; -- --static const struct ath79_pci_irq ar724x_pci_irq_map[] = { -- { -- .slot = 0, -- .pin = 1, -- .irq = ATH79_PCI_IRQ(0), -- } --}; -- --static const struct ath79_pci_irq qca955x_pci_irq_map[] = { -- { -- .bus = 0, -- .slot = 0, -- .pin = 1, -- .irq = ATH79_PCI_IRQ(0), -- }, -- { -- .bus = 1, -- .slot = 0, -- .pin = 1, -- .irq = ATH79_PCI_IRQ(1), -- }, --}; -- --int pcibios_map_irq(const struct pci_dev *dev, uint8_t slot, uint8_t pin) --{ -- int irq = -1; -- int i; -- -- if (ath79_pci_nr_irqs == 0 || -- ath79_pci_irq_map == NULL) { -- if (soc_is_ar71xx()) { -- ath79_pci_irq_map = ar71xx_pci_irq_map; -- ath79_pci_nr_irqs = ARRAY_SIZE(ar71xx_pci_irq_map); -- } else if (soc_is_ar724x() || -- soc_is_ar9342() || -- soc_is_ar9344()) { -- ath79_pci_irq_map = ar724x_pci_irq_map; -- ath79_pci_nr_irqs = ARRAY_SIZE(ar724x_pci_irq_map); -- } else if (soc_is_qca955x()) { -- ath79_pci_irq_map = qca955x_pci_irq_map; -- ath79_pci_nr_irqs = ARRAY_SIZE(qca955x_pci_irq_map); -- } else { -- pr_crit("pci %s: invalid irq map\n", -- pci_name((struct pci_dev *) dev)); -- return irq; -- } -- } -- -- for (i = 0; i < ath79_pci_nr_irqs; i++) { -- const struct ath79_pci_irq *entry; -- -- entry = &ath79_pci_irq_map[i]; -- if (entry->bus == dev->bus->number && -- entry->slot == slot && -- entry->pin == pin) { -- irq = entry->irq; -- break; -- } -- } -- -- if (irq < 0) -- pr_crit("pci %s: no irq found for pin %u\n", -- pci_name((struct pci_dev *) dev), pin); -- else -- pr_info("pci %s: using irq %d for pin %u\n", -- pci_name((struct pci_dev *) dev), irq, pin); -- -- return irq; --} -- --int pcibios_plat_dev_init(struct pci_dev *dev) --{ -- if (ath79_pci_plat_dev_init) -- return ath79_pci_plat_dev_init(dev); -- -- return 0; --} -- --void __init ath79_pci_set_irq_map(unsigned nr_irqs, -- const struct ath79_pci_irq *map) --{ -- ath79_pci_nr_irqs = nr_irqs; -- ath79_pci_irq_map = map; --} -- --void __init ath79_pci_set_plat_dev_init(int (*func)(struct pci_dev *dev)) --{ -- ath79_pci_plat_dev_init = func; --} -- --static struct platform_device * --ath79_register_pci_ar71xx(void) --{ -- struct platform_device *pdev; -- struct resource res[4]; -- -- memset(res, 0, sizeof(res)); -- -- res[0].name = "cfg_base"; -- res[0].flags = IORESOURCE_MEM; -- res[0].start = AR71XX_PCI_CFG_BASE; -- res[0].end = AR71XX_PCI_CFG_BASE + AR71XX_PCI_CFG_SIZE - 1; -- -- res[1].flags = IORESOURCE_IRQ; -- res[1].start = ATH79_CPU_IRQ(2); -- res[1].end = ATH79_CPU_IRQ(2); -- -- res[2].name = "io_base"; -- res[2].flags = IORESOURCE_IO; -- res[2].start = 0; -- res[2].end = 0; -- -- res[3].name = "mem_base"; -- res[3].flags = IORESOURCE_MEM; -- res[3].start = AR71XX_PCI_MEM_BASE; -- res[3].end = AR71XX_PCI_MEM_BASE + AR71XX_PCI_MEM_SIZE - 1; -- -- pdev = platform_device_register_simple("ar71xx-pci", -1, -- res, ARRAY_SIZE(res)); -- return pdev; --} -- --static struct platform_device * --ath79_register_pci_ar724x(int id, -- unsigned long cfg_base, -- unsigned long ctrl_base, -- unsigned long crp_base, -- unsigned long mem_base, -- unsigned long mem_size, -- unsigned long io_base, -- int irq) --{ -- struct platform_device *pdev; -- struct resource res[6]; -- -- memset(res, 0, sizeof(res)); -- -- res[0].name = "cfg_base"; -- res[0].flags = IORESOURCE_MEM; -- res[0].start = cfg_base; -- res[0].end = cfg_base + AR724X_PCI_CFG_SIZE - 1; -- -- res[1].name = "ctrl_base"; -- res[1].flags = IORESOURCE_MEM; -- res[1].start = ctrl_base; -- res[1].end = ctrl_base + AR724X_PCI_CTRL_SIZE - 1; -- -- res[2].flags = IORESOURCE_IRQ; -- res[2].start = irq; -- res[2].end = irq; -- -- res[3].name = "mem_base"; -- res[3].flags = IORESOURCE_MEM; -- res[3].start = mem_base; -- res[3].end = mem_base + mem_size - 1; -- -- res[4].name = "io_base"; -- res[4].flags = IORESOURCE_IO; -- res[4].start = io_base; -- res[4].end = io_base; -- -- res[5].name = "crp_base"; -- res[5].flags = IORESOURCE_MEM; -- res[5].start = crp_base; -- res[5].end = crp_base + AR724X_PCI_CRP_SIZE - 1; -- -- pdev = platform_device_register_simple("ar724x-pci", id, -- res, ARRAY_SIZE(res)); -- return pdev; --} -- --int __init ath79_register_pci(void) --{ -- struct platform_device *pdev = NULL; -- -- if (soc_is_ar71xx()) { -- pdev = ath79_register_pci_ar71xx(); -- } else if (soc_is_ar724x()) { -- pdev = ath79_register_pci_ar724x(-1, -- AR724X_PCI_CFG_BASE, -- AR724X_PCI_CTRL_BASE, -- AR724X_PCI_CRP_BASE, -- AR724X_PCI_MEM_BASE, -- AR724X_PCI_MEM_SIZE, -- 0, -- ATH79_CPU_IRQ(2)); -- } else if (soc_is_ar9342() || -- soc_is_ar9344()) { -- u32 bootstrap; -- -- bootstrap = ath79_reset_rr(AR934X_RESET_REG_BOOTSTRAP); -- if ((bootstrap & AR934X_BOOTSTRAP_PCIE_RC) == 0) -- return -ENODEV; -- -- pdev = ath79_register_pci_ar724x(-1, -- AR724X_PCI_CFG_BASE, -- AR724X_PCI_CTRL_BASE, -- AR724X_PCI_CRP_BASE, -- AR724X_PCI_MEM_BASE, -- AR724X_PCI_MEM_SIZE, -- 0, -- ATH79_IP2_IRQ(0)); -- } else if (soc_is_qca9558()) { -- pdev = ath79_register_pci_ar724x(0, -- QCA955X_PCI_CFG_BASE0, -- QCA955X_PCI_CTRL_BASE0, -- QCA955X_PCI_CRP_BASE0, -- QCA955X_PCI_MEM_BASE0, -- QCA955X_PCI_MEM_SIZE, -- 0, -- ATH79_IP2_IRQ(0)); -- -- pdev = ath79_register_pci_ar724x(1, -- QCA955X_PCI_CFG_BASE1, -- QCA955X_PCI_CTRL_BASE1, -- QCA955X_PCI_CRP_BASE1, -- QCA955X_PCI_MEM_BASE1, -- QCA955X_PCI_MEM_SIZE, -- 1, -- ATH79_IP3_IRQ(2)); -- } else { -- /* No PCI support */ -- return -ENODEV; -- } -- -- if (!pdev) -- pr_err("unable to register PCI controller device\n"); -- -- return pdev ? 0 : -ENODEV; --} ---- a/arch/mips/ath79/pci.h -+++ /dev/null -@@ -1,35 +0,0 @@ --/* -- * Atheros AR71XX/AR724X PCI support -- * -- * Copyright (C) 2011 René Bolldorf -- * Copyright (C) 2008-2011 Gabor Juhos -- * Copyright (C) 2008 Imre Kaloz -- * -- * This program is free software; you can redistribute it and/or modify it -- * under the terms of the GNU General Public License version 2 as published -- * by the Free Software Foundation. -- */ -- --#ifndef _ATH79_PCI_H --#define _ATH79_PCI_H -- --struct ath79_pci_irq { -- int bus; -- u8 slot; -- u8 pin; -- int irq; --}; -- --#ifdef CONFIG_PCI --void ath79_pci_set_irq_map(unsigned nr_irqs, const struct ath79_pci_irq *map); --void ath79_pci_set_plat_dev_init(int (*func)(struct pci_dev *dev)); --int ath79_register_pci(void); --#else --static inline void --ath79_pci_set_irq_map(unsigned nr_irqs, const struct ath79_pci_irq *map) {} --static inline void --ath79_pci_set_plat_dev_init(int (*func)(struct pci_dev *)) {} --static inline int ath79_register_pci(void) { return 0; } --#endif -- --#endif /* _ATH79_PCI_H */ ---- a/arch/mips/pci/Makefile -+++ b/arch/mips/pci/Makefile -@@ -29,6 +29,7 @@ obj-$(CONFIG_MIPS_PCI_VIRTIO) += pci-vir - # - # These are still pretty much in the old state, watch, go blind. - # -+obj-$(CONFIG_ATH79) += fixup-ath79.o - obj-$(CONFIG_LASAT) += pci-lasat.o - obj-$(CONFIG_MIPS_COBALT) += fixup-cobalt.o - obj-$(CONFIG_LEMOTE_FULOONG2E) += fixup-fuloong2e.o ops-loongson2.o ---- /dev/null -+++ b/arch/mips/pci/fixup-ath79.c -@@ -0,0 +1,21 @@ -+/* -+ * Copyright (C) 2018 John Crispin -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+//#include -+#include -+ -+int pcibios_plat_dev_init(struct pci_dev *dev) -+{ -+ return PCIBIOS_SUCCESSFUL; -+} -+ -+int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) -+{ -+ return of_irq_parse_and_map_pci(dev, slot, pin); -+} diff --git a/target/linux/ath79/patches-4.14/0030-MIPS-ath79-drop-platform-device-registration-code.patch b/target/linux/ath79/patches-4.14/0030-MIPS-ath79-drop-platform-device-registration-code.patch deleted file mode 100644 index 93a133c1dfba..000000000000 --- a/target/linux/ath79/patches-4.14/0030-MIPS-ath79-drop-platform-device-registration-code.patch +++ /dev/null @@ -1,933 +0,0 @@ -From dce930fba8ad3a90ccd164f199e57c2d61937ccd Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Sat, 23 Jun 2018 15:12:38 +0200 -Subject: [PATCH 30/33] MIPS: ath79: drop platform device registration code - -With the target now being fully OF based, we can drop the legacy platform -device registration code. All devices and their drivers are now probed -via OF. - -Signed-off-by: John Crispin ---- - arch/mips/ath79/Makefile | 10 -- - arch/mips/ath79/common.h | 2 - - arch/mips/ath79/dev-common.c | 159 ------------------------ - arch/mips/ath79/dev-common.h | 18 --- - arch/mips/ath79/dev-gpio-buttons.c | 56 --------- - arch/mips/ath79/dev-gpio-buttons.h | 23 ---- - arch/mips/ath79/dev-leds-gpio.c | 54 --------- - arch/mips/ath79/dev-leds-gpio.h | 21 ---- - arch/mips/ath79/dev-spi.c | 38 ------ - arch/mips/ath79/dev-spi.h | 22 ---- - arch/mips/ath79/dev-usb.c | 242 ------------------------------------- - arch/mips/ath79/dev-usb.h | 17 --- - arch/mips/ath79/dev-wmac.c | 155 ------------------------ - arch/mips/ath79/dev-wmac.h | 17 --- - arch/mips/ath79/setup.c | 1 - - 15 files changed, 835 deletions(-) - delete mode 100644 arch/mips/ath79/dev-common.c - delete mode 100644 arch/mips/ath79/dev-common.h - delete mode 100644 arch/mips/ath79/dev-gpio-buttons.c - delete mode 100644 arch/mips/ath79/dev-gpio-buttons.h - delete mode 100644 arch/mips/ath79/dev-leds-gpio.c - delete mode 100644 arch/mips/ath79/dev-leds-gpio.h - delete mode 100644 arch/mips/ath79/dev-spi.c - delete mode 100644 arch/mips/ath79/dev-spi.h - delete mode 100644 arch/mips/ath79/dev-usb.c - delete mode 100644 arch/mips/ath79/dev-usb.h - delete mode 100644 arch/mips/ath79/dev-wmac.c - delete mode 100644 arch/mips/ath79/dev-wmac.h - ---- a/arch/mips/ath79/Makefile -+++ b/arch/mips/ath79/Makefile -@@ -11,13 +11,3 @@ - obj-y := prom.o setup.o common.o clock.o - - obj-$(CONFIG_EARLY_PRINTK) += early_printk.o -- --# --# Devices --# --obj-y += dev-common.o --obj-$(CONFIG_ATH79_DEV_GPIO_BUTTONS) += dev-gpio-buttons.o --obj-$(CONFIG_ATH79_DEV_LEDS_GPIO) += dev-leds-gpio.o --obj-$(CONFIG_ATH79_DEV_SPI) += dev-spi.o --obj-$(CONFIG_ATH79_DEV_USB) += dev-usb.o --obj-$(CONFIG_ATH79_DEV_WMAC) += dev-wmac.o ---- a/arch/mips/ath79/common.h -+++ b/arch/mips/ath79/common.h -@@ -24,6 +24,4 @@ unsigned long ath79_get_sys_clk_rate(con - - void ath79_ddr_ctrl_init(void); - --void ath79_gpio_init(void); -- - #endif /* __ATH79_COMMON_H */ ---- a/arch/mips/ath79/dev-common.c -+++ /dev/null -@@ -1,159 +0,0 @@ --/* -- * Atheros AR71XX/AR724X/AR913X common devices -- * -- * Copyright (C) 2008-2011 Gabor Juhos -- * Copyright (C) 2008 Imre Kaloz -- * -- * Parts of this file are based on Atheros' 2.6.15 BSP -- * -- * This program is free software; you can redistribute it and/or modify it -- * under the terms of the GNU General Public License version 2 as published -- * by the Free Software Foundation. -- */ -- --#include --#include --#include --#include --#include --#include --#include -- --#include --#include --#include "common.h" --#include "dev-common.h" -- --static struct resource ath79_uart_resources[] = { -- { -- .start = AR71XX_UART_BASE, -- .end = AR71XX_UART_BASE + AR71XX_UART_SIZE - 1, -- .flags = IORESOURCE_MEM, -- }, --}; -- --#define AR71XX_UART_FLAGS (UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP) --static struct plat_serial8250_port ath79_uart_data[] = { -- { -- .mapbase = AR71XX_UART_BASE, -- .irq = ATH79_MISC_IRQ(3), -- .flags = AR71XX_UART_FLAGS, -- .iotype = UPIO_MEM32, -- .regshift = 2, -- }, { -- /* terminating entry */ -- } --}; -- --static struct platform_device ath79_uart_device = { -- .name = "serial8250", -- .id = PLAT8250_DEV_PLATFORM, -- .resource = ath79_uart_resources, -- .num_resources = ARRAY_SIZE(ath79_uart_resources), -- .dev = { -- .platform_data = ath79_uart_data -- }, --}; -- --static struct resource ar933x_uart_resources[] = { -- { -- .start = AR933X_UART_BASE, -- .end = AR933X_UART_BASE + AR71XX_UART_SIZE - 1, -- .flags = IORESOURCE_MEM, -- }, -- { -- .start = ATH79_MISC_IRQ(3), -- .end = ATH79_MISC_IRQ(3), -- .flags = IORESOURCE_IRQ, -- }, --}; -- --static struct platform_device ar933x_uart_device = { -- .name = "ar933x-uart", -- .id = -1, -- .resource = ar933x_uart_resources, -- .num_resources = ARRAY_SIZE(ar933x_uart_resources), --}; -- --void __init ath79_register_uart(void) --{ -- unsigned long uart_clk_rate; -- -- uart_clk_rate = ath79_get_sys_clk_rate("uart"); -- -- if (soc_is_ar71xx() || -- soc_is_ar724x() || -- soc_is_ar913x() || -- soc_is_ar934x() || -- soc_is_qca955x()) { -- ath79_uart_data[0].uartclk = uart_clk_rate; -- platform_device_register(&ath79_uart_device); -- } else if (soc_is_ar933x()) { -- platform_device_register(&ar933x_uart_device); -- } else { -- BUG(); -- } --} -- --void __init ath79_register_wdt(void) --{ -- struct resource res; -- -- memset(&res, 0, sizeof(res)); -- -- res.flags = IORESOURCE_MEM; -- res.start = AR71XX_RESET_BASE + AR71XX_RESET_REG_WDOG_CTRL; -- res.end = res.start + 0x8 - 1; -- -- platform_device_register_simple("ath79-wdt", -1, &res, 1); --} -- --static struct ath79_gpio_platform_data ath79_gpio_pdata; -- --static struct resource ath79_gpio_resources[] = { -- { -- .flags = IORESOURCE_MEM, -- .start = AR71XX_GPIO_BASE, -- .end = AR71XX_GPIO_BASE + AR71XX_GPIO_SIZE - 1, -- }, -- { -- .start = ATH79_MISC_IRQ(2), -- .end = ATH79_MISC_IRQ(2), -- .flags = IORESOURCE_IRQ, -- }, --}; -- --static struct platform_device ath79_gpio_device = { -- .name = "ath79-gpio", -- .id = -1, -- .resource = ath79_gpio_resources, -- .num_resources = ARRAY_SIZE(ath79_gpio_resources), -- .dev = { -- .platform_data = &ath79_gpio_pdata -- }, --}; -- --void __init ath79_gpio_init(void) --{ -- if (soc_is_ar71xx()) { -- ath79_gpio_pdata.ngpios = AR71XX_GPIO_COUNT; -- } else if (soc_is_ar7240()) { -- ath79_gpio_pdata.ngpios = AR7240_GPIO_COUNT; -- } else if (soc_is_ar7241() || soc_is_ar7242()) { -- ath79_gpio_pdata.ngpios = AR7241_GPIO_COUNT; -- } else if (soc_is_ar913x()) { -- ath79_gpio_pdata.ngpios = AR913X_GPIO_COUNT; -- } else if (soc_is_ar933x()) { -- ath79_gpio_pdata.ngpios = AR933X_GPIO_COUNT; -- } else if (soc_is_ar934x()) { -- ath79_gpio_pdata.ngpios = AR934X_GPIO_COUNT; -- ath79_gpio_pdata.oe_inverted = 1; -- } else if (soc_is_qca955x()) { -- ath79_gpio_pdata.ngpios = QCA955X_GPIO_COUNT; -- ath79_gpio_pdata.oe_inverted = 1; -- } else { -- BUG(); -- } -- -- platform_device_register(&ath79_gpio_device); --} ---- a/arch/mips/ath79/dev-common.h -+++ /dev/null -@@ -1,18 +0,0 @@ --/* -- * Atheros AR71XX/AR724X/AR913X common devices -- * -- * Copyright (C) 2008-2010 Gabor Juhos -- * Copyright (C) 2008 Imre Kaloz -- * -- * This program is free software; you can redistribute it and/or modify it -- * under the terms of the GNU General Public License version 2 as published -- * by the Free Software Foundation. -- */ -- --#ifndef _ATH79_DEV_COMMON_H --#define _ATH79_DEV_COMMON_H -- --void ath79_register_uart(void); --void ath79_register_wdt(void); -- --#endif /* _ATH79_DEV_COMMON_H */ ---- a/arch/mips/ath79/dev-gpio-buttons.c -+++ /dev/null -@@ -1,56 +0,0 @@ --/* -- * Atheros AR71XX/AR724X/AR913X GPIO button support -- * -- * Copyright (C) 2008-2010 Gabor Juhos -- * Copyright (C) 2008 Imre Kaloz -- * -- * This program is free software; you can redistribute it and/or modify it -- * under the terms of the GNU General Public License version 2 as published -- * by the Free Software Foundation. -- */ -- --#include "linux/init.h" --#include "linux/slab.h" --#include -- --#include "dev-gpio-buttons.h" -- --void __init ath79_register_gpio_keys_polled(int id, -- unsigned poll_interval, -- unsigned nbuttons, -- struct gpio_keys_button *buttons) --{ -- struct platform_device *pdev; -- struct gpio_keys_platform_data pdata; -- struct gpio_keys_button *p; -- int err; -- -- p = kmemdup(buttons, nbuttons * sizeof(*p), GFP_KERNEL); -- if (!p) -- return; -- -- pdev = platform_device_alloc("gpio-keys-polled", id); -- if (!pdev) -- goto err_free_buttons; -- -- memset(&pdata, 0, sizeof(pdata)); -- pdata.poll_interval = poll_interval; -- pdata.nbuttons = nbuttons; -- pdata.buttons = p; -- -- err = platform_device_add_data(pdev, &pdata, sizeof(pdata)); -- if (err) -- goto err_put_pdev; -- -- err = platform_device_add(pdev); -- if (err) -- goto err_put_pdev; -- -- return; -- --err_put_pdev: -- platform_device_put(pdev); -- --err_free_buttons: -- kfree(p); --} ---- a/arch/mips/ath79/dev-gpio-buttons.h -+++ /dev/null -@@ -1,23 +0,0 @@ --/* -- * Atheros AR71XX/AR724X/AR913X GPIO button support -- * -- * Copyright (C) 2008-2010 Gabor Juhos -- * Copyright (C) 2008 Imre Kaloz -- * -- * This program is free software; you can redistribute it and/or modify it -- * under the terms of the GNU General Public License version 2 as published -- * by the Free Software Foundation. -- */ -- --#ifndef _ATH79_DEV_GPIO_BUTTONS_H --#define _ATH79_DEV_GPIO_BUTTONS_H -- --#include --#include -- --void ath79_register_gpio_keys_polled(int id, -- unsigned poll_interval, -- unsigned nbuttons, -- struct gpio_keys_button *buttons); -- --#endif /* _ATH79_DEV_GPIO_BUTTONS_H */ ---- a/arch/mips/ath79/dev-leds-gpio.c -+++ /dev/null -@@ -1,54 +0,0 @@ --/* -- * Atheros AR71XX/AR724X/AR913X common GPIO LEDs support -- * -- * Copyright (C) 2008-2010 Gabor Juhos -- * Copyright (C) 2008 Imre Kaloz -- * -- * This program is free software; you can redistribute it and/or modify it -- * under the terms of the GNU General Public License version 2 as published -- * by the Free Software Foundation. -- */ -- --#include --#include --#include -- --#include "dev-leds-gpio.h" -- --void __init ath79_register_leds_gpio(int id, -- unsigned num_leds, -- struct gpio_led *leds) --{ -- struct platform_device *pdev; -- struct gpio_led_platform_data pdata; -- struct gpio_led *p; -- int err; -- -- p = kmemdup(leds, num_leds * sizeof(*p), GFP_KERNEL); -- if (!p) -- return; -- -- pdev = platform_device_alloc("leds-gpio", id); -- if (!pdev) -- goto err_free_leds; -- -- memset(&pdata, 0, sizeof(pdata)); -- pdata.num_leds = num_leds; -- pdata.leds = p; -- -- err = platform_device_add_data(pdev, &pdata, sizeof(pdata)); -- if (err) -- goto err_put_pdev; -- -- err = platform_device_add(pdev); -- if (err) -- goto err_put_pdev; -- -- return; -- --err_put_pdev: -- platform_device_put(pdev); -- --err_free_leds: -- kfree(p); --} ---- a/arch/mips/ath79/dev-leds-gpio.h -+++ /dev/null -@@ -1,21 +0,0 @@ --/* -- * Atheros AR71XX/AR724X/AR913X common GPIO LEDs support -- * -- * Copyright (C) 2008-2010 Gabor Juhos -- * Copyright (C) 2008 Imre Kaloz -- * -- * This program is free software; you can redistribute it and/or modify it -- * under the terms of the GNU General Public License version 2 as published -- * by the Free Software Foundation. -- */ -- --#ifndef _ATH79_DEV_LEDS_GPIO_H --#define _ATH79_DEV_LEDS_GPIO_H -- --#include -- --void ath79_register_leds_gpio(int id, -- unsigned num_leds, -- struct gpio_led *leds); -- --#endif /* _ATH79_DEV_LEDS_GPIO_H */ ---- a/arch/mips/ath79/dev-spi.c -+++ /dev/null -@@ -1,38 +0,0 @@ --/* -- * Atheros AR71XX/AR724X/AR913X SPI controller device -- * -- * Copyright (C) 2008-2010 Gabor Juhos -- * Copyright (C) 2008 Imre Kaloz -- * -- * This program is free software; you can redistribute it and/or modify it -- * under the terms of the GNU General Public License version 2 as published -- * by the Free Software Foundation. -- */ -- --#include --#include --#include "dev-spi.h" -- --static struct resource ath79_spi_resources[] = { -- { -- .start = AR71XX_SPI_BASE, -- .end = AR71XX_SPI_BASE + AR71XX_SPI_SIZE - 1, -- .flags = IORESOURCE_MEM, -- }, --}; -- --static struct platform_device ath79_spi_device = { -- .name = "ath79-spi", -- .id = -1, -- .resource = ath79_spi_resources, -- .num_resources = ARRAY_SIZE(ath79_spi_resources), --}; -- --void __init ath79_register_spi(struct ath79_spi_platform_data *pdata, -- struct spi_board_info const *info, -- unsigned n) --{ -- spi_register_board_info(info, n); -- ath79_spi_device.dev.platform_data = pdata; -- platform_device_register(&ath79_spi_device); --} ---- a/arch/mips/ath79/dev-spi.h -+++ /dev/null -@@ -1,22 +0,0 @@ --/* -- * Atheros AR71XX/AR724X/AR913X SPI controller device -- * -- * Copyright (C) 2008-2010 Gabor Juhos -- * Copyright (C) 2008 Imre Kaloz -- * -- * This program is free software; you can redistribute it and/or modify it -- * under the terms of the GNU General Public License version 2 as published -- * by the Free Software Foundation. -- */ -- --#ifndef _ATH79_DEV_SPI_H --#define _ATH79_DEV_SPI_H -- --#include --#include -- --void ath79_register_spi(struct ath79_spi_platform_data *pdata, -- struct spi_board_info const *info, -- unsigned n); -- --#endif /* _ATH79_DEV_SPI_H */ ---- a/arch/mips/ath79/dev-usb.c -+++ /dev/null -@@ -1,242 +0,0 @@ --/* -- * Atheros AR7XXX/AR9XXX USB Host Controller device -- * -- * Copyright (C) 2008-2011 Gabor Juhos -- * Copyright (C) 2008 Imre Kaloz -- * -- * Parts of this file are based on Atheros' 2.6.15 BSP -- * -- * This program is free software; you can redistribute it and/or modify it -- * under the terms of the GNU General Public License version 2 as published -- * by the Free Software Foundation. -- */ -- --#include --#include --#include --#include --#include --#include --#include --#include -- --#include --#include --#include "common.h" --#include "dev-usb.h" -- --static u64 ath79_usb_dmamask = DMA_BIT_MASK(32); -- --static struct usb_ohci_pdata ath79_ohci_pdata = { --}; -- --static struct usb_ehci_pdata ath79_ehci_pdata_v1 = { -- .has_synopsys_hc_bug = 1, --}; -- --static struct usb_ehci_pdata ath79_ehci_pdata_v2 = { -- .caps_offset = 0x100, -- .has_tt = 1, --}; -- --static void __init ath79_usb_register(const char *name, int id, -- unsigned long base, unsigned long size, -- int irq, const void *data, -- size_t data_size) --{ -- struct resource res[2]; -- struct platform_device *pdev; -- -- memset(res, 0, sizeof(res)); -- -- res[0].flags = IORESOURCE_MEM; -- res[0].start = base; -- res[0].end = base + size - 1; -- -- res[1].flags = IORESOURCE_IRQ; -- res[1].start = irq; -- res[1].end = irq; -- -- pdev = platform_device_register_resndata(NULL, name, id, -- res, ARRAY_SIZE(res), -- data, data_size); -- -- if (IS_ERR(pdev)) { -- pr_err("ath79: unable to register USB at %08lx, err=%d\n", -- base, (int) PTR_ERR(pdev)); -- return; -- } -- -- pdev->dev.dma_mask = &ath79_usb_dmamask; -- pdev->dev.coherent_dma_mask = DMA_BIT_MASK(32); --} -- --#define AR71XX_USB_RESET_MASK (AR71XX_RESET_USB_HOST | \ -- AR71XX_RESET_USB_PHY | \ -- AR71XX_RESET_USB_OHCI_DLL) -- --static void __init ath79_usb_setup(void) --{ -- void __iomem *usb_ctrl_base; -- -- ath79_device_reset_set(AR71XX_USB_RESET_MASK); -- mdelay(1000); -- ath79_device_reset_clear(AR71XX_USB_RESET_MASK); -- -- usb_ctrl_base = ioremap(AR71XX_USB_CTRL_BASE, AR71XX_USB_CTRL_SIZE); -- -- /* Turning on the Buff and Desc swap bits */ -- __raw_writel(0xf0000, usb_ctrl_base + AR71XX_USB_CTRL_REG_CONFIG); -- -- /* WAR for HW bug. Here it adjusts the duration between two SOFS */ -- __raw_writel(0x20c00, usb_ctrl_base + AR71XX_USB_CTRL_REG_FLADJ); -- -- iounmap(usb_ctrl_base); -- -- mdelay(900); -- -- ath79_usb_register("ohci-platform", -1, -- AR71XX_OHCI_BASE, AR71XX_OHCI_SIZE, -- ATH79_MISC_IRQ(6), -- &ath79_ohci_pdata, sizeof(ath79_ohci_pdata)); -- -- ath79_usb_register("ehci-platform", -1, -- AR71XX_EHCI_BASE, AR71XX_EHCI_SIZE, -- ATH79_CPU_IRQ(3), -- &ath79_ehci_pdata_v1, sizeof(ath79_ehci_pdata_v1)); --} -- --static void __init ar7240_usb_setup(void) --{ -- void __iomem *usb_ctrl_base; -- -- ath79_device_reset_clear(AR7240_RESET_OHCI_DLL); -- ath79_device_reset_set(AR7240_RESET_USB_HOST); -- -- mdelay(1000); -- -- ath79_device_reset_set(AR7240_RESET_OHCI_DLL); -- ath79_device_reset_clear(AR7240_RESET_USB_HOST); -- -- usb_ctrl_base = ioremap(AR7240_USB_CTRL_BASE, AR7240_USB_CTRL_SIZE); -- -- /* WAR for HW bug. Here it adjusts the duration between two SOFS */ -- __raw_writel(0x3, usb_ctrl_base + AR71XX_USB_CTRL_REG_FLADJ); -- -- iounmap(usb_ctrl_base); -- -- ath79_usb_register("ohci-platform", -1, -- AR7240_OHCI_BASE, AR7240_OHCI_SIZE, -- ATH79_CPU_IRQ(3), -- &ath79_ohci_pdata, sizeof(ath79_ohci_pdata)); --} -- --static void __init ar724x_usb_setup(void) --{ -- ath79_device_reset_set(AR724X_RESET_USBSUS_OVERRIDE); -- mdelay(10); -- -- ath79_device_reset_clear(AR724X_RESET_USB_HOST); -- mdelay(10); -- -- ath79_device_reset_clear(AR724X_RESET_USB_PHY); -- mdelay(10); -- -- ath79_usb_register("ehci-platform", -1, -- AR724X_EHCI_BASE, AR724X_EHCI_SIZE, -- ATH79_CPU_IRQ(3), -- &ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2)); --} -- --static void __init ar913x_usb_setup(void) --{ -- ath79_device_reset_set(AR913X_RESET_USBSUS_OVERRIDE); -- mdelay(10); -- -- ath79_device_reset_clear(AR913X_RESET_USB_HOST); -- mdelay(10); -- -- ath79_device_reset_clear(AR913X_RESET_USB_PHY); -- mdelay(10); -- -- ath79_usb_register("ehci-platform", -1, -- AR913X_EHCI_BASE, AR913X_EHCI_SIZE, -- ATH79_CPU_IRQ(3), -- &ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2)); --} -- --static void __init ar933x_usb_setup(void) --{ -- ath79_device_reset_set(AR933X_RESET_USBSUS_OVERRIDE); -- mdelay(10); -- -- ath79_device_reset_clear(AR933X_RESET_USB_HOST); -- mdelay(10); -- -- ath79_device_reset_clear(AR933X_RESET_USB_PHY); -- mdelay(10); -- -- ath79_usb_register("ehci-platform", -1, -- AR933X_EHCI_BASE, AR933X_EHCI_SIZE, -- ATH79_CPU_IRQ(3), -- &ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2)); --} -- --static void __init ar934x_usb_setup(void) --{ -- u32 bootstrap; -- -- bootstrap = ath79_reset_rr(AR934X_RESET_REG_BOOTSTRAP); -- if (bootstrap & AR934X_BOOTSTRAP_USB_MODE_DEVICE) -- return; -- -- ath79_device_reset_set(AR934X_RESET_USBSUS_OVERRIDE); -- udelay(1000); -- -- ath79_device_reset_clear(AR934X_RESET_USB_PHY); -- udelay(1000); -- -- ath79_device_reset_clear(AR934X_RESET_USB_PHY_ANALOG); -- udelay(1000); -- -- ath79_device_reset_clear(AR934X_RESET_USB_HOST); -- udelay(1000); -- -- ath79_usb_register("ehci-platform", -1, -- AR934X_EHCI_BASE, AR934X_EHCI_SIZE, -- ATH79_CPU_IRQ(3), -- &ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2)); --} -- --static void __init qca955x_usb_setup(void) --{ -- ath79_usb_register("ehci-platform", 0, -- QCA955X_EHCI0_BASE, QCA955X_EHCI_SIZE, -- ATH79_IP3_IRQ(0), -- &ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2)); -- -- ath79_usb_register("ehci-platform", 1, -- QCA955X_EHCI1_BASE, QCA955X_EHCI_SIZE, -- ATH79_IP3_IRQ(1), -- &ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2)); --} -- --void __init ath79_register_usb(void) --{ -- if (soc_is_ar71xx()) -- ath79_usb_setup(); -- else if (soc_is_ar7240()) -- ar7240_usb_setup(); -- else if (soc_is_ar7241() || soc_is_ar7242()) -- ar724x_usb_setup(); -- else if (soc_is_ar913x()) -- ar913x_usb_setup(); -- else if (soc_is_ar933x()) -- ar933x_usb_setup(); -- else if (soc_is_ar934x()) -- ar934x_usb_setup(); -- else if (soc_is_qca955x()) -- qca955x_usb_setup(); -- else -- BUG(); --} ---- a/arch/mips/ath79/dev-usb.h -+++ /dev/null -@@ -1,17 +0,0 @@ --/* -- * Atheros AR71XX/AR724X/AR913X USB Host Controller support -- * -- * Copyright (C) 2008-2010 Gabor Juhos -- * Copyright (C) 2008 Imre Kaloz -- * -- * This program is free software; you can redistribute it and/or modify it -- * under the terms of the GNU General Public License version 2 as published -- * by the Free Software Foundation. -- */ -- --#ifndef _ATH79_DEV_USB_H --#define _ATH79_DEV_USB_H -- --void ath79_register_usb(void); -- --#endif /* _ATH79_DEV_USB_H */ ---- a/arch/mips/ath79/dev-wmac.c -+++ /dev/null -@@ -1,155 +0,0 @@ --/* -- * Atheros AR913X/AR933X SoC built-in WMAC device support -- * -- * Copyright (C) 2010-2011 Jaiganesh Narayanan -- * Copyright (C) 2008-2011 Gabor Juhos -- * Copyright (C) 2008 Imre Kaloz -- * -- * Parts of this file are based on Atheros 2.6.15/2.6.31 BSP -- * -- * This program is free software; you can redistribute it and/or modify it -- * under the terms of the GNU General Public License version 2 as published -- * by the Free Software Foundation. -- */ -- --#include --#include --#include --#include --#include -- --#include --#include --#include "dev-wmac.h" -- --static struct ath9k_platform_data ath79_wmac_data; -- --static struct resource ath79_wmac_resources[] = { -- { -- /* .start and .end fields are filled dynamically */ -- .flags = IORESOURCE_MEM, -- }, { -- /* .start and .end fields are filled dynamically */ -- .flags = IORESOURCE_IRQ, -- }, --}; -- --static struct platform_device ath79_wmac_device = { -- .name = "ath9k", -- .id = -1, -- .resource = ath79_wmac_resources, -- .num_resources = ARRAY_SIZE(ath79_wmac_resources), -- .dev = { -- .platform_data = &ath79_wmac_data, -- }, --}; -- --static void __init ar913x_wmac_setup(void) --{ -- /* reset the WMAC */ -- ath79_device_reset_set(AR913X_RESET_AMBA2WMAC); -- mdelay(10); -- -- ath79_device_reset_clear(AR913X_RESET_AMBA2WMAC); -- mdelay(10); -- -- ath79_wmac_resources[0].start = AR913X_WMAC_BASE; -- ath79_wmac_resources[0].end = AR913X_WMAC_BASE + AR913X_WMAC_SIZE - 1; -- ath79_wmac_resources[1].start = ATH79_CPU_IRQ(2); -- ath79_wmac_resources[1].end = ATH79_CPU_IRQ(2); --} -- -- --static int ar933x_wmac_reset(void) --{ -- ath79_device_reset_set(AR933X_RESET_WMAC); -- ath79_device_reset_clear(AR933X_RESET_WMAC); -- -- return 0; --} -- --static int ar933x_r1_get_wmac_revision(void) --{ -- return ath79_soc_rev; --} -- --static void __init ar933x_wmac_setup(void) --{ -- u32 t; -- -- ar933x_wmac_reset(); -- -- ath79_wmac_device.name = "ar933x_wmac"; -- -- ath79_wmac_resources[0].start = AR933X_WMAC_BASE; -- ath79_wmac_resources[0].end = AR933X_WMAC_BASE + AR933X_WMAC_SIZE - 1; -- ath79_wmac_resources[1].start = ATH79_CPU_IRQ(2); -- ath79_wmac_resources[1].end = ATH79_CPU_IRQ(2); -- -- t = ath79_reset_rr(AR933X_RESET_REG_BOOTSTRAP); -- if (t & AR933X_BOOTSTRAP_REF_CLK_40) -- ath79_wmac_data.is_clk_25mhz = false; -- else -- ath79_wmac_data.is_clk_25mhz = true; -- -- if (ath79_soc_rev == 1) -- ath79_wmac_data.get_mac_revision = ar933x_r1_get_wmac_revision; -- -- ath79_wmac_data.external_reset = ar933x_wmac_reset; --} -- --static void ar934x_wmac_setup(void) --{ -- u32 t; -- -- ath79_wmac_device.name = "ar934x_wmac"; -- -- ath79_wmac_resources[0].start = AR934X_WMAC_BASE; -- ath79_wmac_resources[0].end = AR934X_WMAC_BASE + AR934X_WMAC_SIZE - 1; -- ath79_wmac_resources[1].start = ATH79_IP2_IRQ(1); -- ath79_wmac_resources[1].end = ATH79_IP2_IRQ(1); -- -- t = ath79_reset_rr(AR934X_RESET_REG_BOOTSTRAP); -- if (t & AR934X_BOOTSTRAP_REF_CLK_40) -- ath79_wmac_data.is_clk_25mhz = false; -- else -- ath79_wmac_data.is_clk_25mhz = true; --} -- --static void qca955x_wmac_setup(void) --{ -- u32 t; -- -- ath79_wmac_device.name = "qca955x_wmac"; -- -- ath79_wmac_resources[0].start = QCA955X_WMAC_BASE; -- ath79_wmac_resources[0].end = QCA955X_WMAC_BASE + QCA955X_WMAC_SIZE - 1; -- ath79_wmac_resources[1].start = ATH79_IP2_IRQ(1); -- ath79_wmac_resources[1].end = ATH79_IP2_IRQ(1); -- -- t = ath79_reset_rr(QCA955X_RESET_REG_BOOTSTRAP); -- if (t & QCA955X_BOOTSTRAP_REF_CLK_40) -- ath79_wmac_data.is_clk_25mhz = false; -- else -- ath79_wmac_data.is_clk_25mhz = true; --} -- --void __init ath79_register_wmac(u8 *cal_data) --{ -- if (soc_is_ar913x()) -- ar913x_wmac_setup(); -- else if (soc_is_ar933x()) -- ar933x_wmac_setup(); -- else if (soc_is_ar934x()) -- ar934x_wmac_setup(); -- else if (soc_is_qca955x()) -- qca955x_wmac_setup(); -- else -- BUG(); -- -- if (cal_data) -- memcpy(ath79_wmac_data.eeprom_data, cal_data, -- sizeof(ath79_wmac_data.eeprom_data)); -- -- platform_device_register(&ath79_wmac_device); --} ---- a/arch/mips/ath79/dev-wmac.h -+++ /dev/null -@@ -1,17 +0,0 @@ --/* -- * Atheros AR913X/AR933X SoC built-in WMAC device support -- * -- * Copyright (C) 2008-2011 Gabor Juhos -- * Copyright (C) 2008 Imre Kaloz -- * -- * This program is free software; you can redistribute it and/or modify it -- * under the terms of the GNU General Public License version 2 as published -- * by the Free Software Foundation. -- */ -- --#ifndef _ATH79_DEV_WMAC_H --#define _ATH79_DEV_WMAC_H -- --void ath79_register_wmac(u8 *cal_data); -- --#endif /* _ATH79_DEV_WMAC_H */ ---- a/arch/mips/ath79/setup.c -+++ b/arch/mips/ath79/setup.c -@@ -32,7 +32,6 @@ - #include - #include - #include "common.h" --#include "dev-common.h" - - #define ATH79_SYS_TYPE_LEN 64 - diff --git a/target/linux/ath79/patches-4.14/0031-MIPS-ath79-drop-OF-clock-code.patch b/target/linux/ath79/patches-4.14/0031-MIPS-ath79-drop-OF-clock-code.patch deleted file mode 100644 index a11be73d7a80..000000000000 --- a/target/linux/ath79/patches-4.14/0031-MIPS-ath79-drop-OF-clock-code.patch +++ /dev/null @@ -1,95 +0,0 @@ -From 00e4313da4609074fff134e61dd9ffe3fd37474d Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Sun, 24 Jun 2018 09:39:41 +0200 -Subject: [PATCH 31/33] MIPS: ath79: drop !OF clock code - -With the target now being fully OF based, we can drop the legacy clock -registration code. All clocks are now probed via devicetree. - -Signed-off-by: John Crispin ---- - arch/mips/ath79/clock.c | 56 ------------------------------------------------ - arch/mips/ath79/common.h | 3 --- - 2 files changed, 59 deletions(-) - ---- a/arch/mips/ath79/clock.c -+++ b/arch/mips/ath79/clock.c -@@ -617,60 +617,6 @@ static void __init qca956x_clocks_init(v - ath79_set_clk(ATH79_CLK_AHB, ahb_rate); - } - --void __init ath79_clocks_init(void) --{ -- const char *wdt; -- const char *uart; -- -- if (soc_is_ar71xx()) -- ar71xx_clocks_init(ath79_pll_base); -- else if (soc_is_ar724x() || soc_is_ar913x()) -- ar724x_clocks_init(ath79_pll_base); -- else if (soc_is_ar933x()) -- ar933x_clocks_init(ath79_pll_base); -- else if (soc_is_ar934x()) -- ar934x_clocks_init(ath79_pll_base); -- else if (soc_is_qca953x()) -- qca953x_clocks_init(ath79_pll_base); -- else if (soc_is_qca955x()) -- qca955x_clocks_init(ath79_pll_base); -- else if (soc_is_qca956x() || soc_is_tp9343()) -- qca956x_clocks_init(ath79_pll_base); -- else -- BUG(); -- -- if (soc_is_ar71xx() || soc_is_ar724x() || soc_is_ar913x()) { -- wdt = "ahb"; -- uart = "ahb"; -- } else if (soc_is_ar933x()) { -- wdt = "ahb"; -- uart = "ref"; -- } else { -- wdt = "ref"; -- uart = "ref"; -- } -- -- clk_add_alias("wdt", NULL, wdt, NULL); -- clk_add_alias("uart", NULL, uart, NULL); --} -- --unsigned long __init --ath79_get_sys_clk_rate(const char *id) --{ -- struct clk *clk; -- unsigned long rate; -- -- clk = clk_get(NULL, id); -- if (IS_ERR(clk)) -- panic("unable to get %s clock, err=%d", id, (int) PTR_ERR(clk)); -- -- rate = clk_get_rate(clk); -- clk_put(clk); -- -- return rate; --} -- --#ifdef CONFIG_OF - static void __init ath79_clocks_init_dt(struct device_node *np) - { - struct clk *ref_clk; -@@ -727,5 +673,3 @@ CLK_OF_DECLARE(ar9340_clk, "qca,ar9340-p - CLK_OF_DECLARE(ar9530_clk, "qca,qca9530-pll", ath79_clocks_init_dt); - CLK_OF_DECLARE(ar9550_clk, "qca,qca9550-pll", ath79_clocks_init_dt); - CLK_OF_DECLARE(ar9560_clk, "qca,qca9560-pll", ath79_clocks_init_dt); -- --#endif ---- a/arch/mips/ath79/common.h -+++ b/arch/mips/ath79/common.h -@@ -19,9 +19,6 @@ - #define ATH79_MEM_SIZE_MIN (2 * 1024 * 1024) - #define ATH79_MEM_SIZE_MAX (256 * 1024 * 1024) - --void ath79_clocks_init(void); --unsigned long ath79_get_sys_clk_rate(const char *id); -- - void ath79_ddr_ctrl_init(void); - - #endif /* __ATH79_COMMON_H */ diff --git a/target/linux/ath79/patches-4.14/0032-MIPS-ath79-sanitize-symbols.patch b/target/linux/ath79/patches-4.14/0032-MIPS-ath79-sanitize-symbols.patch deleted file mode 100644 index eaefc0bd214f..000000000000 --- a/target/linux/ath79/patches-4.14/0032-MIPS-ath79-sanitize-symbols.patch +++ /dev/null @@ -1,93 +0,0 @@ -From 3fc8585cf76022dba7496627074d42af88c30718 Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Sat, 23 Jun 2018 15:16:55 +0200 -Subject: [PATCH 32/33] MIPS: ath79: sanitize symbols - -We no longer need to select which SoCs are supported as the whole arch -code is always built. So lets drop all the SoC symbols - -Signed-off-by: John Crispin ---- - arch/mips/Kconfig | 2 ++ - arch/mips/ath79/Kconfig | 44 +++++--------------------------------------- - arch/mips/pci/Makefile | 2 +- - 3 files changed, 8 insertions(+), 40 deletions(-) - ---- a/arch/mips/Kconfig -+++ b/arch/mips/Kconfig -@@ -203,6 +203,8 @@ config ATH79 - select SYS_SUPPORTS_BIG_ENDIAN - select SYS_SUPPORTS_MIPS16 - select SYS_SUPPORTS_ZBOOT_UART_PROM -+ select HW_HAS_PCI -+ select USB_ARCH_HAS_EHCI - select USE_OF - help - Support for the Atheros AR71XX/AR724X/AR913X SoCs. ---- a/arch/mips/ath79/Kconfig -+++ b/arch/mips/ath79/Kconfig -@@ -1,48 +1,14 @@ - # SPDX-License-Identifier: GPL-2.0 - if ATH79 - --config SOC_AR71XX -- select HW_HAS_PCI -- def_bool n -- --config SOC_AR724X -- select HW_HAS_PCI -- select PCI_AR724X if PCI -- def_bool n -- --config SOC_AR913X -- def_bool n -- --config SOC_AR933X -- def_bool n -- --config SOC_AR934X -- select HW_HAS_PCI -- select PCI_AR724X if PCI -- def_bool n -- --config SOC_QCA955X -- select HW_HAS_PCI -- select PCI_AR724X if PCI -+config PCI_AR71XX -+ bool "PCI support for AR7100 type SoCs" -+ depends on PCI - def_bool n - - config PCI_AR724X -- def_bool n -- --config ATH79_DEV_GPIO_BUTTONS -- def_bool n -- --config ATH79_DEV_LEDS_GPIO -- def_bool n -- --config ATH79_DEV_SPI -- def_bool n -- --config ATH79_DEV_USB -- def_bool n -- --config ATH79_DEV_WMAC -- depends on (SOC_AR913X || SOC_AR933X || SOC_AR934X || SOC_QCA955X) -+ bool "PCI support for AR724x type SoCs" -+ depends on PCI - def_bool n - - endif ---- a/arch/mips/pci/Makefile -+++ b/arch/mips/pci/Makefile -@@ -23,7 +23,7 @@ obj-$(CONFIG_BCM63XX) += pci-bcm63xx.o - ops-bcm63xx.o - obj-$(CONFIG_MIPS_ALCHEMY) += pci-alchemy.o - obj-$(CONFIG_PCI_AR2315) += pci-ar2315.o --obj-$(CONFIG_SOC_AR71XX) += pci-ar71xx.o -+obj-$(CONFIG_PCI_AR71XX) += pci-ar71xx.o - obj-$(CONFIG_PCI_AR724X) += pci-ar724x.o - obj-$(CONFIG_MIPS_PCI_VIRTIO) += pci-virtio-guest.o - # diff --git a/target/linux/ath79/patches-4.14/0033-spi-ath79-drop-pdata-support.patch b/target/linux/ath79/patches-4.14/0033-spi-ath79-drop-pdata-support.patch deleted file mode 100644 index aeb50c9b1caa..000000000000 --- a/target/linux/ath79/patches-4.14/0033-spi-ath79-drop-pdata-support.patch +++ /dev/null @@ -1,73 +0,0 @@ -From c4e197bbcecc7233aa9e553e7047fa50e4e1fe77 Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Mon, 25 Jun 2018 15:52:34 +0200 -Subject: [PATCH 33/33] spi: ath79: drop pdata support - -The target is being converted to pure OF. We can therefore drop all of the -platform data code from the driver. - -Cc: linux-spi@vger.kernel.org -Acked-by: Mark Brown -Signed-off-by: John Crispin ---- - arch/mips/include/asm/mach-ath79/ath79_spi_platform.h | 19 ------------------- - drivers/spi/spi-ath79.c | 8 -------- - 2 files changed, 27 deletions(-) - delete mode 100644 arch/mips/include/asm/mach-ath79/ath79_spi_platform.h - ---- a/arch/mips/include/asm/mach-ath79/ath79_spi_platform.h -+++ /dev/null -@@ -1,19 +0,0 @@ --/* -- * Platform data definition for Atheros AR71XX/AR724X/AR913X SPI controller -- * -- * Copyright (C) 2008-2010 Gabor Juhos -- * -- * This program is free software; you can redistribute it and/or modify it -- * under the terms of the GNU General Public License version 2 as published -- * by the Free Software Foundation. -- */ -- --#ifndef _ATH79_SPI_PLATFORM_H --#define _ATH79_SPI_PLATFORM_H -- --struct ath79_spi_platform_data { -- unsigned bus_num; -- unsigned num_chipselect; --}; -- --#endif /* _ATH79_SPI_PLATFORM_H */ ---- a/drivers/spi/spi-ath79.c -+++ b/drivers/spi/spi-ath79.c -@@ -26,7 +26,6 @@ - #include - - #include --#include - - #define DRV_NAME "ath79-spi" - -@@ -208,7 +207,6 @@ static int ath79_spi_probe(struct platfo - { - struct spi_master *master; - struct ath79_spi *sp; -- struct ath79_spi_platform_data *pdata; - struct resource *r; - unsigned long rate; - int ret; -@@ -223,15 +221,9 @@ static int ath79_spi_probe(struct platfo - master->dev.of_node = pdev->dev.of_node; - platform_set_drvdata(pdev, sp); - -- pdata = dev_get_platdata(&pdev->dev); -- - master->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 32); - master->setup = ath79_spi_setup; - master->cleanup = ath79_spi_cleanup; -- if (pdata) { -- master->bus_num = pdata->bus_num; -- master->num_chipselect = pdata->num_chipselect; -- } - - sp->bitbang.master = master; - sp->bitbang.chipselect = ath79_spi_chipselect; diff --git a/target/linux/ath79/patches-4.14/0034-MIPS-ath79-ath9k-exports.patch b/target/linux/ath79/patches-4.14/0034-MIPS-ath79-ath9k-exports.patch deleted file mode 100644 index 6eec142c7467..000000000000 --- a/target/linux/ath79/patches-4.14/0034-MIPS-ath79-ath9k-exports.patch +++ /dev/null @@ -1,27 +0,0 @@ ---- a/arch/mips/ath79/common.c -+++ b/arch/mips/ath79/common.c -@@ -34,11 +34,13 @@ EXPORT_SYMBOL_GPL(ath79_ddr_freq); - - enum ath79_soc_type ath79_soc; - unsigned int ath79_soc_rev; -+EXPORT_SYMBOL_GPL(ath79_soc_rev); - - void __iomem *ath79_pll_base; - void __iomem *ath79_reset_base; - EXPORT_SYMBOL_GPL(ath79_reset_base); --static void __iomem *ath79_ddr_base; -+void __iomem *ath79_ddr_base; -+EXPORT_SYMBOL_GPL(ath79_ddr_base); - static void __iomem *ath79_ddr_wb_flush_base; - static void __iomem *ath79_ddr_pci_win_base; - ---- a/arch/mips/include/asm/mach-ath79/ath79.h -+++ b/arch/mips/include/asm/mach-ath79/ath79.h -@@ -152,6 +152,7 @@ void ath79_ddr_wb_flush(unsigned int reg - void ath79_ddr_set_pci_windows(void); - - extern void __iomem *ath79_pll_base; -+extern void __iomem *ath79_ddr_base; - extern void __iomem *ath79_reset_base; - - static inline void ath79_pll_wr(unsigned reg, u32 val) diff --git a/target/linux/ath79/patches-4.14/0036-GPIO-add-named-gpio-exports.patch b/target/linux/ath79/patches-4.14/0036-GPIO-add-named-gpio-exports.patch deleted file mode 100644 index 61ed9ea784e7..000000000000 --- a/target/linux/ath79/patches-4.14/0036-GPIO-add-named-gpio-exports.patch +++ /dev/null @@ -1,165 +0,0 @@ -From 4267880319bc1a2270d352e0ded6d6386242a7ef Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Tue, 12 Aug 2014 20:49:27 +0200 -Subject: [PATCH 24/53] GPIO: add named gpio exports - -Signed-off-by: John Crispin ---- - drivers/gpio/gpiolib-of.c | 68 +++++++++++++++++++++++++++++++++++++++++ - drivers/gpio/gpiolib-sysfs.c | 10 +++++- - include/asm-generic/gpio.h | 6 ++++ - include/linux/gpio/consumer.h | 8 +++++ - 4 files changed, 91 insertions(+), 1 deletion(-) - ---- a/drivers/gpio/gpiolib-of.c -+++ b/drivers/gpio/gpiolib-of.c -@@ -23,6 +23,8 @@ - #include - #include - #include -+#include -+#include - - #include "gpiolib.h" - -@@ -513,3 +515,68 @@ void of_gpiochip_remove(struct gpio_chip - gpiochip_remove_pin_ranges(chip); - of_node_put(chip->of_node); - } -+ -+static struct of_device_id gpio_export_ids[] = { -+ { .compatible = "gpio-export" }, -+ { /* sentinel */ } -+}; -+ -+static int of_gpio_export_probe(struct platform_device *pdev) -+{ -+ struct device_node *np = pdev->dev.of_node; -+ struct device_node *cnp; -+ u32 val; -+ int nb = 0; -+ -+ for_each_child_of_node(np, cnp) { -+ const char *name = NULL; -+ int gpio; -+ bool dmc; -+ int max_gpio = 1; -+ int i; -+ -+ of_property_read_string(cnp, "gpio-export,name", &name); -+ -+ if (!name) -+ max_gpio = of_gpio_count(cnp); -+ -+ for (i = 0; i < max_gpio; i++) { -+ unsigned flags = 0; -+ enum of_gpio_flags of_flags; -+ -+ gpio = of_get_gpio_flags(cnp, i, &of_flags); -+ if (!gpio_is_valid(gpio)) -+ return gpio; -+ -+ if (of_flags == OF_GPIO_ACTIVE_LOW) -+ flags |= GPIOF_ACTIVE_LOW; -+ -+ if (!of_property_read_u32(cnp, "gpio-export,output", &val)) -+ flags |= val ? GPIOF_OUT_INIT_HIGH : GPIOF_OUT_INIT_LOW; -+ else -+ flags |= GPIOF_IN; -+ -+ if (devm_gpio_request_one(&pdev->dev, gpio, flags, name ? name : of_node_full_name(np))) -+ continue; -+ -+ dmc = of_property_read_bool(cnp, "gpio-export,direction_may_change"); -+ gpio_export_with_name(gpio, dmc, name); -+ nb++; -+ } -+ } -+ -+ dev_info(&pdev->dev, "%d gpio(s) exported\n", nb); -+ -+ return 0; -+} -+ -+static struct platform_driver gpio_export_driver = { -+ .driver = { -+ .name = "gpio-export", -+ .owner = THIS_MODULE, -+ .of_match_table = of_match_ptr(gpio_export_ids), -+ }, -+ .probe = of_gpio_export_probe, -+}; -+ -+module_platform_driver(gpio_export_driver); ---- a/drivers/gpio/gpiolib-sysfs.c -+++ b/drivers/gpio/gpiolib-sysfs.c -@@ -553,7 +553,7 @@ static struct class gpio_class = { - * - * Returns zero on success, else an error. - */ --int gpiod_export(struct gpio_desc *desc, bool direction_may_change) -+int __gpiod_export(struct gpio_desc *desc, bool direction_may_change, const char *name) - { - struct gpio_chip *chip; - struct gpio_device *gdev; -@@ -615,6 +615,8 @@ int gpiod_export(struct gpio_desc *desc, - offset = gpio_chip_hwgpio(desc); - if (chip->names && chip->names[offset]) - ioname = chip->names[offset]; -+ if (name) -+ ioname = name; - - dev = device_create_with_groups(&gpio_class, &gdev->dev, - MKDEV(0, 0), data, gpio_groups, -@@ -636,6 +638,12 @@ err_unlock: - gpiod_dbg(desc, "%s: status %d\n", __func__, status); - return status; - } -+EXPORT_SYMBOL_GPL(__gpiod_export); -+ -+int gpiod_export(struct gpio_desc *desc, bool direction_may_change) -+{ -+ return __gpiod_export(desc, direction_may_change, NULL); -+} - EXPORT_SYMBOL_GPL(gpiod_export); - - static int match_export(struct device *dev, const void *desc) ---- a/include/asm-generic/gpio.h -+++ b/include/asm-generic/gpio.h -@@ -127,6 +127,12 @@ static inline int gpio_export(unsigned g - return gpiod_export(gpio_to_desc(gpio), direction_may_change); - } - -+int __gpiod_export(struct gpio_desc *desc, bool direction_may_change, const char *name); -+static inline int gpio_export_with_name(unsigned gpio, bool direction_may_change, const char *name) -+{ -+ return __gpiod_export(gpio_to_desc(gpio), direction_may_change, name); -+} -+ - static inline int gpio_export_link(struct device *dev, const char *name, - unsigned gpio) - { ---- a/include/linux/gpio/consumer.h -+++ b/include/linux/gpio/consumer.h -@@ -451,6 +451,7 @@ struct gpio_desc *devm_fwnode_get_gpiod_ - - #if IS_ENABLED(CONFIG_GPIOLIB) && IS_ENABLED(CONFIG_GPIO_SYSFS) - -+int _gpiod_export(struct gpio_desc *desc, bool direction_may_change, const char *name); - int gpiod_export(struct gpio_desc *desc, bool direction_may_change); - int gpiod_export_link(struct device *dev, const char *name, - struct gpio_desc *desc); -@@ -458,6 +459,13 @@ void gpiod_unexport(struct gpio_desc *de - - #else /* CONFIG_GPIOLIB && CONFIG_GPIO_SYSFS */ - -+static inline int _gpiod_export(struct gpio_desc *desc, -+ bool direction_may_change, -+ const char *name) -+{ -+ return -ENOSYS; -+} -+ - static inline int gpiod_export(struct gpio_desc *desc, - bool direction_may_change) - { diff --git a/target/linux/ath79/patches-4.14/0036-MIPS-ath79-remove-irq-code-from-pci.patch b/target/linux/ath79/patches-4.14/0036-MIPS-ath79-remove-irq-code-from-pci.patch deleted file mode 100644 index 460c4580eede..000000000000 --- a/target/linux/ath79/patches-4.14/0036-MIPS-ath79-remove-irq-code-from-pci.patch +++ /dev/null @@ -1,139 +0,0 @@ ---- a/arch/mips/pci/pci-ar71xx.c -+++ b/arch/mips/pci/pci-ar71xx.c -@@ -54,11 +54,9 @@ - struct ar71xx_pci_controller { - struct device_node *np; - void __iomem *cfg_base; -- int irq; - struct pci_controller pci_ctrl; - struct resource io_res; - struct resource mem_res; -- struct irq_domain *domain; - }; - - /* Byte lane enable bits */ -@@ -230,104 +228,6 @@ static struct pci_ops ar71xx_pci_ops = { - .write = ar71xx_pci_write_config, - }; - --static void ar71xx_pci_irq_handler(struct irq_desc *desc) --{ -- void __iomem *base = ath79_reset_base; -- struct irq_chip *chip = irq_desc_get_chip(desc); -- struct ar71xx_pci_controller *apc = irq_desc_get_handler_data(desc); -- u32 pending; -- -- chained_irq_enter(chip, desc); -- pending = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_STATUS) & -- __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE); -- -- if (pending & AR71XX_PCI_INT_DEV0) -- generic_handle_irq(irq_linear_revmap(apc->domain, 1)); -- -- else if (pending & AR71XX_PCI_INT_DEV1) -- generic_handle_irq(irq_linear_revmap(apc->domain, 2)); -- -- else if (pending & AR71XX_PCI_INT_DEV2) -- generic_handle_irq(irq_linear_revmap(apc->domain, 3)); -- -- else if (pending & AR71XX_PCI_INT_CORE) -- generic_handle_irq(irq_linear_revmap(apc->domain, 4)); -- -- else -- spurious_interrupt(); -- chained_irq_exit(chip, desc); --} -- --static void ar71xx_pci_irq_unmask(struct irq_data *d) --{ -- struct ar71xx_pci_controller *apc; -- unsigned int irq; -- void __iomem *base = ath79_reset_base; -- u32 t; -- -- apc = irq_data_get_irq_chip_data(d); -- irq = irq_linear_revmap(apc->domain, d->irq); -- -- t = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE); -- __raw_writel(t | (1 << irq), base + AR71XX_RESET_REG_PCI_INT_ENABLE); -- -- /* flush write */ -- __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE); --} -- --static void ar71xx_pci_irq_mask(struct irq_data *d) --{ -- struct ar71xx_pci_controller *apc; -- unsigned int irq; -- void __iomem *base = ath79_reset_base; -- u32 t; -- -- apc = irq_data_get_irq_chip_data(d); -- irq = irq_linear_revmap(apc->domain, d->irq); -- -- t = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE); -- __raw_writel(t & ~(1 << irq), base + AR71XX_RESET_REG_PCI_INT_ENABLE); -- -- /* flush write */ -- __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE); --} -- --static struct irq_chip ar71xx_pci_irq_chip = { -- .name = "AR71XX PCI", -- .irq_mask = ar71xx_pci_irq_mask, -- .irq_unmask = ar71xx_pci_irq_unmask, -- .irq_mask_ack = ar71xx_pci_irq_mask, --}; -- --static int ar71xx_pci_irq_map(struct irq_domain *d, -- unsigned int irq, irq_hw_number_t hw) --{ -- struct ar71xx_pci_controller *apc = d->host_data; -- -- irq_set_chip_and_handler(irq, &ar71xx_pci_irq_chip, handle_level_irq); -- irq_set_chip_data(irq, apc); -- -- return 0; --} -- --static const struct irq_domain_ops ar71xx_pci_domain_ops = { -- .xlate = irq_domain_xlate_onecell, -- .map = ar71xx_pci_irq_map, --}; -- --static void ar71xx_pci_irq_init(struct ar71xx_pci_controller *apc) --{ -- void __iomem *base = ath79_reset_base; -- -- __raw_writel(0, base + AR71XX_RESET_REG_PCI_INT_ENABLE); -- __raw_writel(0, base + AR71XX_RESET_REG_PCI_INT_STATUS); -- -- apc->domain = irq_domain_add_linear(apc->np, AR71XX_PCI_IRQ_COUNT, -- &ar71xx_pci_domain_ops, apc); -- irq_set_chained_handler_and_data(apc->irq, ar71xx_pci_irq_handler, -- apc); --} -- - static void ar71xx_pci_reset(void) - { - ath79_device_reset_set(AR71XX_RESET_PCI_BUS | AR71XX_RESET_PCI_CORE); -@@ -361,10 +261,6 @@ static int ar71xx_pci_probe(struct platf - if (IS_ERR(apc->cfg_base)) - return PTR_ERR(apc->cfg_base); - -- apc->irq = platform_get_irq(pdev, 0); -- if (apc->irq < 0) -- return -EINVAL; -- - ar71xx_pci_reset(); - - /* setup COMMAND register */ -@@ -375,8 +271,6 @@ static int ar71xx_pci_probe(struct platf - /* clear bus errors */ - ar71xx_pci_check_error(apc, 1); - -- ar71xx_pci_irq_init(apc); -- - apc->np = pdev->dev.of_node; - apc->pci_ctrl.pci_ops = &ar71xx_pci_ops; - apc->pci_ctrl.mem_resource = &apc->mem_res; diff --git a/target/linux/ath79/patches-4.14/0037-missing-registers.patch b/target/linux/ath79/patches-4.14/0037-missing-registers.patch deleted file mode 100644 index 9fde3d39df94..000000000000 --- a/target/linux/ath79/patches-4.14/0037-missing-registers.patch +++ /dev/null @@ -1,21 +0,0 @@ -commit f3ffac90bc7266b7d917616f3233f58e8c08a196 -Author: Christian Lamparter -Date: Fri Aug 10 23:24:47 2018 +0200 - - ath79: gmac: add parsers for rxd(v)- and tx(d|en)-delay for AR9344 - - Signed-off-by: Christian Lamparter - ---- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h -+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h -@@ -1229,6 +1229,10 @@ - #define AR934X_ETH_CFG_RDV_DELAY BIT(16) - #define AR934X_ETH_CFG_RDV_DELAY_MASK 0x3 - #define AR934X_ETH_CFG_RDV_DELAY_SHIFT 16 -+#define AR934X_ETH_CFG_TXD_DELAY_MASK 0x3 -+#define AR934X_ETH_CFG_TXD_DELAY_SHIFT 18 -+#define AR934X_ETH_CFG_TXE_DELAY_MASK 0x3 -+#define AR934X_ETH_CFG_TXE_DELAY_SHIFT 20 - - /* - * QCA953X GMAC Interface diff --git a/target/linux/ath79/patches-4.14/0038-MIPS-ath79-add-missing-QCA955x-GMAC-registers.patch b/target/linux/ath79/patches-4.14/0038-MIPS-ath79-add-missing-QCA955x-GMAC-registers.patch deleted file mode 100644 index dc0af2fe9cc6..000000000000 --- a/target/linux/ath79/patches-4.14/0038-MIPS-ath79-add-missing-QCA955x-GMAC-registers.patch +++ /dev/null @@ -1,90 +0,0 @@ -From 60efe35257b063ce584968f9f80b437030ce6ba6 Mon Sep 17 00:00:00 2001 -From: David Bauer -Date: Mon, 18 Mar 2019 00:54:06 +0100 -Subject: [PATCH] MIPS: ath79: add missing QCA955x GMAC registers - -This adds missing GMAC register definitions for the Qualcomm Atheros -QCA955X series MIPS SoCs. - -They originate from the platforms U-Boot code and the AVM FRITZ!WLAN -Repeater 450E's GPL tarball. - -Signed-off-by: David Bauer ---- - .../mips/include/asm/mach-ath79/ar71xx_regs.h | 54 +++++++++++++++++++ - 1 file changed, 54 insertions(+) - ---- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h -+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h -@@ -1249,7 +1249,12 @@ - */ - - #define QCA955X_GMAC_REG_ETH_CFG 0x00 -+#define QCA955X_GMAC_REG_SGMII_RESET 0x14 - #define QCA955X_GMAC_REG_SGMII_SERDES 0x18 -+#define QCA955X_GMAC_REG_MR_AN_CONTROL 0x1c -+#define QCA955X_GMAC_REG_MR_AN_STATUS 0x20 -+#define QCA955X_GMAC_REG_SGMII_CONFIG 0x34 -+#define QCA955X_GMAC_REG_SGMII_DEBUG 0x58 - - #define QCA955X_ETH_CFG_RGMII_EN BIT(0) - #define QCA955X_ETH_CFG_MII_GE0 BIT(1) -@@ -1271,9 +1276,58 @@ - #define QCA955X_ETH_CFG_TXE_DELAY_MASK 0x3 - #define QCA955X_ETH_CFG_TXE_DELAY_SHIFT 20 - -+#define QCA955X_SGMII_RESET_RX_CLK_N_RESET 0 -+#define QCA955X_SGMII_RESET_RX_CLK_N BIT(0) -+#define QCA955X_SGMII_RESET_TX_CLK_N BIT(1) -+#define QCA955X_SGMII_RESET_RX_125M_N BIT(2) -+#define QCA955X_SGMII_RESET_TX_125M_N BIT(3) -+#define QCA955X_SGMII_RESET_HW_RX_125M_N BIT(4) -+ - #define QCA955X_SGMII_SERDES_LOCK_DETECT_STATUS BIT(15) - #define QCA955X_SGMII_SERDES_RES_CALIBRATION_SHIFT 23 - #define QCA955X_SGMII_SERDES_RES_CALIBRATION_MASK 0xf -+ -+#define QCA955X_MR_AN_CONTROL_SPEED_SEL1 BIT(6) -+#define QCA955X_MR_AN_CONTROL_DUPLEX_MODE BIT(8) -+#define QCA955X_MR_AN_CONTROL_RESTART_AN BIT(9) -+#define QCA955X_MR_AN_CONTROL_POWER_DOWN BIT(11) -+#define QCA955X_MR_AN_CONTROL_AN_ENABLE BIT(12) -+#define QCA955X_MR_AN_CONTROL_SPEED_SEL0 BIT(13) -+#define QCA955X_MR_AN_CONTROL_LOOPBACK BIT(14) -+#define QCA955X_MR_AN_CONTROL_PHY_RESET BIT(15) -+ -+#define QCA955X_MR_AN_STATUS_EXT_CAP BIT(0) -+#define QCA955X_MR_AN_STATUS_LINK_UP BIT(2) -+#define QCA955X_MR_AN_STATUS_AN_ABILITY BIT(3) -+#define QCA955X_MR_AN_STATUS_REMOTE_FAULT BIT(4) -+#define QCA955X_MR_AN_STATUS_AN_COMPLETE BIT(5) -+#define QCA955X_MR_AN_STATUS_NO_PREAMBLE BIT(6) -+#define QCA955X_MR_AN_STATUS_BASE_PAGE BIT(7) -+ -+#define QCA955X_SGMII_CONFIG_MODE_CTRL_SHIFT 0 -+#define QCA955X_SGMII_CONFIG_MODE_CTRL_MASK 0x7 -+#define QCA955X_SGMII_CONFIG_ENABLE_SGMII_TX_PAUSE BIT(3) -+#define QCA955X_SGMII_CONFIG_MR_REG4_CHANGED BIT(4) -+#define QCA955X_SGMII_CONFIG_FORCE_SPEED BIT(5) -+#define QCA955X_SGMII_CONFIG_SPEED_SHIFT 6 -+#define QCA955X_SGMII_CONFIG_SPEED_MASK 0xc0 -+#define QCA955X_SGMII_CONFIG_REMOTE_PHY_LOOPBACK BIT(8) -+#define QCA955X_SGMII_CONFIG_NEXT_PAGE_LOADED BIT(9) -+#define QCA955X_SGMII_CONFIG_MDIO_ENABLE BIT(10) -+#define QCA955X_SGMII_CONFIG_MDIO_PULSE BIT(11) -+#define QCA955X_SGMII_CONFIG_MDIO_COMPLETE BIT(12) -+#define QCA955X_SGMII_CONFIG_PRBS_ENABLE BIT(13) -+#define QCA955X_SGMII_CONFIG_BERT_ENABLE BIT(14) -+ -+#define QCA955X_SGMII_DEBUG_TX_STATE_MASK 0xff -+#define QCA955X_SGMII_DEBUG_TX_STATE_SHIFT 0 -+#define QCA955X_SGMII_DEBUG_RX_STATE_MASK 0xff00 -+#define QCA955X_SGMII_DEBUG_RX_STATE_SHIFT 8 -+#define QCA955X_SGMII_DEBUG_RX_SYNC_STATE_MASK 0xff0000 -+#define QCA955X_SGMII_DEBUG_RX_SYNC_STATE_SHIFT 16 -+#define QCA955X_SGMII_DEBUG_ARB_STATE_MASK 0xf000000 -+#define QCA955X_SGMII_DEBUG_ARB_STATE_SHIFT 24 -+ - /* - * QCA956X GMAC Interface - */ diff --git a/target/linux/ath79/patches-4.14/0038-at803x-disable-delays.patch b/target/linux/ath79/patches-4.14/0038-at803x-disable-delays.patch deleted file mode 100644 index cf05d0fc4ac2..000000000000 --- a/target/linux/ath79/patches-4.14/0038-at803x-disable-delays.patch +++ /dev/null @@ -1,27 +0,0 @@ -Until upstream commit 6d4cd041f0af("net: phy: at803x: disable delay -only for RGMII mode"), delays were not disabled on driver probe -for the Atheros AR803x PHYs, although the RX delay is enabled on -soft and hard reset. - -In addition, the TX delay setting is retained on soft-reset. - -This patch disables both delays on config init to align the behavior -with kernel 5.1 and higher. It can be safely dropped with kernel 5.1. - ---- a/drivers/net/phy/at803x.c -+++ b/drivers/net/phy/at803x.c -@@ -320,6 +320,14 @@ static int at803x_config_init(struct phy - if (ret < 0) - return ret; - -+ /* Disable RX delay */ -+ at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_0, -+ AT803X_DEBUG_RX_CLK_DLY_EN, 0); -+ -+ /* Disable TX delay */ -+ at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_5, -+ AT803X_DEBUG_TX_CLK_DLY_EN, 0); -+ - if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID || - phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) { - ret = at803x_enable_rx_delay(phydev); diff --git a/target/linux/ath79/patches-4.14/004-register_gpio_driver_earlier.patch b/target/linux/ath79/patches-4.14/004-register_gpio_driver_earlier.patch deleted file mode 100644 index cc30e2d91e28..000000000000 --- a/target/linux/ath79/patches-4.14/004-register_gpio_driver_earlier.patch +++ /dev/null @@ -1,18 +0,0 @@ -HACK: register the GPIO driver earlier to ensure that gpio_request calls -from mach files succeed. - ---- a/drivers/gpio/gpio-ath79.c -+++ b/drivers/gpio/gpio-ath79.c -@@ -322,7 +322,11 @@ static struct platform_driver ath79_gpio - .remove = ath79_gpio_remove, - }; - --module_platform_driver(ath79_gpio_driver); -+static int __init ath79_gpio_init(void) -+{ -+ return platform_driver_register(&ath79_gpio_driver); -+} -+postcore_initcall(ath79_gpio_init); - - MODULE_DESCRIPTION("Atheros AR71XX/AR724X/AR913X GPIO API support"); - MODULE_LICENSE("GPL v2"); diff --git a/target/linux/ath79/patches-4.14/404-mtd-cybertan-trx-parser.patch b/target/linux/ath79/patches-4.14/404-mtd-cybertan-trx-parser.patch deleted file mode 100644 index 3cc0b0dd49ff..000000000000 --- a/target/linux/ath79/patches-4.14/404-mtd-cybertan-trx-parser.patch +++ /dev/null @@ -1,19 +0,0 @@ ---- a/drivers/mtd/parsers/Makefile -+++ b/drivers/mtd/parsers/Makefile -@@ -1 +1,2 @@ -+obj-$(CONFIG_MTD_PARSER_CYBERTAN) += parser_cybertan.o - obj-$(CONFIG_MTD_PARSER_TRX) += parser_trx.o ---- a/drivers/mtd/parsers/Kconfig -+++ b/drivers/mtd/parsers/Kconfig -@@ -1,3 +1,11 @@ -+config MTD_PARSER_CYBERTAN -+ tristate "Parser for Cybertan format partitions" -+ depends on MTD && (ATH79 || COMPILE_TEST) -+ help -+ Cybertan has a proprietory header than encompasses a Broadcom trx -+ header. This driver will parse the header and take care of the -+ special offsets that result in the extra headers. -+ - config MTD_PARSER_TRX - tristate "Parser for TRX format partitions" - depends on MTD && (BCM47XX || ARCH_BCM_5301X || COMPILE_TEST) diff --git a/target/linux/ath79/patches-4.14/405-mtd-tp-link-partition-parser.patch b/target/linux/ath79/patches-4.14/405-mtd-tp-link-partition-parser.patch deleted file mode 100644 index 846b7f0a0ccc..000000000000 --- a/target/linux/ath79/patches-4.14/405-mtd-tp-link-partition-parser.patch +++ /dev/null @@ -1,25 +0,0 @@ ---- a/drivers/mtd/Kconfig -+++ b/drivers/mtd/Kconfig -@@ -194,6 +194,12 @@ config MTD_MYLOADER_PARTS - You will still need the parsing functions to be called by the driver - for your particular device. It won't happen automatically. - -+config MTD_TPLINK_PARTS -+ tristate "TP-Link AR7XXX/AR9XXX partitioning support" -+ depends on ATH79 -+ ---help--- -+ TBD. -+ - comment "User Modules And Translation Layers" - - # ---- a/drivers/mtd/Makefile -+++ b/drivers/mtd/Makefile -@@ -18,6 +18,7 @@ obj-$(CONFIG_MTD_BCM63XX_PARTS) += bcm63 - obj-$(CONFIG_MTD_BCM47XX_PARTS) += bcm47xxpart.o - obj-$(CONFIG_MTD_MYLOADER_PARTS) += myloader.o - obj-y += parsers/ -+obj-$(CONFIG_MTD_TPLINK_PARTS) += tplinkpart.o - - # 'Users' - code which presents functionality to userspace. - obj-$(CONFIG_MTD_BLKDEVS) += mtd_blkdevs.o diff --git a/target/linux/ath79/patches-4.14/408-mtd-redboot_partition_scan.patch b/target/linux/ath79/patches-4.14/408-mtd-redboot_partition_scan.patch deleted file mode 100644 index cd41e7ceb272..000000000000 --- a/target/linux/ath79/patches-4.14/408-mtd-redboot_partition_scan.patch +++ /dev/null @@ -1,44 +0,0 @@ ---- a/drivers/mtd/redboot.c -+++ b/drivers/mtd/redboot.c -@@ -76,12 +76,18 @@ static int parse_redboot_partitions(stru - static char nullstring[] = "unallocated"; - #endif - -+ buf = vmalloc(master->erasesize); -+ if (!buf) -+ return -ENOMEM; -+ -+ restart: - if ( directory < 0 ) { - offset = master->size + directory * master->erasesize; - while (mtd_block_isbad(master, offset)) { - if (!offset) { - nogood: - printk(KERN_NOTICE "Failed to find a non-bad block to check for RedBoot partition table\n"); -+ vfree(buf); - return -EIO; - } - offset -= master->erasesize; -@@ -94,10 +100,6 @@ static int parse_redboot_partitions(stru - goto nogood; - } - } -- buf = vmalloc(master->erasesize); -- -- if (!buf) -- return -ENOMEM; - - printk(KERN_NOTICE "Searching for RedBoot partition table in %s at offset 0x%lx\n", - master->name, offset); -@@ -170,6 +172,11 @@ static int parse_redboot_partitions(stru - } - if (i == numslots) { - /* Didn't find it */ -+ if (offset + master->erasesize < master->size) { -+ /* not at the end of the flash yet, maybe next block :) */ -+ directory++; -+ goto restart; -+ } - printk(KERN_NOTICE "No RedBoot partition table detected in %s\n", - master->name); - ret = 0; diff --git a/target/linux/ath79/patches-4.14/420-net-ar71xx_mac_driver.patch b/target/linux/ath79/patches-4.14/420-net-ar71xx_mac_driver.patch deleted file mode 100644 index 6377db0ac22b..000000000000 --- a/target/linux/ath79/patches-4.14/420-net-ar71xx_mac_driver.patch +++ /dev/null @@ -1,28 +0,0 @@ ---- a/drivers/net/ethernet/atheros/Kconfig -+++ b/drivers/net/ethernet/atheros/Kconfig -@@ -5,7 +5,7 @@ - config NET_VENDOR_ATHEROS - bool "Atheros devices" - default y -- depends on PCI -+ depends on (PCI || ATH79) - ---help--- - If you have a network (Ethernet) card belonging to this class, say Y. - -@@ -78,4 +78,6 @@ config ALX - To compile this driver as a module, choose M here. The module - will be called alx. - -+source drivers/net/ethernet/atheros/ag71xx/Kconfig -+ - endif # NET_VENDOR_ATHEROS ---- a/drivers/net/ethernet/atheros/Makefile -+++ b/drivers/net/ethernet/atheros/Makefile -@@ -3,6 +3,7 @@ - # Makefile for the Atheros network device drivers. - # - -+obj-$(CONFIG_AG71XX) += ag71xx/ - obj-$(CONFIG_ATL1) += atlx/ - obj-$(CONFIG_ATL2) += atlx/ - obj-$(CONFIG_ATL1E) += atl1e/ diff --git a/target/linux/ath79/patches-4.14/425-at803x-allow-sgmii-aneg-override.patch b/target/linux/ath79/patches-4.14/425-at803x-allow-sgmii-aneg-override.patch deleted file mode 100644 index 3b302dcd9ed3..000000000000 --- a/target/linux/ath79/patches-4.14/425-at803x-allow-sgmii-aneg-override.patch +++ /dev/null @@ -1,16 +0,0 @@ ---- a/drivers/net/phy/at803x.c -+++ b/drivers/net/phy/at803x.c -@@ -472,6 +472,13 @@ static int at803x_aneg_done(struct phy_d - if (!(phy_read(phydev, AT803X_PSSR) & AT803X_PSSR_MR_AN_COMPLETE)) { - pr_warn("803x_aneg_done: SGMII link is not ok\n"); - aneg_done = 0; -+#ifdef CONFIG_OF_MDIO -+ if (phydev->mdio.dev.of_node && -+ of_property_read_bool(phydev->mdio.dev.of_node, -+ "at803x-override-sgmii-link-check")) { -+ aneg_done = 1; -+ } -+#endif - } - /* switch back to copper page */ - phy_write(phydev, AT803X_REG_CHIP_CONFIG, ccr | AT803X_BT_BX_REG_SEL); diff --git a/target/linux/ath79/patches-4.14/430-drivers-link-spi-before-mtd.patch b/target/linux/ath79/patches-4.14/430-drivers-link-spi-before-mtd.patch deleted file mode 100644 index 2f1549710bc9..000000000000 --- a/target/linux/ath79/patches-4.14/430-drivers-link-spi-before-mtd.patch +++ /dev/null @@ -1,12 +0,0 @@ ---- a/drivers/Makefile -+++ b/drivers/Makefile -@@ -83,8 +83,8 @@ obj-$(CONFIG_SCSI) += scsi/ - obj-y += nvme/ - obj-$(CONFIG_ATA) += ata/ - obj-$(CONFIG_TARGET_CORE) += target/ --obj-$(CONFIG_MTD) += mtd/ - obj-$(CONFIG_SPI) += spi/ -+obj-$(CONFIG_MTD) += mtd/ - obj-$(CONFIG_SPMI) += spmi/ - obj-$(CONFIG_HSI) += hsi/ - obj-y += net/ diff --git a/target/linux/ath79/patches-4.14/461-spi-ath79-add-fast-flash-read.patch b/target/linux/ath79/patches-4.14/461-spi-ath79-add-fast-flash-read.patch deleted file mode 100644 index 7c24fc5e14e5..000000000000 --- a/target/linux/ath79/patches-4.14/461-spi-ath79-add-fast-flash-read.patch +++ /dev/null @@ -1,60 +0,0 @@ ---- a/drivers/spi/spi-ath79.c -+++ b/drivers/spi/spi-ath79.c -@@ -101,9 +101,6 @@ static void ath79_spi_enable(struct ath7 - /* save CTRL register */ - sp->reg_ctrl = ath79_spi_rr(sp, AR71XX_SPI_REG_CTRL); - sp->ioc_base = ath79_spi_rr(sp, AR71XX_SPI_REG_IOC); -- -- /* TODO: setup speed? */ -- ath79_spi_wr(sp, AR71XX_SPI_REG_CTRL, 0x43); - } - - static void ath79_spi_disable(struct ath79_spi *sp) -@@ -203,6 +200,38 @@ static u32 ath79_spi_txrx_mode0(struct s - return ath79_spi_rr(sp, AR71XX_SPI_REG_RDS); - } - -+static bool ath79_spi_flash_read_supported(struct spi_device *spi) -+{ -+ if (spi->chip_select || gpio_is_valid(spi->cs_gpio)) -+ return false; -+ -+ return true; -+} -+ -+static int ath79_spi_read_flash_data(struct spi_device *spi, -+ struct spi_flash_read_message *msg) -+{ -+ struct ath79_spi *sp = ath79_spidev_to_sp(spi); -+ -+ if (msg->addr_width > 3) -+ return -EOPNOTSUPP; -+ -+ /* disable GPIO mode */ -+ ath79_spi_wr(sp, AR71XX_SPI_REG_FS, 0); -+ -+ memcpy_fromio(msg->buf, sp->base + msg->from, msg->len); -+ -+ /* enable GPIO mode */ -+ ath79_spi_wr(sp, AR71XX_SPI_REG_FS, AR71XX_SPI_FS_GPIO); -+ -+ /* restore IOC register */ -+ ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, sp->ioc_base); -+ -+ msg->retlen = msg->len; -+ -+ return 0; -+} -+ - static int ath79_spi_probe(struct platform_device *pdev) - { - struct spi_master *master; -@@ -237,6 +266,8 @@ static int ath79_spi_probe(struct platfo - ret = PTR_ERR(sp->base); - goto err_put_master; - } -+ master->spi_flash_read = ath79_spi_read_flash_data; -+ master->flash_read_supported = ath79_spi_flash_read_supported; - - sp->clk = devm_clk_get(&pdev->dev, "ahb"); - if (IS_ERR(sp->clk)) { diff --git a/target/linux/ath79/patches-4.14/470-MIPS-ath79-swizzle-pci-address-for-ar71xx.patch b/target/linux/ath79/patches-4.14/470-MIPS-ath79-swizzle-pci-address-for-ar71xx.patch deleted file mode 100644 index 634ce5635425..000000000000 --- a/target/linux/ath79/patches-4.14/470-MIPS-ath79-swizzle-pci-address-for-ar71xx.patch +++ /dev/null @@ -1,98 +0,0 @@ ---- /dev/null -+++ b/arch/mips/include/asm/mach-ath79/mangle-port.h -@@ -0,0 +1,37 @@ -+/* -+ * Copyright (C) 2012 Gabor Juhos -+ * -+ * This file was derived from: inlude/asm-mips/mach-generic/mangle-port.h -+ * Copyright (C) 2003, 2004 Ralf Baechle -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#ifndef __ASM_MACH_ATH79_MANGLE_PORT_H -+#define __ASM_MACH_ATH79_MANGLE_PORT_H -+ -+#ifdef CONFIG_PCI_AR71XX -+extern unsigned long (ath79_pci_swizzle_b)(unsigned long port); -+extern unsigned long (ath79_pci_swizzle_w)(unsigned long port); -+#else -+#define ath79_pci_swizzle_b(port) (port) -+#define ath79_pci_swizzle_w(port) (port) -+#endif -+ -+#define __swizzle_addr_b(port) ath79_pci_swizzle_b(port) -+#define __swizzle_addr_w(port) ath79_pci_swizzle_w(port) -+#define __swizzle_addr_l(port) (port) -+#define __swizzle_addr_q(port) (port) -+ -+# define ioswabb(a, x) (x) -+# define __mem_ioswabb(a, x) (x) -+# define ioswabw(a, x) (x) -+# define __mem_ioswabw(a, x) cpu_to_le16(x) -+# define ioswabl(a, x) (x) -+# define __mem_ioswabl(a, x) cpu_to_le32(x) -+# define ioswabq(a, x) (x) -+# define __mem_ioswabq(a, x) cpu_to_le64(x) -+ -+#endif /* __ASM_MACH_ATH79_MANGLE_PORT_H */ ---- a/arch/mips/pci/pci-ar71xx.c -+++ b/arch/mips/pci/pci-ar71xx.c -@@ -71,6 +71,45 @@ static const u32 ar71xx_pci_read_mask[8] - 0, 0xff, 0xffff, 0, 0xffffffff, 0, 0, 0 - }; - -+static unsigned long (*__ath79_pci_swizzle_b)(unsigned long port); -+static unsigned long (*__ath79_pci_swizzle_w)(unsigned long port); -+ -+static inline bool ar71xx_is_pci_addr(unsigned long port) -+{ -+ unsigned long phys = CPHYSADDR(port); -+ -+ return (phys >= AR71XX_PCI_MEM_BASE && -+ phys < AR71XX_PCI_MEM_BASE + AR71XX_PCI_MEM_SIZE); -+} -+ -+static unsigned long ar71xx_pci_swizzle_b(unsigned long port) -+{ -+ return ar71xx_is_pci_addr(port) ? port ^ 3 : port; -+} -+ -+static unsigned long ar71xx_pci_swizzle_w(unsigned long port) -+{ -+ return ar71xx_is_pci_addr(port) ? port ^ 2 : port; -+} -+ -+unsigned long ath79_pci_swizzle_b(unsigned long port) -+{ -+ if (__ath79_pci_swizzle_b) -+ return __ath79_pci_swizzle_b(port); -+ -+ return port; -+} -+EXPORT_SYMBOL(ath79_pci_swizzle_b); -+ -+unsigned long ath79_pci_swizzle_w(unsigned long port) -+{ -+ if (__ath79_pci_swizzle_w) -+ return __ath79_pci_swizzle_w(port); -+ -+ return port; -+} -+EXPORT_SYMBOL(ath79_pci_swizzle_w); -+ - static inline u32 ar71xx_pci_get_ble(int where, int size, int local) - { - u32 t; -@@ -279,6 +318,9 @@ static int ar71xx_pci_probe(struct platf - - register_pci_controller(&apc->pci_ctrl); - -+ __ath79_pci_swizzle_b = ar71xx_pci_swizzle_b; -+ __ath79_pci_swizzle_w = ar71xx_pci_swizzle_w; -+ - return 0; - } - diff --git a/target/linux/ath79/patches-4.14/900-mdio_bitbang_ignore_ta_value.patch b/target/linux/ath79/patches-4.14/900-mdio_bitbang_ignore_ta_value.patch deleted file mode 100644 index 8f8f349a6605..000000000000 --- a/target/linux/ath79/patches-4.14/900-mdio_bitbang_ignore_ta_value.patch +++ /dev/null @@ -1,32 +0,0 @@ ---- a/drivers/net/phy/mdio-bitbang.c -+++ b/drivers/net/phy/mdio-bitbang.c -@@ -155,7 +155,7 @@ static int mdiobb_cmd_addr(struct mdiobb - static int mdiobb_read(struct mii_bus *bus, int phy, int reg) - { - struct mdiobb_ctrl *ctrl = bus->priv; -- int ret, i; -+ int ret; - - if (reg & MII_ADDR_C45) { - reg = mdiobb_cmd_addr(ctrl, phy, reg); -@@ -165,19 +165,7 @@ static int mdiobb_read(struct mii_bus *b - - ctrl->ops->set_mdio_dir(ctrl, 0); - -- /* check the turnaround bit: the PHY should be driving it to zero, if this -- * PHY is listed in phy_ignore_ta_mask as having broken TA, skip that -- */ -- if (mdiobb_get_bit(ctrl) != 0 && -- !(bus->phy_ignore_ta_mask & (1 << phy))) { -- /* PHY didn't drive TA low -- flush any bits it -- * may be trying to send. -- */ -- for (i = 0; i < 32; i++) -- mdiobb_get_bit(ctrl); -- -- return 0xffff; -- } -+ mdiobb_get_bit(ctrl); - - ret = mdiobb_get_num(ctrl, 16); - mdiobb_get_bit(ctrl); diff --git a/target/linux/ath79/patches-4.14/901-phy-mdio-bitbang-prevent-rescheduling-during-command.patch b/target/linux/ath79/patches-4.14/901-phy-mdio-bitbang-prevent-rescheduling-during-command.patch deleted file mode 100644 index a830346a31ef..000000000000 --- a/target/linux/ath79/patches-4.14/901-phy-mdio-bitbang-prevent-rescheduling-during-command.patch +++ /dev/null @@ -1,61 +0,0 @@ -From 66e584435ac0de6e0abeb6d7166fe4fe25d6bb73 Mon Sep 17 00:00:00 2001 -From: Jonas Gorski -Date: Tue, 16 Jun 2015 13:15:08 +0200 -Subject: [PATCH] phy/mdio-bitbang: prevent rescheduling during command - -It seems some phys have some maximum timings for accessing the MDIO line, -resulting in bit errors under cpu stress. Prevent this from happening by -disabling interrupts when sending commands. - -Signed-off-by: Jonas Gorski ---- - drivers/net/phy/mdio-bitbang.c | 9 +++++++++ - 1 file changed, 9 insertions(+) - ---- a/drivers/net/phy/mdio-bitbang.c -+++ b/drivers/net/phy/mdio-bitbang.c -@@ -17,6 +17,7 @@ - * kind, whether express or implied. - */ - -+#include - #include - #include - #include -@@ -156,7 +157,9 @@ static int mdiobb_read(struct mii_bus *b - { - struct mdiobb_ctrl *ctrl = bus->priv; - int ret; -+ unsigned long flags; - -+ local_irq_save(flags); - if (reg & MII_ADDR_C45) { - reg = mdiobb_cmd_addr(ctrl, phy, reg); - mdiobb_cmd(ctrl, MDIO_C45_READ, phy, reg); -@@ -169,13 +172,17 @@ static int mdiobb_read(struct mii_bus *b - - ret = mdiobb_get_num(ctrl, 16); - mdiobb_get_bit(ctrl); -+ local_irq_restore(flags); -+ - return ret; - } - - static int mdiobb_write(struct mii_bus *bus, int phy, int reg, u16 val) - { - struct mdiobb_ctrl *ctrl = bus->priv; -+ unsigned long flags; - -+ local_irq_save(flags); - if (reg & MII_ADDR_C45) { - reg = mdiobb_cmd_addr(ctrl, phy, reg); - mdiobb_cmd(ctrl, MDIO_C45_WRITE, phy, reg); -@@ -190,6 +197,8 @@ static int mdiobb_write(struct mii_bus * - - ctrl->ops->set_mdio_dir(ctrl, 0); - mdiobb_get_bit(ctrl); -+ local_irq_restore(flags); -+ - return 0; - } - diff --git a/target/linux/ath79/patches-4.14/910-unaligned_access_hacks.patch b/target/linux/ath79/patches-4.14/910-unaligned_access_hacks.patch deleted file mode 100644 index cff52e5add0b..000000000000 --- a/target/linux/ath79/patches-4.14/910-unaligned_access_hacks.patch +++ /dev/null @@ -1,900 +0,0 @@ ---- a/arch/mips/include/asm/checksum.h -+++ b/arch/mips/include/asm/checksum.h -@@ -134,26 +134,30 @@ static inline __sum16 ip_fast_csum(const - const unsigned int *stop = word + ihl; - unsigned int csum; - int carry; -+ unsigned int w; - -- csum = word[0]; -- csum += word[1]; -- carry = (csum < word[1]); -+ csum = net_hdr_word(word++); -+ -+ w = net_hdr_word(word++); -+ csum += w; -+ carry = (csum < w); - csum += carry; - -- csum += word[2]; -- carry = (csum < word[2]); -+ w = net_hdr_word(word++); -+ csum += w; -+ carry = (csum < w); - csum += carry; - -- csum += word[3]; -- carry = (csum < word[3]); -+ w = net_hdr_word(word++); -+ csum += w; -+ carry = (csum < w); - csum += carry; - -- word += 4; - do { -- csum += *word; -- carry = (csum < *word); -+ w = net_hdr_word(word++); -+ csum += w; -+ carry = (csum < w); - csum += carry; -- word++; - } while (word != stop); - - return csum_fold(csum); -@@ -214,73 +218,6 @@ static inline __sum16 ip_compute_csum(co - return csum_fold(csum_partial(buff, len, 0)); - } - --#define _HAVE_ARCH_IPV6_CSUM --static __inline__ __sum16 csum_ipv6_magic(const struct in6_addr *saddr, -- const struct in6_addr *daddr, -- __u32 len, __u8 proto, -- __wsum sum) --{ -- __wsum tmp; -- -- __asm__( -- " .set push # csum_ipv6_magic\n" -- " .set noreorder \n" -- " .set noat \n" -- " addu %0, %5 # proto (long in network byte order)\n" -- " sltu $1, %0, %5 \n" -- " addu %0, $1 \n" -- -- " addu %0, %6 # csum\n" -- " sltu $1, %0, %6 \n" -- " lw %1, 0(%2) # four words source address\n" -- " addu %0, $1 \n" -- " addu %0, %1 \n" -- " sltu $1, %0, %1 \n" -- -- " lw %1, 4(%2) \n" -- " addu %0, $1 \n" -- " addu %0, %1 \n" -- " sltu $1, %0, %1 \n" -- -- " lw %1, 8(%2) \n" -- " addu %0, $1 \n" -- " addu %0, %1 \n" -- " sltu $1, %0, %1 \n" -- -- " lw %1, 12(%2) \n" -- " addu %0, $1 \n" -- " addu %0, %1 \n" -- " sltu $1, %0, %1 \n" -- -- " lw %1, 0(%3) \n" -- " addu %0, $1 \n" -- " addu %0, %1 \n" -- " sltu $1, %0, %1 \n" -- -- " lw %1, 4(%3) \n" -- " addu %0, $1 \n" -- " addu %0, %1 \n" -- " sltu $1, %0, %1 \n" -- -- " lw %1, 8(%3) \n" -- " addu %0, $1 \n" -- " addu %0, %1 \n" -- " sltu $1, %0, %1 \n" -- -- " lw %1, 12(%3) \n" -- " addu %0, $1 \n" -- " addu %0, %1 \n" -- " sltu $1, %0, %1 \n" -- -- " addu %0, $1 # Add final carry\n" -- " .set pop" -- : "=&r" (sum), "=&r" (tmp) -- : "r" (saddr), "r" (daddr), -- "0" (htonl(len)), "r" (htonl(proto)), "r" (sum)); -- -- return csum_fold(sum); --} -- - #include - #endif /* CONFIG_GENERIC_CSUM */ - ---- a/include/uapi/linux/ip.h -+++ b/include/uapi/linux/ip.h -@@ -103,7 +103,7 @@ struct iphdr { - __be32 saddr; - __be32 daddr; - /*The options start here. */ --}; -+} __attribute__((packed, aligned(2))); - - - struct ip_auth_hdr { ---- a/include/uapi/linux/ipv6.h -+++ b/include/uapi/linux/ipv6.h -@@ -131,7 +131,7 @@ struct ipv6hdr { - - struct in6_addr saddr; - struct in6_addr daddr; --}; -+} __attribute__((packed, aligned(2))); - - - /* index values for the variables in ipv6_devconf */ ---- a/include/uapi/linux/tcp.h -+++ b/include/uapi/linux/tcp.h -@@ -55,7 +55,7 @@ struct tcphdr { - __be16 window; - __sum16 check; - __be16 urg_ptr; --}; -+} __attribute__((packed, aligned(2))); - - /* - * The union cast uses a gcc extension to avoid aliasing problems -@@ -65,7 +65,7 @@ struct tcphdr { - union tcp_word_hdr { - struct tcphdr hdr; - __be32 words[5]; --}; -+} __attribute__((packed, aligned(2))); - - #define tcp_flag_word(tp) ( ((union tcp_word_hdr *)(tp))->words [3]) - ---- a/include/uapi/linux/udp.h -+++ b/include/uapi/linux/udp.h -@@ -25,7 +25,7 @@ struct udphdr { - __be16 dest; - __be16 len; - __sum16 check; --}; -+} __attribute__((packed, aligned(2))); - - /* UDP socket options */ - #define UDP_CORK 1 /* Never send partially complete segments */ ---- a/net/ipv4/netfilter/nf_conntrack_l3proto_ipv4.c -+++ b/net/ipv4/netfilter/nf_conntrack_l3proto_ipv4.c -@@ -48,8 +48,8 @@ static bool ipv4_pkt_to_tuple(const stru - if (ap == NULL) - return false; - -- tuple->src.u3.ip = ap[0]; -- tuple->dst.u3.ip = ap[1]; -+ tuple->src.u3.ip = net_hdr_word(ap++); -+ tuple->dst.u3.ip = net_hdr_word(ap); - - return true; - } ---- a/include/uapi/linux/icmp.h -+++ b/include/uapi/linux/icmp.h -@@ -82,7 +82,7 @@ struct icmphdr { - } frag; - __u8 reserved[4]; - } un; --}; -+} __attribute__((packed, aligned(2))); - - - /* ---- a/include/uapi/linux/in6.h -+++ b/include/uapi/linux/in6.h -@@ -43,7 +43,7 @@ struct in6_addr { - #define s6_addr16 in6_u.u6_addr16 - #define s6_addr32 in6_u.u6_addr32 - #endif --}; -+} __attribute__((packed, aligned(2))); - #endif /* __UAPI_DEF_IN6_ADDR */ - - #if __UAPI_DEF_SOCKADDR_IN6 ---- a/net/ipv6/tcp_ipv6.c -+++ b/net/ipv6/tcp_ipv6.c -@@ -39,6 +39,7 @@ - #include - #include - #include -+#include - #include - #include - #include -@@ -820,10 +821,10 @@ static void tcp_v6_send_response(const s - topt = (__be32 *)(t1 + 1); - - if (tsecr) { -- *topt++ = htonl((TCPOPT_NOP << 24) | (TCPOPT_NOP << 16) | -- (TCPOPT_TIMESTAMP << 8) | TCPOLEN_TIMESTAMP); -- *topt++ = htonl(tsval); -- *topt++ = htonl(tsecr); -+ put_unaligned_be32((TCPOPT_NOP << 24) | (TCPOPT_NOP << 16) | -+ (TCPOPT_TIMESTAMP << 8) | TCPOLEN_TIMESTAMP, topt++); -+ put_unaligned_be32(tsval, topt++); -+ put_unaligned_be32(tsecr, topt++); - } - - #ifdef CONFIG_TCP_MD5SIG ---- a/include/linux/ipv6.h -+++ b/include/linux/ipv6.h -@@ -6,6 +6,7 @@ - - #define ipv6_optlen(p) (((p)->hdrlen+1) << 3) - #define ipv6_authlen(p) (((p)->hdrlen+2) << 2) -+ - /* - * This structure contains configuration options per IPv6 link. - */ ---- a/net/ipv6/datagram.c -+++ b/net/ipv6/datagram.c -@@ -486,7 +486,7 @@ int ipv6_recv_error(struct sock *sk, str - ipv6_iface_scope_id(&sin->sin6_addr, - IP6CB(skb)->iif); - } else { -- ipv6_addr_set_v4mapped(*(__be32 *)(nh + serr->addr_offset), -+ ipv6_addr_set_v4mapped(net_hdr_word(nh + serr->addr_offset), - &sin->sin6_addr); - sin->sin6_scope_id = 0; - } -@@ -835,12 +835,12 @@ int ip6_datagram_send_ctl(struct net *ne - } - - if (fl6->flowlabel&IPV6_FLOWINFO_MASK) { -- if ((fl6->flowlabel^*(__be32 *)CMSG_DATA(cmsg))&~IPV6_FLOWINFO_MASK) { -+ if ((fl6->flowlabel^net_hdr_word(CMSG_DATA(cmsg)))&~IPV6_FLOWINFO_MASK) { - err = -EINVAL; - goto exit_f; - } - } -- fl6->flowlabel = IPV6_FLOWINFO_MASK & *(__be32 *)CMSG_DATA(cmsg); -+ fl6->flowlabel = IPV6_FLOWINFO_MASK & net_hdr_word(CMSG_DATA(cmsg)); - break; - - case IPV6_2292HOPOPTS: ---- a/net/ipv6/ip6_gre.c -+++ b/net/ipv6/ip6_gre.c -@@ -397,7 +397,7 @@ static void ip6gre_err(struct sk_buff *s - return; - ipv6h = (const struct ipv6hdr *)skb->data; - greh = (const struct gre_base_hdr *)(skb->data + offset); -- key = key_off ? *(__be32 *)(skb->data + key_off) : 0; -+ key = key_off ? net_hdr_word((__be32 *)(skb->data + key_off)) : 0; - - t = ip6gre_tunnel_lookup(skb->dev, &ipv6h->daddr, &ipv6h->saddr, - key, greh->protocol); ---- a/net/ipv6/exthdrs.c -+++ b/net/ipv6/exthdrs.c -@@ -733,7 +733,7 @@ static bool ipv6_hop_jumbo(struct sk_buf - goto drop; - } - -- pkt_len = ntohl(*(__be32 *)(nh + optoff + 2)); -+ pkt_len = ntohl(net_hdr_word(nh + optoff + 2)); - if (pkt_len <= IPV6_MAXPLEN) { - __IP6_INC_STATS(net, ipv6_skb_idev(skb), - IPSTATS_MIB_INHDRERRORS); ---- a/include/linux/types.h -+++ b/include/linux/types.h -@@ -229,5 +229,11 @@ struct callback_head { - typedef void (*rcu_callback_t)(struct rcu_head *head); - typedef void (*call_rcu_func_t)(struct rcu_head *head, rcu_callback_t func); - -+struct net_hdr_word { -+ u32 words[1]; -+} __attribute__((packed, aligned(2))); -+ -+#define net_hdr_word(_p) (((struct net_hdr_word *) (_p))->words[0]) -+ - #endif /* __ASSEMBLY__ */ - #endif /* _LINUX_TYPES_H */ ---- a/net/ipv4/af_inet.c -+++ b/net/ipv4/af_inet.c -@@ -1352,8 +1352,8 @@ struct sk_buff **inet_gro_receive(struct - if (unlikely(ip_fast_csum((u8 *)iph, 5))) - goto out_unlock; - -- id = ntohl(*(__be32 *)&iph->id); -- flush = (u16)((ntohl(*(__be32 *)iph) ^ skb_gro_len(skb)) | (id & ~IP_DF)); -+ id = ntohl(net_hdr_word(&iph->id)); -+ flush = (u16)((ntohl(net_hdr_word(iph)) ^ skb_gro_len(skb)) | (id & ~IP_DF)); - id >>= 16; - - for (p = *head; p; p = p->next) { ---- a/net/ipv4/route.c -+++ b/net/ipv4/route.c -@@ -466,7 +466,7 @@ static struct neighbour *ipv4_neigh_look - else if (skb) - pkey = &ip_hdr(skb)->daddr; - -- n = __ipv4_neigh_lookup(dev, *(__force u32 *)pkey); -+ n = __ipv4_neigh_lookup(dev, net_hdr_word(pkey)); - if (n) - return n; - return neigh_create(&arp_tbl, pkey, dev); ---- a/net/ipv4/tcp_output.c -+++ b/net/ipv4/tcp_output.c -@@ -454,48 +454,53 @@ static void tcp_options_write(__be32 *pt - u16 options = opts->options; /* mungable copy */ - - if (unlikely(OPTION_MD5 & options)) { -- *ptr++ = htonl((TCPOPT_NOP << 24) | (TCPOPT_NOP << 16) | -- (TCPOPT_MD5SIG << 8) | TCPOLEN_MD5SIG); -+ net_hdr_word(ptr++) = -+ htonl((TCPOPT_NOP << 24) | (TCPOPT_NOP << 16) | -+ (TCPOPT_MD5SIG << 8) | TCPOLEN_MD5SIG); - /* overload cookie hash location */ - opts->hash_location = (__u8 *)ptr; - ptr += 4; - } - - if (unlikely(opts->mss)) { -- *ptr++ = htonl((TCPOPT_MSS << 24) | -- (TCPOLEN_MSS << 16) | -- opts->mss); -+ net_hdr_word(ptr++) = -+ htonl((TCPOPT_MSS << 24) | (TCPOLEN_MSS << 16) | -+ opts->mss); - } - - if (likely(OPTION_TS & options)) { - if (unlikely(OPTION_SACK_ADVERTISE & options)) { -- *ptr++ = htonl((TCPOPT_SACK_PERM << 24) | -- (TCPOLEN_SACK_PERM << 16) | -- (TCPOPT_TIMESTAMP << 8) | -- TCPOLEN_TIMESTAMP); -+ net_hdr_word(ptr++) = -+ htonl((TCPOPT_SACK_PERM << 24) | -+ (TCPOLEN_SACK_PERM << 16) | -+ (TCPOPT_TIMESTAMP << 8) | -+ TCPOLEN_TIMESTAMP); - options &= ~OPTION_SACK_ADVERTISE; - } else { -- *ptr++ = htonl((TCPOPT_NOP << 24) | -- (TCPOPT_NOP << 16) | -- (TCPOPT_TIMESTAMP << 8) | -- TCPOLEN_TIMESTAMP); -+ net_hdr_word(ptr++) = -+ htonl((TCPOPT_NOP << 24) | -+ (TCPOPT_NOP << 16) | -+ (TCPOPT_TIMESTAMP << 8) | -+ TCPOLEN_TIMESTAMP); - } -- *ptr++ = htonl(opts->tsval); -- *ptr++ = htonl(opts->tsecr); -+ net_hdr_word(ptr++) = htonl(opts->tsval); -+ net_hdr_word(ptr++) = htonl(opts->tsecr); - } - - if (unlikely(OPTION_SACK_ADVERTISE & options)) { -- *ptr++ = htonl((TCPOPT_NOP << 24) | -- (TCPOPT_NOP << 16) | -- (TCPOPT_SACK_PERM << 8) | -- TCPOLEN_SACK_PERM); -+ net_hdr_word(ptr++) = -+ htonl((TCPOPT_NOP << 24) | -+ (TCPOPT_NOP << 16) | -+ (TCPOPT_SACK_PERM << 8) | -+ TCPOLEN_SACK_PERM); - } - - if (unlikely(OPTION_WSCALE & options)) { -- *ptr++ = htonl((TCPOPT_NOP << 24) | -- (TCPOPT_WINDOW << 16) | -- (TCPOLEN_WINDOW << 8) | -- opts->ws); -+ net_hdr_word(ptr++) = -+ htonl((TCPOPT_NOP << 24) | -+ (TCPOPT_WINDOW << 16) | -+ (TCPOLEN_WINDOW << 8) | -+ opts->ws); - } - - if (unlikely(opts->num_sack_blocks)) { -@@ -503,16 +508,17 @@ static void tcp_options_write(__be32 *pt - tp->duplicate_sack : tp->selective_acks; - int this_sack; - -- *ptr++ = htonl((TCPOPT_NOP << 24) | -- (TCPOPT_NOP << 16) | -- (TCPOPT_SACK << 8) | -- (TCPOLEN_SACK_BASE + (opts->num_sack_blocks * -+ net_hdr_word(ptr++) = -+ htonl((TCPOPT_NOP << 24) | -+ (TCPOPT_NOP << 16) | -+ (TCPOPT_SACK << 8) | -+ (TCPOLEN_SACK_BASE + (opts->num_sack_blocks * - TCPOLEN_SACK_PERBLOCK))); - - for (this_sack = 0; this_sack < opts->num_sack_blocks; - ++this_sack) { -- *ptr++ = htonl(sp[this_sack].start_seq); -- *ptr++ = htonl(sp[this_sack].end_seq); -+ net_hdr_word(ptr++) = htonl(sp[this_sack].start_seq); -+ net_hdr_word(ptr++) = htonl(sp[this_sack].end_seq); - } - - tp->rx_opt.dsack = 0; -@@ -525,13 +531,14 @@ static void tcp_options_write(__be32 *pt - - if (foc->exp) { - len = TCPOLEN_EXP_FASTOPEN_BASE + foc->len; -- *ptr = htonl((TCPOPT_EXP << 24) | (len << 16) | -+ net_hdr_word(ptr) = -+ htonl((TCPOPT_EXP << 24) | (len << 16) | - TCPOPT_FASTOPEN_MAGIC); - p += TCPOLEN_EXP_FASTOPEN_BASE; - } else { - len = TCPOLEN_FASTOPEN_BASE + foc->len; -- *p++ = TCPOPT_FASTOPEN; -- *p++ = len; -+ net_hdr_word(p++) = TCPOPT_FASTOPEN; -+ net_hdr_word(p++) = len; - } - - memcpy(p, foc->val, foc->len); ---- a/include/uapi/linux/igmp.h -+++ b/include/uapi/linux/igmp.h -@@ -33,7 +33,7 @@ struct igmphdr { - __u8 code; /* For newer IGMP */ - __sum16 csum; - __be32 group; --}; -+} __attribute__((packed, aligned(2))); - - /* V3 group record types [grec_type] */ - #define IGMPV3_MODE_IS_INCLUDE 1 -@@ -49,7 +49,7 @@ struct igmpv3_grec { - __be16 grec_nsrcs; - __be32 grec_mca; - __be32 grec_src[0]; --}; -+} __attribute__((packed, aligned(2))); - - struct igmpv3_report { - __u8 type; -@@ -58,7 +58,7 @@ struct igmpv3_report { - __be16 resv2; - __be16 ngrec; - struct igmpv3_grec grec[0]; --}; -+} __attribute__((packed, aligned(2))); - - struct igmpv3_query { - __u8 type; -@@ -79,7 +79,7 @@ struct igmpv3_query { - __u8 qqic; - __be16 nsrcs; - __be32 srcs[0]; --}; -+} __attribute__((packed, aligned(2))); - - #define IGMP_HOST_MEMBERSHIP_QUERY 0x11 /* From RFC1112 */ - #define IGMP_HOST_MEMBERSHIP_REPORT 0x12 /* Ditto */ ---- a/net/core/flow_dissector.c -+++ b/net/core/flow_dissector.c -@@ -109,7 +109,7 @@ __be32 __skb_flow_get_ports(const struct - ports = __skb_header_pointer(skb, thoff + poff, - sizeof(_ports), data, hlen, &_ports); - if (ports) -- return *ports; -+ return (__be32)net_hdr_word(ports); - } - - return 0; ---- a/include/uapi/linux/icmpv6.h -+++ b/include/uapi/linux/icmpv6.h -@@ -77,7 +77,7 @@ struct icmp6hdr { - #define icmp6_addrconf_other icmp6_dataun.u_nd_ra.other - #define icmp6_rt_lifetime icmp6_dataun.u_nd_ra.rt_lifetime - #define icmp6_router_pref icmp6_dataun.u_nd_ra.router_pref --}; -+} __attribute__((packed, aligned(2))); - - - #define ICMPV6_ROUTER_PREF_LOW 0x3 ---- a/include/net/ndisc.h -+++ b/include/net/ndisc.h -@@ -89,7 +89,7 @@ struct ra_msg { - struct icmp6hdr icmph; - __be32 reachable_time; - __be32 retrans_timer; --}; -+} __attribute__((packed, aligned(2))); - - struct rd_msg { - struct icmp6hdr icmph; -@@ -368,10 +368,10 @@ static inline u32 ndisc_hashfn(const voi - { - const u32 *p32 = pkey; - -- return (((p32[0] ^ hash32_ptr(dev)) * hash_rnd[0]) + -- (p32[1] * hash_rnd[1]) + -- (p32[2] * hash_rnd[2]) + -- (p32[3] * hash_rnd[3])); -+ return (((net_hdr_word(&p32[0]) ^ hash32_ptr(dev)) * hash_rnd[0]) + -+ (net_hdr_word(&p32[1]) * hash_rnd[1]) + -+ (net_hdr_word(&p32[2]) * hash_rnd[2]) + -+ (net_hdr_word(&p32[3]) * hash_rnd[3])); - } - - static inline struct neighbour *__ipv6_neigh_lookup_noref(struct net_device *dev, const void *pkey) ---- a/net/sched/cls_u32.c -+++ b/net/sched/cls_u32.c -@@ -165,7 +165,7 @@ next_knode: - data = skb_header_pointer(skb, toff, 4, &hdata); - if (!data) - goto out; -- if ((*data ^ key->val) & key->mask) { -+ if ((net_hdr_word(data) ^ key->val) & key->mask) { - n = rcu_dereference_bh(n->next); - goto next_knode; - } -@@ -218,8 +218,8 @@ check_terminal: - &hdata); - if (!data) - goto out; -- sel = ht->divisor & u32_hash_fold(*data, &n->sel, -- n->fshift); -+ sel = ht->divisor & u32_hash_fold(net_hdr_word(data), -+ &n->sel, n->fshift); - } - if (!(n->sel.flags & (TC_U32_VAROFFSET | TC_U32_OFFSET | TC_U32_EAT))) - goto next_ht; ---- a/net/ipv6/ip6_offload.c -+++ b/net/ipv6/ip6_offload.c -@@ -221,7 +221,7 @@ static struct sk_buff **ipv6_gro_receive - continue; - - iph2 = (struct ipv6hdr *)(p->data + off); -- first_word = *(__be32 *)iph ^ *(__be32 *)iph2; -+ first_word = net_hdr_word(iph) ^ net_hdr_word(iph2); - - /* All fields must match except length and Traffic Class. - * XXX skbs on the gro_list have all been parsed and pulled ---- a/include/net/addrconf.h -+++ b/include/net/addrconf.h -@@ -47,7 +47,7 @@ struct prefix_info { - __be32 reserved2; - - struct in6_addr prefix; --}; -+} __attribute__((packed, aligned(2))); - - #include - #include ---- a/include/net/inet_ecn.h -+++ b/include/net/inet_ecn.h -@@ -125,9 +125,9 @@ static inline int IP6_ECN_set_ce(struct - if (INET_ECN_is_not_ect(ipv6_get_dsfield(iph))) - return 0; - -- from = *(__be32 *)iph; -+ from = net_hdr_word(iph); - to = from | htonl(INET_ECN_CE << 20); -- *(__be32 *)iph = to; -+ net_hdr_word(iph) = to; - if (skb->ip_summed == CHECKSUM_COMPLETE) - skb->csum = csum_add(csum_sub(skb->csum, (__force __wsum)from), - (__force __wsum)to); -@@ -136,7 +136,7 @@ static inline int IP6_ECN_set_ce(struct - - static inline void IP6_ECN_clear(struct ipv6hdr *iph) - { -- *(__be32*)iph &= ~htonl(INET_ECN_MASK << 20); -+ net_hdr_word(iph) &= ~htonl(INET_ECN_MASK << 20); - } - - static inline void ipv6_copy_dscp(unsigned int dscp, struct ipv6hdr *inner) ---- a/include/net/ipv6.h -+++ b/include/net/ipv6.h -@@ -108,7 +108,7 @@ struct frag_hdr { - __u8 reserved; - __be16 frag_off; - __be32 identification; --}; -+} __attribute__((packed, aligned(2))); - - #define IP6_MF 0x0001 - #define IP6_OFFSET 0xFFF8 -@@ -437,8 +437,8 @@ static inline void __ipv6_addr_set_half( - } - #endif - #endif -- addr[0] = wh; -- addr[1] = wl; -+ net_hdr_word(&addr[0]) = wh; -+ net_hdr_word(&addr[1]) = wl; - } - - static inline void ipv6_addr_set(struct in6_addr *addr, -@@ -497,6 +497,8 @@ static inline bool ipv6_prefix_equal(con - const __be32 *a1 = addr1->s6_addr32; - const __be32 *a2 = addr2->s6_addr32; - unsigned int pdw, pbi; -+ /* Used for last <32-bit fraction of prefix */ -+ u32 pbia1, pbia2; - - /* check complete u32 in prefix */ - pdw = prefixlen >> 5; -@@ -505,7 +507,9 @@ static inline bool ipv6_prefix_equal(con - - /* check incomplete u32 in prefix */ - pbi = prefixlen & 0x1f; -- if (pbi && ((a1[pdw] ^ a2[pdw]) & htonl((0xffffffff) << (32 - pbi)))) -+ pbia1 = net_hdr_word(&a1[pdw]); -+ pbia2 = net_hdr_word(&a2[pdw]); -+ if (pbi && ((pbia1 ^ pbia2) & htonl((0xffffffff) << (32 - pbi)))) - return false; - - return true; -@@ -605,13 +609,13 @@ static inline void ipv6_addr_set_v4mappe - */ - static inline int __ipv6_addr_diff32(const void *token1, const void *token2, int addrlen) - { -- const __be32 *a1 = token1, *a2 = token2; -+ const struct in6_addr *a1 = token1, *a2 = token2; - int i; - - addrlen >>= 2; - - for (i = 0; i < addrlen; i++) { -- __be32 xb = a1[i] ^ a2[i]; -+ __be32 xb = a1->s6_addr32[i] ^ a2->s6_addr32[i]; - if (xb) - return i * 32 + 31 - __fls(ntohl(xb)); - } -@@ -780,17 +784,18 @@ static inline int ip6_default_np_autolab - static inline void ip6_flow_hdr(struct ipv6hdr *hdr, unsigned int tclass, - __be32 flowlabel) - { -- *(__be32 *)hdr = htonl(0x60000000 | (tclass << 20)) | flowlabel; -+ net_hdr_word((__be32 *)hdr) = -+ htonl(0x60000000 | (tclass << 20)) | flowlabel; - } - - static inline __be32 ip6_flowinfo(const struct ipv6hdr *hdr) - { -- return *(__be32 *)hdr & IPV6_FLOWINFO_MASK; -+ return net_hdr_word((__be32 *)hdr) & IPV6_FLOWINFO_MASK; - } - - static inline __be32 ip6_flowlabel(const struct ipv6hdr *hdr) - { -- return *(__be32 *)hdr & IPV6_FLOWLABEL_MASK; -+ return net_hdr_word((__be32 *)hdr) & IPV6_FLOWLABEL_MASK; - } - - static inline u8 ip6_tclass(__be32 flowinfo) ---- a/include/net/secure_seq.h -+++ b/include/net/secure_seq.h -@@ -3,6 +3,7 @@ - #define _NET_SECURE_SEQ - - #include -+#include - - u32 secure_ipv4_port_ephemeral(__be32 saddr, __be32 daddr, __be16 dport); - u32 secure_ipv6_port_ephemeral(const __be32 *saddr, const __be32 *daddr, ---- a/include/uapi/linux/in.h -+++ b/include/uapi/linux/in.h -@@ -84,7 +84,7 @@ enum { - /* Internet address. */ - struct in_addr { - __be32 s_addr; --}; -+} __attribute__((packed, aligned(2))); - #endif - - #define IP_TOS 1 ---- a/net/ipv6/ip6_fib.c -+++ b/net/ipv6/ip6_fib.c -@@ -137,7 +137,7 @@ static __be32 addr_bit_set(const void *t - * See include/asm-generic/bitops/le.h. - */ - return (__force __be32)(1 << ((~fn_bit ^ BITOP_BE32_SWIZZLE) & 0x1f)) & -- addr[fn_bit >> 5]; -+ net_hdr_word(&addr[fn_bit >> 5]); - } - - static struct fib6_node *node_alloc(void) ---- a/net/netfilter/nf_conntrack_proto_tcp.c -+++ b/net/netfilter/nf_conntrack_proto_tcp.c -@@ -447,7 +447,7 @@ static void tcp_sack(const struct sk_buf - - /* Fast path for timestamp-only option */ - if (length == TCPOLEN_TSTAMP_ALIGNED -- && *(__be32 *)ptr == htonl((TCPOPT_NOP << 24) -+ && net_hdr_word(ptr) == htonl((TCPOPT_NOP << 24) - | (TCPOPT_NOP << 16) - | (TCPOPT_TIMESTAMP << 8) - | TCPOLEN_TIMESTAMP)) ---- a/net/xfrm/xfrm_input.c -+++ b/net/xfrm/xfrm_input.c -@@ -193,8 +193,8 @@ int xfrm_parse_spi(struct sk_buff *skb, - if (!pskb_may_pull(skb, hlen)) - return -EINVAL; - -- *spi = *(__be32 *)(skb_transport_header(skb) + offset); -- *seq = *(__be32 *)(skb_transport_header(skb) + offset_seq); -+ *spi = net_hdr_word(skb_transport_header(skb) + offset); -+ *seq = net_hdr_word(skb_transport_header(skb) + offset_seq); - return 0; - } - EXPORT_SYMBOL(xfrm_parse_spi); ---- a/net/ipv4/tcp_input.c -+++ b/net/ipv4/tcp_input.c -@@ -3878,14 +3878,16 @@ static bool tcp_parse_aligned_timestamp( - { - const __be32 *ptr = (const __be32 *)(th + 1); - -- if (*ptr == htonl((TCPOPT_NOP << 24) | (TCPOPT_NOP << 16) -- | (TCPOPT_TIMESTAMP << 8) | TCPOLEN_TIMESTAMP)) { -+ if (net_hdr_word(ptr) == -+ htonl((TCPOPT_NOP << 24) | (TCPOPT_NOP << 16) | -+ (TCPOPT_TIMESTAMP << 8) | TCPOLEN_TIMESTAMP)) { - tp->rx_opt.saw_tstamp = 1; - ++ptr; -- tp->rx_opt.rcv_tsval = ntohl(*ptr); -+ tp->rx_opt.rcv_tsval = get_unaligned_be32(ptr); - ++ptr; -- if (*ptr) -- tp->rx_opt.rcv_tsecr = ntohl(*ptr) - tp->tsoffset; -+ if (net_hdr_word(ptr)) -+ tp->rx_opt.rcv_tsecr = get_unaligned_be32(ptr) - -+ tp->tsoffset; - else - tp->rx_opt.rcv_tsecr = 0; - return true; ---- a/include/uapi/linux/if_pppox.h -+++ b/include/uapi/linux/if_pppox.h -@@ -51,6 +51,7 @@ struct pppoe_addr { - */ - struct pptp_addr { - __u16 call_id; -+ __u16 pad; - struct in_addr sin_addr; - }; - ---- a/net/ipv6/netfilter/nf_log_ipv6.c -+++ b/net/ipv6/netfilter/nf_log_ipv6.c -@@ -66,9 +66,9 @@ static void dump_ipv6_packet(struct nf_l - /* Max length: 44 "LEN=65535 TC=255 HOPLIMIT=255 FLOWLBL=FFFFF " */ - nf_log_buf_add(m, "LEN=%zu TC=%u HOPLIMIT=%u FLOWLBL=%u ", - ntohs(ih->payload_len) + sizeof(struct ipv6hdr), -- (ntohl(*(__be32 *)ih) & 0x0ff00000) >> 20, -+ (ntohl(net_hdr_word(ih)) & 0x0ff00000) >> 20, - ih->hop_limit, -- (ntohl(*(__be32 *)ih) & 0x000fffff)); -+ (ntohl(net_hdr_word(ih)) & 0x000fffff)); - - fragment = 0; - ptr = ip6hoff + sizeof(struct ipv6hdr); ---- a/include/net/neighbour.h -+++ b/include/net/neighbour.h -@@ -265,8 +265,10 @@ static inline bool neigh_key_eq128(const - const u32 *n32 = (const u32 *)n->primary_key; - const u32 *p32 = pkey; - -- return ((n32[0] ^ p32[0]) | (n32[1] ^ p32[1]) | -- (n32[2] ^ p32[2]) | (n32[3] ^ p32[3])) == 0; -+ return ((n32[0] ^ net_hdr_word(&p32[0])) | -+ (n32[1] ^ net_hdr_word(&p32[1])) | -+ (n32[2] ^ net_hdr_word(&p32[2])) | -+ (n32[3] ^ net_hdr_word(&p32[3]))) == 0; - } - - static inline struct neighbour *___neigh_lookup_noref( ---- a/include/uapi/linux/netfilter_arp/arp_tables.h -+++ b/include/uapi/linux/netfilter_arp/arp_tables.h -@@ -70,7 +70,7 @@ struct arpt_arp { - __u8 flags; - /* Inverse flags */ - __u16 invflags; --}; -+} __attribute__((aligned(4))); - - /* Values for "flag" field in struct arpt_ip (general arp structure). - * No flags defined yet. ---- a/net/core/utils.c -+++ b/net/core/utils.c -@@ -441,8 +441,14 @@ void inet_proto_csum_replace16(__sum16 * - bool pseudohdr) - { - __be32 diff[] = { -- ~from[0], ~from[1], ~from[2], ~from[3], -- to[0], to[1], to[2], to[3], -+ ~net_hdr_word(&from[0]), -+ ~net_hdr_word(&from[1]), -+ ~net_hdr_word(&from[2]), -+ ~net_hdr_word(&from[3]), -+ net_hdr_word(&to[0]), -+ net_hdr_word(&to[1]), -+ net_hdr_word(&to[2]), -+ net_hdr_word(&to[3]), - }; - if (skb->ip_summed != CHECKSUM_PARTIAL) { - *sum = csum_fold(csum_partial(diff, sizeof(diff), ---- a/include/linux/etherdevice.h -+++ b/include/linux/etherdevice.h -@@ -480,7 +480,7 @@ static inline bool is_etherdev_addr(cons - * @b: Pointer to Ethernet header - * - * Compare two Ethernet headers, returns 0 if equal. -- * This assumes that the network header (i.e., IP header) is 4-byte -+ * This assumes that the network header (i.e., IP header) is 2-byte - * aligned OR the platform can handle unaligned access. This is the - * case for all packets coming into netif_receive_skb or similar - * entry points. -@@ -503,11 +503,12 @@ static inline unsigned long compare_ethe - fold |= *(unsigned long *)(a + 6) ^ *(unsigned long *)(b + 6); - return fold; - #else -- u32 *a32 = (u32 *)((u8 *)a + 2); -- u32 *b32 = (u32 *)((u8 *)b + 2); -+ const u16 *a16 = a; -+ const u16 *b16 = b; - -- return (*(u16 *)a ^ *(u16 *)b) | (a32[0] ^ b32[0]) | -- (a32[1] ^ b32[1]) | (a32[2] ^ b32[2]); -+ return (a16[0] ^ b16[0]) | (a16[1] ^ b16[1]) | (a16[2] ^ b16[2]) | -+ (a16[3] ^ b16[3]) | (a16[4] ^ b16[4]) | (a16[5] ^ b16[5]) | -+ (a16[6] ^ b16[6]); - #endif - } - ---- a/net/ipv4/tcp_offload.c -+++ b/net/ipv4/tcp_offload.c -@@ -226,7 +226,7 @@ struct sk_buff **tcp_gro_receive(struct - - th2 = tcp_hdr(p); - -- if (*(u32 *)&th->source ^ *(u32 *)&th2->source) { -+ if (net_hdr_word(&th->source) ^ net_hdr_word(&th2->source)) { - NAPI_GRO_CB(p)->same_flow = 0; - continue; - } -@@ -244,8 +244,8 @@ found: - ~(TCP_FLAG_CWR | TCP_FLAG_FIN | TCP_FLAG_PSH)); - flush |= (__force int)(th->ack_seq ^ th2->ack_seq); - for (i = sizeof(*th); i < thlen; i += 4) -- flush |= *(u32 *)((u8 *)th + i) ^ -- *(u32 *)((u8 *)th2 + i); -+ flush |= net_hdr_word((u8 *)th + i) ^ -+ net_hdr_word((u8 *)th2 + i); - - /* When we receive our second frame we can made a decision on if we - * continue this flow as an atomic flow with a fixed ID or if we use ---- a/net/ipv6/netfilter/ip6table_mangle.c -+++ b/net/ipv6/netfilter/ip6table_mangle.c -@@ -50,7 +50,7 @@ ip6t_mangle_out(struct sk_buff *skb, con - hop_limit = ipv6_hdr(skb)->hop_limit; - - /* flowlabel and prio (includes version, which shouldn't change either */ -- flowlabel = *((u_int32_t *)ipv6_hdr(skb)); -+ flowlabel = net_hdr_word(ipv6_hdr(skb)); - - ret = ip6t_do_table(skb, state, state->net->ipv6.ip6table_mangle); - -@@ -59,7 +59,7 @@ ip6t_mangle_out(struct sk_buff *skb, con - !ipv6_addr_equal(&ipv6_hdr(skb)->daddr, &daddr) || - skb->mark != mark || - ipv6_hdr(skb)->hop_limit != hop_limit || -- flowlabel != *((u_int32_t *)ipv6_hdr(skb)))) { -+ flowlabel != net_hdr_word(ipv6_hdr(skb)))) { - err = ip6_route_me_harder(state->net, skb); - if (err < 0) - ret = NF_DROP_ERR(err); From patchwork Sun Mar 1 12:12:32 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Hauke Mehrtens X-Patchwork-Id: 1247287 X-Patchwork-Delegate: hauke@hauke-m.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.openwrt.org (client-ip=2607:7c80:54:e::133; helo=bombadil.infradead.org; envelope-from=openwrt-devel-bounces+incoming=patchwork.ozlabs.org@lists.openwrt.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=hauke-m.de Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=lists.infradead.org header.i=@lists.infradead.org header.a=rsa-sha256 header.s=bombadil.20170209 header.b=cddEg5Dn; dkim-atps=neutral Received: from bombadil.infradead.org (bombadil.infradead.org [IPv6:2607:7c80:54:e::133]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 48Vj0K1Swxz9sQt for ; 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Sun, 01 Mar 2020 12:15:25 +0000 Received: from mout-p-102.mailbox.org ([80.241.56.152]) by bombadil.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1j8NSv-0006lT-IM for openwrt-devel@lists.openwrt.org; Sun, 01 Mar 2020 12:13:16 +0000 Received: from smtp2.mailbox.org (smtp2.mailbox.org [IPv6:2001:67c:2050:105:465:1:2:0]) (using TLSv1.2 with cipher ECDHE-RSA-CHACHA20-POLY1305 (256/256 bits)) (No client certificate requested) by mout-p-102.mailbox.org (Postfix) with ESMTPS id 48VhxR67wBzKmbn; Sun, 1 Mar 2020 13:12:59 +0100 (CET) X-Virus-Scanned: amavisd-new at heinlein-support.de Received: from smtp2.mailbox.org ([80.241.60.241]) by gerste.heinlein-support.de (gerste.heinlein-support.de [91.198.250.173]) (amavisd-new, port 10030) with ESMTP id LTIaUWbYjkOH; Sun, 1 Mar 2020 13:12:48 +0100 (CET) From: Hauke Mehrtens To: openwrt-devel@lists.openwrt.org Date: Sun, 1 Mar 2020 13:12:32 +0100 Message-Id: <20200301121241.5545-4-hauke@hauke-m.de> In-Reply-To: <20200301121241.5545-1-hauke@hauke-m.de> References: <20200301121241.5545-1-hauke@hauke-m.de> MIME-Version: 1.0 X-Spam-Note: CRM114 run bypassed due to message size (255667 bytes) X-Spam-Score: -0.7 (/) X-Spam-Report: SpamAssassin version 3.4.3 on bombadil.infradead.org summary: Content analysis details: (-0.7 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at https://www.dnswl.org/, low trust [80.241.56.152 listed in list.dnswl.org] 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.0 SPF_PASS SPF: sender matches SPF record Subject: [OpenWrt-Devel] [PATCH 03/12] gemini: Remove kernel 4.14 support X-BeenThere: openwrt-devel@lists.openwrt.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: hauke@hauke-m.de Sender: "openwrt-devel" Errors-To: openwrt-devel-bounces+incoming=patchwork.ozlabs.org@lists.openwrt.org This target was switched to kernel 4.19 more than 6 months ago in commit f342ffd300da ("treewide: kernel: bump some targets to 4.19") and now with kernel 5.4 support being added it gets harder to support kernel 4.14 in addition to kernel 4.19 and 5.4. Signed-off-by: Hauke Mehrtens --- target/linux/gemini/config-4.14 | 435 -- .../0001-cache-patch-from-OpenWRT.patch | 50 - ...pinctrl-gemini-Add-missing-functions.patch | 33 - ...ts-Add-TVE200-to-the-Gemini-SoC-DTSI.patch | 51 - ...d-skew-delay-pin-config-and-bindings.patch | 73 - ...pinctrl-gemini-Use-generic-DT-parser.patch | 112 - ...ni-Implement-clock-skew-delay-config.patch | 280 -- .../0007-pinctrl-gemini-Fix-GMAC-groups.patch | 186 - ...-gemini-Fix-missing-pad-descriptions.patch | 27 - ...l-gemini-Add-two-missing-GPIO-groups.patch | 25 - ...ctrl-gemini-Fix-usage-of-3512-groups.patch | 25 - ...emini-Support-drive-strength-setting.patch | 198 - ...ernet-PHYs-to-the-a-bunch-of-Geminis.patch | 90 - ...-basic-devicetree-for-D-Link-DNS-313.patch | 272 -- ...s-Flags-D-Link-DIR-685-I2C-bus-gpios.patch | 27 - ...ARM-dts-Add-PCI-to-WBD111-and-WBD222.patch | 74 - ...TVE-TVC-and-ILI9322-panel-to-DIR-685.patch | 113 - ...g-gemini-ftwdt010-rename-DT-bindings.patch | 88 - ...i-ftwdt010-rename-driver-and-symbols.patch | 527 --- ...dog-ftwdt010-Make-interrupt-optional.patch | 93 - .../0020-soc-Add-SoC-driver-for-Gemini.patch | 113 - ...-DT-bindings-for-the-Gemini-ethernet.patch | 119 - ...-a-driver-for-Gemini-gigabit-etherne.patch | 3661 ----------------- ...M-dts-Add-ethernet-to-the-Gemini-SoC.patch | 74 - .../0024-net-gemini-Depend-on-HAS_IOMEM.patch | 30 - ...Set-D-Link-DNS-313-SATA-to-muxmode-0.patch | 36 - ...ini-poweroff-Avoid-spurious-poweroff.patch | 80 - ...st-add-DT-bindings-for-faraday-fotg2.patch | 65 - ...b-host-fotg2-add-device-tree-probing.patch | 61 - ...ost-fotg2-add-silicon-clock-handling.patch | 99 - ...t-fotg2-add-Gemini-specific-handling.patch | 131 - ...s-Add-the-FOTG210-USB-host-to-Gemini.patch | 149 - ...x-bootargs-for-Gemini-D-Link-devices.patch | 38 - ...Add-ethernet-to-a-bunch-of-platforms.patch | 116 - ...-add-openwrt-partitions-for-nas4220b.patch | 17 - ...dts-gemini-fix-ethernet-for-nas4220b.patch | 69 - ...s-gemini-add-second-ata-for-nas4220b.patch | 13 - ...emini-disable-usb-port-1-until-fixed.patch | 11 - ...ix-uninitialized-struct-member-usage.patch | 23 - ...s-gemini-dlink-dir-685-add-rtl8366rb.patch | 82 - 40 files changed, 7766 deletions(-) delete mode 100644 target/linux/gemini/config-4.14 delete mode 100644 target/linux/gemini/patches-4.14/0001-cache-patch-from-OpenWRT.patch delete mode 100644 target/linux/gemini/patches-4.14/0002-pinctrl-gemini-Add-missing-functions.patch delete mode 100644 target/linux/gemini/patches-4.14/0003-ARM-dts-Add-TVE200-to-the-Gemini-SoC-DTSI.patch delete mode 100644 target/linux/gemini/patches-4.14/0004-pinctrl-Add-skew-delay-pin-config-and-bindings.patch delete mode 100644 target/linux/gemini/patches-4.14/0005-pinctrl-gemini-Use-generic-DT-parser.patch delete mode 100644 target/linux/gemini/patches-4.14/0006-pinctrl-gemini-Implement-clock-skew-delay-config.patch delete mode 100644 target/linux/gemini/patches-4.14/0007-pinctrl-gemini-Fix-GMAC-groups.patch delete mode 100644 target/linux/gemini/patches-4.14/0008-pinctrl-gemini-Fix-missing-pad-descriptions.patch delete mode 100644 target/linux/gemini/patches-4.14/0009-pinctrl-gemini-Add-two-missing-GPIO-groups.patch delete mode 100644 target/linux/gemini/patches-4.14/0010-pinctrl-gemini-Fix-usage-of-3512-groups.patch delete mode 100644 target/linux/gemini/patches-4.14/0011-pinctrl-gemini-Support-drive-strength-setting.patch delete mode 100644 target/linux/gemini/patches-4.14/0012-ARM-dts-Add-ethernet-PHYs-to-the-a-bunch-of-Geminis.patch delete mode 100644 target/linux/gemini/patches-4.14/0013-ARM-dts-Add-basic-devicetree-for-D-Link-DNS-313.patch delete mode 100644 target/linux/gemini/patches-4.14/0014-ARM-dts-Flags-D-Link-DIR-685-I2C-bus-gpios.patch delete mode 100644 target/linux/gemini/patches-4.14/0015-ARM-dts-Add-PCI-to-WBD111-and-WBD222.patch delete mode 100644 target/linux/gemini/patches-4.14/0016-ARM-dts-Add-TVE-TVC-and-ILI9322-panel-to-DIR-685.patch delete mode 100644 target/linux/gemini/patches-4.14/0017-watchdog-gemini-ftwdt010-rename-DT-bindings.patch delete mode 100644 target/linux/gemini/patches-4.14/0018-watchdog-gemini-ftwdt010-rename-driver-and-symbols.patch delete mode 100644 target/linux/gemini/patches-4.14/0019-watchdog-ftwdt010-Make-interrupt-optional.patch delete mode 100644 target/linux/gemini/patches-4.14/0020-soc-Add-SoC-driver-for-Gemini.patch delete mode 100644 target/linux/gemini/patches-4.14/0021-net-ethernet-Add-DT-bindings-for-the-Gemini-ethernet.patch delete mode 100644 target/linux/gemini/patches-4.14/0022-net-ethernet-Add-a-driver-for-Gemini-gigabit-etherne.patch delete mode 100644 target/linux/gemini/patches-4.14/0023-ARM-dts-Add-ethernet-to-the-Gemini-SoC.patch delete mode 100644 target/linux/gemini/patches-4.14/0024-net-gemini-Depend-on-HAS_IOMEM.patch delete mode 100644 target/linux/gemini/patches-4.14/0025-ARM-dts-Set-D-Link-DNS-313-SATA-to-muxmode-0.patch delete mode 100644 target/linux/gemini/patches-4.14/0026-power-gemini-poweroff-Avoid-spurious-poweroff.patch delete mode 100644 target/linux/gemini/patches-4.14/0027-usb-host-add-DT-bindings-for-faraday-fotg2.patch delete mode 100644 target/linux/gemini/patches-4.14/0028-usb-host-fotg2-add-device-tree-probing.patch delete mode 100644 target/linux/gemini/patches-4.14/0029-usb-host-fotg2-add-silicon-clock-handling.patch delete mode 100644 target/linux/gemini/patches-4.14/0030-usb-host-fotg2-add-Gemini-specific-handling.patch delete mode 100644 target/linux/gemini/patches-4.14/0031-ARM-dts-Add-the-FOTG210-USB-host-to-Gemini.patch delete mode 100644 target/linux/gemini/patches-4.14/0033-ARM-dts-Fix-bootargs-for-Gemini-D-Link-devices.patch delete mode 100644 target/linux/gemini/patches-4.14/0034-ARM-dts-Add-ethernet-to-a-bunch-of-platforms.patch delete mode 100644 target/linux/gemini/patches-4.14/0900-arm-dts-gemini-add-openwrt-partitions-for-nas4220b.patch delete mode 100644 target/linux/gemini/patches-4.14/0901-arm-dts-gemini-fix-ethernet-for-nas4220b.patch delete mode 100644 target/linux/gemini/patches-4.14/0902-arm-dts-gemini-add-second-ata-for-nas4220b.patch delete mode 100644 target/linux/gemini/patches-4.14/0903-arm-dts-gemini-disable-usb-port-1-until-fixed.patch delete mode 100644 target/linux/gemini/patches-4.14/0904-net-cortina-fix-uninitialized-struct-member-usage.patch delete mode 100644 target/linux/gemini/patches-4.14/0905-arm-dts-gemini-dlink-dir-685-add-rtl8366rb.patch diff --git a/target/linux/gemini/config-4.14 b/target/linux/gemini/config-4.14 deleted file mode 100644 index fb96aa78c73a..000000000000 --- a/target/linux/gemini/config-4.14 +++ /dev/null @@ -1,435 +0,0 @@ -CONFIG_ALIGNMENT_TRAP=y -CONFIG_AMBA_PL08X=y -CONFIG_ARCH_CLOCKSOURCE_DATA=y -CONFIG_ARCH_GEMINI=y -CONFIG_ARCH_HAS_DEBUG_VIRTUAL=y -CONFIG_ARCH_HAS_ELF_RANDOMIZE=y -CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y -CONFIG_ARCH_HAS_RESET_CONTROLLER=y -CONFIG_ARCH_HAS_SET_MEMORY=y -CONFIG_ARCH_HAS_SG_CHAIN=y -CONFIG_ARCH_HAS_STRICT_KERNEL_RWX=y -CONFIG_ARCH_HAS_STRICT_MODULE_RWX=y -CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y -CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y -# CONFIG_ARCH_MOXART is not set -CONFIG_ARCH_MULTIPLATFORM=y -# CONFIG_ARCH_MULTI_CPU_AUTO is not set -CONFIG_ARCH_MULTI_V4=y -# CONFIG_ARCH_MULTI_V4T is not set -CONFIG_ARCH_MULTI_V4_V5=y -# CONFIG_ARCH_MULTI_V5 is not set -CONFIG_ARCH_NR_GPIO=0 -CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y -# CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT is not set -# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set -# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set -CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y -CONFIG_ARCH_SUPPORTS_UPROBES=y -CONFIG_ARCH_USE_BUILTIN_BSWAP=y -CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y -CONFIG_ARCH_WANT_GENERAL_HUGETLB=y -CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y -CONFIG_ARM=y -CONFIG_ARM_AMBA=y -CONFIG_ARM_APPENDED_DTB=y -# CONFIG_ARM_ATAG_DTB_COMPAT is not set -CONFIG_ARM_HAS_SG_CHAIN=y -CONFIG_ARM_L1_CACHE_SHIFT=5 -CONFIG_ARM_PATCH_PHYS_VIRT=y -# CONFIG_ARM_SMMU is not set -# CONFIG_ARM_SP805_WATCHDOG is not set -CONFIG_ARM_UNWIND=y -CONFIG_ATA=y -CONFIG_ATAGS=y -CONFIG_ATA_VERBOSE_ERROR=y -CONFIG_AUTO_ZRELADDR=y -CONFIG_BLK_DEV_SD=y -CONFIG_BLK_MQ_PCI=y -CONFIG_BLK_SCSI_REQUEST=y -CONFIG_BOUNCE=y -# CONFIG_BPF_SYSCALL is not set -# CONFIG_CACHE_L2X0 is not set -CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE=y -# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_CLKDEV_LOOKUP=y -CONFIG_CLKSRC_MMIO=y -CONFIG_CLONE_BACKWARDS=y -CONFIG_COMMON_CLK=y -CONFIG_COMMON_CLK_GEMINI=y -CONFIG_CONSOLE_TRANSLATIONS=y -CONFIG_COREDUMP=y -CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y -CONFIG_CPU_32v4=y -CONFIG_CPU_ABRT_EV4=y -# CONFIG_CPU_BPREDICT_DISABLE is not set -CONFIG_CPU_CACHE_FA=y -CONFIG_CPU_CACHE_VIVT=y -CONFIG_CPU_COPY_FA=y -CONFIG_CPU_CP15=y -CONFIG_CPU_CP15_MMU=y -# CONFIG_CPU_DCACHE_WRITETHROUGH is not set -CONFIG_CPU_FA526=y -# CONFIG_CPU_ICACHE_DISABLE is not set -CONFIG_CPU_NO_EFFICIENT_FFS=y -CONFIG_CPU_PABRT_LEGACY=y -CONFIG_CPU_TLB_FA=y -CONFIG_CPU_USE_DOMAINS=y -CONFIG_CRASH_CORE=y -CONFIG_CRC16=y -# CONFIG_CRC32_SARWATE is not set -CONFIG_CRC32_SLICEBY8=y -CONFIG_CRC_CCITT=y -CONFIG_CRC_ITU_T=y -CONFIG_CROSS_MEMORY_ATTACH=y -CONFIG_CRYPTO_AEAD=y -CONFIG_CRYPTO_AEAD2=y -CONFIG_CRYPTO_CCM=y -CONFIG_CRYPTO_CMAC=y -CONFIG_CRYPTO_CRC32C=y -CONFIG_CRYPTO_CTR=y -CONFIG_CRYPTO_DES=y -CONFIG_CRYPTO_DRBG=y -CONFIG_CRYPTO_DRBG_HMAC=y -CONFIG_CRYPTO_DRBG_MENU=y -CONFIG_CRYPTO_ECB=y -CONFIG_CRYPTO_ECHAINIV=y -CONFIG_CRYPTO_GCM=y -CONFIG_CRYPTO_GF128MUL=y -CONFIG_CRYPTO_GHASH=y -CONFIG_CRYPTO_HASH=y -CONFIG_CRYPTO_HASH2=y -CONFIG_CRYPTO_HMAC=y -CONFIG_CRYPTO_HW=y -CONFIG_CRYPTO_JITTERENTROPY=y -CONFIG_CRYPTO_MANAGER=y -CONFIG_CRYPTO_MANAGER2=y -CONFIG_CRYPTO_MD4=y -CONFIG_CRYPTO_MD5=y -CONFIG_CRYPTO_NULL=y -CONFIG_CRYPTO_NULL2=y -CONFIG_CRYPTO_RNG=y -CONFIG_CRYPTO_RNG2=y -CONFIG_CRYPTO_RNG_DEFAULT=y -CONFIG_CRYPTO_SEQIV=y -CONFIG_CRYPTO_SHA256=y -CONFIG_CRYPTO_WORKQUEUE=y -CONFIG_DEBUG_BUGVERBOSE=y -CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" -CONFIG_DEBUG_MEMORY_INIT=y -# CONFIG_DEBUG_UART_8250 is not set -# CONFIG_DEBUG_USER is not set -CONFIG_DECOMPRESS_BZIP2=y -CONFIG_DECOMPRESS_GZIP=y -CONFIG_DECOMPRESS_LZ4=y -CONFIG_DECOMPRESS_LZMA=y -CONFIG_DECOMPRESS_LZO=y -CONFIG_DECOMPRESS_XZ=y -CONFIG_DEFAULT_CFQ=y -# CONFIG_DEFAULT_DEADLINE is not set -CONFIG_DEFAULT_IOSCHED="cfq" -CONFIG_DMADEVICES=y -CONFIG_DMATEST=y -CONFIG_DMA_ENGINE=y -CONFIG_DMA_ENGINE_RAID=y -CONFIG_DMA_OF=y -CONFIG_DMA_SHARED_BUFFER=y -CONFIG_DMA_VIRTUAL_CHANNELS=y -CONFIG_DTC=y -CONFIG_DUMMY_CONSOLE=y -CONFIG_EDAC_ATOMIC_SCRUB=y -CONFIG_EDAC_SUPPORT=y -CONFIG_EEPROM_93CX6=y -CONFIG_ELF_CORE=y -# CONFIG_EMBEDDED is not set -# CONFIG_ENABLE_WARN_DEPRECATED is not set -# CONFIG_EXPERT is not set -CONFIG_EXT4_FS=y -CONFIG_FARADAY_FTINTC010=y -CONFIG_FHANDLE=y -CONFIG_FIRMWARE_IN_KERNEL=y -CONFIG_FIXED_PHY=y -CONFIG_FIX_EARLYCON_MEM=y -# CONFIG_FPE_FASTFPE is not set -# CONFIG_FPE_NWFPE is not set -CONFIG_FS_MBCACHE=y -CONFIG_FS_POSIX_ACL=y -CONFIG_FTTMR010_TIMER=y -CONFIG_FTWDT010_WATCHDOG=y -# CONFIG_FW_LOADER_USER_HELPER_FALLBACK is not set -CONFIG_GEMINI_ETHERNET=y -CONFIG_GENERIC_ALLOCATOR=y -CONFIG_GENERIC_ATOMIC64=y -CONFIG_GENERIC_BUG=y -CONFIG_GENERIC_CLOCKEVENTS=y -CONFIG_GENERIC_CPU_AUTOPROBE=y -CONFIG_GENERIC_EARLY_IOREMAP=y -CONFIG_GENERIC_IDLE_POLL_SETUP=y -CONFIG_GENERIC_IO=y -CONFIG_GENERIC_IRQ_SHOW=y -CONFIG_GENERIC_IRQ_SHOW_LEVEL=y -CONFIG_GENERIC_PCI_IOMAP=y -CONFIG_GENERIC_PINCONF=y -CONFIG_GENERIC_SCHED_CLOCK=y -CONFIG_GENERIC_SMP_IDLE_THREAD=y -CONFIG_GENERIC_STRNCPY_FROM_USER=y -CONFIG_GENERIC_STRNLEN_USER=y -CONFIG_GLOB=y -CONFIG_GPIOLIB=y -CONFIG_GPIOLIB_IRQCHIP=y -CONFIG_GPIO_FTGPIO010=y -CONFIG_GPIO_GENERIC=y -# CONFIG_GRO_CELLS is not set -CONFIG_HANDLE_DOMAIN_IRQ=y -CONFIG_HARDIRQS_SW_RESEND=y -CONFIG_HAS_DMA=y -CONFIG_HAS_IOMEM=y -CONFIG_HAS_IOPORT_MAP=y -# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set -# CONFIG_HAVE_ARCH_BITREVERSE is not set -CONFIG_HAVE_ARCH_JUMP_LABEL=y -CONFIG_HAVE_ARCH_KGDB=y -CONFIG_HAVE_ARCH_PFN_VALID=y -CONFIG_HAVE_ARCH_TRACEHOOK=y -# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set -CONFIG_HAVE_CC_STACKPROTECTOR=y -CONFIG_HAVE_CLK=y -CONFIG_HAVE_CLK_PREPARE=y -CONFIG_HAVE_CONTEXT_TRACKING=y -CONFIG_HAVE_C_RECORDMCOUNT=y -CONFIG_HAVE_DEBUG_KMEMLEAK=y -CONFIG_HAVE_DMA_API_DEBUG=y -CONFIG_HAVE_DMA_CONTIGUOUS=y -CONFIG_HAVE_DYNAMIC_FTRACE=y -CONFIG_HAVE_DYNAMIC_FTRACE_WITH_REGS=y -CONFIG_HAVE_EBPF_JIT=y -CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y -CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y -CONFIG_HAVE_FUNCTION_TRACER=y -CONFIG_HAVE_GENERIC_DMA_COHERENT=y -CONFIG_HAVE_IDE=y -CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y -CONFIG_HAVE_MEMBLOCK=y -CONFIG_HAVE_MOD_ARCH_SPECIFIC=y -CONFIG_HAVE_NET_DSA=y -CONFIG_HAVE_OPROFILE=y -CONFIG_HAVE_OPTPROBES=y -CONFIG_HAVE_PERF_EVENTS=y -CONFIG_HAVE_PERF_REGS=y -CONFIG_HAVE_PERF_USER_STACK_DUMP=y -CONFIG_HAVE_PROC_CPU=y -CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y -CONFIG_HAVE_SYSCALL_TRACEPOINTS=y -CONFIG_HAVE_UID16=y -CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y -CONFIG_HIGHMEM=y -CONFIG_HIGHPTE=y -CONFIG_HWMON=y -CONFIG_HW_CONSOLE=y -CONFIG_HZ_FIXED=0 -CONFIG_I2C=y -CONFIG_I2C_ALGOBIT=y -CONFIG_I2C_BOARDINFO=y -CONFIG_I2C_COMPAT=y -CONFIG_I2C_GPIO=y -CONFIG_I2C_HELPER_AUTO=y -CONFIG_INITRAMFS_SOURCE="" -CONFIG_INPUT=y -CONFIG_IOMMU_HELPER=y -# CONFIG_IOMMU_IO_PGTABLE_ARMV7S is not set -# CONFIG_IOMMU_IO_PGTABLE_LPAE is not set -CONFIG_IOMMU_SUPPORT=y -CONFIG_IOSCHED_CFQ=y -CONFIG_IPC_NS=y -CONFIG_IRQCHIP=y -CONFIG_IRQ_DOMAIN=y -CONFIG_IRQ_FORCED_THREADING=y -CONFIG_IRQ_WORK=y -# CONFIG_ISDN is not set -CONFIG_JBD2=y -CONFIG_KALLSYMS=y -CONFIG_KERNEL_LZMA=y -# CONFIG_KERNEL_XZ is not set -CONFIG_KEXEC=y -CONFIG_KEXEC_CORE=y -# CONFIG_LDM_DEBUG is not set -CONFIG_LDM_PARTITION=y -CONFIG_LEDS_TRIGGER_DISK=y -CONFIG_LIBFDT=y -CONFIG_LZ4_DECOMPRESS=y -CONFIG_LZO_DECOMPRESS=y -CONFIG_MANDATORY_FILE_LOCKING=y -CONFIG_MDIO_BITBANG=y -CONFIG_MDIO_BUS=y -CONFIG_MDIO_DEVICE=y -CONFIG_MDIO_GPIO=y -CONFIG_MFD_SYSCON=y -CONFIG_MIGHT_HAVE_PCI=y -CONFIG_MIGRATION=y -CONFIG_MODULES_USE_ELF_REL=y -# CONFIG_MODULE_UNLOAD is not set -CONFIG_MQ_IOSCHED_DEADLINE=y -CONFIG_MQ_IOSCHED_KYBER=y -CONFIG_MTD_CFI_STAA=y -# CONFIG_MTD_COMPLEX_MAPPINGS is not set -CONFIG_MTD_PHYSMAP=y -CONFIG_MTD_PHYSMAP_OF_GEMINI=y -CONFIG_MTD_SPLIT_FIRMWARE=y -CONFIG_MTD_SPLIT_WRGG_FW=y -CONFIG_MULTI_IRQ_HANDLER=y -CONFIG_NAMESPACES=y -CONFIG_NEED_DMA_MAP_STATE=y -CONFIG_NEED_KUSER_HELPERS=y -CONFIG_NEED_PER_CPU_KM=y -CONFIG_NET_DSA=y -CONFIG_NET_NS=y -CONFIG_NET_PACKET_ENGINE=y -CONFIG_NET_SWITCHDEV=y -CONFIG_NET_VENDOR_CORTINA=y -CONFIG_NLS=y -CONFIG_NO_BOOTMEM=y -CONFIG_NO_HZ_COMMON=y -CONFIG_NO_HZ_IDLE=y -CONFIG_NVMEM=y -CONFIG_OABI_COMPAT=y -CONFIG_OF=y -CONFIG_OF_ADDRESS=y -CONFIG_OF_ADDRESS_PCI=y -CONFIG_OF_EARLY_FLATTREE=y -CONFIG_OF_FLATTREE=y -CONFIG_OF_GPIO=y -CONFIG_OF_IRQ=y -CONFIG_OF_MDIO=y -CONFIG_OF_NET=y -CONFIG_OF_PCI=y -CONFIG_OF_PCI_IRQ=y -CONFIG_OF_RESERVED_MEM=y -CONFIG_OLD_SIGACTION=y -CONFIG_OLD_SIGSUSPEND3=y -CONFIG_PAGE_OFFSET=0xC0000000 -# CONFIG_PANIC_ON_OOPS is not set -CONFIG_PANIC_ON_OOPS_VALUE=0 -CONFIG_PANIC_TIMEOUT=0 -CONFIG_PATA_FTIDE010=y -CONFIG_PCI=y -CONFIG_PCI_DOMAINS=y -CONFIG_PCI_DOMAINS_GENERIC=y -CONFIG_PCI_FTPCI100=y -CONFIG_PERF_USE_VMALLOC=y -CONFIG_PGTABLE_LEVELS=2 -CONFIG_PHYLIB=y -CONFIG_PID_NS=y -CONFIG_PINCTRL=y -CONFIG_PINCTRL_GEMINI=y -# CONFIG_PINCTRL_SINGLE is not set -CONFIG_PM=y -CONFIG_PM_CLK=y -# CONFIG_PM_DEBUG is not set -CONFIG_POWER_RESET=y -CONFIG_POWER_RESET_GEMINI_POWEROFF=y -CONFIG_POWER_RESET_SYSCON=y -CONFIG_PREEMPT=y -CONFIG_PREEMPT_COUNT=y -# CONFIG_PREEMPT_NONE is not set -CONFIG_PREEMPT_RCU=y -CONFIG_PROC_PAGE_MONITOR=y -CONFIG_RATIONAL=y -CONFIG_RCU_CPU_STALL_TIMEOUT=21 -# CONFIG_RCU_EXPERT is not set -CONFIG_RCU_NEED_SEGCBLIST=y -CONFIG_RCU_STALL_COMMON=y -CONFIG_RD_BZIP2=y -CONFIG_RD_GZIP=y -CONFIG_RD_LZ4=y -CONFIG_RD_LZMA=y -CONFIG_RD_LZO=y -CONFIG_RD_XZ=y -CONFIG_REALTEK_PHY=y -CONFIG_REGMAP=y -CONFIG_REGMAP_I2C=y -CONFIG_REGMAP_MMIO=y -CONFIG_REGMAP_SPI=y -CONFIG_REGULATOR=y -CONFIG_REGULATOR_FIXED_VOLTAGE=y -CONFIG_RELAY=y -CONFIG_RESET_CONTROLLER=y -CONFIG_RTC_CLASS=y -# CONFIG_RTC_DRV_CMOS is not set -CONFIG_RTC_DRV_FTRTC010=y -CONFIG_RTC_I2C_AND_SPI=y -CONFIG_RTC_NVMEM=y -CONFIG_RWSEM_XCHGADD_ALGORITHM=y -CONFIG_SATA_GEMINI=y -CONFIG_SATA_PMP=y -# CONFIG_SCHED_INFO is not set -CONFIG_SCSI=y -# CONFIG_SCSI_LOWLEVEL is not set -# CONFIG_SCSI_PROC_FS is not set -CONFIG_SENSORS_GPIO_FAN=y -CONFIG_SENSORS_LM75=y -CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y -CONFIG_SERIAL_8250_EXAR=y -CONFIG_SERIAL_8250_FSL=y -CONFIG_SERIAL_8250_NR_UARTS=1 -CONFIG_SERIAL_8250_PCI=y -CONFIG_SERIAL_8250_RUNTIME_UARTS=1 -# CONFIG_SERIAL_AMBA_PL011 is not set -CONFIG_SERIAL_OF_PLATFORM=y -CONFIG_SERIO=y -CONFIG_SERIO_LIBPS2=y -CONFIG_SERIO_SERPORT=y -CONFIG_SG_POOL=y -CONFIG_SLUB_DEBUG=y -CONFIG_SPARSE_IRQ=y -CONFIG_SPI=y -CONFIG_SPI_BITBANG=y -CONFIG_SPI_GPIO=y -CONFIG_SPI_MASTER=y -CONFIG_SPLIT_PTLOCK_CPUS=999999 -CONFIG_SRCU=y -# CONFIG_STAGING is not set -# CONFIG_STRIP_ASM_SYMS is not set -CONFIG_SWIOTLB=y -CONFIG_SWPHY=y -CONFIG_SYNC_FILE=y -CONFIG_SYSFS_SYSCALL=y -CONFIG_SYS_SUPPORTS_APM_EMULATION=y -CONFIG_TASKS_RCU=y -# CONFIG_TCP_CONG_ADVANCED is not set -CONFIG_THERMAL=y -CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y -CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0 -CONFIG_THERMAL_GOV_STEP_WISE=y -CONFIG_THERMAL_HWMON=y -CONFIG_THERMAL_OF=y -CONFIG_TICK_CPU_ACCOUNTING=y -CONFIG_TIMER_OF=y -CONFIG_TIMER_PROBE=y -CONFIG_TMPFS_POSIX_ACL=y -CONFIG_TREE_SRCU=y -CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" -CONFIG_UNINLINE_SPIN_UNLOCK=y -CONFIG_USB_SUPPORT=y -# CONFIG_USERIO is not set -CONFIG_USER_NS=y -CONFIG_USE_OF=y -CONFIG_UTS_NS=y -CONFIG_VECTORS_BASE=0xffff0000 -CONFIG_VGA_ARB=y -CONFIG_VGA_ARB_MAX_GPUS=16 -CONFIG_VM_EVENT_COUNTERS=y -CONFIG_VT=y -CONFIG_VT_CONSOLE=y -# CONFIG_VT_HW_CONSOLE_BINDING is not set -CONFIG_WATCHDOG_CORE=y -# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set -CONFIG_XZ_DEC_ARM=y -CONFIG_XZ_DEC_ARMTHUMB=y -CONFIG_XZ_DEC_BCJ=y -CONFIG_XZ_DEC_IA64=y -CONFIG_XZ_DEC_POWERPC=y -CONFIG_XZ_DEC_SPARC=y -CONFIG_XZ_DEC_X86=y -CONFIG_ZBOOT_ROM_BSS=0 -CONFIG_ZBOOT_ROM_TEXT=0 -CONFIG_ZLIB_INFLATE=y diff --git a/target/linux/gemini/patches-4.14/0001-cache-patch-from-OpenWRT.patch b/target/linux/gemini/patches-4.14/0001-cache-patch-from-OpenWRT.patch deleted file mode 100644 index 4430ffee9d74..000000000000 --- a/target/linux/gemini/patches-4.14/0001-cache-patch-from-OpenWRT.patch +++ /dev/null @@ -1,50 +0,0 @@ -From 57615e112aba6ae4c831d50e769c2c102f013686 Mon Sep 17 00:00:00 2001 -From: Linus Walleij -Date: Tue, 7 Jun 2016 22:53:24 +0200 -Subject: [PATCH 01/31] cache patch from OpenWRT - ---- - arch/arm/mm/cache-fa.S | 17 ++++++++++++++++- - 1 file changed, 16 insertions(+), 1 deletion(-) - ---- a/arch/arm/mm/cache-fa.S -+++ b/arch/arm/mm/cache-fa.S -@@ -24,7 +24,8 @@ - /* - * The size of one data cache line. - */ --#define CACHE_DLINESIZE 16 -+#define CACHE_DLINESIZE 16 -+#define CACHE_DLINESHIFT 4 - - /* - * The total size of the data cache. -@@ -169,7 +170,17 @@ ENTRY(fa_flush_kern_dcache_area) - * - start - virtual start address - * - end - virtual end address - */ -+__flush_whole_dcache: -+ mcr p15, 0, r0, c7, c14, 0 @ clean/invalidate D cache -+ mov r0, #0 -+ mcr p15, 0, r0, c7, c10, 4 @ drain write buffer -+ mov pc, lr -+ - fa_dma_inv_range: -+ sub r3, r1, r0 @ calculate total size -+ cmp r3, #CACHE_DLIMIT @ total size >= limit? -+ bhs __flush_whole_dcache @ flush whole D cache -+ - tst r0, #CACHE_DLINESIZE - 1 - bic r0, r0, #CACHE_DLINESIZE - 1 - mcrne p15, 0, r0, c7, c14, 1 @ clean & invalidate D entry -@@ -193,6 +204,10 @@ fa_dma_inv_range: - * - end - virtual end address - */ - fa_dma_clean_range: -+ sub r3, r1, r0 @ calculate total size -+ cmp r3, #CACHE_DLIMIT @ total size >= limit? -+ bhs __flush_whole_dcache @ flush whole D cache -+ - bic r0, r0, #CACHE_DLINESIZE - 1 - 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry - add r0, r0, #CACHE_DLINESIZE diff --git a/target/linux/gemini/patches-4.14/0002-pinctrl-gemini-Add-missing-functions.patch b/target/linux/gemini/patches-4.14/0002-pinctrl-gemini-Add-missing-functions.patch deleted file mode 100644 index d4e93f88b291..000000000000 --- a/target/linux/gemini/patches-4.14/0002-pinctrl-gemini-Add-missing-functions.patch +++ /dev/null @@ -1,33 +0,0 @@ -From fd7823e6993f440930e9cb85e56375be5823485c Mon Sep 17 00:00:00 2001 -From: Linus Walleij -Date: Sat, 14 Oct 2017 17:13:03 +0200 -Subject: [PATCH 02/31] pinctrl: gemini: Add missing functions - -Some two functions were missing from the Gemini pin control -driver. Noticed when trying to use ethernet. Fix it up by -adding them. - -Signed-off-by: Linus Walleij ---- - drivers/pinctrl/pinctrl-gemini.c | 10 ++++++++++ - 1 file changed, 10 insertions(+) - ---- a/drivers/pinctrl/pinctrl-gemini.c -+++ b/drivers/pinctrl/pinctrl-gemini.c -@@ -2102,6 +2102,16 @@ static const struct gemini_pmx_func gemi - .num_groups = ARRAY_SIZE(satagrps), - }, - { -+ .name = "usb", -+ .groups = usbgrps, -+ .num_groups = ARRAY_SIZE(usbgrps), -+ }, -+ { -+ .name = "gmii", -+ .groups = gmiigrps, -+ .num_groups = ARRAY_SIZE(gmiigrps), -+ }, -+ { - .name = "pci", - .groups = pcigrps, - .num_groups = ARRAY_SIZE(pcigrps), diff --git a/target/linux/gemini/patches-4.14/0003-ARM-dts-Add-TVE200-to-the-Gemini-SoC-DTSI.patch b/target/linux/gemini/patches-4.14/0003-ARM-dts-Add-TVE200-to-the-Gemini-SoC-DTSI.patch deleted file mode 100644 index 81d9788af0bf..000000000000 --- a/target/linux/gemini/patches-4.14/0003-ARM-dts-Add-TVE200-to-the-Gemini-SoC-DTSI.patch +++ /dev/null @@ -1,51 +0,0 @@ -From 00e53d08bbe92051765c5bb94223b6f628cd3740 Mon Sep 17 00:00:00 2001 -From: Linus Walleij -Date: Wed, 11 Oct 2017 19:45:19 +0200 -Subject: [PATCH 03/31] ARM: dts: Add TVE200 to the Gemini SoC DTSI - -The Faraday TVE200 is present in the Gemini SoC, sometimes -under the name "TVC". Add it to the SoC DTSI file along with -its resources. - -Signed-off-by: Linus Walleij -Signed-off-by: Arnd Bergmann ---- - arch/arm/boot/dts/gemini.dtsi | 21 +++++++++++++++++++++ - 1 file changed, 21 insertions(+) - ---- a/arch/arm/boot/dts/gemini.dtsi -+++ b/arch/arm/boot/dts/gemini.dtsi -@@ -142,6 +142,12 @@ - groups = "idegrp"; - }; - }; -+ tvc_default_pins: pinctrl-tvc { -+ mux { -+ function = "tvc"; -+ groups = "tvcgrp"; -+ }; -+ }; - }; - }; - -@@ -348,5 +354,20 @@ - memcpy-bus-width = <32>; - #dma-cells = <2>; - }; -+ -+ display-controller@6a000000 { -+ compatible = "cortina,gemini-tvc", "faraday,tve200"; -+ reg = <0x6a000000 0x1000>; -+ interrupts = <13 IRQ_TYPE_EDGE_RISING>; -+ resets = <&syscon GEMINI_RESET_TVC>; -+ clocks = <&syscon GEMINI_CLK_GATE_TVC>, -+ <&syscon GEMINI_CLK_TVC>; -+ clock-names = "PCLK", "TVE"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&tvc_default_pins>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "disabled"; -+ }; - }; - }; diff --git a/target/linux/gemini/patches-4.14/0004-pinctrl-Add-skew-delay-pin-config-and-bindings.patch b/target/linux/gemini/patches-4.14/0004-pinctrl-Add-skew-delay-pin-config-and-bindings.patch deleted file mode 100644 index ac39a3282dc9..000000000000 --- a/target/linux/gemini/patches-4.14/0004-pinctrl-Add-skew-delay-pin-config-and-bindings.patch +++ /dev/null @@ -1,73 +0,0 @@ -From eb3742c4250c6a79e7080bdb6286e5df50c7f26a Mon Sep 17 00:00:00 2001 -From: Linus Walleij -Date: Sat, 28 Oct 2017 15:37:17 +0200 -Subject: [PATCH 04/31] pinctrl: Add skew-delay pin config and bindings - -Some pin controllers (such as the Gemini) can control the -expected clock skew and output delay on certain pins with a -sub-nanosecond granularity. This is typically done by shunting -in a number of double inverters in front of or behind the pin. -Make it possible to configure this with a generic binding. - -Cc: devicetree@vger.kernel.org -Acked-by: Rob Herring -Acked-by: Hans Ulli Kroll -Signed-off-by: Linus Walleij ---- - Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt | 4 ++++ - drivers/pinctrl/pinconf-generic.c | 2 ++ - include/linux/pinctrl/pinconf-generic.h | 5 +++++ - 3 files changed, 11 insertions(+) - ---- a/Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt -+++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt -@@ -271,6 +271,10 @@ output-high - set the pin to output mod - sleep-hardware-state - indicate this is sleep related state which will be programmed - into the registers for the sleep state. - slew-rate - set the slew rate -+skew-delay - this affects the expected clock skew on input pins -+ and the delay before latching a value to an output -+ pin. Typically indicates how many double-inverters are -+ used to delay the signal. - - For example: - ---- a/drivers/pinctrl/pinconf-generic.c -+++ b/drivers/pinctrl/pinconf-generic.c -@@ -49,6 +49,7 @@ static const struct pin_config_item conf - PCONFDUMP(PIN_CONFIG_POWER_SOURCE, "pin power source", "selector", true), - PCONFDUMP(PIN_CONFIG_SLEEP_HARDWARE_STATE, "sleep hardware state", NULL, false), - PCONFDUMP(PIN_CONFIG_SLEW_RATE, "slew rate", NULL, true), -+ PCONFDUMP(PIN_CONFIG_SKEW_DELAY, "skew delay", NULL, true), - }; - - static void pinconf_generic_dump_one(struct pinctrl_dev *pctldev, -@@ -181,6 +182,7 @@ static const struct pinconf_generic_para - { "power-source", PIN_CONFIG_POWER_SOURCE, 0 }, - { "sleep-hardware-state", PIN_CONFIG_SLEEP_HARDWARE_STATE, 0 }, - { "slew-rate", PIN_CONFIG_SLEW_RATE, 0 }, -+ { "skew-delay", PIN_CONFIG_SKEW_DELAY, 0 }, - }; - - /** ---- a/include/linux/pinctrl/pinconf-generic.h -+++ b/include/linux/pinctrl/pinconf-generic.h -@@ -90,6 +90,10 @@ - * @PIN_CONFIG_SLEW_RATE: if the pin can select slew rate, the argument to - * this parameter (on a custom format) tells the driver which alternative - * slew rate to use. -+ * @PIN_CONFIG_SKEW_DELAY: if the pin has programmable skew rate (on inputs) -+ * or latch delay (on outputs) this parameter (in a custom format) -+ * specifies the clock skew or latch delay. It typically controls how -+ * many double inverters are put in front of the line. - * @PIN_CONFIG_END: this is the last enumerator for pin configurations, if - * you need to pass in custom configurations to the pin controller, use - * PIN_CONFIG_END+1 as the base offset. -@@ -117,6 +121,7 @@ enum pin_config_param { - PIN_CONFIG_POWER_SOURCE, - PIN_CONFIG_SLEEP_HARDWARE_STATE, - PIN_CONFIG_SLEW_RATE, -+ PIN_CONFIG_SKEW_DELAY, - PIN_CONFIG_END = 0x7F, - PIN_CONFIG_MAX = 0xFF, - }; diff --git a/target/linux/gemini/patches-4.14/0005-pinctrl-gemini-Use-generic-DT-parser.patch b/target/linux/gemini/patches-4.14/0005-pinctrl-gemini-Use-generic-DT-parser.patch deleted file mode 100644 index f9debdd90020..000000000000 --- a/target/linux/gemini/patches-4.14/0005-pinctrl-gemini-Use-generic-DT-parser.patch +++ /dev/null @@ -1,112 +0,0 @@ -From 09240ae27ffca65518f7b9d2360c020c1b1ddabe Mon Sep 17 00:00:00 2001 -From: Linus Walleij -Date: Sat, 28 Oct 2017 15:37:18 +0200 -Subject: [PATCH 05/31] pinctrl: gemini: Use generic DT parser - -We can just use the generic Device Tree parser code -in this driver and save some code. - -Acked-by: Hans Ulli Kroll -Signed-off-by: Linus Walleij ---- - drivers/pinctrl/Kconfig | 1 + - drivers/pinctrl/pinctrl-gemini.c | 66 +++------------------------------------- - 2 files changed, 5 insertions(+), 62 deletions(-) - ---- a/drivers/pinctrl/Kconfig -+++ b/drivers/pinctrl/Kconfig -@@ -153,6 +153,7 @@ config PINCTRL_GEMINI - depends on ARCH_GEMINI - default ARCH_GEMINI - select PINMUX -+ select GENERIC_PINCONF - select MFD_SYSCON - - config PINCTRL_MCP23S08 ---- a/drivers/pinctrl/pinctrl-gemini.c -+++ b/drivers/pinctrl/pinctrl-gemini.c -@@ -13,6 +13,8 @@ - #include - #include - #include -+#include -+#include - #include - #include - #include -@@ -1946,73 +1948,13 @@ static void gemini_pin_dbg_show(struct p - seq_printf(s, " " DRIVER_NAME); - } - --static int gemini_pinctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev, -- struct device_node *np, -- struct pinctrl_map **map, -- unsigned int *reserved_maps, -- unsigned int *num_maps) --{ -- int ret; -- const char *function = NULL; -- const char *group; -- struct property *prop; -- -- ret = of_property_read_string(np, "function", &function); -- if (ret < 0) -- return ret; -- -- ret = of_property_count_strings(np, "groups"); -- if (ret < 0) -- return ret; -- -- ret = pinctrl_utils_reserve_map(pctldev, map, reserved_maps, -- num_maps, ret); -- if (ret < 0) -- return ret; -- -- of_property_for_each_string(np, "groups", prop, group) { -- ret = pinctrl_utils_add_map_mux(pctldev, map, reserved_maps, -- num_maps, group, function); -- if (ret < 0) -- return ret; -- pr_debug("ADDED FUNCTION %s <-> GROUP %s\n", -- function, group); -- } -- -- return 0; --} -- --static int gemini_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev, -- struct device_node *np_config, -- struct pinctrl_map **map, -- unsigned int *num_maps) --{ -- unsigned int reserved_maps = 0; -- struct device_node *np; -- int ret; -- -- *map = NULL; -- *num_maps = 0; -- -- for_each_child_of_node(np_config, np) { -- ret = gemini_pinctrl_dt_subnode_to_map(pctldev, np, map, -- &reserved_maps, num_maps); -- if (ret < 0) { -- pinctrl_utils_free_map(pctldev, *map, *num_maps); -- return ret; -- } -- } -- -- return 0; --}; -- - static const struct pinctrl_ops gemini_pctrl_ops = { - .get_groups_count = gemini_get_groups_count, - .get_group_name = gemini_get_group_name, - .get_group_pins = gemini_get_group_pins, - .pin_dbg_show = gemini_pin_dbg_show, -- .dt_node_to_map = gemini_pinctrl_dt_node_to_map, -- .dt_free_map = pinctrl_utils_free_map, -+ .dt_node_to_map = pinconf_generic_dt_node_to_map_group, -+ .dt_free_map = pinconf_generic_dt_free_map, - }; - - /** diff --git a/target/linux/gemini/patches-4.14/0006-pinctrl-gemini-Implement-clock-skew-delay-config.patch b/target/linux/gemini/patches-4.14/0006-pinctrl-gemini-Implement-clock-skew-delay-config.patch deleted file mode 100644 index 87a051e1b264..000000000000 --- a/target/linux/gemini/patches-4.14/0006-pinctrl-gemini-Implement-clock-skew-delay-config.patch +++ /dev/null @@ -1,280 +0,0 @@ -From 43e8f011ddbb293e0a3394d0f39819ea2ead4a1b Mon Sep 17 00:00:00 2001 -From: Linus Walleij -Date: Sat, 28 Oct 2017 15:37:19 +0200 -Subject: [PATCH 06/31] pinctrl: gemini: Implement clock skew/delay config - -This enabled pin config on the Gemini driver and implements -pin skew/delay so that the ethernet pins clocking can be -properly configured. - -Acked-by: Hans Ulli Kroll -Signed-off-by: Linus Walleij ---- - .../bindings/pinctrl/cortina,gemini-pinctrl.txt | 10 +- - drivers/pinctrl/pinctrl-gemini.c | 178 ++++++++++++++++++++- - 2 files changed, 182 insertions(+), 6 deletions(-) - ---- a/Documentation/devicetree/bindings/pinctrl/cortina,gemini-pinctrl.txt -+++ b/Documentation/devicetree/bindings/pinctrl/cortina,gemini-pinctrl.txt -@@ -9,8 +9,14 @@ The pin controller node must be a subnod - Required properties: - - compatible: "cortina,gemini-pinctrl" - --Subnodes of the pin controller contain pin control multiplexing set-up. --Please refer to pinctrl-bindings.txt for generic pin multiplexing nodes. -+Subnodes of the pin controller contain pin control multiplexing set-up -+and pin configuration of individual pins. -+ -+Please refer to pinctrl-bindings.txt for generic pin multiplexing nodes -+and generic pin config nodes. -+ -+Supported configurations: -+- skew-delay is supported on the Ethernet pins - - Example: - ---- a/drivers/pinctrl/pinctrl-gemini.c -+++ b/drivers/pinctrl/pinctrl-gemini.c -@@ -24,6 +24,19 @@ - #define DRIVER_NAME "pinctrl-gemini" - - /** -+ * struct gemini_pin_conf - information about configuring a pin -+ * @pin: the pin number -+ * @reg: config register -+ * @mask: the bits affecting the configuration of the pin -+ */ -+struct gemini_pin_conf { -+ unsigned int pin; -+ u32 reg; -+ u32 mask; -+}; -+ -+/** -+ * struct gemini_pmx - state holder for the gemini pin controller - * @dev: a pointer back to containing device - * @virtbase: the offset to the controller in virtual memory - * @map: regmap to access registers -@@ -31,6 +44,8 @@ - * @is_3516: whether the SoC/package is the 3516 variant - * @flash_pin: whether the flash pin (extended pins for parallel - * flash) is set -+ * @confs: pin config information -+ * @nconfs: number of pin config information items - */ - struct gemini_pmx { - struct device *dev; -@@ -39,6 +54,8 @@ struct gemini_pmx { - bool is_3512; - bool is_3516; - bool flash_pin; -+ const struct gemini_pin_conf *confs; -+ unsigned int nconfs; - }; - - /** -@@ -59,6 +76,13 @@ struct gemini_pin_group { - u32 value; - }; - -+/* Some straight-forward control registers */ -+#define GLOBAL_WORD_ID 0x00 -+#define GLOBAL_STATUS 0x04 -+#define GLOBAL_STATUS_FLPIN BIT(20) -+#define GLOBAL_GMAC_CTRL_SKEW 0x1c -+#define GLOBAL_GMAC0_DATA_SKEW 0x20 -+#define GLOBAL_GMAC1_DATA_SKEW 0x24 - /* - * Global Miscellaneous Control Register - * This register controls all Gemini pad/pin multiplexing -@@ -71,9 +95,6 @@ struct gemini_pin_group { - * DISABLED again. So you select a flash configuration once, and then - * you are stuck with it. - */ --#define GLOBAL_WORD_ID 0x00 --#define GLOBAL_STATUS 0x04 --#define GLOBAL_STATUS_FLPIN BIT(20) - #define GLOBAL_MISC_CTRL 0x30 - #define TVC_CLK_PAD_ENABLE BIT(20) - #define PCI_CLK_PAD_ENABLE BIT(17) -@@ -1953,7 +1974,7 @@ static const struct pinctrl_ops gemini_p - .get_group_name = gemini_get_group_name, - .get_group_pins = gemini_get_group_pins, - .pin_dbg_show = gemini_pin_dbg_show, -- .dt_node_to_map = pinconf_generic_dt_node_to_map_group, -+ .dt_node_to_map = pinconf_generic_dt_node_to_map_all, - .dt_free_map = pinconf_generic_dt_free_map, - }; - -@@ -2232,10 +2253,155 @@ static const struct pinmux_ops gemini_pm - .set_mux = gemini_pmx_set_mux, - }; - -+#define GEMINI_CFGPIN(_n, _r, _lb, _hb) { \ -+ .pin = _n, \ -+ .reg = _r, \ -+ .mask = GENMASK(_hb, _lb) \ -+} -+ -+static const struct gemini_pin_conf gemini_confs_3512[] = { -+ GEMINI_CFGPIN(259, GLOBAL_GMAC_CTRL_SKEW, 0, 3), /* GMAC0 RXDV */ -+ GEMINI_CFGPIN(277, GLOBAL_GMAC_CTRL_SKEW, 4, 7), /* GMAC0 RXC */ -+ GEMINI_CFGPIN(241, GLOBAL_GMAC_CTRL_SKEW, 8, 11), /* GMAC0 TXEN */ -+ GEMINI_CFGPIN(312, GLOBAL_GMAC_CTRL_SKEW, 12, 15), /* GMAC0 TXC */ -+ GEMINI_CFGPIN(298, GLOBAL_GMAC_CTRL_SKEW, 16, 19), /* GMAC1 RXDV */ -+ GEMINI_CFGPIN(280, GLOBAL_GMAC_CTRL_SKEW, 20, 23), /* GMAC1 RXC */ -+ GEMINI_CFGPIN(316, GLOBAL_GMAC_CTRL_SKEW, 24, 27), /* GMAC1 TXEN */ -+ GEMINI_CFGPIN(243, GLOBAL_GMAC_CTRL_SKEW, 28, 31), /* GMAC1 TXC */ -+ GEMINI_CFGPIN(295, GLOBAL_GMAC0_DATA_SKEW, 0, 3), /* GMAC0 RXD0 */ -+ GEMINI_CFGPIN(313, GLOBAL_GMAC0_DATA_SKEW, 4, 7), /* GMAC0 RXD1 */ -+ GEMINI_CFGPIN(242, GLOBAL_GMAC0_DATA_SKEW, 8, 11), /* GMAC0 RXD2 */ -+ GEMINI_CFGPIN(260, GLOBAL_GMAC0_DATA_SKEW, 12, 15), /* GMAC0 RXD3 */ -+ GEMINI_CFGPIN(294, GLOBAL_GMAC0_DATA_SKEW, 16, 19), /* GMAC0 TXD0 */ -+ GEMINI_CFGPIN(276, GLOBAL_GMAC0_DATA_SKEW, 20, 23), /* GMAC0 TXD1 */ -+ GEMINI_CFGPIN(258, GLOBAL_GMAC0_DATA_SKEW, 24, 27), /* GMAC0 TXD2 */ -+ GEMINI_CFGPIN(240, GLOBAL_GMAC0_DATA_SKEW, 28, 31), /* GMAC0 TXD3 */ -+ GEMINI_CFGPIN(262, GLOBAL_GMAC1_DATA_SKEW, 0, 3), /* GMAC1 RXD0 */ -+ GEMINI_CFGPIN(244, GLOBAL_GMAC1_DATA_SKEW, 4, 7), /* GMAC1 RXD1 */ -+ GEMINI_CFGPIN(317, GLOBAL_GMAC1_DATA_SKEW, 8, 11), /* GMAC1 RXD2 */ -+ GEMINI_CFGPIN(299, GLOBAL_GMAC1_DATA_SKEW, 12, 15), /* GMAC1 RXD3 */ -+ GEMINI_CFGPIN(261, GLOBAL_GMAC1_DATA_SKEW, 16, 19), /* GMAC1 TXD0 */ -+ GEMINI_CFGPIN(279, GLOBAL_GMAC1_DATA_SKEW, 20, 23), /* GMAC1 TXD1 */ -+ GEMINI_CFGPIN(297, GLOBAL_GMAC1_DATA_SKEW, 24, 27), /* GMAC1 TXD2 */ -+ GEMINI_CFGPIN(315, GLOBAL_GMAC1_DATA_SKEW, 28, 31), /* GMAC1 TXD3 */ -+}; -+ -+static const struct gemini_pin_conf gemini_confs_3516[] = { -+ GEMINI_CFGPIN(347, GLOBAL_GMAC_CTRL_SKEW, 0, 3), /* GMAC0 RXDV */ -+ GEMINI_CFGPIN(386, GLOBAL_GMAC_CTRL_SKEW, 4, 7), /* GMAC0 RXC */ -+ GEMINI_CFGPIN(307, GLOBAL_GMAC_CTRL_SKEW, 8, 11), /* GMAC0 TXEN */ -+ GEMINI_CFGPIN(327, GLOBAL_GMAC_CTRL_SKEW, 12, 15), /* GMAC0 TXC */ -+ GEMINI_CFGPIN(309, GLOBAL_GMAC_CTRL_SKEW, 16, 19), /* GMAC1 RXDV */ -+ GEMINI_CFGPIN(390, GLOBAL_GMAC_CTRL_SKEW, 20, 23), /* GMAC1 RXC */ -+ GEMINI_CFGPIN(370, GLOBAL_GMAC_CTRL_SKEW, 24, 27), /* GMAC1 TXEN */ -+ GEMINI_CFGPIN(350, GLOBAL_GMAC_CTRL_SKEW, 28, 31), /* GMAC1 TXC */ -+ GEMINI_CFGPIN(367, GLOBAL_GMAC0_DATA_SKEW, 0, 3), /* GMAC0 RXD0 */ -+ GEMINI_CFGPIN(348, GLOBAL_GMAC0_DATA_SKEW, 4, 7), /* GMAC0 RXD1 */ -+ GEMINI_CFGPIN(387, GLOBAL_GMAC0_DATA_SKEW, 8, 11), /* GMAC0 RXD2 */ -+ GEMINI_CFGPIN(328, GLOBAL_GMAC0_DATA_SKEW, 12, 15), /* GMAC0 RXD3 */ -+ GEMINI_CFGPIN(306, GLOBAL_GMAC0_DATA_SKEW, 16, 19), /* GMAC0 TXD0 */ -+ GEMINI_CFGPIN(325, GLOBAL_GMAC0_DATA_SKEW, 20, 23), /* GMAC0 TXD1 */ -+ GEMINI_CFGPIN(346, GLOBAL_GMAC0_DATA_SKEW, 24, 27), /* GMAC0 TXD2 */ -+ GEMINI_CFGPIN(326, GLOBAL_GMAC0_DATA_SKEW, 28, 31), /* GMAC0 TXD3 */ -+ GEMINI_CFGPIN(391, GLOBAL_GMAC1_DATA_SKEW, 0, 3), /* GMAC1 RXD0 */ -+ GEMINI_CFGPIN(351, GLOBAL_GMAC1_DATA_SKEW, 4, 7), /* GMAC1 RXD1 */ -+ GEMINI_CFGPIN(310, GLOBAL_GMAC1_DATA_SKEW, 8, 11), /* GMAC1 RXD2 */ -+ GEMINI_CFGPIN(371, GLOBAL_GMAC1_DATA_SKEW, 12, 15), /* GMAC1 RXD3 */ -+ GEMINI_CFGPIN(329, GLOBAL_GMAC1_DATA_SKEW, 16, 19), /* GMAC1 TXD0 */ -+ GEMINI_CFGPIN(389, GLOBAL_GMAC1_DATA_SKEW, 20, 23), /* GMAC1 TXD1 */ -+ GEMINI_CFGPIN(369, GLOBAL_GMAC1_DATA_SKEW, 24, 27), /* GMAC1 TXD2 */ -+ GEMINI_CFGPIN(308, GLOBAL_GMAC1_DATA_SKEW, 28, 31), /* GMAC1 TXD3 */ -+}; -+ -+static const struct gemini_pin_conf *gemini_get_pin_conf(struct gemini_pmx *pmx, -+ unsigned int pin) -+{ -+ const struct gemini_pin_conf *retconf; -+ int i; -+ -+ for (i = 0; i < pmx->nconfs; i++) { -+ retconf = &gemini_confs_3516[i]; -+ if (retconf->pin == pin) -+ return retconf; -+ } -+ return NULL; -+} -+ -+static int gemini_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin, -+ unsigned long *config) -+{ -+ struct gemini_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); -+ enum pin_config_param param = pinconf_to_config_param(*config); -+ const struct gemini_pin_conf *conf; -+ u32 val; -+ -+ switch (param) { -+ case PIN_CONFIG_SKEW_DELAY: -+ conf = gemini_get_pin_conf(pmx, pin); -+ if (!conf) -+ return -ENOTSUPP; -+ regmap_read(pmx->map, conf->reg, &val); -+ val &= conf->mask; -+ val >>= (ffs(conf->mask) - 1); -+ *config = pinconf_to_config_packed(PIN_CONFIG_SKEW_DELAY, val); -+ break; -+ default: -+ return -ENOTSUPP; -+ } -+ -+ return 0; -+} -+ -+static int gemini_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, -+ unsigned long *configs, unsigned int num_configs) -+{ -+ struct gemini_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); -+ const struct gemini_pin_conf *conf; -+ enum pin_config_param param; -+ u32 arg; -+ int ret = 0; -+ int i; -+ -+ for (i = 0; i < num_configs; i++) { -+ param = pinconf_to_config_param(configs[i]); -+ arg = pinconf_to_config_argument(configs[i]); -+ -+ switch (param) { -+ case PIN_CONFIG_SKEW_DELAY: -+ if (arg > 0xf) -+ return -EINVAL; -+ conf = gemini_get_pin_conf(pmx, pin); -+ if (!conf) { -+ dev_err(pmx->dev, -+ "invalid pin for skew delay %d\n", pin); -+ return -ENOTSUPP; -+ } -+ arg <<= (ffs(conf->mask) - 1); -+ dev_dbg(pmx->dev, -+ "set pin %d to skew delay mask %08x, val %08x\n", -+ pin, conf->mask, arg); -+ regmap_update_bits(pmx->map, conf->reg, conf->mask, arg); -+ break; -+ default: -+ dev_err(pmx->dev, "Invalid config param %04x\n", param); -+ return -ENOTSUPP; -+ } -+ } -+ -+ return ret; -+} -+ -+static const struct pinconf_ops gemini_pinconf_ops = { -+ .pin_config_get = gemini_pinconf_get, -+ .pin_config_set = gemini_pinconf_set, -+ .is_generic = true, -+}; -+ - static struct pinctrl_desc gemini_pmx_desc = { - .name = DRIVER_NAME, - .pctlops = &gemini_pctrl_ops, - .pmxops = &gemini_pmx_ops, -+ .confops = &gemini_pinconf_ops, - .owner = THIS_MODULE, - }; - -@@ -2278,11 +2444,15 @@ static int gemini_pmx_probe(struct platf - val &= 0xffff; - if (val == 0x3512) { - pmx->is_3512 = true; -+ pmx->confs = gemini_confs_3512; -+ pmx->nconfs = ARRAY_SIZE(gemini_confs_3512); - gemini_pmx_desc.pins = gemini_3512_pins; - gemini_pmx_desc.npins = ARRAY_SIZE(gemini_3512_pins); - dev_info(dev, "detected 3512 chip variant\n"); - } else if (val == 0x3516) { - pmx->is_3516 = true; -+ pmx->confs = gemini_confs_3516; -+ pmx->nconfs = ARRAY_SIZE(gemini_confs_3516); - gemini_pmx_desc.pins = gemini_3516_pins; - gemini_pmx_desc.npins = ARRAY_SIZE(gemini_3516_pins); - dev_info(dev, "detected 3516 chip variant\n"); diff --git a/target/linux/gemini/patches-4.14/0007-pinctrl-gemini-Fix-GMAC-groups.patch b/target/linux/gemini/patches-4.14/0007-pinctrl-gemini-Fix-GMAC-groups.patch deleted file mode 100644 index 4a4dae34caa2..000000000000 --- a/target/linux/gemini/patches-4.14/0007-pinctrl-gemini-Fix-GMAC-groups.patch +++ /dev/null @@ -1,186 +0,0 @@ -From e7759c44e0c20dd6b5a259300acdc7350ea6dd32 Mon Sep 17 00:00:00 2001 -From: Linus Walleij -Date: Mon, 6 Nov 2017 21:27:34 +0100 -Subject: [PATCH 07/31] pinctrl: gemini: Fix GMAC groups - -The GMII groups need to be split across GMAC0 and GMAC1 since -GMAC0 is always available but GMAC1 masks GPIO2 lines 0-7 -so we might want just one interface out. - -Signed-off-by: Linus Walleij ---- - drivers/pinctrl/pinctrl-gemini.c | 79 +++++++++++++++++++++++++++------------- - 1 file changed, 54 insertions(+), 25 deletions(-) - ---- a/drivers/pinctrl/pinctrl-gemini.c -+++ b/drivers/pinctrl/pinctrl-gemini.c -@@ -96,6 +96,13 @@ struct gemini_pin_group { - * you are stuck with it. - */ - #define GLOBAL_MISC_CTRL 0x30 -+#define GEMINI_GMAC_IOSEL_MASK GENMASK(28, 27) -+/* Not really used */ -+#define GEMINI_GMAC_IOSEL_GMAC0_GMII BIT(28) -+/* Activated with GMAC1 */ -+#define GEMINI_GMAC_IOSEL_GMAC0_GMAC1_RGMII BIT(27) -+/* This will be the default */ -+#define GEMINI_GMAC_IOSEL_GMAC0_RGMII_GMAC1_GPIO2 0 - #define TVC_CLK_PAD_ENABLE BIT(20) - #define PCI_CLK_PAD_ENABLE BIT(17) - #define LPC_CLK_PAD_ENABLE BIT(16) -@@ -109,8 +116,8 @@ struct gemini_pin_group { - #define NAND_PADS_DISABLE BIT(2) - #define PFLASH_PADS_DISABLE BIT(1) - #define SFLASH_PADS_DISABLE BIT(0) --#define PADS_MASK (GENMASK(9, 0) | BIT(16) | BIT(17) | BIT(20)) --#define PADS_MAXBIT 20 -+#define PADS_MASK (GENMASK(9, 0) | BIT(16) | BIT(17) | BIT(20) | BIT(27)) -+#define PADS_MAXBIT 27 - - /* Ordered by bit index */ - static const char * const gemini_padgroups[] = { -@@ -516,9 +523,12 @@ static const unsigned int usb_3512_pins[ - }; - - /* GMII, ethernet pins */ --static const unsigned int gmii_3512_pins[] = { -- 311, 240, 258, 276, 294, 312, 241, 259, 277, 295, 313, 242, 260, 278, 296, -- 315, 297, 279, 261, 243, 316, 298, 280, 262, 244, 317, 299, 281 -+static const unsigned int gmii_gmac0_3512_pins[] = { -+ 240, 241, 242, 258, 259, 260, 276, 277, 278, 294, 295, 311, 312, 313 -+}; -+ -+static const unsigned int gmii_gmac1_3512_pins[] = { -+ 243, 244, 261, 262, 279, 280, 281, 296, 297, 298, 299, 315, 316, 317 - }; - - static const unsigned int pci_3512_pins[] = { -@@ -671,10 +681,10 @@ static const unsigned int gpio1c_3512_pi - /* The GPIO1D (28-31) pins overlap with LCD and TVC */ - static const unsigned int gpio1d_3512_pins[] = { 246, 319, 301, 283 }; - --/* The GPIO2A (0-3) pins overlap with GMII and extended parallel flash */ -+/* The GPIO2A (0-3) pins overlap with GMII GMAC1 and extended parallel flash */ - static const unsigned int gpio2a_3512_pins[] = { 315, 297, 279, 261 }; - --/* The GPIO2B (4-7) pins overlap with GMII, extended parallel flash and LCD */ -+/* The GPIO2B (4-7) pins overlap with GMII GMAC1, extended parallel flash and LCD */ - static const unsigned int gpio2b_3512_pins[] = { 262, 244, 317, 299 }; - - /* The GPIO2C (8-31) pins overlap with PCI */ -@@ -741,9 +751,16 @@ static const struct gemini_pin_group gem - .num_pins = ARRAY_SIZE(usb_3512_pins), - }, - { -- .name = "gmiigrp", -- .pins = gmii_3512_pins, -- .num_pins = ARRAY_SIZE(gmii_3512_pins), -+ .name = "gmii_gmac0_grp", -+ .pins = gmii_gmac0_3512_pins, -+ .num_pins = ARRAY_SIZE(gmii_gmac0_3512_pins), -+ }, -+ { -+ .name = "gmii_gmac1_grp", -+ .pins = gmii_gmac1_3512_pins, -+ .num_pins = ARRAY_SIZE(gmii_gmac1_3512_pins), -+ /* Bring out RGMII on the GMAC1 pins */ -+ .value = GEMINI_GMAC_IOSEL_GMAC0_GMAC1_RGMII, - }, - { - .name = "pcigrp", -@@ -963,14 +980,15 @@ static const struct gemini_pin_group gem - .name = "gpio2agrp", - .pins = gpio2a_3512_pins, - .num_pins = ARRAY_SIZE(gpio2a_3512_pins), -- /* Conflict with GMII and extended parallel flash */ -+ .mask = GEMINI_GMAC_IOSEL_GMAC0_GMAC1_RGMII, -+ /* Conflict with GMII GMAC1 and extended parallel flash */ - }, - { - .name = "gpio2bgrp", - .pins = gpio2b_3512_pins, - .num_pins = ARRAY_SIZE(gpio2b_3512_pins), -- /* Conflict with GMII, extended parallel flash and LCD */ -- .mask = LCD_PADS_ENABLE, -+ /* Conflict with GMII GMAC1, extended parallel flash and LCD */ -+ .mask = LCD_PADS_ENABLE | GEMINI_GMAC_IOSEL_GMAC0_GMAC1_RGMII, - }, - { - .name = "gpio2cgrp", -@@ -1450,9 +1468,12 @@ static const unsigned int usb_3516_pins[ - }; - - /* GMII, ethernet pins */ --static const unsigned int gmii_3516_pins[] = { -- 306, 307, 308, 309, 310, 325, 326, 327, 328, 329, 330, 345, 346, 347, -- 348, 349, 350, 351, 367, 368, 369, 370, 371, 386, 387, 389, 390, 391 -+static const unsigned int gmii_gmac0_3516_pins[] = { -+ 306, 307, 325, 326, 327, 328, 345, 346, 347, 348, 367, 368, 386, 387 -+}; -+ -+static const unsigned int gmii_gmac1_3516_pins[] = { -+ 308, 309, 310, 329, 330, 349, 350, 351, 369, 370, 371, 389, 390, 391 - }; - - static const unsigned int pci_3516_pins[] = { -@@ -1600,10 +1621,10 @@ static const unsigned int gpio1c_3516_pi - /* The GPIO1D (28-31) pins overlap with TVC */ - static const unsigned int gpio1d_3516_pins[] = { 353, 311, 394, 374 }; - --/* The GPIO2A (0-3) pins overlap with GMII and extended parallel flash */ -+/* The GPIO2A (0-3) pins overlap with GMII GMAC1 and extended parallel flash */ - static const unsigned int gpio2a_3516_pins[] = { 308, 369, 389, 329 }; - --/* The GPIO2B (4-7) pins overlap with GMII, extended parallel flash and LCD */ -+/* The GPIO2B (4-7) pins overlap with GMII GMAC1, extended parallel flash and LCD */ - static const unsigned int gpio2b_3516_pins[] = { 391, 351, 310, 371 }; - - /* The GPIO2C (8-31) pins overlap with PCI */ -@@ -1675,9 +1696,16 @@ static const struct gemini_pin_group gem - .num_pins = ARRAY_SIZE(usb_3516_pins), - }, - { -- .name = "gmiigrp", -- .pins = gmii_3516_pins, -- .num_pins = ARRAY_SIZE(gmii_3516_pins), -+ .name = "gmii_gmac0_grp", -+ .pins = gmii_gmac0_3516_pins, -+ .num_pins = ARRAY_SIZE(gmii_gmac0_3516_pins), -+ }, -+ { -+ .name = "gmii_gmac1_grp", -+ .pins = gmii_gmac1_3516_pins, -+ .num_pins = ARRAY_SIZE(gmii_gmac1_3516_pins), -+ /* Bring out RGMII on the GMAC1 pins */ -+ .value = GEMINI_GMAC_IOSEL_GMAC0_GMAC1_RGMII, - }, - { - .name = "pcigrp", -@@ -1889,14 +1917,15 @@ static const struct gemini_pin_group gem - .name = "gpio2agrp", - .pins = gpio2a_3516_pins, - .num_pins = ARRAY_SIZE(gpio2a_3516_pins), -- /* Conflict with GMII and extended parallel flash */ -+ .mask = GEMINI_GMAC_IOSEL_GMAC0_GMAC1_RGMII, -+ /* Conflict with GMII GMAC1 and extended parallel flash */ - }, - { - .name = "gpio2bgrp", - .pins = gpio2b_3516_pins, - .num_pins = ARRAY_SIZE(gpio2b_3516_pins), -- /* Conflict with GMII, extended parallel flash and LCD */ -- .mask = LCD_PADS_ENABLE, -+ /* Conflict with GMII GMAC1, extended parallel flash and LCD */ -+ .mask = LCD_PADS_ENABLE | GEMINI_GMAC_IOSEL_GMAC0_GMAC1_RGMII, - }, - { - .name = "gpio2cgrp", -@@ -1999,7 +2028,7 @@ static const char * const icegrps[] = { - static const char * const idegrps[] = { "idegrp" }; - static const char * const satagrps[] = { "satagrp" }; - static const char * const usbgrps[] = { "usbgrp" }; --static const char * const gmiigrps[] = { "gmiigrp" }; -+static const char * const gmiigrps[] = { "gmii_gmac0_grp", "gmii_gmac1_grp" }; - static const char * const pcigrps[] = { "pcigrp" }; - static const char * const lpcgrps[] = { "lpcgrp" }; - static const char * const lcdgrps[] = { "lcdgrp" }; diff --git a/target/linux/gemini/patches-4.14/0008-pinctrl-gemini-Fix-missing-pad-descriptions.patch b/target/linux/gemini/patches-4.14/0008-pinctrl-gemini-Fix-missing-pad-descriptions.patch deleted file mode 100644 index 2d7ed8304598..000000000000 --- a/target/linux/gemini/patches-4.14/0008-pinctrl-gemini-Fix-missing-pad-descriptions.patch +++ /dev/null @@ -1,27 +0,0 @@ -From 3f2941cb12a6d6a0ef4e53e0ecb8d2431d352964 Mon Sep 17 00:00:00 2001 -From: Linus Walleij -Date: Mon, 13 Nov 2017 22:36:12 +0100 -Subject: [PATCH 08/31] pinctrl: gemini: Fix missing pad descriptions - -A pretty clever static checker found a bug in my patch: I added more -bits to a bitmask but didn't extend the array indexed to the same -bitmask. - -Fixes: 756a024f3983 ("pinctrl: gemini: Fix GMAC groups") -Reported-by: Dan Carpenter -Signed-off-by: Linus Walleij ---- - drivers/pinctrl/pinctrl-gemini.c | 2 ++ - 1 file changed, 2 insertions(+) - ---- a/drivers/pinctrl/pinctrl-gemini.c -+++ b/drivers/pinctrl/pinctrl-gemini.c -@@ -136,6 +136,8 @@ static const char * const gemini_padgrou - "PCI CLK", - NULL, NULL, - "TVC CLK", -+ NULL, NULL, NULL, NULL, NULL, -+ "GMAC1", - }; - - static const struct pinctrl_pin_desc gemini_3512_pins[] = { diff --git a/target/linux/gemini/patches-4.14/0009-pinctrl-gemini-Add-two-missing-GPIO-groups.patch b/target/linux/gemini/patches-4.14/0009-pinctrl-gemini-Add-two-missing-GPIO-groups.patch deleted file mode 100644 index dfb93f6ade48..000000000000 --- a/target/linux/gemini/patches-4.14/0009-pinctrl-gemini-Add-two-missing-GPIO-groups.patch +++ /dev/null @@ -1,25 +0,0 @@ -From c25653d045ce86c5ae472258fdaa39a6baaf75eb Mon Sep 17 00:00:00 2001 -From: Linus Walleij -Date: Sun, 19 Nov 2017 10:57:27 +0100 -Subject: [PATCH 09/31] pinctrl: gemini: Add two missing GPIO groups - -The 3512 has two more GPIO groups on GPIO area 0, so let's -make it possible to combine these with the function. - -Signed-off-by: Linus Walleij ---- - drivers/pinctrl/pinctrl-gemini.c | 3 ++- - 1 file changed, 2 insertions(+), 1 deletion(-) - ---- a/drivers/pinctrl/pinctrl-gemini.c -+++ b/drivers/pinctrl/pinctrl-gemini.c -@@ -2043,7 +2043,8 @@ static const char * const sflashgrps[] = - static const char * const gpio0grps[] = { "gpio0agrp", "gpio0bgrp", "gpio0cgrp", - "gpio0dgrp", "gpio0egrp", "gpio0fgrp", - "gpio0ggrp", "gpio0hgrp", "gpio0igrp", -- "gpio0jgrp", "gpio0kgrp" }; -+ "gpio0jgrp", "gpio0kgrp", "gpio0lgrp", -+ "gpio0mgrp" }; - static const char * const gpio1grps[] = { "gpio1agrp", "gpio1bgrp", "gpio1cgrp", - "gpio1dgrp" }; - static const char * const gpio2grps[] = { "gpio2agrp", "gpio2bgrp", "gpio2cgrp" }; diff --git a/target/linux/gemini/patches-4.14/0010-pinctrl-gemini-Fix-usage-of-3512-groups.patch b/target/linux/gemini/patches-4.14/0010-pinctrl-gemini-Fix-usage-of-3512-groups.patch deleted file mode 100644 index f01edb9bffeb..000000000000 --- a/target/linux/gemini/patches-4.14/0010-pinctrl-gemini-Fix-usage-of-3512-groups.patch +++ /dev/null @@ -1,25 +0,0 @@ -From 88a5c6ad311588f178c5a88e4eeacc6d40b8ede3 Mon Sep 17 00:00:00 2001 -From: Linus Walleij -Date: Wed, 22 Nov 2017 21:04:14 +0100 -Subject: [PATCH 10/31] pinctrl: gemini: Fix usage of 3512 groups - -The pin config lookup function was still hardcoding the -3516 pin set, which is obviously wrong. Use the pointer -in the state container. - -Signed-off-by: Linus Walleij ---- - drivers/pinctrl/pinctrl-gemini.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/drivers/pinctrl/pinctrl-gemini.c -+++ b/drivers/pinctrl/pinctrl-gemini.c -@@ -2352,7 +2352,7 @@ static const struct gemini_pin_conf *gem - int i; - - for (i = 0; i < pmx->nconfs; i++) { -- retconf = &gemini_confs_3516[i]; -+ retconf = &pmx->confs[i]; - if (retconf->pin == pin) - return retconf; - } diff --git a/target/linux/gemini/patches-4.14/0011-pinctrl-gemini-Support-drive-strength-setting.patch b/target/linux/gemini/patches-4.14/0011-pinctrl-gemini-Support-drive-strength-setting.patch deleted file mode 100644 index e6d153403e39..000000000000 --- a/target/linux/gemini/patches-4.14/0011-pinctrl-gemini-Support-drive-strength-setting.patch +++ /dev/null @@ -1,198 +0,0 @@ -From f147cf49ef39f5e87d5df9ef1fab52683bc75c63 Mon Sep 17 00:00:00 2001 -From: Linus Walleij -Date: Sat, 2 Dec 2017 12:23:09 +0100 -Subject: [PATCH 11/31] pinctrl: gemini: Support drive strength setting - -The Gemini pin controller can set drive strength for a few -select groups of pins (not individually). Implement this -for GMAC0 and 1 (ethernet ports), IDE and PCI. - -Cc: devicetree@vger.kernel.org -Reviewed-by: Rob Herring -Signed-off-by: Linus Walleij ---- - .../bindings/pinctrl/cortina,gemini-pinctrl.txt | 3 + - drivers/pinctrl/pinctrl-gemini.c | 81 ++++++++++++++++++++++ - 2 files changed, 84 insertions(+) - ---- a/Documentation/devicetree/bindings/pinctrl/cortina,gemini-pinctrl.txt -+++ b/Documentation/devicetree/bindings/pinctrl/cortina,gemini-pinctrl.txt -@@ -17,6 +17,9 @@ and generic pin config nodes. - - Supported configurations: - - skew-delay is supported on the Ethernet pins -+- drive-strength with 4, 8, 12 or 16 mA as argument is supported for -+ entire groups on the groups "idegrp", "gmii_gmac0_grp", "gmii_gmac1_grp" -+ and "pcigrp". - - Example: - ---- a/drivers/pinctrl/pinctrl-gemini.c -+++ b/drivers/pinctrl/pinctrl-gemini.c -@@ -67,6 +67,9 @@ struct gemini_pmx { - * elements in .pins so we can iterate over that array - * @mask: bits to clear to enable this when doing pin muxing - * @value: bits to set to enable this when doing pin muxing -+ * @driving_mask: bitmask for the IO Pad driving register for this -+ * group, if it supports altering the driving strength of -+ * its lines. - */ - struct gemini_pin_group { - const char *name; -@@ -74,12 +77,14 @@ struct gemini_pin_group { - const unsigned int num_pins; - u32 mask; - u32 value; -+ u32 driving_mask; - }; - - /* Some straight-forward control registers */ - #define GLOBAL_WORD_ID 0x00 - #define GLOBAL_STATUS 0x04 - #define GLOBAL_STATUS_FLPIN BIT(20) -+#define GLOBAL_IODRIVE 0x10 - #define GLOBAL_GMAC_CTRL_SKEW 0x1c - #define GLOBAL_GMAC0_DATA_SKEW 0x20 - #define GLOBAL_GMAC1_DATA_SKEW 0x24 -@@ -741,6 +746,7 @@ static const struct gemini_pin_group gem - /* Conflict with all flash usage */ - .value = IDE_PADS_ENABLE | NAND_PADS_DISABLE | - PFLASH_PADS_DISABLE | SFLASH_PADS_DISABLE, -+ .driving_mask = GENMASK(21, 20), - }, - { - .name = "satagrp", -@@ -756,6 +762,7 @@ static const struct gemini_pin_group gem - .name = "gmii_gmac0_grp", - .pins = gmii_gmac0_3512_pins, - .num_pins = ARRAY_SIZE(gmii_gmac0_3512_pins), -+ .driving_mask = GENMASK(17, 16), - }, - { - .name = "gmii_gmac1_grp", -@@ -763,6 +770,7 @@ static const struct gemini_pin_group gem - .num_pins = ARRAY_SIZE(gmii_gmac1_3512_pins), - /* Bring out RGMII on the GMAC1 pins */ - .value = GEMINI_GMAC_IOSEL_GMAC0_GMAC1_RGMII, -+ .driving_mask = GENMASK(19, 18), - }, - { - .name = "pcigrp", -@@ -770,6 +778,7 @@ static const struct gemini_pin_group gem - .num_pins = ARRAY_SIZE(pci_3512_pins), - /* Conflict only with GPIO2 */ - .value = PCI_PADS_ENABLE | PCI_CLK_PAD_ENABLE, -+ .driving_mask = GENMASK(23, 22), - }, - { - .name = "lpcgrp", -@@ -1686,6 +1695,7 @@ static const struct gemini_pin_group gem - /* Conflict with all flash usage */ - .value = IDE_PADS_ENABLE | NAND_PADS_DISABLE | - PFLASH_PADS_DISABLE | SFLASH_PADS_DISABLE, -+ .driving_mask = GENMASK(21, 20), - }, - { - .name = "satagrp", -@@ -1701,6 +1711,7 @@ static const struct gemini_pin_group gem - .name = "gmii_gmac0_grp", - .pins = gmii_gmac0_3516_pins, - .num_pins = ARRAY_SIZE(gmii_gmac0_3516_pins), -+ .driving_mask = GENMASK(17, 16), - }, - { - .name = "gmii_gmac1_grp", -@@ -1708,6 +1719,7 @@ static const struct gemini_pin_group gem - .num_pins = ARRAY_SIZE(gmii_gmac1_3516_pins), - /* Bring out RGMII on the GMAC1 pins */ - .value = GEMINI_GMAC_IOSEL_GMAC0_GMAC1_RGMII, -+ .driving_mask = GENMASK(19, 18), - }, - { - .name = "pcigrp", -@@ -1715,6 +1727,7 @@ static const struct gemini_pin_group gem - .num_pins = ARRAY_SIZE(pci_3516_pins), - /* Conflict only with GPIO2 */ - .value = PCI_PADS_ENABLE | PCI_CLK_PAD_ENABLE, -+ .driving_mask = GENMASK(23, 22), - }, - { - .name = "lpcgrp", -@@ -2423,9 +2436,77 @@ static int gemini_pinconf_set(struct pin - return ret; - } - -+static int gemini_pinconf_group_set(struct pinctrl_dev *pctldev, -+ unsigned selector, -+ unsigned long *configs, -+ unsigned num_configs) -+{ -+ struct gemini_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); -+ const struct gemini_pin_group *grp = NULL; -+ enum pin_config_param param; -+ u32 arg; -+ u32 val; -+ int i; -+ -+ if (pmx->is_3512) -+ grp = &gemini_3512_pin_groups[selector]; -+ if (pmx->is_3516) -+ grp = &gemini_3516_pin_groups[selector]; -+ -+ /* First figure out if this group supports configs */ -+ if (!grp->driving_mask) { -+ dev_err(pmx->dev, "pin config group \"%s\" does " -+ "not support drive strength setting\n", -+ grp->name); -+ return -EINVAL; -+ } -+ -+ for (i = 0; i < num_configs; i++) { -+ param = pinconf_to_config_param(configs[i]); -+ arg = pinconf_to_config_argument(configs[i]); -+ -+ switch (param) { -+ case PIN_CONFIG_DRIVE_STRENGTH: -+ switch (arg) { -+ case 4: -+ val = 0; -+ break; -+ case 8: -+ val = 1; -+ break; -+ case 12: -+ val = 2; -+ break; -+ case 16: -+ val = 3; -+ break; -+ default: -+ dev_err(pmx->dev, -+ "invalid drive strength %d mA\n", -+ arg); -+ return -ENOTSUPP; -+ } -+ val <<= (ffs(grp->driving_mask) - 1); -+ regmap_update_bits(pmx->map, GLOBAL_IODRIVE, -+ grp->driving_mask, -+ val); -+ dev_info(pmx->dev, -+ "set group %s to %d mA drive strength mask %08x val %08x\n", -+ grp->name, arg, grp->driving_mask, val); -+ break; -+ default: -+ dev_err(pmx->dev, "invalid config param %04x\n", param); -+ return -ENOTSUPP; -+ } -+ } -+ -+ return 0; -+} -+ - static const struct pinconf_ops gemini_pinconf_ops = { - .pin_config_get = gemini_pinconf_get, - .pin_config_set = gemini_pinconf_set, -+ .pin_config_group_set = gemini_pinconf_group_set, - .is_generic = true, - }; - diff --git a/target/linux/gemini/patches-4.14/0012-ARM-dts-Add-ethernet-PHYs-to-the-a-bunch-of-Geminis.patch b/target/linux/gemini/patches-4.14/0012-ARM-dts-Add-ethernet-PHYs-to-the-a-bunch-of-Geminis.patch deleted file mode 100644 index 2549ea3151da..000000000000 --- a/target/linux/gemini/patches-4.14/0012-ARM-dts-Add-ethernet-PHYs-to-the-a-bunch-of-Geminis.patch +++ /dev/null @@ -1,90 +0,0 @@ -From f0674df220f3da81c173025636a904b395cf8f8b Mon Sep 17 00:00:00 2001 -From: Linus Walleij -Date: Sun, 19 Nov 2017 10:46:16 +0100 -Subject: [PATCH 12/31] ARM: dts: Add ethernet PHYs to the a bunch of Geminis - -These Gemini boards have Ethernet PHY on GPIO bit-banged -MDIO, clearly defined in the corresponding OpenWRT -ethernet patches since ages. Add them in accordance with -the OpenWRT patch so we can use them when we add ethernet -support. - -Reviewed-by: Andrew Lunn -Signed-off-by: Linus Walleij ---- - arch/arm/boot/dts/gemini-nas4220b.dts | 13 +++++++++++++ - arch/arm/boot/dts/gemini-wbd111.dts | 13 +++++++++++++ - arch/arm/boot/dts/gemini-wbd222.dts | 18 ++++++++++++++++++ - 4 files changed, 57 insertions(+) - ---- a/arch/arm/boot/dts/gemini-nas4220b.dts -+++ b/arch/arm/boot/dts/gemini-nas4220b.dts -@@ -64,6 +64,19 @@ - }; - }; - -+ mdio0: ethernet-phy { -+ compatible = "virtual,mdio-gpio"; -+ gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>, /* MDC */ -+ <&gpio0 21 GPIO_ACTIVE_HIGH>; /* MDIO */ -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ phy0: ethernet-phy@1 { -+ reg = <1>; -+ device_type = "ethernet-phy"; -+ }; -+ }; -+ - soc { - flash@30000000 { - status = "okay"; ---- a/arch/arm/boot/dts/gemini-wbd111.dts -+++ b/arch/arm/boot/dts/gemini-wbd111.dts -@@ -69,6 +69,19 @@ - }; - }; - -+ mdio0: ethernet-phy { -+ compatible = "virtual,mdio-gpio"; -+ gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>, /* MDC */ -+ <&gpio0 21 GPIO_ACTIVE_HIGH>; /* MDIO */ -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ phy0: ethernet-phy@1 { -+ reg = <1>; -+ device_type = "ethernet-phy"; -+ }; -+ }; -+ - soc { - flash@30000000 { - status = "okay"; ---- a/arch/arm/boot/dts/gemini-wbd222.dts -+++ b/arch/arm/boot/dts/gemini-wbd222.dts -@@ -69,6 +69,24 @@ - }; - }; - -+ mdio0: ethernet-phy { -+ compatible = "virtual,mdio-gpio"; -+ gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>, /* MDC */ -+ <&gpio0 21 GPIO_ACTIVE_HIGH>; /* MDIO */ -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ phy0: ethernet-phy@1 { -+ reg = <1>; -+ device_type = "ethernet-phy"; -+ }; -+ -+ phy1: ethernet-phy@3 { -+ reg = <3>; -+ device_type = "ethernet-phy"; -+ }; -+ }; -+ - soc { - flash@30000000 { - status = "okay"; diff --git a/target/linux/gemini/patches-4.14/0013-ARM-dts-Add-basic-devicetree-for-D-Link-DNS-313.patch b/target/linux/gemini/patches-4.14/0013-ARM-dts-Add-basic-devicetree-for-D-Link-DNS-313.patch deleted file mode 100644 index 3d2f4ed8a96c..000000000000 --- a/target/linux/gemini/patches-4.14/0013-ARM-dts-Add-basic-devicetree-for-D-Link-DNS-313.patch +++ /dev/null @@ -1,272 +0,0 @@ -From 2f08de94f207a4347053e1faa22c9a310c9c61b0 Mon Sep 17 00:00:00 2001 -From: Linus Walleij -Date: Fri, 17 Nov 2017 16:36:32 +0100 -Subject: [PATCH 13/31] ARM: dts: Add basic devicetree for D-Link DNS-313 - -This adds a basic device tree for the D-Link DNS-313 -NAS enclosure. This device has a thermal sensor and a -fan so we add a thermal zone for the chassis in the -device tree based on information from the product. - -Reviewed-by: Andrew Lunn -Signed-off-by: Linus Walleij ---- - arch/arm/boot/dts/Makefile | 1 + - arch/arm/boot/dts/gemini-dlink-dns-313.dts | 241 +++++++++++++++++++++++++++++ - 2 files changed, 242 insertions(+) - create mode 100644 arch/arm/boot/dts/gemini-dlink-dns-313.dts - ---- a/arch/arm/boot/dts/Makefile -+++ b/arch/arm/boot/dts/Makefile -@@ -185,6 +185,7 @@ dtb-$(CONFIG_ARCH_EXYNOS5) += \ - exynos5800-peach-pi.dtb - dtb-$(CONFIG_ARCH_GEMINI) += \ - gemini-dlink-dir-685.dtb \ -+ gemini-dlink-dns-313.dtb \ - gemini-nas4220b.dtb \ - gemini-rut1xx.dtb \ - gemini-sq201.dtb \ ---- /dev/null -+++ b/arch/arm/boot/dts/gemini-dlink-dns-313.dts -@@ -0,0 +1,241 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * Device Tree file for D-Link DNS-313 1-Bay Network Storage Enclosure -+ */ -+ -+/dts-v1/; -+ -+#include "gemini.dtsi" -+#include -+#include -+ -+/ { -+ model = "D-Link DNS-313 1-Bay Network Storage Enclosure"; -+ compatible = "dlink,dns-313", "cortina,gemini"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ -+ memory { -+ /* 64 MB SDRAM in a Nanya NT5DS32M16BS-6K package */ -+ device_type = "memory"; -+ reg = <0x00000000 0x4000000>; -+ }; -+ -+ aliases { -+ mdio-gpio0 = &mdio0; -+ }; -+ -+ chosen { -+ stdout-path = "uart0:19200n8"; -+ }; -+ -+ gpio_keys { -+ compatible = "gpio-keys"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ button-esc { -+ debounce_interval = <50>; -+ wakeup-source; -+ linux,code = ; -+ label = "reset"; -+ gpios = <&gpio1 31 GPIO_ACTIVE_LOW>; -+ }; -+ }; -+ -+ leds { -+ compatible = "gpio-leds"; -+ led-power { -+ label = "dns313:blue:power"; -+ gpios = <&gpio0 1 GPIO_ACTIVE_HIGH>; -+ default-state = "on"; -+ linux,default-trigger = "heartbeat"; -+ }; -+ led-disk-blue { -+ label = "dns313:blue:disk"; -+ gpios = <&gpio0 2 GPIO_ACTIVE_HIGH>; -+ default-state = "off"; -+ }; -+ led-disk-green { -+ label = "dns313:green:disk"; -+ gpios = <&gpio0 3 GPIO_ACTIVE_HIGH>; -+ default-state = "off"; -+ linux,default-trigger = "ide-disk"; -+ /* Ideally should activate while reading */ -+ }; -+ led-disk-red { -+ label = "dns313:red:disk"; -+ gpios = <&gpio0 4 GPIO_ACTIVE_HIGH>; -+ default-state = "off"; -+ /* Ideally should activate while writing */ -+ }; -+ }; -+ -+ /* -+ * This is a ADDA AD0405GB-G73 fan @3000 and 6000 RPM. -+ */ -+ fan0: gpio-fan { -+ compatible = "gpio-fan"; -+ gpios = <&gpio0 11 GPIO_ACTIVE_HIGH>, -+ <&gpio0 12 GPIO_ACTIVE_HIGH>; -+ gpio-fan,speed-map = <0 0>, <3000 1>, <6000 2>; -+ cooling-min-level = <0>; -+ cooling-max-level = <2>; -+ #cooling-cells = <2>; -+ }; -+ -+ -+ /* Global Mixed-Mode Technology G751 mounted on GPIO I2C */ -+ gpio-i2c { -+ compatible = "i2c-gpio"; -+ sda-gpios = <&gpio0 15 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; -+ scl-gpios = <&gpio0 16 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ g751: temperature-sensor@48 { -+ compatible = "gmt,g751"; -+ reg = <0x48>; -+ #thermal-sensor-cells = <0>; -+ }; -+ }; -+ -+ thermal-zones { -+ chassis-thermal { -+ /* Poll every 20 seconds */ -+ polling-delay = <20000>; -+ /* Poll every 2nd second when cooling */ -+ polling-delay-passive = <2000>; -+ -+ thermal-sensors = <&g751>; -+ -+ /* Tripping points from the fan.script in the rootfs */ -+ trips { -+ chassis_alert0: chassis-alert0 { -+ /* At 43 degrees turn on low speed */ -+ temperature = <43000>; -+ hysteresis = <3000>; -+ type = "active"; -+ }; -+ chassis_alert1: chassis-alert1 { -+ /* At 47 degrees turn on high speed */ -+ temperature = <47000>; -+ hysteresis = <3000>; -+ type = "active"; -+ }; -+ chassis_crit: chassis-crit { -+ /* Just shut down at 60 degrees */ -+ temperature = <60000>; -+ hysteresis = <2000>; -+ type = "critical"; -+ }; -+ }; -+ -+ cooling-maps { -+ map0 { -+ trip = <&chassis_alert0>; -+ cooling-device = <&fan0 1 1>; -+ }; -+ map1 { -+ trip = <&chassis_alert1>; -+ cooling-device = <&fan0 2 2>; -+ }; -+ }; -+ }; -+ }; -+ -+ mdio0: ethernet-phy { -+ compatible = "virtual,mdio-gpio"; -+ /* Uses MDC and MDIO */ -+ gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>, /* MDC */ -+ <&gpio0 21 GPIO_ACTIVE_HIGH>; /* MDIO */ -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ /* This is a Realtek RTL8211B Gigabit ethernet transceiver */ -+ phy0: ethernet-phy@1 { -+ reg = <1>; -+ device_type = "ethernet-phy"; -+ }; -+ }; -+ -+ soc { -+ flash@30000000 { -+ status = "okay"; -+ /* 512KB of flash */ -+ reg = <0x30000000 0x00080000>; -+ -+ /* -+ * This "RedBoot" is the Storlink derivative. -+ */ -+ partition@0 { -+ label = "RedBoot"; -+ reg = <0x00000000 0x00040000>; -+ read-only; -+ }; -+ partition@40000 { -+ label = "MTD1"; -+ reg = <0x00040000 0x00020000>; -+ read-only; -+ }; -+ partition@60000 { -+ label = "MTD2"; -+ reg = <0x00060000 0x00020000>; -+ read-only; -+ }; -+ }; -+ -+ syscon: syscon@40000000 { -+ pinctrl { -+ /* -+ */ -+ gpio0_default_pins: pinctrl-gpio0 { -+ mux { -+ function = "gpio0"; -+ groups = -+ /* Used by LEDs conflicts ICE */ -+ "gpio0bgrp", -+ /* Used by ? conflicts ICE */ -+ "gpio0cgrp", -+ /* -+ * Used by fan & G751, conflicts LPC, -+ * UART modem lines, SSP -+ */ -+ "gpio0egrp", -+ /* Used by G751 */ -+ "gpio0fgrp", -+ /* Used by MDIO */ -+ "gpio0igrp"; -+ }; -+ }; -+ gpio1_default_pins: pinctrl-gpio1 { -+ mux { -+ function = "gpio1"; -+ /* Used by "reset" button */ -+ groups = "gpio1dgrp"; -+ }; -+ }; -+ }; -+ }; -+ -+ sata: sata@46000000 { -+ /* The ROM uses this muxmode */ -+ cortina,gemini-ata-muxmode = <3>; -+ cortina,gemini-enable-sata-bridge; -+ status = "okay"; -+ }; -+ -+ gpio0: gpio@4d000000 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&gpio0_default_pins>; -+ }; -+ -+ gpio1: gpio@4e000000 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&gpio1_default_pins>; -+ }; -+ -+ ata@63000000 { -+ status = "okay"; -+ }; -+ }; -+}; diff --git a/target/linux/gemini/patches-4.14/0014-ARM-dts-Flags-D-Link-DIR-685-I2C-bus-gpios.patch b/target/linux/gemini/patches-4.14/0014-ARM-dts-Flags-D-Link-DIR-685-I2C-bus-gpios.patch deleted file mode 100644 index 5cefd18aa94f..000000000000 --- a/target/linux/gemini/patches-4.14/0014-ARM-dts-Flags-D-Link-DIR-685-I2C-bus-gpios.patch +++ /dev/null @@ -1,27 +0,0 @@ -From eed839dc713fdb7b2579dbfea41d676386b8259b Mon Sep 17 00:00:00 2001 -From: Linus Walleij -Date: Sun, 10 Sep 2017 20:02:33 +0200 -Subject: [PATCH 14/31] ARM: dts: Flags D-Link DIR-685 I2C bus gpios - -These GPIOs are used in open drain mode, so make sure to -flag them as such. Use the new separate scl/sda line -GPIO bindings. - -Signed-off-by: Linus Walleij ---- - arch/arm/boot/dts/gemini-dlink-dir-685.dts | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) - ---- a/arch/arm/boot/dts/gemini-dlink-dir-685.dts -+++ b/arch/arm/boot/dts/gemini-dlink-dir-685.dts -@@ -99,8 +99,8 @@ - gpio-i2c { - compatible = "i2c-gpio"; - /* Collides with ICE */ -- gpios = <&gpio0 5 0>, /* SDA */ -- <&gpio0 6 0>; /* SCL */ -+ sda-gpios = <&gpio0 5 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; -+ scl-gpios = <&gpio0 6 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; - #address-cells = <1>; - #size-cells = <0>; - diff --git a/target/linux/gemini/patches-4.14/0015-ARM-dts-Add-PCI-to-WBD111-and-WBD222.patch b/target/linux/gemini/patches-4.14/0015-ARM-dts-Add-PCI-to-WBD111-and-WBD222.patch deleted file mode 100644 index 429625ed2083..000000000000 --- a/target/linux/gemini/patches-4.14/0015-ARM-dts-Add-PCI-to-WBD111-and-WBD222.patch +++ /dev/null @@ -1,74 +0,0 @@ -From dec551d2301f71a692ed1729a323c8259d36f849 Mon Sep 17 00:00:00 2001 -From: Linus Walleij -Date: Wed, 11 Oct 2017 19:49:13 +0200 -Subject: [PATCH 15/31] ARM: dts: Add PCI to WBD111 and WBD222 - -These two boards have mini-PCI card slots, so enable PCI -on both of them. - -Signed-off-by: Linus Walleij ---- - arch/arm/boot/dts/gemini-wbd111.dts | 22 ++++++++++++++++++++++ - arch/arm/boot/dts/gemini-wbd222.dts | 22 ++++++++++++++++++++++ - 2 files changed, 44 insertions(+) - ---- a/arch/arm/boot/dts/gemini-wbd111.dts -+++ b/arch/arm/boot/dts/gemini-wbd111.dts -@@ -138,5 +138,27 @@ - pinctrl-names = "default"; - pinctrl-0 = <&gpio0_default_pins>; - }; -+ -+ pci@50000000 { -+ status = "okay"; -+ interrupt-map-mask = <0xf800 0 0 7>; -+ interrupt-map = -+ <0x4800 0 0 1 &pci_intc 0>, /* Slot 9 */ -+ <0x4800 0 0 2 &pci_intc 1>, -+ <0x4800 0 0 3 &pci_intc 2>, -+ <0x4800 0 0 4 &pci_intc 3>, -+ <0x5000 0 0 1 &pci_intc 1>, /* Slot 10 */ -+ <0x5000 0 0 2 &pci_intc 2>, -+ <0x5000 0 0 3 &pci_intc 3>, -+ <0x5000 0 0 4 &pci_intc 0>, -+ <0x5800 0 0 1 &pci_intc 2>, /* Slot 11 */ -+ <0x5800 0 0 2 &pci_intc 3>, -+ <0x5800 0 0 3 &pci_intc 0>, -+ <0x5800 0 0 4 &pci_intc 1>, -+ <0x6000 0 0 1 &pci_intc 3>, /* Slot 12 */ -+ <0x6000 0 0 2 &pci_intc 0>, -+ <0x6000 0 0 3 &pci_intc 1>, -+ <0x6000 0 0 4 &pci_intc 2>; -+ }; - }; - }; ---- a/arch/arm/boot/dts/gemini-wbd222.dts -+++ b/arch/arm/boot/dts/gemini-wbd222.dts -@@ -143,5 +143,27 @@ - pinctrl-names = "default"; - pinctrl-0 = <&gpio0_default_pins>; - }; -+ -+ pci@50000000 { -+ status = "okay"; -+ interrupt-map-mask = <0xf800 0 0 7>; -+ interrupt-map = -+ <0x4800 0 0 1 &pci_intc 0>, /* Slot 9 */ -+ <0x4800 0 0 2 &pci_intc 1>, -+ <0x4800 0 0 3 &pci_intc 2>, -+ <0x4800 0 0 4 &pci_intc 3>, -+ <0x5000 0 0 1 &pci_intc 1>, /* Slot 10 */ -+ <0x5000 0 0 2 &pci_intc 2>, -+ <0x5000 0 0 3 &pci_intc 3>, -+ <0x5000 0 0 4 &pci_intc 0>, -+ <0x5800 0 0 1 &pci_intc 2>, /* Slot 11 */ -+ <0x5800 0 0 2 &pci_intc 3>, -+ <0x5800 0 0 3 &pci_intc 0>, -+ <0x5800 0 0 4 &pci_intc 1>, -+ <0x6000 0 0 1 &pci_intc 3>, /* Slot 12 */ -+ <0x6000 0 0 2 &pci_intc 0>, -+ <0x6000 0 0 3 &pci_intc 1>, -+ <0x6000 0 0 4 &pci_intc 2>; -+ }; - }; - }; diff --git a/target/linux/gemini/patches-4.14/0016-ARM-dts-Add-TVE-TVC-and-ILI9322-panel-to-DIR-685.patch b/target/linux/gemini/patches-4.14/0016-ARM-dts-Add-TVE-TVC-and-ILI9322-panel-to-DIR-685.patch deleted file mode 100644 index b9779370ba52..000000000000 --- a/target/linux/gemini/patches-4.14/0016-ARM-dts-Add-TVE-TVC-and-ILI9322-panel-to-DIR-685.patch +++ /dev/null @@ -1,113 +0,0 @@ -From 9d3b968d13ba1eecaf22d5824cf8fd270c061534 Mon Sep 17 00:00:00 2001 -From: Linus Walleij -Date: Sat, 15 Jul 2017 21:02:06 +0200 -Subject: [PATCH 16/31] ARM: dts: Add TVE/TVC and ILI9322 panel to DIR-685 - -This adds the TVE200/TVC TV-encoder and the Ilitek ILI9322 panel -to the DIR-685 device tree. - -This brings graphics to this funky router and it is possible to -even run a console on its tiny screen. - -Incidentally this requires us to disable the access to the -parallel (NOR) flash, as the communication pins to the panel -are shared with the flash memory. - -To access the flash, a separate kernel with the panel disabled -and the flash enabled should be booted. The pin control selecting -whether to use the lines cannot be altered at runtime due to -hardware constraints. - -Cc: David Lechner -Cc: Stefano Babic -Cc: Ben Dooks -Signed-off-by: Linus Walleij ---- - arch/arm/boot/dts/gemini-dlink-dir-685.dts | 63 +++++++++++++++++++++++++++++- - 1 file changed, 62 insertions(+), 1 deletion(-) - ---- a/arch/arm/boot/dts/gemini-dlink-dir-685.dts -+++ b/arch/arm/boot/dts/gemini-dlink-dir-685.dts -@@ -45,6 +45,47 @@ - }; - }; - -+ vdisp: regulator { -+ compatible = "regulator-fixed"; -+ regulator-name = "display-power"; -+ regulator-min-microvolt = <3600000>; -+ regulator-max-microvolt = <3600000>; -+ /* Collides with LCD E */ -+ gpio = <&gpio0 16 GPIO_ACTIVE_HIGH>; -+ enable-active-high; -+ }; -+ -+ spi { -+ compatible = "spi-gpio"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ /* Collides with IDE pins, that's cool (we do not use them) */ -+ gpio-sck = <&gpio1 5 GPIO_ACTIVE_HIGH>; -+ gpio-miso = <&gpio1 8 GPIO_ACTIVE_HIGH>; -+ gpio-mosi = <&gpio1 7 GPIO_ACTIVE_HIGH>; -+ /* Collides with pflash CE1, not so cool */ -+ cs-gpios = <&gpio0 20 GPIO_ACTIVE_HIGH>; -+ num-chipselects = <1>; -+ -+ panel: display@0 { -+ compatible = "dlink,dir-685-panel", "ilitek,ili9322"; -+ reg = <0>; -+ /* 50 ns min period = 20 MHz */ -+ spi-max-frequency = <20000000>; -+ spi-cpol; /* Clock active low */ -+ vcc-supply = <&vdisp>; -+ iovcc-supply = <&vdisp>; -+ vci-supply = <&vdisp>; -+ -+ port { -+ panel_in: endpoint { -+ remote-endpoint = <&display_out>; -+ }; -+ }; -+ }; -+ }; -+ - leds { - compatible = "gpio-leds"; - led-wps { -@@ -115,7 +156,16 @@ - - soc { - flash@30000000 { -- status = "okay"; -+ /* -+ * Flash access is by default disabled, because it -+ * collides with the Chip Enable signal for the display -+ * panel, that reuse the parallel flash Chip Select 1 -+ * (CS1). Enabling flash makes graphics stop working. -+ * -+ * We might be able to hack around this by letting -+ * GPIO poke around in the flash controller registers. -+ */ -+ /* status = "okay"; */ - /* 32MB of flash */ - reg = <0x30000000 0x02000000>; - -@@ -238,5 +288,16 @@ - ata@63000000 { - status = "okay"; - }; -+ -+ display-controller@6a000000 { -+ status = "okay"; -+ -+ port@0 { -+ reg = <0>; -+ display_out: endpoint { -+ remote-endpoint = <&panel_in>; -+ }; -+ }; -+ }; - }; - }; diff --git a/target/linux/gemini/patches-4.14/0017-watchdog-gemini-ftwdt010-rename-DT-bindings.patch b/target/linux/gemini/patches-4.14/0017-watchdog-gemini-ftwdt010-rename-DT-bindings.patch deleted file mode 100644 index 3fe0b8f8ce45..000000000000 --- a/target/linux/gemini/patches-4.14/0017-watchdog-gemini-ftwdt010-rename-DT-bindings.patch +++ /dev/null @@ -1,88 +0,0 @@ -From d73f6cc09bcbe258a72c06899215d1a3e8a7686d Mon Sep 17 00:00:00 2001 -From: Linus Walleij -Date: Mon, 16 Oct 2017 22:54:23 +0200 -Subject: [PATCH 17/31] watchdog: gemini/ftwdt010: rename DT bindings - -The device tree bindings are in two copies and also should be -consolidated into a single Faraday Technology FTWDT010 -binding since we uncovered that this IP part is a standard -IP from Faraday. - -Cc: devicetree@vger.kernel.org -Acked-by: Rob Herring -Signed-off-by: Linus Walleij -Reviewed-by: Guenter Roeck -Signed-off-by: Guenter Roeck -Signed-off-by: Wim Van Sebroeck ---- - .../bindings/watchdog/cortina,gemini-watchdog.txt | 17 ----------------- - ...{cortina,gemin-watchdog.txt => faraday,ftwdt010.txt} | 11 ++++++++--- - 2 files changed, 8 insertions(+), 20 deletions(-) - delete mode 100644 Documentation/devicetree/bindings/watchdog/cortina,gemini-watchdog.txt - rename Documentation/devicetree/bindings/watchdog/{cortina,gemin-watchdog.txt => faraday,ftwdt010.txt} (55%) - ---- a/Documentation/devicetree/bindings/watchdog/cortina,gemini-watchdog.txt -+++ /dev/null -@@ -1,17 +0,0 @@ --Cortina Systems Gemini SoC Watchdog -- --Required properties: --- compatible : must be "cortina,gemini-watchdog" --- reg : shall contain base register location and length --- interrupts : shall contain the interrupt for the watchdog -- --Optional properties: --- timeout-sec : the default watchdog timeout in seconds. -- --Example: -- --watchdog@41000000 { -- compatible = "cortina,gemini-watchdog"; -- reg = <0x41000000 0x1000>; -- interrupts = <3 IRQ_TYPE_LEVEL_HIGH>; --}; ---- a/Documentation/devicetree/bindings/watchdog/cortina,gemin-watchdog.txt -+++ /dev/null -@@ -1,17 +0,0 @@ --Cortina Systems Gemini SoC Watchdog -- --Required properties: --- compatible : must be "cortina,gemini-watchdog" --- reg : shall contain base register location and length --- interrupts : shall contain the interrupt for the watchdog -- --Optional properties: --- timeout-sec : the default watchdog timeout in seconds. -- --Example: -- --watchdog@41000000 { -- compatible = "cortina,gemini-watchdog"; -- reg = <0x41000000 0x1000>; -- interrupts = <3 IRQ_TYPE_LEVEL_HIGH>; --}; ---- /dev/null -+++ b/Documentation/devicetree/bindings/watchdog/faraday,ftwdt010.txt -@@ -0,0 +1,22 @@ -+Faraday Technology FTWDT010 watchdog -+ -+This is an IP part from Faraday Technology found in the Gemini -+SoCs and others. -+ -+Required properties: -+- compatible : must be one of -+ "faraday,ftwdt010" -+ "cortina,gemini-watchdog", "faraday,ftwdt010" -+- reg : shall contain base register location and length -+- interrupts : shall contain the interrupt for the watchdog -+ -+Optional properties: -+- timeout-sec : the default watchdog timeout in seconds. -+ -+Example: -+ -+watchdog@41000000 { -+ compatible = "faraday,ftwdt010"; -+ reg = <0x41000000 0x1000>; -+ interrupts = <3 IRQ_TYPE_LEVEL_HIGH>; -+}; diff --git a/target/linux/gemini/patches-4.14/0018-watchdog-gemini-ftwdt010-rename-driver-and-symbols.patch b/target/linux/gemini/patches-4.14/0018-watchdog-gemini-ftwdt010-rename-driver-and-symbols.patch deleted file mode 100644 index 23c19893578d..000000000000 --- a/target/linux/gemini/patches-4.14/0018-watchdog-gemini-ftwdt010-rename-driver-and-symbols.patch +++ /dev/null @@ -1,527 +0,0 @@ -From c197a5a04d658da490de08636066a6bdbebf16c5 Mon Sep 17 00:00:00 2001 -From: Linus Walleij -Date: Mon, 16 Oct 2017 22:54:24 +0200 -Subject: [PATCH 18/31] watchdog: gemini/ftwdt010: rename driver and symbols - -This renames all the driver files and symbols for the Gemini -watchdog to FTWDT010 as it has been revealed that this IP block -is a generic watchdog timer from Faraday Technology used in -several SoC designs. - -Select this driver by default for the Gemini, it is a sensible -driver to always have enabled. - -Signed-off-by: Linus Walleij -Reviewed-by: Guenter Roeck -Signed-off-by: Guenter Roeck -Signed-off-by: Wim Van Sebroeck ---- - drivers/watchdog/Kconfig | 14 +-- - drivers/watchdog/Makefile | 2 +- - drivers/watchdog/{gemini_wdt.c => ftwdt010_wdt.c} | 117 +++++++++++----------- - 3 files changed, 68 insertions(+), 65 deletions(-) - rename drivers/watchdog/{gemini_wdt.c => ftwdt010_wdt.c} (50%) - ---- a/drivers/watchdog/Kconfig -+++ b/drivers/watchdog/Kconfig -@@ -321,16 +321,18 @@ config 977_WATCHDOG - - Not sure? It's safe to say N. - --config GEMINI_WATCHDOG -- tristate "Gemini watchdog" -- depends on ARCH_GEMINI -+config FTWDT010_WATCHDOG -+ tristate "Faraday Technology FTWDT010 watchdog" -+ depends on ARM || COMPILE_TEST - select WATCHDOG_CORE -+ default ARCH_GEMINI - help -- Say Y here if to include support for the watchdog timer -- embedded in the Cortina Systems Gemini family of devices. -+ Say Y here if to include support for the Faraday Technology -+ FTWDT010 watchdog timer embedded in the Cortina Systems Gemini -+ family of devices. - - To compile this driver as a module, choose M here: the -- module will be called gemini_wdt. -+ module will be called ftwdt010_wdt. - - config IXP4XX_WATCHDOG - tristate "IXP4xx Watchdog" ---- a/drivers/watchdog/Makefile -+++ b/drivers/watchdog/Makefile -@@ -46,7 +46,7 @@ obj-$(CONFIG_OMAP_WATCHDOG) += omap_wdt. - obj-$(CONFIG_TWL4030_WATCHDOG) += twl4030_wdt.o - obj-$(CONFIG_21285_WATCHDOG) += wdt285.o - obj-$(CONFIG_977_WATCHDOG) += wdt977.o --obj-$(CONFIG_GEMINI_WATCHDOG) += gemini_wdt.o -+obj-$(CONFIG_FTWDT010_WATCHDOG) += ftwdt010_wdt.o - obj-$(CONFIG_IXP4XX_WATCHDOG) += ixp4xx_wdt.o - obj-$(CONFIG_KS8695_WATCHDOG) += ks8695_wdt.o - obj-$(CONFIG_S3C2410_WATCHDOG) += s3c2410_wdt.o ---- a/drivers/watchdog/gemini_wdt.c -+++ /dev/null -@@ -1,229 +0,0 @@ --/* -- * Watchdog driver for Cortina Systems Gemini SoC -- * -- * Copyright (C) 2017 Linus Walleij -- * -- * Inspired by the out-of-tree drivers from OpenWRT: -- * Copyright (C) 2009 Paulius Zaleckas -- * -- * This program is free software; you can redistribute it and/or modify -- * it under the terms of the GNU General Public License version 2 as -- * published by the Free Software Foundation. -- */ -- --#include --#include --#include --#include --#include --#include --#include --#include --#include --#include -- --#define GEMINI_WDCOUNTER 0x0 --#define GEMINI_WDLOAD 0x4 --#define GEMINI_WDRESTART 0x8 --#define GEMINI_WDCR 0xC -- --#define WDRESTART_MAGIC 0x5AB9 -- --#define WDCR_CLOCK_5MHZ BIT(4) --#define WDCR_SYS_RST BIT(1) --#define WDCR_ENABLE BIT(0) -- --#define WDT_CLOCK 5000000 /* 5 MHz */ -- --struct gemini_wdt { -- struct watchdog_device wdd; -- struct device *dev; -- void __iomem *base; --}; -- --static inline --struct gemini_wdt *to_gemini_wdt(struct watchdog_device *wdd) --{ -- return container_of(wdd, struct gemini_wdt, wdd); --} -- --static int gemini_wdt_start(struct watchdog_device *wdd) --{ -- struct gemini_wdt *gwdt = to_gemini_wdt(wdd); -- -- writel(wdd->timeout * WDT_CLOCK, gwdt->base + GEMINI_WDLOAD); -- writel(WDRESTART_MAGIC, gwdt->base + GEMINI_WDRESTART); -- /* set clock before enabling */ -- writel(WDCR_CLOCK_5MHZ | WDCR_SYS_RST, -- gwdt->base + GEMINI_WDCR); -- writel(WDCR_CLOCK_5MHZ | WDCR_SYS_RST | WDCR_ENABLE, -- gwdt->base + GEMINI_WDCR); -- -- return 0; --} -- --static int gemini_wdt_stop(struct watchdog_device *wdd) --{ -- struct gemini_wdt *gwdt = to_gemini_wdt(wdd); -- -- writel(0, gwdt->base + GEMINI_WDCR); -- -- return 0; --} -- --static int gemini_wdt_ping(struct watchdog_device *wdd) --{ -- struct gemini_wdt *gwdt = to_gemini_wdt(wdd); -- -- writel(WDRESTART_MAGIC, gwdt->base + GEMINI_WDRESTART); -- -- return 0; --} -- --static int gemini_wdt_set_timeout(struct watchdog_device *wdd, -- unsigned int timeout) --{ -- wdd->timeout = timeout; -- if (watchdog_active(wdd)) -- gemini_wdt_start(wdd); -- -- return 0; --} -- --static irqreturn_t gemini_wdt_interrupt(int irq, void *data) --{ -- struct gemini_wdt *gwdt = data; -- -- watchdog_notify_pretimeout(&gwdt->wdd); -- -- return IRQ_HANDLED; --} -- --static const struct watchdog_ops gemini_wdt_ops = { -- .start = gemini_wdt_start, -- .stop = gemini_wdt_stop, -- .ping = gemini_wdt_ping, -- .set_timeout = gemini_wdt_set_timeout, -- .owner = THIS_MODULE, --}; -- --static const struct watchdog_info gemini_wdt_info = { -- .options = WDIOF_KEEPALIVEPING -- | WDIOF_MAGICCLOSE -- | WDIOF_SETTIMEOUT, -- .identity = KBUILD_MODNAME, --}; -- -- --static int gemini_wdt_probe(struct platform_device *pdev) --{ -- struct device *dev = &pdev->dev; -- struct resource *res; -- struct gemini_wdt *gwdt; -- unsigned int reg; -- int irq; -- int ret; -- -- gwdt = devm_kzalloc(dev, sizeof(*gwdt), GFP_KERNEL); -- if (!gwdt) -- return -ENOMEM; -- -- res = platform_get_resource(pdev, IORESOURCE_MEM, 0); -- gwdt->base = devm_ioremap_resource(dev, res); -- if (IS_ERR(gwdt->base)) -- return PTR_ERR(gwdt->base); -- -- irq = platform_get_irq(pdev, 0); -- if (!irq) -- return -EINVAL; -- -- gwdt->dev = dev; -- gwdt->wdd.info = &gemini_wdt_info; -- gwdt->wdd.ops = &gemini_wdt_ops; -- gwdt->wdd.min_timeout = 1; -- gwdt->wdd.max_timeout = 0xFFFFFFFF / WDT_CLOCK; -- gwdt->wdd.parent = dev; -- -- /* -- * If 'timeout-sec' unspecified in devicetree, assume a 13 second -- * default. -- */ -- gwdt->wdd.timeout = 13U; -- watchdog_init_timeout(&gwdt->wdd, 0, dev); -- -- reg = readw(gwdt->base + GEMINI_WDCR); -- if (reg & WDCR_ENABLE) { -- /* Watchdog was enabled by the bootloader, disable it. */ -- reg &= ~WDCR_ENABLE; -- writel(reg, gwdt->base + GEMINI_WDCR); -- } -- -- ret = devm_request_irq(dev, irq, gemini_wdt_interrupt, 0, -- "watchdog bark", gwdt); -- if (ret) -- return ret; -- -- ret = devm_watchdog_register_device(dev, &gwdt->wdd); -- if (ret) { -- dev_err(&pdev->dev, "failed to register watchdog\n"); -- return ret; -- } -- -- /* Set up platform driver data */ -- platform_set_drvdata(pdev, gwdt); -- dev_info(dev, "Gemini watchdog driver enabled\n"); -- -- return 0; --} -- --static int __maybe_unused gemini_wdt_suspend(struct device *dev) --{ -- struct gemini_wdt *gwdt = dev_get_drvdata(dev); -- unsigned int reg; -- -- reg = readw(gwdt->base + GEMINI_WDCR); -- reg &= ~WDCR_ENABLE; -- writel(reg, gwdt->base + GEMINI_WDCR); -- -- return 0; --} -- --static int __maybe_unused gemini_wdt_resume(struct device *dev) --{ -- struct gemini_wdt *gwdt = dev_get_drvdata(dev); -- unsigned int reg; -- -- if (watchdog_active(&gwdt->wdd)) { -- reg = readw(gwdt->base + GEMINI_WDCR); -- reg |= WDCR_ENABLE; -- writel(reg, gwdt->base + GEMINI_WDCR); -- } -- -- return 0; --} -- --static const struct dev_pm_ops gemini_wdt_dev_pm_ops = { -- SET_SYSTEM_SLEEP_PM_OPS(gemini_wdt_suspend, -- gemini_wdt_resume) --}; -- --#ifdef CONFIG_OF --static const struct of_device_id gemini_wdt_match[] = { -- { .compatible = "cortina,gemini-watchdog" }, -- {}, --}; --MODULE_DEVICE_TABLE(of, gemini_wdt_match); --#endif -- --static struct platform_driver gemini_wdt_driver = { -- .probe = gemini_wdt_probe, -- .driver = { -- .name = "gemini-wdt", -- .of_match_table = of_match_ptr(gemini_wdt_match), -- .pm = &gemini_wdt_dev_pm_ops, -- }, --}; --module_platform_driver(gemini_wdt_driver); --MODULE_AUTHOR("Linus Walleij"); --MODULE_DESCRIPTION("Watchdog driver for Gemini"); --MODULE_LICENSE("GPL"); ---- /dev/null -+++ b/drivers/watchdog/ftwdt010_wdt.c -@@ -0,0 +1,230 @@ -+/* -+ * Watchdog driver for Faraday Technology FTWDT010 -+ * -+ * Copyright (C) 2017 Linus Walleij -+ * -+ * Inspired by the out-of-tree drivers from OpenWRT: -+ * Copyright (C) 2009 Paulius Zaleckas -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#define FTWDT010_WDCOUNTER 0x0 -+#define FTWDT010_WDLOAD 0x4 -+#define FTWDT010_WDRESTART 0x8 -+#define FTWDT010_WDCR 0xC -+ -+#define WDRESTART_MAGIC 0x5AB9 -+ -+#define WDCR_CLOCK_5MHZ BIT(4) -+#define WDCR_SYS_RST BIT(1) -+#define WDCR_ENABLE BIT(0) -+ -+#define WDT_CLOCK 5000000 /* 5 MHz */ -+ -+struct ftwdt010_wdt { -+ struct watchdog_device wdd; -+ struct device *dev; -+ void __iomem *base; -+}; -+ -+static inline -+struct ftwdt010_wdt *to_ftwdt010_wdt(struct watchdog_device *wdd) -+{ -+ return container_of(wdd, struct ftwdt010_wdt, wdd); -+} -+ -+static int ftwdt010_wdt_start(struct watchdog_device *wdd) -+{ -+ struct ftwdt010_wdt *gwdt = to_ftwdt010_wdt(wdd); -+ -+ writel(wdd->timeout * WDT_CLOCK, gwdt->base + FTWDT010_WDLOAD); -+ writel(WDRESTART_MAGIC, gwdt->base + FTWDT010_WDRESTART); -+ /* set clock before enabling */ -+ writel(WDCR_CLOCK_5MHZ | WDCR_SYS_RST, -+ gwdt->base + FTWDT010_WDCR); -+ writel(WDCR_CLOCK_5MHZ | WDCR_SYS_RST | WDCR_ENABLE, -+ gwdt->base + FTWDT010_WDCR); -+ -+ return 0; -+} -+ -+static int ftwdt010_wdt_stop(struct watchdog_device *wdd) -+{ -+ struct ftwdt010_wdt *gwdt = to_ftwdt010_wdt(wdd); -+ -+ writel(0, gwdt->base + FTWDT010_WDCR); -+ -+ return 0; -+} -+ -+static int ftwdt010_wdt_ping(struct watchdog_device *wdd) -+{ -+ struct ftwdt010_wdt *gwdt = to_ftwdt010_wdt(wdd); -+ -+ writel(WDRESTART_MAGIC, gwdt->base + FTWDT010_WDRESTART); -+ -+ return 0; -+} -+ -+static int ftwdt010_wdt_set_timeout(struct watchdog_device *wdd, -+ unsigned int timeout) -+{ -+ wdd->timeout = timeout; -+ if (watchdog_active(wdd)) -+ ftwdt010_wdt_start(wdd); -+ -+ return 0; -+} -+ -+static irqreturn_t ftwdt010_wdt_interrupt(int irq, void *data) -+{ -+ struct ftwdt010_wdt *gwdt = data; -+ -+ watchdog_notify_pretimeout(&gwdt->wdd); -+ -+ return IRQ_HANDLED; -+} -+ -+static const struct watchdog_ops ftwdt010_wdt_ops = { -+ .start = ftwdt010_wdt_start, -+ .stop = ftwdt010_wdt_stop, -+ .ping = ftwdt010_wdt_ping, -+ .set_timeout = ftwdt010_wdt_set_timeout, -+ .owner = THIS_MODULE, -+}; -+ -+static const struct watchdog_info ftwdt010_wdt_info = { -+ .options = WDIOF_KEEPALIVEPING -+ | WDIOF_MAGICCLOSE -+ | WDIOF_SETTIMEOUT, -+ .identity = KBUILD_MODNAME, -+}; -+ -+ -+static int ftwdt010_wdt_probe(struct platform_device *pdev) -+{ -+ struct device *dev = &pdev->dev; -+ struct resource *res; -+ struct ftwdt010_wdt *gwdt; -+ unsigned int reg; -+ int irq; -+ int ret; -+ -+ gwdt = devm_kzalloc(dev, sizeof(*gwdt), GFP_KERNEL); -+ if (!gwdt) -+ return -ENOMEM; -+ -+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); -+ gwdt->base = devm_ioremap_resource(dev, res); -+ if (IS_ERR(gwdt->base)) -+ return PTR_ERR(gwdt->base); -+ -+ irq = platform_get_irq(pdev, 0); -+ if (!irq) -+ return -EINVAL; -+ -+ gwdt->dev = dev; -+ gwdt->wdd.info = &ftwdt010_wdt_info; -+ gwdt->wdd.ops = &ftwdt010_wdt_ops; -+ gwdt->wdd.min_timeout = 1; -+ gwdt->wdd.max_timeout = 0xFFFFFFFF / WDT_CLOCK; -+ gwdt->wdd.parent = dev; -+ -+ /* -+ * If 'timeout-sec' unspecified in devicetree, assume a 13 second -+ * default. -+ */ -+ gwdt->wdd.timeout = 13U; -+ watchdog_init_timeout(&gwdt->wdd, 0, dev); -+ -+ reg = readw(gwdt->base + FTWDT010_WDCR); -+ if (reg & WDCR_ENABLE) { -+ /* Watchdog was enabled by the bootloader, disable it. */ -+ reg &= ~WDCR_ENABLE; -+ writel(reg, gwdt->base + FTWDT010_WDCR); -+ } -+ -+ ret = devm_request_irq(dev, irq, ftwdt010_wdt_interrupt, 0, -+ "watchdog bark", gwdt); -+ if (ret) -+ return ret; -+ -+ ret = devm_watchdog_register_device(dev, &gwdt->wdd); -+ if (ret) { -+ dev_err(&pdev->dev, "failed to register watchdog\n"); -+ return ret; -+ } -+ -+ /* Set up platform driver data */ -+ platform_set_drvdata(pdev, gwdt); -+ dev_info(dev, "FTWDT010 watchdog driver enabled\n"); -+ -+ return 0; -+} -+ -+static int __maybe_unused ftwdt010_wdt_suspend(struct device *dev) -+{ -+ struct ftwdt010_wdt *gwdt = dev_get_drvdata(dev); -+ unsigned int reg; -+ -+ reg = readw(gwdt->base + FTWDT010_WDCR); -+ reg &= ~WDCR_ENABLE; -+ writel(reg, gwdt->base + FTWDT010_WDCR); -+ -+ return 0; -+} -+ -+static int __maybe_unused ftwdt010_wdt_resume(struct device *dev) -+{ -+ struct ftwdt010_wdt *gwdt = dev_get_drvdata(dev); -+ unsigned int reg; -+ -+ if (watchdog_active(&gwdt->wdd)) { -+ reg = readw(gwdt->base + FTWDT010_WDCR); -+ reg |= WDCR_ENABLE; -+ writel(reg, gwdt->base + FTWDT010_WDCR); -+ } -+ -+ return 0; -+} -+ -+static const struct dev_pm_ops ftwdt010_wdt_dev_pm_ops = { -+ SET_SYSTEM_SLEEP_PM_OPS(ftwdt010_wdt_suspend, -+ ftwdt010_wdt_resume) -+}; -+ -+#ifdef CONFIG_OF -+static const struct of_device_id ftwdt010_wdt_match[] = { -+ { .compatible = "faraday,ftwdt010" }, -+ { .compatible = "cortina,gemini-watchdog" }, -+ {}, -+}; -+MODULE_DEVICE_TABLE(of, ftwdt010_wdt_match); -+#endif -+ -+static struct platform_driver ftwdt010_wdt_driver = { -+ .probe = ftwdt010_wdt_probe, -+ .driver = { -+ .name = "ftwdt010-wdt", -+ .of_match_table = of_match_ptr(ftwdt010_wdt_match), -+ .pm = &ftwdt010_wdt_dev_pm_ops, -+ }, -+}; -+module_platform_driver(ftwdt010_wdt_driver); -+MODULE_AUTHOR("Linus Walleij"); -+MODULE_DESCRIPTION("Watchdog driver for Faraday Technology FTWDT010"); -+MODULE_LICENSE("GPL"); diff --git a/target/linux/gemini/patches-4.14/0019-watchdog-ftwdt010-Make-interrupt-optional.patch b/target/linux/gemini/patches-4.14/0019-watchdog-ftwdt010-Make-interrupt-optional.patch deleted file mode 100644 index 23c4ab5c0d67..000000000000 --- a/target/linux/gemini/patches-4.14/0019-watchdog-ftwdt010-Make-interrupt-optional.patch +++ /dev/null @@ -1,93 +0,0 @@ -From 4347a0b0699989b889857c9d4ccfbce339859f13 Mon Sep 17 00:00:00 2001 -From: Linus Walleij -Date: Mon, 16 Oct 2017 22:54:25 +0200 -Subject: [PATCH 19/31] watchdog: ftwdt010: Make interrupt optional - -The Moxart does not appear to be using the interrupt from the -watchdog timer, maybe it's not even routed, so as to support -more architectures with this driver, make the interrupt -optional. - -While we are at it: actually enable the use of the interrupt -if present by setting the right bit in the control register -and define the missing control register bits. - -Signed-off-by: Linus Walleij -Reviewed-by: Guenter Roeck -Signed-off-by: Guenter Roeck -Signed-off-by: Wim Van Sebroeck ---- - drivers/watchdog/ftwdt010_wdt.c | 30 ++++++++++++++++++------------ - 1 file changed, 18 insertions(+), 12 deletions(-) - ---- a/drivers/watchdog/ftwdt010_wdt.c -+++ b/drivers/watchdog/ftwdt010_wdt.c -@@ -30,6 +30,8 @@ - #define WDRESTART_MAGIC 0x5AB9 - - #define WDCR_CLOCK_5MHZ BIT(4) -+#define WDCR_WDEXT BIT(3) -+#define WDCR_WDINTR BIT(2) - #define WDCR_SYS_RST BIT(1) - #define WDCR_ENABLE BIT(0) - -@@ -39,6 +41,7 @@ struct ftwdt010_wdt { - struct watchdog_device wdd; - struct device *dev; - void __iomem *base; -+ bool has_irq; - }; - - static inline -@@ -50,14 +53,17 @@ struct ftwdt010_wdt *to_ftwdt010_wdt(str - static int ftwdt010_wdt_start(struct watchdog_device *wdd) - { - struct ftwdt010_wdt *gwdt = to_ftwdt010_wdt(wdd); -+ u32 enable; - - writel(wdd->timeout * WDT_CLOCK, gwdt->base + FTWDT010_WDLOAD); - writel(WDRESTART_MAGIC, gwdt->base + FTWDT010_WDRESTART); - /* set clock before enabling */ -- writel(WDCR_CLOCK_5MHZ | WDCR_SYS_RST, -- gwdt->base + FTWDT010_WDCR); -- writel(WDCR_CLOCK_5MHZ | WDCR_SYS_RST | WDCR_ENABLE, -- gwdt->base + FTWDT010_WDCR); -+ enable = WDCR_CLOCK_5MHZ | WDCR_SYS_RST; -+ writel(enable, gwdt->base + FTWDT010_WDCR); -+ if (gwdt->has_irq) -+ enable |= WDCR_WDINTR; -+ enable |= WDCR_ENABLE; -+ writel(enable, gwdt->base + FTWDT010_WDCR); - - return 0; - } -@@ -133,10 +139,6 @@ static int ftwdt010_wdt_probe(struct pla - if (IS_ERR(gwdt->base)) - return PTR_ERR(gwdt->base); - -- irq = platform_get_irq(pdev, 0); -- if (!irq) -- return -EINVAL; -- - gwdt->dev = dev; - gwdt->wdd.info = &ftwdt010_wdt_info; - gwdt->wdd.ops = &ftwdt010_wdt_ops; -@@ -158,10 +160,14 @@ static int ftwdt010_wdt_probe(struct pla - writel(reg, gwdt->base + FTWDT010_WDCR); - } - -- ret = devm_request_irq(dev, irq, ftwdt010_wdt_interrupt, 0, -- "watchdog bark", gwdt); -- if (ret) -- return ret; -+ irq = platform_get_irq(pdev, 0); -+ if (irq) { -+ ret = devm_request_irq(dev, irq, ftwdt010_wdt_interrupt, 0, -+ "watchdog bark", gwdt); -+ if (ret) -+ return ret; -+ gwdt->has_irq = true; -+ } - - ret = devm_watchdog_register_device(dev, &gwdt->wdd); - if (ret) { diff --git a/target/linux/gemini/patches-4.14/0020-soc-Add-SoC-driver-for-Gemini.patch b/target/linux/gemini/patches-4.14/0020-soc-Add-SoC-driver-for-Gemini.patch deleted file mode 100644 index f1bbe0a15ff5..000000000000 --- a/target/linux/gemini/patches-4.14/0020-soc-Add-SoC-driver-for-Gemini.patch +++ /dev/null @@ -1,113 +0,0 @@ -From b0a88a861b036124ef2d6acfe6dd87cfde63e750 Mon Sep 17 00:00:00 2001 -From: Linus Walleij -Date: Fri, 22 Dec 2017 00:19:08 +0100 -Subject: [PATCH 20/31] soc: Add SoC driver for Gemini - -This adds an SoC driver for the Gemini. Currently there -is only one thing not fitting into any other framework, -and that is the bus arbitration setting. - -All Gemini vendor trees seem to be setting this register to -exactly the same arbitration so we just add a small code -snippet to do this at subsys_init() time before any other -drivers kick in. - -Signed-off-by: Linus Walleij -Signed-off-by: Arnd Bergmann ---- - drivers/soc/Makefile | 1 + - drivers/soc/gemini/Makefile | 2 ++ - drivers/soc/gemini/soc-gemini.c | 71 +++++++++++++++++++++++++++++++++++++++++ - 3 files changed, 74 insertions(+) - create mode 100644 drivers/soc/gemini/Makefile - create mode 100644 drivers/soc/gemini/soc-gemini.c - ---- a/drivers/soc/Makefile -+++ b/drivers/soc/Makefile -@@ -9,6 +9,7 @@ obj-y += bcm/ - obj-$(CONFIG_ARCH_DOVE) += dove/ - obj-$(CONFIG_MACH_DOVE) += dove/ - obj-y += fsl/ -+obj-$(CONFIG_ARCH_GEMINI) += gemini/ - obj-$(CONFIG_ARCH_MXC) += imx/ - obj-$(CONFIG_SOC_XWAY) += lantiq/ - obj-$(CONFIG_ARCH_MEDIATEK) += mediatek/ ---- /dev/null -+++ b/drivers/soc/gemini/Makefile -@@ -0,0 +1,2 @@ -+# SPDX-License-Identifier: GPL-2.0 -+obj-y += soc-gemini.o ---- /dev/null -+++ b/drivers/soc/gemini/soc-gemini.c -@@ -0,0 +1,71 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * Copyright (C) 2017 Linaro Ltd. -+ * -+ * Author: Linus Walleij -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2, as -+ * published by the Free Software Foundation. -+ * -+ */ -+#include -+#include -+#include -+#include -+#include -+ -+#define GLOBAL_WORD_ID 0x00 -+#define GEMINI_GLOBAL_ARB1_CTRL 0x2c -+#define GEMINI_ARB1_BURST_MASK GENMASK(21, 16) -+#define GEMINI_ARB1_BURST_SHIFT 16 -+/* These all define the priority on the BUS2 backplane */ -+#define GEMINI_ARB1_PRIO_MASK GENMASK(9, 0) -+#define GEMINI_ARB1_DMAC_HIGH_PRIO BIT(0) -+#define GEMINI_ARB1_IDE_HIGH_PRIO BIT(1) -+#define GEMINI_ARB1_RAID_HIGH_PRIO BIT(2) -+#define GEMINI_ARB1_SECURITY_HIGH_PRIO BIT(3) -+#define GEMINI_ARB1_GMAC0_HIGH_PRIO BIT(4) -+#define GEMINI_ARB1_GMAC1_HIGH_PRIO BIT(5) -+#define GEMINI_ARB1_USB0_HIGH_PRIO BIT(6) -+#define GEMINI_ARB1_USB1_HIGH_PRIO BIT(7) -+#define GEMINI_ARB1_PCI_HIGH_PRIO BIT(8) -+#define GEMINI_ARB1_TVE_HIGH_PRIO BIT(9) -+ -+#define GEMINI_DEFAULT_BURST_SIZE 0x20 -+#define GEMINI_DEFAULT_PRIO (GEMINI_ARB1_GMAC0_HIGH_PRIO | \ -+ GEMINI_ARB1_GMAC1_HIGH_PRIO) -+ -+static int __init gemini_soc_init(void) -+{ -+ struct regmap *map; -+ u32 rev; -+ u32 val; -+ int ret; -+ -+ /* Multiplatform guard, only proceed on Gemini */ -+ if (!of_machine_is_compatible("cortina,gemini")) -+ return 0; -+ -+ map = syscon_regmap_lookup_by_compatible("cortina,gemini-syscon"); -+ if (IS_ERR(map)) -+ return PTR_ERR(map); -+ ret = regmap_read(map, GLOBAL_WORD_ID, &rev); -+ if (ret) -+ return ret; -+ -+ val = (GEMINI_DEFAULT_BURST_SIZE << GEMINI_ARB1_BURST_SHIFT) | -+ GEMINI_DEFAULT_PRIO; -+ -+ /* Set up system arbitration */ -+ regmap_update_bits(map, -+ GEMINI_GLOBAL_ARB1_CTRL, -+ GEMINI_ARB1_BURST_MASK | GEMINI_ARB1_PRIO_MASK, -+ val); -+ -+ pr_info("Gemini SoC %04x revision %02x, set arbitration %08x\n", -+ rev >> 8, rev & 0xff, val); -+ -+ return 0; -+} -+subsys_initcall(gemini_soc_init); diff --git a/target/linux/gemini/patches-4.14/0021-net-ethernet-Add-DT-bindings-for-the-Gemini-ethernet.patch b/target/linux/gemini/patches-4.14/0021-net-ethernet-Add-DT-bindings-for-the-Gemini-ethernet.patch deleted file mode 100644 index 19653d5ad1ae..000000000000 --- a/target/linux/gemini/patches-4.14/0021-net-ethernet-Add-DT-bindings-for-the-Gemini-ethernet.patch +++ /dev/null @@ -1,119 +0,0 @@ -From 49bc597009f52ec8970269f6201d3ed415a844ee Mon Sep 17 00:00:00 2001 -From: Linus Walleij -Date: Fri, 12 Jan 2018 22:34:23 +0100 -Subject: [PATCH 21/31] net: ethernet: Add DT bindings for the Gemini ethernet -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -This adds the device tree bindings for the Gemini ethernet -controller. It is pretty straight-forward, using standard -bindings and modelling the two child ports as child devices -under the parent ethernet controller device. - -Cc: devicetree@vger.kernel.org -Cc: Tobias Waldvogel -Cc: MichaÅ‚ MirosÅ‚aw -Reviewed-by: Rob Herring -Signed-off-by: Linus Walleij -Signed-off-by: David S. Miller ---- - .../bindings/net/cortina,gemini-ethernet.txt | 92 ++++++++++++++++++++++ - 1 file changed, 92 insertions(+) - create mode 100644 Documentation/devicetree/bindings/net/cortina,gemini-ethernet.txt - ---- /dev/null -+++ b/Documentation/devicetree/bindings/net/cortina,gemini-ethernet.txt -@@ -0,0 +1,92 @@ -+Cortina Systems Gemini Ethernet Controller -+========================================== -+ -+This ethernet controller is found in the Gemini SoC family: -+StorLink SL3512 and SL3516, also known as Cortina Systems -+CS3512 and CS3516. -+ -+Required properties: -+- compatible: must be "cortina,gemini-ethernet" -+- reg: must contain the global registers and the V-bit and A-bit -+ memory areas, in total three register sets. -+- syscon: a phandle to the system controller -+- #address-cells: must be specified, must be <1> -+- #size-cells: must be specified, must be <1> -+- ranges: should be state like this giving a 1:1 address translation -+ for the subnodes -+ -+The subnodes represents the two ethernet ports in this device. -+They are not independent of each other since they share resources -+in the parent node, and are thus children. -+ -+Required subnodes: -+- port0: contains the resources for ethernet port 0 -+- port1: contains the resources for ethernet port 1 -+ -+Required subnode properties: -+- compatible: must be "cortina,gemini-ethernet-port" -+- reg: must contain two register areas: the DMA/TOE memory and -+ the GMAC memory area of the port -+- interrupts: should contain the interrupt line of the port. -+ this is nominally a level interrupt active high. -+- resets: this must provide an SoC-integrated reset line for -+ the port. -+- clocks: this should contain a handle to the PCLK clock for -+ clocking the silicon in this port -+- clock-names: must be "PCLK" -+ -+Optional subnode properties: -+- phy-mode: see ethernet.txt -+- phy-handle: see ethernet.txt -+ -+Example: -+ -+mdio-bus { -+ (...) -+ phy0: ethernet-phy@1 { -+ reg = <1>; -+ device_type = "ethernet-phy"; -+ }; -+ phy1: ethernet-phy@3 { -+ reg = <3>; -+ device_type = "ethernet-phy"; -+ }; -+}; -+ -+ -+ethernet@60000000 { -+ compatible = "cortina,gemini-ethernet"; -+ reg = <0x60000000 0x4000>, /* Global registers, queue */ -+ <0x60004000 0x2000>, /* V-bit */ -+ <0x60006000 0x2000>; /* A-bit */ -+ syscon = <&syscon>; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges; -+ -+ gmac0: ethernet-port@0 { -+ compatible = "cortina,gemini-ethernet-port"; -+ reg = <0x60008000 0x2000>, /* Port 0 DMA/TOE */ -+ <0x6000a000 0x2000>; /* Port 0 GMAC */ -+ interrupt-parent = <&intcon>; -+ interrupts = <1 IRQ_TYPE_LEVEL_HIGH>; -+ resets = <&syscon GEMINI_RESET_GMAC0>; -+ clocks = <&syscon GEMINI_CLK_GATE_GMAC0>; -+ clock-names = "PCLK"; -+ phy-mode = "rgmii"; -+ phy-handle = <&phy0>; -+ }; -+ -+ gmac1: ethernet-port@1 { -+ compatible = "cortina,gemini-ethernet-port"; -+ reg = <0x6000c000 0x2000>, /* Port 1 DMA/TOE */ -+ <0x6000e000 0x2000>; /* Port 1 GMAC */ -+ interrupt-parent = <&intcon>; -+ interrupts = <2 IRQ_TYPE_LEVEL_HIGH>; -+ resets = <&syscon GEMINI_RESET_GMAC1>; -+ clocks = <&syscon GEMINI_CLK_GATE_GMAC1>; -+ clock-names = "PCLK"; -+ phy-mode = "rgmii"; -+ phy-handle = <&phy1>; -+ }; -+}; diff --git a/target/linux/gemini/patches-4.14/0022-net-ethernet-Add-a-driver-for-Gemini-gigabit-etherne.patch b/target/linux/gemini/patches-4.14/0022-net-ethernet-Add-a-driver-for-Gemini-gigabit-etherne.patch deleted file mode 100644 index bad9bfa34e4c..000000000000 --- a/target/linux/gemini/patches-4.14/0022-net-ethernet-Add-a-driver-for-Gemini-gigabit-etherne.patch +++ /dev/null @@ -1,3661 +0,0 @@ -From 07826b86d4ce4d35fd1674d7f78e4b2060ab2910 Mon Sep 17 00:00:00 2001 -From: Linus Walleij -Date: Fri, 12 Jan 2018 22:34:24 +0100 -Subject: [PATCH 22/31] net: ethernet: Add a driver for Gemini gigabit ethernet -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -The Gemini ethernet has been around for years as an out-of-tree -patch used with the NAS boxen and routers built on StorLink -SL3512 and SL3516, later Storm Semiconductor, later Cortina -Systems. These ASICs are still being deployed and brand new -off-the-shelf systems using it can easily be acquired. - -The full name of the IP block is "Net Engine and Gigabit -Ethernet MAC" commonly just called "GMAC". - -The hardware block contains a common TCP Offload Enginer (TOE) -that can be used by both MACs. The current driver does not use -it. - -Cc: Tobias Waldvogel -Signed-off-by: MichaÅ‚ MirosÅ‚aw -Signed-off-by: Linus Walleij -Signed-off-by: David S. Miller ---- - MAINTAINERS | 2 + - drivers/net/ethernet/Kconfig | 1 + - drivers/net/ethernet/Makefile | 1 + - drivers/net/ethernet/cortina/Kconfig | 22 + - drivers/net/ethernet/cortina/Makefile | 4 + - drivers/net/ethernet/cortina/gemini.c | 2593 +++++++++++++++++++++++++++++++++ - drivers/net/ethernet/cortina/gemini.h | 958 ++++++++++++ - 7 files changed, 3581 insertions(+) - create mode 100644 drivers/net/ethernet/cortina/Kconfig - create mode 100644 drivers/net/ethernet/cortina/Makefile - create mode 100644 drivers/net/ethernet/cortina/gemini.c - create mode 100644 drivers/net/ethernet/cortina/gemini.h - ---- a/MAINTAINERS -+++ b/MAINTAINERS -@@ -1327,8 +1327,10 @@ T: git git://github.com/ulli-kroll/linux - S: Maintained - F: Documentation/devicetree/bindings/arm/gemini.txt - F: Documentation/devicetree/bindings/pinctrl/cortina,gemini-pinctrl.txt -+F: Documentation/devicetree/bindings/net/cortina,gemini-ethernet.txt - F: Documentation/devicetree/bindings/rtc/faraday,ftrtc010.txt - F: arch/arm/mach-gemini/ -+F: drivers/net/ethernet/cortina/gemini/* - F: drivers/pinctrl/pinctrl-gemini.c - F: drivers/rtc/rtc-ftrtc010.c - ---- a/drivers/net/ethernet/Kconfig -+++ b/drivers/net/ethernet/Kconfig -@@ -42,6 +42,7 @@ source "drivers/net/ethernet/cavium/Kcon - source "drivers/net/ethernet/chelsio/Kconfig" - source "drivers/net/ethernet/cirrus/Kconfig" - source "drivers/net/ethernet/cisco/Kconfig" -+source "drivers/net/ethernet/cortina/Kconfig" - - config CX_ECAT - tristate "Beckhoff CX5020 EtherCAT master support" ---- a/drivers/net/ethernet/Makefile -+++ b/drivers/net/ethernet/Makefile -@@ -29,6 +29,7 @@ obj-$(CONFIG_NET_VENDOR_CAVIUM) += caviu - obj-$(CONFIG_NET_VENDOR_CHELSIO) += chelsio/ - obj-$(CONFIG_NET_VENDOR_CIRRUS) += cirrus/ - obj-$(CONFIG_NET_VENDOR_CISCO) += cisco/ -+obj-$(CONFIG_NET_VENDOR_CORTINA) += cortina/ - obj-$(CONFIG_CX_ECAT) += ec_bhf.o - obj-$(CONFIG_DM9000) += davicom/ - obj-$(CONFIG_DNET) += dnet.o ---- /dev/null -+++ b/drivers/net/ethernet/cortina/Kconfig -@@ -0,0 +1,22 @@ -+# SPDX-License-Identifier: GPL-2.0 -+# Cortina ethernet devices -+ -+config NET_VENDOR_CORTINA -+ bool "Cortina Gemini devices" -+ default y -+ ---help--- -+ If you have a network (Ethernet) card belonging to this class, say Y -+ and read the Ethernet-HOWTO, available from -+ . -+ -+if NET_VENDOR_CORTINA -+ -+config GEMINI_ETHERNET -+ tristate "Gemini Gigabit Ethernet support" -+ depends on OF -+ select PHYLIB -+ select CRC32 -+ ---help--- -+ This driver supports StorLink SL351x (Gemini) dual Gigabit Ethernet. -+ -+endif # NET_VENDOR_CORTINA ---- /dev/null -+++ b/drivers/net/ethernet/cortina/Makefile -@@ -0,0 +1,4 @@ -+# SPDX-License-Identifier: GPL-2.0 -+# Makefile for the Cortina Gemini network device drivers. -+ -+obj-$(CONFIG_GEMINI_ETHERNET) += gemini.o ---- /dev/null -+++ b/drivers/net/ethernet/cortina/gemini.c -@@ -0,0 +1,2593 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* Ethernet device driver for Cortina Systems Gemini SoC -+ * Also known as the StorLink SL3512 and SL3516 (SL351x) or Lepus -+ * Net Engine and Gigabit Ethernet MAC (GMAC) -+ * This hardware contains a TCP Offload Engine (TOE) but currently the -+ * driver does not make use of it. -+ * -+ * Authors: -+ * Linus Walleij -+ * Tobias Waldvogel (OpenWRT) -+ * MichaÅ‚ MirosÅ‚aw -+ * Paulius Zaleckas -+ * Giuseppe De Robertis -+ * Gary Chen & Ch Hsu Storlink Semiconductor -+ */ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+#include -+ -+#include "gemini.h" -+ -+#define DRV_NAME "gmac-gemini" -+#define DRV_VERSION "1.0" -+ -+#define HSIZE_8 0x00 -+#define HSIZE_16 0x01 -+#define HSIZE_32 0x02 -+ -+#define HBURST_SINGLE 0x00 -+#define HBURST_INCR 0x01 -+#define HBURST_INCR4 0x02 -+#define HBURST_INCR8 0x03 -+ -+#define HPROT_DATA_CACHE BIT(0) -+#define HPROT_PRIVILIGED BIT(1) -+#define HPROT_BUFFERABLE BIT(2) -+#define HPROT_CACHABLE BIT(3) -+ -+#define DEFAULT_RX_COALESCE_NSECS 0 -+#define DEFAULT_GMAC_RXQ_ORDER 9 -+#define DEFAULT_GMAC_TXQ_ORDER 8 -+#define DEFAULT_RX_BUF_ORDER 11 -+#define DEFAULT_NAPI_WEIGHT 64 -+#define TX_MAX_FRAGS 16 -+#define TX_QUEUE_NUM 1 /* max: 6 */ -+#define RX_MAX_ALLOC_ORDER 2 -+ -+#define GMAC0_IRQ0_2 (GMAC0_TXDERR_INT_BIT | GMAC0_TXPERR_INT_BIT | \ -+ GMAC0_RXDERR_INT_BIT | GMAC0_RXPERR_INT_BIT) -+#define GMAC0_IRQ0_TXQ0_INTS (GMAC0_SWTQ00_EOF_INT_BIT | \ -+ GMAC0_SWTQ00_FIN_INT_BIT) -+#define GMAC0_IRQ4_8 (GMAC0_MIB_INT_BIT | GMAC0_RX_OVERRUN_INT_BIT) -+ -+#define GMAC_OFFLOAD_FEATURES (NETIF_F_SG | NETIF_F_IP_CSUM | \ -+ NETIF_F_IPV6_CSUM | NETIF_F_RXCSUM | \ -+ NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6) -+ -+/** -+ * struct gmac_queue_page - page buffer per-page info -+ */ -+struct gmac_queue_page { -+ struct page *page; -+ dma_addr_t mapping; -+}; -+ -+struct gmac_txq { -+ struct gmac_txdesc *ring; -+ struct sk_buff **skb; -+ unsigned int cptr; -+ unsigned int noirq_packets; -+}; -+ -+struct gemini_ethernet; -+ -+struct gemini_ethernet_port { -+ u8 id; /* 0 or 1 */ -+ -+ struct gemini_ethernet *geth; -+ struct net_device *netdev; -+ struct device *dev; -+ void __iomem *dma_base; -+ void __iomem *gmac_base; -+ struct clk *pclk; -+ struct reset_control *reset; -+ int irq; -+ __le32 mac_addr[3]; -+ -+ void __iomem *rxq_rwptr; -+ struct gmac_rxdesc *rxq_ring; -+ unsigned int rxq_order; -+ -+ struct napi_struct napi; -+ struct hrtimer rx_coalesce_timer; -+ unsigned int rx_coalesce_nsecs; -+ unsigned int freeq_refill; -+ struct gmac_txq txq[TX_QUEUE_NUM]; -+ unsigned int txq_order; -+ unsigned int irq_every_tx_packets; -+ -+ dma_addr_t rxq_dma_base; -+ dma_addr_t txq_dma_base; -+ -+ unsigned int msg_enable; -+ spinlock_t config_lock; /* Locks config register */ -+ -+ struct u64_stats_sync tx_stats_syncp; -+ struct u64_stats_sync rx_stats_syncp; -+ struct u64_stats_sync ir_stats_syncp; -+ -+ struct rtnl_link_stats64 stats; -+ u64 hw_stats[RX_STATS_NUM]; -+ u64 rx_stats[RX_STATUS_NUM]; -+ u64 rx_csum_stats[RX_CHKSUM_NUM]; -+ u64 rx_napi_exits; -+ u64 tx_frag_stats[TX_MAX_FRAGS]; -+ u64 tx_frags_linearized; -+ u64 tx_hw_csummed; -+}; -+ -+struct gemini_ethernet { -+ struct device *dev; -+ void __iomem *base; -+ struct gemini_ethernet_port *port0; -+ struct gemini_ethernet_port *port1; -+ -+ spinlock_t irq_lock; /* Locks IRQ-related registers */ -+ unsigned int freeq_order; -+ unsigned int freeq_frag_order; -+ struct gmac_rxdesc *freeq_ring; -+ dma_addr_t freeq_dma_base; -+ struct gmac_queue_page *freeq_pages; -+ unsigned int num_freeq_pages; -+ spinlock_t freeq_lock; /* Locks queue from reentrance */ -+}; -+ -+#define GMAC_STATS_NUM ( \ -+ RX_STATS_NUM + RX_STATUS_NUM + RX_CHKSUM_NUM + 1 + \ -+ TX_MAX_FRAGS + 2) -+ -+static const char gmac_stats_strings[GMAC_STATS_NUM][ETH_GSTRING_LEN] = { -+ "GMAC_IN_DISCARDS", -+ "GMAC_IN_ERRORS", -+ "GMAC_IN_MCAST", -+ "GMAC_IN_BCAST", -+ "GMAC_IN_MAC1", -+ "GMAC_IN_MAC2", -+ "RX_STATUS_GOOD_FRAME", -+ "RX_STATUS_TOO_LONG_GOOD_CRC", -+ "RX_STATUS_RUNT_FRAME", -+ "RX_STATUS_SFD_NOT_FOUND", -+ "RX_STATUS_CRC_ERROR", -+ "RX_STATUS_TOO_LONG_BAD_CRC", -+ "RX_STATUS_ALIGNMENT_ERROR", -+ "RX_STATUS_TOO_LONG_BAD_ALIGN", -+ "RX_STATUS_RX_ERR", -+ "RX_STATUS_DA_FILTERED", -+ "RX_STATUS_BUFFER_FULL", -+ "RX_STATUS_11", -+ "RX_STATUS_12", -+ "RX_STATUS_13", -+ "RX_STATUS_14", -+ "RX_STATUS_15", -+ "RX_CHKSUM_IP_UDP_TCP_OK", -+ "RX_CHKSUM_IP_OK_ONLY", -+ "RX_CHKSUM_NONE", -+ "RX_CHKSUM_3", -+ "RX_CHKSUM_IP_ERR_UNKNOWN", -+ "RX_CHKSUM_IP_ERR", -+ "RX_CHKSUM_TCP_UDP_ERR", -+ "RX_CHKSUM_7", -+ "RX_NAPI_EXITS", -+ "TX_FRAGS[1]", -+ "TX_FRAGS[2]", -+ "TX_FRAGS[3]", -+ "TX_FRAGS[4]", -+ "TX_FRAGS[5]", -+ "TX_FRAGS[6]", -+ "TX_FRAGS[7]", -+ "TX_FRAGS[8]", -+ "TX_FRAGS[9]", -+ "TX_FRAGS[10]", -+ "TX_FRAGS[11]", -+ "TX_FRAGS[12]", -+ "TX_FRAGS[13]", -+ "TX_FRAGS[14]", -+ "TX_FRAGS[15]", -+ "TX_FRAGS[16+]", -+ "TX_FRAGS_LINEARIZED", -+ "TX_HW_CSUMMED", -+}; -+ -+static void gmac_dump_dma_state(struct net_device *netdev); -+ -+static void gmac_update_config0_reg(struct net_device *netdev, -+ u32 val, u32 vmask) -+{ -+ struct gemini_ethernet_port *port = netdev_priv(netdev); -+ unsigned long flags; -+ u32 reg; -+ -+ spin_lock_irqsave(&port->config_lock, flags); -+ -+ reg = readl(port->gmac_base + GMAC_CONFIG0); -+ reg = (reg & ~vmask) | val; -+ writel(reg, port->gmac_base + GMAC_CONFIG0); -+ -+ spin_unlock_irqrestore(&port->config_lock, flags); -+} -+ -+static void gmac_enable_tx_rx(struct net_device *netdev) -+{ -+ struct gemini_ethernet_port *port = netdev_priv(netdev); -+ unsigned long flags; -+ u32 reg; -+ -+ spin_lock_irqsave(&port->config_lock, flags); -+ -+ reg = readl(port->gmac_base + GMAC_CONFIG0); -+ reg &= ~CONFIG0_TX_RX_DISABLE; -+ writel(reg, port->gmac_base + GMAC_CONFIG0); -+ -+ spin_unlock_irqrestore(&port->config_lock, flags); -+} -+ -+static void gmac_disable_tx_rx(struct net_device *netdev) -+{ -+ struct gemini_ethernet_port *port = netdev_priv(netdev); -+ unsigned long flags; -+ u32 val; -+ -+ spin_lock_irqsave(&port->config_lock, flags); -+ -+ val = readl(port->gmac_base + GMAC_CONFIG0); -+ val |= CONFIG0_TX_RX_DISABLE; -+ writel(val, port->gmac_base + GMAC_CONFIG0); -+ -+ spin_unlock_irqrestore(&port->config_lock, flags); -+ -+ mdelay(10); /* let GMAC consume packet */ -+} -+ -+static void gmac_set_flow_control(struct net_device *netdev, bool tx, bool rx) -+{ -+ struct gemini_ethernet_port *port = netdev_priv(netdev); -+ unsigned long flags; -+ u32 val; -+ -+ spin_lock_irqsave(&port->config_lock, flags); -+ -+ val = readl(port->gmac_base + GMAC_CONFIG0); -+ val &= ~CONFIG0_FLOW_CTL; -+ if (tx) -+ val |= CONFIG0_FLOW_TX; -+ if (rx) -+ val |= CONFIG0_FLOW_RX; -+ writel(val, port->gmac_base + GMAC_CONFIG0); -+ -+ spin_unlock_irqrestore(&port->config_lock, flags); -+} -+ -+static void gmac_speed_set(struct net_device *netdev) -+{ -+ struct gemini_ethernet_port *port = netdev_priv(netdev); -+ struct phy_device *phydev = netdev->phydev; -+ union gmac_status status, old_status; -+ int pause_tx = 0; -+ int pause_rx = 0; -+ -+ status.bits32 = readl(port->gmac_base + GMAC_STATUS); -+ old_status.bits32 = status.bits32; -+ status.bits.link = phydev->link; -+ status.bits.duplex = phydev->duplex; -+ -+ switch (phydev->speed) { -+ case 1000: -+ status.bits.speed = GMAC_SPEED_1000; -+ if (phydev->interface == PHY_INTERFACE_MODE_RGMII) -+ status.bits.mii_rmii = GMAC_PHY_RGMII_1000; -+ netdev_info(netdev, "connect to RGMII @ 1Gbit\n"); -+ break; -+ case 100: -+ status.bits.speed = GMAC_SPEED_100; -+ if (phydev->interface == PHY_INTERFACE_MODE_RGMII) -+ status.bits.mii_rmii = GMAC_PHY_RGMII_100_10; -+ netdev_info(netdev, "connect to RGMII @ 100 Mbit\n"); -+ break; -+ case 10: -+ status.bits.speed = GMAC_SPEED_10; -+ if (phydev->interface == PHY_INTERFACE_MODE_RGMII) -+ status.bits.mii_rmii = GMAC_PHY_RGMII_100_10; -+ netdev_info(netdev, "connect to RGMII @ 10 Mbit\n"); -+ break; -+ default: -+ netdev_warn(netdev, "Not supported PHY speed (%d)\n", -+ phydev->speed); -+ } -+ -+ if (phydev->duplex == DUPLEX_FULL) { -+ u16 lcladv = phy_read(phydev, MII_ADVERTISE); -+ u16 rmtadv = phy_read(phydev, MII_LPA); -+ u8 cap = mii_resolve_flowctrl_fdx(lcladv, rmtadv); -+ -+ if (cap & FLOW_CTRL_RX) -+ pause_rx = 1; -+ if (cap & FLOW_CTRL_TX) -+ pause_tx = 1; -+ } -+ -+ gmac_set_flow_control(netdev, pause_tx, pause_rx); -+ -+ if (old_status.bits32 == status.bits32) -+ return; -+ -+ if (netif_msg_link(port)) { -+ phy_print_status(phydev); -+ netdev_info(netdev, "link flow control: %s\n", -+ phydev->pause -+ ? (phydev->asym_pause ? "tx" : "both") -+ : (phydev->asym_pause ? "rx" : "none") -+ ); -+ } -+ -+ gmac_disable_tx_rx(netdev); -+ writel(status.bits32, port->gmac_base + GMAC_STATUS); -+ gmac_enable_tx_rx(netdev); -+} -+ -+static int gmac_setup_phy(struct net_device *netdev) -+{ -+ struct gemini_ethernet_port *port = netdev_priv(netdev); -+ union gmac_status status = { .bits32 = 0 }; -+ struct device *dev = port->dev; -+ struct phy_device *phy; -+ -+ phy = of_phy_get_and_connect(netdev, -+ dev->of_node, -+ gmac_speed_set); -+ if (!phy) -+ return -ENODEV; -+ netdev->phydev = phy; -+ -+ netdev_info(netdev, "connected to PHY \"%s\"\n", -+ phydev_name(phy)); -+ phy_attached_print(phy, "phy_id=0x%.8lx, phy_mode=%s\n", -+ (unsigned long)phy->phy_id, -+ phy_modes(phy->interface)); -+ -+ phy->supported &= PHY_GBIT_FEATURES; -+ phy->supported |= SUPPORTED_Asym_Pause | SUPPORTED_Pause; -+ phy->advertising = phy->supported; -+ -+ /* set PHY interface type */ -+ switch (phy->interface) { -+ case PHY_INTERFACE_MODE_MII: -+ netdev_info(netdev, "set GMAC0 to GMII mode, GMAC1 disabled\n"); -+ status.bits.mii_rmii = GMAC_PHY_MII; -+ netdev_info(netdev, "connect to MII\n"); -+ break; -+ case PHY_INTERFACE_MODE_GMII: -+ netdev_info(netdev, "set GMAC0 to GMII mode, GMAC1 disabled\n"); -+ status.bits.mii_rmii = GMAC_PHY_GMII; -+ netdev_info(netdev, "connect to GMII\n"); -+ break; -+ case PHY_INTERFACE_MODE_RGMII: -+ dev_info(dev, "set GMAC0 and GMAC1 to MII/RGMII mode\n"); -+ status.bits.mii_rmii = GMAC_PHY_RGMII_100_10; -+ netdev_info(netdev, "connect to RGMII\n"); -+ break; -+ default: -+ netdev_err(netdev, "Unsupported MII interface\n"); -+ phy_disconnect(phy); -+ netdev->phydev = NULL; -+ return -EINVAL; -+ } -+ writel(status.bits32, port->gmac_base + GMAC_STATUS); -+ -+ return 0; -+} -+ -+static int gmac_pick_rx_max_len(int max_l3_len) -+{ -+ /* index = CONFIG_MAXLEN_XXX values */ -+ static const int max_len[8] = { -+ 1536, 1518, 1522, 1542, -+ 9212, 10236, 1518, 1518 -+ }; -+ int i, n = 5; -+ -+ max_l3_len += ETH_HLEN + VLAN_HLEN; -+ -+ if (max_l3_len > max_len[n]) -+ return -1; -+ -+ for (i = 0; i < 5; i++) { -+ if (max_len[i] >= max_l3_len && max_len[i] < max_len[n]) -+ n = i; -+ } -+ -+ return n; -+} -+ -+static int gmac_init(struct net_device *netdev) -+{ -+ struct gemini_ethernet_port *port = netdev_priv(netdev); -+ union gmac_config0 config0 = { .bits = { -+ .dis_tx = 1, -+ .dis_rx = 1, -+ .ipv4_rx_chksum = 1, -+ .ipv6_rx_chksum = 1, -+ .rx_err_detect = 1, -+ .rgmm_edge = 1, -+ .port0_chk_hwq = 1, -+ .port1_chk_hwq = 1, -+ .port0_chk_toeq = 1, -+ .port1_chk_toeq = 1, -+ .port0_chk_classq = 1, -+ .port1_chk_classq = 1, -+ } }; -+ union gmac_ahb_weight ahb_weight = { .bits = { -+ .rx_weight = 1, -+ .tx_weight = 1, -+ .hash_weight = 1, -+ .pre_req = 0x1f, -+ .tq_dv_threshold = 0, -+ } }; -+ union gmac_tx_wcr0 hw_weigh = { .bits = { -+ .hw_tq3 = 1, -+ .hw_tq2 = 1, -+ .hw_tq1 = 1, -+ .hw_tq0 = 1, -+ } }; -+ union gmac_tx_wcr1 sw_weigh = { .bits = { -+ .sw_tq5 = 1, -+ .sw_tq4 = 1, -+ .sw_tq3 = 1, -+ .sw_tq2 = 1, -+ .sw_tq1 = 1, -+ .sw_tq0 = 1, -+ } }; -+ union gmac_config1 config1 = { .bits = { -+ .set_threshold = 16, -+ .rel_threshold = 24, -+ } }; -+ union gmac_config2 config2 = { .bits = { -+ .set_threshold = 16, -+ .rel_threshold = 32, -+ } }; -+ union gmac_config3 config3 = { .bits = { -+ .set_threshold = 0, -+ .rel_threshold = 0, -+ } }; -+ union gmac_config0 tmp; -+ u32 val; -+ -+ config0.bits.max_len = gmac_pick_rx_max_len(netdev->mtu); -+ tmp.bits32 = readl(port->gmac_base + GMAC_CONFIG0); -+ config0.bits.reserved = tmp.bits.reserved; -+ writel(config0.bits32, port->gmac_base + GMAC_CONFIG0); -+ writel(config1.bits32, port->gmac_base + GMAC_CONFIG1); -+ writel(config2.bits32, port->gmac_base + GMAC_CONFIG2); -+ writel(config3.bits32, port->gmac_base + GMAC_CONFIG3); -+ -+ val = readl(port->dma_base + GMAC_AHB_WEIGHT_REG); -+ writel(ahb_weight.bits32, port->dma_base + GMAC_AHB_WEIGHT_REG); -+ -+ writel(hw_weigh.bits32, -+ port->dma_base + GMAC_TX_WEIGHTING_CTRL_0_REG); -+ writel(sw_weigh.bits32, -+ port->dma_base + GMAC_TX_WEIGHTING_CTRL_1_REG); -+ -+ port->rxq_order = DEFAULT_GMAC_RXQ_ORDER; -+ port->txq_order = DEFAULT_GMAC_TXQ_ORDER; -+ port->rx_coalesce_nsecs = DEFAULT_RX_COALESCE_NSECS; -+ -+ /* Mark every quarter of the queue a packet for interrupt -+ * in order to be able to wake up the queue if it was stopped -+ */ -+ port->irq_every_tx_packets = 1 << (port->txq_order - 2); -+ -+ return 0; -+} -+ -+static void gmac_uninit(struct net_device *netdev) -+{ -+ if (netdev->phydev) -+ phy_disconnect(netdev->phydev); -+} -+ -+static int gmac_setup_txqs(struct net_device *netdev) -+{ -+ struct gemini_ethernet_port *port = netdev_priv(netdev); -+ unsigned int n_txq = netdev->num_tx_queues; -+ struct gemini_ethernet *geth = port->geth; -+ size_t entries = 1 << port->txq_order; -+ struct gmac_txq *txq = port->txq; -+ struct gmac_txdesc *desc_ring; -+ size_t len = n_txq * entries; -+ struct sk_buff **skb_tab; -+ void __iomem *rwptr_reg; -+ unsigned int r; -+ int i; -+ -+ rwptr_reg = port->dma_base + GMAC_SW_TX_QUEUE0_PTR_REG; -+ -+ skb_tab = kcalloc(len, sizeof(*skb_tab), GFP_KERNEL); -+ if (!skb_tab) -+ return -ENOMEM; -+ -+ desc_ring = dma_alloc_coherent(geth->dev, len * sizeof(*desc_ring), -+ &port->txq_dma_base, GFP_KERNEL); -+ -+ if (!desc_ring) { -+ kfree(skb_tab); -+ return -ENOMEM; -+ } -+ -+ if (port->txq_dma_base & ~DMA_Q_BASE_MASK) { -+ dev_warn(geth->dev, "TX queue base it not aligned\n"); -+ return -ENOMEM; -+ } -+ -+ writel(port->txq_dma_base | port->txq_order, -+ port->dma_base + GMAC_SW_TX_QUEUE_BASE_REG); -+ -+ for (i = 0; i < n_txq; i++) { -+ txq->ring = desc_ring; -+ txq->skb = skb_tab; -+ txq->noirq_packets = 0; -+ -+ r = readw(rwptr_reg); -+ rwptr_reg += 2; -+ writew(r, rwptr_reg); -+ rwptr_reg += 2; -+ txq->cptr = r; -+ -+ txq++; -+ desc_ring += entries; -+ skb_tab += entries; -+ } -+ -+ return 0; -+} -+ -+static void gmac_clean_txq(struct net_device *netdev, struct gmac_txq *txq, -+ unsigned int r) -+{ -+ struct gemini_ethernet_port *port = netdev_priv(netdev); -+ unsigned int m = (1 << port->txq_order) - 1; -+ struct gemini_ethernet *geth = port->geth; -+ unsigned int c = txq->cptr; -+ union gmac_txdesc_0 word0; -+ union gmac_txdesc_1 word1; -+ unsigned int hwchksum = 0; -+ unsigned long bytes = 0; -+ struct gmac_txdesc *txd; -+ unsigned short nfrags; -+ unsigned int errs = 0; -+ unsigned int pkts = 0; -+ unsigned int word3; -+ dma_addr_t mapping; -+ -+ if (c == r) -+ return; -+ -+ while (c != r) { -+ txd = txq->ring + c; -+ word0 = txd->word0; -+ word1 = txd->word1; -+ mapping = txd->word2.buf_adr; -+ word3 = txd->word3.bits32; -+ -+ dma_unmap_single(geth->dev, mapping, -+ word0.bits.buffer_size, DMA_TO_DEVICE); -+ -+ if (word3 & EOF_BIT) -+ dev_kfree_skb(txq->skb[c]); -+ -+ c++; -+ c &= m; -+ -+ if (!(word3 & SOF_BIT)) -+ continue; -+ -+ if (!word0.bits.status_tx_ok) { -+ errs++; -+ continue; -+ } -+ -+ pkts++; -+ bytes += txd->word1.bits.byte_count; -+ -+ if (word1.bits32 & TSS_CHECKUM_ENABLE) -+ hwchksum++; -+ -+ nfrags = word0.bits.desc_count - 1; -+ if (nfrags) { -+ if (nfrags >= TX_MAX_FRAGS) -+ nfrags = TX_MAX_FRAGS - 1; -+ -+ u64_stats_update_begin(&port->tx_stats_syncp); -+ port->tx_frag_stats[nfrags]++; -+ u64_stats_update_end(&port->ir_stats_syncp); -+ } -+ } -+ -+ u64_stats_update_begin(&port->ir_stats_syncp); -+ port->stats.tx_errors += errs; -+ port->stats.tx_packets += pkts; -+ port->stats.tx_bytes += bytes; -+ port->tx_hw_csummed += hwchksum; -+ u64_stats_update_end(&port->ir_stats_syncp); -+ -+ txq->cptr = c; -+} -+ -+static void gmac_cleanup_txqs(struct net_device *netdev) -+{ -+ struct gemini_ethernet_port *port = netdev_priv(netdev); -+ unsigned int n_txq = netdev->num_tx_queues; -+ struct gemini_ethernet *geth = port->geth; -+ void __iomem *rwptr_reg; -+ unsigned int r, i; -+ -+ rwptr_reg = port->dma_base + GMAC_SW_TX_QUEUE0_PTR_REG; -+ -+ for (i = 0; i < n_txq; i++) { -+ r = readw(rwptr_reg); -+ rwptr_reg += 2; -+ writew(r, rwptr_reg); -+ rwptr_reg += 2; -+ -+ gmac_clean_txq(netdev, port->txq + i, r); -+ } -+ writel(0, port->dma_base + GMAC_SW_TX_QUEUE_BASE_REG); -+ -+ kfree(port->txq->skb); -+ dma_free_coherent(geth->dev, -+ n_txq * sizeof(*port->txq->ring) << port->txq_order, -+ port->txq->ring, port->txq_dma_base); -+} -+ -+static int gmac_setup_rxq(struct net_device *netdev) -+{ -+ struct gemini_ethernet_port *port = netdev_priv(netdev); -+ struct gemini_ethernet *geth = port->geth; -+ struct nontoe_qhdr __iomem *qhdr; -+ -+ qhdr = geth->base + TOE_DEFAULT_Q_HDR_BASE(netdev->dev_id); -+ port->rxq_rwptr = &qhdr->word1; -+ -+ /* Remap a slew of memory to use for the RX queue */ -+ port->rxq_ring = dma_alloc_coherent(geth->dev, -+ sizeof(*port->rxq_ring) << port->rxq_order, -+ &port->rxq_dma_base, GFP_KERNEL); -+ if (!port->rxq_ring) -+ return -ENOMEM; -+ if (port->rxq_dma_base & ~NONTOE_QHDR0_BASE_MASK) { -+ dev_warn(geth->dev, "RX queue base it not aligned\n"); -+ return -ENOMEM; -+ } -+ -+ writel(port->rxq_dma_base | port->rxq_order, &qhdr->word0); -+ writel(0, port->rxq_rwptr); -+ return 0; -+} -+ -+static struct gmac_queue_page * -+gmac_get_queue_page(struct gemini_ethernet *geth, -+ struct gemini_ethernet_port *port, -+ dma_addr_t addr) -+{ -+ struct gmac_queue_page *gpage; -+ dma_addr_t mapping; -+ int i; -+ -+ /* Only look for even pages */ -+ mapping = addr & PAGE_MASK; -+ -+ if (!geth->freeq_pages) { -+ dev_err(geth->dev, "try to get page with no page list\n"); -+ return NULL; -+ } -+ -+ /* Look up a ring buffer page from virtual mapping */ -+ for (i = 0; i < geth->num_freeq_pages; i++) { -+ gpage = &geth->freeq_pages[i]; -+ if (gpage->mapping == mapping) -+ return gpage; -+ } -+ -+ return NULL; -+} -+ -+static void gmac_cleanup_rxq(struct net_device *netdev) -+{ -+ struct gemini_ethernet_port *port = netdev_priv(netdev); -+ struct gemini_ethernet *geth = port->geth; -+ struct gmac_rxdesc *rxd = port->rxq_ring; -+ static struct gmac_queue_page *gpage; -+ struct nontoe_qhdr __iomem *qhdr; -+ void __iomem *dma_reg; -+ void __iomem *ptr_reg; -+ dma_addr_t mapping; -+ union dma_rwptr rw; -+ unsigned int r, w; -+ -+ qhdr = geth->base + -+ TOE_DEFAULT_Q_HDR_BASE(netdev->dev_id); -+ dma_reg = &qhdr->word0; -+ ptr_reg = &qhdr->word1; -+ -+ rw.bits32 = readl(ptr_reg); -+ r = rw.bits.rptr; -+ w = rw.bits.wptr; -+ writew(r, ptr_reg + 2); -+ -+ writel(0, dma_reg); -+ -+ /* Loop from read pointer to write pointer of the RX queue -+ * and free up all pages by the queue. -+ */ -+ while (r != w) { -+ mapping = rxd[r].word2.buf_adr; -+ r++; -+ r &= ((1 << port->rxq_order) - 1); -+ -+ if (!mapping) -+ continue; -+ -+ /* Freeq pointers are one page off */ -+ gpage = gmac_get_queue_page(geth, port, mapping + PAGE_SIZE); -+ if (!gpage) { -+ dev_err(geth->dev, "could not find page\n"); -+ continue; -+ } -+ /* Release the RX queue reference to the page */ -+ put_page(gpage->page); -+ } -+ -+ dma_free_coherent(geth->dev, sizeof(*port->rxq_ring) << port->rxq_order, -+ port->rxq_ring, port->rxq_dma_base); -+} -+ -+static struct page *geth_freeq_alloc_map_page(struct gemini_ethernet *geth, -+ int pn) -+{ -+ struct gmac_rxdesc *freeq_entry; -+ struct gmac_queue_page *gpage; -+ unsigned int fpp_order; -+ unsigned int frag_len; -+ dma_addr_t mapping; -+ struct page *page; -+ int i; -+ -+ /* First allocate and DMA map a single page */ -+ page = alloc_page(GFP_ATOMIC); -+ if (!page) -+ return NULL; -+ -+ mapping = dma_map_single(geth->dev, page_address(page), -+ PAGE_SIZE, DMA_FROM_DEVICE); -+ if (dma_mapping_error(geth->dev, mapping)) { -+ put_page(page); -+ return NULL; -+ } -+ -+ /* The assign the page mapping (physical address) to the buffer address -+ * in the hardware queue. PAGE_SHIFT on ARM is 12 (1 page is 4096 bytes, -+ * 4k), and the default RX frag order is 11 (fragments are up 20 2048 -+ * bytes, 2k) so fpp_order (fragments per page order) is default 1. Thus -+ * each page normally needs two entries in the queue. -+ */ -+ frag_len = 1 << geth->freeq_frag_order; /* Usually 2048 */ -+ fpp_order = PAGE_SHIFT - geth->freeq_frag_order; -+ freeq_entry = geth->freeq_ring + (pn << fpp_order); -+ dev_dbg(geth->dev, "allocate page %d fragment length %d fragments per page %d, freeq entry %p\n", -+ pn, frag_len, (1 << fpp_order), freeq_entry); -+ for (i = (1 << fpp_order); i > 0; i--) { -+ freeq_entry->word2.buf_adr = mapping; -+ freeq_entry++; -+ mapping += frag_len; -+ } -+ -+ /* If the freeq entry already has a page mapped, then unmap it. */ -+ gpage = &geth->freeq_pages[pn]; -+ if (gpage->page) { -+ mapping = geth->freeq_ring[pn << fpp_order].word2.buf_adr; -+ dma_unmap_single(geth->dev, mapping, frag_len, DMA_FROM_DEVICE); -+ /* This should be the last reference to the page so it gets -+ * released -+ */ -+ put_page(gpage->page); -+ } -+ -+ /* Then put our new mapping into the page table */ -+ dev_dbg(geth->dev, "page %d, DMA addr: %08x, page %p\n", -+ pn, (unsigned int)mapping, page); -+ gpage->mapping = mapping; -+ gpage->page = page; -+ -+ return page; -+} -+ -+/** -+ * geth_fill_freeq() - Fill the freeq with empty fragments to use -+ * @geth: the ethernet adapter -+ * @refill: whether to reset the queue by filling in all freeq entries or -+ * just refill it, usually the interrupt to refill the queue happens when -+ * the queue is half empty. -+ */ -+static unsigned int geth_fill_freeq(struct gemini_ethernet *geth, bool refill) -+{ -+ unsigned int fpp_order = PAGE_SHIFT - geth->freeq_frag_order; -+ unsigned int count = 0; -+ unsigned int pn, epn; -+ unsigned long flags; -+ union dma_rwptr rw; -+ unsigned int m_pn; -+ -+ /* Mask for page */ -+ m_pn = (1 << (geth->freeq_order - fpp_order)) - 1; -+ -+ spin_lock_irqsave(&geth->freeq_lock, flags); -+ -+ rw.bits32 = readl(geth->base + GLOBAL_SWFQ_RWPTR_REG); -+ pn = (refill ? rw.bits.wptr : rw.bits.rptr) >> fpp_order; -+ epn = (rw.bits.rptr >> fpp_order) - 1; -+ epn &= m_pn; -+ -+ /* Loop over the freeq ring buffer entries */ -+ while (pn != epn) { -+ struct gmac_queue_page *gpage; -+ struct page *page; -+ -+ gpage = &geth->freeq_pages[pn]; -+ page = gpage->page; -+ -+ dev_dbg(geth->dev, "fill entry %d page ref count %d add %d refs\n", -+ pn, page_ref_count(page), 1 << fpp_order); -+ -+ if (page_ref_count(page) > 1) { -+ unsigned int fl = (pn - epn) & m_pn; -+ -+ if (fl > 64 >> fpp_order) -+ break; -+ -+ page = geth_freeq_alloc_map_page(geth, pn); -+ if (!page) -+ break; -+ } -+ -+ /* Add one reference per fragment in the page */ -+ page_ref_add(page, 1 << fpp_order); -+ count += 1 << fpp_order; -+ pn++; -+ pn &= m_pn; -+ } -+ -+ writew(pn << fpp_order, geth->base + GLOBAL_SWFQ_RWPTR_REG + 2); -+ -+ spin_unlock_irqrestore(&geth->freeq_lock, flags); -+ -+ return count; -+} -+ -+static int geth_setup_freeq(struct gemini_ethernet *geth) -+{ -+ unsigned int fpp_order = PAGE_SHIFT - geth->freeq_frag_order; -+ unsigned int frag_len = 1 << geth->freeq_frag_order; -+ unsigned int len = 1 << geth->freeq_order; -+ unsigned int pages = len >> fpp_order; -+ union queue_threshold qt; -+ union dma_skb_size skbsz; -+ unsigned int filled; -+ unsigned int pn; -+ -+ geth->freeq_ring = dma_alloc_coherent(geth->dev, -+ sizeof(*geth->freeq_ring) << geth->freeq_order, -+ &geth->freeq_dma_base, GFP_KERNEL); -+ if (!geth->freeq_ring) -+ return -ENOMEM; -+ if (geth->freeq_dma_base & ~DMA_Q_BASE_MASK) { -+ dev_warn(geth->dev, "queue ring base it not aligned\n"); -+ goto err_freeq; -+ } -+ -+ /* Allocate a mapping to page look-up index */ -+ geth->freeq_pages = kzalloc(pages * sizeof(*geth->freeq_pages), -+ GFP_KERNEL); -+ if (!geth->freeq_pages) -+ goto err_freeq; -+ geth->num_freeq_pages = pages; -+ -+ dev_info(geth->dev, "allocate %d pages for queue\n", pages); -+ for (pn = 0; pn < pages; pn++) -+ if (!geth_freeq_alloc_map_page(geth, pn)) -+ goto err_freeq_alloc; -+ -+ filled = geth_fill_freeq(geth, false); -+ if (!filled) -+ goto err_freeq_alloc; -+ -+ qt.bits32 = readl(geth->base + GLOBAL_QUEUE_THRESHOLD_REG); -+ qt.bits.swfq_empty = 32; -+ writel(qt.bits32, geth->base + GLOBAL_QUEUE_THRESHOLD_REG); -+ -+ skbsz.bits.sw_skb_size = 1 << geth->freeq_frag_order; -+ writel(skbsz.bits32, geth->base + GLOBAL_DMA_SKB_SIZE_REG); -+ writel(geth->freeq_dma_base | geth->freeq_order, -+ geth->base + GLOBAL_SW_FREEQ_BASE_SIZE_REG); -+ -+ return 0; -+ -+err_freeq_alloc: -+ while (pn > 0) { -+ struct gmac_queue_page *gpage; -+ dma_addr_t mapping; -+ -+ --pn; -+ mapping = geth->freeq_ring[pn << fpp_order].word2.buf_adr; -+ dma_unmap_single(geth->dev, mapping, frag_len, DMA_FROM_DEVICE); -+ gpage = &geth->freeq_pages[pn]; -+ put_page(gpage->page); -+ } -+ -+ kfree(geth->freeq_pages); -+err_freeq: -+ dma_free_coherent(geth->dev, -+ sizeof(*geth->freeq_ring) << geth->freeq_order, -+ geth->freeq_ring, geth->freeq_dma_base); -+ geth->freeq_ring = NULL; -+ return -ENOMEM; -+} -+ -+/** -+ * geth_cleanup_freeq() - cleanup the DMA mappings and free the queue -+ * @geth: the Gemini global ethernet state -+ */ -+static void geth_cleanup_freeq(struct gemini_ethernet *geth) -+{ -+ unsigned int fpp_order = PAGE_SHIFT - geth->freeq_frag_order; -+ unsigned int frag_len = 1 << geth->freeq_frag_order; -+ unsigned int len = 1 << geth->freeq_order; -+ unsigned int pages = len >> fpp_order; -+ unsigned int pn; -+ -+ writew(readw(geth->base + GLOBAL_SWFQ_RWPTR_REG), -+ geth->base + GLOBAL_SWFQ_RWPTR_REG + 2); -+ writel(0, geth->base + GLOBAL_SW_FREEQ_BASE_SIZE_REG); -+ -+ for (pn = 0; pn < pages; pn++) { -+ struct gmac_queue_page *gpage; -+ dma_addr_t mapping; -+ -+ mapping = geth->freeq_ring[pn << fpp_order].word2.buf_adr; -+ dma_unmap_single(geth->dev, mapping, frag_len, DMA_FROM_DEVICE); -+ -+ gpage = &geth->freeq_pages[pn]; -+ while (page_ref_count(gpage->page) > 0) -+ put_page(gpage->page); -+ } -+ -+ kfree(geth->freeq_pages); -+ -+ dma_free_coherent(geth->dev, -+ sizeof(*geth->freeq_ring) << geth->freeq_order, -+ geth->freeq_ring, geth->freeq_dma_base); -+} -+ -+/** -+ * geth_resize_freeq() - resize the software queue depth -+ * @port: the port requesting the change -+ * -+ * This gets called at least once during probe() so the device queue gets -+ * "resized" from the hardware defaults. Since both ports/net devices share -+ * the same hardware queue, some synchronization between the ports is -+ * needed. -+ */ -+static int geth_resize_freeq(struct gemini_ethernet_port *port) -+{ -+ struct gemini_ethernet *geth = port->geth; -+ struct net_device *netdev = port->netdev; -+ struct gemini_ethernet_port *other_port; -+ struct net_device *other_netdev; -+ unsigned int new_size = 0; -+ unsigned int new_order; -+ unsigned long flags; -+ u32 en; -+ int ret; -+ -+ if (netdev->dev_id == 0) -+ other_netdev = geth->port1->netdev; -+ else -+ other_netdev = geth->port0->netdev; -+ -+ if (other_netdev && netif_running(other_netdev)) -+ return -EBUSY; -+ -+ new_size = 1 << (port->rxq_order + 1); -+ netdev_dbg(netdev, "port %d size: %d order %d\n", -+ netdev->dev_id, -+ new_size, -+ port->rxq_order); -+ if (other_netdev) { -+ other_port = netdev_priv(other_netdev); -+ new_size += 1 << (other_port->rxq_order + 1); -+ netdev_dbg(other_netdev, "port %d size: %d order %d\n", -+ other_netdev->dev_id, -+ (1 << (other_port->rxq_order + 1)), -+ other_port->rxq_order); -+ } -+ -+ new_order = min(15, ilog2(new_size - 1) + 1); -+ dev_dbg(geth->dev, "set shared queue to size %d order %d\n", -+ new_size, new_order); -+ if (geth->freeq_order == new_order) -+ return 0; -+ -+ spin_lock_irqsave(&geth->irq_lock, flags); -+ -+ /* Disable the software queue IRQs */ -+ en = readl(geth->base + GLOBAL_INTERRUPT_ENABLE_4_REG); -+ en &= ~SWFQ_EMPTY_INT_BIT; -+ writel(en, geth->base + GLOBAL_INTERRUPT_ENABLE_4_REG); -+ spin_unlock_irqrestore(&geth->irq_lock, flags); -+ -+ /* Drop the old queue */ -+ if (geth->freeq_ring) -+ geth_cleanup_freeq(geth); -+ -+ /* Allocate a new queue with the desired order */ -+ geth->freeq_order = new_order; -+ ret = geth_setup_freeq(geth); -+ -+ /* Restart the interrupts - NOTE if this is the first resize -+ * after probe(), this is where the interrupts get turned on -+ * in the first place. -+ */ -+ spin_lock_irqsave(&geth->irq_lock, flags); -+ en |= SWFQ_EMPTY_INT_BIT; -+ writel(en, geth->base + GLOBAL_INTERRUPT_ENABLE_4_REG); -+ spin_unlock_irqrestore(&geth->irq_lock, flags); -+ -+ return ret; -+} -+ -+static void gmac_tx_irq_enable(struct net_device *netdev, -+ unsigned int txq, int en) -+{ -+ struct gemini_ethernet_port *port = netdev_priv(netdev); -+ struct gemini_ethernet *geth = port->geth; -+ u32 val, mask; -+ -+ netdev_dbg(netdev, "%s device %d\n", __func__, netdev->dev_id); -+ -+ mask = GMAC0_IRQ0_TXQ0_INTS << (6 * netdev->dev_id + txq); -+ -+ if (en) -+ writel(mask, geth->base + GLOBAL_INTERRUPT_STATUS_0_REG); -+ -+ val = readl(geth->base + GLOBAL_INTERRUPT_ENABLE_0_REG); -+ val = en ? val | mask : val & ~mask; -+ writel(val, geth->base + GLOBAL_INTERRUPT_ENABLE_0_REG); -+} -+ -+static void gmac_tx_irq(struct net_device *netdev, unsigned int txq_num) -+{ -+ struct netdev_queue *ntxq = netdev_get_tx_queue(netdev, txq_num); -+ -+ gmac_tx_irq_enable(netdev, txq_num, 0); -+ netif_tx_wake_queue(ntxq); -+} -+ -+static int gmac_map_tx_bufs(struct net_device *netdev, struct sk_buff *skb, -+ struct gmac_txq *txq, unsigned short *desc) -+{ -+ struct gemini_ethernet_port *port = netdev_priv(netdev); -+ struct skb_shared_info *skb_si = skb_shinfo(skb); -+ unsigned short m = (1 << port->txq_order) - 1; -+ short frag, last_frag = skb_si->nr_frags - 1; -+ struct gemini_ethernet *geth = port->geth; -+ unsigned int word1, word3, buflen; -+ unsigned short w = *desc; -+ struct gmac_txdesc *txd; -+ skb_frag_t *skb_frag; -+ dma_addr_t mapping; -+ unsigned short mtu; -+ void *buffer; -+ -+ mtu = ETH_HLEN; -+ mtu += netdev->mtu; -+ if (skb->protocol == htons(ETH_P_8021Q)) -+ mtu += VLAN_HLEN; -+ -+ word1 = skb->len; -+ word3 = SOF_BIT; -+ -+ if (word1 > mtu) { -+ word1 |= TSS_MTU_ENABLE_BIT; -+ word3 |= mtu; -+ } -+ -+ if (skb->ip_summed != CHECKSUM_NONE) { -+ int tcp = 0; -+ -+ if (skb->protocol == htons(ETH_P_IP)) { -+ word1 |= TSS_IP_CHKSUM_BIT; -+ tcp = ip_hdr(skb)->protocol == IPPROTO_TCP; -+ } else { /* IPv6 */ -+ word1 |= TSS_IPV6_ENABLE_BIT; -+ tcp = ipv6_hdr(skb)->nexthdr == IPPROTO_TCP; -+ } -+ -+ word1 |= tcp ? TSS_TCP_CHKSUM_BIT : TSS_UDP_CHKSUM_BIT; -+ } -+ -+ frag = -1; -+ while (frag <= last_frag) { -+ if (frag == -1) { -+ buffer = skb->data; -+ buflen = skb_headlen(skb); -+ } else { -+ skb_frag = skb_si->frags + frag; -+ buffer = page_address(skb_frag_page(skb_frag)) + -+ skb_frag->page_offset; -+ buflen = skb_frag->size; -+ } -+ -+ if (frag == last_frag) { -+ word3 |= EOF_BIT; -+ txq->skb[w] = skb; -+ } -+ -+ mapping = dma_map_single(geth->dev, buffer, buflen, -+ DMA_TO_DEVICE); -+ if (dma_mapping_error(geth->dev, mapping)) -+ goto map_error; -+ -+ txd = txq->ring + w; -+ txd->word0.bits32 = buflen; -+ txd->word1.bits32 = word1; -+ txd->word2.buf_adr = mapping; -+ txd->word3.bits32 = word3; -+ -+ word3 &= MTU_SIZE_BIT_MASK; -+ w++; -+ w &= m; -+ frag++; -+ } -+ -+ *desc = w; -+ return 0; -+ -+map_error: -+ while (w != *desc) { -+ w--; -+ w &= m; -+ -+ dma_unmap_page(geth->dev, txq->ring[w].word2.buf_adr, -+ txq->ring[w].word0.bits.buffer_size, -+ DMA_TO_DEVICE); -+ } -+ return -ENOMEM; -+} -+ -+static int gmac_start_xmit(struct sk_buff *skb, struct net_device *netdev) -+{ -+ struct gemini_ethernet_port *port = netdev_priv(netdev); -+ unsigned short m = (1 << port->txq_order) - 1; -+ struct netdev_queue *ntxq; -+ unsigned short r, w, d; -+ void __iomem *ptr_reg; -+ struct gmac_txq *txq; -+ int txq_num, nfrags; -+ union dma_rwptr rw; -+ -+ SKB_FRAG_ASSERT(skb); -+ -+ if (skb->len >= 0x10000) -+ goto out_drop_free; -+ -+ txq_num = skb_get_queue_mapping(skb); -+ ptr_reg = port->dma_base + GMAC_SW_TX_QUEUE_PTR_REG(txq_num); -+ txq = &port->txq[txq_num]; -+ ntxq = netdev_get_tx_queue(netdev, txq_num); -+ nfrags = skb_shinfo(skb)->nr_frags; -+ -+ rw.bits32 = readl(ptr_reg); -+ r = rw.bits.rptr; -+ w = rw.bits.wptr; -+ -+ d = txq->cptr - w - 1; -+ d &= m; -+ -+ if (d < nfrags + 2) { -+ gmac_clean_txq(netdev, txq, r); -+ d = txq->cptr - w - 1; -+ d &= m; -+ -+ if (d < nfrags + 2) { -+ netif_tx_stop_queue(ntxq); -+ -+ d = txq->cptr + nfrags + 16; -+ d &= m; -+ txq->ring[d].word3.bits.eofie = 1; -+ gmac_tx_irq_enable(netdev, txq_num, 1); -+ -+ u64_stats_update_begin(&port->tx_stats_syncp); -+ netdev->stats.tx_fifo_errors++; -+ u64_stats_update_end(&port->tx_stats_syncp); -+ return NETDEV_TX_BUSY; -+ } -+ } -+ -+ if (gmac_map_tx_bufs(netdev, skb, txq, &w)) { -+ if (skb_linearize(skb)) -+ goto out_drop; -+ -+ u64_stats_update_begin(&port->tx_stats_syncp); -+ port->tx_frags_linearized++; -+ u64_stats_update_end(&port->tx_stats_syncp); -+ -+ if (gmac_map_tx_bufs(netdev, skb, txq, &w)) -+ goto out_drop_free; -+ } -+ -+ writew(w, ptr_reg + 2); -+ -+ gmac_clean_txq(netdev, txq, r); -+ return NETDEV_TX_OK; -+ -+out_drop_free: -+ dev_kfree_skb(skb); -+out_drop: -+ u64_stats_update_begin(&port->tx_stats_syncp); -+ port->stats.tx_dropped++; -+ u64_stats_update_end(&port->tx_stats_syncp); -+ return NETDEV_TX_OK; -+} -+ -+static void gmac_tx_timeout(struct net_device *netdev) -+{ -+ netdev_err(netdev, "Tx timeout\n"); -+ gmac_dump_dma_state(netdev); -+} -+ -+static void gmac_enable_irq(struct net_device *netdev, int enable) -+{ -+ struct gemini_ethernet_port *port = netdev_priv(netdev); -+ struct gemini_ethernet *geth = port->geth; -+ unsigned long flags; -+ u32 val, mask; -+ -+ netdev_info(netdev, "%s device %d %s\n", __func__, -+ netdev->dev_id, enable ? "enable" : "disable"); -+ spin_lock_irqsave(&geth->irq_lock, flags); -+ -+ mask = GMAC0_IRQ0_2 << (netdev->dev_id * 2); -+ val = readl(geth->base + GLOBAL_INTERRUPT_ENABLE_0_REG); -+ val = enable ? (val | mask) : (val & ~mask); -+ writel(val, geth->base + GLOBAL_INTERRUPT_ENABLE_0_REG); -+ -+ mask = DEFAULT_Q0_INT_BIT << netdev->dev_id; -+ val = readl(geth->base + GLOBAL_INTERRUPT_ENABLE_1_REG); -+ val = enable ? (val | mask) : (val & ~mask); -+ writel(val, geth->base + GLOBAL_INTERRUPT_ENABLE_1_REG); -+ -+ mask = GMAC0_IRQ4_8 << (netdev->dev_id * 8); -+ val = readl(geth->base + GLOBAL_INTERRUPT_ENABLE_4_REG); -+ val = enable ? (val | mask) : (val & ~mask); -+ writel(val, geth->base + GLOBAL_INTERRUPT_ENABLE_4_REG); -+ -+ spin_unlock_irqrestore(&geth->irq_lock, flags); -+} -+ -+static void gmac_enable_rx_irq(struct net_device *netdev, int enable) -+{ -+ struct gemini_ethernet_port *port = netdev_priv(netdev); -+ struct gemini_ethernet *geth = port->geth; -+ unsigned long flags; -+ u32 val, mask; -+ -+ netdev_dbg(netdev, "%s device %d %s\n", __func__, netdev->dev_id, -+ enable ? "enable" : "disable"); -+ spin_lock_irqsave(&geth->irq_lock, flags); -+ mask = DEFAULT_Q0_INT_BIT << netdev->dev_id; -+ -+ val = readl(geth->base + GLOBAL_INTERRUPT_ENABLE_1_REG); -+ val = enable ? (val | mask) : (val & ~mask); -+ writel(val, geth->base + GLOBAL_INTERRUPT_ENABLE_1_REG); -+ -+ spin_unlock_irqrestore(&geth->irq_lock, flags); -+} -+ -+static struct sk_buff *gmac_skb_if_good_frame(struct gemini_ethernet_port *port, -+ union gmac_rxdesc_0 word0, -+ unsigned int frame_len) -+{ -+ unsigned int rx_csum = word0.bits.chksum_status; -+ unsigned int rx_status = word0.bits.status; -+ struct sk_buff *skb = NULL; -+ -+ port->rx_stats[rx_status]++; -+ port->rx_csum_stats[rx_csum]++; -+ -+ if (word0.bits.derr || word0.bits.perr || -+ rx_status || frame_len < ETH_ZLEN || -+ rx_csum >= RX_CHKSUM_IP_ERR_UNKNOWN) { -+ port->stats.rx_errors++; -+ -+ if (frame_len < ETH_ZLEN || RX_ERROR_LENGTH(rx_status)) -+ port->stats.rx_length_errors++; -+ if (RX_ERROR_OVER(rx_status)) -+ port->stats.rx_over_errors++; -+ if (RX_ERROR_CRC(rx_status)) -+ port->stats.rx_crc_errors++; -+ if (RX_ERROR_FRAME(rx_status)) -+ port->stats.rx_frame_errors++; -+ return NULL; -+ } -+ -+ skb = napi_get_frags(&port->napi); -+ if (!skb) -+ goto update_exit; -+ -+ if (rx_csum == RX_CHKSUM_IP_UDP_TCP_OK) -+ skb->ip_summed = CHECKSUM_UNNECESSARY; -+ -+update_exit: -+ port->stats.rx_bytes += frame_len; -+ port->stats.rx_packets++; -+ return skb; -+} -+ -+static unsigned int gmac_rx(struct net_device *netdev, unsigned int budget) -+{ -+ struct gemini_ethernet_port *port = netdev_priv(netdev); -+ unsigned short m = (1 << port->rxq_order) - 1; -+ struct gemini_ethernet *geth = port->geth; -+ void __iomem *ptr_reg = port->rxq_rwptr; -+ unsigned int frame_len, frag_len; -+ struct gmac_rxdesc *rx = NULL; -+ struct gmac_queue_page *gpage; -+ static struct sk_buff *skb; -+ union gmac_rxdesc_0 word0; -+ union gmac_rxdesc_1 word1; -+ union gmac_rxdesc_3 word3; -+ struct page *page = NULL; -+ unsigned int page_offs; -+ unsigned short r, w; -+ union dma_rwptr rw; -+ dma_addr_t mapping; -+ int frag_nr = 0; -+ -+ rw.bits32 = readl(ptr_reg); -+ /* Reset interrupt as all packages until here are taken into account */ -+ writel(DEFAULT_Q0_INT_BIT << netdev->dev_id, -+ geth->base + GLOBAL_INTERRUPT_STATUS_1_REG); -+ r = rw.bits.rptr; -+ w = rw.bits.wptr; -+ -+ while (budget && w != r) { -+ rx = port->rxq_ring + r; -+ word0 = rx->word0; -+ word1 = rx->word1; -+ mapping = rx->word2.buf_adr; -+ word3 = rx->word3; -+ -+ r++; -+ r &= m; -+ -+ frag_len = word0.bits.buffer_size; -+ frame_len = word1.bits.byte_count; -+ page_offs = mapping & ~PAGE_MASK; -+ -+ if (!mapping) { -+ netdev_err(netdev, -+ "rxq[%u]: HW BUG: zero DMA desc\n", r); -+ goto err_drop; -+ } -+ -+ /* Freeq pointers are one page off */ -+ gpage = gmac_get_queue_page(geth, port, mapping + PAGE_SIZE); -+ if (!gpage) { -+ dev_err(geth->dev, "could not find mapping\n"); -+ continue; -+ } -+ page = gpage->page; -+ -+ if (word3.bits32 & SOF_BIT) { -+ if (skb) { -+ napi_free_frags(&port->napi); -+ port->stats.rx_dropped++; -+ } -+ -+ skb = gmac_skb_if_good_frame(port, word0, frame_len); -+ if (!skb) -+ goto err_drop; -+ -+ page_offs += NET_IP_ALIGN; -+ frag_len -= NET_IP_ALIGN; -+ frag_nr = 0; -+ -+ } else if (!skb) { -+ put_page(page); -+ continue; -+ } -+ -+ if (word3.bits32 & EOF_BIT) -+ frag_len = frame_len - skb->len; -+ -+ /* append page frag to skb */ -+ if (frag_nr == MAX_SKB_FRAGS) -+ goto err_drop; -+ -+ if (frag_len == 0) -+ netdev_err(netdev, "Received fragment with len = 0\n"); -+ -+ skb_fill_page_desc(skb, frag_nr, page, page_offs, frag_len); -+ skb->len += frag_len; -+ skb->data_len += frag_len; -+ skb->truesize += frag_len; -+ frag_nr++; -+ -+ if (word3.bits32 & EOF_BIT) { -+ napi_gro_frags(&port->napi); -+ skb = NULL; -+ --budget; -+ } -+ continue; -+ -+err_drop: -+ if (skb) { -+ napi_free_frags(&port->napi); -+ skb = NULL; -+ } -+ -+ if (mapping) -+ put_page(page); -+ -+ port->stats.rx_dropped++; -+ } -+ -+ writew(r, ptr_reg); -+ return budget; -+} -+ -+static int gmac_napi_poll(struct napi_struct *napi, int budget) -+{ -+ struct gemini_ethernet_port *port = netdev_priv(napi->dev); -+ struct gemini_ethernet *geth = port->geth; -+ unsigned int freeq_threshold; -+ unsigned int received; -+ -+ freeq_threshold = 1 << (geth->freeq_order - 1); -+ u64_stats_update_begin(&port->rx_stats_syncp); -+ -+ received = gmac_rx(napi->dev, budget); -+ if (received < budget) { -+ napi_gro_flush(napi, false); -+ napi_complete_done(napi, received); -+ gmac_enable_rx_irq(napi->dev, 1); -+ ++port->rx_napi_exits; -+ } -+ -+ port->freeq_refill += (budget - received); -+ if (port->freeq_refill > freeq_threshold) { -+ port->freeq_refill -= freeq_threshold; -+ geth_fill_freeq(geth, true); -+ } -+ -+ u64_stats_update_end(&port->rx_stats_syncp); -+ return received; -+} -+ -+static void gmac_dump_dma_state(struct net_device *netdev) -+{ -+ struct gemini_ethernet_port *port = netdev_priv(netdev); -+ struct gemini_ethernet *geth = port->geth; -+ void __iomem *ptr_reg; -+ u32 reg[5]; -+ -+ /* Interrupt status */ -+ reg[0] = readl(geth->base + GLOBAL_INTERRUPT_STATUS_0_REG); -+ reg[1] = readl(geth->base + GLOBAL_INTERRUPT_STATUS_1_REG); -+ reg[2] = readl(geth->base + GLOBAL_INTERRUPT_STATUS_2_REG); -+ reg[3] = readl(geth->base + GLOBAL_INTERRUPT_STATUS_3_REG); -+ reg[4] = readl(geth->base + GLOBAL_INTERRUPT_STATUS_4_REG); -+ netdev_err(netdev, "IRQ status: 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n", -+ reg[0], reg[1], reg[2], reg[3], reg[4]); -+ -+ /* Interrupt enable */ -+ reg[0] = readl(geth->base + GLOBAL_INTERRUPT_ENABLE_0_REG); -+ reg[1] = readl(geth->base + GLOBAL_INTERRUPT_ENABLE_1_REG); -+ reg[2] = readl(geth->base + GLOBAL_INTERRUPT_ENABLE_2_REG); -+ reg[3] = readl(geth->base + GLOBAL_INTERRUPT_ENABLE_3_REG); -+ reg[4] = readl(geth->base + GLOBAL_INTERRUPT_ENABLE_4_REG); -+ netdev_err(netdev, "IRQ enable: 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n", -+ reg[0], reg[1], reg[2], reg[3], reg[4]); -+ -+ /* RX DMA status */ -+ reg[0] = readl(port->dma_base + GMAC_DMA_RX_FIRST_DESC_REG); -+ reg[1] = readl(port->dma_base + GMAC_DMA_RX_CURR_DESC_REG); -+ reg[2] = GET_RPTR(port->rxq_rwptr); -+ reg[3] = GET_WPTR(port->rxq_rwptr); -+ netdev_err(netdev, "RX DMA regs: 0x%08x 0x%08x, ptr: %u %u\n", -+ reg[0], reg[1], reg[2], reg[3]); -+ -+ reg[0] = readl(port->dma_base + GMAC_DMA_RX_DESC_WORD0_REG); -+ reg[1] = readl(port->dma_base + GMAC_DMA_RX_DESC_WORD1_REG); -+ reg[2] = readl(port->dma_base + GMAC_DMA_RX_DESC_WORD2_REG); -+ reg[3] = readl(port->dma_base + GMAC_DMA_RX_DESC_WORD3_REG); -+ netdev_err(netdev, "RX DMA descriptor: 0x%08x 0x%08x 0x%08x 0x%08x\n", -+ reg[0], reg[1], reg[2], reg[3]); -+ -+ /* TX DMA status */ -+ ptr_reg = port->dma_base + GMAC_SW_TX_QUEUE0_PTR_REG; -+ -+ reg[0] = readl(port->dma_base + GMAC_DMA_TX_FIRST_DESC_REG); -+ reg[1] = readl(port->dma_base + GMAC_DMA_TX_CURR_DESC_REG); -+ reg[2] = GET_RPTR(ptr_reg); -+ reg[3] = GET_WPTR(ptr_reg); -+ netdev_err(netdev, "TX DMA regs: 0x%08x 0x%08x, ptr: %u %u\n", -+ reg[0], reg[1], reg[2], reg[3]); -+ -+ reg[0] = readl(port->dma_base + GMAC_DMA_TX_DESC_WORD0_REG); -+ reg[1] = readl(port->dma_base + GMAC_DMA_TX_DESC_WORD1_REG); -+ reg[2] = readl(port->dma_base + GMAC_DMA_TX_DESC_WORD2_REG); -+ reg[3] = readl(port->dma_base + GMAC_DMA_TX_DESC_WORD3_REG); -+ netdev_err(netdev, "TX DMA descriptor: 0x%08x 0x%08x 0x%08x 0x%08x\n", -+ reg[0], reg[1], reg[2], reg[3]); -+ -+ /* FREE queues status */ -+ ptr_reg = geth->base + GLOBAL_SWFQ_RWPTR_REG; -+ -+ reg[0] = GET_RPTR(ptr_reg); -+ reg[1] = GET_WPTR(ptr_reg); -+ -+ ptr_reg = geth->base + GLOBAL_HWFQ_RWPTR_REG; -+ -+ reg[2] = GET_RPTR(ptr_reg); -+ reg[3] = GET_WPTR(ptr_reg); -+ netdev_err(netdev, "FQ SW ptr: %u %u, HW ptr: %u %u\n", -+ reg[0], reg[1], reg[2], reg[3]); -+} -+ -+static void gmac_update_hw_stats(struct net_device *netdev) -+{ -+ struct gemini_ethernet_port *port = netdev_priv(netdev); -+ unsigned int rx_discards, rx_mcast, rx_bcast; -+ struct gemini_ethernet *geth = port->geth; -+ unsigned long flags; -+ -+ spin_lock_irqsave(&geth->irq_lock, flags); -+ u64_stats_update_begin(&port->ir_stats_syncp); -+ -+ rx_discards = readl(port->gmac_base + GMAC_IN_DISCARDS); -+ port->hw_stats[0] += rx_discards; -+ port->hw_stats[1] += readl(port->gmac_base + GMAC_IN_ERRORS); -+ rx_mcast = readl(port->gmac_base + GMAC_IN_MCAST); -+ port->hw_stats[2] += rx_mcast; -+ rx_bcast = readl(port->gmac_base + GMAC_IN_BCAST); -+ port->hw_stats[3] += rx_bcast; -+ port->hw_stats[4] += readl(port->gmac_base + GMAC_IN_MAC1); -+ port->hw_stats[5] += readl(port->gmac_base + GMAC_IN_MAC2); -+ -+ port->stats.rx_missed_errors += rx_discards; -+ port->stats.multicast += rx_mcast; -+ port->stats.multicast += rx_bcast; -+ -+ writel(GMAC0_MIB_INT_BIT << (netdev->dev_id * 8), -+ geth->base + GLOBAL_INTERRUPT_STATUS_4_REG); -+ -+ u64_stats_update_end(&port->ir_stats_syncp); -+ spin_unlock_irqrestore(&geth->irq_lock, flags); -+} -+ -+/** -+ * gmac_get_intr_flags() - get interrupt status flags for a port from -+ * @netdev: the net device for the port to get flags from -+ * @i: the interrupt status register 0..4 -+ */ -+static u32 gmac_get_intr_flags(struct net_device *netdev, int i) -+{ -+ struct gemini_ethernet_port *port = netdev_priv(netdev); -+ struct gemini_ethernet *geth = port->geth; -+ void __iomem *irqif_reg, *irqen_reg; -+ unsigned int offs, val; -+ -+ /* Calculate the offset using the stride of the status registers */ -+ offs = i * (GLOBAL_INTERRUPT_STATUS_1_REG - -+ GLOBAL_INTERRUPT_STATUS_0_REG); -+ -+ irqif_reg = geth->base + GLOBAL_INTERRUPT_STATUS_0_REG + offs; -+ irqen_reg = geth->base + GLOBAL_INTERRUPT_ENABLE_0_REG + offs; -+ -+ val = readl(irqif_reg) & readl(irqen_reg); -+ return val; -+} -+ -+static enum hrtimer_restart gmac_coalesce_delay_expired(struct hrtimer *timer) -+{ -+ struct gemini_ethernet_port *port = -+ container_of(timer, struct gemini_ethernet_port, -+ rx_coalesce_timer); -+ -+ napi_schedule(&port->napi); -+ return HRTIMER_NORESTART; -+} -+ -+static irqreturn_t gmac_irq(int irq, void *data) -+{ -+ struct gemini_ethernet_port *port; -+ struct net_device *netdev = data; -+ struct gemini_ethernet *geth; -+ u32 val, orr = 0; -+ -+ port = netdev_priv(netdev); -+ geth = port->geth; -+ -+ val = gmac_get_intr_flags(netdev, 0); -+ orr |= val; -+ -+ if (val & (GMAC0_IRQ0_2 << (netdev->dev_id * 2))) { -+ /* Oh, crap */ -+ netdev_err(netdev, "hw failure/sw bug\n"); -+ gmac_dump_dma_state(netdev); -+ -+ /* don't know how to recover, just reduce losses */ -+ gmac_enable_irq(netdev, 0); -+ return IRQ_HANDLED; -+ } -+ -+ if (val & (GMAC0_IRQ0_TXQ0_INTS << (netdev->dev_id * 6))) -+ gmac_tx_irq(netdev, 0); -+ -+ val = gmac_get_intr_flags(netdev, 1); -+ orr |= val; -+ -+ if (val & (DEFAULT_Q0_INT_BIT << netdev->dev_id)) { -+ gmac_enable_rx_irq(netdev, 0); -+ -+ if (!port->rx_coalesce_nsecs) { -+ napi_schedule(&port->napi); -+ } else { -+ ktime_t ktime; -+ -+ ktime = ktime_set(0, port->rx_coalesce_nsecs); -+ hrtimer_start(&port->rx_coalesce_timer, ktime, -+ HRTIMER_MODE_REL); -+ } -+ } -+ -+ val = gmac_get_intr_flags(netdev, 4); -+ orr |= val; -+ -+ if (val & (GMAC0_MIB_INT_BIT << (netdev->dev_id * 8))) -+ gmac_update_hw_stats(netdev); -+ -+ if (val & (GMAC0_RX_OVERRUN_INT_BIT << (netdev->dev_id * 8))) { -+ writel(GMAC0_RXDERR_INT_BIT << (netdev->dev_id * 8), -+ geth->base + GLOBAL_INTERRUPT_STATUS_4_REG); -+ -+ spin_lock(&geth->irq_lock); -+ u64_stats_update_begin(&port->ir_stats_syncp); -+ ++port->stats.rx_fifo_errors; -+ u64_stats_update_end(&port->ir_stats_syncp); -+ spin_unlock(&geth->irq_lock); -+ } -+ -+ return orr ? IRQ_HANDLED : IRQ_NONE; -+} -+ -+static void gmac_start_dma(struct gemini_ethernet_port *port) -+{ -+ void __iomem *dma_ctrl_reg = port->dma_base + GMAC_DMA_CTRL_REG; -+ union gmac_dma_ctrl dma_ctrl; -+ -+ dma_ctrl.bits32 = readl(dma_ctrl_reg); -+ dma_ctrl.bits.rd_enable = 1; -+ dma_ctrl.bits.td_enable = 1; -+ dma_ctrl.bits.loopback = 0; -+ dma_ctrl.bits.drop_small_ack = 0; -+ dma_ctrl.bits.rd_insert_bytes = NET_IP_ALIGN; -+ dma_ctrl.bits.rd_prot = HPROT_DATA_CACHE | HPROT_PRIVILIGED; -+ dma_ctrl.bits.rd_burst_size = HBURST_INCR8; -+ dma_ctrl.bits.rd_bus = HSIZE_8; -+ dma_ctrl.bits.td_prot = HPROT_DATA_CACHE; -+ dma_ctrl.bits.td_burst_size = HBURST_INCR8; -+ dma_ctrl.bits.td_bus = HSIZE_8; -+ -+ writel(dma_ctrl.bits32, dma_ctrl_reg); -+} -+ -+static void gmac_stop_dma(struct gemini_ethernet_port *port) -+{ -+ void __iomem *dma_ctrl_reg = port->dma_base + GMAC_DMA_CTRL_REG; -+ union gmac_dma_ctrl dma_ctrl; -+ -+ dma_ctrl.bits32 = readl(dma_ctrl_reg); -+ dma_ctrl.bits.rd_enable = 0; -+ dma_ctrl.bits.td_enable = 0; -+ writel(dma_ctrl.bits32, dma_ctrl_reg); -+} -+ -+static int gmac_open(struct net_device *netdev) -+{ -+ struct gemini_ethernet_port *port = netdev_priv(netdev); -+ int err; -+ -+ if (!netdev->phydev) { -+ err = gmac_setup_phy(netdev); -+ if (err) { -+ netif_err(port, ifup, netdev, -+ "PHY init failed: %d\n", err); -+ return err; -+ } -+ } -+ -+ err = request_irq(netdev->irq, gmac_irq, -+ IRQF_SHARED, netdev->name, netdev); -+ if (err) { -+ netdev_err(netdev, "no IRQ\n"); -+ return err; -+ } -+ -+ netif_carrier_off(netdev); -+ phy_start(netdev->phydev); -+ -+ err = geth_resize_freeq(port); -+ if (err) { -+ netdev_err(netdev, "could not resize freeq\n"); -+ goto err_stop_phy; -+ } -+ -+ err = gmac_setup_rxq(netdev); -+ if (err) { -+ netdev_err(netdev, "could not setup RXQ\n"); -+ goto err_stop_phy; -+ } -+ -+ err = gmac_setup_txqs(netdev); -+ if (err) { -+ netdev_err(netdev, "could not setup TXQs\n"); -+ gmac_cleanup_rxq(netdev); -+ goto err_stop_phy; -+ } -+ -+ napi_enable(&port->napi); -+ -+ gmac_start_dma(port); -+ gmac_enable_irq(netdev, 1); -+ gmac_enable_tx_rx(netdev); -+ netif_tx_start_all_queues(netdev); -+ -+ hrtimer_init(&port->rx_coalesce_timer, CLOCK_MONOTONIC, -+ HRTIMER_MODE_REL); -+ port->rx_coalesce_timer.function = &gmac_coalesce_delay_expired; -+ -+ netdev_info(netdev, "opened\n"); -+ -+ return 0; -+ -+err_stop_phy: -+ phy_stop(netdev->phydev); -+ free_irq(netdev->irq, netdev); -+ return err; -+} -+ -+static int gmac_stop(struct net_device *netdev) -+{ -+ struct gemini_ethernet_port *port = netdev_priv(netdev); -+ -+ hrtimer_cancel(&port->rx_coalesce_timer); -+ netif_tx_stop_all_queues(netdev); -+ gmac_disable_tx_rx(netdev); -+ gmac_stop_dma(port); -+ napi_disable(&port->napi); -+ -+ gmac_enable_irq(netdev, 0); -+ gmac_cleanup_rxq(netdev); -+ gmac_cleanup_txqs(netdev); -+ -+ phy_stop(netdev->phydev); -+ free_irq(netdev->irq, netdev); -+ -+ gmac_update_hw_stats(netdev); -+ return 0; -+} -+ -+static void gmac_set_rx_mode(struct net_device *netdev) -+{ -+ struct gemini_ethernet_port *port = netdev_priv(netdev); -+ union gmac_rx_fltr filter = { .bits = { -+ .broadcast = 1, -+ .multicast = 1, -+ .unicast = 1, -+ } }; -+ struct netdev_hw_addr *ha; -+ unsigned int bit_nr; -+ u32 mc_filter[2]; -+ -+ mc_filter[1] = 0; -+ mc_filter[0] = 0; -+ -+ if (netdev->flags & IFF_PROMISC) { -+ filter.bits.error = 1; -+ filter.bits.promiscuous = 1; -+ mc_filter[1] = ~0; -+ mc_filter[0] = ~0; -+ } else if (netdev->flags & IFF_ALLMULTI) { -+ mc_filter[1] = ~0; -+ mc_filter[0] = ~0; -+ } else { -+ netdev_for_each_mc_addr(ha, netdev) { -+ bit_nr = ~crc32_le(~0, ha->addr, ETH_ALEN) & 0x3f; -+ mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 0x1f); -+ } -+ } -+ -+ writel(mc_filter[0], port->gmac_base + GMAC_MCAST_FIL0); -+ writel(mc_filter[1], port->gmac_base + GMAC_MCAST_FIL1); -+ writel(filter.bits32, port->gmac_base + GMAC_RX_FLTR); -+} -+ -+static void gmac_write_mac_address(struct net_device *netdev) -+{ -+ struct gemini_ethernet_port *port = netdev_priv(netdev); -+ __le32 addr[3]; -+ -+ memset(addr, 0, sizeof(addr)); -+ memcpy(addr, netdev->dev_addr, ETH_ALEN); -+ -+ writel(le32_to_cpu(addr[0]), port->gmac_base + GMAC_STA_ADD0); -+ writel(le32_to_cpu(addr[1]), port->gmac_base + GMAC_STA_ADD1); -+ writel(le32_to_cpu(addr[2]), port->gmac_base + GMAC_STA_ADD2); -+} -+ -+static int gmac_set_mac_address(struct net_device *netdev, void *addr) -+{ -+ struct sockaddr *sa = addr; -+ -+ memcpy(netdev->dev_addr, sa->sa_data, ETH_ALEN); -+ gmac_write_mac_address(netdev); -+ -+ return 0; -+} -+ -+static void gmac_clear_hw_stats(struct net_device *netdev) -+{ -+ struct gemini_ethernet_port *port = netdev_priv(netdev); -+ -+ readl(port->gmac_base + GMAC_IN_DISCARDS); -+ readl(port->gmac_base + GMAC_IN_ERRORS); -+ readl(port->gmac_base + GMAC_IN_MCAST); -+ readl(port->gmac_base + GMAC_IN_BCAST); -+ readl(port->gmac_base + GMAC_IN_MAC1); -+ readl(port->gmac_base + GMAC_IN_MAC2); -+} -+ -+static void gmac_get_stats64(struct net_device *netdev, -+ struct rtnl_link_stats64 *stats) -+{ -+ struct gemini_ethernet_port *port = netdev_priv(netdev); -+ unsigned int start; -+ -+ gmac_update_hw_stats(netdev); -+ -+ /* Racing with RX NAPI */ -+ do { -+ start = u64_stats_fetch_begin(&port->rx_stats_syncp); -+ -+ stats->rx_packets = port->stats.rx_packets; -+ stats->rx_bytes = port->stats.rx_bytes; -+ stats->rx_errors = port->stats.rx_errors; -+ stats->rx_dropped = port->stats.rx_dropped; -+ -+ stats->rx_length_errors = port->stats.rx_length_errors; -+ stats->rx_over_errors = port->stats.rx_over_errors; -+ stats->rx_crc_errors = port->stats.rx_crc_errors; -+ stats->rx_frame_errors = port->stats.rx_frame_errors; -+ -+ } while (u64_stats_fetch_retry(&port->rx_stats_syncp, start)); -+ -+ /* Racing with MIB and TX completion interrupts */ -+ do { -+ start = u64_stats_fetch_begin(&port->ir_stats_syncp); -+ -+ stats->tx_errors = port->stats.tx_errors; -+ stats->tx_packets = port->stats.tx_packets; -+ stats->tx_bytes = port->stats.tx_bytes; -+ -+ stats->multicast = port->stats.multicast; -+ stats->rx_missed_errors = port->stats.rx_missed_errors; -+ stats->rx_fifo_errors = port->stats.rx_fifo_errors; -+ -+ } while (u64_stats_fetch_retry(&port->ir_stats_syncp, start)); -+ -+ /* Racing with hard_start_xmit */ -+ do { -+ start = u64_stats_fetch_begin(&port->tx_stats_syncp); -+ -+ stats->tx_dropped = port->stats.tx_dropped; -+ -+ } while (u64_stats_fetch_retry(&port->tx_stats_syncp, start)); -+ -+ stats->rx_dropped += stats->rx_missed_errors; -+} -+ -+static int gmac_change_mtu(struct net_device *netdev, int new_mtu) -+{ -+ int max_len = gmac_pick_rx_max_len(new_mtu); -+ -+ if (max_len < 0) -+ return -EINVAL; -+ -+ gmac_disable_tx_rx(netdev); -+ -+ netdev->mtu = new_mtu; -+ gmac_update_config0_reg(netdev, max_len << CONFIG0_MAXLEN_SHIFT, -+ CONFIG0_MAXLEN_MASK); -+ -+ netdev_update_features(netdev); -+ -+ gmac_enable_tx_rx(netdev); -+ -+ return 0; -+} -+ -+static netdev_features_t gmac_fix_features(struct net_device *netdev, -+ netdev_features_t features) -+{ -+ if (netdev->mtu + ETH_HLEN + VLAN_HLEN > MTU_SIZE_BIT_MASK) -+ features &= ~GMAC_OFFLOAD_FEATURES; -+ -+ return features; -+} -+ -+static int gmac_set_features(struct net_device *netdev, -+ netdev_features_t features) -+{ -+ struct gemini_ethernet_port *port = netdev_priv(netdev); -+ int enable = features & NETIF_F_RXCSUM; -+ unsigned long flags; -+ u32 reg; -+ -+ spin_lock_irqsave(&port->config_lock, flags); -+ -+ reg = readl(port->gmac_base + GMAC_CONFIG0); -+ reg = enable ? reg | CONFIG0_RX_CHKSUM : reg & ~CONFIG0_RX_CHKSUM; -+ writel(reg, port->gmac_base + GMAC_CONFIG0); -+ -+ spin_unlock_irqrestore(&port->config_lock, flags); -+ return 0; -+} -+ -+static int gmac_get_sset_count(struct net_device *netdev, int sset) -+{ -+ return sset == ETH_SS_STATS ? GMAC_STATS_NUM : 0; -+} -+ -+static void gmac_get_strings(struct net_device *netdev, u32 stringset, u8 *data) -+{ -+ if (stringset != ETH_SS_STATS) -+ return; -+ -+ memcpy(data, gmac_stats_strings, sizeof(gmac_stats_strings)); -+} -+ -+static void gmac_get_ethtool_stats(struct net_device *netdev, -+ struct ethtool_stats *estats, u64 *values) -+{ -+ struct gemini_ethernet_port *port = netdev_priv(netdev); -+ unsigned int start; -+ u64 *p; -+ int i; -+ -+ gmac_update_hw_stats(netdev); -+ -+ /* Racing with MIB interrupt */ -+ do { -+ p = values; -+ start = u64_stats_fetch_begin(&port->ir_stats_syncp); -+ -+ for (i = 0; i < RX_STATS_NUM; i++) -+ *p++ = port->hw_stats[i]; -+ -+ } while (u64_stats_fetch_retry(&port->ir_stats_syncp, start)); -+ values = p; -+ -+ /* Racing with RX NAPI */ -+ do { -+ p = values; -+ start = u64_stats_fetch_begin(&port->rx_stats_syncp); -+ -+ for (i = 0; i < RX_STATUS_NUM; i++) -+ *p++ = port->rx_stats[i]; -+ for (i = 0; i < RX_CHKSUM_NUM; i++) -+ *p++ = port->rx_csum_stats[i]; -+ *p++ = port->rx_napi_exits; -+ -+ } while (u64_stats_fetch_retry(&port->rx_stats_syncp, start)); -+ values = p; -+ -+ /* Racing with TX start_xmit */ -+ do { -+ p = values; -+ start = u64_stats_fetch_begin(&port->tx_stats_syncp); -+ -+ for (i = 0; i < TX_MAX_FRAGS; i++) { -+ *values++ = port->tx_frag_stats[i]; -+ port->tx_frag_stats[i] = 0; -+ } -+ *values++ = port->tx_frags_linearized; -+ *values++ = port->tx_hw_csummed; -+ -+ } while (u64_stats_fetch_retry(&port->tx_stats_syncp, start)); -+} -+ -+static int gmac_get_ksettings(struct net_device *netdev, -+ struct ethtool_link_ksettings *cmd) -+{ -+ if (!netdev->phydev) -+ return -ENXIO; -+ phy_ethtool_ksettings_get(netdev->phydev, cmd); -+ -+ return 0; -+} -+ -+static int gmac_set_ksettings(struct net_device *netdev, -+ const struct ethtool_link_ksettings *cmd) -+{ -+ if (!netdev->phydev) -+ return -ENXIO; -+ return phy_ethtool_ksettings_set(netdev->phydev, cmd); -+} -+ -+static int gmac_nway_reset(struct net_device *netdev) -+{ -+ if (!netdev->phydev) -+ return -ENXIO; -+ return phy_start_aneg(netdev->phydev); -+} -+ -+static void gmac_get_pauseparam(struct net_device *netdev, -+ struct ethtool_pauseparam *pparam) -+{ -+ struct gemini_ethernet_port *port = netdev_priv(netdev); -+ union gmac_config0 config0; -+ -+ config0.bits32 = readl(port->gmac_base + GMAC_CONFIG0); -+ -+ pparam->rx_pause = config0.bits.rx_fc_en; -+ pparam->tx_pause = config0.bits.tx_fc_en; -+ pparam->autoneg = true; -+} -+ -+static void gmac_get_ringparam(struct net_device *netdev, -+ struct ethtool_ringparam *rp) -+{ -+ struct gemini_ethernet_port *port = netdev_priv(netdev); -+ union gmac_config0 config0; -+ -+ config0.bits32 = readl(port->gmac_base + GMAC_CONFIG0); -+ -+ rp->rx_max_pending = 1 << 15; -+ rp->rx_mini_max_pending = 0; -+ rp->rx_jumbo_max_pending = 0; -+ rp->tx_max_pending = 1 << 15; -+ -+ rp->rx_pending = 1 << port->rxq_order; -+ rp->rx_mini_pending = 0; -+ rp->rx_jumbo_pending = 0; -+ rp->tx_pending = 1 << port->txq_order; -+} -+ -+static int gmac_set_ringparam(struct net_device *netdev, -+ struct ethtool_ringparam *rp) -+{ -+ struct gemini_ethernet_port *port = netdev_priv(netdev); -+ int err = 0; -+ -+ if (netif_running(netdev)) -+ return -EBUSY; -+ -+ if (rp->rx_pending) { -+ port->rxq_order = min(15, ilog2(rp->rx_pending - 1) + 1); -+ err = geth_resize_freeq(port); -+ } -+ if (rp->tx_pending) { -+ port->txq_order = min(15, ilog2(rp->tx_pending - 1) + 1); -+ port->irq_every_tx_packets = 1 << (port->txq_order - 2); -+ } -+ -+ return err; -+} -+ -+static int gmac_get_coalesce(struct net_device *netdev, -+ struct ethtool_coalesce *ecmd) -+{ -+ struct gemini_ethernet_port *port = netdev_priv(netdev); -+ -+ ecmd->rx_max_coalesced_frames = 1; -+ ecmd->tx_max_coalesced_frames = port->irq_every_tx_packets; -+ ecmd->rx_coalesce_usecs = port->rx_coalesce_nsecs / 1000; -+ -+ return 0; -+} -+ -+static int gmac_set_coalesce(struct net_device *netdev, -+ struct ethtool_coalesce *ecmd) -+{ -+ struct gemini_ethernet_port *port = netdev_priv(netdev); -+ -+ if (ecmd->tx_max_coalesced_frames < 1) -+ return -EINVAL; -+ if (ecmd->tx_max_coalesced_frames >= 1 << port->txq_order) -+ return -EINVAL; -+ -+ port->irq_every_tx_packets = ecmd->tx_max_coalesced_frames; -+ port->rx_coalesce_nsecs = ecmd->rx_coalesce_usecs * 1000; -+ -+ return 0; -+} -+ -+static u32 gmac_get_msglevel(struct net_device *netdev) -+{ -+ struct gemini_ethernet_port *port = netdev_priv(netdev); -+ -+ return port->msg_enable; -+} -+ -+static void gmac_set_msglevel(struct net_device *netdev, u32 level) -+{ -+ struct gemini_ethernet_port *port = netdev_priv(netdev); -+ -+ port->msg_enable = level; -+} -+ -+static void gmac_get_drvinfo(struct net_device *netdev, -+ struct ethtool_drvinfo *info) -+{ -+ strcpy(info->driver, DRV_NAME); -+ strcpy(info->version, DRV_VERSION); -+ strcpy(info->bus_info, netdev->dev_id ? "1" : "0"); -+} -+ -+static const struct net_device_ops gmac_351x_ops = { -+ .ndo_init = gmac_init, -+ .ndo_uninit = gmac_uninit, -+ .ndo_open = gmac_open, -+ .ndo_stop = gmac_stop, -+ .ndo_start_xmit = gmac_start_xmit, -+ .ndo_tx_timeout = gmac_tx_timeout, -+ .ndo_set_rx_mode = gmac_set_rx_mode, -+ .ndo_set_mac_address = gmac_set_mac_address, -+ .ndo_get_stats64 = gmac_get_stats64, -+ .ndo_change_mtu = gmac_change_mtu, -+ .ndo_fix_features = gmac_fix_features, -+ .ndo_set_features = gmac_set_features, -+}; -+ -+static const struct ethtool_ops gmac_351x_ethtool_ops = { -+ .get_sset_count = gmac_get_sset_count, -+ .get_strings = gmac_get_strings, -+ .get_ethtool_stats = gmac_get_ethtool_stats, -+ .get_link = ethtool_op_get_link, -+ .get_link_ksettings = gmac_get_ksettings, -+ .set_link_ksettings = gmac_set_ksettings, -+ .nway_reset = gmac_nway_reset, -+ .get_pauseparam = gmac_get_pauseparam, -+ .get_ringparam = gmac_get_ringparam, -+ .set_ringparam = gmac_set_ringparam, -+ .get_coalesce = gmac_get_coalesce, -+ .set_coalesce = gmac_set_coalesce, -+ .get_msglevel = gmac_get_msglevel, -+ .set_msglevel = gmac_set_msglevel, -+ .get_drvinfo = gmac_get_drvinfo, -+}; -+ -+static irqreturn_t gemini_port_irq_thread(int irq, void *data) -+{ -+ unsigned long irqmask = SWFQ_EMPTY_INT_BIT; -+ struct gemini_ethernet_port *port = data; -+ struct gemini_ethernet *geth; -+ unsigned long flags; -+ -+ geth = port->geth; -+ /* The queue is half empty so refill it */ -+ geth_fill_freeq(geth, true); -+ -+ spin_lock_irqsave(&geth->irq_lock, flags); -+ /* ACK queue interrupt */ -+ writel(irqmask, geth->base + GLOBAL_INTERRUPT_STATUS_4_REG); -+ /* Enable queue interrupt again */ -+ irqmask |= readl(geth->base + GLOBAL_INTERRUPT_ENABLE_4_REG); -+ writel(irqmask, geth->base + GLOBAL_INTERRUPT_ENABLE_4_REG); -+ spin_unlock_irqrestore(&geth->irq_lock, flags); -+ -+ return IRQ_HANDLED; -+} -+ -+static irqreturn_t gemini_port_irq(int irq, void *data) -+{ -+ struct gemini_ethernet_port *port = data; -+ struct gemini_ethernet *geth; -+ irqreturn_t ret = IRQ_NONE; -+ u32 val, en; -+ -+ geth = port->geth; -+ spin_lock(&geth->irq_lock); -+ -+ val = readl(geth->base + GLOBAL_INTERRUPT_STATUS_4_REG); -+ en = readl(geth->base + GLOBAL_INTERRUPT_ENABLE_4_REG); -+ -+ if (val & en & SWFQ_EMPTY_INT_BIT) { -+ /* Disable the queue empty interrupt while we work on -+ * processing the queue. Also disable overrun interrupts -+ * as there is not much we can do about it here. -+ */ -+ en &= ~(SWFQ_EMPTY_INT_BIT | GMAC0_RX_OVERRUN_INT_BIT -+ | GMAC1_RX_OVERRUN_INT_BIT); -+ writel(en, geth->base + GLOBAL_INTERRUPT_ENABLE_4_REG); -+ ret = IRQ_WAKE_THREAD; -+ } -+ -+ spin_unlock(&geth->irq_lock); -+ -+ return ret; -+} -+ -+static void gemini_port_remove(struct gemini_ethernet_port *port) -+{ -+ if (port->netdev) -+ unregister_netdev(port->netdev); -+ clk_disable_unprepare(port->pclk); -+ geth_cleanup_freeq(port->geth); -+} -+ -+static void gemini_ethernet_init(struct gemini_ethernet *geth) -+{ -+ writel(0, geth->base + GLOBAL_INTERRUPT_ENABLE_0_REG); -+ writel(0, geth->base + GLOBAL_INTERRUPT_ENABLE_1_REG); -+ writel(0, geth->base + GLOBAL_INTERRUPT_ENABLE_2_REG); -+ writel(0, geth->base + GLOBAL_INTERRUPT_ENABLE_3_REG); -+ writel(0, geth->base + GLOBAL_INTERRUPT_ENABLE_4_REG); -+ -+ /* Interrupt config: -+ * -+ * GMAC0 intr bits ------> int0 ----> eth0 -+ * GMAC1 intr bits ------> int1 ----> eth1 -+ * TOE intr -------------> int1 ----> eth1 -+ * Classification Intr --> int0 ----> eth0 -+ * Default Q0 -----------> int0 ----> eth0 -+ * Default Q1 -----------> int1 ----> eth1 -+ * FreeQ intr -----------> int1 ----> eth1 -+ */ -+ writel(0xCCFC0FC0, geth->base + GLOBAL_INTERRUPT_SELECT_0_REG); -+ writel(0x00F00002, geth->base + GLOBAL_INTERRUPT_SELECT_1_REG); -+ writel(0xFFFFFFFF, geth->base + GLOBAL_INTERRUPT_SELECT_2_REG); -+ writel(0xFFFFFFFF, geth->base + GLOBAL_INTERRUPT_SELECT_3_REG); -+ writel(0xFF000003, geth->base + GLOBAL_INTERRUPT_SELECT_4_REG); -+ -+ /* edge-triggered interrupts packed to level-triggered one... */ -+ writel(~0, geth->base + GLOBAL_INTERRUPT_STATUS_0_REG); -+ writel(~0, geth->base + GLOBAL_INTERRUPT_STATUS_1_REG); -+ writel(~0, geth->base + GLOBAL_INTERRUPT_STATUS_2_REG); -+ writel(~0, geth->base + GLOBAL_INTERRUPT_STATUS_3_REG); -+ writel(~0, geth->base + GLOBAL_INTERRUPT_STATUS_4_REG); -+ -+ /* Set up queue */ -+ writel(0, geth->base + GLOBAL_SW_FREEQ_BASE_SIZE_REG); -+ writel(0, geth->base + GLOBAL_HW_FREEQ_BASE_SIZE_REG); -+ writel(0, geth->base + GLOBAL_SWFQ_RWPTR_REG); -+ writel(0, geth->base + GLOBAL_HWFQ_RWPTR_REG); -+ -+ geth->freeq_frag_order = DEFAULT_RX_BUF_ORDER; -+ /* This makes the queue resize on probe() so that we -+ * set up and enable the queue IRQ. FIXME: fragile. -+ */ -+ geth->freeq_order = 1; -+} -+ -+static void gemini_port_save_mac_addr(struct gemini_ethernet_port *port) -+{ -+ port->mac_addr[0] = -+ cpu_to_le32(readl(port->gmac_base + GMAC_STA_ADD0)); -+ port->mac_addr[1] = -+ cpu_to_le32(readl(port->gmac_base + GMAC_STA_ADD1)); -+ port->mac_addr[2] = -+ cpu_to_le32(readl(port->gmac_base + GMAC_STA_ADD2)); -+} -+ -+static int gemini_ethernet_port_probe(struct platform_device *pdev) -+{ -+ char *port_names[2] = { "ethernet0", "ethernet1" }; -+ struct gemini_ethernet_port *port; -+ struct device *dev = &pdev->dev; -+ struct gemini_ethernet *geth; -+ struct net_device *netdev; -+ struct resource *gmacres; -+ struct resource *dmares; -+ struct device *parent; -+ unsigned int id; -+ int irq; -+ int ret; -+ -+ parent = dev->parent; -+ geth = dev_get_drvdata(parent); -+ -+ if (!strcmp(dev_name(dev), "60008000.ethernet-port")) -+ id = 0; -+ else if (!strcmp(dev_name(dev), "6000c000.ethernet-port")) -+ id = 1; -+ else -+ return -ENODEV; -+ -+ dev_info(dev, "probe %s ID %d\n", dev_name(dev), id); -+ -+ netdev = alloc_etherdev_mq(sizeof(*port), TX_QUEUE_NUM); -+ if (!netdev) { -+ dev_err(dev, "Can't allocate ethernet device #%d\n", id); -+ return -ENOMEM; -+ } -+ -+ port = netdev_priv(netdev); -+ SET_NETDEV_DEV(netdev, dev); -+ port->netdev = netdev; -+ port->id = id; -+ port->geth = geth; -+ port->dev = dev; -+ -+ /* DMA memory */ -+ dmares = platform_get_resource(pdev, IORESOURCE_MEM, 0); -+ if (!dmares) { -+ dev_err(dev, "no DMA resource\n"); -+ return -ENODEV; -+ } -+ port->dma_base = devm_ioremap_resource(dev, dmares); -+ if (IS_ERR(port->dma_base)) -+ return PTR_ERR(port->dma_base); -+ -+ /* GMAC config memory */ -+ gmacres = platform_get_resource(pdev, IORESOURCE_MEM, 1); -+ if (!gmacres) { -+ dev_err(dev, "no GMAC resource\n"); -+ return -ENODEV; -+ } -+ port->gmac_base = devm_ioremap_resource(dev, gmacres); -+ if (IS_ERR(port->gmac_base)) -+ return PTR_ERR(port->gmac_base); -+ -+ /* Interrupt */ -+ irq = platform_get_irq(pdev, 0); -+ if (irq <= 0) { -+ dev_err(dev, "no IRQ\n"); -+ return irq ? irq : -ENODEV; -+ } -+ port->irq = irq; -+ -+ /* Clock the port */ -+ port->pclk = devm_clk_get(dev, "PCLK"); -+ if (IS_ERR(port->pclk)) { -+ dev_err(dev, "no PCLK\n"); -+ return PTR_ERR(port->pclk); -+ } -+ ret = clk_prepare_enable(port->pclk); -+ if (ret) -+ return ret; -+ -+ /* Maybe there is a nice ethernet address we should use */ -+ gemini_port_save_mac_addr(port); -+ -+ /* Reset the port */ -+ port->reset = devm_reset_control_get_exclusive(dev, NULL); -+ if (IS_ERR(port->reset)) { -+ dev_err(dev, "no reset\n"); -+ return PTR_ERR(port->reset); -+ } -+ reset_control_reset(port->reset); -+ usleep_range(100, 500); -+ -+ /* Assign pointer in the main state container */ -+ if (!id) -+ geth->port0 = port; -+ else -+ geth->port1 = port; -+ platform_set_drvdata(pdev, port); -+ -+ /* Set up and register the netdev */ -+ netdev->dev_id = port->id; -+ netdev->irq = irq; -+ netdev->netdev_ops = &gmac_351x_ops; -+ netdev->ethtool_ops = &gmac_351x_ethtool_ops; -+ -+ spin_lock_init(&port->config_lock); -+ gmac_clear_hw_stats(netdev); -+ -+ netdev->hw_features = GMAC_OFFLOAD_FEATURES; -+ netdev->features |= GMAC_OFFLOAD_FEATURES | NETIF_F_GRO; -+ -+ port->freeq_refill = 0; -+ netif_napi_add(netdev, &port->napi, gmac_napi_poll, -+ DEFAULT_NAPI_WEIGHT); -+ -+ if (is_valid_ether_addr((void *)port->mac_addr)) { -+ memcpy(netdev->dev_addr, port->mac_addr, ETH_ALEN); -+ } else { -+ dev_dbg(dev, "ethernet address 0x%08x%08x%08x invalid\n", -+ port->mac_addr[0], port->mac_addr[1], -+ port->mac_addr[2]); -+ dev_info(dev, "using a random ethernet address\n"); -+ random_ether_addr(netdev->dev_addr); -+ } -+ gmac_write_mac_address(netdev); -+ -+ ret = devm_request_threaded_irq(port->dev, -+ port->irq, -+ gemini_port_irq, -+ gemini_port_irq_thread, -+ IRQF_SHARED, -+ port_names[port->id], -+ port); -+ if (ret) -+ return ret; -+ -+ ret = register_netdev(netdev); -+ if (!ret) { -+ netdev_info(netdev, -+ "irq %d, DMA @ 0x%pap, GMAC @ 0x%pap\n", -+ port->irq, &dmares->start, -+ &gmacres->start); -+ ret = gmac_setup_phy(netdev); -+ if (ret) -+ netdev_info(netdev, -+ "PHY init failed, deferring to ifup time\n"); -+ return 0; -+ } -+ -+ port->netdev = NULL; -+ free_netdev(netdev); -+ return ret; -+} -+ -+static int gemini_ethernet_port_remove(struct platform_device *pdev) -+{ -+ struct gemini_ethernet_port *port = platform_get_drvdata(pdev); -+ -+ gemini_port_remove(port); -+ return 0; -+} -+ -+static const struct of_device_id gemini_ethernet_port_of_match[] = { -+ { -+ .compatible = "cortina,gemini-ethernet-port", -+ }, -+ {}, -+}; -+MODULE_DEVICE_TABLE(of, gemini_ethernet_port_of_match); -+ -+static struct platform_driver gemini_ethernet_port_driver = { -+ .driver = { -+ .name = "gemini-ethernet-port", -+ .of_match_table = of_match_ptr(gemini_ethernet_port_of_match), -+ }, -+ .probe = gemini_ethernet_port_probe, -+ .remove = gemini_ethernet_port_remove, -+}; -+ -+static int gemini_ethernet_probe(struct platform_device *pdev) -+{ -+ struct device *dev = &pdev->dev; -+ struct gemini_ethernet *geth; -+ unsigned int retry = 5; -+ struct resource *res; -+ u32 val; -+ -+ /* Global registers */ -+ geth = devm_kzalloc(dev, sizeof(*geth), GFP_KERNEL); -+ if (!geth) -+ return -ENOMEM; -+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); -+ if (!res) -+ return -ENODEV; -+ geth->base = devm_ioremap_resource(dev, res); -+ if (IS_ERR(geth->base)) -+ return PTR_ERR(geth->base); -+ geth->dev = dev; -+ -+ /* Wait for ports to stabilize */ -+ do { -+ udelay(2); -+ val = readl(geth->base + GLOBAL_TOE_VERSION_REG); -+ barrier(); -+ } while (!val && --retry); -+ if (!retry) { -+ dev_err(dev, "failed to reset ethernet\n"); -+ return -EIO; -+ } -+ dev_info(dev, "Ethernet device ID: 0x%03x, revision 0x%01x\n", -+ (val >> 4) & 0xFFFU, val & 0xFU); -+ -+ spin_lock_init(&geth->irq_lock); -+ spin_lock_init(&geth->freeq_lock); -+ gemini_ethernet_init(geth); -+ -+ /* The children will use this */ -+ platform_set_drvdata(pdev, geth); -+ -+ /* Spawn child devices for the two ports */ -+ return devm_of_platform_populate(dev); -+} -+ -+static int gemini_ethernet_remove(struct platform_device *pdev) -+{ -+ struct gemini_ethernet *geth = platform_get_drvdata(pdev); -+ -+ gemini_ethernet_init(geth); -+ geth_cleanup_freeq(geth); -+ -+ return 0; -+} -+ -+static const struct of_device_id gemini_ethernet_of_match[] = { -+ { -+ .compatible = "cortina,gemini-ethernet", -+ }, -+ {}, -+}; -+MODULE_DEVICE_TABLE(of, gemini_ethernet_of_match); -+ -+static struct platform_driver gemini_ethernet_driver = { -+ .driver = { -+ .name = DRV_NAME, -+ .of_match_table = of_match_ptr(gemini_ethernet_of_match), -+ }, -+ .probe = gemini_ethernet_probe, -+ .remove = gemini_ethernet_remove, -+}; -+ -+static int __init gemini_ethernet_module_init(void) -+{ -+ int ret; -+ -+ ret = platform_driver_register(&gemini_ethernet_port_driver); -+ if (ret) -+ return ret; -+ -+ ret = platform_driver_register(&gemini_ethernet_driver); -+ if (ret) { -+ platform_driver_unregister(&gemini_ethernet_port_driver); -+ return ret; -+ } -+ -+ return 0; -+} -+module_init(gemini_ethernet_module_init); -+ -+static void __exit gemini_ethernet_module_exit(void) -+{ -+ platform_driver_unregister(&gemini_ethernet_driver); -+ platform_driver_unregister(&gemini_ethernet_port_driver); -+} -+module_exit(gemini_ethernet_module_exit); -+ -+MODULE_AUTHOR("Linus Walleij "); -+MODULE_DESCRIPTION("StorLink SL351x (Gemini) ethernet driver"); -+MODULE_LICENSE("GPL"); -+MODULE_ALIAS("platform:" DRV_NAME); ---- /dev/null -+++ b/drivers/net/ethernet/cortina/gemini.h -@@ -0,0 +1,958 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* Register definitions for Gemini GMAC Ethernet device driver -+ * -+ * Copyright (C) 2006 Storlink, Corp. -+ * Copyright (C) 2008-2009 Paulius Zaleckas -+ * Copyright (C) 2010 MichaÅ‚ MirosÅ‚aw -+ * Copytight (C) 2017 Linus Walleij -+ */ -+#ifndef _GEMINI_ETHERNET_H -+#define _GEMINI_ETHERNET_H -+ -+#include -+ -+/* Base Registers */ -+#define TOE_NONTOE_QUE_HDR_BASE 0x2000 -+#define TOE_TOE_QUE_HDR_BASE 0x3000 -+ -+/* Queue ID */ -+#define TOE_SW_FREE_QID 0x00 -+#define TOE_HW_FREE_QID 0x01 -+#define TOE_GMAC0_SW_TXQ0_QID 0x02 -+#define TOE_GMAC0_SW_TXQ1_QID 0x03 -+#define TOE_GMAC0_SW_TXQ2_QID 0x04 -+#define TOE_GMAC0_SW_TXQ3_QID 0x05 -+#define TOE_GMAC0_SW_TXQ4_QID 0x06 -+#define TOE_GMAC0_SW_TXQ5_QID 0x07 -+#define TOE_GMAC0_HW_TXQ0_QID 0x08 -+#define TOE_GMAC0_HW_TXQ1_QID 0x09 -+#define TOE_GMAC0_HW_TXQ2_QID 0x0A -+#define TOE_GMAC0_HW_TXQ3_QID 0x0B -+#define TOE_GMAC1_SW_TXQ0_QID 0x12 -+#define TOE_GMAC1_SW_TXQ1_QID 0x13 -+#define TOE_GMAC1_SW_TXQ2_QID 0x14 -+#define TOE_GMAC1_SW_TXQ3_QID 0x15 -+#define TOE_GMAC1_SW_TXQ4_QID 0x16 -+#define TOE_GMAC1_SW_TXQ5_QID 0x17 -+#define TOE_GMAC1_HW_TXQ0_QID 0x18 -+#define TOE_GMAC1_HW_TXQ1_QID 0x19 -+#define TOE_GMAC1_HW_TXQ2_QID 0x1A -+#define TOE_GMAC1_HW_TXQ3_QID 0x1B -+#define TOE_GMAC0_DEFAULT_QID 0x20 -+#define TOE_GMAC1_DEFAULT_QID 0x21 -+#define TOE_CLASSIFICATION_QID(x) (0x22 + x) /* 0x22 ~ 0x2F */ -+#define TOE_TOE_QID(x) (0x40 + x) /* 0x40 ~ 0x7F */ -+ -+/* TOE DMA Queue Size should be 2^n, n = 6...12 -+ * TOE DMA Queues are the following queue types: -+ * SW Free Queue, HW Free Queue, -+ * GMAC 0/1 SW TX Q0-5, and GMAC 0/1 HW TX Q0-5 -+ * The base address and descriptor number are configured at -+ * DMA Queues Descriptor Ring Base Address/Size Register (offset 0x0004) -+ */ -+#define GET_WPTR(addr) readw((addr) + 2) -+#define GET_RPTR(addr) readw((addr)) -+#define SET_WPTR(addr, data) writew((data), (addr) + 2) -+#define SET_RPTR(addr, data) writew((data), (addr)) -+#define __RWPTR_NEXT(x, mask) (((unsigned int)(x) + 1) & (mask)) -+#define __RWPTR_PREV(x, mask) (((unsigned int)(x) - 1) & (mask)) -+#define __RWPTR_DISTANCE(r, w, mask) (((unsigned int)(w) - (r)) & (mask)) -+#define __RWPTR_MASK(order) ((1 << (order)) - 1) -+#define RWPTR_NEXT(x, order) __RWPTR_NEXT((x), __RWPTR_MASK((order))) -+#define RWPTR_PREV(x, order) __RWPTR_PREV((x), __RWPTR_MASK((order))) -+#define RWPTR_DISTANCE(r, w, order) __RWPTR_DISTANCE((r), (w), \ -+ __RWPTR_MASK((order))) -+ -+/* Global registers */ -+#define GLOBAL_TOE_VERSION_REG 0x0000 -+#define GLOBAL_SW_FREEQ_BASE_SIZE_REG 0x0004 -+#define GLOBAL_HW_FREEQ_BASE_SIZE_REG 0x0008 -+#define GLOBAL_DMA_SKB_SIZE_REG 0x0010 -+#define GLOBAL_SWFQ_RWPTR_REG 0x0014 -+#define GLOBAL_HWFQ_RWPTR_REG 0x0018 -+#define GLOBAL_INTERRUPT_STATUS_0_REG 0x0020 -+#define GLOBAL_INTERRUPT_ENABLE_0_REG 0x0024 -+#define GLOBAL_INTERRUPT_SELECT_0_REG 0x0028 -+#define GLOBAL_INTERRUPT_STATUS_1_REG 0x0030 -+#define GLOBAL_INTERRUPT_ENABLE_1_REG 0x0034 -+#define GLOBAL_INTERRUPT_SELECT_1_REG 0x0038 -+#define GLOBAL_INTERRUPT_STATUS_2_REG 0x0040 -+#define GLOBAL_INTERRUPT_ENABLE_2_REG 0x0044 -+#define GLOBAL_INTERRUPT_SELECT_2_REG 0x0048 -+#define GLOBAL_INTERRUPT_STATUS_3_REG 0x0050 -+#define GLOBAL_INTERRUPT_ENABLE_3_REG 0x0054 -+#define GLOBAL_INTERRUPT_SELECT_3_REG 0x0058 -+#define GLOBAL_INTERRUPT_STATUS_4_REG 0x0060 -+#define GLOBAL_INTERRUPT_ENABLE_4_REG 0x0064 -+#define GLOBAL_INTERRUPT_SELECT_4_REG 0x0068 -+#define GLOBAL_HASH_TABLE_BASE_REG 0x006C -+#define GLOBAL_QUEUE_THRESHOLD_REG 0x0070 -+ -+/* GMAC 0/1 DMA/TOE register */ -+#define GMAC_DMA_CTRL_REG 0x0000 -+#define GMAC_TX_WEIGHTING_CTRL_0_REG 0x0004 -+#define GMAC_TX_WEIGHTING_CTRL_1_REG 0x0008 -+#define GMAC_SW_TX_QUEUE0_PTR_REG 0x000C -+#define GMAC_SW_TX_QUEUE1_PTR_REG 0x0010 -+#define GMAC_SW_TX_QUEUE2_PTR_REG 0x0014 -+#define GMAC_SW_TX_QUEUE3_PTR_REG 0x0018 -+#define GMAC_SW_TX_QUEUE4_PTR_REG 0x001C -+#define GMAC_SW_TX_QUEUE5_PTR_REG 0x0020 -+#define GMAC_SW_TX_QUEUE_PTR_REG(i) (GMAC_SW_TX_QUEUE0_PTR_REG + 4 * (i)) -+#define GMAC_HW_TX_QUEUE0_PTR_REG 0x0024 -+#define GMAC_HW_TX_QUEUE1_PTR_REG 0x0028 -+#define GMAC_HW_TX_QUEUE2_PTR_REG 0x002C -+#define GMAC_HW_TX_QUEUE3_PTR_REG 0x0030 -+#define GMAC_HW_TX_QUEUE_PTR_REG(i) (GMAC_HW_TX_QUEUE0_PTR_REG + 4 * (i)) -+#define GMAC_DMA_TX_FIRST_DESC_REG 0x0038 -+#define GMAC_DMA_TX_CURR_DESC_REG 0x003C -+#define GMAC_DMA_TX_DESC_WORD0_REG 0x0040 -+#define GMAC_DMA_TX_DESC_WORD1_REG 0x0044 -+#define GMAC_DMA_TX_DESC_WORD2_REG 0x0048 -+#define GMAC_DMA_TX_DESC_WORD3_REG 0x004C -+#define GMAC_SW_TX_QUEUE_BASE_REG 0x0050 -+#define GMAC_HW_TX_QUEUE_BASE_REG 0x0054 -+#define GMAC_DMA_RX_FIRST_DESC_REG 0x0058 -+#define GMAC_DMA_RX_CURR_DESC_REG 0x005C -+#define GMAC_DMA_RX_DESC_WORD0_REG 0x0060 -+#define GMAC_DMA_RX_DESC_WORD1_REG 0x0064 -+#define GMAC_DMA_RX_DESC_WORD2_REG 0x0068 -+#define GMAC_DMA_RX_DESC_WORD3_REG 0x006C -+#define GMAC_HASH_ENGINE_REG0 0x0070 -+#define GMAC_HASH_ENGINE_REG1 0x0074 -+/* matching rule 0 Control register 0 */ -+#define GMAC_MR0CR0 0x0078 -+#define GMAC_MR0CR1 0x007C -+#define GMAC_MR0CR2 0x0080 -+#define GMAC_MR1CR0 0x0084 -+#define GMAC_MR1CR1 0x0088 -+#define GMAC_MR1CR2 0x008C -+#define GMAC_MR2CR0 0x0090 -+#define GMAC_MR2CR1 0x0094 -+#define GMAC_MR2CR2 0x0098 -+#define GMAC_MR3CR0 0x009C -+#define GMAC_MR3CR1 0x00A0 -+#define GMAC_MR3CR2 0x00A4 -+/* Support Protocol Register 0 */ -+#define GMAC_SPR0 0x00A8 -+#define GMAC_SPR1 0x00AC -+#define GMAC_SPR2 0x00B0 -+#define GMAC_SPR3 0x00B4 -+#define GMAC_SPR4 0x00B8 -+#define GMAC_SPR5 0x00BC -+#define GMAC_SPR6 0x00C0 -+#define GMAC_SPR7 0x00C4 -+/* GMAC Hash/Rx/Tx AHB Weighting register */ -+#define GMAC_AHB_WEIGHT_REG 0x00C8 -+ -+/* TOE GMAC 0/1 register */ -+#define GMAC_STA_ADD0 0x0000 -+#define GMAC_STA_ADD1 0x0004 -+#define GMAC_STA_ADD2 0x0008 -+#define GMAC_RX_FLTR 0x000c -+#define GMAC_MCAST_FIL0 0x0010 -+#define GMAC_MCAST_FIL1 0x0014 -+#define GMAC_CONFIG0 0x0018 -+#define GMAC_CONFIG1 0x001c -+#define GMAC_CONFIG2 0x0020 -+#define GMAC_CONFIG3 0x0024 -+#define GMAC_RESERVED 0x0028 -+#define GMAC_STATUS 0x002c -+#define GMAC_IN_DISCARDS 0x0030 -+#define GMAC_IN_ERRORS 0x0034 -+#define GMAC_IN_MCAST 0x0038 -+#define GMAC_IN_BCAST 0x003c -+#define GMAC_IN_MAC1 0x0040 /* for STA 1 MAC Address */ -+#define GMAC_IN_MAC2 0x0044 /* for STA 2 MAC Address */ -+ -+#define RX_STATS_NUM 6 -+ -+/* DMA Queues description Ring Base Address/Size Register (offset 0x0004) */ -+union dma_q_base_size { -+ unsigned int bits32; -+ unsigned int base_size; -+}; -+ -+#define DMA_Q_BASE_MASK (~0x0f) -+ -+/* DMA SKB Buffer register (offset 0x0008) */ -+union dma_skb_size { -+ unsigned int bits32; -+ struct bit_0008 { -+ unsigned int sw_skb_size : 16; /* SW Free poll SKB Size */ -+ unsigned int hw_skb_size : 16; /* HW Free poll SKB Size */ -+ } bits; -+}; -+ -+/* DMA SW Free Queue Read/Write Pointer Register (offset 0x000c) */ -+union dma_rwptr { -+ unsigned int bits32; -+ struct bit_000c { -+ unsigned int rptr : 16; /* Read Ptr, RO */ -+ unsigned int wptr : 16; /* Write Ptr, RW */ -+ } bits; -+}; -+ -+/* Interrupt Status Register 0 (offset 0x0020) -+ * Interrupt Mask Register 0 (offset 0x0024) -+ * Interrupt Select Register 0 (offset 0x0028) -+ */ -+#define GMAC1_TXDERR_INT_BIT BIT(31) -+#define GMAC1_TXPERR_INT_BIT BIT(30) -+#define GMAC0_TXDERR_INT_BIT BIT(29) -+#define GMAC0_TXPERR_INT_BIT BIT(28) -+#define GMAC1_RXDERR_INT_BIT BIT(27) -+#define GMAC1_RXPERR_INT_BIT BIT(26) -+#define GMAC0_RXDERR_INT_BIT BIT(25) -+#define GMAC0_RXPERR_INT_BIT BIT(24) -+#define GMAC1_SWTQ15_FIN_INT_BIT BIT(23) -+#define GMAC1_SWTQ14_FIN_INT_BIT BIT(22) -+#define GMAC1_SWTQ13_FIN_INT_BIT BIT(21) -+#define GMAC1_SWTQ12_FIN_INT_BIT BIT(20) -+#define GMAC1_SWTQ11_FIN_INT_BIT BIT(19) -+#define GMAC1_SWTQ10_FIN_INT_BIT BIT(18) -+#define GMAC0_SWTQ05_FIN_INT_BIT BIT(17) -+#define GMAC0_SWTQ04_FIN_INT_BIT BIT(16) -+#define GMAC0_SWTQ03_FIN_INT_BIT BIT(15) -+#define GMAC0_SWTQ02_FIN_INT_BIT BIT(14) -+#define GMAC0_SWTQ01_FIN_INT_BIT BIT(13) -+#define GMAC0_SWTQ00_FIN_INT_BIT BIT(12) -+#define GMAC1_SWTQ15_EOF_INT_BIT BIT(11) -+#define GMAC1_SWTQ14_EOF_INT_BIT BIT(10) -+#define GMAC1_SWTQ13_EOF_INT_BIT BIT(9) -+#define GMAC1_SWTQ12_EOF_INT_BIT BIT(8) -+#define GMAC1_SWTQ11_EOF_INT_BIT BIT(7) -+#define GMAC1_SWTQ10_EOF_INT_BIT BIT(6) -+#define GMAC0_SWTQ05_EOF_INT_BIT BIT(5) -+#define GMAC0_SWTQ04_EOF_INT_BIT BIT(4) -+#define GMAC0_SWTQ03_EOF_INT_BIT BIT(3) -+#define GMAC0_SWTQ02_EOF_INT_BIT BIT(2) -+#define GMAC0_SWTQ01_EOF_INT_BIT BIT(1) -+#define GMAC0_SWTQ00_EOF_INT_BIT BIT(0) -+ -+/* Interrupt Status Register 1 (offset 0x0030) -+ * Interrupt Mask Register 1 (offset 0x0034) -+ * Interrupt Select Register 1 (offset 0x0038) -+ */ -+#define TOE_IQ3_FULL_INT_BIT BIT(31) -+#define TOE_IQ2_FULL_INT_BIT BIT(30) -+#define TOE_IQ1_FULL_INT_BIT BIT(29) -+#define TOE_IQ0_FULL_INT_BIT BIT(28) -+#define TOE_IQ3_INT_BIT BIT(27) -+#define TOE_IQ2_INT_BIT BIT(26) -+#define TOE_IQ1_INT_BIT BIT(25) -+#define TOE_IQ0_INT_BIT BIT(24) -+#define GMAC1_HWTQ13_EOF_INT_BIT BIT(23) -+#define GMAC1_HWTQ12_EOF_INT_BIT BIT(22) -+#define GMAC1_HWTQ11_EOF_INT_BIT BIT(21) -+#define GMAC1_HWTQ10_EOF_INT_BIT BIT(20) -+#define GMAC0_HWTQ03_EOF_INT_BIT BIT(19) -+#define GMAC0_HWTQ02_EOF_INT_BIT BIT(18) -+#define GMAC0_HWTQ01_EOF_INT_BIT BIT(17) -+#define GMAC0_HWTQ00_EOF_INT_BIT BIT(16) -+#define CLASS_RX_INT_BIT(x) BIT((x + 2)) -+#define DEFAULT_Q1_INT_BIT BIT(1) -+#define DEFAULT_Q0_INT_BIT BIT(0) -+ -+#define TOE_IQ_INT_BITS (TOE_IQ0_INT_BIT | TOE_IQ1_INT_BIT | \ -+ TOE_IQ2_INT_BIT | TOE_IQ3_INT_BIT) -+#define TOE_IQ_FULL_BITS (TOE_IQ0_FULL_INT_BIT | TOE_IQ1_FULL_INT_BIT | \ -+ TOE_IQ2_FULL_INT_BIT | TOE_IQ3_FULL_INT_BIT) -+#define TOE_IQ_ALL_BITS (TOE_IQ_INT_BITS | TOE_IQ_FULL_BITS) -+#define TOE_CLASS_RX_INT_BITS 0xfffc -+ -+/* Interrupt Status Register 2 (offset 0x0040) -+ * Interrupt Mask Register 2 (offset 0x0044) -+ * Interrupt Select Register 2 (offset 0x0048) -+ */ -+#define TOE_QL_FULL_INT_BIT(x) BIT(x) -+ -+/* Interrupt Status Register 3 (offset 0x0050) -+ * Interrupt Mask Register 3 (offset 0x0054) -+ * Interrupt Select Register 3 (offset 0x0058) -+ */ -+#define TOE_QH_FULL_INT_BIT(x) BIT(x - 32) -+ -+/* Interrupt Status Register 4 (offset 0x0060) -+ * Interrupt Mask Register 4 (offset 0x0064) -+ * Interrupt Select Register 4 (offset 0x0068) -+ */ -+#define GMAC1_RESERVED_INT_BIT BIT(31) -+#define GMAC1_MIB_INT_BIT BIT(30) -+#define GMAC1_RX_PAUSE_ON_INT_BIT BIT(29) -+#define GMAC1_TX_PAUSE_ON_INT_BIT BIT(28) -+#define GMAC1_RX_PAUSE_OFF_INT_BIT BIT(27) -+#define GMAC1_TX_PAUSE_OFF_INT_BIT BIT(26) -+#define GMAC1_RX_OVERRUN_INT_BIT BIT(25) -+#define GMAC1_STATUS_CHANGE_INT_BIT BIT(24) -+#define GMAC0_RESERVED_INT_BIT BIT(23) -+#define GMAC0_MIB_INT_BIT BIT(22) -+#define GMAC0_RX_PAUSE_ON_INT_BIT BIT(21) -+#define GMAC0_TX_PAUSE_ON_INT_BIT BIT(20) -+#define GMAC0_RX_PAUSE_OFF_INT_BIT BIT(19) -+#define GMAC0_TX_PAUSE_OFF_INT_BIT BIT(18) -+#define GMAC0_RX_OVERRUN_INT_BIT BIT(17) -+#define GMAC0_STATUS_CHANGE_INT_BIT BIT(16) -+#define CLASS_RX_FULL_INT_BIT(x) BIT(x + 2) -+#define HWFQ_EMPTY_INT_BIT BIT(1) -+#define SWFQ_EMPTY_INT_BIT BIT(0) -+ -+#define GMAC0_INT_BITS (GMAC0_RESERVED_INT_BIT | GMAC0_MIB_INT_BIT | \ -+ GMAC0_RX_PAUSE_ON_INT_BIT | \ -+ GMAC0_TX_PAUSE_ON_INT_BIT | \ -+ GMAC0_RX_PAUSE_OFF_INT_BIT | \ -+ GMAC0_TX_PAUSE_OFF_INT_BIT | \ -+ GMAC0_RX_OVERRUN_INT_BIT | \ -+ GMAC0_STATUS_CHANGE_INT_BIT) -+#define GMAC1_INT_BITS (GMAC1_RESERVED_INT_BIT | GMAC1_MIB_INT_BIT | \ -+ GMAC1_RX_PAUSE_ON_INT_BIT | \ -+ GMAC1_TX_PAUSE_ON_INT_BIT | \ -+ GMAC1_RX_PAUSE_OFF_INT_BIT | \ -+ GMAC1_TX_PAUSE_OFF_INT_BIT | \ -+ GMAC1_RX_OVERRUN_INT_BIT | \ -+ GMAC1_STATUS_CHANGE_INT_BIT) -+ -+#define CLASS_RX_FULL_INT_BITS 0xfffc -+ -+/* GLOBAL_QUEUE_THRESHOLD_REG (offset 0x0070) */ -+union queue_threshold { -+ unsigned int bits32; -+ struct bit_0070_2 { -+ /* 7:0 Software Free Queue Empty Threshold */ -+ unsigned int swfq_empty:8; -+ /* 15:8 Hardware Free Queue Empty Threshold */ -+ unsigned int hwfq_empty:8; -+ /* 23:16 */ -+ unsigned int intrq:8; -+ /* 31:24 */ -+ unsigned int toe_class:8; -+ } bits; -+}; -+ -+/* GMAC DMA Control Register -+ * GMAC0 offset 0x8000 -+ * GMAC1 offset 0xC000 -+ */ -+union gmac_dma_ctrl { -+ unsigned int bits32; -+ struct bit_8000 { -+ /* bit 1:0 Peripheral Bus Width */ -+ unsigned int td_bus:2; -+ /* bit 3:2 TxDMA max burst size for every AHB request */ -+ unsigned int td_burst_size:2; -+ /* bit 7:4 TxDMA protection control */ -+ unsigned int td_prot:4; -+ /* bit 9:8 Peripheral Bus Width */ -+ unsigned int rd_bus:2; -+ /* bit 11:10 DMA max burst size for every AHB request */ -+ unsigned int rd_burst_size:2; -+ /* bit 15:12 DMA Protection Control */ -+ unsigned int rd_prot:4; -+ /* bit 17:16 */ -+ unsigned int rd_insert_bytes:2; -+ /* bit 27:18 */ -+ unsigned int reserved:10; -+ /* bit 28 1: Drop, 0: Accept */ -+ unsigned int drop_small_ack:1; -+ /* bit 29 Loopback TxDMA to RxDMA */ -+ unsigned int loopback:1; -+ /* bit 30 Tx DMA Enable */ -+ unsigned int td_enable:1; -+ /* bit 31 Rx DMA Enable */ -+ unsigned int rd_enable:1; -+ } bits; -+}; -+ -+/* GMAC Tx Weighting Control Register 0 -+ * GMAC0 offset 0x8004 -+ * GMAC1 offset 0xC004 -+ */ -+union gmac_tx_wcr0 { -+ unsigned int bits32; -+ struct bit_8004 { -+ /* bit 5:0 HW TX Queue 3 */ -+ unsigned int hw_tq0:6; -+ /* bit 11:6 HW TX Queue 2 */ -+ unsigned int hw_tq1:6; -+ /* bit 17:12 HW TX Queue 1 */ -+ unsigned int hw_tq2:6; -+ /* bit 23:18 HW TX Queue 0 */ -+ unsigned int hw_tq3:6; -+ /* bit 31:24 */ -+ unsigned int reserved:8; -+ } bits; -+}; -+ -+/* GMAC Tx Weighting Control Register 1 -+ * GMAC0 offset 0x8008 -+ * GMAC1 offset 0xC008 -+ */ -+union gmac_tx_wcr1 { -+ unsigned int bits32; -+ struct bit_8008 { -+ /* bit 4:0 SW TX Queue 0 */ -+ unsigned int sw_tq0:5; -+ /* bit 9:5 SW TX Queue 1 */ -+ unsigned int sw_tq1:5; -+ /* bit 14:10 SW TX Queue 2 */ -+ unsigned int sw_tq2:5; -+ /* bit 19:15 SW TX Queue 3 */ -+ unsigned int sw_tq3:5; -+ /* bit 24:20 SW TX Queue 4 */ -+ unsigned int sw_tq4:5; -+ /* bit 29:25 SW TX Queue 5 */ -+ unsigned int sw_tq5:5; -+ /* bit 31:30 */ -+ unsigned int reserved:2; -+ } bits; -+}; -+ -+/* GMAC DMA Tx Description Word 0 Register -+ * GMAC0 offset 0x8040 -+ * GMAC1 offset 0xC040 -+ */ -+union gmac_txdesc_0 { -+ unsigned int bits32; -+ struct bit_8040 { -+ /* bit 15:0 Transfer size */ -+ unsigned int buffer_size:16; -+ /* bit 21:16 number of descriptors used for the current frame */ -+ unsigned int desc_count:6; -+ /* bit 22 Tx Status, 1: Successful 0: Failed */ -+ unsigned int status_tx_ok:1; -+ /* bit 28:23 Tx Status, Reserved bits */ -+ unsigned int status_rvd:6; -+ /* bit 29 protocol error during processing this descriptor */ -+ unsigned int perr:1; -+ /* bit 30 data error during processing this descriptor */ -+ unsigned int derr:1; -+ /* bit 31 */ -+ unsigned int reserved:1; -+ } bits; -+}; -+ -+/* GMAC DMA Tx Description Word 1 Register -+ * GMAC0 offset 0x8044 -+ * GMAC1 offset 0xC044 -+ */ -+union gmac_txdesc_1 { -+ unsigned int bits32; -+ struct txdesc_word1 { -+ /* bit 15: 0 Tx Frame Byte Count */ -+ unsigned int byte_count:16; -+ /* bit 16 TSS segmentation use MTU setting */ -+ unsigned int mtu_enable:1; -+ /* bit 17 IPV4 Header Checksum Enable */ -+ unsigned int ip_chksum:1; -+ /* bit 18 IPV6 Tx Enable */ -+ unsigned int ipv6_enable:1; -+ /* bit 19 TCP Checksum Enable */ -+ unsigned int tcp_chksum:1; -+ /* bit 20 UDP Checksum Enable */ -+ unsigned int udp_chksum:1; -+ /* bit 21 Bypass HW offload engine */ -+ unsigned int bypass_tss:1; -+ /* bit 22 Don't update IP length field */ -+ unsigned int ip_fixed_len:1; -+ /* bit 31:23 Tx Flag, Reserved */ -+ unsigned int reserved:9; -+ } bits; -+}; -+ -+#define TSS_IP_FIXED_LEN_BIT BIT(22) -+#define TSS_BYPASS_BIT BIT(21) -+#define TSS_UDP_CHKSUM_BIT BIT(20) -+#define TSS_TCP_CHKSUM_BIT BIT(19) -+#define TSS_IPV6_ENABLE_BIT BIT(18) -+#define TSS_IP_CHKSUM_BIT BIT(17) -+#define TSS_MTU_ENABLE_BIT BIT(16) -+ -+#define TSS_CHECKUM_ENABLE \ -+ (TSS_IP_CHKSUM_BIT | TSS_IPV6_ENABLE_BIT | \ -+ TSS_TCP_CHKSUM_BIT | TSS_UDP_CHKSUM_BIT) -+ -+/* GMAC DMA Tx Description Word 2 Register -+ * GMAC0 offset 0x8048 -+ * GMAC1 offset 0xC048 -+ */ -+union gmac_txdesc_2 { -+ unsigned int bits32; -+ unsigned int buf_adr; -+}; -+ -+/* GMAC DMA Tx Description Word 3 Register -+ * GMAC0 offset 0x804C -+ * GMAC1 offset 0xC04C -+ */ -+union gmac_txdesc_3 { -+ unsigned int bits32; -+ struct txdesc_word3 { -+ /* bit 12: 0 Tx Frame Byte Count */ -+ unsigned int mtu_size:13; -+ /* bit 28:13 */ -+ unsigned int reserved:16; -+ /* bit 29 End of frame interrupt enable */ -+ unsigned int eofie:1; -+ /* bit 31:30 11: only one, 10: first, 01: last, 00: linking */ -+ unsigned int sof_eof:2; -+ } bits; -+}; -+ -+#define SOF_EOF_BIT_MASK 0x3fffffff -+#define SOF_BIT 0x80000000 -+#define EOF_BIT 0x40000000 -+#define EOFIE_BIT BIT(29) -+#define MTU_SIZE_BIT_MASK 0x1fff -+ -+/* GMAC Tx Descriptor */ -+struct gmac_txdesc { -+ union gmac_txdesc_0 word0; -+ union gmac_txdesc_1 word1; -+ union gmac_txdesc_2 word2; -+ union gmac_txdesc_3 word3; -+}; -+ -+/* GMAC DMA Rx Description Word 0 Register -+ * GMAC0 offset 0x8060 -+ * GMAC1 offset 0xC060 -+ */ -+union gmac_rxdesc_0 { -+ unsigned int bits32; -+ struct bit_8060 { -+ /* bit 15:0 number of descriptors used for the current frame */ -+ unsigned int buffer_size:16; -+ /* bit 21:16 number of descriptors used for the current frame */ -+ unsigned int desc_count:6; -+ /* bit 24:22 Status of rx frame */ -+ unsigned int status:4; -+ /* bit 28:26 Check Sum Status */ -+ unsigned int chksum_status:3; -+ /* bit 29 protocol error during processing this descriptor */ -+ unsigned int perr:1; -+ /* bit 30 data error during processing this descriptor */ -+ unsigned int derr:1; -+ /* bit 31 TOE/CIS Queue Full dropped packet to default queue */ -+ unsigned int drop:1; -+ } bits; -+}; -+ -+#define GMAC_RXDESC_0_T_derr BIT(30) -+#define GMAC_RXDESC_0_T_perr BIT(29) -+#define GMAC_RXDESC_0_T_chksum_status(x) BIT(x + 26) -+#define GMAC_RXDESC_0_T_status(x) BIT(x + 22) -+#define GMAC_RXDESC_0_T_desc_count(x) BIT(x + 16) -+ -+#define RX_CHKSUM_IP_UDP_TCP_OK 0 -+#define RX_CHKSUM_IP_OK_ONLY 1 -+#define RX_CHKSUM_NONE 2 -+#define RX_CHKSUM_IP_ERR_UNKNOWN 4 -+#define RX_CHKSUM_IP_ERR 5 -+#define RX_CHKSUM_TCP_UDP_ERR 6 -+#define RX_CHKSUM_NUM 8 -+ -+#define RX_STATUS_GOOD_FRAME 0 -+#define RX_STATUS_TOO_LONG_GOOD_CRC 1 -+#define RX_STATUS_RUNT_FRAME 2 -+#define RX_STATUS_SFD_NOT_FOUND 3 -+#define RX_STATUS_CRC_ERROR 4 -+#define RX_STATUS_TOO_LONG_BAD_CRC 5 -+#define RX_STATUS_ALIGNMENT_ERROR 6 -+#define RX_STATUS_TOO_LONG_BAD_ALIGN 7 -+#define RX_STATUS_RX_ERR 8 -+#define RX_STATUS_DA_FILTERED 9 -+#define RX_STATUS_BUFFER_FULL 10 -+#define RX_STATUS_NUM 16 -+ -+#define RX_ERROR_LENGTH(s) \ -+ ((s) == RX_STATUS_TOO_LONG_GOOD_CRC || \ -+ (s) == RX_STATUS_TOO_LONG_BAD_CRC || \ -+ (s) == RX_STATUS_TOO_LONG_BAD_ALIGN) -+#define RX_ERROR_OVER(s) \ -+ ((s) == RX_STATUS_BUFFER_FULL) -+#define RX_ERROR_CRC(s) \ -+ ((s) == RX_STATUS_CRC_ERROR || \ -+ (s) == RX_STATUS_TOO_LONG_BAD_CRC) -+#define RX_ERROR_FRAME(s) \ -+ ((s) == RX_STATUS_ALIGNMENT_ERROR || \ -+ (s) == RX_STATUS_TOO_LONG_BAD_ALIGN) -+#define RX_ERROR_FIFO(s) \ -+ (0) -+ -+/* GMAC DMA Rx Description Word 1 Register -+ * GMAC0 offset 0x8064 -+ * GMAC1 offset 0xC064 -+ */ -+union gmac_rxdesc_1 { -+ unsigned int bits32; -+ struct rxdesc_word1 { -+ /* bit 15: 0 Rx Frame Byte Count */ -+ unsigned int byte_count:16; -+ /* bit 31:16 Software ID */ -+ unsigned int sw_id:16; -+ } bits; -+}; -+ -+/* GMAC DMA Rx Description Word 2 Register -+ * GMAC0 offset 0x8068 -+ * GMAC1 offset 0xC068 -+ */ -+union gmac_rxdesc_2 { -+ unsigned int bits32; -+ unsigned int buf_adr; -+}; -+ -+#define RX_INSERT_NONE 0 -+#define RX_INSERT_1_BYTE 1 -+#define RX_INSERT_2_BYTE 2 -+#define RX_INSERT_3_BYTE 3 -+ -+/* GMAC DMA Rx Description Word 3 Register -+ * GMAC0 offset 0x806C -+ * GMAC1 offset 0xC06C -+ */ -+union gmac_rxdesc_3 { -+ unsigned int bits32; -+ struct rxdesc_word3 { -+ /* bit 7: 0 L3 data offset */ -+ unsigned int l3_offset:8; -+ /* bit 15: 8 L4 data offset */ -+ unsigned int l4_offset:8; -+ /* bit 23: 16 L7 data offset */ -+ unsigned int l7_offset:8; -+ /* bit 24 Duplicated ACK detected */ -+ unsigned int dup_ack:1; -+ /* bit 25 abnormal case found */ -+ unsigned int abnormal:1; -+ /* bit 26 IPV4 option or IPV6 extension header */ -+ unsigned int option:1; -+ /* bit 27 Out of Sequence packet */ -+ unsigned int out_of_seq:1; -+ /* bit 28 Control Flag is present */ -+ unsigned int ctrl_flag:1; -+ /* bit 29 End of frame interrupt enable */ -+ unsigned int eofie:1; -+ /* bit 31:30 11: only one, 10: first, 01: last, 00: linking */ -+ unsigned int sof_eof:2; -+ } bits; -+}; -+ -+/* GMAC Rx Descriptor, this is simply fitted over the queue registers */ -+struct gmac_rxdesc { -+ union gmac_rxdesc_0 word0; -+ union gmac_rxdesc_1 word1; -+ union gmac_rxdesc_2 word2; -+ union gmac_rxdesc_3 word3; -+}; -+ -+/* GMAC Matching Rule Control Register 0 -+ * GMAC0 offset 0x8078 -+ * GMAC1 offset 0xC078 -+ */ -+#define MR_L2_BIT BIT(31) -+#define MR_L3_BIT BIT(30) -+#define MR_L4_BIT BIT(29) -+#define MR_L7_BIT BIT(28) -+#define MR_PORT_BIT BIT(27) -+#define MR_PRIORITY_BIT BIT(26) -+#define MR_DA_BIT BIT(23) -+#define MR_SA_BIT BIT(22) -+#define MR_ETHER_TYPE_BIT BIT(21) -+#define MR_VLAN_BIT BIT(20) -+#define MR_PPPOE_BIT BIT(19) -+#define MR_IP_VER_BIT BIT(15) -+#define MR_IP_HDR_LEN_BIT BIT(14) -+#define MR_FLOW_LABLE_BIT BIT(13) -+#define MR_TOS_TRAFFIC_BIT BIT(12) -+#define MR_SPR_BIT(x) BIT(x) -+#define MR_SPR_BITS 0xff -+ -+/* GMAC_AHB_WEIGHT registers -+ * GMAC0 offset 0x80C8 -+ * GMAC1 offset 0xC0C8 -+ */ -+union gmac_ahb_weight { -+ unsigned int bits32; -+ struct bit_80C8 { -+ /* 4:0 */ -+ unsigned int hash_weight:5; -+ /* 9:5 */ -+ unsigned int rx_weight:5; -+ /* 14:10 */ -+ unsigned int tx_weight:5; -+ /* 19:15 Rx Data Pre Request FIFO Threshold */ -+ unsigned int pre_req:5; -+ /* 24:20 DMA TqCtrl to Start tqDV FIFO Threshold */ -+ unsigned int tq_dv_threshold:5; -+ /* 31:25 */ -+ unsigned int reserved:7; -+ } bits; -+}; -+ -+/* GMAC RX FLTR -+ * GMAC0 Offset 0xA00C -+ * GMAC1 Offset 0xE00C -+ */ -+union gmac_rx_fltr { -+ unsigned int bits32; -+ struct bit1_000c { -+ /* Enable receive of unicast frames that are sent to STA -+ * address -+ */ -+ unsigned int unicast:1; -+ /* Enable receive of multicast frames that pass multicast -+ * filter -+ */ -+ unsigned int multicast:1; -+ /* Enable receive of broadcast frames */ -+ unsigned int broadcast:1; -+ /* Enable receive of all frames */ -+ unsigned int promiscuous:1; -+ /* Enable receive of all error frames */ -+ unsigned int error:1; -+ unsigned int reserved:27; -+ } bits; -+}; -+ -+/* GMAC Configuration 0 -+ * GMAC0 Offset 0xA018 -+ * GMAC1 Offset 0xE018 -+ */ -+union gmac_config0 { -+ unsigned int bits32; -+ struct bit1_0018 { -+ /* 0: disable transmit */ -+ unsigned int dis_tx:1; -+ /* 1: disable receive */ -+ unsigned int dis_rx:1; -+ /* 2: transmit data loopback enable */ -+ unsigned int loop_back:1; -+ /* 3: flow control also trigged by Rx queues */ -+ unsigned int flow_ctrl:1; -+ /* 4-7: adjust IFG from 96+/-56 */ -+ unsigned int adj_ifg:4; -+ /* 8-10 maximum receive frame length allowed */ -+ unsigned int max_len:3; -+ /* 11: disable back-off function */ -+ unsigned int dis_bkoff:1; -+ /* 12: disable 16 collisions abort function */ -+ unsigned int dis_col:1; -+ /* 13: speed up timers in simulation */ -+ unsigned int sim_test:1; -+ /* 14: RX flow control enable */ -+ unsigned int rx_fc_en:1; -+ /* 15: TX flow control enable */ -+ unsigned int tx_fc_en:1; -+ /* 16: RGMII in-band status enable */ -+ unsigned int rgmii_en:1; -+ /* 17: IPv4 RX Checksum enable */ -+ unsigned int ipv4_rx_chksum:1; -+ /* 18: IPv6 RX Checksum enable */ -+ unsigned int ipv6_rx_chksum:1; -+ /* 19: Remove Rx VLAN tag */ -+ unsigned int rx_tag_remove:1; -+ /* 20 */ -+ unsigned int rgmm_edge:1; -+ /* 21 */ -+ unsigned int rxc_inv:1; -+ /* 22 */ -+ unsigned int ipv6_exthdr_order:1; -+ /* 23 */ -+ unsigned int rx_err_detect:1; -+ /* 24 */ -+ unsigned int port0_chk_hwq:1; -+ /* 25 */ -+ unsigned int port1_chk_hwq:1; -+ /* 26 */ -+ unsigned int port0_chk_toeq:1; -+ /* 27 */ -+ unsigned int port1_chk_toeq:1; -+ /* 28 */ -+ unsigned int port0_chk_classq:1; -+ /* 29 */ -+ unsigned int port1_chk_classq:1; -+ /* 30, 31 */ -+ unsigned int reserved:2; -+ } bits; -+}; -+ -+#define CONFIG0_TX_RX_DISABLE (BIT(1) | BIT(0)) -+#define CONFIG0_RX_CHKSUM (BIT(18) | BIT(17)) -+#define CONFIG0_FLOW_RX BIT(14) -+#define CONFIG0_FLOW_TX BIT(15) -+#define CONFIG0_FLOW_TX_RX (BIT(14) | BIT(15)) -+#define CONFIG0_FLOW_CTL (BIT(14) | BIT(15)) -+ -+#define CONFIG0_MAXLEN_SHIFT 8 -+#define CONFIG0_MAXLEN_MASK (7 << CONFIG0_MAXLEN_SHIFT) -+#define CONFIG0_MAXLEN_1536 0 -+#define CONFIG0_MAXLEN_1518 1 -+#define CONFIG0_MAXLEN_1522 2 -+#define CONFIG0_MAXLEN_1542 3 -+#define CONFIG0_MAXLEN_9k 4 /* 9212 */ -+#define CONFIG0_MAXLEN_10k 5 /* 10236 */ -+#define CONFIG0_MAXLEN_1518__6 6 -+#define CONFIG0_MAXLEN_1518__7 7 -+ -+/* GMAC Configuration 1 -+ * GMAC0 Offset 0xA01C -+ * GMAC1 Offset 0xE01C -+ */ -+union gmac_config1 { -+ unsigned int bits32; -+ struct bit1_001c { -+ /* Flow control set threshold */ -+ unsigned int set_threshold:8; -+ /* Flow control release threshold */ -+ unsigned int rel_threshold:8; -+ unsigned int reserved:16; -+ } bits; -+}; -+ -+#define GMAC_FLOWCTRL_SET_MAX 32 -+#define GMAC_FLOWCTRL_SET_MIN 0 -+#define GMAC_FLOWCTRL_RELEASE_MAX 32 -+#define GMAC_FLOWCTRL_RELEASE_MIN 0 -+ -+/* GMAC Configuration 2 -+ * GMAC0 Offset 0xA020 -+ * GMAC1 Offset 0xE020 -+ */ -+union gmac_config2 { -+ unsigned int bits32; -+ struct bit1_0020 { -+ /* Flow control set threshold */ -+ unsigned int set_threshold:16; -+ /* Flow control release threshold */ -+ unsigned int rel_threshold:16; -+ } bits; -+}; -+ -+/* GMAC Configuration 3 -+ * GMAC0 Offset 0xA024 -+ * GMAC1 Offset 0xE024 -+ */ -+union gmac_config3 { -+ unsigned int bits32; -+ struct bit1_0024 { -+ /* Flow control set threshold */ -+ unsigned int set_threshold:16; -+ /* Flow control release threshold */ -+ unsigned int rel_threshold:16; -+ } bits; -+}; -+ -+/* GMAC STATUS -+ * GMAC0 Offset 0xA02C -+ * GMAC1 Offset 0xE02C -+ */ -+union gmac_status { -+ unsigned int bits32; -+ struct bit1_002c { -+ /* Link status */ -+ unsigned int link:1; -+ /* Link speed(00->2.5M 01->25M 10->125M) */ -+ unsigned int speed:2; -+ /* Duplex mode */ -+ unsigned int duplex:1; -+ unsigned int reserved_1:1; -+ /* PHY interface type */ -+ unsigned int mii_rmii:2; -+ unsigned int reserved_2:25; -+ } bits; -+}; -+ -+#define GMAC_SPEED_10 0 -+#define GMAC_SPEED_100 1 -+#define GMAC_SPEED_1000 2 -+ -+#define GMAC_PHY_MII 0 -+#define GMAC_PHY_GMII 1 -+#define GMAC_PHY_RGMII_100_10 2 -+#define GMAC_PHY_RGMII_1000 3 -+ -+/* Queue Header -+ * (1) TOE Queue Header -+ * (2) Non-TOE Queue Header -+ * (3) Interrupt Queue Header -+ * -+ * memory Layout -+ * TOE Queue Header -+ * 0x60003000 +---------------------------+ 0x0000 -+ * | TOE Queue 0 Header | -+ * | 8 * 4 Bytes | -+ * +---------------------------+ 0x0020 -+ * | TOE Queue 1 Header | -+ * | 8 * 4 Bytes | -+ * +---------------------------+ 0x0040 -+ * | ...... | -+ * | | -+ * +---------------------------+ -+ * -+ * Non TOE Queue Header -+ * 0x60002000 +---------------------------+ 0x0000 -+ * | Default Queue 0 Header | -+ * | 2 * 4 Bytes | -+ * +---------------------------+ 0x0008 -+ * | Default Queue 1 Header | -+ * | 2 * 4 Bytes | -+ * +---------------------------+ 0x0010 -+ * | Classification Queue 0 | -+ * | 2 * 4 Bytes | -+ * +---------------------------+ -+ * | Classification Queue 1 | -+ * | 2 * 4 Bytes | -+ * +---------------------------+ (n * 8 + 0x10) -+ * | ... | -+ * | 2 * 4 Bytes | -+ * +---------------------------+ (13 * 8 + 0x10) -+ * | Classification Queue 13 | -+ * | 2 * 4 Bytes | -+ * +---------------------------+ 0x80 -+ * | Interrupt Queue 0 | -+ * | 2 * 4 Bytes | -+ * +---------------------------+ -+ * | Interrupt Queue 1 | -+ * | 2 * 4 Bytes | -+ * +---------------------------+ -+ * | Interrupt Queue 2 | -+ * | 2 * 4 Bytes | -+ * +---------------------------+ -+ * | Interrupt Queue 3 | -+ * | 2 * 4 Bytes | -+ * +---------------------------+ -+ * -+ */ -+#define TOE_QUEUE_HDR_ADDR(n) (TOE_TOE_QUE_HDR_BASE + n * 32) -+#define TOE_Q_HDR_AREA_END (TOE_QUEUE_HDR_ADDR(TOE_TOE_QUEUE_MAX + 1)) -+#define TOE_DEFAULT_Q_HDR_BASE(x) (TOE_NONTOE_QUE_HDR_BASE + 0x08 * (x)) -+#define TOE_CLASS_Q_HDR_BASE (TOE_NONTOE_QUE_HDR_BASE + 0x10) -+#define TOE_INTR_Q_HDR_BASE (TOE_NONTOE_QUE_HDR_BASE + 0x80) -+#define INTERRUPT_QUEUE_HDR_ADDR(n) (TOE_INTR_Q_HDR_BASE + n * 8) -+#define NONTOE_Q_HDR_AREA_END (INTERRUPT_QUEUE_HDR_ADDR(TOE_INTR_QUEUE_MAX + 1)) -+ -+/* NONTOE Queue Header Word 0 */ -+union nontoe_qhdr0 { -+ unsigned int bits32; -+ unsigned int base_size; -+}; -+ -+#define NONTOE_QHDR0_BASE_MASK (~0x0f) -+ -+/* NONTOE Queue Header Word 1 */ -+union nontoe_qhdr1 { -+ unsigned int bits32; -+ struct bit_nonqhdr1 { -+ /* bit 15:0 */ -+ unsigned int rptr:16; -+ /* bit 31:16 */ -+ unsigned int wptr:16; -+ } bits; -+}; -+ -+/* Non-TOE Queue Header */ -+struct nontoe_qhdr { -+ union nontoe_qhdr0 word0; -+ union nontoe_qhdr1 word1; -+}; -+ -+#endif /* _GEMINI_ETHERNET_H */ diff --git a/target/linux/gemini/patches-4.14/0023-ARM-dts-Add-ethernet-to-the-Gemini-SoC.patch b/target/linux/gemini/patches-4.14/0023-ARM-dts-Add-ethernet-to-the-Gemini-SoC.patch deleted file mode 100644 index 0960f6bfddaf..000000000000 --- a/target/linux/gemini/patches-4.14/0023-ARM-dts-Add-ethernet-to-the-Gemini-SoC.patch +++ /dev/null @@ -1,74 +0,0 @@ -From 860005c1a2f16aaa33458a7d80c9728b710ae292 Mon Sep 17 00:00:00 2001 -From: Linus Walleij -Date: Mon, 6 Nov 2017 00:05:28 +0100 -Subject: [PATCH 23/31] ARM: dts: Add ethernet to the Gemini SoC - -This adds the Gemini ethernet node to the Gemini SoC. - -Signed-off-by: Linus Walleij ---- - arch/arm/boot/dts/gemini.dtsi | 44 ++++++++++++++++++++++++++++++++++++++++++- - 1 file changed, 43 insertions(+), 1 deletion(-) - ---- a/arch/arm/boot/dts/gemini.dtsi -+++ b/arch/arm/boot/dts/gemini.dtsi -@@ -114,9 +114,16 @@ - }; - }; - gmii_default_pins: pinctrl-gmii { -+ /* -+ * Only activate GMAC0 by default since -+ * GMAC1 will overlap with 8 GPIO lines -+ * gpio2a, gpio2b. Overlay groups with -+ * "gmii_gmac0_grp", "gmii_gmac1_grp" for -+ * both ethernet interfaces. -+ */ - mux { - function = "gmii"; -- groups = "gmiigrp"; -+ groups = "gmii_gmac0_grp"; - }; - }; - pci_default_pins: pinctrl-pci { -@@ -316,6 +323,41 @@ - }; - }; - -+ ethernet@60000000 { -+ compatible = "cortina,gemini-ethernet"; -+ reg = <0x60000000 0x4000>, /* Global registers, queue */ -+ <0x60004000 0x2000>, /* V-bit */ -+ <0x60006000 0x2000>; /* A-bit */ -+ pinctrl-names = "default"; -+ pinctrl-0 = <&gmii_default_pins>; -+ status = "disabled"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges; -+ -+ gmac0: ethernet-port@0 { -+ compatible = "cortina,gemini-ethernet-port"; -+ reg = <0x60008000 0x2000>, /* Port 0 DMA/TOE */ -+ <0x6000a000 0x2000>; /* Port 0 GMAC */ -+ interrupt-parent = <&intcon>; -+ interrupts = <1 IRQ_TYPE_LEVEL_HIGH>; -+ resets = <&syscon GEMINI_RESET_GMAC0>; -+ clocks = <&syscon GEMINI_CLK_GATE_GMAC0>; -+ clock-names = "PCLK"; -+ }; -+ -+ gmac1: ethernet-port@1 { -+ compatible = "cortina,gemini-ethernet-port"; -+ reg = <0x6000c000 0x2000>, /* Port 1 DMA/TOE */ -+ <0x6000e000 0x2000>; /* Port 1 GMAC */ -+ interrupt-parent = <&intcon>; -+ interrupts = <2 IRQ_TYPE_LEVEL_HIGH>; -+ resets = <&syscon GEMINI_RESET_GMAC1>; -+ clocks = <&syscon GEMINI_CLK_GATE_GMAC1>; -+ clock-names = "PCLK"; -+ }; -+ }; -+ - ata@63000000 { - compatible = "cortina,gemini-pata", "faraday,ftide010"; - reg = <0x63000000 0x1000>; diff --git a/target/linux/gemini/patches-4.14/0024-net-gemini-Depend-on-HAS_IOMEM.patch b/target/linux/gemini/patches-4.14/0024-net-gemini-Depend-on-HAS_IOMEM.patch deleted file mode 100644 index 2b95a9287f79..000000000000 --- a/target/linux/gemini/patches-4.14/0024-net-gemini-Depend-on-HAS_IOMEM.patch +++ /dev/null @@ -1,30 +0,0 @@ -From e0a7c7762e3a81e908bcca4176139ea9755d0985 Mon Sep 17 00:00:00 2001 -From: Linus Walleij -Date: Sun, 21 Jan 2018 14:15:41 +0100 -Subject: [PATCH 24/31] net: gemini: Depend on HAS_IOMEM - -The zeroday builder notices that since Usermode Linux does not -have IO memory, the build fails for them when selecting everything -it can enable. - -As the driver is clearly using memory-mapped registers to access -the network adapter, we add depends on HAS_IOMEM to solve this -problem. - -Reported-by: kbuild test robot -Signed-off-by: Linus Walleij -Signed-off-by: David S. Miller ---- - drivers/net/ethernet/cortina/Kconfig | 1 + - 1 file changed, 1 insertion(+) - ---- a/drivers/net/ethernet/cortina/Kconfig -+++ b/drivers/net/ethernet/cortina/Kconfig -@@ -14,6 +14,7 @@ if NET_VENDOR_CORTINA - config GEMINI_ETHERNET - tristate "Gemini Gigabit Ethernet support" - depends on OF -+ depends on HAS_IOMEM - select PHYLIB - select CRC32 - ---help--- diff --git a/target/linux/gemini/patches-4.14/0025-ARM-dts-Set-D-Link-DNS-313-SATA-to-muxmode-0.patch b/target/linux/gemini/patches-4.14/0025-ARM-dts-Set-D-Link-DNS-313-SATA-to-muxmode-0.patch deleted file mode 100644 index 06609a7ed6a6..000000000000 --- a/target/linux/gemini/patches-4.14/0025-ARM-dts-Set-D-Link-DNS-313-SATA-to-muxmode-0.patch +++ /dev/null @@ -1,36 +0,0 @@ -From f30cc6acdeb834be1a6ae54d47c84b2f8012b83d Mon Sep 17 00:00:00 2001 -From: Linus Walleij -Date: Thu, 18 Jan 2018 14:36:21 +0100 -Subject: [PATCH 25/31] ARM: dts: Set D-Link DNS-313 SATA to muxmode 0 - -This stops the driver from trying to probe the ATA slave -interface. The vendor code enables the slave interface -but the driver in the vendor tree does not make use of -it. - -Setting it to muxmode 0 disables the slave interface: -the hardware only has the master interface connected -to the one harddrive slot anyways. - -Without this change booting takes excessive time, so it -is very annoying to end users. - -Fixes: dd5c0561db75 ("ARM: dts: Add basic devicetree for D-Link DNS-313") -Signed-off-by: Linus Walleij ---- -ARM SoC folks: please apply this for fixes for v4.16. ---- - arch/arm/boot/dts/gemini-dlink-dns-313.dts | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/arch/arm/boot/dts/gemini-dlink-dns-313.dts -+++ b/arch/arm/boot/dts/gemini-dlink-dns-313.dts -@@ -219,7 +219,7 @@ - - sata: sata@46000000 { - /* The ROM uses this muxmode */ -- cortina,gemini-ata-muxmode = <3>; -+ cortina,gemini-ata-muxmode = <0>; - cortina,gemini-enable-sata-bridge; - status = "okay"; - }; diff --git a/target/linux/gemini/patches-4.14/0026-power-gemini-poweroff-Avoid-spurious-poweroff.patch b/target/linux/gemini/patches-4.14/0026-power-gemini-poweroff-Avoid-spurious-poweroff.patch deleted file mode 100644 index e97aeaca43b2..000000000000 --- a/target/linux/gemini/patches-4.14/0026-power-gemini-poweroff-Avoid-spurious-poweroff.patch +++ /dev/null @@ -1,80 +0,0 @@ -From da443bc125265cae24a0e5f7d1c7bba196a9319f Mon Sep 17 00:00:00 2001 -From: Linus Walleij -Date: Thu, 22 Feb 2018 08:34:35 +0100 -Subject: [PATCH 26/31] power: gemini-poweroff: Avoid spurious poweroff - -On the D-Link DIR-685 we get spurious poweroff from -infrared. Since that block (CIR) doesn't even have a -driver this can be safely ignored, we can revisit this -code once we have a device supporting CIR. - -On the D-Link DNS-313 we get spurious poweroff from -the power button. This appears to be an initialization -issue: we need to enable the block (start the state -machine) before we clear any dangling IRQ. - -This patch fixes both issues. - -Fixes: f7a388d6cd1c ("power: reset: Add a driver for the Gemini poweroff") -Signed-off-by: Linus Walleij ---- -ChangeLog v1->v2: -- Fix both issues and rename the patch. -- Proper commit message with specifics. ---- - drivers/power/reset/gemini-poweroff.c | 30 +++++++++++++++++------------- - 1 file changed, 17 insertions(+), 13 deletions(-) - ---- a/drivers/power/reset/gemini-poweroff.c -+++ b/drivers/power/reset/gemini-poweroff.c -@@ -47,8 +47,12 @@ static irqreturn_t gemini_powerbutton_in - val &= 0x70U; - switch (val) { - case GEMINI_STAT_CIR: -- dev_info(gpw->dev, "infrared poweroff\n"); -- orderly_poweroff(true); -+ /* -+ * We do not yet have a driver for the infrared -+ * controller so it can cause spurious poweroff -+ * events. Ignore those for now. -+ */ -+ dev_info(gpw->dev, "infrared poweroff - ignored\n"); - break; - case GEMINI_STAT_RTC: - dev_info(gpw->dev, "RTC poweroff\n"); -@@ -116,7 +120,17 @@ static int gemini_poweroff_probe(struct - return -ENODEV; - } - -- /* Clear the power management IRQ */ -+ /* -+ * Enable the power controller. This is crucial on Gemini -+ * systems: if this is not done, pressing the power button -+ * will result in unconditional poweroff without any warning. -+ * This makes the kernel handle the poweroff. -+ */ -+ val = readl(gpw->base + GEMINI_PWC_CTRLREG); -+ val |= GEMINI_CTRL_ENABLE; -+ writel(val, gpw->base + GEMINI_PWC_CTRLREG); -+ -+ /* Now that the state machine is active, clear the IRQ */ - val = readl(gpw->base + GEMINI_PWC_CTRLREG); - val |= GEMINI_CTRL_IRQ_CLR; - writel(val, gpw->base + GEMINI_PWC_CTRLREG); -@@ -129,16 +143,6 @@ static int gemini_poweroff_probe(struct - pm_power_off = gemini_poweroff; - gpw_poweroff = gpw; - -- /* -- * Enable the power controller. This is crucial on Gemini -- * systems: if this is not done, pressing the power button -- * will result in unconditional poweroff without any warning. -- * This makes the kernel handle the poweroff. -- */ -- val = readl(gpw->base + GEMINI_PWC_CTRLREG); -- val |= GEMINI_CTRL_ENABLE; -- writel(val, gpw->base + GEMINI_PWC_CTRLREG); -- - dev_info(dev, "Gemini poweroff driver registered\n"); - - return 0; diff --git a/target/linux/gemini/patches-4.14/0027-usb-host-add-DT-bindings-for-faraday-fotg2.patch b/target/linux/gemini/patches-4.14/0027-usb-host-add-DT-bindings-for-faraday-fotg2.patch deleted file mode 100644 index e677c3843806..000000000000 --- a/target/linux/gemini/patches-4.14/0027-usb-host-add-DT-bindings-for-faraday-fotg2.patch +++ /dev/null @@ -1,65 +0,0 @@ -From 3699f119ff8da021fe7a1759e98e38ca88fa6766 Mon Sep 17 00:00:00 2001 -From: Hans Ulli Kroll -Date: Wed, 8 Feb 2017 21:00:09 +0100 -Subject: [PATCH 27/31] usb: host: add DT bindings for faraday fotg2 - -This adds device tree bindings for the Faraday FOTG2 -dual-mode host controller. - -Cc: devicetree@vger.kernel.org -Signed-off-by: Hans Ulli Kroll -Signed-off-by: Linus Walleij ---- -ChangeLog v1->v3: -- Change compatible to "faraday,fotg210" as the name of the - hardware block. -- Add an elaborate SoC-specific compatible string for the - Cortina Systems Gemini so that SoC-specific features can - be enabled. -- Add cortina,gemini-mini-b to indicate a Gemini PHY with - a Mini-B adapter connected. -- Indicated that the Gemini version can handle "wakeup-source". -- Add optional IP block clock. ---- - .../devicetree/bindings/usb/faraday,fotg210.txt | 35 ++++++++++++++++++++++ - 1 file changed, 35 insertions(+) - create mode 100644 Documentation/devicetree/bindings/usb/faraday,fotg210.txt - ---- /dev/null -+++ b/Documentation/devicetree/bindings/usb/faraday,fotg210.txt -@@ -0,0 +1,35 @@ -+Faraday FOTG Host controller -+ -+This OTG-capable USB host controller is found in Cortina Systems -+Gemini and other SoC products. -+ -+Required properties: -+- compatible: should be one of: -+ "faraday,fotg210" -+ "cortina,gemini-usb", "faraday,fotg210" -+- reg: should contain one register range i.e. start and length -+- interrupts: description of the interrupt line -+ -+Optional properties: -+- clocks: should contain the IP block clock -+- clock-names: should be "PCLK" for the IP block clock -+ -+Required properties for "cortina,gemini-usb" compatible: -+- syscon: a phandle to the system controller to access PHY registers -+ -+Optional properties for "cortina,gemini-usb" compatible: -+- cortina,gemini-mini-b: boolean property that indicates that a Mini-B -+ OTH connector is in use -+- wakeup-source: see power/wakeup-source.txt -+ -+Example for Gemini: -+ -+usb@68000000 { -+ compatible = "cortina,gemini-usb", "faraday,fotg210"; -+ reg = <0x68000000 0x1000>; -+ interrupts = <10 IRQ_TYPE_LEVEL_HIGH>; -+ clocks = <&cc 12>; -+ clock-names = "PCLK"; -+ syscon = <&syscon>; -+ wakeup-source; -+}; diff --git a/target/linux/gemini/patches-4.14/0028-usb-host-fotg2-add-device-tree-probing.patch b/target/linux/gemini/patches-4.14/0028-usb-host-fotg2-add-device-tree-probing.patch deleted file mode 100644 index 01a704830fd3..000000000000 --- a/target/linux/gemini/patches-4.14/0028-usb-host-fotg2-add-device-tree-probing.patch +++ /dev/null @@ -1,61 +0,0 @@ -From 5662c553e89ac4179ec2a7a94a342ba3e5d78cf7 Mon Sep 17 00:00:00 2001 -From: Hans Ulli Kroll -Date: Thu, 9 Feb 2017 15:20:49 +0100 -Subject: [PATCH 28/31] usb: host: fotg2: add device tree probing - -Add device tree probing to the fotg2 driver. - -Signed-off-by: Hans Ulli Kroll -Signed-off-by: Linus Walleij ---- -ChangeLog v2->v3: -- Change compatible to "faraday,fotg210" simply. ---- - drivers/usb/host/fotg210-hcd.c | 19 +++++++++++++++++++ - 1 file changed, 19 insertions(+) - ---- a/drivers/usb/host/fotg210-hcd.c -+++ b/drivers/usb/host/fotg210-hcd.c -@@ -23,6 +23,7 @@ - * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. - */ - #include -+#include - #include - #include - #include -@@ -5604,6 +5605,15 @@ static int fotg210_hcd_probe(struct plat - if (usb_disabled()) - return -ENODEV; - -+ /* Right now device-tree probed devices don't get dma_mask set. -+ * Since shared usb code relies on it, set it here for now. -+ * Once we have dma capability bindings this can go away. -+ */ -+ -+ retval = dma_coerce_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); -+ if (retval) -+ goto fail_create_hcd; -+ - pdev->dev.power.power_state = PMSG_ON; - - res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); -@@ -5680,9 +5690,18 @@ static int fotg210_hcd_remove(struct pla - return 0; - } - -+#ifdef CONFIG_OF -+static const struct of_device_id fotg210_of_match[] = { -+ { .compatible = "faraday,fotg210" }, -+ {}, -+}; -+MODULE_DEVICE_TABLE(of, fotg210_of_match); -+#endif -+ - static struct platform_driver fotg210_hcd_driver = { - .driver = { - .name = "fotg210-hcd", -+ .of_match_table = of_match_ptr(fotg210_of_match), - }, - .probe = fotg210_hcd_probe, - .remove = fotg210_hcd_remove, diff --git a/target/linux/gemini/patches-4.14/0029-usb-host-fotg2-add-silicon-clock-handling.patch b/target/linux/gemini/patches-4.14/0029-usb-host-fotg2-add-silicon-clock-handling.patch deleted file mode 100644 index 5ecd9297e526..000000000000 --- a/target/linux/gemini/patches-4.14/0029-usb-host-fotg2-add-silicon-clock-handling.patch +++ /dev/null @@ -1,99 +0,0 @@ -From acd19633751f14607ccd76f9dfde5bde7935766c Mon Sep 17 00:00:00 2001 -From: Linus Walleij -Date: Fri, 21 Apr 2017 20:46:12 +0200 -Subject: [PATCH 29/31] usb: host: fotg2: add silicon clock handling - -When used in a system with software-controller silicon clocks, -the FOTG210 needs to grab, prepare and enable the clock. -This is needed on for example the Cortina Gemini, where the -platform will by default gate off the clock unless the -peripheral (in this case the USB driver) grabs and enables -the clock. - -Signed-off-by: Linus Walleij ---- - drivers/usb/host/fotg210-hcd.c | 26 ++++++++++++++++++++++---- - drivers/usb/host/fotg210.h | 3 +++ - 2 files changed, 25 insertions(+), 4 deletions(-) - ---- a/drivers/usb/host/fotg210-hcd.c -+++ b/drivers/usb/host/fotg210-hcd.c -@@ -45,6 +45,7 @@ - #include - #include - #include -+#include - - #include - #include -@@ -5639,7 +5640,7 @@ static int fotg210_hcd_probe(struct plat - hcd->regs = devm_ioremap_resource(&pdev->dev, res); - if (IS_ERR(hcd->regs)) { - retval = PTR_ERR(hcd->regs); -- goto failed; -+ goto failed_put_hcd; - } - - hcd->rsrc_start = res->start; -@@ -5649,22 +5650,35 @@ static int fotg210_hcd_probe(struct plat - - fotg210->caps = hcd->regs; - -+ /* It's OK not to supply this clock */ -+ fotg210->pclk = clk_get(dev, "PCLK"); -+ if (!IS_ERR(fotg210->pclk)) { -+ retval = clk_prepare_enable(fotg210->pclk); -+ if (retval) { -+ dev_err(dev, "failed to enable PCLK\n"); -+ goto failed_dis_clk; -+ } -+ } -+ - retval = fotg210_setup(hcd); - if (retval) -- goto failed; -+ goto failed_dis_clk; - - fotg210_init(fotg210); - - retval = usb_add_hcd(hcd, irq, IRQF_SHARED); - if (retval) { - dev_err(dev, "failed to add hcd with err %d\n", retval); -- goto failed; -+ goto failed_dis_clk; - } - device_wakeup_enable(hcd->self.controller); - - return retval; - --failed: -+failed_dis_clk: -+ if (!IS_ERR(fotg210->pclk)) -+ clk_disable_unprepare(fotg210->pclk); -+failed_put_hcd: - usb_put_hcd(hcd); - fail_create_hcd: - dev_err(dev, "init %s fail, %d\n", dev_name(dev), retval); -@@ -5680,6 +5694,10 @@ static int fotg210_hcd_remove(struct pla - { - struct device *dev = &pdev->dev; - struct usb_hcd *hcd = dev_get_drvdata(dev); -+ struct fotg210_hcd *fotg210 = hcd_to_fotg210(hcd); -+ -+ if (!IS_ERR(fotg210->pclk)) -+ clk_disable_unprepare(fotg210->pclk); - - if (!hcd) - return 0; ---- a/drivers/usb/host/fotg210.h -+++ b/drivers/usb/host/fotg210.h -@@ -182,6 +182,9 @@ struct fotg210_hcd { /* one per contro - # define COUNT(x) - #endif - -+ /* silicon clock */ -+ struct clk *pclk; -+ - /* debug files */ - struct dentry *debug_dir; - }; diff --git a/target/linux/gemini/patches-4.14/0030-usb-host-fotg2-add-Gemini-specific-handling.patch b/target/linux/gemini/patches-4.14/0030-usb-host-fotg2-add-Gemini-specific-handling.patch deleted file mode 100644 index 0125e816d6c9..000000000000 --- a/target/linux/gemini/patches-4.14/0030-usb-host-fotg2-add-Gemini-specific-handling.patch +++ /dev/null @@ -1,131 +0,0 @@ -From e8ede0f62b39a3d3b06ae3dc04a74680a1f0a64b Mon Sep 17 00:00:00 2001 -From: Linus Walleij -Date: Fri, 21 Apr 2017 22:19:00 +0200 -Subject: [PATCH 30/31] usb: host: fotg2: add Gemini-specific handling - -The Cortina Systems Gemini has bolted on a PHY inside the -silicon that can be handled by six bits in a MISC register in -the system controller. - -If we are running on Gemini, look up a syscon regmap through -a phandle and enable VBUS and optionally the Mini-B connector. - -If the device is flagged as "wakeup-source" using the standard -DT bindings, we also enable this in the global controller for -respective port. - -Signed-off-by: Linus Walleij ---- - drivers/usb/host/Kconfig | 1 + - drivers/usb/host/fotg210-hcd.c | 76 ++++++++++++++++++++++++++++++++++++++++++ - 2 files changed, 77 insertions(+) - ---- a/drivers/usb/host/Kconfig -+++ b/drivers/usb/host/Kconfig -@@ -375,6 +375,7 @@ config USB_ISP1362_HCD - config USB_FOTG210_HCD - tristate "FOTG210 HCD support" - depends on USB && HAS_DMA && HAS_IOMEM -+ select MFD_SYSCON - ---help--- - Faraday FOTG210 is an OTG controller which can be configured as - an USB2.0 host. It is designed to meet USB2.0 EHCI specification ---- a/drivers/usb/host/fotg210-hcd.c -+++ b/drivers/usb/host/fotg210-hcd.c -@@ -46,6 +46,10 @@ - #include - #include - #include -+#include -+/* For Cortina Gemini */ -+#include -+#include - - #include - #include -@@ -5587,6 +5591,72 @@ static void fotg210_init(struct fotg210_ - iowrite32(value, &fotg210->regs->otgcsr); - } - -+/* -+ * Gemini-specific initialization function, only executed on the -+ * Gemini SoC using the global misc control register. -+ */ -+#define GEMINI_GLOBAL_MISC_CTRL 0x30 -+#define GEMINI_MISC_USB0_WAKEUP BIT(14) -+#define GEMINI_MISC_USB1_WAKEUP BIT(15) -+#define GEMINI_MISC_USB0_VBUS_ON BIT(22) -+#define GEMINI_MISC_USB1_VBUS_ON BIT(23) -+#define GEMINI_MISC_USB0_MINI_B BIT(29) -+#define GEMINI_MISC_USB1_MINI_B BIT(30) -+ -+static int fotg210_gemini_init(struct device *dev, struct usb_hcd *hcd) -+{ -+ struct device_node *np = dev->of_node; -+ struct regmap *map; -+ bool mini_b; -+ bool wakeup; -+ u32 mask, val; -+ int ret; -+ -+ map = syscon_regmap_lookup_by_phandle(np, "syscon"); -+ if (IS_ERR(map)) { -+ dev_err(dev, "no syscon\n"); -+ return PTR_ERR(map); -+ } -+ mini_b = of_property_read_bool(np, "cortina,gemini-mini-b"); -+ wakeup = of_property_read_bool(np, "wakeup-source"); -+ -+ /* -+ * Figure out if this is USB0 or USB1 by simply checking the -+ * physical base address. -+ */ -+ mask = 0; -+ if (hcd->rsrc_start == 0x69000000) { -+ val = GEMINI_MISC_USB1_VBUS_ON; -+ if (mini_b) -+ val |= GEMINI_MISC_USB1_MINI_B; -+ else -+ mask |= GEMINI_MISC_USB1_MINI_B; -+ if (wakeup) -+ val |= GEMINI_MISC_USB1_WAKEUP; -+ else -+ mask |= GEMINI_MISC_USB1_WAKEUP; -+ } else { -+ val = GEMINI_MISC_USB0_VBUS_ON; -+ if (mini_b) -+ val |= GEMINI_MISC_USB0_MINI_B; -+ else -+ mask |= GEMINI_MISC_USB0_MINI_B; -+ if (wakeup) -+ val |= GEMINI_MISC_USB0_WAKEUP; -+ else -+ mask |= GEMINI_MISC_USB0_WAKEUP; -+ } -+ -+ ret = regmap_update_bits(map, GEMINI_GLOBAL_MISC_CTRL, mask, val); -+ if (ret) { -+ dev_err(dev, "failed to initialize Gemini PHY\n"); -+ return ret; -+ } -+ -+ dev_info(dev, "initialized Gemini PHY\n"); -+ return 0; -+} -+ - /** - * fotg210_hcd_probe - initialize faraday FOTG210 HCDs - * -@@ -5666,6 +5736,12 @@ static int fotg210_hcd_probe(struct plat - - fotg210_init(fotg210); - -+ if (of_device_is_compatible(dev->of_node, "cortina,gemini-usb")) { -+ retval = fotg210_gemini_init(dev, hcd); -+ if (retval) -+ goto failed_dis_clk; -+ } -+ - retval = usb_add_hcd(hcd, irq, IRQF_SHARED); - if (retval) { - dev_err(dev, "failed to add hcd with err %d\n", retval); diff --git a/target/linux/gemini/patches-4.14/0031-ARM-dts-Add-the-FOTG210-USB-host-to-Gemini.patch b/target/linux/gemini/patches-4.14/0031-ARM-dts-Add-the-FOTG210-USB-host-to-Gemini.patch deleted file mode 100644 index 5b2c4139c17a..000000000000 --- a/target/linux/gemini/patches-4.14/0031-ARM-dts-Add-the-FOTG210-USB-host-to-Gemini.patch +++ /dev/null @@ -1,149 +0,0 @@ -From dd62aee5d2d24199e71e745544e49a1a8b3c6f7a Mon Sep 17 00:00:00 2001 -From: Linus Walleij -Date: Fri, 21 Apr 2017 20:50:22 +0200 -Subject: [PATCH 31/31] ARM: dts: Add the FOTG210 USB host to Gemini - -This adds the FOTG210 USB host controller to the Gemini -device trees. In the main SoC DTSI it is flagged as disabled -and then it is selectively enabled on the devices that utilize -it (these per-platform enablements are done on the out-of-tree -OpenWrt patch set). It is not enabled on the Itian SquareOne -NAS/router since this instead has a VIA host controller -soldered on the PCI port, and can gate off these USB host -controllers. - -Signed-off-by: Linus Walleij ---- -USB maintainers: I will merge this through the ARM SoC tree, -the patch is only included in the series for context. ---- - arch/arm/boot/dts/gemini-dlink-dir-685.dts | 8 ++++++++ - arch/arm/boot/dts/gemini-nas4220b.dts | 8 ++++++++ - arch/arm/boot/dts/gemini-wbd111.dts | 20 ++++++++++++++++++++ - arch/arm/boot/dts/gemini-wbd222.dts | 21 +++++++++++++++++++++ - arch/arm/boot/dts/gemini.dtsi | 26 ++++++++++++++++++++++++++ - 6 files changed, 103 insertions(+) - ---- a/arch/arm/boot/dts/gemini-dlink-dir-685.dts -+++ b/arch/arm/boot/dts/gemini-dlink-dir-685.dts -@@ -299,5 +299,13 @@ - }; - }; - }; -+ -+ usb@68000000 { -+ status = "okay"; -+ }; -+ -+ usb@69000000 { -+ status = "okay"; -+ }; - }; - }; ---- a/arch/arm/boot/dts/gemini-nas4220b.dts -+++ b/arch/arm/boot/dts/gemini-nas4220b.dts -@@ -146,5 +146,13 @@ - ata@63000000 { - status = "okay"; - }; -+ -+ usb@68000000 { -+ status = "okay"; -+ }; -+ -+ usb@69000000 { -+ status = "okay"; -+ }; - }; - }; ---- a/arch/arm/boot/dts/gemini-wbd111.dts -+++ b/arch/arm/boot/dts/gemini-wbd111.dts -@@ -160,5 +160,25 @@ - <0x6000 0 0 3 &pci_intc 1>, - <0x6000 0 0 4 &pci_intc 2>; - }; -+ -+ ethernet@60000000 { -+ status = "okay"; -+ -+ ethernet-port@0 { -+ phy-mode = "rgmii"; -+ phy-handle = <&phy0>; -+ }; -+ ethernet-port@1 { -+ /* Not used in this platform */ -+ }; -+ }; -+ -+ usb@68000000 { -+ status = "okay"; -+ }; -+ -+ usb@69000000 { -+ status = "okay"; -+ }; - }; - }; ---- a/arch/arm/boot/dts/gemini-wbd222.dts -+++ b/arch/arm/boot/dts/gemini-wbd222.dts -@@ -165,5 +165,26 @@ - <0x6000 0 0 3 &pci_intc 1>, - <0x6000 0 0 4 &pci_intc 2>; - }; -+ -+ ethernet@60000000 { -+ status = "okay"; -+ -+ ethernet-port@0 { -+ phy-mode = "rgmii"; -+ phy-handle = <&phy0>; -+ }; -+ ethernet-port@1 { -+ phy-mode = "rgmii"; -+ phy-handle = <&phy1>; -+ }; -+ }; -+ -+ usb@68000000 { -+ status = "okay"; -+ }; -+ -+ usb@69000000 { -+ status = "okay"; -+ }; - }; - }; ---- a/arch/arm/boot/dts/gemini.dtsi -+++ b/arch/arm/boot/dts/gemini.dtsi -@@ -411,5 +411,31 @@ - #size-cells = <0>; - status = "disabled"; - }; -+ -+ usb@68000000 { -+ compatible = "cortina,gemini-usb", "faraday,fotg210"; -+ reg = <0x68000000 0x1000>; -+ interrupts = <10 IRQ_TYPE_LEVEL_HIGH>; -+ resets = <&syscon GEMINI_RESET_USB0>; -+ clocks = <&syscon GEMINI_CLK_GATE_USB0>; -+ clock-names = "PCLK"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&usb_default_pins>; -+ syscon = <&syscon>; -+ status = "disabled"; -+ }; -+ -+ usb@69000000 { -+ compatible = "cortina,gemini-usb", "faraday,fotg210"; -+ reg = <0x69000000 0x1000>; -+ interrupts = <11 IRQ_TYPE_LEVEL_HIGH>; -+ resets = <&syscon GEMINI_RESET_USB1>; -+ clocks = <&syscon GEMINI_CLK_GATE_USB1>; -+ clock-names = "PCLK"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&usb_default_pins>; -+ syscon = <&syscon>; -+ status = "disabled"; -+ }; - }; - }; diff --git a/target/linux/gemini/patches-4.14/0033-ARM-dts-Fix-bootargs-for-Gemini-D-Link-devices.patch b/target/linux/gemini/patches-4.14/0033-ARM-dts-Fix-bootargs-for-Gemini-D-Link-devices.patch deleted file mode 100644 index d8fd853b3b41..000000000000 --- a/target/linux/gemini/patches-4.14/0033-ARM-dts-Fix-bootargs-for-Gemini-D-Link-devices.patch +++ /dev/null @@ -1,38 +0,0 @@ -From 5813b729eb9fe91fcf895a5c2f30bf34fbd46379 Mon Sep 17 00:00:00 2001 -From: Linus Walleij -Date: Wed, 2 May 2018 09:17:25 +0200 -Subject: [PATCH] ARM: dts: Fix bootargs for Gemini D-Link devices - -These machines need to be booted from very specific harddisk -partitions (as the D-Link DNS-313 boots specifically from -partition 4). Add the proper bootargs so that everything works -smoothly. - -Signed-off-by: Linus Walleij ---- - arch/arm/boot/dts/gemini-dlink-dir-685.dts | 3 ++- - arch/arm/boot/dts/gemini-dlink-dns-313.dts | 1 + - 2 files changed, 3 insertions(+), 1 deletion(-) - ---- a/arch/arm/boot/dts/gemini-dlink-dir-685.dts -+++ b/arch/arm/boot/dts/gemini-dlink-dir-685.dts -@@ -20,7 +20,8 @@ - }; - - chosen { -- stdout-path = "uart0:115200n8"; -+ bootargs = "console=ttyS0,19200n8 root=/dev/sda1 rw rootwait"; -+ stdout-path = "uart0:19200n8"; - }; - - gpio_keys { ---- a/arch/arm/boot/dts/gemini-dlink-dns-313.dts -+++ b/arch/arm/boot/dts/gemini-dlink-dns-313.dts -@@ -26,6 +26,7 @@ - }; - - chosen { -+ bootargs = "console=ttyS0,19200n8 root=/dev/sda4 rw rootwait"; - stdout-path = "uart0:19200n8"; - }; - diff --git a/target/linux/gemini/patches-4.14/0034-ARM-dts-Add-ethernet-to-a-bunch-of-platforms.patch b/target/linux/gemini/patches-4.14/0034-ARM-dts-Add-ethernet-to-a-bunch-of-platforms.patch deleted file mode 100644 index 3e588223b601..000000000000 --- a/target/linux/gemini/patches-4.14/0034-ARM-dts-Add-ethernet-to-a-bunch-of-platforms.patch +++ /dev/null @@ -1,116 +0,0 @@ -From 6d5af7093aea4f18e040e73db2ad99aaa0c0f77e Mon Sep 17 00:00:00 2001 -From: Linus Walleij -Date: Sun, 19 Nov 2017 11:04:23 +0100 -Subject: [PATCH] ARM: dts: Add ethernet to a bunch of platforms - -These platforms have the PHY defined already so we just -need to add a single device node to each of them to activate -the ethernet device. - -The PHY skew/delay settings for pin control is known from a -few vendor trees and old OpenWRT patch sets. - -This is a modified version of upstream commit -95220046a62c00b5afb1aa7c1971989d427db977, -just dropping the NAS4220B changes. - -Signed-off-by: Linus Walleij ---- - arch/arm/boot/dts/gemini-dlink-dns-313.dts | 62 ++++++++++++++++++++++++++++++ - arch/arm/boot/dts/gemini-wbd222.dts | 7 ++++ - 2 files changed, 69 insertions(+) - ---- a/arch/arm/boot/dts/gemini-dlink-dns-313.dts -+++ b/arch/arm/boot/dts/gemini-dlink-dns-313.dts -@@ -215,6 +215,56 @@ - groups = "gpio1dgrp"; - }; - }; -+ pinctrl-gmii { -+ mux { -+ function = "gmii"; -+ groups = "gmii_gmac0_grp"; -+ }; -+ /* -+ * In the vendor Linux tree, these values are set for the C3 -+ * version of the SL3512 ASIC with the comment "benson suggest" -+ */ -+ conf0 { -+ pins = "R8 GMAC0 RXDV", "U11 GMAC1 RXDV"; -+ skew-delay = <0>; -+ }; -+ conf1 { -+ pins = "T8 GMAC0 RXC"; -+ skew-delay = <10>; -+ }; -+ conf2 { -+ pins = "T11 GMAC1 RXC"; -+ skew-delay = <15>; -+ }; -+ conf3 { -+ pins = "P8 GMAC0 TXEN", "V11 GMAC1 TXEN"; -+ skew-delay = <7>; -+ }; -+ conf4 { -+ pins = "V7 GMAC0 TXC", "P10 GMAC1 TXC"; -+ skew-delay = <10>; -+ }; -+ conf5 { -+ /* The data lines all have default skew */ -+ pins = "U8 GMAC0 RXD0", "V8 GMAC0 RXD1", -+ "P9 GMAC0 RXD2", "R9 GMAC0 RXD3", -+ "R11 GMAC1 RXD0", "P11 GMAC1 RXD1", -+ "V12 GMAC1 RXD2", "U12 GMAC1 RXD3", -+ "R10 GMAC1 TXD0", "T10 GMAC1 TXD1", -+ "U10 GMAC1 TXD2", "V10 GMAC1 TXD3"; -+ skew-delay = <7>; -+ }; -+ conf6 { -+ pins = "U7 GMAC0 TXD0", "T7 GMAC0 TXD1", -+ "R7 GMAC0 TXD2", "P7 GMAC0 TXD3"; -+ skew-delay = <5>; -+ }; -+ /* Set up drive strength on GMAC0 to 16 mA */ -+ conf7 { -+ groups = "gmii_gmac0_grp"; -+ drive-strength = <16>; -+ }; -+ }; - }; - }; - -@@ -235,6 +285,18 @@ - pinctrl-0 = <&gpio1_default_pins>; - }; - -+ ethernet@60000000 { -+ status = "okay"; -+ -+ ethernet-port@0 { -+ phy-mode = "rgmii"; -+ phy-handle = <&phy0>; -+ }; -+ ethernet-port@1 { -+ /* Not used in this platform */ -+ }; -+ }; -+ - ata@63000000 { - status = "okay"; - }; ---- a/arch/arm/boot/dts/gemini-wbd222.dts -+++ b/arch/arm/boot/dts/gemini-wbd222.dts -@@ -136,6 +136,13 @@ - "gpio0bgrp"; - }; - }; -+ pinctrl-gmii { -+ /* This platform use both the ethernet ports */ -+ mux { -+ function = "gmii"; -+ groups = "gmii_gmac0_grp", "gmii_gmac1_grp"; -+ }; -+ }; - }; - }; - diff --git a/target/linux/gemini/patches-4.14/0900-arm-dts-gemini-add-openwrt-partitions-for-nas4220b.patch b/target/linux/gemini/patches-4.14/0900-arm-dts-gemini-add-openwrt-partitions-for-nas4220b.patch deleted file mode 100644 index 0fae0af0e12f..000000000000 --- a/target/linux/gemini/patches-4.14/0900-arm-dts-gemini-add-openwrt-partitions-for-nas4220b.patch +++ /dev/null @@ -1,17 +0,0 @@ ---- a/arch/arm/boot/dts/gemini-nas4220b.dts -+++ b/arch/arm/boot/dts/gemini-nas4220b.dts -@@ -115,6 +115,14 @@ - reg = <0x00fe0000 0x00020000>; - read-only; - }; -+ firmware@20000 { -+ label = "firmware"; -+ reg = <0x00020000 0x00f00000>; -+ }; -+ rootfs@320000 { -+ label = "rootfs"; -+ reg = <0x00320000 0x00c00000>; -+ }; - }; - - syscon: syscon@40000000 { diff --git a/target/linux/gemini/patches-4.14/0901-arm-dts-gemini-fix-ethernet-for-nas4220b.patch b/target/linux/gemini/patches-4.14/0901-arm-dts-gemini-fix-ethernet-for-nas4220b.patch deleted file mode 100644 index 90e95a70c4db..000000000000 --- a/target/linux/gemini/patches-4.14/0901-arm-dts-gemini-fix-ethernet-for-nas4220b.patch +++ /dev/null @@ -1,69 +0,0 @@ ---- a/arch/arm/boot/dts/gemini-nas4220b.dts -+++ b/arch/arm/boot/dts/gemini-nas4220b.dts -@@ -137,6 +137,47 @@ - groups = "gpio1dgrp"; - }; - }; -+ pinctrl-gmii { -+ mux { -+ function = "gmii"; -+ groups = "gmii_gmac0_grp"; -+ }; -+ conf0 { -+ pins = "V8 GMAC0 RXDV", "T10 GMAC1 RXDV"; -+ skew-delay = <0>; -+ }; -+ conf1 { -+ pins = "Y7 GMAC0 RXC", "Y11 GMAC1 RXC"; -+ skew-delay = <15>; -+ }; -+ conf2 { -+ pins = "T8 GMAC0 TXEN", "W11 GMAC1 TXEN"; -+ skew-delay = <7>; -+ }; -+ conf3 { -+ pins = "U8 GMAC0 TXC"; -+ skew-delay = <11>; -+ }; -+ conf4 { -+ pins = "V11 GMAC1 TXC"; -+ skew-delay = <10>; -+ }; -+ conf5 { -+ pins = "W8 GMAC0 RXD0", "V9 GMAC0 RXD1", -+ "Y8 GMAC0 RXD2", "U9 GMAC0 RXD3", -+ "T7 GMAC0 TXD0", "U6 GMAC0 TXD1", -+ "V7 GMAC0 TXD2", "U7 GMAC0 TXD3", -+ "Y12 GMAC1 RXD0", "V12 GMAC1 RXD1", -+ "T11 GMAC1 RXD2", "W12 GMAC1 RXD3", -+ "U10 GMAC1 TXD0", "Y10 GMAC1 TXD1", -+ "W10 GMAC1 TXD2", "T9 GMAC1 TXD3"; -+ skew-delay = <7>; -+ }; -+ conf6 { -+ groups = "gmii_gmac0_grp"; -+ drive-strength = <16>; -+ }; -+ }; - }; - }; - -@@ -151,6 +192,18 @@ - pinctrl-0 = <&gpio1_default_pins>; - }; - -+ ethernet@60000000 { -+ status = "okay"; -+ -+ gmac0: ethernet-port@0 { -+ phy-mode = "rgmii"; -+ phy-handle = <&phy0>; -+ }; -+ gmac1: ethernet-port@1 { -+ status = "disabled"; -+ }; -+ }; -+ - ata@63000000 { - status = "okay"; - }; diff --git a/target/linux/gemini/patches-4.14/0902-arm-dts-gemini-add-second-ata-for-nas4220b.patch b/target/linux/gemini/patches-4.14/0902-arm-dts-gemini-add-second-ata-for-nas4220b.patch deleted file mode 100644 index ef98172367a6..000000000000 --- a/target/linux/gemini/patches-4.14/0902-arm-dts-gemini-add-second-ata-for-nas4220b.patch +++ /dev/null @@ -1,13 +0,0 @@ ---- a/arch/arm/boot/dts/gemini-nas4220b.dts -+++ b/arch/arm/boot/dts/gemini-nas4220b.dts -@@ -208,6 +208,10 @@ - status = "okay"; - }; - -+ ata@63400000 { -+ status = "okay"; -+ }; -+ - usb@68000000 { - status = "okay"; - }; diff --git a/target/linux/gemini/patches-4.14/0903-arm-dts-gemini-disable-usb-port-1-until-fixed.patch b/target/linux/gemini/patches-4.14/0903-arm-dts-gemini-disable-usb-port-1-until-fixed.patch deleted file mode 100644 index 6962d563ad6e..000000000000 --- a/target/linux/gemini/patches-4.14/0903-arm-dts-gemini-disable-usb-port-1-until-fixed.patch +++ /dev/null @@ -1,11 +0,0 @@ ---- a/arch/arm/boot/dts/gemini-nas4220b.dts -+++ b/arch/arm/boot/dts/gemini-nas4220b.dts -@@ -217,7 +217,7 @@ - }; - - usb@69000000 { -- status = "okay"; -+ status = "disabled"; - }; - }; - }; diff --git a/target/linux/gemini/patches-4.14/0904-net-cortina-fix-uninitialized-struct-member-usage.patch b/target/linux/gemini/patches-4.14/0904-net-cortina-fix-uninitialized-struct-member-usage.patch deleted file mode 100644 index 15a2d6cd895b..000000000000 --- a/target/linux/gemini/patches-4.14/0904-net-cortina-fix-uninitialized-struct-member-usage.patch +++ /dev/null @@ -1,23 +0,0 @@ ---- a/drivers/net/ethernet/cortina/gemini.c -+++ b/drivers/net/ethernet/cortina/gemini.c -@@ -1013,9 +1013,9 @@ static int geth_resize_freeq(struct gemi - int ret; - - if (netdev->dev_id == 0) -- other_netdev = geth->port1->netdev; -+ other_netdev = (geth->port1)? geth->port1->netdev : NULL; - else -- other_netdev = geth->port0->netdev; -+ other_netdev = (geth->port0)? geth->port0->netdev : NULL; - - if (other_netdev && netif_running(other_netdev)) - return -EBUSY; -@@ -2510,6 +2510,8 @@ static int gemini_ethernet_probe(struct - if (IS_ERR(geth->base)) - return PTR_ERR(geth->base); - geth->dev = dev; -+ geth->port0 = NULL; -+ geth->port1 = NULL; - - /* Wait for ports to stabilize */ - do { diff --git a/target/linux/gemini/patches-4.14/0905-arm-dts-gemini-dlink-dir-685-add-rtl8366rb.patch b/target/linux/gemini/patches-4.14/0905-arm-dts-gemini-dlink-dir-685-add-rtl8366rb.patch deleted file mode 100644 index 8cab32200f90..000000000000 --- a/target/linux/gemini/patches-4.14/0905-arm-dts-gemini-dlink-dir-685-add-rtl8366rb.patch +++ /dev/null @@ -1,82 +0,0 @@ ---- a/arch/arm/boot/dts/gemini-dlink-dir-685.dts -+++ b/arch/arm/boot/dts/gemini-dlink-dir-685.dts -@@ -87,6 +87,12 @@ - }; - }; - -+ rtl8366rb { -+ compatible = "realtek,rtl8366rb"; -+ gpio-sda = <&gpio0 22 GPIO_ACTIVE_HIGH>; -+ gpio-sck = <&gpio0 21 GPIO_ACTIVE_HIGH>; -+ }; -+ - leds { - compatible = "gpio-leds"; - led-wps { -@@ -245,6 +251,47 @@ - groups = "gpio1bgrp"; - }; - }; -+ pinctrl-gmii { -+ mux { -+ function = "gmii"; -+ groups = "gmii_gmac0_grp"; -+ }; -+ conf0 { -+ pins = "V8 GMAC0 RXDV", "T10 GMAC1 RXDV"; -+ skew-delay = <0>; -+ }; -+ conf1 { -+ pins = "Y7 GMAC0 RXC", "Y11 GMAC1 RXC"; -+ skew-delay = <15>; -+ }; -+ conf2 { -+ pins = "T8 GMAC0 TXEN", "W11 GMAC1 TXEN"; -+ skew-delay = <7>; -+ }; -+ conf3 { -+ pins = "U8 GMAC0 TXC"; -+ skew-delay = <11>; -+ }; -+ conf4 { -+ pins = "V11 GMAC1 TXC"; -+ skew-delay = <10>; -+ }; -+ conf5 { -+ pins = "W8 GMAC0 RXD0", "V9 GMAC0 RXD1", -+ "Y8 GMAC0 RXD2", "U9 GMAC0 RXD3", -+ "T7 GMAC0 TXD0", "U6 GMAC0 TXD1", -+ "V7 GMAC0 TXD2", "U7 GMAC0 TXD3", -+ "Y12 GMAC1 RXD0", "V12 GMAC1 RXD1", -+ "T11 GMAC1 RXD2", "W12 GMAC1 RXD3", -+ "U10 GMAC1 TXD0", "Y10 GMAC1 TXD1", -+ "W10 GMAC1 TXD2", "T9 GMAC1 TXD3"; -+ skew-delay = <7>; -+ }; -+ conf6 { -+ groups = "gmii_gmac0_grp"; -+ drive-strength = <16>; -+ }; -+ }; - }; - }; - -@@ -286,6 +333,18 @@ - <0x6000 0 0 4 &pci_intc 2>; - }; - -+ ethernet@60000000 { -+ status = "okay"; -+ -+ ethernet-port@0 { -+ phy-mode = "rgmii"; -+ // phy-handle = <&phy0>; -+ }; -+ ethernet-port@1 { -+ /* Not used in this platform */ -+ }; -+ }; -+ - ata@63000000 { - status = "okay"; - }; From patchwork Sun Mar 1 12:12:33 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Hauke Mehrtens X-Patchwork-Id: 1247283 X-Patchwork-Delegate: hauke@hauke-m.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.openwrt.org (client-ip=2607:7c80:54:e::133; helo=bombadil.infradead.org; envelope-from=openwrt-devel-bounces+incoming=patchwork.ozlabs.org@lists.openwrt.org; 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Sun, 1 Mar 2020 13:12:52 +0100 (CET) X-Virus-Scanned: amavisd-new at heinlein-support.de Received: from smtp2.mailbox.org ([80.241.60.241]) by spamfilter02.heinlein-hosting.de (spamfilter02.heinlein-hosting.de [80.241.56.116]) (amavisd-new, port 10030) with ESMTP id 0Aoo7nIiFjnc; Sun, 1 Mar 2020 13:12:49 +0100 (CET) From: Hauke Mehrtens To: openwrt-devel@lists.openwrt.org Date: Sun, 1 Mar 2020 13:12:33 +0100 Message-Id: <20200301121241.5545-5-hauke@hauke-m.de> In-Reply-To: <20200301121241.5545-1-hauke@hauke-m.de> References: <20200301121241.5545-1-hauke@hauke-m.de> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200301_041259_757395_BD2B02DE X-CRM114-Status: GOOD ( 11.15 ) X-Spam-Score: 0.1 (/) X-Spam-Report: SpamAssassin version 3.4.3 on bombadil.infradead.org summary: Content analysis details: (0.1 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at https://www.dnswl.org/, low trust [80.241.56.172 listed in list.dnswl.org] 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.0 SPF_PASS SPF: sender matches SPF record 0.8 UPPERCASE_50_75 message body is 50-75% uppercase Subject: [OpenWrt-Devel] [PATCH 04/12] imx6: Remove kernel 4.14 support X-BeenThere: openwrt-devel@lists.openwrt.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: hauke@hauke-m.de Sender: "openwrt-devel" Errors-To: openwrt-devel-bounces+incoming=patchwork.ozlabs.org@lists.openwrt.org This target was switched to kernel 4.19 more than 6 months ago in commit f342ffd300da ("treewide: kernel: bump some targets to 4.19") and now with kernel 5.4 support being added it gets harder to support kernel 4.14 in addition to kernel 4.19 and 5.4. Signed-off-by: Hauke Mehrtens --- target/linux/imx6/config-4.14 | 525 ------------------ .../imx6/patches-4.14/100-bootargs.patch | 11 - .../imx6/patches-4.14/200-disable-msi.patch | 18 - .../301-apalis-ixora-dts-leds.patch | 86 --- .../302-apalis-ixora-dts-reset-button.patch | 76 --- 5 files changed, 716 deletions(-) delete mode 100644 target/linux/imx6/config-4.14 delete mode 100644 target/linux/imx6/patches-4.14/100-bootargs.patch delete mode 100644 target/linux/imx6/patches-4.14/200-disable-msi.patch delete mode 100644 target/linux/imx6/patches-4.14/301-apalis-ixora-dts-leds.patch delete mode 100644 target/linux/imx6/patches-4.14/302-apalis-ixora-dts-reset-button.patch diff --git a/target/linux/imx6/config-4.14 b/target/linux/imx6/config-4.14 deleted file mode 100644 index 313f657a80f0..000000000000 --- a/target/linux/imx6/config-4.14 +++ /dev/null @@ -1,525 +0,0 @@ -CONFIG_AHCI_IMX=y -CONFIG_ALIGNMENT_TRAP=y -CONFIG_ARCH_CLOCKSOURCE_DATA=y -CONFIG_ARCH_HAS_DEBUG_VIRTUAL=y -CONFIG_ARCH_HAS_ELF_RANDOMIZE=y -CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y -CONFIG_ARCH_HAS_RESET_CONTROLLER=y -CONFIG_ARCH_HAS_SET_MEMORY=y -CONFIG_ARCH_HAS_SG_CHAIN=y -CONFIG_ARCH_HAS_STRICT_KERNEL_RWX=y -CONFIG_ARCH_HAS_STRICT_MODULE_RWX=y -CONFIG_ARCH_HAS_TICK_BROADCAST=y -CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y -CONFIG_ARCH_HIBERNATION_POSSIBLE=y -CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y -CONFIG_ARCH_MMAP_RND_BITS_MAX=15 -CONFIG_ARCH_MULTIPLATFORM=y -# CONFIG_ARCH_MULTI_CPU_AUTO is not set -CONFIG_ARCH_MULTI_V6_V7=y -CONFIG_ARCH_MULTI_V7=y -CONFIG_ARCH_MXC=y -CONFIG_ARCH_NR_GPIO=0 -CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y -CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y -# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set -# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set -CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y -CONFIG_ARCH_SUPPORTS_BIG_ENDIAN=y -CONFIG_ARCH_SUPPORTS_UPROBES=y -CONFIG_ARCH_SUSPEND_POSSIBLE=y -CONFIG_ARCH_USE_BUILTIN_BSWAP=y -CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y -CONFIG_ARCH_WANT_GENERAL_HUGETLB=y -CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y -CONFIG_ARM=y -CONFIG_ARM_CPU_SUSPEND=y -CONFIG_ARM_CRYPTO=y -CONFIG_ARM_ERRATA_754322=y -CONFIG_ARM_ERRATA_764369=y -CONFIG_ARM_ERRATA_775420=y -CONFIG_ARM_GIC=y -CONFIG_ARM_HAS_SG_CHAIN=y -CONFIG_ARM_HEAVY_MB=y -CONFIG_ARM_IMX6Q_CPUFREQ=y -CONFIG_ARM_L1_CACHE_SHIFT=6 -CONFIG_ARM_L1_CACHE_SHIFT_6=y -# CONFIG_ARM_LPAE is not set -CONFIG_ARM_PATCH_IDIV=y -CONFIG_ARM_PATCH_PHYS_VIRT=y -CONFIG_ARM_THUMB=y -# CONFIG_ARM_THUMBEE is not set -CONFIG_ARM_VIRT_EXT=y -CONFIG_ASN1=y -CONFIG_ASSOCIATIVE_ARRAY=y -CONFIG_ATA=y -CONFIG_ATAGS=y -CONFIG_AUTO_ZRELADDR=y -CONFIG_BLK_DEV_LOOP=y -CONFIG_BLK_MQ_PCI=y -CONFIG_BLK_SCSI_REQUEST=y -CONFIG_CACHE_L2X0=y -CONFIG_CLKDEV_LOOKUP=y -CONFIG_CLKSRC_IMX_GPT=y -CONFIG_CLKSRC_MMIO=y -CONFIG_CLONE_BACKWARDS=y -CONFIG_CLZ_TAB=y -CONFIG_COMMON_CLK=y -CONFIG_CPUFREQ_DT=y -CONFIG_CPUFREQ_DT_PLATDEV=y -CONFIG_CPU_32v6K=y -CONFIG_CPU_32v7=y -CONFIG_CPU_ABRT_EV7=y -# CONFIG_CPU_BIG_ENDIAN is not set -# CONFIG_CPU_BPREDICT_DISABLE is not set -CONFIG_CPU_CACHE_V7=y -CONFIG_CPU_CACHE_VIPT=y -CONFIG_CPU_COPY_V6=y -CONFIG_CPU_CP15=y -CONFIG_CPU_CP15_MMU=y -CONFIG_CPU_FREQ=y -CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y -CONFIG_CPU_FREQ_GOV_ATTR_SET=y -CONFIG_CPU_FREQ_GOV_COMMON=y -CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y -CONFIG_CPU_FREQ_GOV_ONDEMAND=y -CONFIG_CPU_FREQ_GOV_PERFORMANCE=y -CONFIG_CPU_FREQ_GOV_POWERSAVE=y -CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y -CONFIG_CPU_FREQ_GOV_USERSPACE=y -CONFIG_CPU_FREQ_STAT=y -CONFIG_CPU_HAS_ASID=y -# CONFIG_CPU_ICACHE_DISABLE is not set -CONFIG_CPU_PABRT_V7=y -CONFIG_CPU_RMAP=y -CONFIG_CPU_SPECTRE=y -CONFIG_CPU_THERMAL=y -CONFIG_CPU_THUMB_CAPABLE=y -CONFIG_CPU_TLB_V7=y -CONFIG_CPU_V7=y -# CONFIG_CRASHLOG is not set -CONFIG_CRC16=y -CONFIG_CRYPTO_ACOMP2=y -CONFIG_CRYPTO_AEAD=y -CONFIG_CRYPTO_AEAD2=y -CONFIG_CRYPTO_AES_ARM=y -CONFIG_CRYPTO_AES_ARM_BS=y -# CONFIG_CRYPTO_AES_ARM_CE is not set -CONFIG_CRYPTO_AKCIPHER=y -CONFIG_CRYPTO_AKCIPHER2=y -CONFIG_CRYPTO_AUTHENC=y -CONFIG_CRYPTO_CBC=y -CONFIG_CRYPTO_CHACHA20=y -CONFIG_CRYPTO_CHACHA20_NEON=y -CONFIG_CRYPTO_CRC32=y -CONFIG_CRYPTO_CRC32C=y -CONFIG_CRYPTO_CRC32_ARM_CE=y -CONFIG_CRYPTO_CRYPTD=y -CONFIG_CRYPTO_CTR=y -CONFIG_CRYPTO_CTS=y -CONFIG_CRYPTO_DEFLATE=y -CONFIG_CRYPTO_DEV_FSL_CAAM=y -CONFIG_CRYPTO_DEV_FSL_CAAM_AHASH_API=y -CONFIG_CRYPTO_DEV_FSL_CAAM_CRYPTO_API=y -CONFIG_CRYPTO_DEV_FSL_CAAM_CRYPTO_API_DESC=y -# CONFIG_CRYPTO_DEV_FSL_CAAM_DEBUG is not set -# CONFIG_CRYPTO_DEV_FSL_CAAM_INTC is not set -CONFIG_CRYPTO_DEV_FSL_CAAM_JR=y -CONFIG_CRYPTO_DEV_FSL_CAAM_PKC_API=y -CONFIG_CRYPTO_DEV_FSL_CAAM_RINGSIZE=9 -CONFIG_CRYPTO_DEV_FSL_CAAM_RNG_API=y -CONFIG_CRYPTO_DRBG=y -CONFIG_CRYPTO_DRBG_HMAC=y -CONFIG_CRYPTO_DRBG_MENU=y -CONFIG_CRYPTO_ECB=y -CONFIG_CRYPTO_GF128MUL=y -# CONFIG_CRYPTO_GHASH_ARM_CE is not set -CONFIG_CRYPTO_HASH=y -CONFIG_CRYPTO_HASH2=y -CONFIG_CRYPTO_HMAC=y -CONFIG_CRYPTO_HW=y -CONFIG_CRYPTO_JITTERENTROPY=y -CONFIG_CRYPTO_LZO=y -CONFIG_CRYPTO_MANAGER=y -CONFIG_CRYPTO_MANAGER2=y -CONFIG_CRYPTO_NULL=y -CONFIG_CRYPTO_NULL2=y -CONFIG_CRYPTO_RNG=y -CONFIG_CRYPTO_RNG2=y -CONFIG_CRYPTO_RNG_DEFAULT=y -CONFIG_CRYPTO_RSA=y -CONFIG_CRYPTO_SEQIV=y -CONFIG_CRYPTO_SHA1=y -CONFIG_CRYPTO_SHA1_ARM=y -# CONFIG_CRYPTO_SHA1_ARM_CE is not set -CONFIG_CRYPTO_SHA1_ARM_NEON=y -CONFIG_CRYPTO_SHA256=y -CONFIG_CRYPTO_SHA256_ARM=y -# CONFIG_CRYPTO_SHA2_ARM_CE is not set -CONFIG_CRYPTO_SHA512_ARM=y -CONFIG_CRYPTO_SIMD=y -CONFIG_CRYPTO_WORKQUEUE=y -CONFIG_CRYPTO_XTS=y -CONFIG_DCACHE_WORD_ACCESS=y -CONFIG_DEBUG_IMX_UART_PORT=1 -CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" -# CONFIG_DEBUG_UART_8250 is not set -# CONFIG_DEBUG_USER is not set -CONFIG_DECOMPRESS_BZIP2=y -CONFIG_DECOMPRESS_GZIP=y -CONFIG_DECOMPRESS_LZO=y -CONFIG_DECOMPRESS_XZ=y -CONFIG_DMADEVICES=y -CONFIG_DMA_ENGINE=y -CONFIG_DMA_OF=y -CONFIG_DTC=y -CONFIG_E1000E=y -CONFIG_EDAC_ATOMIC_SCRUB=y -CONFIG_EDAC_SUPPORT=y -CONFIG_ENCRYPTED_KEYS=y -CONFIG_EXT4_ENCRYPTION=y -CONFIG_EXT4_FS=y -CONFIG_EXT4_FS_ENCRYPTION=y -CONFIG_EXT4_FS_POSIX_ACL=y -CONFIG_EXT4_FS_SECURITY=y -CONFIG_EXTCON=y -CONFIG_EXTRA_FIRMWARE="imx/sdma/sdma-imx6q.bin" -CONFIG_EXTRA_FIRMWARE_DIR="firmware" -# CONFIG_F2FS_CHECK_FS is not set -CONFIG_F2FS_FS=y -# CONFIG_F2FS_FS_SECURITY is not set -CONFIG_F2FS_FS_XATTR=y -CONFIG_F2FS_STAT_FS=y -CONFIG_FEC=y -CONFIG_FIXED_PHY=y -CONFIG_FIX_EARLYCON_MEM=y -CONFIG_FRAME_POINTER=y -CONFIG_FSL_GUTS=y -CONFIG_FS_ENCRYPTION=y -CONFIG_FS_MBCACHE=y -CONFIG_FS_POSIX_ACL=y -CONFIG_GENERIC_ALLOCATOR=y -CONFIG_GENERIC_ARCH_TOPOLOGY=y -CONFIG_GENERIC_BUG=y -CONFIG_GENERIC_CLOCKEVENTS=y -CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y -CONFIG_GENERIC_CPU_AUTOPROBE=y -CONFIG_GENERIC_EARLY_IOREMAP=y -CONFIG_GENERIC_IDLE_POLL_SETUP=y -CONFIG_GENERIC_IO=y -CONFIG_GENERIC_IRQ_CHIP=y -CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y -CONFIG_GENERIC_IRQ_SHOW=y -CONFIG_GENERIC_IRQ_SHOW_LEVEL=y -CONFIG_GENERIC_PCI_IOMAP=y -CONFIG_GENERIC_PINCONF=y -CONFIG_GENERIC_PINCTRL_GROUPS=y -CONFIG_GENERIC_PINMUX_FUNCTIONS=y -CONFIG_GENERIC_SCHED_CLOCK=y -CONFIG_GENERIC_SMP_IDLE_THREAD=y -CONFIG_GENERIC_STRNCPY_FROM_USER=y -CONFIG_GENERIC_STRNLEN_USER=y -# CONFIG_GIANFAR is not set -CONFIG_GLOB=y -CONFIG_GPIOLIB=y -CONFIG_GPIOLIB_IRQCHIP=y -CONFIG_GPIO_GENERIC=y -CONFIG_GPIO_MXC=y -CONFIG_GPIO_PCA953X=y -CONFIG_GPIO_PCA953X_IRQ=y -CONFIG_GPIO_SYSFS=y -# CONFIG_GRO_CELLS is not set -CONFIG_HANDLE_DOMAIN_IRQ=y -CONFIG_HARDEN_BRANCH_PREDICTOR=y -CONFIG_HARDIRQS_SW_RESEND=y -CONFIG_HAS_DMA=y -CONFIG_HAS_IOMEM=y -CONFIG_HAS_IOPORT_MAP=y -# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set -CONFIG_HAVE_ARCH_AUDITSYSCALL=y -CONFIG_HAVE_ARCH_BITREVERSE=y -CONFIG_HAVE_ARCH_JUMP_LABEL=y -CONFIG_HAVE_ARCH_KGDB=y -CONFIG_HAVE_ARCH_PFN_VALID=y -CONFIG_HAVE_ARCH_SECCOMP_FILTER=y -CONFIG_HAVE_ARCH_TRACEHOOK=y -CONFIG_HAVE_ARM_SCU=y -CONFIG_HAVE_ARM_SMCCC=y -CONFIG_HAVE_ARM_TWD=y -# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set -CONFIG_HAVE_CC_STACKPROTECTOR=y -CONFIG_HAVE_CLK=y -CONFIG_HAVE_CLK_PREPARE=y -CONFIG_HAVE_CONTEXT_TRACKING=y -CONFIG_HAVE_C_RECORDMCOUNT=y -CONFIG_HAVE_DEBUG_KMEMLEAK=y -CONFIG_HAVE_DMA_API_DEBUG=y -CONFIG_HAVE_DMA_CONTIGUOUS=y -CONFIG_HAVE_DYNAMIC_FTRACE=y -CONFIG_HAVE_DYNAMIC_FTRACE_WITH_REGS=y -CONFIG_HAVE_EBPF_JIT=y -CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y -CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y -CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y -CONFIG_HAVE_FUNCTION_TRACER=y -CONFIG_HAVE_GENERIC_DMA_COHERENT=y -CONFIG_HAVE_IDE=y -CONFIG_HAVE_IMX_ANATOP=y -CONFIG_HAVE_IMX_GPC=y -CONFIG_HAVE_IMX_MMDC=y -CONFIG_HAVE_IMX_SRC=y -CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y -CONFIG_HAVE_MEMBLOCK=y -CONFIG_HAVE_MOD_ARCH_SPECIFIC=y -CONFIG_HAVE_NET_DSA=y -CONFIG_HAVE_OPROFILE=y -CONFIG_HAVE_OPTPROBES=y -CONFIG_HAVE_PERF_EVENTS=y -CONFIG_HAVE_PERF_REGS=y -CONFIG_HAVE_PERF_USER_STACK_DUMP=y -CONFIG_HAVE_PROC_CPU=y -CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y -CONFIG_HAVE_SMP=y -CONFIG_HAVE_SYSCALL_TRACEPOINTS=y -CONFIG_HAVE_UID16=y -CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y -CONFIG_HWMON=y -CONFIG_HW_RANDOM=y -CONFIG_HW_RANDOM_IMX_RNGC=y -CONFIG_HZ_FIXED=0 -CONFIG_HZ_PERIODIC=y -CONFIG_I2C=y -CONFIG_I2C_BOARDINFO=y -CONFIG_I2C_CHARDEV=y -CONFIG_I2C_IMX=y -# CONFIG_I2C_IMX_LPI2C is not set -CONFIG_IMX2_WDT=y -CONFIG_IMX_DMA=y -CONFIG_IMX_SDMA=y -CONFIG_IMX_THERMAL=y -# CONFIG_IMX_WEIM is not set -CONFIG_INITRAMFS_SOURCE="" -CONFIG_IOMMU_HELPER=y -CONFIG_IRQCHIP=y -CONFIG_IRQ_DOMAIN=y -CONFIG_IRQ_DOMAIN_HIERARCHY=y -CONFIG_IRQ_FORCED_THREADING=y -CONFIG_IRQ_WORK=y -CONFIG_JBD2=y -# CONFIG_JFFS2_FS is not set -CONFIG_KEYS=y -CONFIG_LIBFDT=y -CONFIG_LOCK_SPIN_ON_OWNER=y -CONFIG_LZO_COMPRESS=y -CONFIG_LZO_DECOMPRESS=y -CONFIG_MARVELL_PHY=y -CONFIG_MDIO_BUS=y -CONFIG_MDIO_DEVICE=y -CONFIG_MFD_SYSCON=y -CONFIG_MICREL_PHY=y -CONFIG_MIGHT_HAVE_CACHE_L2X0=y -CONFIG_MIGHT_HAVE_PCI=y -CONFIG_MIGRATION=y -CONFIG_MMC=y -CONFIG_MMC_BLOCK=y -# CONFIG_MMC_MXC is not set -CONFIG_MMC_SDHCI=y -CONFIG_MMC_SDHCI_ESDHC_IMX=y -CONFIG_MMC_SDHCI_IO_ACCESSORS=y -CONFIG_MMC_SDHCI_OF_ESDHC=y -# CONFIG_MMC_SDHCI_PCI is not set -CONFIG_MMC_SDHCI_PLTFM=y -# CONFIG_MMC_TIFM_SD is not set -CONFIG_MODULES_USE_ELF_REL=y -CONFIG_MPILIB=y -CONFIG_MTD_NAND=y -CONFIG_MTD_NAND_ECC=y -CONFIG_MTD_NAND_GPMI_NAND=y -CONFIG_MTD_UBI=y -CONFIG_MTD_UBI_BEB_LIMIT=20 -CONFIG_MTD_UBI_BLOCK=y -# CONFIG_MTD_UBI_FASTMAP is not set -# CONFIG_MTD_UBI_GLUEBI is not set -CONFIG_MTD_UBI_WL_THRESHOLD=4096 -CONFIG_MULTI_IRQ_HANDLER=y -CONFIG_MUTEX_SPIN_ON_OWNER=y -# CONFIG_MX3_IPU is not set -CONFIG_MXS_DMA=y -CONFIG_NEED_DMA_MAP_STATE=y -CONFIG_NEON=y -CONFIG_NET_DSA=y -CONFIG_NET_DSA_MV88E6XXX=y -CONFIG_NET_DSA_MV88E6XXX_GLOBAL2=y -CONFIG_NET_DSA_TAG_DSA=y -CONFIG_NET_DSA_TAG_EDSA=y -CONFIG_NET_FLOW_LIMIT=y -CONFIG_NET_PTP_CLASSIFY=y -CONFIG_NET_SWITCHDEV=y -CONFIG_NLS=y -CONFIG_NLS_CODEPAGE_437=y -CONFIG_NO_BOOTMEM=y -CONFIG_NR_CPUS=4 -CONFIG_NVMEM=y -# CONFIG_NVMEM_IMX_IIM is not set -CONFIG_NVMEM_IMX_OCOTP=y -CONFIG_OF=y -CONFIG_OF_ADDRESS=y -CONFIG_OF_ADDRESS_PCI=y -CONFIG_OF_EARLY_FLATTREE=y -CONFIG_OF_FLATTREE=y -CONFIG_OF_GPIO=y -CONFIG_OF_IRQ=y -CONFIG_OF_MDIO=y -CONFIG_OF_NET=y -CONFIG_OF_PCI=y -CONFIG_OF_PCI_IRQ=y -CONFIG_OF_RESERVED_MEM=y -CONFIG_OLD_SIGACTION=y -CONFIG_OLD_SIGSUSPEND3=y -CONFIG_OUTER_CACHE=y -CONFIG_OUTER_CACHE_SYNC=y -CONFIG_PADATA=y -CONFIG_PAGE_OFFSET=0x80000000 -CONFIG_PCI=y -CONFIG_PCIEAER=y -CONFIG_PCIEPORTBUS=y -CONFIG_PCIE_DW=y -CONFIG_PCIE_DW_HOST=y -CONFIG_PCIE_PME=y -CONFIG_PCI_DOMAINS=y -CONFIG_PCI_DOMAINS_GENERIC=y -CONFIG_PCI_IMX6=y -CONFIG_PERF_USE_VMALLOC=y -CONFIG_PGTABLE_LEVELS=2 -CONFIG_PHYLIB=y -CONFIG_PINCTRL=y -CONFIG_PINCTRL_IMX=y -CONFIG_PINCTRL_IMX6Q=y -CONFIG_PINCTRL_IMX6SL=y -CONFIG_PINCTRL_IMX6SX=y -CONFIG_PINCTRL_IMX6UL=y -# CONFIG_PL310_ERRATA_588369 is not set -# CONFIG_PL310_ERRATA_727915 is not set -# CONFIG_PL310_ERRATA_753970 is not set -CONFIG_PL310_ERRATA_769419=y -CONFIG_PM=y -CONFIG_PM_CLK=y -# CONFIG_PM_DEBUG is not set -CONFIG_PM_GENERIC_DOMAINS=y -CONFIG_PM_GENERIC_DOMAINS_OF=y -CONFIG_PM_OPP=y -CONFIG_PPS=y -CONFIG_PTP_1588_CLOCK=y -CONFIG_PWM=y -CONFIG_PWM_IMX=y -CONFIG_PWM_SYSFS=y -CONFIG_RAS=y -CONFIG_RATIONAL=y -CONFIG_RCU_NEED_SEGCBLIST=y -CONFIG_RCU_STALL_COMMON=y -CONFIG_RD_BZIP2=y -CONFIG_RD_GZIP=y -CONFIG_RD_LZO=y -CONFIG_RD_XZ=y -CONFIG_REGMAP=y -CONFIG_REGMAP_I2C=y -CONFIG_REGMAP_MMIO=y -CONFIG_REGMAP_SPI=y -CONFIG_REGULATOR=y -CONFIG_REGULATOR_ANATOP=y -CONFIG_REGULATOR_FIXED_VOLTAGE=y -CONFIG_REGULATOR_LTC3676=y -CONFIG_REGULATOR_PFUZE100=y -CONFIG_RESET_CONTROLLER=y -CONFIG_RFS_ACCEL=y -CONFIG_RPS=y -CONFIG_RTC_CLASS=y -# CONFIG_RTC_DRV_CMOS is not set -CONFIG_RTC_DRV_DS1307=y -CONFIG_RTC_DRV_DS1672=y -# CONFIG_RTC_DRV_IMXDI is not set -# CONFIG_RTC_DRV_MXC is not set -CONFIG_RTC_I2C_AND_SPI=y -CONFIG_RWSEM_SPIN_ON_OWNER=y -CONFIG_RWSEM_XCHGADD_ALGORITHM=y -# CONFIG_SCHED_INFO is not set -CONFIG_SCSI=y -CONFIG_SENSORS_AD7418=y -CONFIG_SERIAL_8250_FSL=y -CONFIG_SERIAL_IMX=y -CONFIG_SERIAL_IMX_CONSOLE=y -CONFIG_SERIAL_MCTRL_GPIO=y -CONFIG_SG_POOL=y -CONFIG_SMP=y -CONFIG_SMP_ON_UP=y -CONFIG_SOC_BUS=y -# CONFIG_SOC_IMX50 is not set -# CONFIG_SOC_IMX51 is not set -# CONFIG_SOC_IMX53 is not set -CONFIG_SOC_IMX6=y -CONFIG_SOC_IMX6Q=y -CONFIG_SOC_IMX6SL=y -CONFIG_SOC_IMX6SX=y -CONFIG_SOC_IMX6UL=y -# CONFIG_SOC_IMX7D is not set -# CONFIG_SOC_LS1021A is not set -# CONFIG_SOC_VF610 is not set -CONFIG_SPARSE_IRQ=y -CONFIG_SPI=y -CONFIG_SPI_BITBANG=y -# CONFIG_SPI_FSL_LPSPI is not set -CONFIG_SPI_IMX=y -CONFIG_SPI_MASTER=y -CONFIG_SRAM=y -CONFIG_SRAM_EXEC=y -CONFIG_SRCU=y -CONFIG_STMP_DEVICE=y -CONFIG_SWIOTLB=y -CONFIG_SWPHY=y -CONFIG_SWP_EMULATE=y -CONFIG_SYS_SUPPORTS_APM_EMULATION=y -CONFIG_THERMAL=y -CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y -CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0 -CONFIG_THERMAL_GOV_STEP_WISE=y -CONFIG_THERMAL_OF=y -# CONFIG_THUMB2_KERNEL is not set -CONFIG_TICK_CPU_ACCOUNTING=y -CONFIG_TIMER_OF=y -CONFIG_TIMER_PROBE=y -CONFIG_TREE_RCU=y -CONFIG_TREE_SRCU=y -CONFIG_UBIFS_FS=y -CONFIG_UBIFS_FS_ADVANCED_COMPR=y -CONFIG_UBIFS_FS_LZO=y -CONFIG_UBIFS_FS_ZLIB=y -CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" -CONFIG_USB=y -CONFIG_USB_CHIPIDEA=y -CONFIG_USB_CHIPIDEA_HOST=y -CONFIG_USB_CHIPIDEA_OF=y -CONFIG_USB_CHIPIDEA_UDC=y -CONFIG_USB_COMMON=y -CONFIG_USB_EHCI_HCD=y -# CONFIG_USB_EHCI_HCD_PLATFORM is not set -# CONFIG_USB_EHCI_MXC is not set -CONFIG_USB_GADGET=y -CONFIG_USB_MXS_PHY=y -CONFIG_USB_OTG=y -CONFIG_USB_PHY=y -CONFIG_USB_SUPPORT=y -CONFIG_USE_OF=y -CONFIG_VECTORS_BASE=0xffff0000 -CONFIG_VFP=y -CONFIG_VFPv3=y -CONFIG_VMSPLIT_2G=y -# CONFIG_VMSPLIT_3G is not set -CONFIG_WATCHDOG_CORE=y -CONFIG_XPS=y -CONFIG_XZ_DEC_ARM=y -CONFIG_XZ_DEC_ARMTHUMB=y -CONFIG_XZ_DEC_BCJ=y -CONFIG_ZBOOT_ROM_BSS=0 -CONFIG_ZBOOT_ROM_TEXT=0 -CONFIG_ZLIB_DEFLATE=y -CONFIG_ZLIB_INFLATE=y diff --git a/target/linux/imx6/patches-4.14/100-bootargs.patch b/target/linux/imx6/patches-4.14/100-bootargs.patch deleted file mode 100644 index 09543912036d..000000000000 --- a/target/linux/imx6/patches-4.14/100-bootargs.patch +++ /dev/null @@ -1,11 +0,0 @@ ---- a/arch/arm/boot/dts/imx6dl-wandboard.dts -+++ b/arch/arm/boot/dts/imx6dl-wandboard.dts -@@ -19,4 +19,8 @@ - memory { - reg = <0x10000000 0x40000000>; - }; -+ -+ chosen { -+ bootargs = "console=ttymxc0,115200"; -+ }; - }; diff --git a/target/linux/imx6/patches-4.14/200-disable-msi.patch b/target/linux/imx6/patches-4.14/200-disable-msi.patch deleted file mode 100644 index 9de7eeee4242..000000000000 --- a/target/linux/imx6/patches-4.14/200-disable-msi.patch +++ /dev/null @@ -1,18 +0,0 @@ ---- a/drivers/pci/dwc/Kconfig -+++ b/drivers/pci/dwc/Kconfig -@@ -6,7 +6,6 @@ config PCIE_DW - config PCIE_DW_HOST - bool - depends on PCI -- depends on PCI_MSI_IRQ_DOMAIN - select PCIE_DW - - config PCIE_DW_EP -@@ -74,7 +73,6 @@ config PCI_IMX6 - bool "Freescale i.MX6 PCIe controller" - depends on PCI - depends on SOC_IMX6Q -- depends on PCI_MSI_IRQ_DOMAIN - select PCIEPORTBUS - select PCIE_DW_HOST - diff --git a/target/linux/imx6/patches-4.14/301-apalis-ixora-dts-leds.patch b/target/linux/imx6/patches-4.14/301-apalis-ixora-dts-leds.patch deleted file mode 100644 index acec1e8e3d51..000000000000 --- a/target/linux/imx6/patches-4.14/301-apalis-ixora-dts-leds.patch +++ /dev/null @@ -1,86 +0,0 @@ -arm: dts: apalis-ixora: Add status LEDs aliases - -Signed-off-by: Petr Å tetiar - ---- a/arch/arm/boot/dts/imx6q-apalis-ixora.dts -+++ b/arch/arm/boot/dts/imx6q-apalis-ixora.dts -@@ -60,6 +60,10 @@ - i2c2 = &i2c2; - rtc0 = &rtc_i2c; - rtc1 = &snvs_rtc; -+ led-boot = &led_boot; -+ led-failsafe = &led_failsafe; -+ led-running = &led_running; -+ led-upgrade = &led_upgrade; - }; - - gpio-keys { -@@ -123,22 +127,22 @@ - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_leds_ixora>; - -- led4-green { -+ led_running: led4-green { - label = "LED_4_GREEN"; - gpios = <&gpio1 17 GPIO_ACTIVE_HIGH>; - }; - -- led4-red { -+ led_upgrade: led4-red { - label = "LED_4_RED"; - gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>; - }; - -- led5-green { -+ led_boot: led5-green { - label = "LED_5_GREEN"; - gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>; - }; - -- led5-red { -+ led_failsafe: led5-red { - label = "LED_5_RED"; - gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>; - }; ---- a/arch/arm/boot/dts/imx6q-apalis-ixora-v1.1.dts -+++ b/arch/arm/boot/dts/imx6q-apalis-ixora-v1.1.dts -@@ -61,6 +61,10 @@ - i2c2 = &i2c2; - rtc0 = &rtc_i2c; - rtc1 = &snvs_rtc; -+ led-boot = &led_boot; -+ led-failsafe = &led_failsafe; -+ led-running = &led_running; -+ led-upgrade = &led_upgrade; - }; - - gpio-keys { -@@ -124,22 +128,22 @@ - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_leds_ixora>; - -- led4-green { -+ led_running: led4-green { - label = "LED_4_GREEN"; -- gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>; -+ gpios = <&gpio1 17 GPIO_ACTIVE_HIGH>; - }; - -- led4-red { -+ led_upgrade: led4-red { - label = "LED_4_RED"; -- gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>; -+ gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>; - }; - -- led5-green { -+ led_boot: led5-green { - label = "LED_5_GREEN"; - gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>; - }; - -- led5-red { -+ led_failsafe: led5-red { - label = "LED_5_RED"; - gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>; - }; diff --git a/target/linux/imx6/patches-4.14/302-apalis-ixora-dts-reset-button.patch b/target/linux/imx6/patches-4.14/302-apalis-ixora-dts-reset-button.patch deleted file mode 100644 index ede872fb628e..000000000000 --- a/target/linux/imx6/patches-4.14/302-apalis-ixora-dts-reset-button.patch +++ /dev/null @@ -1,76 +0,0 @@ -arm: dts: apalis-ixora: Add switch3 as reset button - -Signed-off-by: Petr Å tetiar - ---- a/arch/arm/boot/dts/imx6q-apalis-ixora-v1.1.dts -+++ b/arch/arm/boot/dts/imx6q-apalis-ixora-v1.1.dts -@@ -70,7 +70,7 @@ - gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; -- pinctrl-0 = <&pinctrl_gpio_keys>; -+ pinctrl-0 = <&pinctrl_gpio_keys &pinctrl_switch3_ixora>; - - wakeup { - label = "Wake-Up"; -@@ -79,6 +79,13 @@ - debounce-interval = <10>; - wakeup-source; - }; -+ -+ reset { -+ label = "reset"; -+ gpios = <&gpio1 16 GPIO_ACTIVE_LOW>; -+ linux,code = ; -+ debounce-interval = <10>; -+ }; - }; - - lcd_display: display@di0 { -@@ -292,4 +299,10 @@ - MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0 - >; - }; -+ -+ pinctrl_switch3_ixora: switch3ixora { -+ fsl,pins = < -+ MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x1b0b0 -+ >; -+ }; - }; ---- a/arch/arm/boot/dts/imx6q-apalis-ixora.dts -+++ b/arch/arm/boot/dts/imx6q-apalis-ixora.dts -@@ -69,7 +69,7 @@ - gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; -- pinctrl-0 = <&pinctrl_gpio_keys>; -+ pinctrl-0 = <&pinctrl_gpio_keys &pinctrl_switch3_ixora>; - - wakeup { - label = "Wake-Up"; -@@ -78,6 +78,13 @@ - debounce-interval = <10>; - wakeup-source; - }; -+ -+ reset { -+ label = "reset"; -+ gpios = <&gpio1 16 GPIO_ACTIVE_LOW>; -+ linux,code = ; -+ debounce-interval = <10>; -+ }; - }; - - lcd_display: display@di0 { -@@ -293,4 +300,10 @@ - MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0 - >; - }; -+ -+ pinctrl_switch3_ixora: switch3ixora { -+ fsl,pins = < -+ MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x1b0b0 -+ >; -+ }; - }; From patchwork Sun Mar 1 12:12:35 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hauke Mehrtens X-Patchwork-Id: 1247282 X-Patchwork-Delegate: hauke@hauke-m.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.openwrt.org (client-ip=2607:7c80:54:e::133; helo=bombadil.infradead.org; envelope-from=openwrt-devel-bounces+incoming=patchwork.ozlabs.org@lists.openwrt.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=hauke-m.de Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=lists.infradead.org header.i=@lists.infradead.org header.a=rsa-sha256 header.s=bombadil.20170209 header.b=nLU7h4NQ; dkim-atps=neutral Received: from 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Received: from smtp2.mailbox.org ([80.241.60.241]) by spamfilter06.heinlein-hosting.de (spamfilter06.heinlein-hosting.de [80.241.56.125]) (amavisd-new, port 10030) with ESMTP id vn0s2j3Ye8_y; Sun, 1 Mar 2020 13:12:50 +0100 (CET) From: Hauke Mehrtens To: openwrt-devel@lists.openwrt.org Date: Sun, 1 Mar 2020 13:12:35 +0100 Message-Id: <20200301121241.5545-7-hauke@hauke-m.de> In-Reply-To: <20200301121241.5545-1-hauke@hauke-m.de> References: <20200301121241.5545-1-hauke@hauke-m.de> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200301_041259_936744_800C9F8D X-CRM114-Status: GOOD ( 10.53 ) X-Spam-Score: 0.5 (/) X-Spam-Report: SpamAssassin version 3.4.3 on bombadil.infradead.org summary: Content analysis details: (0.5 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at https://www.dnswl.org/, low trust [80.241.56.152 listed in list.dnswl.org] 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.0 SPF_PASS SPF: sender matches SPF record 1.2 UPPERCASE_75_100 message body is 75-100% uppercase Subject: [OpenWrt-Devel] [PATCH 06/12] malta: Remove kernel 4.14 support X-BeenThere: openwrt-devel@lists.openwrt.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: hauke@hauke-m.de Sender: "openwrt-devel" Errors-To: openwrt-devel-bounces+incoming=patchwork.ozlabs.org@lists.openwrt.org This target was switched to kernel 4.19 more than 6 months ago in commit f342ffd300da ("treewide: kernel: bump some targets to 4.19") and now with kernel 5.4 support being added it gets harder to support kernel 4.14 in addition to kernel 4.19 and 5.4. Signed-off-by: Hauke Mehrtens Acked-by: Yousong Zhou --- target/linux/malta/config-4.14 | 326 --------------------------------- 1 file changed, 326 deletions(-) delete mode 100644 target/linux/malta/config-4.14 diff --git a/target/linux/malta/config-4.14 b/target/linux/malta/config-4.14 deleted file mode 100644 index 6fc80b33c9ff..000000000000 --- a/target/linux/malta/config-4.14 +++ /dev/null @@ -1,326 +0,0 @@ -CONFIG_ARCH_BINFMT_ELF_STATE=y -CONFIG_ARCH_CLOCKSOURCE_DATA=y -CONFIG_ARCH_DISCARD_MEMBLOCK=y -CONFIG_ARCH_HAS_ELF_RANDOMIZE=y -# CONFIG_ARCH_HAS_GCOV_PROFILE_ALL is not set -# CONFIG_ARCH_HAS_SG_CHAIN is not set -# CONFIG_ARCH_HAS_STRICT_KERNEL_RWX is not set -# CONFIG_ARCH_HAS_STRICT_MODULE_RWX is not set -CONFIG_ARCH_MAY_HAVE_PC_FDC=y -CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y -CONFIG_ARCH_MIGHT_HAVE_PC_SERIO=y -CONFIG_ARCH_MMAP_RND_BITS_MAX=15 -CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=15 -# CONFIG_ARCH_OPTIONAL_KERNEL_RWX is not set -# CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT is not set -CONFIG_ARCH_SUPPORTS_UPROBES=y -CONFIG_ARCH_USE_BUILTIN_BSWAP=y -CONFIG_ARCH_USE_QUEUED_RWLOCKS=y -CONFIG_ARCH_USE_QUEUED_SPINLOCKS=y -CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y -CONFIG_ATA=y -CONFIG_ATA_PIIX=y -CONFIG_BLK_DEV_BSG=y -CONFIG_BLK_DEV_BSGLIB=y -# CONFIG_BLK_DEV_DM is not set -# CONFIG_BLK_DEV_INITRD is not set -# CONFIG_BLK_DEV_MD is not set -CONFIG_BLK_DEV_RAM=y -CONFIG_BLK_DEV_RAM_COUNT=16 -CONFIG_BLK_DEV_RAM_SIZE=4096 -CONFIG_BLK_DEV_SD=y -CONFIG_BLK_MQ_PCI=y -CONFIG_BLK_SCSI_REQUEST=y -CONFIG_BOARD_SCACHE=y -CONFIG_BOOT_ELF32=y -CONFIG_BOUNCE=y -CONFIG_BUILTIN_DTB=y -CONFIG_CEVT_R4K=y -CONFIG_CLKBLD_I8253=y -CONFIG_CLKDEV_LOOKUP=y -CONFIG_CLKEVT_I8253=y -CONFIG_CLKSRC_I8253=y -CONFIG_CLKSRC_MIPS_GIC=y -CONFIG_CLONE_BACKWARDS=y -CONFIG_COMMON_CLK=y -# CONFIG_COMMON_CLK_BOSTON is not set -CONFIG_CONSOLE_TRANSLATIONS=y -CONFIG_CPU_GENERIC_DUMP_TLB=y -CONFIG_CPU_HAS_PREFETCH=y -CONFIG_CPU_HAS_RIXI=y -# CONFIG_CPU_HAS_SMARTMIPS is not set -CONFIG_CPU_HAS_SYNC=y -# CONFIG_CPU_MICROMIPS is not set -CONFIG_CPU_MIPS32=y -# CONFIG_CPU_MIPS32_3_5_FEATURES is not set -# CONFIG_CPU_MIPS32_R1 is not set -# CONFIG_CPU_MIPS32_R2 is not set -# CONFIG_CPU_MIPS32_R5_FEATURES is not set -# CONFIG_CPU_MIPS32_R6 is not set -# CONFIG_CPU_MIPS64_R1 is not set -# CONFIG_CPU_MIPS64_R2 is not set -# CONFIG_CPU_MIPS64_R6 is not set -CONFIG_CPU_MIPSR2=y -CONFIG_CPU_MIPSR2_IRQ_EI=y -CONFIG_CPU_MIPSR2_IRQ_VI=y -CONFIG_CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS=y -# CONFIG_CPU_NEVADA is not set -CONFIG_CPU_R4K_CACHE_TLB=y -CONFIG_CPU_R4K_FPU=y -# CONFIG_CPU_RM7000 is not set -CONFIG_CPU_RMAP=y -CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y -CONFIG_CPU_SUPPORTS_HIGHMEM=y -CONFIG_CPU_SUPPORTS_MSA=y -CONFIG_CRC16=y -CONFIG_CRYPTO_AEAD=y -CONFIG_CRYPTO_AEAD2=y -CONFIG_CRYPTO_CRC32C=y -CONFIG_CRYPTO_HASH=y -CONFIG_CRYPTO_HASH2=y -CONFIG_CRYPTO_MANAGER=y -CONFIG_CRYPTO_MANAGER2=y -CONFIG_CRYPTO_NULL2=y -CONFIG_CRYPTO_RNG2=y -CONFIG_CRYPTO_WORKQUEUE=y -CONFIG_CSRC_R4K=y -CONFIG_DMA_MAYBE_COHERENT=y -CONFIG_DMA_NONCOHERENT=y -CONFIG_DMA_UNMAP_POST_FLUSH=y -CONFIG_DNOTIFY=y -CONFIG_DTC=y -CONFIG_DUMMY_CONSOLE=y -CONFIG_ENABLE_MUST_CHECK=y -CONFIG_EXT4_FS=y -CONFIG_FIRMWARE_IN_KERNEL=y -CONFIG_FS_MBCACHE=y -CONFIG_FS_POSIX_ACL=y -CONFIG_GENERIC_ATOMIC64=y -CONFIG_GENERIC_CLOCKEVENTS=y -CONFIG_GENERIC_CMOS_UPDATE=y -CONFIG_GENERIC_CPU_AUTOPROBE=y -CONFIG_GENERIC_IO=y -CONFIG_GENERIC_IRQ_CHIP=y -CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y -CONFIG_GENERIC_IRQ_IPI=y -CONFIG_GENERIC_IRQ_SHOW=y -CONFIG_GENERIC_ISA_DMA=y -CONFIG_GENERIC_PCI_IOMAP=y -CONFIG_GENERIC_SCHED_CLOCK=y -CONFIG_GENERIC_SMP_IDLE_THREAD=y -CONFIG_GENERIC_TIME_VSYSCALL=y -CONFIG_GLOB=y -# CONFIG_GRO_CELLS is not set -CONFIG_HANDLE_DOMAIN_IRQ=y -CONFIG_HARDWARE_WATCHPOINTS=y -CONFIG_HAS_DMA=y -CONFIG_HAS_IOMEM=y -CONFIG_HAS_IOPORT_MAP=y -# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set -# CONFIG_HAVE_ARCH_BITREVERSE is not set -CONFIG_HAVE_ARCH_COMPILER_H=y -CONFIG_HAVE_ARCH_JUMP_LABEL=y -CONFIG_HAVE_ARCH_KGDB=y -CONFIG_HAVE_ARCH_SECCOMP_FILTER=y -CONFIG_HAVE_ARCH_TRACEHOOK=y -# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set -CONFIG_HAVE_CBPF_JIT=y -CONFIG_HAVE_CC_STACKPROTECTOR=y -CONFIG_HAVE_CLK=y -CONFIG_HAVE_CLK_PREPARE=y -CONFIG_HAVE_CONTEXT_TRACKING=y -CONFIG_HAVE_COPY_THREAD_TLS=y -CONFIG_HAVE_C_RECORDMCOUNT=y -CONFIG_HAVE_DEBUG_KMEMLEAK=y -CONFIG_HAVE_DEBUG_STACKOVERFLOW=y -CONFIG_HAVE_DMA_API_DEBUG=y -CONFIG_HAVE_DMA_CONTIGUOUS=y -CONFIG_HAVE_DYNAMIC_FTRACE=y -CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y -CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y -CONFIG_HAVE_FUNCTION_TRACER=y -CONFIG_HAVE_GENERIC_DMA_COHERENT=y -CONFIG_HAVE_IDE=y -CONFIG_HAVE_IRQ_EXIT_ON_IRQ_STACK=y -CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y -CONFIG_HAVE_KVM=y -CONFIG_HAVE_LATENCYTOP_SUPPORT=y -CONFIG_HAVE_MEMBLOCK=y -CONFIG_HAVE_MEMBLOCK_NODE_MAP=y -CONFIG_HAVE_MOD_ARCH_SPECIFIC=y -CONFIG_HAVE_NET_DSA=y -CONFIG_HAVE_OPROFILE=y -CONFIG_HAVE_PCSPKR_PLATFORM=y -CONFIG_HAVE_PERF_EVENTS=y -CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y -CONFIG_HAVE_SYSCALL_TRACEPOINTS=y -CONFIG_HW_CONSOLE=y -CONFIG_HW_HAS_PCI=y -CONFIG_I8253=y -CONFIG_I8253_LOCK=y -CONFIG_I8259=y -CONFIG_INPUT=y -# CONFIG_INPUT_MISC is not set -CONFIG_INPUT_MOUSEDEV=y -CONFIG_INPUT_MOUSEDEV_PSAUX=y -CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 -CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 -CONFIG_IRQCHIP=y -CONFIG_IRQ_DOMAIN=y -CONFIG_IRQ_DOMAIN_HIERARCHY=y -CONFIG_IRQ_FORCED_THREADING=y -CONFIG_IRQ_MIPS_CPU=y -CONFIG_IRQ_WORK=y -CONFIG_ISA_DMA_API=y -CONFIG_JBD2=y -CONFIG_JFFS2_FS_POSIX_ACL=y -CONFIG_JFFS2_FS_SECURITY=y -CONFIG_KALLSYMS=y -CONFIG_KERNEL_GZIP=y -# CONFIG_KERNEL_XZ is not set -# CONFIG_LEDS_TRIGGER_TIMER is not set -CONFIG_LIBFDT=y -CONFIG_MD=y -# CONFIG_MDIO_BUS is not set -CONFIG_MIGRATION=y -CONFIG_MIPS=y -CONFIG_MIPS_ASID_BITS=8 -CONFIG_MIPS_ASID_SHIFT=0 -CONFIG_MIPS_BONITO64=y -CONFIG_MIPS_CLOCK_VSYSCALL=y -CONFIG_MIPS_CM=y -# CONFIG_MIPS_CMDLINE_DTB_EXTEND is not set -CONFIG_MIPS_CMDLINE_FROM_BOOTLOADER=y -# CONFIG_MIPS_CMDLINE_FROM_DTB is not set -# CONFIG_MIPS_CMP is not set -CONFIG_MIPS_CPC=y -# CONFIG_MIPS_CPS is not set -CONFIG_MIPS_CPU_SCACHE=y -# CONFIG_MIPS_ELF_APPENDED_DTB is not set -CONFIG_MIPS_EXTERNAL_TIMER=y -CONFIG_MIPS_GIC=y -# CONFIG_MIPS_HUGE_TLB_SUPPORT is not set -CONFIG_MIPS_L1_CACHE_SHIFT=6 -CONFIG_MIPS_L1_CACHE_SHIFT_6=y -# CONFIG_MIPS_MACHINE is not set -CONFIG_MIPS_MALTA=y -CONFIG_MIPS_MALTA_PM=y -CONFIG_MIPS_MSC=y -CONFIG_MIPS_MT=y -CONFIG_MIPS_MT_FPAFF=y -CONFIG_MIPS_MT_SMP=y -CONFIG_MIPS_NO_APPENDED_DTB=y -CONFIG_MIPS_PERF_SHARED_TC_COUNTERS=y -# CONFIG_MIPS_RAW_APPENDED_DTB is not set -CONFIG_MIPS_SPRAM=y -# CONFIG_MIPS_VPE_LOADER is not set -CONFIG_MODULES_TREE_LOOKUP=y -CONFIG_MODULES_USE_ELF_REL=y -CONFIG_MODULE_FORCE_UNLOAD=y -CONFIG_MTD_CFI_STAA=y -# CONFIG_MTD_COMPLEX_MAPPINGS is not set -CONFIG_MTD_PHYSMAP=y -CONFIG_NEED_DMA_MAP_STATE=y -CONFIG_NET_FLOW_LIMIT=y -CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y -CONFIG_NO_HZ=y -CONFIG_NO_HZ_COMMON=y -CONFIG_NO_HZ_IDLE=y -# CONFIG_NO_IOPORT_MAP is not set -CONFIG_NR_CPUS=2 -CONFIG_OF=y -CONFIG_OF_ADDRESS=y -CONFIG_OF_ADDRESS_PCI=y -CONFIG_OF_EARLY_FLATTREE=y -CONFIG_OF_FLATTREE=y -CONFIG_OF_IRQ=y -CONFIG_OF_NET=y -CONFIG_OF_PCI=y -CONFIG_OF_PCI_IRQ=y -CONFIG_PADATA=y -# CONFIG_PARTITION_ADVANCED is not set -CONFIG_PCI=y -CONFIG_PCI_DOMAINS=y -CONFIG_PCI_DRIVERS_LEGACY=y -CONFIG_PCI_GT64XXX_PCI0=y -CONFIG_PCSPKR_PLATFORM=y -CONFIG_PERF_EVENTS=y -CONFIG_PERF_USE_VMALLOC=y -CONFIG_PGTABLE_LEVELS=2 -CONFIG_PRINT_QUOTA_WARNING=y -CONFIG_PROC_PAGE_MONITOR=y -# CONFIG_QFMT_V1 is not set -CONFIG_QFMT_V2=y -CONFIG_QUEUED_RWLOCKS=y -CONFIG_QUEUED_SPINLOCKS=y -CONFIG_QUOTA=y -CONFIG_QUOTACTL=y -# CONFIG_QUOTA_NETLINK_INTERFACE is not set -CONFIG_QUOTA_TREE=y -CONFIG_RATIONAL=y -CONFIG_RCU_NEED_SEGCBLIST=y -CONFIG_RCU_STALL_COMMON=y -CONFIG_RELAY=y -CONFIG_RFS_ACCEL=y -CONFIG_RPS=y -CONFIG_RTC_CLASS=y -CONFIG_RTC_MC146818_LIB=y -# CONFIG_SCHED_INFO is not set -CONFIG_SCSI=y -CONFIG_SECCOMP=y -CONFIG_SECCOMP_FILTER=y -# CONFIG_SERIAL_8250_FSL is not set -CONFIG_SERIAL_8250_NR_UARTS=4 -CONFIG_SERIAL_8250_RUNTIME_UARTS=4 -CONFIG_SERIO=y -CONFIG_SERIO_SERPORT=y -CONFIG_SG_POOL=y -CONFIG_SMP=y -CONFIG_SMP_UP=y -CONFIG_SRCU=y -CONFIG_SWAP_IO_SPACE=y -CONFIG_SYNC_R4K=y -CONFIG_SYSCTL_EXCEPTION_TRACE=y -CONFIG_SYSFS_DEPRECATED=y -CONFIG_SYSFS_DEPRECATED_V2=y -CONFIG_SYS_HAS_CPU_MIPS32_R1=y -CONFIG_SYS_HAS_CPU_MIPS32_R2=y -CONFIG_SYS_HAS_CPU_MIPS32_R3_5=y -CONFIG_SYS_HAS_CPU_MIPS32_R5=y -CONFIG_SYS_HAS_CPU_MIPS32_R6=y -CONFIG_SYS_HAS_CPU_MIPS64_R1=y -CONFIG_SYS_HAS_CPU_MIPS64_R2=y -CONFIG_SYS_HAS_CPU_MIPS64_R6=y -CONFIG_SYS_HAS_CPU_NEVADA=y -CONFIG_SYS_HAS_CPU_RM7000=y -CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y -CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y -CONFIG_SYS_SUPPORTS_ARBIT_HZ=y -CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y -CONFIG_SYS_SUPPORTS_HIGHMEM=y -CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y -CONFIG_SYS_SUPPORTS_MICROMIPS=y -CONFIG_SYS_SUPPORTS_MIPS16=y -CONFIG_SYS_SUPPORTS_MIPS_CMP=y -CONFIG_SYS_SUPPORTS_MIPS_CPS=y -CONFIG_SYS_SUPPORTS_MULTITHREADING=y -CONFIG_SYS_SUPPORTS_RELOCATABLE=y -CONFIG_SYS_SUPPORTS_SCHED_SMT=y -CONFIG_SYS_SUPPORTS_SMARTMIPS=y -CONFIG_SYS_SUPPORTS_SMP=y -CONFIG_SYS_SUPPORTS_ZBOOT=y -CONFIG_TICK_CPU_ACCOUNTING=y -CONFIG_TIMER_OF=y -CONFIG_TIMER_PROBE=y -CONFIG_TREE_RCU=y -CONFIG_TREE_SRCU=y -CONFIG_USB_SUPPORT=y -# CONFIG_USERIO is not set -CONFIG_USE_OF=y -# CONFIG_VGA_CONSOLE is not set -CONFIG_VM_EVENT_COUNTERS=y -CONFIG_VT=y -CONFIG_VT_CONSOLE=y -CONFIG_VT_HW_CONSOLE_BINDING=y -CONFIG_VXFS_FS=y -CONFIG_XPS=y From patchwork Sun Mar 1 12:12:36 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hauke Mehrtens X-Patchwork-Id: 1247281 X-Patchwork-Delegate: hauke@hauke-m.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) 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with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1j8NSq-0006gg-Q2 for openwrt-devel@lists.openwrt.org; Sun, 01 Mar 2020 12:13:01 +0000 Received: from smtp2.mailbox.org (smtp2.mailbox.org [80.241.60.241]) (using TLSv1.2 with cipher ECDHE-RSA-CHACHA20-POLY1305 (256/256 bits)) (No client certificate requested) by mout-p-201.mailbox.org (Postfix) with ESMTPS id 48VhxL2TrKzQlBp; Sun, 1 Mar 2020 13:12:54 +0100 (CET) X-Virus-Scanned: amavisd-new at heinlein-support.de Received: from smtp2.mailbox.org ([80.241.60.241]) by spamfilter02.heinlein-hosting.de (spamfilter02.heinlein-hosting.de [80.241.56.116]) (amavisd-new, port 10030) with ESMTP id D1Pqw1To6jMO; Sun, 1 Mar 2020 13:12:50 +0100 (CET) From: Hauke Mehrtens To: openwrt-devel@lists.openwrt.org Date: Sun, 1 Mar 2020 13:12:36 +0100 Message-Id: <20200301121241.5545-8-hauke@hauke-m.de> In-Reply-To: <20200301121241.5545-1-hauke@hauke-m.de> References: <20200301121241.5545-1-hauke@hauke-m.de> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200301_041257_178141_15A5A36D X-CRM114-Status: GOOD ( 16.21 ) X-Spam-Score: 0.0 (/) X-Spam-Report: SpamAssassin version 3.4.3 on bombadil.infradead.org summary: Content analysis details: (0.0 points) pts rule name description ---- ---------------------- -------------------------------------------------- 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.0 SPF_PASS SPF: sender matches SPF record Subject: [OpenWrt-Devel] [PATCH 07/12] mpc85xx: Remove kernel 4.14 support X-BeenThere: openwrt-devel@lists.openwrt.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: hauke@hauke-m.de Sender: "openwrt-devel" Errors-To: openwrt-devel-bounces+incoming=patchwork.ozlabs.org@lists.openwrt.org This target was switched to kernel 4.19 more than 6 months ago in commit f342ffd300da ("treewide: kernel: bump some targets to 4.19") and now with kernel 5.4 support being added it gets harder to support kernel 4.14 in addition to kernel 4.19 and 5.4. Signed-off-by: Hauke Mehrtens --- target/linux/mpc85xx/config-4.14 | 365 ------------------ ...85xx-add-gpio-keys-to-of-match-table.patch | 10 - ...0-powerpc-85xx-tl-wdr4900-v1-support.patch | 82 ---- .../101-powerpc-85xx-hiveap-330-support.patch | 30 -- .../102-powerpc-add-cmdline-override.patch | 37 -- .../103-powerpc-fix-build-cross32ar.patch | 10 - ...change-P2020RDB-dts-file-for-OpenWRT.patch | 170 -------- .../105-powerpc-85xx-red-15w-rev1.patch | 29 -- .../106-powerpc-85xx-panda-support.patch | 30 -- 9 files changed, 763 deletions(-) delete mode 100644 target/linux/mpc85xx/config-4.14 delete mode 100644 target/linux/mpc85xx/patches-4.14/001-powerpc-85xx-add-gpio-keys-to-of-match-table.patch delete mode 100644 target/linux/mpc85xx/patches-4.14/100-powerpc-85xx-tl-wdr4900-v1-support.patch delete mode 100644 target/linux/mpc85xx/patches-4.14/101-powerpc-85xx-hiveap-330-support.patch delete mode 100644 target/linux/mpc85xx/patches-4.14/102-powerpc-add-cmdline-override.patch delete mode 100644 target/linux/mpc85xx/patches-4.14/103-powerpc-fix-build-cross32ar.patch delete mode 100644 target/linux/mpc85xx/patches-4.14/104-powerpc-mpc85xx-change-P2020RDB-dts-file-for-OpenWRT.patch delete mode 100644 target/linux/mpc85xx/patches-4.14/105-powerpc-85xx-red-15w-rev1.patch delete mode 100644 target/linux/mpc85xx/patches-4.14/106-powerpc-85xx-panda-support.patch diff --git a/target/linux/mpc85xx/config-4.14 b/target/linux/mpc85xx/config-4.14 deleted file mode 100644 index dd80f2cdd76a..000000000000 --- a/target/linux/mpc85xx/config-4.14 +++ /dev/null @@ -1,365 +0,0 @@ -# CONFIG_40x is not set -# CONFIG_44x is not set -# CONFIG_ADVANCED_OPTIONS is not set -CONFIG_AR8216_PHY=y -CONFIG_AR8216_PHY_LEDS=y -CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y -CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y -CONFIG_ARCH_HAS_DMA_SET_COHERENT_MASK=y -CONFIG_ARCH_HAS_ELF_RANDOMIZE=y -CONFIG_ARCH_HAS_FORTIFY_SOURCE=y -CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y -CONFIG_ARCH_HAS_SG_CHAIN=y -CONFIG_ARCH_HAS_STRICT_KERNEL_RWX=y -# CONFIG_ARCH_HAS_STRICT_MODULE_RWX is not set -CONFIG_ARCH_HAS_WALK_MEMORY=y -CONFIG_ARCH_HAVE_NMI_SAFE_CMPXCHG=y -CONFIG_ARCH_HIBERNATION_POSSIBLE=y -CONFIG_ARCH_MAY_HAVE_PC_FDC=y -CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y -CONFIG_ARCH_MIGHT_HAVE_PC_SERIO=y -CONFIG_ARCH_MMAP_RND_BITS=11 -CONFIG_ARCH_MMAP_RND_BITS_MAX=17 -CONFIG_ARCH_MMAP_RND_BITS_MIN=11 -CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=17 -CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11 -CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y -# CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT is not set -# CONFIG_ARCH_RANDOM is not set -CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y -CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y -CONFIG_ARCH_SUPPORTS_DEFERRED_STRUCT_PAGE_INIT=y -CONFIG_ARCH_SUPPORTS_UPROBES=y -CONFIG_ARCH_SUSPEND_POSSIBLE=y -CONFIG_ARCH_USE_BUILTIN_BSWAP=y -CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y -CONFIG_ARCH_WEAK_RELEASE_ACQUIRE=y -CONFIG_ASN1=y -CONFIG_AUDIT_ARCH=y -CONFIG_BLK_MQ_PCI=y -CONFIG_BOOKE=y -CONFIG_BOOKE_WDT=y -CONFIG_BOUNCE=y -# CONFIG_BSC9131_RDB is not set -# CONFIG_BSC9132_QDS is not set -# CONFIG_C293_PCIE is not set -CONFIG_CLONE_BACKWARDS=y -CONFIG_CLZ_TAB=y -CONFIG_CMDLINE="console=ttyS0,115200" -CONFIG_CMDLINE_BOOL=y -# CONFIG_CMDLINE_OVERRIDE is not set -# CONFIG_CORENET_GENERIC is not set -# CONFIG_CPM2 is not set -CONFIG_CPU_BIG_ENDIAN=y -CONFIG_CRYPTO_AEAD=y -CONFIG_CRYPTO_AEAD2=y -# CONFIG_CRYPTO_AES_PPC_SPE is not set -CONFIG_CRYPTO_AKCIPHER=y -CONFIG_CRYPTO_AKCIPHER2=y -CONFIG_CRYPTO_AUTHENC=y -CONFIG_CRYPTO_HASH=y -CONFIG_CRYPTO_HASH2=y -CONFIG_CRYPTO_HW=y -CONFIG_CRYPTO_MANAGER=y -CONFIG_CRYPTO_MANAGER2=y -# CONFIG_CRYPTO_MD5_PPC is not set -CONFIG_CRYPTO_NULL=y -CONFIG_CRYPTO_NULL2=y -CONFIG_CRYPTO_RNG=y -CONFIG_CRYPTO_RNG2=y -CONFIG_CRYPTO_RSA=y -# CONFIG_CRYPTO_SHA1_PPC is not set -# CONFIG_CRYPTO_SHA1_PPC_SPE is not set -# CONFIG_CRYPTO_SHA256_PPC_SPE is not set -CONFIG_CRYPTO_WORKQUEUE=y -CONFIG_DEBUG_BUGVERBOSE=y -# CONFIG_DEFAULT_UIMAGE is not set -CONFIG_DNOTIFY=y -CONFIG_DTC=y -# CONFIG_E200 is not set -CONFIG_E500=y -CONFIG_EARLY_PRINTK=y -CONFIG_EDAC_ATOMIC_SCRUB=y -CONFIG_EDAC_SUPPORT=y -CONFIG_ENABLE_MUST_CHECK=y -# CONFIG_EPAPR_BOOT is not set -CONFIG_ETHERNET_PACKET_MANGLE=y -# CONFIG_FHCI_DEBUG is not set -CONFIG_FIXED_PHY=y -# CONFIG_FORCE_SMP is not set -CONFIG_FSL_BOOKE=y -# CONFIG_FSL_DPAA is not set -CONFIG_FSL_EMB_PERFMON=y -# CONFIG_FSL_FMAN is not set -CONFIG_FSL_GTM=y -CONFIG_FSL_LBC=y -CONFIG_FSL_PCI=y -CONFIG_FSL_PQ_MDIO=y -CONFIG_FSL_SOC=y -CONFIG_FSL_SOC_BOOKE=y -# CONFIG_FSL_ULI1575 is not set -CONFIG_GENERIC_ALLOCATOR=y -CONFIG_GENERIC_ATOMIC64=y -CONFIG_GENERIC_BUG=y -CONFIG_GENERIC_CLOCKEVENTS=y -CONFIG_GENERIC_CMOS_UPDATE=y -CONFIG_GENERIC_CPU_AUTOPROBE=y -# CONFIG_GENERIC_CSUM is not set -CONFIG_GENERIC_IO=y -CONFIG_GENERIC_IRQ_SHOW=y -CONFIG_GENERIC_IRQ_SHOW_LEVEL=y -CONFIG_GENERIC_ISA_DMA=y -CONFIG_GENERIC_NVRAM=y -CONFIG_GENERIC_PCI_IOMAP=y -CONFIG_GENERIC_SMP_IDLE_THREAD=y -CONFIG_GENERIC_STRNCPY_FROM_USER=y -CONFIG_GENERIC_STRNLEN_USER=y -# CONFIG_GENERIC_TBSYNC is not set -CONFIG_GENERIC_TIME_VSYSCALL=y -CONFIG_GEN_RTC=y -# CONFIG_GE_FPGA is not set -# CONFIG_GE_IMP3A is not set -CONFIG_GIANFAR=y -CONFIG_GPIOLIB=y -CONFIG_GPIO_GENERIC=y -CONFIG_GPIO_MPC8XXX=y -CONFIG_GPIO_SYSFS=y -# CONFIG_GRO_CELLS is not set -CONFIG_HAS_DMA=y -CONFIG_HAS_IOMEM=y -CONFIG_HAS_IOPORT_MAP=y -# CONFIG_HAS_RAPIDIO is not set -# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set -CONFIG_HAVE_ARCH_AUDITSYSCALL=y -# CONFIG_HAVE_ARCH_BITREVERSE is not set -CONFIG_HAVE_ARCH_JUMP_LABEL=y -CONFIG_HAVE_ARCH_KGDB=y -CONFIG_HAVE_ARCH_SECCOMP_FILTER=y -CONFIG_HAVE_ARCH_TRACEHOOK=y -# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set -CONFIG_HAVE_CBPF_JIT=y -CONFIG_HAVE_DEBUG_KMEMLEAK=y -CONFIG_HAVE_DEBUG_STACKOVERFLOW=y -CONFIG_HAVE_DMA_API_DEBUG=y -CONFIG_HAVE_DYNAMIC_FTRACE=y -CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y -CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y -CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y -CONFIG_HAVE_FUNCTION_TRACER=y -# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set -CONFIG_HAVE_GENERIC_GUP=y -CONFIG_HAVE_IDE=y -CONFIG_HAVE_IOREMAP_PROT=y -CONFIG_HAVE_IRQ_EXIT_ON_IRQ_STACK=y -CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y -CONFIG_HAVE_KPROBES_ON_FTRACE=y -CONFIG_HAVE_MEMBLOCK=y -CONFIG_HAVE_MEMBLOCK_NODE_MAP=y -CONFIG_HAVE_MOD_ARCH_SPECIFIC=y -CONFIG_HAVE_NET_DSA=y -CONFIG_HAVE_OPROFILE=y -CONFIG_HAVE_PERF_EVENTS=y -CONFIG_HAVE_PERF_REGS=y -CONFIG_HAVE_PERF_USER_STACK_DUMP=y -CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y -# CONFIG_HAVE_SETUP_PER_CPU_AREA is not set -CONFIG_HAVE_SYSCALL_TRACEPOINTS=y -CONFIG_HAVE_VIRT_CPU_ACCOUNTING=y -# CONFIG_HIVEAP_330 is not set -CONFIG_HW_RANDOM=y -CONFIG_HZ=250 -# CONFIG_HZ_100 is not set -CONFIG_HZ_250=y -CONFIG_HZ_PERIODIC=y -CONFIG_I2C=y -CONFIG_I2C_BOARDINFO=y -CONFIG_I2C_MPC=y -CONFIG_ILLEGAL_POINTER_VALUE=0 -CONFIG_INITRAMFS_SOURCE="" -CONFIG_IOMMU_HELPER=y -# CONFIG_IPIC is not set -CONFIG_IRQCHIP=y -CONFIG_IRQ_DOMAIN=y -CONFIG_IRQ_FORCED_THREADING=y -CONFIG_IRQ_WORK=y -CONFIG_ISA_DMA_API=y -CONFIG_KERNEL_GZIP=y -CONFIG_KERNEL_START=0xc0000000 -# CONFIG_KSI8560 is not set -CONFIG_LIBFDT=y -CONFIG_LOWMEM_CAM_NUM=3 -CONFIG_LOWMEM_SIZE=0x30000000 -CONFIG_LXT_PHY=y -# CONFIG_MATH_EMULATION is not set -CONFIG_MDIO_BUS=y -CONFIG_MDIO_DEVICE=y -CONFIG_MIGRATION=y -# CONFIG_MMIO_NVRAM is not set -CONFIG_MODULES_USE_ELF_RELA=y -# CONFIG_MPC8536_DS is not set -# CONFIG_MPC8540_ADS is not set -# CONFIG_MPC8560_ADS is not set -# CONFIG_MPC85xx_CDS is not set -# CONFIG_MPC85xx_DS is not set -# CONFIG_MPC85xx_MDS is not set -# CONFIG_MPC85xx_RDB is not set -CONFIG_MPIC=y -# CONFIG_MPIC_MSGR is not set -CONFIG_MPIC_TIMER=y -# CONFIG_MPIC_U3_HT_IRQS is not set -# CONFIG_MPIC_WEIRD is not set -CONFIG_MPILIB=y -# CONFIG_MTD_CFI is not set -CONFIG_MTD_M25P80=y -CONFIG_MTD_NAND=y -CONFIG_MTD_NAND_ECC=y -CONFIG_MTD_SPI_NOR=y -# CONFIG_MVME2500 is not set -# CONFIG_NEED_DMA_MAP_STATE is not set -# CONFIG_NEED_PER_CPU_EMBED_FIRST_CHUNK is not set -CONFIG_NEED_PER_CPU_KM=y -CONFIG_NEED_SG_DMA_LENGTH=y -CONFIG_NLS=y -# CONFIG_NONSTATIC_KERNEL is not set -CONFIG_NO_BOOTMEM=y -CONFIG_NR_IRQS=512 -CONFIG_OF=y -CONFIG_OF_ADDRESS=y -CONFIG_OF_ADDRESS_PCI=y -CONFIG_OF_EARLY_FLATTREE=y -CONFIG_OF_FLATTREE=y -CONFIG_OF_GPIO=y -CONFIG_OF_IRQ=y -CONFIG_OF_MDIO=y -CONFIG_OF_NET=y -CONFIG_OF_PCI=y -CONFIG_OF_PCI_IRQ=y -CONFIG_OF_RESERVED_MEM=y -CONFIG_OLD_SIGACTION=y -CONFIG_OLD_SIGSUSPEND=y -# CONFIG_P1010_RDB is not set -# CONFIG_P1022_DS is not set -# CONFIG_P1022_RDK is not set -# CONFIG_P1023_RDB is not set -CONFIG_PAGE_OFFSET=0xc0000000 -# CONFIG_PANDA is not set -CONFIG_PCI=y -CONFIG_PCIEAER=y -CONFIG_PCIEASPM=y -# CONFIG_PCIEASPM_DEBUG is not set -CONFIG_PCIEASPM_DEFAULT=y -# CONFIG_PCIEASPM_PERFORMANCE is not set -# CONFIG_PCIEASPM_POWERSAVE is not set -# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set -CONFIG_PCIEPORTBUS=y -CONFIG_PCI_DOMAINS=y -CONFIG_PGTABLE_LEVELS=2 -CONFIG_PHYLIB=y -CONFIG_PHYSICAL_ALIGN=0x04000000 -CONFIG_PHYSICAL_START=0x00000000 -# CONFIG_PHYS_64BIT is not set -# CONFIG_PPA8548 is not set -CONFIG_PPC=y -CONFIG_PPC32=y -# CONFIG_PPC64 is not set -CONFIG_PPC_85xx=y -# CONFIG_PPC_8xx is not set -# CONFIG_PPC_970_NAP is not set -CONFIG_PPC_ADV_DEBUG_DACS=2 -CONFIG_PPC_ADV_DEBUG_DVCS=0 -CONFIG_PPC_ADV_DEBUG_IACS=2 -CONFIG_PPC_ADV_DEBUG_REGS=y -CONFIG_PPC_BOOK3E_MMU=y -# CONFIG_PPC_BOOK3S_32 is not set -# CONFIG_PPC_CELL is not set -# CONFIG_PPC_CELL_NATIVE is not set -# CONFIG_PPC_COPRO_BASE is not set -# CONFIG_PPC_DCR_MMIO is not set -# CONFIG_PPC_DCR_NATIVE is not set -CONFIG_PPC_DOORBELL=y -# CONFIG_PPC_E500MC is not set -# CONFIG_PPC_EARLY_DEBUG is not set -# CONFIG_PPC_EPAPR_HV_PIC is not set -CONFIG_PPC_FSL_BOOK3E=y -# CONFIG_PPC_I8259 is not set -# CONFIG_PPC_ICP_HV is not set -# CONFIG_PPC_ICP_NATIVE is not set -# CONFIG_PPC_ICS_RTAS is not set -CONFIG_PPC_INDIRECT_PCI=y -CONFIG_PPC_MMU_NOHASH=y -# CONFIG_PPC_MM_SLICES is not set -# CONFIG_PPC_MPC106 is not set -# CONFIG_PPC_P7_NAP is not set -CONFIG_PPC_PCI_CHOICE=y -# CONFIG_PPC_PTDUMP is not set -# CONFIG_PPC_QEMU_E500 is not set -# CONFIG_PPC_RTAS is not set -CONFIG_PPC_SMP_MUXED_IPI=y -CONFIG_PPC_UDBG_16550=y -CONFIG_PPC_WERROR=y -# CONFIG_PPC_XICS is not set -# CONFIG_PPC_XIVE is not set -# CONFIG_PPC_XIVE_SPAPR is not set -# CONFIG_PQ2ADS is not set -CONFIG_QE_GPIO=y -CONFIG_QE_USB=y -CONFIG_QUICC_ENGINE=y -CONFIG_RAS=y -# CONFIG_RCU_NEED_SEGCBLIST is not set -# CONFIG_RCU_STALL_COMMON is not set -# CONFIG_RED_15W_REV1 is not set -CONFIG_REGMAP=y -CONFIG_REGMAP_I2C=y -CONFIG_REGMAP_SPI=y -CONFIG_RTC_CLASS=y -CONFIG_RTC_DRV_GENERIC=y -CONFIG_RTC_I2C_AND_SPI=y -CONFIG_RTC_MC146818_LIB=y -CONFIG_RWSEM_XCHGADD_ALGORITHM=y -# CONFIG_SBC8548 is not set -# CONFIG_SCHED_INFO is not set -# CONFIG_SCSI_DMA is not set -CONFIG_SERIAL_8250_EXTENDED=y -CONFIG_SERIAL_8250_FSL=y -CONFIG_SERIAL_8250_SHARE_IRQ=y -CONFIG_SERIAL_OF_PLATFORM=y -# CONFIG_SERIAL_QE is not set -CONFIG_SIMPLE_GPIO=y -# CONFIG_SOCRATES is not set -CONFIG_SPARSE_IRQ=y -CONFIG_SPE=y -CONFIG_SPE_POSSIBLE=y -CONFIG_SPI=y -CONFIG_SPI_FSL_ESPI=y -CONFIG_SPI_MASTER=y -CONFIG_SRCU=y -# CONFIG_STRIP_ASM_SYMS is not set -# CONFIG_STX_GP3 is not set -CONFIG_SWCONFIG=y -CONFIG_SWIOTLB=y -CONFIG_SWPHY=y -CONFIG_SYSCTL_EXCEPTION_TRACE=y -CONFIG_TASK_SIZE=0xc0000000 -CONFIG_THREAD_SHIFT=13 -CONFIG_TICK_CPU_ACCOUNTING=y -CONFIG_TINY_SRCU=y -# CONFIG_TL_WDR4900_V1 is not set -# CONFIG_TQM8540 is not set -# CONFIG_TQM8541 is not set -# CONFIG_TQM8548 is not set -# CONFIG_TQM8555 is not set -# CONFIG_TQM8560 is not set -# CONFIG_TWR_P102x is not set -CONFIG_UCC=y -CONFIG_UCC_FAST=y -CONFIG_UCC_GETH=y -# CONFIG_UGETH_TX_ON_DEMAND is not set -CONFIG_USB_SUPPORT=y -CONFIG_VDSO32=y -# CONFIG_VIRT_CPU_ACCOUNTING_NATIVE is not set -CONFIG_VM_EVENT_COUNTERS=y -CONFIG_WATCHDOG_CORE=y -# CONFIG_XES_MPC85xx is not set -# CONFIG_XPS_USB_HCD_XILINX is not set -CONFIG_XZ_DEC_BCJ=y -CONFIG_XZ_DEC_POWERPC=y diff --git a/target/linux/mpc85xx/patches-4.14/001-powerpc-85xx-add-gpio-keys-to-of-match-table.patch b/target/linux/mpc85xx/patches-4.14/001-powerpc-85xx-add-gpio-keys-to-of-match-table.patch deleted file mode 100644 index 58c4be60070a..000000000000 --- a/target/linux/mpc85xx/patches-4.14/001-powerpc-85xx-add-gpio-keys-to-of-match-table.patch +++ /dev/null @@ -1,10 +0,0 @@ ---- a/arch/powerpc/platforms/85xx/common.c -+++ b/arch/powerpc/platforms/85xx/common.c -@@ -33,6 +33,7 @@ static const struct of_device_id mpc85xx - { .compatible = "fsl,mpc8548-guts", }, - /* Probably unnecessary? */ - { .compatible = "gpio-leds", }, -+ { .compatible = "gpio-keys", }, - /* For all PCI controllers */ - { .compatible = "fsl,mpc8540-pci", }, - { .compatible = "fsl,mpc8548-pcie", }, diff --git a/target/linux/mpc85xx/patches-4.14/100-powerpc-85xx-tl-wdr4900-v1-support.patch b/target/linux/mpc85xx/patches-4.14/100-powerpc-85xx-tl-wdr4900-v1-support.patch deleted file mode 100644 index 86b6a577354c..000000000000 --- a/target/linux/mpc85xx/patches-4.14/100-powerpc-85xx-tl-wdr4900-v1-support.patch +++ /dev/null @@ -1,82 +0,0 @@ -From 53bc6ae5da3b2902581c30ac2568f51ce35e7624 Mon Sep 17 00:00:00 2001 -From: Gabor Juhos -Date: Wed, 20 Feb 2013 08:40:33 +0100 -Subject: [PATCH] powerpc: 85xx: add support for the TP-Link TL-WDR4900 v1 - board - -This patch adds support for the TP-Link TL-WDR4900 v1 -concurrent dual-band wireless router. The devices uses -the Freescale P1014 SoC. - -Signed-off-by: Gabor Juhos -Signed-off-by: Pawel Dembicki ---- - arch/powerpc/boot/Makefile | 3 ++- - arch/powerpc/boot/wrapper | 5 +++++ - arch/powerpc/platforms/85xx/Kconfig | 11 +++++++++++ - arch/powerpc/platforms/85xx/Makefile | 1 + - 4 files changed, 19 insertions(+), 1 deletion(-) - ---- a/arch/powerpc/boot/Makefile -+++ b/arch/powerpc/boot/Makefile -@@ -156,6 +156,7 @@ src-plat-$(CONFIG_PPC_PSERIES) += pserie - src-plat-$(CONFIG_PPC_POWERNV) += pseries-head.S - src-plat-$(CONFIG_PPC_IBM_CELL_BLADE) += pseries-head.S - src-plat-$(CONFIG_MVME7100) += motload-head.S mvme7100.c -+src-plat-$(CONFIG_TL_WDR4900_V1) += simpleboot.c fixed-head.S - - src-wlib := $(sort $(src-wlib-y)) - src-plat := $(sort $(src-plat-y)) -@@ -335,7 +336,7 @@ image-$(CONFIG_TQM8555) += cuImage.tqm - image-$(CONFIG_TQM8560) += cuImage.tqm8560 - image-$(CONFIG_SBC8548) += cuImage.sbc8548 - image-$(CONFIG_KSI8560) += cuImage.ksi8560 -- -+image-$(CONFIG_TL_WDR4900_V1) += simpleImage.tl-wdr4900-v1 - # Board ports in arch/powerpc/platform/86xx/Kconfig - image-$(CONFIG_MVME7100) += dtbImage.mvme7100 - ---- a/arch/powerpc/boot/wrapper -+++ b/arch/powerpc/boot/wrapper -@@ -302,6 +302,11 @@ adder875-redboot) - platformo="$object/fixed-head.o $object/redboot-8xx.o" - binary=y - ;; -+simpleboot-tl-wdr4900-v1) -+ platformo="$object/fixed-head.o $object/simpleboot.o" -+ link_address='0x1000000' -+ binary=y -+ ;; - simpleboot-virtex405-*) - platformo="$object/virtex405-head.o $object/simpleboot.o $object/virtex.o" - binary=y ---- a/arch/powerpc/platforms/85xx/Kconfig -+++ b/arch/powerpc/platforms/85xx/Kconfig -@@ -170,6 +170,17 @@ config STX_GP3 - select CPM2 - select DEFAULT_UIMAGE - -+config TL_WDR4900_V1 -+ bool "TP-Link TL-WDR4900 v1" -+ select DEFAULT_UIMAGE -+ select ARCH_REQUIRE_GPIOLIB -+ select GPIO_MPC8XXX -+ help -+ This option enables support for the TP-Link TL-WDR4900 v1 board. -+ -+ This board is a Concurrent Dual-Band wireless router with a -+ Freescale P1014 SoC. -+ - config TQM8540 - bool "TQ Components TQM8540" - help ---- a/arch/powerpc/platforms/85xx/Makefile -+++ b/arch/powerpc/platforms/85xx/Makefile -@@ -26,6 +26,7 @@ obj-$(CONFIG_CORENET_GENERIC) += coren - obj-$(CONFIG_FB_FSL_DIU) += t1042rdb_diu.o - obj-$(CONFIG_STX_GP3) += stx_gp3.o - obj-$(CONFIG_TQM85xx) += tqm85xx.o -+obj-$(CONFIG_TL_WDR4900_V1) += tl_wdr4900_v1.o - obj-$(CONFIG_SBC8548) += sbc8548.o - obj-$(CONFIG_PPA8548) += ppa8548.o - obj-$(CONFIG_SOCRATES) += socrates.o socrates_fpga_pic.o diff --git a/target/linux/mpc85xx/patches-4.14/101-powerpc-85xx-hiveap-330-support.patch b/target/linux/mpc85xx/patches-4.14/101-powerpc-85xx-hiveap-330-support.patch deleted file mode 100644 index 34568398c2ff..000000000000 --- a/target/linux/mpc85xx/patches-4.14/101-powerpc-85xx-hiveap-330-support.patch +++ /dev/null @@ -1,30 +0,0 @@ ---- a/arch/powerpc/platforms/85xx/Kconfig -+++ b/arch/powerpc/platforms/85xx/Kconfig -@@ -49,6 +49,17 @@ config BSC9132_QDS - and dual StarCore SC3850 DSP cores. - Manufacturer : Freescale Semiconductor, Inc - -+config HIVEAP_330 -+ bool "Aerohive HiveAP-330" -+ select DEFAULT_UIMAGE -+ select ARCH_REQUIRE_GPIOLIB -+ select GPIO_MPC8XXX -+ help -+ This option enables support for the Aerohive HiveAP-330 board. -+ -+ This board is a Concurrent Dual-Band wireless access point with a -+ Freescale P1020 SoC. -+ - config MPC8540_ADS - bool "Freescale MPC8540 ADS" - select DEFAULT_UIMAGE ---- a/arch/powerpc/platforms/85xx/Makefile -+++ b/arch/powerpc/platforms/85xx/Makefile -@@ -10,6 +10,7 @@ obj-y += common.o - obj-$(CONFIG_BSC9131_RDB) += bsc913x_rdb.o - obj-$(CONFIG_BSC9132_QDS) += bsc913x_qds.o - obj-$(CONFIG_C293_PCIE) += c293pcie.o -+obj-$(CONFIG_HIVEAP_330) += hiveap-330.o - obj-$(CONFIG_MPC8540_ADS) += mpc85xx_ads.o - obj-$(CONFIG_MPC8560_ADS) += mpc85xx_ads.o - obj-$(CONFIG_MPC85xx_CDS) += mpc85xx_cds.o diff --git a/target/linux/mpc85xx/patches-4.14/102-powerpc-add-cmdline-override.patch b/target/linux/mpc85xx/patches-4.14/102-powerpc-add-cmdline-override.patch deleted file mode 100644 index 087798e3d813..000000000000 --- a/target/linux/mpc85xx/patches-4.14/102-powerpc-add-cmdline-override.patch +++ /dev/null @@ -1,37 +0,0 @@ ---- a/arch/powerpc/Kconfig -+++ b/arch/powerpc/Kconfig -@@ -837,6 +837,14 @@ config CMDLINE_FORCE - This is useful if you cannot or don't want to change the - command-line options your boot loader passes to the kernel. - -+config CMDLINE_OVERRIDE -+ bool "Use alternative cmdline from device tree" -+ help -+ Some bootloaders may have uneditable bootargs. While CMDLINE_FORCE can -+ be used, this is not a good option for kernels that are shared across -+ devices. This setting enables using "chosen/cmdline-override" as the -+ cmdline if it exists in the device tree. -+ - config EXTRA_TARGETS - string "Additional default image types" - help ---- a/drivers/of/fdt.c -+++ b/drivers/of/fdt.c -@@ -1131,6 +1131,17 @@ int __init early_init_dt_scan_chosen(uns - if (p != NULL && l > 0) - strlcpy(data, p, min((int)l, COMMAND_LINE_SIZE)); - -+ /* CONFIG_CMDLINE_OVERRIDE is used to fallback to a different -+ * device tree option of chosen/bootargs-override. This is -+ * helpful on boards where u-boot sets bootargs, and is unable -+ * to be modified. -+ */ -+#ifdef CONFIG_CMDLINE_OVERRIDE -+ p = of_get_flat_dt_prop(node, "bootargs-override", &l); -+ if (p != NULL && l > 0) -+ strlcpy(data, p, min((int)l, COMMAND_LINE_SIZE)); -+#endif -+ - /* - * CONFIG_CMDLINE is meant to be a default in case nothing else - * managed to set the command line, unless CONFIG_CMDLINE_FORCE diff --git a/target/linux/mpc85xx/patches-4.14/103-powerpc-fix-build-cross32ar.patch b/target/linux/mpc85xx/patches-4.14/103-powerpc-fix-build-cross32ar.patch deleted file mode 100644 index 7ed52f649c4e..000000000000 --- a/target/linux/mpc85xx/patches-4.14/103-powerpc-fix-build-cross32ar.patch +++ /dev/null @@ -1,10 +0,0 @@ ---- a/arch/powerpc/Makefile -+++ b/arch/powerpc/Makefile -@@ -23,6 +23,7 @@ CROSS32AR := $(CROSS32_COMPILE)ar - ifeq ($(HAS_BIARCH),y) - ifeq ($(CROSS32_COMPILE),) - CROSS32CC := $(CC) -m32 -+CROSS32AR := $(AR) - KBUILD_ARFLAGS += --target=elf32-powerpc - endif - endif diff --git a/target/linux/mpc85xx/patches-4.14/104-powerpc-mpc85xx-change-P2020RDB-dts-file-for-OpenWRT.patch b/target/linux/mpc85xx/patches-4.14/104-powerpc-mpc85xx-change-P2020RDB-dts-file-for-OpenWRT.patch deleted file mode 100644 index 39c72314b8da..000000000000 --- a/target/linux/mpc85xx/patches-4.14/104-powerpc-mpc85xx-change-P2020RDB-dts-file-for-OpenWRT.patch +++ /dev/null @@ -1,170 +0,0 @@ -From 93514afd769c305182beeed1f9c4c46235879ef8 Mon Sep 17 00:00:00 2001 -From: Pawel Dembicki -Date: Sun, 30 Dec 2018 23:24:41 +0100 -Subject: [PATCH] powerpc: mpc85xx: change P2020RDB dts file for OpenWRT - -This patch apply chages for OpenWRT in P2020RDB -dts file. - -Signed-off-by: Pawel Dembicki ---- - arch/powerpc/boot/dts/fsl/p2020rdb.dts | 98 +++++++++++++++++--------- - 1 file changed, 63 insertions(+), 35 deletions(-) - ---- a/arch/powerpc/boot/dts/fsl/p2020rdb.dts -+++ b/arch/powerpc/boot/dts/fsl/p2020rdb.dts -@@ -2,6 +2,7 @@ - * P2020 RDB Device Tree Source - * - * Copyright 2009-2012 Freescale Semiconductor Inc. -+ * Copyright 2018 Pawel Dembicki - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the -@@ -9,10 +10,15 @@ - * option) any later version. - */ - -+/dts-v1/; -+ - /include/ "p2020si-pre.dtsi" - -+#include -+#include -+ - / { -- model = "fsl,P2020RDB"; -+ model = "Freescale P2020RDB"; - compatible = "fsl,P2020RDB"; - - aliases { -@@ -38,48 +44,38 @@ - 0x2 0x0 0x0 0xffb00000 0x00020000>; - - nor@0,0 { -- #address-cells = <1>; -- #size-cells = <1>; - compatible = "cfi-flash"; - reg = <0x0 0x0 0x1000000>; - bank-width = <2>; - device-width = <1>; - -- partition@0 { -- /* This location must not be altered */ -- /* 256KB for Vitesse 7385 Switch firmware */ -- reg = <0x0 0x00040000>; -- label = "NOR (RO) Vitesse-7385 Firmware"; -- read-only; -- }; -- -- partition@40000 { -- /* 256KB for DTB Image */ -- reg = <0x00040000 0x00040000>; -- label = "NOR (RO) DTB Image"; -- read-only; -- }; -+ partitions { -+ compatible = "fixed-partitions"; -+ #address-cells = <1>; -+ #size-cells = <1>; - -- partition@80000 { -- /* 3.5 MB for Linux Kernel Image */ -- reg = <0x00080000 0x00380000>; -- label = "NOR (RO) Linux Kernel Image"; -- read-only; -- }; -+ partition@0 { -+ /* This location must not be altered */ -+ /* 256KB for Vitesse 7385 Switch firmware */ -+ reg = <0x0 0x00040000>; -+ label = "NOR (RO) Vitesse-7385 Firmware"; -+ read-only; -+ }; - -- partition@400000 { -- /* 11MB for JFFS2 based Root file System */ -- reg = <0x00400000 0x00b00000>; -- label = "NOR (RW) JFFS2 Root File System"; -- }; -+ partition@40000 { -+ compatible = "denx,fit"; -+ reg = <0x00040000 0x00ec0000>; -+ label = "firmware"; -+ }; - -- partition@f00000 { -- /* This location must not be altered */ -- /* 512KB for u-boot Bootloader Image */ -- /* 512KB for u-boot Environment Variables */ -- reg = <0x00f00000 0x00100000>; -- label = "NOR (RO) U-Boot Image"; -- read-only; -+ partition@f00000 { -+ /* This location must not be altered */ -+ /* 512KB for u-boot Bootloader Image */ -+ /* 512KB for u-boot Environment Variables */ -+ reg = <0x00f00000 0x00100000>; -+ label = "u-boot"; -+ read-only; -+ }; - }; - }; - -@@ -144,13 +140,43 @@ - soc: soc@ffe00000 { - ranges = <0x0 0x0 0xffe00000 0x100000>; - -+ gpio0: gpio-controller@fc00 { -+ }; -+ - i2c@3000 { -+ temperature-sensor@4c { -+ compatible = "adi,adt7461"; -+ reg = <0x4c>; -+ }; -+ -+ eeprom@50 { -+ compatible = "atmel,24c256"; -+ reg = <0x50>; -+ }; -+ - rtc@68 { - compatible = "dallas,ds1339"; - reg = <0x68>; - }; - }; - -+ i2c@3100 { -+ pmic@11 { -+ compatible = "zl2006"; -+ reg = <0x11>; -+ }; -+ -+ gpio@18 { -+ compatible = "nxp,pca9557"; -+ reg = <0x18>; -+ }; -+ -+ eeprom@52 { -+ compatible = "atmel,24c01"; -+ reg = <0x52>; -+ }; -+ }; -+ - spi@7000 { - flash@0 { - #address-cells = <1>; -@@ -204,10 +230,12 @@ - phy0: ethernet-phy@0 { - interrupts = <3 1 0 0>; - reg = <0x0>; -+ reset-gpios = <&gpio0 14 GPIO_ACTIVE_LOW>; - }; - phy1: ethernet-phy@1 { - interrupts = <3 1 0 0>; - reg = <0x1>; -+ reset-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; - }; - tbi-phy@2 { - device_type = "tbi-phy"; diff --git a/target/linux/mpc85xx/patches-4.14/105-powerpc-85xx-red-15w-rev1.patch b/target/linux/mpc85xx/patches-4.14/105-powerpc-85xx-red-15w-rev1.patch deleted file mode 100644 index 42bcd58de02b..000000000000 --- a/target/linux/mpc85xx/patches-4.14/105-powerpc-85xx-red-15w-rev1.patch +++ /dev/null @@ -1,29 +0,0 @@ ---- a/arch/powerpc/platforms/85xx/Kconfig -+++ b/arch/powerpc/platforms/85xx/Kconfig -@@ -173,6 +173,16 @@ config XES_MPC85xx - Manufacturer: Extreme Engineering Solutions, Inc. - URL: - -+config RED_15W_REV1 -+ bool "Sophos RED 15w Rev.1" -+ select DEFAULT_UIMAGE -+ select ARCH_REQUIRE_GPIOLIB -+ select GPIO_MPC8XXX -+ help -+ This option enables support for the SOPHOS RED 15w Rev.1 board. -+ -+ This board is a wireless VPN router with a Freescale P1010 SoC. -+ - config STX_GP3 - bool "Silicon Turnkey Express GP3" - help ---- a/arch/powerpc/platforms/85xx/Makefile -+++ b/arch/powerpc/platforms/85xx/Makefile -@@ -25,6 +25,7 @@ obj-$(CONFIG_P1023_RDB) += p1023_rdb.o - obj-$(CONFIG_TWR_P102x) += twr_p102x.o - obj-$(CONFIG_CORENET_GENERIC) += corenet_generic.o - obj-$(CONFIG_FB_FSL_DIU) += t1042rdb_diu.o -+obj-$(CONFIG_RED_15W_REV1) += red15w_rev1.o - obj-$(CONFIG_STX_GP3) += stx_gp3.o - obj-$(CONFIG_TQM85xx) += tqm85xx.o - obj-$(CONFIG_TL_WDR4900_V1) += tl_wdr4900_v1.o diff --git a/target/linux/mpc85xx/patches-4.14/106-powerpc-85xx-panda-support.patch b/target/linux/mpc85xx/patches-4.14/106-powerpc-85xx-panda-support.patch deleted file mode 100644 index a08bc302f211..000000000000 --- a/target/linux/mpc85xx/patches-4.14/106-powerpc-85xx-panda-support.patch +++ /dev/null @@ -1,30 +0,0 @@ ---- a/arch/powerpc/platforms/85xx/Kconfig -+++ b/arch/powerpc/platforms/85xx/Kconfig -@@ -60,6 +60,17 @@ config HIVEAP_330 - This board is a Concurrent Dual-Band wireless access point with a - Freescale P1020 SoC. - -+config PANDA -+ bool "OCEDO PANDA" -+ select DEFAULT_UIMAGE -+ select ARCH_REQUIRE_GPIOLIB -+ select GPIO_MPC8XXX -+ help -+ This option enables support for the OCEDO PANDA board. -+ -+ This board is a Concurrent Dual-Band wireless access point with a -+ Freescale P1020 SoC. -+ - config MPC8540_ADS - bool "Freescale MPC8540 ADS" - select DEFAULT_UIMAGE ---- a/arch/powerpc/platforms/85xx/Makefile -+++ b/arch/powerpc/platforms/85xx/Makefile -@@ -22,6 +22,7 @@ obj-$(CONFIG_P1010_RDB) += p1010rdb.o - obj-$(CONFIG_P1022_DS) += p1022_ds.o - obj-$(CONFIG_P1022_RDK) += p1022_rdk.o - obj-$(CONFIG_P1023_RDB) += p1023_rdb.o -+obj-$(CONFIG_PANDA) += panda.o - obj-$(CONFIG_TWR_P102x) += twr_p102x.o - obj-$(CONFIG_CORENET_GENERIC) += corenet_generic.o - obj-$(CONFIG_FB_FSL_DIU) += t1042rdb_diu.o From patchwork Sun Mar 1 12:12:37 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Hauke Mehrtens X-Patchwork-Id: 1247288 X-Patchwork-Delegate: hauke@hauke-m.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.openwrt.org (client-ip=2607:7c80:54:e::133; helo=bombadil.infradead.org; envelope-from=openwrt-devel-bounces+incoming=patchwork.ozlabs.org@lists.openwrt.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=hauke-m.de Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=lists.infradead.org header.i=@lists.infradead.org header.a=rsa-sha256 header.s=bombadil.20170209 header.b=Y0db4NOg; dkim-atps=neutral Received: from bombadil.infradead.org (bombadil.infradead.org [IPv6:2607:7c80:54:e::133]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 48Vj0t5nWMz9sQt for ; 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Sun, 01 Mar 2020 12:15:53 +0000 Received: from mout-p-103.mailbox.org ([2001:67c:2050::465:103]) by bombadil.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1j8NSw-0006mC-9L for openwrt-devel@lists.openwrt.org; Sun, 01 Mar 2020 12:13:21 +0000 Received: from smtp2.mailbox.org (smtp2.mailbox.org [IPv6:2001:67c:2050:105:465:1:2:0]) (using TLSv1.2 with cipher ECDHE-RSA-CHACHA20-POLY1305 (256/256 bits)) (No client certificate requested) by mout-p-103.mailbox.org (Postfix) with ESMTPS id 48VhxS6mHNzKmgT; Sun, 1 Mar 2020 13:13:00 +0100 (CET) X-Virus-Scanned: amavisd-new at heinlein-support.de Received: from smtp2.mailbox.org ([80.241.60.241]) by spamfilter05.heinlein-hosting.de (spamfilter05.heinlein-hosting.de [80.241.56.123]) (amavisd-new, port 10030) with ESMTP id JIlsHv1RuRXB; Sun, 1 Mar 2020 13:12:51 +0100 (CET) From: Hauke Mehrtens To: openwrt-devel@lists.openwrt.org Date: Sun, 1 Mar 2020 13:12:37 +0100 Message-Id: <20200301121241.5545-9-hauke@hauke-m.de> In-Reply-To: <20200301121241.5545-1-hauke@hauke-m.de> References: <20200301121241.5545-1-hauke@hauke-m.de> MIME-Version: 1.0 X-Spam-Note: CRM114 run bypassed due to message size (278442 bytes) X-Spam-Score: 0.0 (/) X-Spam-Report: SpamAssassin version 3.4.3 on bombadil.infradead.org summary: Content analysis details: (0.0 points) pts rule name description ---- ---------------------- -------------------------------------------------- 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.0 SPF_PASS SPF: sender matches SPF record Subject: [OpenWrt-Devel] [PATCH 08/12] mvebu: Remove kernel 4.14 support X-BeenThere: openwrt-devel@lists.openwrt.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: hauke@hauke-m.de Sender: "openwrt-devel" Errors-To: openwrt-devel-bounces+incoming=patchwork.ozlabs.org@lists.openwrt.org This target was switched to kernel 4.19 more than 6 months ago in commit f342ffd300da ("treewide: kernel: bump some targets to 4.19") and now with kernel 5.4 support being added it gets harder to support kernel 4.14 in addition to kernel 4.19 and 5.4. Signed-off-by: Hauke Mehrtens --- target/linux/mvebu/config-4.14 | 498 --------- target/linux/mvebu/cortexa53/config-4.14 | 113 -- target/linux/mvebu/cortexa72/config-4.14 | 121 --- .../arm/boot/dts/armada-385-linksys-venom.dts | 207 ---- .../marvell/armada-3720-espressobin-emmc.dts | 28 - .../armada-3720-espressobin-v7-emmc.dts | 43 - .../marvell/armada-3720-espressobin-v7.dts | 31 - .../patches-4.14/002-add_powertables.patch | 770 -------------- .../patches-4.14/003-add_switch_nodes.patch | 40 - .../004-add_sata_disk_activity_trigger.patch | 39 - ...5-linksys_hardcode_nand_ecc_settings.patch | 17 - ...Mangle-bootloader-s-kernel-arguments.patch | 201 ---- .../patches-4.14/100-find_active_root.patch | 60 -- .../patches-4.14/102-revert_i2c_delay.patch | 15 - .../103-remove-nand-driver-bug.patch | 13 - ...04-linksys_mamba_disable_keep_config.patch | 10 - .../110-pxa3xxx_revert_irq_thread.patch | 69 -- .../205-armada-385-rd-mtd-partitions.patch | 19 - .../206-ARM-mvebu-385-ap-Add-partitions.patch | 35 - .../210-clearfog_switch_node.patch | 21 - .../220-disable-untested-dsa-boards.patch | 30 - ...-armada-xp-linksys-mamba-broken-idle.patch | 10 - .../300-mvneta-tx-queue-workaround.patch | 35 - ...dicate-failure-to-enter-deeper-sleep.patch | 40 - ...-pci-mvebu-time-out-reset-on-link-up.patch | 60 -- ...2-sfp-display-SFP-module-information.patch | 290 ------ .../403-net-mvneta-convert-to-phylink.patch | 979 ------------------ ...04-net-mvneta-hack-fix-phy_interface.patch | 28 - ...le-MVNETA_CAUSE_PSC_SYNC_CHANGE-inte.patch | 56 - ...ta-add-module-EEPROM-reading-support.patch | 44 - ...ed-phy-remove-fixed_phy_update_state.patch | 80 -- ...eeprom-ethtool-access-into-netdev-co.patch | 181 ---- ...fp-use-netdev-sfp_bus-for-start-stop.patch | 34 - ...w-marvell-10G-phy-support-to-use-SFP.patch | 132 --- .../411-sfp-add-sfp-compatible.patch | 24 - ...da388-clearfog-emmc-on-clearfog-base.patch | 87 -- ...8-clearfog-increase-speed-of-i2c0-to.patch | 42 - ...a388-clearfog-add-SFP-module-support.patch | 81 -- ...rmada388-clearfog-document-MPP-usage.patch | 124 --- ...38x-add-support-for-trimming-the-RTC.patch | 143 --- ...armada38x-reset-after-rtc-power-loss.patch | 73 -- ...ada-385-linksys-Disable-internal-RTC.patch | 28 - .../patches-4.14/450-reprobe_sfp_phy.patch | 94 -- ...-SPI-mode-before-asserting-chip-sele.patch | 70 -- ...s-marvell-armada-37xx-add-UART-clock.patch | 27 - ...-armada-37xx-periph-cosmetic-changes.patch | 78 -- ...-37xx-periph-prepare-cpu-clk-to-be-u.patch | 178 ---- ...-37xx-periph-add-DVFS-support-for-cp.patch | 315 ------ ...req-Add-DVFS-support-for-Armada-37xx.patch | 297 ------ ...l-armada-37xx-add-nodes-allowing-cpu.patch | 48 - ...a-3720-espressobin-wire-up-spi-flash.patch | 56 - ...9-cpufreq-armada-37xx-Fix-clock-leak.patch | 35 - ...-37xx-periph-Fix-switching-CPU-rate-.patch | 92 -- ...-37xx-periph-Fix-wrong-return-value-.patch | 33 - ...-37xx-periph-Remove-unused-var-num_p.patch | 33 - ...l-armada37xx-Add-emmc-sdio-pinctrl-d.patch | 40 - ...l-armada-37xx-Enable-emmc-on-espress.patch | 49 - ...ts-marvell-armada37xx-Add-eth0-alias.patch | 20 - ...da-3720-espressobin-correct-spi-node.patch | 58 -- ...l-armada-3720-espressobin-add-ports-.patch | 26 - ...-device-to-the-same-MAX-payload-size.patch | 138 --- ...ardvark-disable-LOS-state-by-default.patch | 55 - ...ark-allow-to-specify-link-capability.patch | 43 - ...-3720-espressobin-set-max-link-to-ge.patch | 73 -- 64 files changed, 6809 deletions(-) delete mode 100644 target/linux/mvebu/config-4.14 delete mode 100644 target/linux/mvebu/cortexa53/config-4.14 delete mode 100644 target/linux/mvebu/cortexa72/config-4.14 delete mode 100644 target/linux/mvebu/files-4.14/arch/arm/boot/dts/armada-385-linksys-venom.dts delete mode 100644 target/linux/mvebu/files-4.14/arch/arm64/boot/dts/marvell/armada-3720-espressobin-emmc.dts delete mode 100644 target/linux/mvebu/files-4.14/arch/arm64/boot/dts/marvell/armada-3720-espressobin-v7-emmc.dts delete mode 100644 target/linux/mvebu/files-4.14/arch/arm64/boot/dts/marvell/armada-3720-espressobin-v7.dts delete mode 100644 target/linux/mvebu/patches-4.14/002-add_powertables.patch delete mode 100644 target/linux/mvebu/patches-4.14/003-add_switch_nodes.patch delete mode 100644 target/linux/mvebu/patches-4.14/004-add_sata_disk_activity_trigger.patch delete mode 100644 target/linux/mvebu/patches-4.14/005-linksys_hardcode_nand_ecc_settings.patch delete mode 100644 target/linux/mvebu/patches-4.14/006-mvebu-Mangle-bootloader-s-kernel-arguments.patch delete mode 100644 target/linux/mvebu/patches-4.14/100-find_active_root.patch delete mode 100644 target/linux/mvebu/patches-4.14/102-revert_i2c_delay.patch delete mode 100644 target/linux/mvebu/patches-4.14/103-remove-nand-driver-bug.patch delete mode 100644 target/linux/mvebu/patches-4.14/104-linksys_mamba_disable_keep_config.patch delete mode 100644 target/linux/mvebu/patches-4.14/110-pxa3xxx_revert_irq_thread.patch delete mode 100644 target/linux/mvebu/patches-4.14/205-armada-385-rd-mtd-partitions.patch delete mode 100644 target/linux/mvebu/patches-4.14/206-ARM-mvebu-385-ap-Add-partitions.patch delete mode 100644 target/linux/mvebu/patches-4.14/210-clearfog_switch_node.patch delete mode 100644 target/linux/mvebu/patches-4.14/220-disable-untested-dsa-boards.patch delete mode 100644 target/linux/mvebu/patches-4.14/230-armada-xp-linksys-mamba-broken-idle.patch delete mode 100644 target/linux/mvebu/patches-4.14/300-mvneta-tx-queue-workaround.patch delete mode 100644 target/linux/mvebu/patches-4.14/400-cpuidle-mvebu-indicate-failure-to-enter-deeper-sleep.patch delete mode 100644 target/linux/mvebu/patches-4.14/401-pci-mvebu-time-out-reset-on-link-up.patch delete mode 100644 target/linux/mvebu/patches-4.14/402-sfp-display-SFP-module-information.patch delete mode 100644 target/linux/mvebu/patches-4.14/403-net-mvneta-convert-to-phylink.patch delete mode 100644 target/linux/mvebu/patches-4.14/404-net-mvneta-hack-fix-phy_interface.patch delete mode 100644 target/linux/mvebu/patches-4.14/405-net-mvneta-disable-MVNETA_CAUSE_PSC_SYNC_CHANGE-inte.patch delete mode 100644 target/linux/mvebu/patches-4.14/406-net-mvneta-add-module-EEPROM-reading-support.patch delete mode 100644 target/linux/mvebu/patches-4.14/407-phy-fixed-phy-remove-fixed_phy_update_state.patch delete mode 100644 target/linux/mvebu/patches-4.14/408-sfp-move-module-eeprom-ethtool-access-into-netdev-co.patch delete mode 100644 target/linux/mvebu/patches-4.14/409-sfp-use-netdev-sfp_bus-for-start-stop.patch delete mode 100644 target/linux/mvebu/patches-4.14/410-sfp-hack-allow-marvell-10G-phy-support-to-use-SFP.patch delete mode 100644 target/linux/mvebu/patches-4.14/411-sfp-add-sfp-compatible.patch delete mode 100644 target/linux/mvebu/patches-4.14/412-ARM-dts-armada388-clearfog-emmc-on-clearfog-base.patch delete mode 100644 target/linux/mvebu/patches-4.14/413-ARM-dts-armada388-clearfog-increase-speed-of-i2c0-to.patch delete mode 100644 target/linux/mvebu/patches-4.14/414-ARM-dts-armada388-clearfog-add-SFP-module-support.patch delete mode 100644 target/linux/mvebu/patches-4.14/415-ARM-dts-armada388-clearfog-document-MPP-usage.patch delete mode 100644 target/linux/mvebu/patches-4.14/420-rtc-armada38x-add-support-for-trimming-the-RTC.patch delete mode 100644 target/linux/mvebu/patches-4.14/421-rtc-armada38x-reset-after-rtc-power-loss.patch delete mode 100644 target/linux/mvebu/patches-4.14/423-ARM-dts-armada-385-linksys-Disable-internal-RTC.patch delete mode 100644 target/linux/mvebu/patches-4.14/450-reprobe_sfp_phy.patch delete mode 100644 target/linux/mvebu/patches-4.14/501-spi-a3700-Change-SPI-mode-before-asserting-chip-sele.patch delete mode 100644 target/linux/mvebu/patches-4.14/502-arm64-dts-marvell-armada-37xx-add-UART-clock.patch delete mode 100644 target/linux/mvebu/patches-4.14/503-clk-mvebu-armada-37xx-periph-cosmetic-changes.patch delete mode 100644 target/linux/mvebu/patches-4.14/504-clk-mvebu-armada-37xx-periph-prepare-cpu-clk-to-be-u.patch delete mode 100644 target/linux/mvebu/patches-4.14/505-clk-mvebu-armada-37xx-periph-add-DVFS-support-for-cp.patch delete mode 100644 target/linux/mvebu/patches-4.14/506-cpufreq-Add-DVFS-support-for-Armada-37xx.patch delete mode 100644 target/linux/mvebu/patches-4.14/507-arm64-dts-marvell-armada-37xx-add-nodes-allowing-cpu.patch delete mode 100644 target/linux/mvebu/patches-4.14/508-arm64-dts-armada-3720-espressobin-wire-up-spi-flash.patch delete mode 100644 target/linux/mvebu/patches-4.14/509-cpufreq-armada-37xx-Fix-clock-leak.patch delete mode 100644 target/linux/mvebu/patches-4.14/510-clk-mvebu-armada-37xx-periph-Fix-switching-CPU-rate-.patch delete mode 100644 target/linux/mvebu/patches-4.14/511-clk-mvebu-armada-37xx-periph-Fix-wrong-return-value-.patch delete mode 100644 target/linux/mvebu/patches-4.14/512-clk-mvebu-armada-37xx-periph-Remove-unused-var-num_p.patch delete mode 100644 target/linux/mvebu/patches-4.14/513-arm64-dts-marvell-armada37xx-Add-emmc-sdio-pinctrl-d.patch delete mode 100644 target/linux/mvebu/patches-4.14/514-arm64-dts-marvell-armada-37xx-Enable-emmc-on-espress.patch delete mode 100644 target/linux/mvebu/patches-4.14/520-arm64-dts-marvell-armada37xx-Add-eth0-alias.patch delete mode 100644 target/linux/mvebu/patches-4.14/521-arm64-dts-armada-3720-espressobin-correct-spi-node.patch delete mode 100644 target/linux/mvebu/patches-4.14/522-arm64-dts-marvell-armada-3720-espressobin-add-ports-.patch delete mode 100644 target/linux/mvebu/patches-4.14/524-PCI-aardvark-set-host-and-device-to-the-same-MAX-payload-size.patch delete mode 100644 target/linux/mvebu/patches-4.14/526-PCI-aardvark-disable-LOS-state-by-default.patch delete mode 100644 target/linux/mvebu/patches-4.14/527-PCI-aardvark-allow-to-specify-link-capability.patch delete mode 100644 target/linux/mvebu/patches-4.14/528-arm64-dts-armada-3720-espressobin-set-max-link-to-ge.patch diff --git a/target/linux/mvebu/config-4.14 b/target/linux/mvebu/config-4.14 deleted file mode 100644 index 7a0caeeb6120..000000000000 --- a/target/linux/mvebu/config-4.14 +++ /dev/null @@ -1,498 +0,0 @@ -CONFIG_AHCI_MVEBU=y -CONFIG_ALIGNMENT_TRAP=y -CONFIG_ARCH_CLOCKSOURCE_DATA=y -CONFIG_ARCH_HAS_DEBUG_VIRTUAL=y -CONFIG_ARCH_HAS_ELF_RANDOMIZE=y -CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y -CONFIG_ARCH_HAS_SET_MEMORY=y -CONFIG_ARCH_HAS_SG_CHAIN=y -CONFIG_ARCH_HAS_STRICT_KERNEL_RWX=y -CONFIG_ARCH_HAS_STRICT_MODULE_RWX=y -CONFIG_ARCH_HAS_TICK_BROADCAST=y -CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y -CONFIG_ARCH_HIBERNATION_POSSIBLE=y -CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y -CONFIG_ARCH_MULTIPLATFORM=y -# CONFIG_ARCH_MULTI_CPU_AUTO is not set -CONFIG_ARCH_MULTI_V6_V7=y -CONFIG_ARCH_MULTI_V7=y -CONFIG_ARCH_MVEBU=y -CONFIG_ARCH_NR_GPIO=0 -CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y -CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y -# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set -# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set -CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y -CONFIG_ARCH_SUPPORTS_BIG_ENDIAN=y -CONFIG_ARCH_SUPPORTS_UPROBES=y -CONFIG_ARCH_SUSPEND_POSSIBLE=y -CONFIG_ARCH_USE_BUILTIN_BSWAP=y -CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y -CONFIG_ARCH_WANT_GENERAL_HUGETLB=y -CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y -CONFIG_ARM=y -CONFIG_ARMADA_370_CLK=y -CONFIG_ARMADA_370_XP_IRQ=y -CONFIG_ARMADA_370_XP_TIMER=y -CONFIG_ARMADA_38X_CLK=y -CONFIG_ARMADA_THERMAL=y -CONFIG_ARMADA_XP_CLK=y -CONFIG_ARM_APPENDED_DTB=y -# CONFIG_ARM_ARMADA_37XX_CPUFREQ is not set -CONFIG_ARM_ATAG_DTB_COMPAT=y -# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set -# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER is not set -CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE=y -CONFIG_ARM_CPU_SUSPEND=y -CONFIG_ARM_CRYPTO=y -CONFIG_ARM_ERRATA_720789=y -CONFIG_ARM_ERRATA_764369=y -CONFIG_ARM_GIC=y -CONFIG_ARM_GLOBAL_TIMER=y -CONFIG_ARM_HAS_SG_CHAIN=y -CONFIG_ARM_HEAVY_MB=y -CONFIG_ARM_L1_CACHE_SHIFT=6 -CONFIG_ARM_L1_CACHE_SHIFT_6=y -# CONFIG_ARM_LPAE is not set -CONFIG_ARM_MVEBU_V7_CPUIDLE=y -CONFIG_ARM_PATCH_IDIV=y -CONFIG_ARM_PATCH_PHYS_VIRT=y -CONFIG_ARM_THUMB=y -# CONFIG_ARM_THUMBEE is not set -CONFIG_ARM_UNWIND=y -CONFIG_ARM_VIRT_EXT=y -CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH=y -CONFIG_ATA=y -CONFIG_ATAGS=y -CONFIG_AUTO_ZRELADDR=y -CONFIG_BLK_DEV_LOOP=y -CONFIG_BLK_DEV_SD=y -CONFIG_BLK_MQ_PCI=y -CONFIG_BLK_SCSI_REQUEST=y -CONFIG_BOUNCE=y -# CONFIG_CACHE_FEROCEON_L2 is not set -CONFIG_CACHE_L2X0=y -CONFIG_CLKDEV_LOOKUP=y -CONFIG_CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK=y -CONFIG_CLKSRC_MMIO=y -CONFIG_CLONE_BACKWARDS=y -CONFIG_COMMON_CLK=y -CONFIG_CPUFREQ_DT=y -CONFIG_CPUFREQ_DT_PLATDEV=y -CONFIG_CPU_32v6K=y -CONFIG_CPU_32v7=y -CONFIG_CPU_ABRT_EV7=y -# CONFIG_CPU_BIG_ENDIAN is not set -# CONFIG_CPU_BPREDICT_DISABLE is not set -CONFIG_CPU_CACHE_V7=y -CONFIG_CPU_CACHE_VIPT=y -CONFIG_CPU_COPY_V6=y -CONFIG_CPU_CP15=y -CONFIG_CPU_CP15_MMU=y -CONFIG_CPU_FREQ=y -CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y -# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set -CONFIG_CPU_FREQ_GOV_ATTR_SET=y -CONFIG_CPU_FREQ_GOV_COMMON=y -# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set -CONFIG_CPU_FREQ_GOV_ONDEMAND=y -CONFIG_CPU_FREQ_GOV_PERFORMANCE=y -# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set -# CONFIG_CPU_FREQ_GOV_USERSPACE is not set -CONFIG_CPU_FREQ_STAT=y -CONFIG_CPU_HAS_ASID=y -# CONFIG_CPU_HOTPLUG_STATE_CONTROL is not set -# CONFIG_CPU_ICACHE_DISABLE is not set -CONFIG_CPU_IDLE=y -CONFIG_CPU_IDLE_GOV_LADDER=y -CONFIG_CPU_PABRT_V7=y -CONFIG_CPU_PJ4B=y -CONFIG_CPU_PM=y -CONFIG_CPU_RMAP=y -CONFIG_CPU_SPECTRE=y -CONFIG_CPU_THERMAL=y -CONFIG_CPU_THUMB_CAPABLE=y -CONFIG_CPU_TLB_V7=y -CONFIG_CPU_V7=y -CONFIG_CRC16=y -CONFIG_CRYPTO_ACOMP2=y -CONFIG_CRYPTO_AEAD=y -CONFIG_CRYPTO_AEAD2=y -CONFIG_CRYPTO_AES_ARM=y -CONFIG_CRYPTO_AES_ARM_BS=y -# CONFIG_CRYPTO_AES_ARM_CE is not set -# CONFIG_CRYPTO_CHACHA20_NEON is not set -CONFIG_CRYPTO_CRC32=y -CONFIG_CRYPTO_CRC32C=y -# CONFIG_CRYPTO_CRC32_ARM_CE is not set -CONFIG_CRYPTO_CRYPTD=y -CONFIG_CRYPTO_DEFLATE=y -CONFIG_CRYPTO_DES=y -CONFIG_CRYPTO_DEV_MARVELL_CESA=y -# CONFIG_CRYPTO_GHASH_ARM_CE is not set -CONFIG_CRYPTO_HASH=y -CONFIG_CRYPTO_HASH2=y -CONFIG_CRYPTO_HW=y -CONFIG_CRYPTO_LZO=y -CONFIG_CRYPTO_MANAGER=y -CONFIG_CRYPTO_MANAGER2=y -CONFIG_CRYPTO_NULL2=y -CONFIG_CRYPTO_RNG2=y -CONFIG_CRYPTO_SHA1=y -CONFIG_CRYPTO_SHA1_ARM=y -# CONFIG_CRYPTO_SHA1_ARM_CE is not set -CONFIG_CRYPTO_SHA1_ARM_NEON=y -CONFIG_CRYPTO_SHA256_ARM=y -# CONFIG_CRYPTO_SHA2_ARM_CE is not set -CONFIG_CRYPTO_SHA512_ARM=y -CONFIG_CRYPTO_SIMD=y -CONFIG_CRYPTO_WORKQUEUE=y -CONFIG_DCACHE_WORD_ACCESS=y -CONFIG_DEBUG_ALIGN_RODATA=y -CONFIG_DEBUG_INFO=y -CONFIG_DEBUG_LL=y -CONFIG_DEBUG_LL_INCLUDE="debug/8250.S" -CONFIG_DEBUG_MVEBU_UART0=y -# CONFIG_DEBUG_MVEBU_UART0_ALTERNATE is not set -# CONFIG_DEBUG_MVEBU_UART1_ALTERNATE is not set -CONFIG_DEBUG_UART_8250=y -# CONFIG_DEBUG_UART_8250_FLOW_CONTROL is not set -CONFIG_DEBUG_UART_8250_SHIFT=2 -# CONFIG_DEBUG_UART_8250_WORD is not set -CONFIG_DEBUG_UART_PHYS=0xd0012000 -CONFIG_DEBUG_UART_VIRT=0xfec12000 -CONFIG_DEBUG_UNCOMPRESS=y -CONFIG_DEBUG_USER=y -CONFIG_DMADEVICES=y -CONFIG_DMA_ENGINE=y -CONFIG_DMA_ENGINE_RAID=y -CONFIG_DMA_OF=y -CONFIG_DTC=y -CONFIG_EARLY_PRINTK=y -CONFIG_EDAC_ATOMIC_SCRUB=y -CONFIG_EDAC_SUPPORT=y -CONFIG_EXT4_FS=y -CONFIG_EXTCON=y -# CONFIG_F2FS_CHECK_FS is not set -CONFIG_F2FS_FS=y -# CONFIG_F2FS_FS_SECURITY is not set -CONFIG_F2FS_FS_XATTR=y -CONFIG_F2FS_STAT_FS=y -CONFIG_FIXED_PHY=y -CONFIG_FIX_EARLYCON_MEM=y -CONFIG_FS_MBCACHE=y -CONFIG_GENERIC_ALLOCATOR=y -CONFIG_GENERIC_ARCH_TOPOLOGY=y -CONFIG_GENERIC_BUG=y -CONFIG_GENERIC_CLOCKEVENTS=y -CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y -CONFIG_GENERIC_CPU_AUTOPROBE=y -CONFIG_GENERIC_EARLY_IOREMAP=y -CONFIG_GENERIC_IDLE_POLL_SETUP=y -CONFIG_GENERIC_IO=y -CONFIG_GENERIC_IRQ_CHIP=y -CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y -CONFIG_GENERIC_IRQ_SHOW=y -CONFIG_GENERIC_IRQ_SHOW_LEVEL=y -CONFIG_GENERIC_MSI_IRQ=y -CONFIG_GENERIC_MSI_IRQ_DOMAIN=y -CONFIG_GENERIC_PCI_IOMAP=y -CONFIG_GENERIC_PHY=y -CONFIG_GENERIC_SCHED_CLOCK=y -CONFIG_GENERIC_SMP_IDLE_THREAD=y -CONFIG_GENERIC_STRNCPY_FROM_USER=y -CONFIG_GENERIC_STRNLEN_USER=y -CONFIG_GLOB=y -CONFIG_GPIOLIB=y -CONFIG_GPIOLIB_IRQCHIP=y -CONFIG_GPIO_GENERIC=y -CONFIG_GPIO_GENERIC_PLATFORM=y -CONFIG_GPIO_MVEBU=y -CONFIG_GPIO_PCA953X=y -CONFIG_GPIO_PCA953X_IRQ=y -CONFIG_GPIO_SYSFS=y -# CONFIG_GRO_CELLS is not set -CONFIG_HANDLE_DOMAIN_IRQ=y -CONFIG_HARDEN_BRANCH_PREDICTOR=y -CONFIG_HARDIRQS_SW_RESEND=y -CONFIG_HAS_DMA=y -CONFIG_HAS_IOMEM=y -CONFIG_HAS_IOPORT_MAP=y -# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set -CONFIG_HAVE_ARCH_AUDITSYSCALL=y -CONFIG_HAVE_ARCH_BITREVERSE=y -CONFIG_HAVE_ARCH_JUMP_LABEL=y -CONFIG_HAVE_ARCH_KGDB=y -CONFIG_HAVE_ARCH_PFN_VALID=y -CONFIG_HAVE_ARCH_SECCOMP_FILTER=y -CONFIG_HAVE_ARCH_TRACEHOOK=y -CONFIG_HAVE_ARM_SCU=y -CONFIG_HAVE_ARM_SMCCC=y -CONFIG_HAVE_ARM_TWD=y -# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set -CONFIG_HAVE_CC_STACKPROTECTOR=y -CONFIG_HAVE_CLK=y -CONFIG_HAVE_CLK_PREPARE=y -CONFIG_HAVE_CONTEXT_TRACKING=y -CONFIG_HAVE_C_RECORDMCOUNT=y -CONFIG_HAVE_DEBUG_KMEMLEAK=y -CONFIG_HAVE_DMA_API_DEBUG=y -CONFIG_HAVE_DMA_CONTIGUOUS=y -CONFIG_HAVE_DYNAMIC_FTRACE=y -CONFIG_HAVE_DYNAMIC_FTRACE_WITH_REGS=y -CONFIG_HAVE_EBPF_JIT=y -CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y -CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y -CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y -CONFIG_HAVE_FUNCTION_TRACER=y -CONFIG_HAVE_GENERIC_DMA_COHERENT=y -CONFIG_HAVE_IDE=y -CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y -CONFIG_HAVE_MEMBLOCK=y -CONFIG_HAVE_MOD_ARCH_SPECIFIC=y -CONFIG_HAVE_NET_DSA=y -CONFIG_HAVE_OPROFILE=y -CONFIG_HAVE_OPTPROBES=y -CONFIG_HAVE_PERF_EVENTS=y -CONFIG_HAVE_PERF_REGS=y -CONFIG_HAVE_PERF_USER_STACK_DUMP=y -CONFIG_HAVE_PROC_CPU=y -CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y -CONFIG_HAVE_SMP=y -CONFIG_HAVE_SYSCALL_TRACEPOINTS=y -CONFIG_HAVE_UID16=y -CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y -CONFIG_HIGHMEM=y -# CONFIG_HIGHPTE is not set -CONFIG_HOTPLUG_CPU=y -CONFIG_HWBM=y -CONFIG_HWMON=y -CONFIG_HW_RANDOM=y -# CONFIG_HW_RANDOM_OMAP is not set -CONFIG_HZ_FIXED=0 -CONFIG_HZ_PERIODIC=y -CONFIG_I2C=y -CONFIG_I2C_BOARDINFO=y -CONFIG_I2C_CHARDEV=y -CONFIG_I2C_MV64XXX=y -# CONFIG_I2C_PXA is not set -CONFIG_INITRAMFS_SOURCE="" -CONFIG_IOMMU_HELPER=y -CONFIG_IRQCHIP=y -CONFIG_IRQ_DOMAIN=y -CONFIG_IRQ_DOMAIN_DEBUG=y -CONFIG_IRQ_DOMAIN_HIERARCHY=y -CONFIG_IRQ_FORCED_THREADING=y -CONFIG_IRQ_WORK=y -# CONFIG_IWMMXT is not set -CONFIG_JBD2=y -CONFIG_LEDS_GPIO=y -CONFIG_LEDS_PCA963X=y -CONFIG_LEDS_TLC591XX=y -CONFIG_LEDS_TRIGGER_DISK=y -CONFIG_LIBFDT=y -CONFIG_LOCK_SPIN_ON_OWNER=y -CONFIG_LZO_COMPRESS=y -CONFIG_LZO_DECOMPRESS=y -CONFIG_MACH_ARMADA_370=y -# CONFIG_MACH_ARMADA_375 is not set -CONFIG_MACH_ARMADA_38X=y -# CONFIG_MACH_ARMADA_39X is not set -CONFIG_MACH_ARMADA_XP=y -# CONFIG_MACH_DOVE is not set -CONFIG_MACH_MVEBU_ANY=y -CONFIG_MACH_MVEBU_V7=y -CONFIG_MAGIC_SYSRQ=y -CONFIG_MANGLE_BOOTARGS=y -CONFIG_MARVELL_PHY=y -CONFIG_MDIO_BUS=y -CONFIG_MDIO_DEVICE=y -CONFIG_MDIO_I2C=y -CONFIG_MEMORY=y -CONFIG_MIGHT_HAVE_CACHE_L2X0=y -CONFIG_MIGHT_HAVE_PCI=y -CONFIG_MIGRATION=y -CONFIG_MMC=y -CONFIG_MMC_BLOCK=y -CONFIG_MMC_MVSDIO=y -CONFIG_MMC_SDHCI=y -# CONFIG_MMC_SDHCI_PCI is not set -CONFIG_MMC_SDHCI_PLTFM=y -CONFIG_MMC_SDHCI_PXAV3=y -# CONFIG_MMC_TIFM_SD is not set -CONFIG_MODULES_USE_ELF_REL=y -CONFIG_MTD_CFI_STAA=y -CONFIG_MTD_M25P80=y -CONFIG_MTD_NAND=y -CONFIG_MTD_NAND_ECC=y -CONFIG_MTD_NAND_PXA3xx=y -CONFIG_MTD_SPI_NOR=y -CONFIG_MTD_SPLIT_FIRMWARE=y -CONFIG_MTD_UBI=y -CONFIG_MTD_UBI_BEB_LIMIT=20 -CONFIG_MTD_UBI_BLOCK=y -# CONFIG_MTD_UBI_FASTMAP is not set -# CONFIG_MTD_UBI_GLUEBI is not set -CONFIG_MTD_UBI_WL_THRESHOLD=4096 -CONFIG_MULTI_IRQ_HANDLER=y -CONFIG_MUTEX_SPIN_ON_OWNER=y -CONFIG_MVEBU_CLK_COMMON=y -CONFIG_MVEBU_CLK_COREDIV=y -CONFIG_MVEBU_CLK_CPU=y -CONFIG_MVEBU_DEVBUS=y -CONFIG_MVEBU_MBUS=y -CONFIG_MVMDIO=y -CONFIG_MVNETA=y -CONFIG_MVNETA_BM=y -CONFIG_MVNETA_BM_ENABLE=y -CONFIG_MVPP2=y -CONFIG_MVSW61XX_PHY=y -CONFIG_MV_XOR=y -CONFIG_NEED_DMA_MAP_STATE=y -CONFIG_NEON=y -CONFIG_NET_DSA=y -CONFIG_NET_DSA_MV88E6XXX=y -CONFIG_NET_DSA_MV88E6XXX_GLOBAL2=y -CONFIG_NET_DSA_TAG_DSA=y -CONFIG_NET_DSA_TAG_EDSA=y -CONFIG_NET_FLOW_LIMIT=y -CONFIG_NET_SWITCHDEV=y -CONFIG_NLS=y -CONFIG_NOP_USB_XCEIV=y -CONFIG_NO_BOOTMEM=y -CONFIG_NR_CPUS=4 -CONFIG_OF=y -CONFIG_OF_ADDRESS=y -CONFIG_OF_ADDRESS_PCI=y -CONFIG_OF_EARLY_FLATTREE=y -CONFIG_OF_FLATTREE=y -CONFIG_OF_GPIO=y -CONFIG_OF_IRQ=y -CONFIG_OF_MDIO=y -CONFIG_OF_NET=y -CONFIG_OF_PCI=y -CONFIG_OF_PCI_IRQ=y -CONFIG_OF_RESERVED_MEM=y -CONFIG_OLD_SIGACTION=y -CONFIG_OLD_SIGSUSPEND3=y -CONFIG_ORION_WATCHDOG=y -CONFIG_OUTER_CACHE=y -CONFIG_OUTER_CACHE_SYNC=y -CONFIG_PADATA=y -CONFIG_PAGE_OFFSET=0xC0000000 -CONFIG_PCI=y -CONFIG_PCI_DOMAINS=y -CONFIG_PCI_DOMAINS_GENERIC=y -CONFIG_PCI_MSI=y -CONFIG_PCI_MSI_IRQ_DOMAIN=y -CONFIG_PCI_MVEBU=y -CONFIG_PERF_USE_VMALLOC=y -CONFIG_PGTABLE_LEVELS=2 -CONFIG_PHYLIB=y -CONFIG_PHYLINK=y -# CONFIG_PHY_MVEBU_CP110_COMPHY is not set -CONFIG_PINCTRL=y -CONFIG_PINCTRL_ARMADA_370=y -CONFIG_PINCTRL_ARMADA_38X=y -CONFIG_PINCTRL_ARMADA_XP=y -CONFIG_PINCTRL_MVEBU=y -# CONFIG_PINCTRL_SINGLE is not set -CONFIG_PJ4B_ERRATA_4742=y -# CONFIG_PL310_ERRATA_588369 is not set -# CONFIG_PL310_ERRATA_727915 is not set -CONFIG_PL310_ERRATA_753970=y -# CONFIG_PL310_ERRATA_769419 is not set -CONFIG_PLAT_ORION=y -CONFIG_PM_OPP=y -CONFIG_PRINTK_SAFE_LOG_BUF_SHIFT=11 -CONFIG_PWM=y -CONFIG_PWM_SYSFS=y -CONFIG_RATIONAL=y -CONFIG_RCU_NEED_SEGCBLIST=y -CONFIG_RCU_STALL_COMMON=y -CONFIG_REGMAP=y -CONFIG_REGMAP_I2C=y -CONFIG_REGMAP_MMIO=y -CONFIG_REGMAP_SPI=y -CONFIG_REGULATOR=y -CONFIG_REGULATOR_FIXED_VOLTAGE=y -CONFIG_RFS_ACCEL=y -CONFIG_RPS=y -CONFIG_RTC_CLASS=y -CONFIG_RTC_DRV_ARMADA38X=y -CONFIG_RTC_DRV_MV=y -CONFIG_RTC_I2C_AND_SPI=y -CONFIG_RTC_MC146818_LIB=y -CONFIG_RWSEM_SPIN_ON_OWNER=y -CONFIG_RWSEM_XCHGADD_ALGORITHM=y -CONFIG_SATA_AHCI_PLATFORM=y -CONFIG_SATA_MV=y -CONFIG_SATA_PMP=y -# CONFIG_SCHED_INFO is not set -CONFIG_SCSI=y -CONFIG_SENSORS_PWM_FAN=y -CONFIG_SENSORS_TMP421=y -CONFIG_SERIAL_8250_DW=y -CONFIG_SERIAL_8250_FSL=y -CONFIG_SERIAL_MVEBU_CONSOLE=y -CONFIG_SERIAL_MVEBU_UART=y -CONFIG_SFP=y -CONFIG_SG_POOL=y -CONFIG_SMP=y -CONFIG_SMP_ON_UP=y -CONFIG_SOC_BUS=y -CONFIG_SPARSE_IRQ=y -CONFIG_SPI=y -# CONFIG_SPI_ARMADA_3700 is not set -CONFIG_SPI_MASTER=y -CONFIG_SPI_ORION=y -CONFIG_SRAM=y -CONFIG_SRAM_EXEC=y -CONFIG_SRCU=y -CONFIG_SWCONFIG=y -CONFIG_SWIOTLB=y -CONFIG_SWPHY=y -CONFIG_SWP_EMULATE=y -CONFIG_SYS_SUPPORTS_APM_EMULATION=y -CONFIG_THERMAL=y -CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y -CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0 -CONFIG_THERMAL_GOV_STEP_WISE=y -CONFIG_THERMAL_HWMON=y -CONFIG_THERMAL_OF=y -# CONFIG_THUMB2_KERNEL is not set -CONFIG_TICK_CPU_ACCOUNTING=y -CONFIG_TIMER_OF=y -CONFIG_TIMER_PROBE=y -CONFIG_TREE_RCU=y -CONFIG_TREE_SRCU=y -CONFIG_UBIFS_FS=y -# CONFIG_UBIFS_FS_ADVANCED_COMPR is not set -CONFIG_UBIFS_FS_LZO=y -CONFIG_UBIFS_FS_ZLIB=y -CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" -CONFIG_USB=y -CONFIG_USB_COMMON=y -CONFIG_USB_EHCI_HCD=y -CONFIG_USB_EHCI_HCD_ORION=y -CONFIG_USB_EHCI_HCD_PLATFORM=y -CONFIG_USB_LEDS_TRIGGER_USBPORT=y -CONFIG_USB_PHY=y -CONFIG_USB_STORAGE=y -CONFIG_USB_SUPPORT=y -CONFIG_USB_XHCI_HCD=y -CONFIG_USB_XHCI_MVEBU=y -CONFIG_USB_XHCI_PCI=y -CONFIG_USB_XHCI_PLATFORM=y -CONFIG_USE_OF=y -CONFIG_VECTORS_BASE=0xffff0000 -CONFIG_VFP=y -CONFIG_VFPv3=y -CONFIG_WATCHDOG_CORE=y -CONFIG_XPS=y -CONFIG_XZ_DEC_ARM=y -CONFIG_XZ_DEC_BCJ=y -CONFIG_ZBOOT_ROM_BSS=0x0 -CONFIG_ZBOOT_ROM_TEXT=0x0 -CONFIG_ZLIB_DEFLATE=y -CONFIG_ZLIB_INFLATE=y diff --git a/target/linux/mvebu/cortexa53/config-4.14 b/target/linux/mvebu/cortexa53/config-4.14 deleted file mode 100644 index df5f6f341bf0..000000000000 --- a/target/linux/mvebu/cortexa53/config-4.14 +++ /dev/null @@ -1,113 +0,0 @@ -CONFIG_64BIT=y -# CONFIG_ACPI is not set -CONFIG_ARCH_DMA_ADDR_T_64BIT=y -CONFIG_ARCH_HAS_CACHE_LINE_SIZE=y -CONFIG_ARCH_HAS_FORTIFY_SOURCE=y -CONFIG_ARCH_HAS_HOLES_MEMORYMODEL=y -CONFIG_ARCH_HAS_KCOV=y -CONFIG_ARCH_MMAP_RND_BITS=18 -CONFIG_ARCH_MMAP_RND_BITS_MAX=24 -CONFIG_ARCH_MMAP_RND_BITS_MIN=18 -CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11 -# CONFIG_ARCH_OPTIONAL_KERNEL_RWX is not set -# CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT is not set -CONFIG_ARCH_PHYS_ADDR_T_64BIT=y -CONFIG_ARCH_PROC_KCORE_TEXT=y -CONFIG_ARCH_SELECT_MEMORY_MODEL=y -CONFIG_ARCH_SPARSEMEM_DEFAULT=y -CONFIG_ARCH_SPARSEMEM_ENABLE=y -CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y -CONFIG_ARCH_SUPPORTS_MEMORY_FAILURE=y -CONFIG_ARCH_SUPPORTS_NUMA_BALANCING=y -CONFIG_ARCH_WANT_COMPAT_IPC_PARSE_VERSION=y -CONFIG_ARCH_WANT_FRAME_POINTERS=y -CONFIG_ARCH_WANT_HUGE_PMD_SHARE=y -CONFIG_ARM64=y -# CONFIG_ARM64_16K_PAGES is not set -CONFIG_ARM64_4K_PAGES=y -# CONFIG_ARM64_64K_PAGES is not set -CONFIG_ARM64_CONT_SHIFT=4 -# CONFIG_ARM64_CRYPTO is not set -# CONFIG_ARM64_HW_AFDBM is not set -# CONFIG_ARM64_LSE_ATOMICS is not set -CONFIG_ARM64_PAGE_SHIFT=12 -# CONFIG_ARM64_PAN is not set -# CONFIG_ARM64_PMEM is not set -# CONFIG_ARM64_PTDUMP_CORE is not set -# CONFIG_ARM64_PTDUMP_DEBUGFS is not set -# CONFIG_ARM64_RANDOMIZE_TEXT_OFFSET is not set -CONFIG_ARM64_SSBD=y -# CONFIG_ARM64_UAO is not set -CONFIG_ARM64_VA_BITS=39 -CONFIG_ARM64_VA_BITS_39=y -# CONFIG_ARM64_VA_BITS_48 is not set -# CONFIG_ARM64_VHE is not set -CONFIG_ARMADA_37XX_CLK=y -CONFIG_ARMADA_AP806_SYSCON=y -CONFIG_ARMADA_CP110_SYSCON=y -CONFIG_ARM_AMBA=y -CONFIG_ARM_ARCH_TIMER=y -CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y -CONFIG_ARM_ARMADA_37XX_CPUFREQ=y -CONFIG_ARM_GIC_V2M=y -CONFIG_ARM_GIC_V3=y -CONFIG_ARM_GIC_V3_ITS=y -# CONFIG_ARM_PL172_MPMC is not set -CONFIG_ARM_PSCI_FW=y -# CONFIG_ARM_SP805_WATCHDOG is not set -CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y -# CONFIG_DEBUG_ALIGN_RODATA is not set -CONFIG_FRAME_POINTER=y -CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y -CONFIG_GENERIC_CSUM=y -CONFIG_GENERIC_IRQ_MIGRATION=y -CONFIG_GENERIC_PINCONF=y -CONFIG_GENERIC_TIME_VSYSCALL=y -CONFIG_HAVE_ALIGNED_STRUCT_PAGE=y -CONFIG_HAVE_ARCH_HUGE_VMAP=y -CONFIG_HAVE_ARCH_KASAN=y -CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE=y -CONFIG_HAVE_ARCH_VMAP_STACK=y -CONFIG_HAVE_CMPXCHG_DOUBLE=y -CONFIG_HAVE_CMPXCHG_LOCAL=y -CONFIG_HAVE_DEBUG_BUGVERBOSE=y -CONFIG_HAVE_GENERIC_GUP=y -CONFIG_HAVE_MEMORY_PRESENT=y -CONFIG_HAVE_PATA_PLATFORM=y -CONFIG_HAVE_RCU_TABLE_FREE=y -CONFIG_HOLES_IN_ZONE=y -# CONFIG_HUGETLBFS is not set -CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000 -CONFIG_MFD_SYSCON=y -CONFIG_MMC_SDHCI_XENON=y -CONFIG_MODULES_USE_ELF_RELA=y -CONFIG_MVEBU_GICP=y -CONFIG_MVEBU_ICU=y -CONFIG_MVEBU_ODMI=y -CONFIG_MVEBU_PIC=y -CONFIG_NEED_SG_DMA_LENGTH=y -# CONFIG_NUMA is not set -CONFIG_PARTITION_PERCPU=y -CONFIG_PCI_AARDVARK=y -CONFIG_PCI_BUS_ADDR_T_64BIT=y -CONFIG_PGTABLE_LEVELS=3 -CONFIG_PHYS_ADDR_T_64BIT=y -CONFIG_PINCTRL_ARMADA_37XX=y -CONFIG_PINCTRL_ARMADA_AP806=y -CONFIG_PINCTRL_ARMADA_CP110=y -CONFIG_POWER_RESET=y -CONFIG_POWER_SUPPLY=y -# CONFIG_RANDOMIZE_BASE is not set -CONFIG_REGULATOR_GPIO=y -# CONFIG_SERIAL_AMBA_PL011 is not set -CONFIG_SPARSEMEM=y -CONFIG_SPARSEMEM_EXTREME=y -CONFIG_SPARSEMEM_MANUAL=y -CONFIG_SPARSEMEM_VMEMMAP=y -CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y -CONFIG_SPI_ARMADA_3700=y -CONFIG_SYSCTL_EXCEPTION_TRACE=y -CONFIG_SYS_SUPPORTS_HUGETLBFS=y -CONFIG_THREAD_INFO_IN_TASK=y -CONFIG_UNMAP_KERNEL_AT_EL0=y -CONFIG_VMAP_STACK=y diff --git a/target/linux/mvebu/cortexa72/config-4.14 b/target/linux/mvebu/cortexa72/config-4.14 deleted file mode 100644 index f9bcefc4c511..000000000000 --- a/target/linux/mvebu/cortexa72/config-4.14 +++ /dev/null @@ -1,121 +0,0 @@ -CONFIG_64BIT=y -# CONFIG_ACPI is not set -CONFIG_ARCH_DMA_ADDR_T_64BIT=y -CONFIG_ARCH_HAS_CACHE_LINE_SIZE=y -CONFIG_ARCH_HAS_FORTIFY_SOURCE=y -CONFIG_ARCH_HAS_HOLES_MEMORYMODEL=y -CONFIG_ARCH_HAS_KCOV=y -CONFIG_ARCH_MMAP_RND_BITS=18 -CONFIG_ARCH_MMAP_RND_BITS_MAX=24 -CONFIG_ARCH_MMAP_RND_BITS_MIN=18 -CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11 -# CONFIG_ARCH_OPTIONAL_KERNEL_RWX is not set -# CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT is not set -CONFIG_ARCH_PHYS_ADDR_T_64BIT=y -CONFIG_ARCH_PROC_KCORE_TEXT=y -CONFIG_ARCH_SELECT_MEMORY_MODEL=y -CONFIG_ARCH_SPARSEMEM_DEFAULT=y -CONFIG_ARCH_SPARSEMEM_ENABLE=y -CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y -CONFIG_ARCH_SUPPORTS_MEMORY_FAILURE=y -CONFIG_ARCH_SUPPORTS_NUMA_BALANCING=y -CONFIG_ARCH_WANT_COMPAT_IPC_PARSE_VERSION=y -CONFIG_ARCH_WANT_FRAME_POINTERS=y -CONFIG_ARCH_WANT_HUGE_PMD_SHARE=y -CONFIG_ARM64=y -# CONFIG_ARM64_16K_PAGES is not set -CONFIG_ARM64_4K_PAGES=y -# CONFIG_ARM64_64K_PAGES is not set -CONFIG_ARM64_CONT_SHIFT=4 -# CONFIG_ARM64_CRYPTO is not set -# CONFIG_ARM64_HW_AFDBM is not set -# CONFIG_ARM64_LSE_ATOMICS is not set -CONFIG_ARM64_PAGE_SHIFT=12 -# CONFIG_ARM64_PAN is not set -# CONFIG_ARM64_PMEM is not set -# CONFIG_ARM64_PTDUMP_CORE is not set -# CONFIG_ARM64_PTDUMP_DEBUGFS is not set -# CONFIG_ARM64_RANDOMIZE_TEXT_OFFSET is not set -CONFIG_ARM64_SSBD=y -# CONFIG_ARM64_UAO is not set -CONFIG_ARM64_VA_BITS=39 -CONFIG_ARM64_VA_BITS_39=y -# CONFIG_ARM64_VA_BITS_48 is not set -# CONFIG_ARM64_VHE is not set -CONFIG_ARMADA_37XX_CLK=y -CONFIG_ARMADA_AP806_SYSCON=y -CONFIG_ARMADA_CP110_SYSCON=y -CONFIG_ARM_AMBA=y -CONFIG_ARM_ARCH_TIMER=y -CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y -CONFIG_ARM_GIC_V2M=y -CONFIG_ARM_GIC_V3=y -CONFIG_ARM_GIC_V3_ITS=y -# CONFIG_ARM_PL172_MPMC is not set -CONFIG_ARM_PSCI_FW=y -# CONFIG_ARM_SP805_WATCHDOG is not set -CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y -# CONFIG_DEBUG_ALIGN_RODATA is not set -CONFIG_FRAME_POINTER=y -CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y -CONFIG_GENERIC_CSUM=y -CONFIG_GENERIC_IRQ_MIGRATION=y -CONFIG_GENERIC_PINCONF=y -CONFIG_GENERIC_TIME_VSYSCALL=y -CONFIG_HAVE_ALIGNED_STRUCT_PAGE=y -CONFIG_HAVE_ARCH_HUGE_VMAP=y -CONFIG_HAVE_ARCH_KASAN=y -CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE=y -CONFIG_HAVE_ARCH_VMAP_STACK=y -CONFIG_HAVE_CMPXCHG_DOUBLE=y -CONFIG_HAVE_CMPXCHG_LOCAL=y -CONFIG_HAVE_DEBUG_BUGVERBOSE=y -CONFIG_HAVE_GENERIC_GUP=y -CONFIG_HAVE_MEMORY_PRESENT=y -CONFIG_HAVE_PATA_PLATFORM=y -CONFIG_HAVE_RCU_TABLE_FREE=y -CONFIG_HOLES_IN_ZONE=y -# CONFIG_HUGETLBFS is not set -CONFIG_HW_RANDOM_OMAP=y -CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000 -CONFIG_MARVELL_10G_PHY=y -CONFIG_MFD_SYSCON=y -CONFIG_MMC_SDHCI_XENON=y -CONFIG_MODULES_USE_ELF_RELA=y -CONFIG_MVEBU_GICP=y -CONFIG_MVEBU_ICU=y -CONFIG_MVEBU_ODMI=y -CONFIG_MVEBU_PIC=y -CONFIG_MV_XOR_V2=y -CONFIG_NEED_SG_DMA_LENGTH=y -# CONFIG_NUMA is not set -CONFIG_PARTITION_PERCPU=y -CONFIG_PCIEAER=y -CONFIG_PCIEPORTBUS=y -CONFIG_PCIE_ARMADA_8K=y -CONFIG_PCIE_DW=y -CONFIG_PCIE_DW_HOST=y -# CONFIG_PCI_AARDVARK is not set -CONFIG_PCI_BUS_ADDR_T_64BIT=y -CONFIG_PGTABLE_LEVELS=3 -CONFIG_PHYS_ADDR_T_64BIT=y -CONFIG_PHY_MVEBU_CP110_COMPHY=y -CONFIG_PINCTRL_ARMADA_37XX=y -CONFIG_PINCTRL_ARMADA_AP806=y -CONFIG_PINCTRL_ARMADA_CP110=y -CONFIG_POWER_RESET=y -CONFIG_POWER_SUPPLY=y -# CONFIG_RANDOMIZE_BASE is not set -CONFIG_RAS=y -CONFIG_REGULATOR_GPIO=y -# CONFIG_SERIAL_AMBA_PL011 is not set -CONFIG_SPARSEMEM=y -CONFIG_SPARSEMEM_EXTREME=y -CONFIG_SPARSEMEM_MANUAL=y -CONFIG_SPARSEMEM_VMEMMAP=y -CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y -CONFIG_SYSCTL_EXCEPTION_TRACE=y -CONFIG_SYS_SUPPORTS_HUGETLBFS=y -CONFIG_THREAD_INFO_IN_TASK=y -CONFIG_UNMAP_KERNEL_AT_EL0=y -CONFIG_VMAP_STACK=y diff --git a/target/linux/mvebu/files-4.14/arch/arm/boot/dts/armada-385-linksys-venom.dts b/target/linux/mvebu/files-4.14/arch/arm/boot/dts/armada-385-linksys-venom.dts deleted file mode 100644 index 2e0bed815f50..000000000000 --- a/target/linux/mvebu/files-4.14/arch/arm/boot/dts/armada-385-linksys-venom.dts +++ /dev/null @@ -1,207 +0,0 @@ -/* - * Device Tree file for the Linksys WRT32X (Venom) - * - * Copyright (C) 2017 Imre Kaloz - * - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without - * any warranty of any kind, whether express or implied. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include -#include -#include "armada-385-linksys.dtsi" - -/ { - model = "Linksys WRT32X"; - compatible = "linksys,venom", "linksys,armada385", "marvell,armada385", - "marvell,armada380"; - - chosen { - bootargs = "console=ttyS0,115200"; - stdout-path = "serial0:115200n8"; - append-rootblock = "root=/dev/mtdblock"; - }; -}; - - &expander0 { - wan_amber@0 { - label = "venom:amber:wan"; - reg = <0x0>; - }; - - wan_blue@1 { - label = "venom:blue:wan"; - reg = <0x1>; - }; - - usb2@5 { - label = "venom:blue:usb2"; - reg = <0x5>; - }; - - usb3_1@6 { - label = "venom:blue:usb3_1"; - reg = <0x6>; - }; - - usb3_2@7 { - label = "venom:blue:usb3_2"; - reg = <0x7>; - }; - - wps_blue@8 { - label = "venom:blue:wps"; - reg = <0x8>; - }; - - wps_amber@9 { - label = "venom:amber:wps"; - reg = <0x9>; - }; - }; - - &gpio_leds { - power { - gpios = <&gpio1 24 GPIO_ACTIVE_HIGH>; - label = "venom:blue:power"; - }; - - sata { - gpios = <&gpio1 21 GPIO_ACTIVE_LOW>; - label = "venom:blue:sata"; - }; - - wlan_2g { - gpios = <&gpio1 13 GPIO_ACTIVE_LOW>; - label = "venom:blue:wlan_2g"; - }; - - wlan_5g { - gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; - label = "venom:blue:wlan_5g"; - }; - }; - - &gpio_leds_pins { - marvell,pins = "mpp21", "mpp45", "mpp46", "mpp56"; - }; - - &nand { - /* Spansion S34ML02G2 256MiB, OEM Layout */ - partition@0 { - label = "u-boot"; - reg = <0x0000000 0x200000>; /* 2MB */ - read-only; - }; - - partition@200000 { - label = "u_env"; - reg = <0x200000 0x20000>; /* 128KB */ - }; - - partition@220000 { - label = "s_env"; - reg = <0x220000 0x40000>; /* 256KB */ - }; - - partition@180000 { - label = "unused_area"; - reg = <0x260000 0x5c0000>; /* 5.75MB */ - }; - - partition@7e0000 { - label = "devinfo"; - reg = <0x7e0000 0x40000>; /* 256KB */ - read-only; - }; - - /* kernel1 overlaps with rootfs1 by design */ - partition@900000 { - label = "kernel1"; - reg = <0x900000 0x7b00000>; /* 123MB */ - }; - - partition@c00000 { - label = "rootfs1"; - reg = <0xc00000 0x7800000>; /* 120MB */ - }; - - /* kernel2 overlaps with rootfs2 by design */ - partition@8400000 { - label = "kernel2"; - reg = <0x8400000 0x7b00000>; /* 123MB */ - }; - - partition@8700000 { - label = "rootfs2"; - reg = <0x8700000 0x7800000>; /* 120MB */ - }; - - /* last MB is for the BBT, not writable */ - partition@ff00000 { - label = "BBT"; - reg = <0xff00000 0x100000>; - }; - }; - - - &pcie1 { - mwlwifi { - marvell,chainmask = <4 4>; - }; - }; - - &pcie2 { - mwlwifi { - marvell,chainmask = <4 4>; - }; - }; - - &sdhci { - pinctrl-names = "default"; - pinctrl-0 = <&sdhci_pins>; - no-1-8-v; - non-removable; - wp-inverted; - bus-width = <8>; - status = "okay"; - }; - - &usb3_1_vbus { - gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>; - }; - - &usb3_1_vbus_pins { - marvell,pins = "mpp44"; - }; diff --git a/target/linux/mvebu/files-4.14/arch/arm64/boot/dts/marvell/armada-3720-espressobin-emmc.dts b/target/linux/mvebu/files-4.14/arch/arm64/boot/dts/marvell/armada-3720-espressobin-emmc.dts deleted file mode 100644 index ef90a1bd387b..000000000000 --- a/target/linux/mvebu/files-4.14/arch/arm64/boot/dts/marvell/armada-3720-espressobin-emmc.dts +++ /dev/null @@ -1,28 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree file for Globalscale Marvell ESPRESSOBin Board with eMMC - * Copyright (C) 2018 Marvell - * - * Romain Perier - * Konstantin Porotchkin - * - */ - -#include "armada-3720-espressobin.dts" - -/ { - model = "Globalscale Marvell ESPRESSOBin Board (eMMC)"; - compatible = "globalscale,espressobin-emmc", "globalscale,espressobin", - "marvell,armada3720", "marvell,armada3710"; -}; - -&sdhci0 { - status = "okay"; - - #address-cells = <1>; - #size-cells = <0>; - mmccard: mmccard@0 { - compatible = "mmc-card"; - reg = <0>; - }; -}; diff --git a/target/linux/mvebu/files-4.14/arch/arm64/boot/dts/marvell/armada-3720-espressobin-v7-emmc.dts b/target/linux/mvebu/files-4.14/arch/arm64/boot/dts/marvell/armada-3720-espressobin-v7-emmc.dts deleted file mode 100644 index 2b565ca8d822..000000000000 --- a/target/linux/mvebu/files-4.14/arch/arm64/boot/dts/marvell/armada-3720-espressobin-v7-emmc.dts +++ /dev/null @@ -1,43 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree file for Globalscale Marvell ESPRESSOBin Board V7 with eMMC - * Copyright (C) 2018 Marvell - * - * Romain Perier - * Konstantin Porotchkin - * - */ - -#include "armada-3720-espressobin.dts" - -/ { - model = "Globalscale Marvell ESPRESSOBin Board V7 (eMMC)"; - compatible = "globalscale,espressobin-v7-emmc", "globalscale,espressobin-v7", - "globalscale,espressobin", "marvell,armada3720", - "marvell,armada3710"; -}; - -&ports { - port@1 { - reg = <1>; - label = "lan1"; - phy-handle = <&switch0phy0>; - }; - - port@3 { - reg = <3>; - label = "wan"; - phy-handle = <&switch0phy2>; - }; -}; - -&sdhci0 { - status = "okay"; - - #address-cells = <1>; - #size-cells = <0>; - mmccard: mmccard@0 { - compatible = "mmc-card"; - reg = <0>; - }; -}; diff --git a/target/linux/mvebu/files-4.14/arch/arm64/boot/dts/marvell/armada-3720-espressobin-v7.dts b/target/linux/mvebu/files-4.14/arch/arm64/boot/dts/marvell/armada-3720-espressobin-v7.dts deleted file mode 100644 index 8a408c3c48f4..000000000000 --- a/target/linux/mvebu/files-4.14/arch/arm64/boot/dts/marvell/armada-3720-espressobin-v7.dts +++ /dev/null @@ -1,31 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree file for Globalscale Marvell ESPRESSOBin Board V7 - * Copyright (C) 2018 Marvell - * - * Romain Perier - * Konstantin Porotchkin - * - */ - -#include "armada-3720-espressobin.dts" - -/ { - model = "Globalscale Marvell ESPRESSOBin Board V7"; - compatible = "globalscale,espressobin-v7", "globalscale,espressobin", - "marvell,armada3720", "marvell,armada3710"; -}; - -&ports { - port@1 { - reg = <1>; - label = "lan1"; - phy-handle = <&switch0phy0>; - }; - - port@3 { - reg = <3>; - label = "wan"; - phy-handle = <&switch0phy2>; - }; -}; diff --git a/target/linux/mvebu/patches-4.14/002-add_powertables.patch b/target/linux/mvebu/patches-4.14/002-add_powertables.patch deleted file mode 100644 index c5a211dd4042..000000000000 --- a/target/linux/mvebu/patches-4.14/002-add_powertables.patch +++ /dev/null @@ -1,770 +0,0 @@ ---- a/arch/arm/boot/dts/armada-385-linksys.dtsi -+++ b/arch/arm/boot/dts/armada-385-linksys.dtsi -@@ -237,11 +237,19 @@ - &pcie1 { - /* Marvell 88W8864, 5GHz-only */ - status = "okay"; -+ -+ mwlwifi { -+ marvell,2ghz = <0>; -+ }; - }; - - &pcie2 { - /* Marvell 88W8864, 2GHz-only */ - status = "okay"; -+ -+ mwlwifi { -+ marvell,5ghz = <0>; -+ }; - }; - - &pinctrl { ---- a/arch/arm/boot/dts/armada-385-linksys-caiman.dts -+++ b/arch/arm/boot/dts/armada-385-linksys-caiman.dts -@@ -169,3 +169,205 @@ - reg = <0x280000 0x680000>; /* 6.5MiB */ - }; - }; -+ -+&pcie1 { -+ mwlwifi { -+ marvell,chainmask = <2 2>; -+ marvell,powertable { -+ AU = -+ <36 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>, -+ <40 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>, -+ <44 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>, -+ <48 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>, -+ <52 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>, -+ <56 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>, -+ <60 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>, -+ <64 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>, -+ <100 0 0x17 0x17 0x17 0x17 0x17 0x17 0x17 0x15 0x17 0x17 0x17 0x14 0x17 0x17 0x17 0x14 0 0xf>, -+ <104 0 0x17 0x17 0x17 0x17 0x17 0x17 0x17 0x15 0x17 0x17 0x17 0x14 0x17 0x17 0x17 0x14 0 0xf>, -+ <108 0 0x17 0x17 0x17 0x17 0x17 0x17 0x17 0x15 0x17 0x17 0x17 0x14 0x17 0x17 0x17 0x14 0 0xf>, -+ <112 0 0x17 0x17 0x17 0x17 0x17 0x17 0x17 0x15 0x17 0x17 0x17 0x14 0x17 0x17 0x17 0x14 0 0xf>, -+ <116 0 0x17 0x17 0x17 0x17 0x17 0x17 0x17 0x15 0x17 0x17 0x17 0x14 0x17 0x17 0x17 0x14 0 0xf>, -+ <120 0 0x17 0x17 0x17 0x17 0x17 0x17 0x17 0x15 0x17 0x17 0x17 0x14 0x17 0x17 0x17 0x14 0 0xf>, -+ <124 0 0x17 0x17 0x17 0x17 0x17 0x17 0x17 0x15 0x17 0x17 0x17 0x14 0x17 0x17 0x17 0x14 0 0xf>, -+ <128 0 0x17 0x17 0x17 0x17 0x17 0x17 0x17 0x15 0x17 0x17 0x17 0x14 0x17 0x17 0x17 0x14 0 0xf>, -+ <132 0 0x17 0x17 0x17 0x17 0x17 0x17 0x17 0x15 0x17 0x17 0x17 0x14 0x17 0x17 0x17 0x14 0 0xf>, -+ <136 0 0x17 0x17 0x17 0x17 0x17 0x17 0x17 0x15 0x17 0x17 0x17 0x14 0x17 0x17 0x17 0x14 0 0xf>, -+ <140 0 0x17 0x17 0x17 0x17 0x17 0x17 0x17 0x15 0x17 0x17 0x17 0x14 0x17 0x17 0x17 0x14 0 0xf>, -+ <149 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x1a 0x1a 0x17 0x14 0 0xf>, -+ <153 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x1a 0x1a 0x17 0x14 0 0xf>, -+ <157 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x1a 0x1a 0x17 0x14 0 0xf>, -+ <161 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x1a 0x1a 0x17 0x14 0 0xf>, -+ <165 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x1a 0x1a 0x17 0x14 0 0xf>; -+ CA = -+ <36 0 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0 0xf>, -+ <40 0 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0 0xf>, -+ <44 0 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0 0xf>, -+ <48 0 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0 0xf>, -+ <52 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>, -+ <56 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>, -+ <60 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>, -+ <64 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>, -+ <100 0 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>, -+ <104 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>, -+ <108 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, -+ <112 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, -+ <116 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, -+ <120 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, -+ <124 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, -+ <128 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, -+ <132 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, -+ <136 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, -+ <140 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, -+ <149 0 0x1a 0x1a 0x18 0x17 0x19 0x19 0x17 0x15 0x18 0x18 0x17 0x14 0x15 0x15 0x15 0x14 0 0xf>, -+ <153 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x15 0x15 0x15 0x14 0 0xf>, -+ <157 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x15 0x15 0x15 0x14 0 0xf>, -+ <161 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x15 0x15 0x15 0x14 0 0xf>, -+ <165 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x15 0x15 0x15 0x14 0 0xf>; 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-+ ETSI = -+ <36 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>, -+ <40 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>, -+ <44 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>, -+ <48 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>, -+ <52 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>, -+ <56 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>, -+ <60 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>, -+ <64 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>, -+ <100 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>, -+ <104 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>, -+ <108 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>, -+ <112 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>, -+ <116 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>, -+ <120 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>, -+ <124 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>, -+ <128 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>, -+ <132 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>, -+ <136 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>, -+ <140 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>, -+ <149 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>; -+ FCC = -+ <36 0 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>, -+ <40 0 0x19 0x19 0x18 0x17 0x19 0x19 0x17 0x15 0x17 0x17 0x17 0x14 0x10 0x10 0x10 0x10 0 0xf>, -+ <44 0 0x19 0x19 0x18 0x17 0x19 0x19 0x17 0x15 0x17 0x17 0x17 0x14 0x10 0x10 0x10 0x10 0 0xf>, -+ <48 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x17 0x17 0x17 0x14 0x10 0x10 0x10 0x10 0 0xf>, -+ <52 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>, -+ <56 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>, -+ <60 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>, -+ <64 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>, -+ <100 0 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>, -+ <104 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>, -+ <108 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, -+ <112 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, -+ <116 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, -+ <120 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, -+ <124 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, -+ <128 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, -+ <132 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, -+ <136 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, -+ <140 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, -+ <149 0 0x1a 0x1a 0x18 0x17 0x19 0x19 0x17 0x15 0x18 0x18 0x17 0x14 0x15 0x15 0x15 0x14 0 0xf>, -+ <153 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x15 0x15 0x15 0x14 0 0xf>, -+ <157 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x15 0x15 0x15 0x14 0 0xf>, -+ <161 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x15 0x15 0x15 0x14 0 0xf>, -+ <165 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x15 0x15 0x15 0x14 0 0xf>; -+ }; -+ }; -+}; -+ -+&pcie2 { -+ mwlwifi { -+ marvell,chainmask = <2 2>; -+ marvell,powertable { -+ AU = -+ <1 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>, -+ <2 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>, -+ <3 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>, -+ <4 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>, -+ <5 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>, -+ <6 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>, -+ <7 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>, -+ <8 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>, -+ <9 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>, -+ <10 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>, -+ <11 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>; -+ CA = -+ <1 0 0x19 0x14 0x14 0x14 0x13 0x13 0x13 0x13 0x10 0x10 0x10 0x10 0x00 0x00 0x00 0x00 0 0xf>, -+ <2 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x00 0x00 0x00 0x00 0 0xf>, -+ <3 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x00 0x00 0x00 0x00 0 0xf>, -+ <4 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x00 0x00 0x00 0x00 0 0xf>, -+ <5 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x00 0x00 0x00 0x00 0 0xf>, -+ <6 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x00 0x00 0x00 0x00 0 0xf>, -+ <7 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x00 0x00 0x00 0x00 0 0xf>, -+ <8 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x00 0x00 0x00 0x00 0 0xf>, -+ <9 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x00 0x00 0x00 0x00 0 0xf>, -+ <10 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x00 0x00 0x00 0x00 0 0xf>, -+ <11 0 0x19 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0x13 0x13 0x13 0x13 0x00 0x00 0x00 0x00 0 0xf>; -+ CN = -+ <1 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>, -+ <2 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>, -+ <3 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>, -+ <4 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>, -+ <5 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>, -+ <6 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>, -+ <7 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>, -+ <8 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>, -+ <9 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>, -+ <10 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>, -+ <11 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>, -+ <12 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>, -+ <13 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>, -+ <14 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>; -+ ETSI = -+ <1 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>, -+ <2 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>, -+ <3 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>, -+ <4 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>, -+ <5 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>, -+ <6 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>, -+ <7 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>, -+ <8 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>, -+ <9 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>, -+ <10 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>, -+ <11 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>, -+ <12 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>, -+ <13 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>; -+ FCC = -+ <1 0 0x19 0x14 0x14 0x14 0x13 0x13 0x13 0x13 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>, -+ <2 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x0 0x0 0x0 0x0 0 0xf>, -+ <3 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x0 0x0 0x0 0x0 0 0xf>, -+ <4 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x0 0x0 0x0 0x0 0 0xf>, -+ <5 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x0 0x0 0x0 0x0 0 0xf>, -+ <6 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x0 0x0 0x0 0x0 0 0xf>, -+ <7 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x0 0x0 0x0 0x0 0 0xf>, -+ <8 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x0 0x0 0x0 0x0 0 0xf>, -+ <9 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x0 0x0 0x0 0x0 0 0xf>, -+ <10 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x0 0x0 0x0 0x0 0 0xf>, -+ <11 0 0x19 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0x13 0x13 0x13 0x13 0x0 0x0 0x0 0x0 0 0xf>; -+ }; -+ }; -+}; ---- a/arch/arm/boot/dts/armada-385-linksys-cobra.dts -+++ b/arch/arm/boot/dts/armada-385-linksys-cobra.dts -@@ -169,3 +169,205 @@ - reg = <0x280000 0x680000>; /* 6.5MiB */ - }; - }; -+ -+&pcie1 { -+ mwlwifi { -+ marvell,chainmask = <4 4>; -+ marvell,powertable { -+ AU = -+ <36 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <40 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <44 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <48 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <52 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <56 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <60 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <64 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <100 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>, -+ <104 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>, -+ <108 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>, -+ <112 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>, -+ <116 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>, -+ <120 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>, -+ <124 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>, -+ <128 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>, -+ <132 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>, -+ <136 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>, -+ <140 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>, -+ <149 0 0x19 0x19 0x19 0x17 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0 0xf>, -+ <153 0 0x19 0x19 0x19 0x17 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0 0xf>, -+ <157 0 0x19 0x19 0x19 0x17 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0 0xf>, -+ <161 0 0x19 0x19 0x19 0x17 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0 0xf>, -+ <165 0 0x19 0x19 0x19 0x17 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0 0xf>; -+ CA = -+ <36 0 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0 0xf>, -+ <40 0 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0 0xf>, -+ <44 0 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0 0xf>, -+ <48 0 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0 0xf>, -+ <52 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>, -+ <56 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>, -+ <60 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>, -+ <64 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>, -+ <100 0 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>, -+ <104 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>, -+ <108 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, -+ <112 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, -+ <116 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, -+ <120 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, -+ <124 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, -+ <128 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, -+ <132 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, -+ <136 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, -+ <140 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, -+ <149 0 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>, -+ <153 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>, -+ <157 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>, -+ <161 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>, -+ <165 0 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>; -+ CN = -+ <36 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <40 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <44 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <48 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <52 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <56 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <60 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <64 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <100 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <104 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <108 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <112 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <116 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <120 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <124 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <128 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <132 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <136 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <140 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <149 0 0x14 0x14 0x14 0x14 0x13 0x13 0x13 0x13 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, -+ <153 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0x10 0x10 0x10 0x10 0 0xf>, -+ <157 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0x10 0x10 0x10 0x10 0 0xf>, -+ <161 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0x10 0x10 0x10 0x10 0 0xf>, -+ <165 0 0x13 0x13 0x13 0x13 0x13 0x13 0x13 0x13 0x14 0x14 0x14 0x14 0x10 0x10 0x10 0x10 0 0xf>; -+ ETSI = -+ <36 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <40 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <44 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <48 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <52 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <56 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <60 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <64 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <100 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <104 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <108 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <112 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <116 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <120 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <124 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <128 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <132 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <136 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <140 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <149 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>; -+ FCC = -+ <36 0 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0xf 0xf 0xf 0xf 0 0xf>, -+ <40 0 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0xf 0xf 0xf 0xf 0 0xf>, -+ <44 0 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0xf 0xf 0xf 0xf 0 0xf>, -+ <48 0 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0xf 0xf 0xf 0xf 0 0xf>, -+ <52 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>, -+ <56 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>, -+ <60 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>, -+ <64 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>, -+ <100 0 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>, -+ <104 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>, -+ <108 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, -+ <112 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, -+ <116 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, -+ <120 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, -+ <124 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, -+ <128 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, -+ <132 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, -+ <136 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, -+ <140 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, -+ <149 0 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>, -+ <153 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>, -+ <157 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>, -+ <161 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>, -+ <165 0 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>; -+ }; -+ }; -+}; -+ -+&pcie2 { -+ mwlwifi { -+ marvell,chainmask = <4 4>; -+ marvell,powertable { -+ AU = -+ <1 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <2 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <3 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <4 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <5 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <6 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <7 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <8 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <9 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <10 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <11 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>; -+ CA = -+ <1 0 0x17 0x10 0x10 0x10 0xf 0xf 0xf 0xf 0xe 0xe 0xe 0xe 0x0 0x0 0x0 0x0 0 0xf>, -+ <2 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>, -+ <3 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>, -+ <4 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>, -+ <5 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>, -+ <6 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>, -+ <7 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>, -+ <8 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>, -+ <9 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>, -+ <10 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>, -+ <11 0 0x17 0x12 0x12 0x12 0x13 0x13 0x13 0x13 0xf 0xf 0xf 0xf 0x0 0x0 0x0 0x0 0 0xf>; -+ CN = -+ <1 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <2 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <3 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <4 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <5 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <6 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <7 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <8 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <9 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <10 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <11 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <12 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <13 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <14 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>; -+ ETSI = -+ <1 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <2 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <3 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <4 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <5 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <6 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <7 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <8 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <9 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <10 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <11 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <12 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <13 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>; -+ FCC = -+ <1 0 0x17 0x10 0x10 0x10 0xf 0xf 0xf 0xf 0xe 0xe 0xe 0xe 0x0 0x0 0x0 0x0 0 0xf>, -+ <2 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>, -+ <3 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>, -+ <4 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>, -+ <5 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>, -+ <6 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>, -+ <7 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>, -+ <8 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>, -+ <9 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>, -+ <10 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>, -+ <11 0 0x17 0x12 0x12 0x12 0x13 0x13 0x13 0x13 0xf 0xf 0xf 0xf 0x0 0x0 0x0 0x0 0 0xf>; -+ }; -+ }; -+}; ---- a/arch/arm/boot/dts/armada-385-linksys-shelby.dts -+++ b/arch/arm/boot/dts/armada-385-linksys-shelby.dts -@@ -169,3 +169,205 @@ - reg = <0x280000 0x680000>; /* 6.5MiB */ - }; - }; -+ -+&pcie1 { -+ mwlwifi { -+ marvell,chainmask = <4 4>; -+ marvell,powertable { -+ AU = -+ <36 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <40 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <44 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <48 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <52 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <56 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <60 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <64 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <100 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>, -+ <104 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>, -+ <108 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>, -+ <112 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>, -+ <116 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>, -+ <120 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>, -+ <124 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>, -+ <128 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>, -+ <132 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>, -+ <136 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>, -+ <140 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>, -+ <149 0 0x19 0x19 0x19 0x17 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0 0xf>, -+ <153 0 0x19 0x19 0x19 0x17 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0 0xf>, -+ <157 0 0x19 0x19 0x19 0x17 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0 0xf>, -+ <161 0 0x19 0x19 0x19 0x17 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0 0xf>, -+ <165 0 0x19 0x19 0x19 0x17 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0 0xf>; -+ CA = -+ <36 0 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0 0xf>, -+ <40 0 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0 0xf>, -+ <44 0 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0 0xf>, -+ <48 0 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0 0xf>, -+ <52 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>, -+ <56 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>, -+ <60 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>, -+ <64 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>, -+ <100 0 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>, -+ <104 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>, -+ <108 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, -+ <112 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, -+ <116 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, -+ <120 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, -+ <124 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, -+ <128 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, -+ <132 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, -+ <136 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, -+ <140 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, -+ <149 0 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>, -+ <153 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>, -+ <157 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>, -+ <161 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>, -+ <165 0 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>; -+ CN = -+ <36 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <40 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <44 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <48 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <52 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <56 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <60 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <64 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <100 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <104 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <108 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <112 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <116 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <120 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <124 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <128 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <132 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <136 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <140 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <149 0 0x14 0x14 0x14 0x14 0x13 0x13 0x13 0x13 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, -+ <153 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0x10 0x10 0x10 0x10 0 0xf>, -+ <157 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0x10 0x10 0x10 0x10 0 0xf>, -+ <161 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0x10 0x10 0x10 0x10 0 0xf>, -+ <165 0 0x13 0x13 0x13 0x13 0x13 0x13 0x13 0x13 0x14 0x14 0x14 0x14 0x10 0x10 0x10 0x10 0 0xf>; -+ ETSI = -+ <36 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <40 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <44 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <48 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <52 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <56 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <60 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <64 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <100 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <104 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <108 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <112 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <116 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <120 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <124 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <128 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <132 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <136 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <140 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <149 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>; -+ FCC = -+ <36 0 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0xf 0xf 0xf 0xf 0 0xf>, -+ <40 0 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0xf 0xf 0xf 0xf 0 0xf>, -+ <44 0 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0xf 0xf 0xf 0xf 0 0xf>, -+ <48 0 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0xf 0xf 0xf 0xf 0 0xf>, -+ <52 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>, -+ <56 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>, -+ <60 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>, -+ <64 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>, -+ <100 0 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>, -+ <104 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>, -+ <108 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, -+ <112 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, -+ <116 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, -+ <120 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, -+ <124 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, -+ <128 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, -+ <132 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, -+ <136 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, -+ <140 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, -+ <149 0 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>, -+ <153 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>, -+ <157 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>, -+ <161 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>, -+ <165 0 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>; -+ }; -+ }; -+}; -+ -+&pcie2 { -+ mwlwifi { -+ marvell,chainmask = <4 4>; -+ marvell,powertable { -+ AU = -+ <1 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <2 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <3 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <4 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <5 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <6 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <7 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <8 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <9 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <10 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <11 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>; -+ CA = -+ <1 0 0x17 0x10 0x10 0x10 0xf 0xf 0xf 0xf 0xe 0xe 0xe 0xe 0x0 0x0 0x0 0x0 0 0xf>, -+ <2 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>, -+ <3 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>, -+ <4 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>, -+ <5 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>, -+ <6 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>, -+ <7 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>, -+ <8 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>, -+ <9 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>, -+ <10 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>, -+ <11 0 0x17 0x12 0x12 0x12 0x13 0x13 0x13 0x13 0xf 0xf 0xf 0xf 0x0 0x0 0x0 0x0 0 0xf>; -+ CN = -+ <1 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <2 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <3 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <4 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <5 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <6 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <7 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <8 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <9 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <10 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <11 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <12 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <13 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <14 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>; -+ ETSI = -+ <1 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <2 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <3 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <4 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <5 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <6 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <7 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <8 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <9 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <10 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <11 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <12 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <13 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>; -+ FCC = -+ <1 0 0x17 0x10 0x10 0x10 0xf 0xf 0xf 0xf 0xe 0xe 0xe 0xe 0x0 0x0 0x0 0x0 0 0xf>, -+ <2 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>, -+ <3 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>, -+ <4 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>, -+ <5 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>, -+ <6 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>, -+ <7 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>, -+ <8 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>, -+ <9 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>, -+ <10 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>, -+ <11 0 0x17 0x12 0x12 0x12 0x13 0x13 0x13 0x13 0xf 0xf 0xf 0xf 0x0 0x0 0x0 0x0 0 0xf>; -+ }; -+ }; -+}; ---- a/arch/arm/boot/dts/armada-385-linksys-rango.dts -+++ b/arch/arm/boot/dts/armada-385-linksys-rango.dts -@@ -184,6 +184,18 @@ - }; - }; - -+&pcie1 { -+ mwlwifi { -+ marvell,chainmask = <4 4>; -+ }; -+}; -+ -+&pcie2 { -+ mwlwifi { -+ marvell,chainmask = <4 4>; -+ }; -+}; -+ - &sdhci { - pinctrl-names = "default"; - pinctrl-0 = <&sdhci_pins>; ---- a/arch/arm/boot/dts/armada-xp-linksys-mamba.dts -+++ b/arch/arm/boot/dts/armada-xp-linksys-mamba.dts -@@ -376,12 +376,100 @@ - pcie@2,0 { - /* Port 0, Lane 1 */ - status = "okay"; -+ -+ mwlwifi { -+ marvell,5ghz = <0>; -+ marvell,chainmask = <4 4>; -+ marvell,powertable { -+ FCC = -+ <1 0 0x17 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0xf 0xf 0xf 0xf 0x0 0x0 0x0 0x0 0 0xf>, -+ <2 0 0x17 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>, -+ <3 0 0x17 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>, -+ <4 0 0x17 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>, -+ <5 0 0x17 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>, -+ <6 0 0x17 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>, -+ <7 0 0x17 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>, -+ <8 0 0x17 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>, -+ <9 0 0x17 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>, -+ <10 0 0x17 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>, -+ <11 0 0x17 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>; -+ -+ ETSI = -+ <1 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>, -+ <2 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>, -+ <3 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>, -+ <4 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>, -+ <5 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>, -+ <6 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>, -+ <7 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>, -+ <8 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>, -+ <9 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>, -+ <10 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>, -+ <11 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>, -+ <12 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>, -+ <13 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>; -+ }; -+ }; - }; - - /* Second mini-PCIe port */ - pcie@3,0 { - /* Port 0, Lane 3 */ - status = "okay"; -+ -+ mwlwifi { -+ marvell,2ghz = <0>; -+ marvell,chainmask = <4 4>; -+ marvell,powertable { -+ FCC = -+ <36 0 0x8 0x8 0x8 0x8 0x8 0x8 0x8 0x8 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0 0xf>, -+ <40 0 0x8 0x8 0x8 0x8 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0 0xf>, -+ <44 0 0x8 0x8 0x8 0x8 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0 0xf>, -+ <48 0 0x8 0x8 0x8 0x8 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0 0xf>, -+ <52 0 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0 0xf>, -+ <56 0 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0 0xf>, -+ <60 0 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0 0xf>, -+ <64 0 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0 0xf>, -+ <100 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>, -+ <104 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>, -+ <108 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>, -+ <112 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>, -+ <116 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>, -+ <120 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>, -+ <124 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>, -+ <128 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>, -+ <132 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>, -+ <136 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>, -+ <140 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>, -+ <149 0 0x16 0x16 0x16 0x16 0x14 0x14 0x14 0x14 0x15 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0 0xf>, -+ <153 0 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0 0xf>, -+ <157 0 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0 0xf>, -+ <161 0 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0 0xf>, -+ <165 0 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0 0xf>; -+ -+ ETSI = -+ <36 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>, -+ <40 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>, -+ <44 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>, -+ <48 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>, -+ <52 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>, -+ <56 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>, -+ <60 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>, -+ <64 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>, -+ <100 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>, -+ <104 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>, -+ <108 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>, -+ <112 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>, -+ <116 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>, -+ <120 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>, -+ <124 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>, -+ <128 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>, -+ <132 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>, -+ <136 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>, -+ <140 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>, -+ <149 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>; -+ }; -+ }; - }; - }; - diff --git a/target/linux/mvebu/patches-4.14/003-add_switch_nodes.patch b/target/linux/mvebu/patches-4.14/003-add_switch_nodes.patch deleted file mode 100644 index 5d43d9f0f8cb..000000000000 --- a/target/linux/mvebu/patches-4.14/003-add_switch_nodes.patch +++ /dev/null @@ -1,40 +0,0 @@ ---- a/arch/arm/boot/dts/armada-xp-linksys-mamba.dts -+++ b/arch/arm/boot/dts/armada-xp-linksys-mamba.dts -@@ -361,6 +361,16 @@ - }; - }; - }; -+ -+ mvsw61xx { -+ compatible = "marvell,88e6172"; -+ status = "okay"; -+ reg = <0x10>; -+ -+ mii-bus = <&mdio>; -+ cpu-port-0 = <5>; -+ cpu-port-1 = <6>; -+ }; - }; - - &pciec { ---- a/arch/arm/boot/dts/armada-385-linksys.dtsi -+++ b/arch/arm/boot/dts/armada-385-linksys.dtsi -@@ -113,6 +113,18 @@ - linux,default-trigger = "disk-activity"; - }; - }; -+ -+ mvsw61xx { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ compatible = "marvell,88e6176"; -+ status = "okay"; -+ reg = <0x10>; -+ -+ mii-bus = <&mdio>; -+ cpu-port-0 = <5>; -+ cpu-port-1 = <6>; -+ }; - }; - - &ahci0 { diff --git a/target/linux/mvebu/patches-4.14/004-add_sata_disk_activity_trigger.patch b/target/linux/mvebu/patches-4.14/004-add_sata_disk_activity_trigger.patch deleted file mode 100644 index 1a2b33cb1ad5..000000000000 --- a/target/linux/mvebu/patches-4.14/004-add_sata_disk_activity_trigger.patch +++ /dev/null @@ -1,39 +0,0 @@ -From 172230195068703b78ad5733a09492f5d6814c09 Mon Sep 17 00:00:00 2001 -From: Ansuel Smith -Date: Tue, 28 Feb 2017 14:15:50 +0100 -Subject: [PATCH] ARM: dts: armada: Add default trigger for sata led - -In others board we have the sata led set to function -with the sata led trigger by default. -This patch makes the same for these board that have sata -led but get disabled by not associating it to any trigger. - -Signed-off-by: Ansuel Smith -Acked-by: Jason Cooper -Signed-off-by: Gregory CLEMENT ---- - arch/arm/boot/dts/armada-385-linksys-caiman.dts | 1 + - arch/arm/boot/dts/armada-385-linksys-cobra.dts | 1 + - arch/arm/boot/dts/armada-xp-linksys-mamba.dts | 1 + - 3 files changed, 3 insertions(+) - ---- a/arch/arm/boot/dts/armada-385-linksys-caiman.dts -+++ b/arch/arm/boot/dts/armada-385-linksys-caiman.dts -@@ -100,6 +100,7 @@ - - sata { - label = "caiman:white:sata"; -+ linux,default-trigger = "disk-activity"; - }; - }; - ---- a/arch/arm/boot/dts/armada-385-linksys-cobra.dts -+++ b/arch/arm/boot/dts/armada-385-linksys-cobra.dts -@@ -100,6 +100,7 @@ - - sata { - label = "cobra:white:sata"; -+ linux,default-trigger = "disk-activity"; - }; - }; - diff --git a/target/linux/mvebu/patches-4.14/005-linksys_hardcode_nand_ecc_settings.patch b/target/linux/mvebu/patches-4.14/005-linksys_hardcode_nand_ecc_settings.patch deleted file mode 100644 index c00e153239c1..000000000000 --- a/target/linux/mvebu/patches-4.14/005-linksys_hardcode_nand_ecc_settings.patch +++ /dev/null @@ -1,17 +0,0 @@ -Newer Linksys boards might come with a Winbond W29N02GV which can be -configured in different ways. Make sure we configure it the same way -as the older chips so everything keeps working. - -Signed-off-by: Imre Kaloz - ---- a/arch/arm/boot/dts/armada-385-linksys.dtsi -+++ b/arch/arm/boot/dts/armada-385-linksys.dtsi -@@ -185,6 +185,8 @@ - /* 128MiB or 256MiB */ - status = "okay"; - num-cs = <1>; -+ nand-ecc-strength = <4>; -+ nand-ecc-step-size = <512>; - marvell,nand-keep-config; - marvell,nand-enable-arbiter; - nand-on-flash-bbt; diff --git a/target/linux/mvebu/patches-4.14/006-mvebu-Mangle-bootloader-s-kernel-arguments.patch b/target/linux/mvebu/patches-4.14/006-mvebu-Mangle-bootloader-s-kernel-arguments.patch deleted file mode 100644 index 8f11632d04a4..000000000000 --- a/target/linux/mvebu/patches-4.14/006-mvebu-Mangle-bootloader-s-kernel-arguments.patch +++ /dev/null @@ -1,201 +0,0 @@ -From 71270226b14733a4b1f2cde58ea9265caa50b38d Mon Sep 17 00:00:00 2001 -From: Adrian Panella -Date: Thu, 9 Mar 2017 09:37:17 +0100 -Subject: [PATCH 67/69] generic: Mangle bootloader's kernel arguments - -The command-line arguments provided by the boot loader will be -appended to a new device tree property: bootloader-args. -If there is a property "append-rootblock" in DT under /chosen -and a root= option in bootloaders command line it will be parsed -and added to DT bootargs with the form: XX. -Only command line ATAG will be processed, the rest of the ATAGs -sent by bootloader will be ignored. -This is usefull in dual boot systems, to get the current root partition -without afecting the rest of the system. - -Signed-off-by: Adrian Panella - -This patch has been modified to be mvebu specific. The original patch -did not pass the bootloader cmdline on if no append-rootblock stanza -was found, resulting in blank cmdline and failure to boot. - -Signed-off-by: Michael Gray ---- - arch/arm/Kconfig | 11 +++++ - arch/arm/boot/compressed/atags_to_fdt.c | 72 ++++++++++++++++++++++++++++++++- - init/main.c | 16 ++++++++ - 3 files changed, 98 insertions(+), 1 deletion(-) - ---- a/arch/arm/Kconfig -+++ b/arch/arm/Kconfig -@@ -1939,6 +1939,17 @@ config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEN - The command-line arguments provided by the boot loader will be - appended to the the device tree bootargs property. - -+config ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE -+ bool "Append rootblock parsing bootloader's kernel arguments" -+ help -+ The command-line arguments provided by the boot loader will be -+ appended to a new device tree property: bootloader-args. -+ If there is a property "append-rootblock" in DT under /chosen -+ and a root= option in bootloaders command line it will be parsed -+ and added to DT bootargs with the form: XX. -+ Only command line ATAG will be processed, the rest of the ATAGs -+ sent by bootloader will be ignored. -+ - endchoice - - config CMDLINE ---- a/arch/arm/boot/compressed/atags_to_fdt.c -+++ b/arch/arm/boot/compressed/atags_to_fdt.c -@@ -4,6 +4,8 @@ - - #if defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND) - #define do_extend_cmdline 1 -+#elif defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE) -+#define do_extend_cmdline 1 - #else - #define do_extend_cmdline 0 - #endif -@@ -67,6 +69,65 @@ static uint32_t get_cell_size(const void - return cell_size; - } - -+#if defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE) -+ -+static char *append_rootblock(char *dest, const char *str, int len, void *fdt) -+{ -+ char *ptr, *end; -+ char *root="root="; -+ int i, l; -+ const char *rootblock; -+ -+ //ARM doesn't have __HAVE_ARCH_STRSTR, so search manually -+ ptr = str - 1; -+ -+ do { -+ //first find an 'r' at the begining or after a space -+ do { -+ ptr++; -+ ptr = strchr(ptr, 'r'); -+ if(!ptr) return dest; -+ -+ } while (ptr != str && *(ptr-1) != ' '); -+ -+ //then check for the rest -+ for(i = 1; i <= 4; i++) -+ if(*(ptr+i) != *(root+i)) break; -+ -+ } while (i != 5); -+ -+ end = strchr(ptr, ' '); -+ end = end ? (end - 1) : (strchr(ptr, 0) - 1); -+ -+ //find partition number (assumes format root=/dev/mtdXX | /dev/mtdblockXX | yy:XX ) -+ for( i = 0; end >= ptr && *end >= '0' && *end <= '9'; end--, i++); -+ ptr = end + 1; -+ -+ /* if append-rootblock property is set use it to append to command line */ -+ rootblock = getprop(fdt, "/chosen", "append-rootblock", &l); -+ if(rootblock != NULL) { -+ if(*dest != ' ') { -+ *dest = ' '; -+ dest++; -+ len++; -+ } -+ if (len + l + i <= COMMAND_LINE_SIZE) { -+ memcpy(dest, rootblock, l); -+ dest += l - 1; -+ memcpy(dest, ptr, i); -+ dest += i; -+ } -+ } else { -+ len = strlen(str); -+ if (len + 1 < COMMAND_LINE_SIZE) { -+ memcpy(dest, str, len); -+ dest += len; -+ } -+ } -+ return dest; -+} -+#endif -+ - static void merge_fdt_bootargs(void *fdt, const char *fdt_cmdline) - { - char cmdline[COMMAND_LINE_SIZE]; -@@ -86,12 +147,21 @@ static void merge_fdt_bootargs(void *fdt - - /* and append the ATAG_CMDLINE */ - if (fdt_cmdline) { -+ -+#if defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE) -+ //save original bootloader args -+ //and append ubi.mtd with root partition number to current cmdline -+ setprop_string(fdt, "/chosen", "bootloader-args", fdt_cmdline); -+ ptr = append_rootblock(ptr, fdt_cmdline, len, fdt); -+ -+#else - len = strlen(fdt_cmdline); - if (ptr - cmdline + len + 2 < COMMAND_LINE_SIZE) { - *ptr++ = ' '; - memcpy(ptr, fdt_cmdline, len); - ptr += len; - } -+#endif - } - *ptr = '\0'; - -@@ -148,7 +218,9 @@ int atags_to_fdt(void *atag_list, void * - else - setprop_string(fdt, "/chosen", "bootargs", - atag->u.cmdline.cmdline); -- } else if (atag->hdr.tag == ATAG_MEM) { -+ } -+#ifndef CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE -+ else if (atag->hdr.tag == ATAG_MEM) { - if (memcount >= sizeof(mem_reg_property)/4) - continue; - if (!atag->u.mem.size) -@@ -187,6 +259,10 @@ int atags_to_fdt(void *atag_list, void * - setprop(fdt, "/memory", "reg", mem_reg_property, - 4 * memcount * memsize); - } -+#else -+ -+ } -+#endif - - return fdt_pack(fdt); - } ---- a/init/main.c -+++ b/init/main.c -@@ -95,6 +95,10 @@ - #include - #include - -+#if defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE) -+#include -+#endif -+ - static int kernel_init(void *); - - extern void init_IRQ(void); -@@ -573,6 +577,18 @@ asmlinkage __visible void __init start_k - page_alloc_init(); - - pr_notice("Kernel command line: %s\n", boot_command_line); -+ -+#if defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE) -+ //Show bootloader's original command line for reference -+ if(of_chosen) { -+ const char *prop = of_get_property(of_chosen, "bootloader-args", NULL); -+ if(prop) -+ pr_notice("Bootloader command line (ignored): %s\n", prop); -+ else -+ pr_notice("Bootloader command line not present\n"); -+ } -+#endif -+ - /* parameters may set static keys */ - jump_label_init(); - parse_early_param(); diff --git a/target/linux/mvebu/patches-4.14/100-find_active_root.patch b/target/linux/mvebu/patches-4.14/100-find_active_root.patch deleted file mode 100644 index f52a5108b852..000000000000 --- a/target/linux/mvebu/patches-4.14/100-find_active_root.patch +++ /dev/null @@ -1,60 +0,0 @@ -The WRT1900AC among other Linksys routers uses a dual-firmware layout. -Dynamically rename the active partition to "ubi". - -Signed-off-by: Imre Kaloz - ---- a/drivers/mtd/ofpart.c -+++ b/drivers/mtd/ofpart.c -@@ -25,6 +25,8 @@ static bool node_has_compatible(struct d - return of_get_property(pp, "compatible", NULL); - } - -+static int mangled_rootblock; -+ - static int parse_fixed_partitions(struct mtd_info *master, - const struct mtd_partition **pparts, - struct mtd_part_parser_data *data) -@@ -33,6 +35,7 @@ static int parse_fixed_partitions(struct - struct device_node *mtd_node; - struct device_node *ofpart_node; - const char *partname; -+ const char *owrtpart = "ubi"; - struct device_node *pp; - int nr_parts, i, ret = 0; - bool dedicated = true; -@@ -110,9 +113,13 @@ static int parse_fixed_partitions(struct - parts[i].size = of_read_number(reg + a_cells, s_cells); - parts[i].of_node = pp; - -- partname = of_get_property(pp, "label", &len); -- if (!partname) -- partname = of_get_property(pp, "name", &len); -+ if (mangled_rootblock && (i == mangled_rootblock)) { -+ partname = owrtpart; -+ } else { -+ partname = of_get_property(pp, "label", &len); -+ if (!partname) -+ partname = of_get_property(pp, "name", &len); -+ } - parts[i].name = partname; - - if (of_get_property(pp, "read-only", &len)) -@@ -219,6 +226,18 @@ static int __init ofpart_parser_init(voi - return 0; - } - -+static int __init active_root(char *str) -+{ -+ get_option(&str, &mangled_rootblock); -+ -+ if (!mangled_rootblock) -+ return 1; -+ -+ return 1; -+} -+ -+__setup("mangled_rootblock=", active_root); -+ - static void __exit ofpart_parser_exit(void) - { - deregister_mtd_parser(&ofpart_parser); diff --git a/target/linux/mvebu/patches-4.14/102-revert_i2c_delay.patch b/target/linux/mvebu/patches-4.14/102-revert_i2c_delay.patch deleted file mode 100644 index 77583ac0b5cd..000000000000 --- a/target/linux/mvebu/patches-4.14/102-revert_i2c_delay.patch +++ /dev/null @@ -1,15 +0,0 @@ ---- a/arch/arm/boot/dts/armada-xp.dtsi -+++ b/arch/arm/boot/dts/armada-xp.dtsi -@@ -274,12 +274,10 @@ - }; - - &i2c0 { -- compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c"; - reg = <0x11000 0x100>; - }; - - &i2c1 { -- compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c"; - reg = <0x11100 0x100>; - }; - diff --git a/target/linux/mvebu/patches-4.14/103-remove-nand-driver-bug.patch b/target/linux/mvebu/patches-4.14/103-remove-nand-driver-bug.patch deleted file mode 100644 index 19a2a1e27654..000000000000 --- a/target/linux/mvebu/patches-4.14/103-remove-nand-driver-bug.patch +++ /dev/null @@ -1,13 +0,0 @@ -Remove a BUG() call that would crash on a race condition that should -otherwise be harmless. - ---- a/drivers/mtd/nand/pxa3xx_nand.c -+++ b/drivers/mtd/nand/pxa3xx_nand.c -@@ -727,7 +727,6 @@ static void handle_data_pio(struct pxa3x - default: - dev_err(&info->pdev->dev, "%s: invalid state %d\n", __func__, - info->state); -- BUG(); - } - - /* Update buffer pointers for multi-page read/write */ diff --git a/target/linux/mvebu/patches-4.14/104-linksys_mamba_disable_keep_config.patch b/target/linux/mvebu/patches-4.14/104-linksys_mamba_disable_keep_config.patch deleted file mode 100644 index f6c7239ab278..000000000000 --- a/target/linux/mvebu/patches-4.14/104-linksys_mamba_disable_keep_config.patch +++ /dev/null @@ -1,10 +0,0 @@ ---- a/arch/arm/boot/dts/armada-xp-linksys-mamba.dts -+++ b/arch/arm/boot/dts/armada-xp-linksys-mamba.dts -@@ -200,7 +200,6 @@ - nand@d0000 { - status = "okay"; - num-cs = <1>; -- marvell,nand-keep-config; - marvell,nand-enable-arbiter; - nand-on-flash-bbt; - nand-ecc-strength = <4>; diff --git a/target/linux/mvebu/patches-4.14/110-pxa3xxx_revert_irq_thread.patch b/target/linux/mvebu/patches-4.14/110-pxa3xxx_revert_irq_thread.patch deleted file mode 100644 index 223ee652d827..000000000000 --- a/target/linux/mvebu/patches-4.14/110-pxa3xxx_revert_irq_thread.patch +++ /dev/null @@ -1,69 +0,0 @@ -Revert "mtd: pxa3xx-nand: handle PIO in threaded interrupt" - -This reverts commit 24542257a3b987025d4b998ec2d15e556c98ad3f -This upstream change has been causing spurious timeouts on accesses -to the NAND flash if something else on the system is causing -significant latency. - -Nothing guarantees that the thread will run in time, so the -usual timeout is unreliable. - -Signed-off-by: Felix Fietkau - ---- a/drivers/mtd/nand/pxa3xx_nand.c -+++ b/drivers/mtd/nand/pxa3xx_nand.c -@@ -791,24 +791,11 @@ static void start_data_dma(struct pxa3xx - __func__, direction, info->dma_cookie, info->sg.length); - } - --static irqreturn_t pxa3xx_nand_irq_thread(int irq, void *data) --{ -- struct pxa3xx_nand_info *info = data; -- -- handle_data_pio(info); -- -- info->state = STATE_CMD_DONE; -- nand_writel(info, NDSR, NDSR_WRDREQ | NDSR_RDDREQ); -- -- return IRQ_HANDLED; --} -- - static irqreturn_t pxa3xx_nand_irq(int irq, void *devid) - { - struct pxa3xx_nand_info *info = devid; - unsigned int status, is_completed = 0, is_ready = 0; - unsigned int ready, cmd_done; -- irqreturn_t ret = IRQ_HANDLED; - - if (info->cs == 0) { - ready = NDSR_FLASH_RDY; -@@ -850,8 +837,7 @@ static irqreturn_t pxa3xx_nand_irq(int i - } else { - info->state = (status & NDSR_RDDREQ) ? - STATE_PIO_READING : STATE_PIO_WRITING; -- ret = IRQ_WAKE_THREAD; -- goto NORMAL_IRQ_EXIT; -+ handle_data_pio(info); - } - } - if (status & cmd_done) { -@@ -896,7 +882,7 @@ static irqreturn_t pxa3xx_nand_irq(int i - if (is_ready) - complete(&info->dev_ready); - NORMAL_IRQ_EXIT: -- return ret; -+ return IRQ_HANDLED; - } - - static inline int is_buf_blank(uint8_t *buf, size_t len) -@@ -1865,9 +1851,7 @@ static int alloc_nand_resource(struct pl - /* initialize all interrupts to be disabled */ - disable_int(info, NDSR_MASK); - -- ret = request_threaded_irq(irq, pxa3xx_nand_irq, -- pxa3xx_nand_irq_thread, IRQF_ONESHOT, -- pdev->name, info); -+ ret = request_irq(irq, pxa3xx_nand_irq, 0, pdev->name, info); - if (ret < 0) { - dev_err(&pdev->dev, "failed to request IRQ: %d\n", ret); - goto fail_free_buf; diff --git a/target/linux/mvebu/patches-4.14/205-armada-385-rd-mtd-partitions.patch b/target/linux/mvebu/patches-4.14/205-armada-385-rd-mtd-partitions.patch deleted file mode 100644 index e75a5eebda5f..000000000000 --- a/target/linux/mvebu/patches-4.14/205-armada-385-rd-mtd-partitions.patch +++ /dev/null @@ -1,19 +0,0 @@ ---- a/arch/arm/boot/dts/armada-388-rd.dts -+++ b/arch/arm/boot/dts/armada-388-rd.dts -@@ -140,6 +140,16 @@ - compatible = "st,m25p128", "jedec,spi-nor"; - reg = <0>; /* Chip select 0 */ - spi-max-frequency = <108000000>; -+ -+ partition@0 { -+ label = "uboot"; -+ reg = <0 0x400000>; -+ }; -+ -+ partition@1 { -+ label = "firmware"; -+ reg = <0x400000 0xc00000>; -+ }; - }; - }; - diff --git a/target/linux/mvebu/patches-4.14/206-ARM-mvebu-385-ap-Add-partitions.patch b/target/linux/mvebu/patches-4.14/206-ARM-mvebu-385-ap-Add-partitions.patch deleted file mode 100644 index b7af272360b2..000000000000 --- a/target/linux/mvebu/patches-4.14/206-ARM-mvebu-385-ap-Add-partitions.patch +++ /dev/null @@ -1,35 +0,0 @@ -From 9861f93a59142a3131870df2521eb2deb73026d7 Mon Sep 17 00:00:00 2001 -From: Maxime Ripard -Date: Tue, 13 Jan 2015 11:14:09 +0100 -Subject: [PATCH 2/2] ARM: mvebu: 385-ap: Add partitions - -Signed-off-by: Maxime Ripard ---- - arch/arm/boot/dts/armada-385-db-ap.dts | 15 +++++++++++++++ - 1 file changed, 15 insertions(+) - ---- a/arch/arm/boot/dts/armada-385-db-ap.dts -+++ b/arch/arm/boot/dts/armada-385-db-ap.dts -@@ -181,19 +181,19 @@ - #size-cells = <1>; - - partition@0 { -- label = "U-Boot"; -+ label = "u-boot"; - reg = <0x00000000 0x00800000>; - read-only; - }; - - partition@800000 { -- label = "uImage"; -+ label = "kernel"; - reg = <0x00800000 0x00400000>; - read-only; - }; - - partition@c00000 { -- label = "Root"; -+ label = "ubi"; - reg = <0x00c00000 0x3f400000>; - }; - }; diff --git a/target/linux/mvebu/patches-4.14/210-clearfog_switch_node.patch b/target/linux/mvebu/patches-4.14/210-clearfog_switch_node.patch deleted file mode 100644 index e880cc13e7bd..000000000000 --- a/target/linux/mvebu/patches-4.14/210-clearfog_switch_node.patch +++ /dev/null @@ -1,21 +0,0 @@ ---- a/arch/arm/boot/dts/armada-388-clearfog.dts -+++ b/arch/arm/boot/dts/armada-388-clearfog.dts -@@ -129,6 +129,18 @@ - }; - }; - -+ mvsw61xx { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ compatible = "marvell,88e6176"; -+ status = "okay"; -+ reg = <0x4>; -+ is-indirect; -+ -+ mii-bus = <&mdio>; -+ cpu-port-0 = <5>; -+ }; -+ - gpio-keys { - compatible = "gpio-keys"; - pinctrl-0 = <&rear_button_pins>; diff --git a/target/linux/mvebu/patches-4.14/220-disable-untested-dsa-boards.patch b/target/linux/mvebu/patches-4.14/220-disable-untested-dsa-boards.patch deleted file mode 100644 index 5df94bdfad4d..000000000000 --- a/target/linux/mvebu/patches-4.14/220-disable-untested-dsa-boards.patch +++ /dev/null @@ -1,30 +0,0 @@ ---- a/arch/arm/boot/dts/armada-385-linksys.dtsi -+++ b/arch/arm/boot/dts/armada-385-linksys.dtsi -@@ -196,6 +196,7 @@ - status = "okay"; - - switch@0 { -+ status = "disabled"; - compatible = "marvell,mv88e6085"; - #address-cells = <1>; - #size-cells = <0>; ---- a/arch/arm/boot/dts/armada-388-clearfog.dts -+++ b/arch/arm/boot/dts/armada-388-clearfog.dts -@@ -202,6 +202,7 @@ - status = "okay"; - - switch@4 { -+ status = "disabled"; - compatible = "marvell,mv88e6085"; - #address-cells = <1>; - #size-cells = <0>; ---- a/arch/arm/boot/dts/armada-xp-linksys-mamba.dts -+++ b/arch/arm/boot/dts/armada-xp-linksys-mamba.dts -@@ -516,6 +516,7 @@ - status = "okay"; - - switch@0 { -+ status = "disabled"; - compatible = "marvell,mv88e6085"; - #address-cells = <1>; - #size-cells = <0>; diff --git a/target/linux/mvebu/patches-4.14/230-armada-xp-linksys-mamba-broken-idle.patch b/target/linux/mvebu/patches-4.14/230-armada-xp-linksys-mamba-broken-idle.patch deleted file mode 100644 index e82a899a7578..000000000000 --- a/target/linux/mvebu/patches-4.14/230-armada-xp-linksys-mamba-broken-idle.patch +++ /dev/null @@ -1,10 +0,0 @@ ---- a/arch/arm/boot/dts/armada-xp-linksys-mamba.dts -+++ b/arch/arm/boot/dts/armada-xp-linksys-mamba.dts -@@ -563,3 +563,7 @@ - }; - }; - }; -+ -+&coherencyfab { -+ broken-idle; -+}; diff --git a/target/linux/mvebu/patches-4.14/300-mvneta-tx-queue-workaround.patch b/target/linux/mvebu/patches-4.14/300-mvneta-tx-queue-workaround.patch deleted file mode 100644 index f21f8083ee19..000000000000 --- a/target/linux/mvebu/patches-4.14/300-mvneta-tx-queue-workaround.patch +++ /dev/null @@ -1,35 +0,0 @@ -The hardware queue scheduling is apparently configured with fixed -priorities, which creates a nasty fairness issue where traffic from one -CPU can starve traffic from all other CPUs. - -Work around this issue by forcing all tx packets to go through one CPU, -until this issue is fixed properly. - -Signed-off-by: Felix Fietkau ---- ---- a/drivers/net/ethernet/marvell/mvneta.c -+++ b/drivers/net/ethernet/marvell/mvneta.c -@@ -3961,6 +3961,15 @@ static int mvneta_ethtool_set_wol(struct - return ret; - } - -+static u16 mvneta_select_queue(struct net_device *dev, struct sk_buff *skb, -+ void *accel_priv, -+ select_queue_fallback_t fallback) -+{ -+ /* XXX: hardware queue scheduling is broken, -+ * use only one queue until it is fixed */ -+ return 0; -+} -+ - static const struct net_device_ops mvneta_netdev_ops = { - .ndo_open = mvneta_open, - .ndo_stop = mvneta_stop, -@@ -3971,6 +3980,7 @@ static const struct net_device_ops mvnet - .ndo_fix_features = mvneta_fix_features, - .ndo_get_stats64 = mvneta_get_stats64, - .ndo_do_ioctl = mvneta_ioctl, -+ .ndo_select_queue = mvneta_select_queue, - }; - - static const struct ethtool_ops mvneta_eth_tool_ops = { diff --git a/target/linux/mvebu/patches-4.14/400-cpuidle-mvebu-indicate-failure-to-enter-deeper-sleep.patch b/target/linux/mvebu/patches-4.14/400-cpuidle-mvebu-indicate-failure-to-enter-deeper-sleep.patch deleted file mode 100644 index 29f36be460d2..000000000000 --- a/target/linux/mvebu/patches-4.14/400-cpuidle-mvebu-indicate-failure-to-enter-deeper-sleep.patch +++ /dev/null @@ -1,40 +0,0 @@ -From c28b2d367da8a471482e6a4aa8337ab6369a80c2 Mon Sep 17 00:00:00 2001 -From: Russell King -Date: Sat, 3 Oct 2015 09:13:05 +0100 -Subject: cpuidle: mvebu: indicate failure to enter deeper sleep states - -The cpuidle ->enter method expects the return value to be the sleep -state we entered. Returning negative numbers or other codes is not -permissible since coupled CPU idle was merged. - -At least some of the mvebu_v7_cpu_suspend() implementations return the -value from cpu_suspend(), which returns zero if the CPU vectors back -into the kernel via cpu_resume() (the success case), or the non-zero -return value of the suspend actor, or one (failure cases). - -We do not want to be returning the failure case value back to CPU idle -as that indicates that we successfully entered one of the deeper idle -states. Always return zero instead, indicating that we slept for the -shortest amount of time. - -Signed-off-by: Russell King ---- - drivers/cpuidle/cpuidle-mvebu-v7.c | 6 +++++- - 1 file changed, 5 insertions(+), 1 deletion(-) - ---- a/drivers/cpuidle/cpuidle-mvebu-v7.c -+++ b/drivers/cpuidle/cpuidle-mvebu-v7.c -@@ -39,8 +39,12 @@ static int mvebu_v7_enter_idle(struct cp - ret = mvebu_v7_cpu_suspend(deepidle); - cpu_pm_exit(); - -+ /* -+ * If we failed to enter the desired state, indicate that we -+ * slept lightly. -+ */ - if (ret) -- return ret; -+ return 0; - - return index; - } diff --git a/target/linux/mvebu/patches-4.14/401-pci-mvebu-time-out-reset-on-link-up.patch b/target/linux/mvebu/patches-4.14/401-pci-mvebu-time-out-reset-on-link-up.patch deleted file mode 100644 index 504d11026404..000000000000 --- a/target/linux/mvebu/patches-4.14/401-pci-mvebu-time-out-reset-on-link-up.patch +++ /dev/null @@ -1,60 +0,0 @@ -From 287b9df160b6159f8d385424904f8bac501280c1 Mon Sep 17 00:00:00 2001 -From: Russell King -Date: Sat, 9 Jul 2016 10:58:16 +0100 -Subject: pci: mvebu: time out reset on link up - -If the port reports that the link is up while we are resetting, there's -little point in waiting for the full duration. - -Signed-off-by: Russell King ---- - drivers/pci/host/pci-mvebu.c | 20 ++++++++++++++------ - 1 file changed, 14 insertions(+), 6 deletions(-) - ---- a/drivers/pci/host/pci-mvebu.c -+++ b/drivers/pci/host/pci-mvebu.c -@@ -1167,6 +1167,7 @@ static int mvebu_pcie_powerup(struct mve - - if (port->reset_gpio) { - u32 reset_udelay = PCI_PM_D3COLD_WAIT * 1000; -+ unsigned int i; - - of_property_read_u32(port->dn, "reset-delay-us", - &reset_udelay); -@@ -1174,7 +1175,13 @@ static int mvebu_pcie_powerup(struct mve - udelay(100); - - gpiod_set_value_cansleep(port->reset_gpio, 0); -- msleep(reset_udelay / 1000); -+ for (i = 0; i < reset_udelay; i += 1000) { -+ if (mvebu_pcie_link_up(port)) -+ break; -+ msleep(1); -+ } -+ -+ printk("%s: reset completed in %dus\n", port->name, i); - } - - return 0; -@@ -1261,15 +1268,16 @@ static int mvebu_pcie_probe(struct platf - if (!child) - continue; - -- ret = mvebu_pcie_powerup(port); -- if (ret < 0) -- continue; -- - port->base = mvebu_pcie_map_registers(pdev, child, port); - if (IS_ERR(port->base)) { - dev_err(dev, "%s: cannot map registers\n", port->name); - port->base = NULL; -- mvebu_pcie_powerdown(port); -+ continue; -+ } -+ -+ ret = mvebu_pcie_powerup(port); -+ if (ret < 0) { -+ port->base = NULL; - continue; - } - diff --git a/target/linux/mvebu/patches-4.14/402-sfp-display-SFP-module-information.patch b/target/linux/mvebu/patches-4.14/402-sfp-display-SFP-module-information.patch deleted file mode 100644 index c531c375a03f..000000000000 --- a/target/linux/mvebu/patches-4.14/402-sfp-display-SFP-module-information.patch +++ /dev/null @@ -1,290 +0,0 @@ -From e76632d118659347d9261a4470d9f60bfbe0044c Mon Sep 17 00:00:00 2001 -From: Russell King -Date: Sun, 13 Sep 2015 01:06:31 +0100 -Subject: sfp: display SFP module information - -Signed-off-by: Russell King ---- - drivers/net/phy/sfp.c | 254 +++++++++++++++++++++++++++++++++++++++++++++++++- - 1 file changed, 253 insertions(+), 1 deletion(-) - ---- a/drivers/net/phy/sfp.c -+++ b/drivers/net/phy/sfp.c -@@ -265,6 +265,184 @@ static unsigned int sfp_check(void *buf, - return check; - } - -+static const char *sfp_link_len(char *buf, size_t size, unsigned int length, -+ unsigned int multiplier) -+{ -+ if (length == 0) -+ return "unsupported/unspecified"; -+ -+ if (length == 255) { -+ *buf++ = '>'; -+ size -= 1; -+ length -= 1; -+ } -+ -+ length *= multiplier; -+ -+ if (length >= 1000) -+ snprintf(buf, size, "%u.%0*ukm", -+ length / 1000, -+ multiplier > 100 ? 1 : -+ multiplier > 10 ? 2 : 3, -+ length % 1000); -+ else -+ snprintf(buf, size, "%um", length); -+ -+ return buf; -+} -+ -+struct bitfield { -+ unsigned int mask; -+ unsigned int val; -+ const char *str; -+}; -+ -+static const struct bitfield sfp_options[] = { -+ { -+ .mask = SFP_OPTIONS_HIGH_POWER_LEVEL, -+ .val = SFP_OPTIONS_HIGH_POWER_LEVEL, -+ .str = "hpl", -+ }, { -+ .mask = SFP_OPTIONS_PAGING_A2, -+ .val = SFP_OPTIONS_PAGING_A2, -+ .str = "paginga2", -+ }, { -+ .mask = SFP_OPTIONS_RETIMER, -+ .val = SFP_OPTIONS_RETIMER, -+ .str = "retimer", -+ }, { -+ .mask = SFP_OPTIONS_COOLED_XCVR, -+ .val = SFP_OPTIONS_COOLED_XCVR, -+ .str = "cooled", -+ }, { -+ .mask = SFP_OPTIONS_POWER_DECL, -+ .val = SFP_OPTIONS_POWER_DECL, -+ .str = "powerdecl", -+ }, { -+ .mask = SFP_OPTIONS_RX_LINEAR_OUT, -+ .val = SFP_OPTIONS_RX_LINEAR_OUT, -+ .str = "rxlinear", -+ }, { -+ .mask = SFP_OPTIONS_RX_DECISION_THRESH, -+ .val = SFP_OPTIONS_RX_DECISION_THRESH, -+ .str = "rxthresh", -+ }, { -+ .mask = SFP_OPTIONS_TUNABLE_TX, -+ .val = SFP_OPTIONS_TUNABLE_TX, -+ .str = "tunabletx", -+ }, { -+ .mask = SFP_OPTIONS_RATE_SELECT, -+ .val = SFP_OPTIONS_RATE_SELECT, -+ .str = "ratesel", -+ }, { -+ .mask = SFP_OPTIONS_TX_DISABLE, -+ .val = SFP_OPTIONS_TX_DISABLE, -+ .str = "txdisable", -+ }, { -+ .mask = SFP_OPTIONS_TX_FAULT, -+ .val = SFP_OPTIONS_TX_FAULT, -+ .str = "txfault", -+ }, { -+ .mask = SFP_OPTIONS_LOS_INVERTED, -+ .val = SFP_OPTIONS_LOS_INVERTED, -+ .str = "los-", -+ }, { -+ .mask = SFP_OPTIONS_LOS_NORMAL, -+ .val = SFP_OPTIONS_LOS_NORMAL, -+ .str = "los+", -+ }, { } -+}; -+ -+static const struct bitfield diagmon[] = { -+ { -+ .mask = SFP_DIAGMON_DDM, -+ .val = SFP_DIAGMON_DDM, -+ .str = "ddm", -+ }, { -+ .mask = SFP_DIAGMON_INT_CAL, -+ .val = SFP_DIAGMON_INT_CAL, -+ .str = "intcal", -+ }, { -+ .mask = SFP_DIAGMON_EXT_CAL, -+ .val = SFP_DIAGMON_EXT_CAL, -+ .str = "extcal", -+ }, { -+ .mask = SFP_DIAGMON_RXPWR_AVG, -+ .val = SFP_DIAGMON_RXPWR_AVG, -+ .str = "rxpwravg", -+ }, { } -+}; -+ -+static const char *sfp_bitfield(char *out, size_t outsz, const struct bitfield *bits, unsigned int val) -+{ -+ char *p = out; -+ int n; -+ -+ *p = '\0'; -+ while (bits->mask) { -+ if ((val & bits->mask) == bits->val) { -+ n = snprintf(p, outsz, "%s%s", -+ out != p ? ", " : "", -+ bits->str); -+ if (n == outsz) -+ break; -+ p += n; -+ outsz -= n; -+ } -+ bits++; -+ } -+ -+ return out; -+} -+ -+static const char *sfp_connector(unsigned int connector) -+{ -+ switch (connector) { -+ case SFP_CONNECTOR_UNSPEC: -+ return "unknown/unspecified"; -+ case SFP_CONNECTOR_SC: -+ return "SC"; -+ case SFP_CONNECTOR_FIBERJACK: -+ return "Fiberjack"; -+ case SFP_CONNECTOR_LC: -+ return "LC"; -+ case SFP_CONNECTOR_MT_RJ: -+ return "MT-RJ"; -+ case SFP_CONNECTOR_MU: -+ return "MU"; -+ case SFP_CONNECTOR_SG: -+ return "SG"; -+ case SFP_CONNECTOR_OPTICAL_PIGTAIL: -+ return "Optical pigtail"; -+ case SFP_CONNECTOR_HSSDC_II: -+ return "HSSDC II"; -+ case SFP_CONNECTOR_COPPER_PIGTAIL: -+ return "Copper pigtail"; -+ default: -+ return "unknown"; -+ } -+} -+ -+static const char *sfp_encoding(unsigned int encoding) -+{ -+ switch (encoding) { -+ case SFP_ENCODING_UNSPEC: -+ return "unspecified"; -+ case SFP_ENCODING_8472_64B66B: -+ return "64b66b"; -+ case SFP_ENCODING_8B10B: -+ return "8b10b"; -+ case SFP_ENCODING_4B5B: -+ return "4b5b"; -+ case SFP_ENCODING_NRZ: -+ return "NRZ"; -+ case SFP_ENCODING_8472_MANCHESTER: -+ return "MANCHESTER"; -+ default: -+ return "unknown"; -+ } -+} -+ - /* Helpers */ - static void sfp_module_tx_disable(struct sfp *sfp) - { -@@ -433,6 +611,7 @@ static int sfp_sm_mod_probe(struct sfp * - char sn[17]; - char date[9]; - char rev[5]; -+ char options[80]; - u8 check; - int err; - -@@ -476,10 +655,83 @@ static int sfp_sm_mod_probe(struct sfp * - rev[4] = '\0'; - memcpy(sn, sfp->id.ext.vendor_sn, 16); - sn[16] = '\0'; -- memcpy(date, sfp->id.ext.datecode, 8); -+ date[0] = sfp->id.ext.datecode[4]; -+ date[1] = sfp->id.ext.datecode[5]; -+ date[2] = '-'; -+ date[3] = sfp->id.ext.datecode[2]; -+ date[4] = sfp->id.ext.datecode[3]; -+ date[5] = '-'; -+ date[6] = sfp->id.ext.datecode[0]; -+ date[7] = sfp->id.ext.datecode[1]; - date[8] = '\0'; - - dev_info(sfp->dev, "module %s %s rev %s sn %s dc %s\n", vendor, part, rev, sn, date); -+ dev_info(sfp->dev, " %s connector, encoding %s, nominal bitrate %u.%uGbps +%u%% -%u%%\n", -+ sfp_connector(sfp->id.base.connector), -+ sfp_encoding(sfp->id.base.encoding), -+ sfp->id.base.br_nominal / 10, -+ sfp->id.base.br_nominal % 10, -+ sfp->id.ext.br_max, sfp->id.ext.br_min); -+ dev_info(sfp->dev, " 1000BaseSX%c 1000BaseLX%c 1000BaseCX%c 1000BaseT%c 100BaseTLX%c 1000BaseFX%c BaseBX10%c BasePX%c\n", -+ sfp->id.base.e1000_base_sx ? '+' : '-', -+ sfp->id.base.e1000_base_lx ? '+' : '-', -+ sfp->id.base.e1000_base_cx ? '+' : '-', -+ sfp->id.base.e1000_base_t ? '+' : '-', -+ sfp->id.base.e100_base_lx ? '+' : '-', -+ sfp->id.base.e100_base_fx ? '+' : '-', -+ sfp->id.base.e_base_bx10 ? '+' : '-', -+ sfp->id.base.e_base_px ? '+' : '-'); -+ dev_info(sfp->dev, " 10GBaseSR%c 10GBaseLR%c 10GBaseLRM%c 10GBaseER%c\n", -+ sfp->id.base.e10g_base_sr ? '+' : '-', -+ sfp->id.base.e10g_base_lr ? '+' : '-', -+ sfp->id.base.e10g_base_lrm ? '+' : '-', -+ sfp->id.base.e10g_base_er ? '+' : '-'); -+ -+ if (!sfp->id.base.sfp_ct_passive && !sfp->id.base.sfp_ct_active && -+ !sfp->id.base.e1000_base_t) { -+ char len_9um[16], len_om[16]; -+ -+ dev_info(sfp->dev, " Wavelength %unm, fiber lengths:\n", -+ be16_to_cpup(&sfp->id.base.optical_wavelength)); -+ -+ if (sfp->id.base.link_len[0] == 255) -+ strcpy(len_9um, ">254km"); -+ else if (sfp->id.base.link_len[1] && sfp->id.base.link_len[1] != 255) -+ sprintf(len_9um, "%um", -+ sfp->id.base.link_len[1] * 100); -+ else if (sfp->id.base.link_len[0]) -+ sprintf(len_9um, "%ukm", sfp->id.base.link_len[0]); -+ else if (sfp->id.base.link_len[1] == 255) -+ strcpy(len_9um, ">25.4km"); -+ else -+ strcpy(len_9um, "unsupported"); -+ -+ dev_info(sfp->dev, " 9µm SM : %s\n", len_9um); -+ dev_info(sfp->dev, " 62.5µm MM OM1: %s\n", -+ sfp_link_len(len_om, sizeof(len_om), -+ sfp->id.base.link_len[3], 10)); -+ dev_info(sfp->dev, " 50µm MM OM2: %s\n", -+ sfp_link_len(len_om, sizeof(len_om), -+ sfp->id.base.link_len[2], 10)); -+ dev_info(sfp->dev, " 50µm MM OM3: %s\n", -+ sfp_link_len(len_om, sizeof(len_om), -+ sfp->id.base.link_len[5], 10)); -+ dev_info(sfp->dev, " 50µm MM OM4: %s\n", -+ sfp_link_len(len_om, sizeof(len_om), -+ sfp->id.base.link_len[4], 10)); -+ } else { -+ char len[16]; -+ dev_info(sfp->dev, " Copper length: %s\n", -+ sfp_link_len(len, sizeof(len), -+ sfp->id.base.link_len[4], 1)); -+ } -+ -+ dev_info(sfp->dev, " Options: %s\n", -+ sfp_bitfield(options, sizeof(options), sfp_options, -+ be16_to_cpu(sfp->id.ext.options))); -+ dev_info(sfp->dev, " Diagnostics: %s\n", -+ sfp_bitfield(options, sizeof(options), diagmon, -+ sfp->id.ext.diagmon)); - - /* We only support SFP modules, not the legacy GBIC modules. */ - if (sfp->id.base.phys_id != SFP_PHYS_ID_SFP || diff --git a/target/linux/mvebu/patches-4.14/403-net-mvneta-convert-to-phylink.patch b/target/linux/mvebu/patches-4.14/403-net-mvneta-convert-to-phylink.patch deleted file mode 100644 index 34a2d342dbe7..000000000000 --- a/target/linux/mvebu/patches-4.14/403-net-mvneta-convert-to-phylink.patch +++ /dev/null @@ -1,979 +0,0 @@ -From 36f29e6cf8071fed3854d9825217ed2a3c83b990 Mon Sep 17 00:00:00 2001 -From: Russell King -Date: Wed, 16 Sep 2015 21:27:10 +0100 -Subject: net: mvneta: convert to phylink - -Convert mvneta to use phylink, which models the MAC to PHY link in -a generic, reusable form. - -Signed-off-by: Russell King - -- remove unused sync status ---- - drivers/net/ethernet/marvell/Kconfig | 2 +- - drivers/net/ethernet/marvell/mvneta.c | 594 ++++++++++++++++++++-------------- - 2 files changed, 349 insertions(+), 247 deletions(-) - ---- a/drivers/net/ethernet/marvell/Kconfig -+++ b/drivers/net/ethernet/marvell/Kconfig -@@ -60,7 +60,7 @@ config MVNETA - depends on ARCH_MVEBU || COMPILE_TEST - depends on HAS_DMA - select MVMDIO -- select FIXED_PHY -+ select PHYLINK - ---help--- - This driver supports the network interface units in the - Marvell ARMADA XP, ARMADA 370, ARMADA 38x and ---- a/drivers/net/ethernet/marvell/mvneta.c -+++ b/drivers/net/ethernet/marvell/mvneta.c -@@ -28,7 +28,7 @@ - #include - #include - #include --#include -+#include - #include - #include - #include -@@ -189,6 +189,7 @@ - #define MVNETA_GMAC_CTRL_0 0x2c00 - #define MVNETA_GMAC_MAX_RX_SIZE_SHIFT 2 - #define MVNETA_GMAC_MAX_RX_SIZE_MASK 0x7ffc -+#define MVNETA_GMAC0_PORT_1000BASE_X BIT(1) - #define MVNETA_GMAC0_PORT_ENABLE BIT(0) - #define MVNETA_GMAC_CTRL_2 0x2c08 - #define MVNETA_GMAC2_INBAND_AN_ENABLE BIT(0) -@@ -204,13 +205,19 @@ - #define MVNETA_GMAC_TX_FLOW_CTRL_ENABLE BIT(5) - #define MVNETA_GMAC_RX_FLOW_CTRL_ACTIVE BIT(6) - #define MVNETA_GMAC_TX_FLOW_CTRL_ACTIVE BIT(7) -+#define MVNETA_GMAC_AN_COMPLETE BIT(11) -+#define MVNETA_GMAC_SYNC_OK BIT(14) - #define MVNETA_GMAC_AUTONEG_CONFIG 0x2c0c - #define MVNETA_GMAC_FORCE_LINK_DOWN BIT(0) - #define MVNETA_GMAC_FORCE_LINK_PASS BIT(1) - #define MVNETA_GMAC_INBAND_AN_ENABLE BIT(2) -+#define MVNETA_GMAC_AN_BYPASS_ENABLE BIT(3) -+#define MVNETA_GMAC_INBAND_RESTART_AN BIT(4) - #define MVNETA_GMAC_CONFIG_MII_SPEED BIT(5) - #define MVNETA_GMAC_CONFIG_GMII_SPEED BIT(6) - #define MVNETA_GMAC_AN_SPEED_EN BIT(7) -+#define MVNETA_GMAC_CONFIG_FLOW_CTRL BIT(8) -+#define MVNETA_GMAC_ADVERT_SYM_FLOW_CTRL BIT(9) - #define MVNETA_GMAC_AN_FLOW_CTRL_EN BIT(11) - #define MVNETA_GMAC_CONFIG_FULL_DUPLEX BIT(12) - #define MVNETA_GMAC_AN_DUPLEX_EN BIT(13) -@@ -237,6 +244,12 @@ - #define MVNETA_TXQ_TOKEN_SIZE_REG(q) (0x3e40 + ((q) << 2)) - #define MVNETA_TXQ_TOKEN_SIZE_MAX 0x7fffffff - -+#define MVNETA_LPI_CTRL_0 0x2cc0 -+#define MVNETA_LPI_CTRL_1 0x2cc4 -+#define MVNETA_LPI_REQUEST_ENABLE BIT(0) -+#define MVNETA_LPI_CTRL_2 0x2cc8 -+#define MVNETA_LPI_STATUS 0x2ccc -+ - #define MVNETA_CAUSE_TXQ_SENT_DESC_ALL_MASK 0xff - - /* Descriptor ring Macros */ -@@ -313,6 +326,11 @@ - #define MVNETA_RX_GET_BM_POOL_ID(rxd) \ - (((rxd)->status & MVNETA_RXD_BM_POOL_MASK) >> MVNETA_RXD_BM_POOL_SHIFT) - -+enum { -+ ETHTOOL_STAT_EEE_WAKEUP, -+ ETHTOOL_MAX_STATS, -+}; -+ - struct mvneta_statistic { - unsigned short offset; - unsigned short type; -@@ -321,6 +339,7 @@ struct mvneta_statistic { - - #define T_REG_32 32 - #define T_REG_64 64 -+#define T_SW 1 - - static const struct mvneta_statistic mvneta_statistics[] = { - { 0x3000, T_REG_64, "good_octets_received", }, -@@ -355,6 +374,7 @@ static const struct mvneta_statistic mvn - { 0x304c, T_REG_32, "broadcast_frames_sent", }, - { 0x3054, T_REG_32, "fc_sent", }, - { 0x300c, T_REG_32, "internal_mac_transmit_err", }, -+ { ETHTOOL_STAT_EEE_WAKEUP, T_SW, "eee_wakeup_errors", }, - }; - - struct mvneta_pcpu_stats { -@@ -407,20 +427,19 @@ struct mvneta_port { - u16 tx_ring_size; - u16 rx_ring_size; - -- struct mii_bus *mii_bus; -- phy_interface_t phy_interface; -- struct device_node *phy_node; -- unsigned int link; -- unsigned int duplex; -- unsigned int speed; -+ struct device_node *dn; - unsigned int tx_csum_limit; -- unsigned int use_inband_status:1; -+ struct phylink *phylink; - - struct mvneta_bm *bm_priv; - struct mvneta_bm_pool *pool_long; - struct mvneta_bm_pool *pool_short; - int bm_win_id; - -+ bool eee_enabled; -+ bool eee_active; -+ bool tx_lpi_enabled; -+ - u64 ethtool_stats[ARRAY_SIZE(mvneta_statistics)]; - - u32 indir[MVNETA_RSS_LU_TABLE_SIZE]; -@@ -1215,10 +1234,6 @@ static void mvneta_port_disable(struct m - val &= ~MVNETA_GMAC0_PORT_ENABLE; - mvreg_write(pp, MVNETA_GMAC_CTRL_0, val); - -- pp->link = 0; -- pp->duplex = -1; -- pp->speed = 0; -- - udelay(200); - } - -@@ -1278,44 +1293,6 @@ static void mvneta_set_other_mcast_table - mvreg_write(pp, MVNETA_DA_FILT_OTH_MCAST + offset, val); - } - --static void mvneta_set_autoneg(struct mvneta_port *pp, int enable) --{ -- u32 val; -- -- if (enable) { -- val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG); -- val &= ~(MVNETA_GMAC_FORCE_LINK_PASS | -- MVNETA_GMAC_FORCE_LINK_DOWN | -- MVNETA_GMAC_AN_FLOW_CTRL_EN); -- val |= MVNETA_GMAC_INBAND_AN_ENABLE | -- MVNETA_GMAC_AN_SPEED_EN | -- MVNETA_GMAC_AN_DUPLEX_EN; -- mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val); -- -- val = mvreg_read(pp, MVNETA_GMAC_CLOCK_DIVIDER); -- val |= MVNETA_GMAC_1MS_CLOCK_ENABLE; -- mvreg_write(pp, MVNETA_GMAC_CLOCK_DIVIDER, val); -- -- val = mvreg_read(pp, MVNETA_GMAC_CTRL_2); -- val |= MVNETA_GMAC2_INBAND_AN_ENABLE; -- mvreg_write(pp, MVNETA_GMAC_CTRL_2, val); -- } else { -- val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG); -- val &= ~(MVNETA_GMAC_INBAND_AN_ENABLE | -- MVNETA_GMAC_AN_SPEED_EN | -- MVNETA_GMAC_AN_DUPLEX_EN); -- mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val); -- -- val = mvreg_read(pp, MVNETA_GMAC_CLOCK_DIVIDER); -- val &= ~MVNETA_GMAC_1MS_CLOCK_ENABLE; -- mvreg_write(pp, MVNETA_GMAC_CLOCK_DIVIDER, val); -- -- val = mvreg_read(pp, MVNETA_GMAC_CTRL_2); -- val &= ~MVNETA_GMAC2_INBAND_AN_ENABLE; -- mvreg_write(pp, MVNETA_GMAC_CTRL_2, val); -- } --} -- - static void mvneta_percpu_unmask_interrupt(void *arg) - { - struct mvneta_port *pp = arg; -@@ -1468,7 +1445,6 @@ static void mvneta_defaults_set(struct m - val &= ~MVNETA_PHY_POLLING_ENABLE; - mvreg_write(pp, MVNETA_UNIT_CONTROL, val); - -- mvneta_set_autoneg(pp, pp->use_inband_status); - mvneta_set_ucast_table(pp, -1); - mvneta_set_special_mcast_table(pp, -1); - mvneta_set_other_mcast_table(pp, -1); -@@ -2693,26 +2669,11 @@ static irqreturn_t mvneta_percpu_isr(int - return IRQ_HANDLED; - } - --static int mvneta_fixed_link_update(struct mvneta_port *pp, -- struct phy_device *phy) -+static void mvneta_link_change(struct mvneta_port *pp) - { -- struct fixed_phy_status status; -- struct fixed_phy_status changed = {}; - u32 gmac_stat = mvreg_read(pp, MVNETA_GMAC_STATUS); - -- status.link = !!(gmac_stat & MVNETA_GMAC_LINK_UP); -- if (gmac_stat & MVNETA_GMAC_SPEED_1000) -- status.speed = SPEED_1000; -- else if (gmac_stat & MVNETA_GMAC_SPEED_100) -- status.speed = SPEED_100; -- else -- status.speed = SPEED_10; -- status.duplex = !!(gmac_stat & MVNETA_GMAC_FULL_DUPLEX); -- changed.link = 1; -- changed.speed = 1; -- changed.duplex = 1; -- fixed_phy_update_state(phy, &status, &changed); -- return 0; -+ phylink_mac_change(pp->phylink, !!(gmac_stat & MVNETA_GMAC_LINK_UP)); - } - - /* NAPI handler -@@ -2728,7 +2689,6 @@ static int mvneta_poll(struct napi_struc - u32 cause_rx_tx; - int rx_queue; - struct mvneta_port *pp = netdev_priv(napi->dev); -- struct net_device *ndev = pp->dev; - struct mvneta_pcpu_port *port = this_cpu_ptr(pp->ports); - - if (!netif_running(pp->dev)) { -@@ -2742,12 +2702,11 @@ static int mvneta_poll(struct napi_struc - u32 cause_misc = mvreg_read(pp, MVNETA_INTR_MISC_CAUSE); - - mvreg_write(pp, MVNETA_INTR_MISC_CAUSE, 0); -- if (pp->use_inband_status && (cause_misc & -- (MVNETA_CAUSE_PHY_STATUS_CHANGE | -- MVNETA_CAUSE_LINK_CHANGE | -- MVNETA_CAUSE_PSC_SYNC_CHANGE))) { -- mvneta_fixed_link_update(pp, ndev->phydev); -- } -+ -+ if (cause_misc & (MVNETA_CAUSE_PHY_STATUS_CHANGE | -+ MVNETA_CAUSE_LINK_CHANGE | -+ MVNETA_CAUSE_PSC_SYNC_CHANGE)) -+ mvneta_link_change(pp); - } - - /* Release Tx descriptors */ -@@ -3061,7 +3020,6 @@ static int mvneta_setup_txqs(struct mvne - static void mvneta_start_dev(struct mvneta_port *pp) - { - int cpu; -- struct net_device *ndev = pp->dev; - - mvneta_max_rx_size_set(pp, pp->pkt_size); - mvneta_txq_max_tx_size_set(pp, pp->pkt_size); -@@ -3089,16 +3047,15 @@ static void mvneta_start_dev(struct mvne - MVNETA_CAUSE_LINK_CHANGE | - MVNETA_CAUSE_PSC_SYNC_CHANGE); - -- phy_start(ndev->phydev); -+ phylink_start(pp->phylink); - netif_tx_start_all_queues(pp->dev); - } - - static void mvneta_stop_dev(struct mvneta_port *pp) - { - unsigned int cpu; -- struct net_device *ndev = pp->dev; - -- phy_stop(ndev->phydev); -+ phylink_stop(pp->phylink); - - if (!pp->neta_armada3700) { - for_each_online_cpu(cpu) { -@@ -3251,103 +3208,232 @@ static int mvneta_set_mac_addr(struct ne - return 0; - } - --static void mvneta_adjust_link(struct net_device *ndev) -+static void mvneta_validate(struct net_device *ndev, unsigned long *supported, -+ struct phylink_link_state *state) -+{ -+ __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; -+ -+ /* Allow all the expected bits */ -+ phylink_set(mask, Autoneg); -+ phylink_set_port_modes(mask); -+ -+ /* Asymmetric pause is unsupported */ -+ phylink_set(mask, Pause); -+ /* Half-duplex at speeds higher than 100Mbit is unsupported */ -+ phylink_set(mask, 1000baseT_Full); -+ phylink_set(mask, 1000baseX_Full); -+ -+ if (state->interface != PHY_INTERFACE_MODE_1000BASEX) { -+ /* 10M and 100M are only supported in non-802.3z mode */ -+ phylink_set(mask, 10baseT_Half); -+ phylink_set(mask, 10baseT_Full); -+ phylink_set(mask, 100baseT_Half); -+ phylink_set(mask, 100baseT_Full); -+ } -+ -+ bitmap_and(supported, supported, mask, -+ __ETHTOOL_LINK_MODE_MASK_NBITS); -+ bitmap_and(state->advertising, state->advertising, mask, -+ __ETHTOOL_LINK_MODE_MASK_NBITS); -+} -+ -+static int mvneta_mac_link_state(struct net_device *ndev, -+ struct phylink_link_state *state) - { - struct mvneta_port *pp = netdev_priv(ndev); -- struct phy_device *phydev = ndev->phydev; -- int status_change = 0; -+ u32 gmac_stat; - -- if (phydev->link) { -- if ((pp->speed != phydev->speed) || -- (pp->duplex != phydev->duplex)) { -- u32 val; -- -- val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG); -- val &= ~(MVNETA_GMAC_CONFIG_MII_SPEED | -- MVNETA_GMAC_CONFIG_GMII_SPEED | -- MVNETA_GMAC_CONFIG_FULL_DUPLEX); -- -- if (phydev->duplex) -- val |= MVNETA_GMAC_CONFIG_FULL_DUPLEX; -- -- if (phydev->speed == SPEED_1000) -- val |= MVNETA_GMAC_CONFIG_GMII_SPEED; -- else if (phydev->speed == SPEED_100) -- val |= MVNETA_GMAC_CONFIG_MII_SPEED; -+ gmac_stat = mvreg_read(pp, MVNETA_GMAC_STATUS); - -- mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val); -+ if (gmac_stat & MVNETA_GMAC_SPEED_1000) -+ state->speed = SPEED_1000; -+ else if (gmac_stat & MVNETA_GMAC_SPEED_100) -+ state->speed = SPEED_100; -+ else -+ state->speed = SPEED_10; - -- pp->duplex = phydev->duplex; -- pp->speed = phydev->speed; -- } -+ state->an_complete = !!(gmac_stat & MVNETA_GMAC_AN_COMPLETE); -+ state->link = !!(gmac_stat & MVNETA_GMAC_LINK_UP); -+ state->duplex = !!(gmac_stat & MVNETA_GMAC_FULL_DUPLEX); -+ -+ state->pause = 0; -+ if (gmac_stat & MVNETA_GMAC_RX_FLOW_CTRL_ENABLE) -+ state->pause |= MLO_PAUSE_RX; -+ if (gmac_stat & MVNETA_GMAC_TX_FLOW_CTRL_ENABLE) -+ state->pause |= MLO_PAUSE_TX; -+ -+ return 1; -+} -+ -+static void mvneta_mac_an_restart(struct net_device *ndev) -+{ -+ struct mvneta_port *pp = netdev_priv(ndev); -+ u32 gmac_an = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG); -+ -+ mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, -+ gmac_an | MVNETA_GMAC_INBAND_RESTART_AN); -+ mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, -+ gmac_an & ~MVNETA_GMAC_INBAND_RESTART_AN); -+} -+ -+static void mvneta_mac_config(struct net_device *ndev, unsigned int mode, -+ const struct phylink_link_state *state) -+{ -+ struct mvneta_port *pp = netdev_priv(ndev); -+ u32 new_ctrl0, gmac_ctrl0 = mvreg_read(pp, MVNETA_GMAC_CTRL_0); -+ u32 new_ctrl2, gmac_ctrl2 = mvreg_read(pp, MVNETA_GMAC_CTRL_2); -+ u32 new_clk, gmac_clk = mvreg_read(pp, MVNETA_GMAC_CLOCK_DIVIDER); -+ u32 new_an, gmac_an = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG); -+ -+ new_ctrl0 = gmac_ctrl0 & ~MVNETA_GMAC0_PORT_1000BASE_X; -+ new_ctrl2 = gmac_ctrl2 & ~MVNETA_GMAC2_INBAND_AN_ENABLE; -+ new_clk = gmac_clk & ~MVNETA_GMAC_1MS_CLOCK_ENABLE; -+ new_an = gmac_an & ~(MVNETA_GMAC_INBAND_AN_ENABLE | -+ MVNETA_GMAC_INBAND_RESTART_AN | -+ MVNETA_GMAC_CONFIG_MII_SPEED | -+ MVNETA_GMAC_CONFIG_GMII_SPEED | -+ MVNETA_GMAC_AN_SPEED_EN | -+ MVNETA_GMAC_ADVERT_SYM_FLOW_CTRL | -+ MVNETA_GMAC_CONFIG_FLOW_CTRL | -+ MVNETA_GMAC_AN_FLOW_CTRL_EN | -+ MVNETA_GMAC_CONFIG_FULL_DUPLEX | -+ MVNETA_GMAC_AN_DUPLEX_EN); -+ -+ if (phylink_test(state->advertising, Pause)) -+ new_an |= MVNETA_GMAC_ADVERT_SYM_FLOW_CTRL; -+ if (state->pause & MLO_PAUSE_TXRX_MASK) -+ new_an |= MVNETA_GMAC_CONFIG_FLOW_CTRL; -+ -+ if (!phylink_autoneg_inband(mode)) { -+ /* Phy or fixed speed */ -+ if (state->duplex) -+ new_an |= MVNETA_GMAC_CONFIG_FULL_DUPLEX; -+ -+ if (state->speed == SPEED_1000) -+ new_an |= MVNETA_GMAC_CONFIG_GMII_SPEED; -+ else if (state->speed == SPEED_100) -+ new_an |= MVNETA_GMAC_CONFIG_MII_SPEED; -+ } else if (state->interface == PHY_INTERFACE_MODE_SGMII) { -+ /* SGMII mode receives the state from the PHY */ -+ new_ctrl2 |= MVNETA_GMAC2_INBAND_AN_ENABLE; -+ new_clk |= MVNETA_GMAC_1MS_CLOCK_ENABLE; -+ new_an = (new_an & ~(MVNETA_GMAC_FORCE_LINK_DOWN | -+ MVNETA_GMAC_FORCE_LINK_PASS)) | -+ MVNETA_GMAC_INBAND_AN_ENABLE | -+ MVNETA_GMAC_AN_SPEED_EN | -+ MVNETA_GMAC_AN_DUPLEX_EN; -+ } else { -+ /* 802.3z negotiation - only 1000base-X */ -+ new_ctrl0 |= MVNETA_GMAC0_PORT_1000BASE_X; -+ new_clk |= MVNETA_GMAC_1MS_CLOCK_ENABLE; -+ new_an = (new_an & ~(MVNETA_GMAC_FORCE_LINK_DOWN | -+ MVNETA_GMAC_FORCE_LINK_PASS)) | -+ MVNETA_GMAC_INBAND_AN_ENABLE | -+ MVNETA_GMAC_CONFIG_GMII_SPEED | -+ /* The MAC only supports FD mode */ -+ MVNETA_GMAC_CONFIG_FULL_DUPLEX; -+ -+ if (state->pause & MLO_PAUSE_AN && state->an_enabled) -+ new_an |= MVNETA_GMAC_AN_FLOW_CTRL_EN; -+ } -+ -+ /* Armada 370 documentation says we can only change the port mode -+ * and in-band enable when the link is down, so force it down -+ * while making these changes. We also do this for GMAC_CTRL2 */ -+ if ((new_ctrl0 ^ gmac_ctrl0) & MVNETA_GMAC0_PORT_1000BASE_X || -+ (new_ctrl2 ^ gmac_ctrl2) & MVNETA_GMAC2_INBAND_AN_ENABLE || -+ (new_an ^ gmac_an) & MVNETA_GMAC_INBAND_AN_ENABLE) { -+ mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, -+ (gmac_an & ~MVNETA_GMAC_FORCE_LINK_PASS) | -+ MVNETA_GMAC_FORCE_LINK_DOWN); -+ } -+ -+ if (new_ctrl0 != gmac_ctrl0) -+ mvreg_write(pp, MVNETA_GMAC_CTRL_0, new_ctrl0); -+ if (new_ctrl2 != gmac_ctrl2) -+ mvreg_write(pp, MVNETA_GMAC_CTRL_2, new_ctrl2); -+ if (new_clk != gmac_clk) -+ mvreg_write(pp, MVNETA_GMAC_CLOCK_DIVIDER, new_clk); -+ if (new_an != gmac_an) -+ mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, new_an); -+} -+ -+static void mvneta_set_eee(struct mvneta_port *pp, bool enable) -+{ -+ u32 lpi_ctl1; -+ -+ lpi_ctl1 = mvreg_read(pp, MVNETA_LPI_CTRL_1); -+ if (enable) -+ lpi_ctl1 |= MVNETA_LPI_REQUEST_ENABLE; -+ else -+ lpi_ctl1 &= ~MVNETA_LPI_REQUEST_ENABLE; -+ mvreg_write(pp, MVNETA_LPI_CTRL_1, lpi_ctl1); -+} -+ -+static void mvneta_mac_link_down(struct net_device *ndev, unsigned int mode) -+{ -+ struct mvneta_port *pp = netdev_priv(ndev); -+ u32 val; -+ -+ mvneta_port_down(pp); -+ -+ if (!phylink_autoneg_inband(mode)) { -+ val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG); -+ val &= ~MVNETA_GMAC_FORCE_LINK_PASS; -+ val |= MVNETA_GMAC_FORCE_LINK_DOWN; -+ mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val); - } - -- if (phydev->link != pp->link) { -- if (!phydev->link) { -- pp->duplex = -1; -- pp->speed = 0; -- } -+ pp->eee_active = false; -+ mvneta_set_eee(pp, false); -+} -+ -+static void mvneta_mac_link_up(struct net_device *ndev, unsigned int mode, -+ struct phy_device *phy) -+{ -+ struct mvneta_port *pp = netdev_priv(ndev); -+ u32 val; - -- pp->link = phydev->link; -- status_change = 1; -+ if (!phylink_autoneg_inband(mode)) { -+ val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG); -+ val &= ~MVNETA_GMAC_FORCE_LINK_DOWN; -+ val |= MVNETA_GMAC_FORCE_LINK_PASS; -+ mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val); - } - -- if (status_change) { -- if (phydev->link) { -- if (!pp->use_inband_status) { -- u32 val = mvreg_read(pp, -- MVNETA_GMAC_AUTONEG_CONFIG); -- val &= ~MVNETA_GMAC_FORCE_LINK_DOWN; -- val |= MVNETA_GMAC_FORCE_LINK_PASS; -- mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, -- val); -- } -- mvneta_port_up(pp); -- } else { -- if (!pp->use_inband_status) { -- u32 val = mvreg_read(pp, -- MVNETA_GMAC_AUTONEG_CONFIG); -- val &= ~MVNETA_GMAC_FORCE_LINK_PASS; -- val |= MVNETA_GMAC_FORCE_LINK_DOWN; -- mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, -- val); -- } -- mvneta_port_down(pp); -- } -- phy_print_status(phydev); -+ mvneta_port_up(pp); -+ -+ if (phy && pp->eee_enabled) { -+ pp->eee_active = phy_init_eee(phy, 0) >= 0; -+ mvneta_set_eee(pp, pp->eee_active && pp->tx_lpi_enabled); - } - } - -+static const struct phylink_mac_ops mvneta_phylink_ops = { -+ .validate = mvneta_validate, -+ .mac_link_state = mvneta_mac_link_state, -+ .mac_an_restart = mvneta_mac_an_restart, -+ .mac_config = mvneta_mac_config, -+ .mac_link_down = mvneta_mac_link_down, -+ .mac_link_up = mvneta_mac_link_up, -+}; -+ - static int mvneta_mdio_probe(struct mvneta_port *pp) - { -- struct phy_device *phy_dev; - struct ethtool_wolinfo wol = { .cmd = ETHTOOL_GWOL }; -+ int err = phylink_of_phy_connect(pp->phylink, pp->dn); -+ if (err) -+ netdev_err(pp->dev, "could not attach PHY\n"); - -- phy_dev = of_phy_connect(pp->dev, pp->phy_node, mvneta_adjust_link, 0, -- pp->phy_interface); -- if (!phy_dev) { -- netdev_err(pp->dev, "could not find the PHY\n"); -- return -ENODEV; -- } -- -- phy_ethtool_get_wol(phy_dev, &wol); -+ phylink_ethtool_get_wol(pp->phylink, &wol); - device_set_wakeup_capable(&pp->dev->dev, !!wol.supported); - -- phy_dev->supported &= PHY_GBIT_FEATURES; -- phy_dev->advertising = phy_dev->supported; -- -- pp->link = 0; -- pp->duplex = 0; -- pp->speed = 0; -- -- return 0; -+ return err; - } - - static void mvneta_mdio_remove(struct mvneta_port *pp) - { -- struct net_device *ndev = pp->dev; -- -- phy_disconnect(ndev->phydev); -+ phylink_disconnect_phy(pp->phylink); - } - - /* Electing a CPU must be done in an atomic way: it should be done -@@ -3626,10 +3712,9 @@ static int mvneta_stop(struct net_device - - static int mvneta_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) - { -- if (!dev->phydev) -- return -ENOTSUPP; -+ struct mvneta_port *pp = netdev_priv(dev); - -- return phy_mii_ioctl(dev->phydev, ifr, cmd); -+ return phylink_mii_ioctl(pp->phylink, ifr, cmd); - } - - /* Ethtool methods */ -@@ -3640,44 +3725,25 @@ mvneta_ethtool_set_link_ksettings(struct - const struct ethtool_link_ksettings *cmd) - { - struct mvneta_port *pp = netdev_priv(ndev); -- struct phy_device *phydev = ndev->phydev; - -- if (!phydev) -- return -ENODEV; -- -- if ((cmd->base.autoneg == AUTONEG_ENABLE) != pp->use_inband_status) { -- u32 val; -- -- mvneta_set_autoneg(pp, cmd->base.autoneg == AUTONEG_ENABLE); -- -- if (cmd->base.autoneg == AUTONEG_DISABLE) { -- val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG); -- val &= ~(MVNETA_GMAC_CONFIG_MII_SPEED | -- MVNETA_GMAC_CONFIG_GMII_SPEED | -- MVNETA_GMAC_CONFIG_FULL_DUPLEX); -- -- if (phydev->duplex) -- val |= MVNETA_GMAC_CONFIG_FULL_DUPLEX; -+ return phylink_ethtool_ksettings_set(pp->phylink, cmd); -+} - -- if (phydev->speed == SPEED_1000) -- val |= MVNETA_GMAC_CONFIG_GMII_SPEED; -- else if (phydev->speed == SPEED_100) -- val |= MVNETA_GMAC_CONFIG_MII_SPEED; -+/* Get link ksettings for ethtools */ -+static int -+mvneta_ethtool_get_link_ksettings(struct net_device *ndev, -+ struct ethtool_link_ksettings *cmd) -+{ -+ struct mvneta_port *pp = netdev_priv(ndev); - -- mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val); -- } -+ return phylink_ethtool_ksettings_get(pp->phylink, cmd); -+} - -- pp->use_inband_status = (cmd->base.autoneg == AUTONEG_ENABLE); -- netdev_info(pp->dev, "autoneg status set to %i\n", -- pp->use_inband_status); -- -- if (netif_running(ndev)) { -- mvneta_port_down(pp); -- mvneta_port_up(pp); -- } -- } -+static int mvneta_ethtool_nway_reset(struct net_device *dev) -+{ -+ struct mvneta_port *pp = netdev_priv(dev); - -- return phy_ethtool_ksettings_set(ndev->phydev, cmd); -+ return phylink_ethtool_nway_reset(pp->phylink); - } - - /* Set interrupt coalescing for ethtools */ -@@ -3769,6 +3835,22 @@ static int mvneta_ethtool_set_ringparam( - return 0; - } - -+static void mvneta_ethtool_get_pauseparam(struct net_device *dev, -+ struct ethtool_pauseparam *pause) -+{ -+ struct mvneta_port *pp = netdev_priv(dev); -+ -+ phylink_ethtool_get_pauseparam(pp->phylink, pause); -+} -+ -+static int mvneta_ethtool_set_pauseparam(struct net_device *dev, -+ struct ethtool_pauseparam *pause) -+{ -+ struct mvneta_port *pp = netdev_priv(dev); -+ -+ return phylink_ethtool_set_pauseparam(pp->phylink, pause); -+} -+ - static void mvneta_ethtool_get_strings(struct net_device *netdev, u32 sset, - u8 *data) - { -@@ -3785,26 +3867,35 @@ static void mvneta_ethtool_update_stats( - { - const struct mvneta_statistic *s; - void __iomem *base = pp->base; -- u32 high, low, val; -- u64 val64; -+ u32 high, low; -+ u64 val; - int i; - - for (i = 0, s = mvneta_statistics; - s < mvneta_statistics + ARRAY_SIZE(mvneta_statistics); - s++, i++) { -+ val = 0; -+ - switch (s->type) { - case T_REG_32: - val = readl_relaxed(base + s->offset); -- pp->ethtool_stats[i] += val; - break; - case T_REG_64: - /* Docs say to read low 32-bit then high */ - low = readl_relaxed(base + s->offset); - high = readl_relaxed(base + s->offset + 4); -- val64 = (u64)high << 32 | low; -- pp->ethtool_stats[i] += val64; -+ val = (u64)high << 32 | low; -+ break; -+ case T_SW: -+ switch (s->offset) { -+ case ETHTOOL_STAT_EEE_WAKEUP: -+ val = phylink_get_eee_err(pp->phylink); -+ break; -+ } - break; - } -+ -+ pp->ethtool_stats[i] += val; - } - } - -@@ -3939,28 +4030,65 @@ static int mvneta_ethtool_get_rxfh(struc - static void mvneta_ethtool_get_wol(struct net_device *dev, - struct ethtool_wolinfo *wol) - { -- wol->supported = 0; -- wol->wolopts = 0; -+ struct mvneta_port *pp = netdev_priv(dev); - -- if (dev->phydev) -- phy_ethtool_get_wol(dev->phydev, wol); -+ phylink_ethtool_get_wol(pp->phylink, wol); - } - - static int mvneta_ethtool_set_wol(struct net_device *dev, - struct ethtool_wolinfo *wol) - { -+ struct mvneta_port *pp = netdev_priv(dev); - int ret; - -- if (!dev->phydev) -- return -EOPNOTSUPP; -- -- ret = phy_ethtool_set_wol(dev->phydev, wol); -+ ret = phylink_ethtool_set_wol(pp->phylink, wol); - if (!ret) - device_set_wakeup_enable(&dev->dev, !!wol->wolopts); - - return ret; - } - -+static int mvneta_ethtool_get_eee(struct net_device *dev, -+ struct ethtool_eee *eee) -+{ -+ struct mvneta_port *pp = netdev_priv(dev); -+ u32 lpi_ctl0; -+ -+ lpi_ctl0 = mvreg_read(pp, MVNETA_LPI_CTRL_0); -+ -+ eee->eee_enabled = pp->eee_enabled; -+ eee->eee_active = pp->eee_active; -+ eee->tx_lpi_enabled = pp->tx_lpi_enabled; -+ eee->tx_lpi_timer = (lpi_ctl0) >> 8; // * scale; -+ -+ return phylink_ethtool_get_eee(pp->phylink, eee); -+} -+ -+static int mvneta_ethtool_set_eee(struct net_device *dev, -+ struct ethtool_eee *eee) -+{ -+ struct mvneta_port *pp = netdev_priv(dev); -+ u32 lpi_ctl0; -+ -+ /* The Armada 37x documents do not give limits for this other than -+ * it being an 8-bit register. */ -+ if (eee->tx_lpi_enabled && -+ (eee->tx_lpi_timer < 0 || eee->tx_lpi_timer > 255)) -+ return -EINVAL; -+ -+ lpi_ctl0 = mvreg_read(pp, MVNETA_LPI_CTRL_0); -+ lpi_ctl0 &= ~(0xff << 8); -+ lpi_ctl0 |= eee->tx_lpi_timer << 8; -+ mvreg_write(pp, MVNETA_LPI_CTRL_0, lpi_ctl0); -+ -+ pp->eee_enabled = eee->eee_enabled; -+ pp->tx_lpi_enabled = eee->tx_lpi_enabled; -+ -+ mvneta_set_eee(pp, eee->tx_lpi_enabled && eee->eee_enabled); -+ -+ return phylink_ethtool_set_eee(pp->phylink, eee); -+} -+ - static u16 mvneta_select_queue(struct net_device *dev, struct sk_buff *skb, - void *accel_priv, - select_queue_fallback_t fallback) -@@ -3984,13 +4112,15 @@ static const struct net_device_ops mvnet - }; - - static const struct ethtool_ops mvneta_eth_tool_ops = { -- .nway_reset = phy_ethtool_nway_reset, -+ .nway_reset = mvneta_ethtool_nway_reset, - .get_link = ethtool_op_get_link, - .set_coalesce = mvneta_ethtool_set_coalesce, - .get_coalesce = mvneta_ethtool_get_coalesce, - .get_drvinfo = mvneta_ethtool_get_drvinfo, - .get_ringparam = mvneta_ethtool_get_ringparam, - .set_ringparam = mvneta_ethtool_set_ringparam, -+ .get_pauseparam = mvneta_ethtool_get_pauseparam, -+ .set_pauseparam = mvneta_ethtool_set_pauseparam, - .get_strings = mvneta_ethtool_get_strings, - .get_ethtool_stats = mvneta_ethtool_get_stats, - .get_sset_count = mvneta_ethtool_get_sset_count, -@@ -3998,10 +4128,12 @@ static const struct ethtool_ops mvneta_e - .get_rxnfc = mvneta_ethtool_get_rxnfc, - .get_rxfh = mvneta_ethtool_get_rxfh, - .set_rxfh = mvneta_ethtool_set_rxfh, -- .get_link_ksettings = phy_ethtool_get_link_ksettings, -+ .get_link_ksettings = mvneta_ethtool_get_link_ksettings, - .set_link_ksettings = mvneta_ethtool_set_link_ksettings, - .get_wol = mvneta_ethtool_get_wol, - .set_wol = mvneta_ethtool_set_wol, -+ .get_eee = mvneta_ethtool_get_eee, -+ .set_eee = mvneta_ethtool_set_eee, - }; - - /* Initialize hw */ -@@ -4146,14 +4278,13 @@ static int mvneta_probe(struct platform_ - { - struct resource *res; - struct device_node *dn = pdev->dev.of_node; -- struct device_node *phy_node; - struct device_node *bm_node; - struct mvneta_port *pp; - struct net_device *dev; -+ struct phylink *phylink; - const char *dt_mac_addr; - char hw_mac_addr[ETH_ALEN]; - const char *mac_from; -- const char *managed; - int tx_csum_limit; - int phy_mode; - int err; -@@ -4169,31 +4300,11 @@ static int mvneta_probe(struct platform_ - goto err_free_netdev; - } - -- phy_node = of_parse_phandle(dn, "phy", 0); -- if (!phy_node) { -- if (!of_phy_is_fixed_link(dn)) { -- dev_err(&pdev->dev, "no PHY specified\n"); -- err = -ENODEV; -- goto err_free_irq; -- } -- -- err = of_phy_register_fixed_link(dn); -- if (err < 0) { -- dev_err(&pdev->dev, "cannot register fixed PHY\n"); -- goto err_free_irq; -- } -- -- /* In the case of a fixed PHY, the DT node associated -- * to the PHY is the Ethernet MAC DT node. -- */ -- phy_node = of_node_get(dn); -- } -- - phy_mode = of_get_phy_mode(dn); - if (phy_mode < 0) { - dev_err(&pdev->dev, "incorrect phy-mode\n"); - err = -EINVAL; -- goto err_put_phy_node; -+ goto err_free_irq; - } - - dev->tx_queue_len = MVNETA_MAX_TXD; -@@ -4204,12 +4315,7 @@ static int mvneta_probe(struct platform_ - - pp = netdev_priv(dev); - spin_lock_init(&pp->lock); -- pp->phy_node = phy_node; -- pp->phy_interface = phy_mode; -- -- err = of_property_read_string(dn, "managed", &managed); -- pp->use_inband_status = (err == 0 && -- strcmp(managed, "in-band-status") == 0); -+ pp->dn = dn; - - pp->rxq_def = rxq_def; - -@@ -4231,7 +4337,7 @@ static int mvneta_probe(struct platform_ - pp->clk = devm_clk_get(&pdev->dev, NULL); - if (IS_ERR(pp->clk)) { - err = PTR_ERR(pp->clk); -- goto err_put_phy_node; -+ goto err_free_irq; - } - - clk_prepare_enable(pp->clk); -@@ -4357,6 +4463,14 @@ static int mvneta_probe(struct platform_ - /* 9676 == 9700 - 20 and rounding to 8 */ - dev->max_mtu = 9676; - -+ phylink = phylink_create(dev, dn, phy_mode, &mvneta_phylink_ops); -+ if (IS_ERR(phylink)) { -+ err = PTR_ERR(phylink); -+ goto err_netdev; -+ } -+ -+ pp->phylink = phylink; -+ - err = register_netdev(dev); - if (err < 0) { - dev_err(&pdev->dev, "failed to register\n"); -@@ -4368,14 +4482,6 @@ static int mvneta_probe(struct platform_ - - platform_set_drvdata(pdev, pp->dev); - -- if (pp->use_inband_status) { -- struct phy_device *phy = of_phy_find_device(dn); -- -- mvneta_fixed_link_update(pp, phy); -- -- put_device(&phy->mdio.dev); -- } -- - return 0; - - err_netdev: -@@ -4384,16 +4490,14 @@ err_netdev: - mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_short, - 1 << pp->id); - } -+ if (pp->phylink) -+ phylink_destroy(pp->phylink); - free_percpu(pp->stats); - err_free_ports: - free_percpu(pp->ports); - err_clk: - clk_disable_unprepare(pp->clk_bus); - clk_disable_unprepare(pp->clk); --err_put_phy_node: -- of_node_put(phy_node); -- if (of_phy_is_fixed_link(dn)) -- of_phy_deregister_fixed_link(dn); - err_free_irq: - irq_dispose_mapping(dev->irq); - err_free_netdev: -@@ -4405,7 +4509,6 @@ err_free_netdev: - static int mvneta_remove(struct platform_device *pdev) - { - struct net_device *dev = platform_get_drvdata(pdev); -- struct device_node *dn = pdev->dev.of_node; - struct mvneta_port *pp = netdev_priv(dev); - - unregister_netdev(dev); -@@ -4413,10 +4516,8 @@ static int mvneta_remove(struct platform - clk_disable_unprepare(pp->clk); - free_percpu(pp->ports); - free_percpu(pp->stats); -- if (of_phy_is_fixed_link(dn)) -- of_phy_deregister_fixed_link(dn); - irq_dispose_mapping(dev->irq); -- of_node_put(pp->phy_node); -+ phylink_destroy(pp->phylink); - free_netdev(dev); - - if (pp->bm_priv) { -@@ -4468,9 +4569,6 @@ static int mvneta_resume(struct device * - return err; - } - -- if (pp->use_inband_status) -- mvneta_fixed_link_update(pp, dev->phydev); -- - netif_device_attach(dev); - if (netif_running(dev)) { - mvneta_open(dev); diff --git a/target/linux/mvebu/patches-4.14/404-net-mvneta-hack-fix-phy_interface.patch b/target/linux/mvebu/patches-4.14/404-net-mvneta-hack-fix-phy_interface.patch deleted file mode 100644 index 906c163ac9b8..000000000000 --- a/target/linux/mvebu/patches-4.14/404-net-mvneta-hack-fix-phy_interface.patch +++ /dev/null @@ -1,28 +0,0 @@ -From acdfcc7ef78c46baca1439a1cac5b73008abc672 Mon Sep 17 00:00:00 2001 -From: Russell King -Date: Tue, 16 May 2017 11:55:58 +0100 -Subject: net: mvneta: hack fix phy_interface - -Signed-off-by: Russell King ---- - drivers/net/ethernet/marvell/mvneta.c | 2 ++ - 1 file changed, 2 insertions(+) - ---- a/drivers/net/ethernet/marvell/mvneta.c -+++ b/drivers/net/ethernet/marvell/mvneta.c -@@ -427,6 +427,7 @@ struct mvneta_port { - u16 tx_ring_size; - u16 rx_ring_size; - -+ phy_interface_t phy_interface; - struct device_node *dn; - unsigned int tx_csum_limit; - struct phylink *phylink; -@@ -4315,6 +4316,7 @@ static int mvneta_probe(struct platform_ - - pp = netdev_priv(dev); - spin_lock_init(&pp->lock); -+ pp->phy_interface = phy_mode; - pp->dn = dn; - - pp->rxq_def = rxq_def; diff --git a/target/linux/mvebu/patches-4.14/405-net-mvneta-disable-MVNETA_CAUSE_PSC_SYNC_CHANGE-inte.patch b/target/linux/mvebu/patches-4.14/405-net-mvneta-disable-MVNETA_CAUSE_PSC_SYNC_CHANGE-inte.patch deleted file mode 100644 index 7d02b0a93b69..000000000000 --- a/target/linux/mvebu/patches-4.14/405-net-mvneta-disable-MVNETA_CAUSE_PSC_SYNC_CHANGE-inte.patch +++ /dev/null @@ -1,56 +0,0 @@ -From fde9e742a47606110232b7464608b6f9c0510938 Mon Sep 17 00:00:00 2001 -From: Russell King -Date: Sat, 24 Dec 2016 10:27:08 +0000 -Subject: net: mvneta: disable MVNETA_CAUSE_PSC_SYNC_CHANGE interrupt - -The PSC sync change interrupt can fire multiple times while the link is -down. As this isn't information we make use of, it's pointless having -the interrupt enabled, so let's disable this interrupt. - -Signed-off-by: Russell King ---- - drivers/net/ethernet/marvell/mvneta.c | 12 ++++-------- - 1 file changed, 4 insertions(+), 8 deletions(-) - ---- a/drivers/net/ethernet/marvell/mvneta.c -+++ b/drivers/net/ethernet/marvell/mvneta.c -@@ -2705,8 +2705,7 @@ static int mvneta_poll(struct napi_struc - mvreg_write(pp, MVNETA_INTR_MISC_CAUSE, 0); - - if (cause_misc & (MVNETA_CAUSE_PHY_STATUS_CHANGE | -- MVNETA_CAUSE_LINK_CHANGE | -- MVNETA_CAUSE_PSC_SYNC_CHANGE)) -+ MVNETA_CAUSE_LINK_CHANGE)) - mvneta_link_change(pp); - } - -@@ -3045,8 +3044,7 @@ static void mvneta_start_dev(struct mvne - - mvreg_write(pp, MVNETA_INTR_MISC_MASK, - MVNETA_CAUSE_PHY_STATUS_CHANGE | -- MVNETA_CAUSE_LINK_CHANGE | -- MVNETA_CAUSE_PSC_SYNC_CHANGE); -+ MVNETA_CAUSE_LINK_CHANGE); - - phylink_start(pp->phylink); - netif_tx_start_all_queues(pp->dev); -@@ -3542,8 +3540,7 @@ static int mvneta_cpu_online(unsigned in - on_each_cpu(mvneta_percpu_unmask_interrupt, pp, true); - mvreg_write(pp, MVNETA_INTR_MISC_MASK, - MVNETA_CAUSE_PHY_STATUS_CHANGE | -- MVNETA_CAUSE_LINK_CHANGE | -- MVNETA_CAUSE_PSC_SYNC_CHANGE); -+ MVNETA_CAUSE_LINK_CHANGE); - netif_tx_start_all_queues(pp->dev); - spin_unlock(&pp->lock); - return 0; -@@ -3584,8 +3581,7 @@ static int mvneta_cpu_dead(unsigned int - on_each_cpu(mvneta_percpu_unmask_interrupt, pp, true); - mvreg_write(pp, MVNETA_INTR_MISC_MASK, - MVNETA_CAUSE_PHY_STATUS_CHANGE | -- MVNETA_CAUSE_LINK_CHANGE | -- MVNETA_CAUSE_PSC_SYNC_CHANGE); -+ MVNETA_CAUSE_LINK_CHANGE); - netif_tx_start_all_queues(pp->dev); - return 0; - } diff --git a/target/linux/mvebu/patches-4.14/406-net-mvneta-add-module-EEPROM-reading-support.patch b/target/linux/mvebu/patches-4.14/406-net-mvneta-add-module-EEPROM-reading-support.patch deleted file mode 100644 index 39eb33ac2c18..000000000000 --- a/target/linux/mvebu/patches-4.14/406-net-mvneta-add-module-EEPROM-reading-support.patch +++ /dev/null @@ -1,44 +0,0 @@ -From 2ff039aa4462c2104c210b7cf39691c612de8214 Mon Sep 17 00:00:00 2001 -From: Russell King -Date: Thu, 1 Oct 2015 23:32:39 +0100 -Subject: net: mvneta: add module EEPROM reading support - -Signed-off-by: Russell King ---- - drivers/net/ethernet/marvell/mvneta.c | 18 ++++++++++++++++++ - 1 file changed, 18 insertions(+) - ---- a/drivers/net/ethernet/marvell/mvneta.c -+++ b/drivers/net/ethernet/marvell/mvneta.c -@@ -4045,6 +4045,22 @@ static int mvneta_ethtool_set_wol(struct - return ret; - } - -+static int mvneta_ethtool_get_module_info(struct net_device *dev, -+ struct ethtool_modinfo *modinfo) -+{ -+ struct mvneta_port *pp = netdev_priv(dev); -+ -+ return phylink_ethtool_get_module_info(pp->phylink, modinfo); -+} -+ -+static int mvneta_ethtool_get_module_eeprom(struct net_device *dev, -+ struct ethtool_eeprom *ee, u8 *buf) -+{ -+ struct mvneta_port *pp = netdev_priv(dev); -+ -+ return phylink_ethtool_get_module_eeprom(pp->phylink, ee, buf); -+} -+ - static int mvneta_ethtool_get_eee(struct net_device *dev, - struct ethtool_eee *eee) - { -@@ -4129,6 +4145,8 @@ static const struct ethtool_ops mvneta_e - .set_link_ksettings = mvneta_ethtool_set_link_ksettings, - .get_wol = mvneta_ethtool_get_wol, - .set_wol = mvneta_ethtool_set_wol, -+ .get_module_info = mvneta_ethtool_get_module_info, -+ .get_module_eeprom = mvneta_ethtool_get_module_eeprom, - .get_eee = mvneta_ethtool_get_eee, - .set_eee = mvneta_ethtool_set_eee, - }; diff --git a/target/linux/mvebu/patches-4.14/407-phy-fixed-phy-remove-fixed_phy_update_state.patch b/target/linux/mvebu/patches-4.14/407-phy-fixed-phy-remove-fixed_phy_update_state.patch deleted file mode 100644 index 71c2f45555ed..000000000000 --- a/target/linux/mvebu/patches-4.14/407-phy-fixed-phy-remove-fixed_phy_update_state.patch +++ /dev/null @@ -1,80 +0,0 @@ -From 774ce2eda0a929f79ee398ba6d2d13fd406f31c4 Mon Sep 17 00:00:00 2001 -From: Russell King -Date: Fri, 2 Oct 2015 22:46:54 +0100 -Subject: phy: fixed-phy: remove fixed_phy_update_state() - -mvneta is the only user of fixed_phy_update_state(), which has been -converted to use phylink instead. Remove fixed_phy_update_state(). - -Reviewed-by: Florian Fainelli -Signed-off-by: Russell King ---- - drivers/net/phy/fixed_phy.c | 31 ------------------------------- - include/linux/phy_fixed.h | 9 --------- - 2 files changed, 40 deletions(-) - ---- a/drivers/net/phy/fixed_phy.c -+++ b/drivers/net/phy/fixed_phy.c -@@ -115,37 +115,6 @@ int fixed_phy_set_link_update(struct phy - } - EXPORT_SYMBOL_GPL(fixed_phy_set_link_update); - --int fixed_phy_update_state(struct phy_device *phydev, -- const struct fixed_phy_status *status, -- const struct fixed_phy_status *changed) --{ -- struct fixed_mdio_bus *fmb = &platform_fmb; -- struct fixed_phy *fp; -- -- if (!phydev || phydev->mdio.bus != fmb->mii_bus) -- return -EINVAL; -- -- list_for_each_entry(fp, &fmb->phys, node) { -- if (fp->addr == phydev->mdio.addr) { -- write_seqcount_begin(&fp->seqcount); --#define _UPD(x) if (changed->x) \ -- fp->status.x = status->x -- _UPD(link); -- _UPD(speed); -- _UPD(duplex); -- _UPD(pause); -- _UPD(asym_pause); --#undef _UPD -- fixed_phy_update(fp); -- write_seqcount_end(&fp->seqcount); -- return 0; -- } -- } -- -- return -ENOENT; --} --EXPORT_SYMBOL(fixed_phy_update_state); -- - int fixed_phy_add(unsigned int irq, int phy_addr, - struct fixed_phy_status *status, - int link_gpio) ---- a/include/linux/phy_fixed.h -+++ b/include/linux/phy_fixed.h -@@ -24,9 +24,6 @@ extern void fixed_phy_unregister(struct - extern int fixed_phy_set_link_update(struct phy_device *phydev, - int (*link_update)(struct net_device *, - struct fixed_phy_status *)); --extern int fixed_phy_update_state(struct phy_device *phydev, -- const struct fixed_phy_status *status, -- const struct fixed_phy_status *changed); - #else - static inline int fixed_phy_add(unsigned int irq, int phy_id, - struct fixed_phy_status *status, -@@ -50,12 +47,6 @@ static inline int fixed_phy_set_link_upd - { - return -ENODEV; - } --static inline int fixed_phy_update_state(struct phy_device *phydev, -- const struct fixed_phy_status *status, -- const struct fixed_phy_status *changed) --{ -- return -ENODEV; --} - #endif /* CONFIG_FIXED_PHY */ - - #endif /* __PHY_FIXED_H */ diff --git a/target/linux/mvebu/patches-4.14/408-sfp-move-module-eeprom-ethtool-access-into-netdev-co.patch b/target/linux/mvebu/patches-4.14/408-sfp-move-module-eeprom-ethtool-access-into-netdev-co.patch deleted file mode 100644 index 19f8f1e6327c..000000000000 --- a/target/linux/mvebu/patches-4.14/408-sfp-move-module-eeprom-ethtool-access-into-netdev-co.patch +++ /dev/null @@ -1,181 +0,0 @@ -From c47beb7e3f8575dfd7d58240a72c4e4e66ce5449 Mon Sep 17 00:00:00 2001 -From: Russell King -Date: Fri, 14 Apr 2017 15:26:32 +0100 -Subject: sfp: move module eeprom ethtool access into netdev core ethtool - -Signed-off-by: Russell King ---- - drivers/net/ethernet/marvell/mvneta.c | 18 ------------------ - drivers/net/phy/phylink.c | 28 ---------------------------- - drivers/net/phy/sfp-bus.c | 6 ++---- - include/linux/netdevice.h | 2 ++ - include/linux/phylink.h | 3 --- - net/core/ethtool.c | 7 +++++++ - 6 files changed, 11 insertions(+), 53 deletions(-) - ---- a/drivers/net/ethernet/marvell/mvneta.c -+++ b/drivers/net/ethernet/marvell/mvneta.c -@@ -4045,22 +4045,6 @@ static int mvneta_ethtool_set_wol(struct - return ret; - } - --static int mvneta_ethtool_get_module_info(struct net_device *dev, -- struct ethtool_modinfo *modinfo) --{ -- struct mvneta_port *pp = netdev_priv(dev); -- -- return phylink_ethtool_get_module_info(pp->phylink, modinfo); --} -- --static int mvneta_ethtool_get_module_eeprom(struct net_device *dev, -- struct ethtool_eeprom *ee, u8 *buf) --{ -- struct mvneta_port *pp = netdev_priv(dev); -- -- return phylink_ethtool_get_module_eeprom(pp->phylink, ee, buf); --} -- - static int mvneta_ethtool_get_eee(struct net_device *dev, - struct ethtool_eee *eee) - { -@@ -4145,8 +4129,6 @@ static const struct ethtool_ops mvneta_e - .set_link_ksettings = mvneta_ethtool_set_link_ksettings, - .get_wol = mvneta_ethtool_get_wol, - .set_wol = mvneta_ethtool_set_wol, -- .get_module_info = mvneta_ethtool_get_module_info, -- .get_module_eeprom = mvneta_ethtool_get_module_eeprom, - .get_eee = mvneta_ethtool_get_eee, - .set_eee = mvneta_ethtool_set_eee, - }; ---- a/drivers/net/phy/phylink.c -+++ b/drivers/net/phy/phylink.c -@@ -1060,34 +1060,6 @@ int phylink_ethtool_set_pauseparam(struc - } - EXPORT_SYMBOL_GPL(phylink_ethtool_set_pauseparam); - --int phylink_ethtool_get_module_info(struct phylink *pl, -- struct ethtool_modinfo *modinfo) --{ -- int ret = -EOPNOTSUPP; -- -- WARN_ON(!lockdep_rtnl_is_held()); -- -- if (pl->sfp_bus) -- ret = sfp_get_module_info(pl->sfp_bus, modinfo); -- -- return ret; --} --EXPORT_SYMBOL_GPL(phylink_ethtool_get_module_info); -- --int phylink_ethtool_get_module_eeprom(struct phylink *pl, -- struct ethtool_eeprom *ee, u8 *buf) --{ -- int ret = -EOPNOTSUPP; -- -- WARN_ON(!lockdep_rtnl_is_held()); -- -- if (pl->sfp_bus) -- ret = sfp_get_module_eeprom(pl->sfp_bus, ee, buf); -- -- return ret; --} --EXPORT_SYMBOL_GPL(phylink_ethtool_get_module_eeprom); -- - int phylink_init_eee(struct phylink *pl, bool clk_stop_enable) - { - int ret = -EPROTONOSUPPORT; ---- a/drivers/net/phy/sfp-bus.c -+++ b/drivers/net/phy/sfp-bus.c -@@ -279,6 +279,7 @@ static int sfp_register_bus(struct sfp_b - bus->socket_ops->attach(bus->sfp); - if (bus->started) - bus->socket_ops->start(bus->sfp); -+ bus->netdev->sfp_bus = bus; - bus->registered = true; - return 0; - } -@@ -294,14 +295,13 @@ static void sfp_unregister_bus(struct sf - if (bus->phydev && ops && ops->disconnect_phy) - ops->disconnect_phy(bus->upstream); - } -+ bus->netdev->sfp_bus = NULL; - bus->registered = false; - } - - - int sfp_get_module_info(struct sfp_bus *bus, struct ethtool_modinfo *modinfo) - { -- if (!bus->registered) -- return -ENOIOCTLCMD; - return bus->socket_ops->module_info(bus->sfp, modinfo); - } - EXPORT_SYMBOL_GPL(sfp_get_module_info); -@@ -309,8 +309,6 @@ EXPORT_SYMBOL_GPL(sfp_get_module_info); - int sfp_get_module_eeprom(struct sfp_bus *bus, struct ethtool_eeprom *ee, - u8 *data) - { -- if (!bus->registered) -- return -ENOIOCTLCMD; - return bus->socket_ops->module_eeprom(bus->sfp, ee, data); - } - EXPORT_SYMBOL_GPL(sfp_get_module_eeprom); ---- a/include/linux/netdevice.h -+++ b/include/linux/netdevice.h -@@ -57,6 +57,7 @@ struct device; - struct phy_device; - struct dsa_switch_tree; - -+struct sfp_bus; - /* 802.11 specific */ - struct wireless_dev; - /* 802.15.4 specific */ -@@ -1940,6 +1941,7 @@ struct net_device { - struct netprio_map __rcu *priomap; - #endif - struct phy_device *phydev; -+ struct sfp_bus *sfp_bus; - struct lock_class_key *qdisc_tx_busylock; - struct lock_class_key *qdisc_running_key; - bool proto_down; ---- a/include/linux/phylink.h -+++ b/include/linux/phylink.h -@@ -125,9 +125,6 @@ void phylink_ethtool_get_pauseparam(stru - struct ethtool_pauseparam *); - int phylink_ethtool_set_pauseparam(struct phylink *, - struct ethtool_pauseparam *); --int phylink_ethtool_get_module_info(struct phylink *, struct ethtool_modinfo *); --int phylink_ethtool_get_module_eeprom(struct phylink *, -- struct ethtool_eeprom *, u8 *); - int phylink_init_eee(struct phylink *, bool); - int phylink_get_eee_err(struct phylink *); - int phylink_ethtool_get_eee(struct phylink *, struct ethtool_eee *); ---- a/net/core/ethtool.c -+++ b/net/core/ethtool.c -@@ -22,6 +22,7 @@ - #include - #include - #include -+#include - #include - #include - #include -@@ -2214,6 +2215,9 @@ static int __ethtool_get_module_info(str - const struct ethtool_ops *ops = dev->ethtool_ops; - struct phy_device *phydev = dev->phydev; - -+ if (dev->sfp_bus) -+ return sfp_get_module_info(dev->sfp_bus, modinfo); -+ - if (phydev && phydev->drv && phydev->drv->module_info) - return phydev->drv->module_info(phydev, modinfo); - -@@ -2248,6 +2252,9 @@ static int __ethtool_get_module_eeprom(s - const struct ethtool_ops *ops = dev->ethtool_ops; - struct phy_device *phydev = dev->phydev; - -+ if (dev->sfp_bus) -+ return sfp_get_module_eeprom(dev->sfp_bus, ee, data); -+ - if (phydev && phydev->drv && phydev->drv->module_eeprom) - return phydev->drv->module_eeprom(phydev, ee, data); - diff --git a/target/linux/mvebu/patches-4.14/409-sfp-use-netdev-sfp_bus-for-start-stop.patch b/target/linux/mvebu/patches-4.14/409-sfp-use-netdev-sfp_bus-for-start-stop.patch deleted file mode 100644 index 10bd2d0a46cd..000000000000 --- a/target/linux/mvebu/patches-4.14/409-sfp-use-netdev-sfp_bus-for-start-stop.patch +++ /dev/null @@ -1,34 +0,0 @@ -From 883dc66755313e133a787eba4dfde313fe33525b Mon Sep 17 00:00:00 2001 -From: Russell King -Date: Fri, 14 Apr 2017 16:41:55 +0100 -Subject: sfp: use netdev sfp_bus for start/stop - -Signed-off-by: Russell King ---- - drivers/net/phy/phylink.c | 8 ++++---- - 1 file changed, 4 insertions(+), 4 deletions(-) - ---- a/drivers/net/phy/phylink.c -+++ b/drivers/net/phy/phylink.c -@@ -777,8 +777,8 @@ void phylink_start(struct phylink *pl) - clear_bit(PHYLINK_DISABLE_STOPPED, &pl->phylink_disable_state); - phylink_run_resolve(pl); - -- if (pl->sfp_bus) -- sfp_upstream_start(pl->sfp_bus); -+ if (pl->netdev->sfp_bus) -+ sfp_upstream_start(pl->netdev->sfp_bus); - if (pl->phydev) - phy_start(pl->phydev); - } -@@ -790,8 +790,8 @@ void phylink_stop(struct phylink *pl) - - if (pl->phydev) - phy_stop(pl->phydev); -- if (pl->sfp_bus) -- sfp_upstream_stop(pl->sfp_bus); -+ if (pl->netdev->sfp_bus) -+ sfp_upstream_stop(pl->netdev->sfp_bus); - - phylink_run_resolve_and_disable(pl, PHYLINK_DISABLE_STOPPED); - } diff --git a/target/linux/mvebu/patches-4.14/410-sfp-hack-allow-marvell-10G-phy-support-to-use-SFP.patch b/target/linux/mvebu/patches-4.14/410-sfp-hack-allow-marvell-10G-phy-support-to-use-SFP.patch deleted file mode 100644 index d6e5fbf33f89..000000000000 --- a/target/linux/mvebu/patches-4.14/410-sfp-hack-allow-marvell-10G-phy-support-to-use-SFP.patch +++ /dev/null @@ -1,132 +0,0 @@ -From 4a4aca08b11501cb1b2c509113bbb65eb66a1f45 Mon Sep 17 00:00:00 2001 -From: Russell King -Date: Fri, 14 Apr 2017 14:21:25 +0100 -Subject: sfp: hack: allow marvell 10G phy support to use SFP - -Allow the Marvell 10G PHY to register with the SFP bus, so that SFP+ -cages can work. This bypasses phylink, meaning that socket status -is not taken into account for the link state. Also, the tx-disable -signal must be commented out in DT for this to work... - -Signed-off-by: Russell King ---- - drivers/net/phy/marvell10g.c | 54 +++++++++++++++++++++++++++++++++++++++++++- - 1 file changed, 53 insertions(+), 1 deletion(-) - ---- a/drivers/net/phy/marvell10g.c -+++ b/drivers/net/phy/marvell10g.c -@@ -15,8 +15,10 @@ - * If both the fiber and copper ports are connected, the first to gain - * link takes priority and the other port is completely locked out. - */ -+#include - #include - #include -+#include - - enum { - MV_PMA_BOOT = 0xc050, -@@ -41,6 +43,11 @@ enum { - MV_AN_RESULT_SPD_10000 = BIT(15), - }; - -+struct mv3310_priv { -+ struct device_node *sfp_node; -+ struct sfp_bus *sfp_bus; -+}; -+ - static int mv3310_modify(struct phy_device *phydev, int devad, u16 reg, - u16 mask, u16 bits) - { -@@ -59,8 +66,25 @@ static int mv3310_modify(struct phy_devi - return ret < 0 ? ret : 1; - } - -+static int mv3310_sfp_insert(void *upstream, const struct sfp_eeprom_id *id) -+{ -+ struct phy_device *phydev = upstream; -+ struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev); -+ -+ if (sfp_parse_interface(priv->sfp_bus, id) != PHY_INTERFACE_MODE_10GKR) { -+ dev_err(&phydev->mdio.dev, "incompatible SFP module inserted\n"); -+ return -EINVAL; -+ } -+ return 0; -+} -+ -+static const struct sfp_upstream_ops mv3310_sfp_ops = { -+ .module_insert = mv3310_sfp_insert, -+}; -+ - static int mv3310_probe(struct phy_device *phydev) - { -+ struct mv3310_priv *priv; - u32 mmd_mask = MDIO_DEVS_PMAPMD | MDIO_DEVS_AN; - int ret; - -@@ -78,9 +102,27 @@ static int mv3310_probe(struct phy_devic - return -ENODEV; - } - -+ priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL); -+ if (!priv) -+ return -ENOMEM; -+ -+ dev_set_drvdata(&phydev->mdio.dev, priv); -+ -+ if (phydev->mdio.dev.of_node) -+ priv->sfp_node = of_parse_phandle(phydev->mdio.dev.of_node, -+ "sfp", 0); -+ - return 0; - } - -+static void mv3310_remove(struct phy_device *phydev) -+{ -+ struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev); -+ -+ if (priv->sfp_bus) -+ sfp_unregister_upstream(priv->sfp_bus); -+} -+ - /* - * Resetting the MV88X3310 causes it to become non-responsive. Avoid - * setting the reset bit(s). -@@ -92,6 +134,7 @@ static int mv3310_soft_reset(struct phy_ - - static int mv3310_config_init(struct phy_device *phydev) - { -+ struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev); - __ETHTOOL_DECLARE_LINK_MODE_MASK(supported) = { 0, }; - u32 mask; - int val; -@@ -180,6 +223,14 @@ static int mv3310_config_init(struct phy - phydev->supported &= mask; - phydev->advertising &= phydev->supported; - -+ /* Would be nice to do this in the probe function, but unfortunately, -+ * phylib doesn't have phydev->attached_dev set there. -+ */ -+ if (priv->sfp_node && !priv->sfp_bus) -+ priv->sfp_bus = sfp_register_upstream(priv->sfp_node, -+ phydev->attached_dev, -+ phydev, &mv3310_sfp_ops); -+ - return 0; - } - -@@ -363,12 +414,13 @@ static struct phy_driver mv3310_drivers[ - SUPPORTED_FIBRE | - SUPPORTED_10000baseT_Full | - SUPPORTED_Backplane, -- .probe = mv3310_probe, - .soft_reset = mv3310_soft_reset, - .config_init = mv3310_config_init, -+ .probe = mv3310_probe, - .config_aneg = mv3310_config_aneg, - .aneg_done = mv3310_aneg_done, - .read_status = mv3310_read_status, -+ .remove = mv3310_remove, - }, - }; - diff --git a/target/linux/mvebu/patches-4.14/411-sfp-add-sfp-compatible.patch b/target/linux/mvebu/patches-4.14/411-sfp-add-sfp-compatible.patch deleted file mode 100644 index 9174765e6a34..000000000000 --- a/target/linux/mvebu/patches-4.14/411-sfp-add-sfp-compatible.patch +++ /dev/null @@ -1,24 +0,0 @@ -From 3344f73509a34d2124b716efc79cd9787773018b Mon Sep 17 00:00:00 2001 -From: Russell King -Date: Fri, 14 Apr 2017 20:17:13 +0100 -Subject: sfp: add sfp+ compatible - -Add a compatible for SFP+ cages. SFP+ cages are backwards compatible, -but the ethernet device behind them may not support the slower speeds -of SFP modules. - -Signed-off-by: Russell King ---- - drivers/net/phy/sfp.c | 1 + - 1 file changed, 1 insertion(+) - ---- a/drivers/net/phy/sfp.c -+++ b/drivers/net/phy/sfp.c -@@ -1168,6 +1168,7 @@ static int sfp_remove(struct platform_de - - static const struct of_device_id sfp_of_match[] = { - { .compatible = "sff,sfp", }, -+ { .compatible = "sff,sfp+", }, - { }, - }; - MODULE_DEVICE_TABLE(of, sfp_of_match); diff --git a/target/linux/mvebu/patches-4.14/412-ARM-dts-armada388-clearfog-emmc-on-clearfog-base.patch b/target/linux/mvebu/patches-4.14/412-ARM-dts-armada388-clearfog-emmc-on-clearfog-base.patch deleted file mode 100644 index 222a323825bf..000000000000 --- a/target/linux/mvebu/patches-4.14/412-ARM-dts-armada388-clearfog-emmc-on-clearfog-base.patch +++ /dev/null @@ -1,87 +0,0 @@ -From 8137da20701c776ad3481115305a5e8e410871ba Mon Sep 17 00:00:00 2001 -From: Russell King -Date: Tue, 29 Nov 2016 10:15:45 +0000 -Subject: ARM: dts: armada388-clearfog: emmc on clearfog base - -Signed-off-by: Russell King ---- - arch/arm/boot/dts/armada-388-clearfog-base.dts | 1 + - .../dts/armada-38x-solidrun-microsom-emmc.dtsi | 62 ++++++++++++++++++++++ - 2 files changed, 63 insertions(+) - create mode 100644 arch/arm/boot/dts/armada-38x-solidrun-microsom-emmc.dtsi - ---- a/arch/arm/boot/dts/armada-388-clearfog-base.dts -+++ b/arch/arm/boot/dts/armada-388-clearfog-base.dts -@@ -48,6 +48,7 @@ - - /dts-v1/; - #include "armada-388-clearfog.dtsi" -+#include "armada-38x-solidrun-microsom-emmc.dtsi" - - / { - model = "SolidRun Clearfog Base A1"; ---- /dev/null -+++ b/arch/arm/boot/dts/armada-38x-solidrun-microsom-emmc.dtsi -@@ -0,0 +1,62 @@ -+/* -+ * Device Tree file for SolidRun Armada 38x Microsom add-on for eMMC -+ * -+ * Copyright (C) 2015 Russell King -+ * -+ * This board is in development; the contents of this file work with -+ * the A1 rev 2.0 of the board, which does not represent final -+ * production board. Things will change, don't expect this file to -+ * remain compatible info the future. -+ * -+ * This file is dual-licensed: you can use it either under the terms -+ * of the GPL or the X11 license, at your option. Note that this dual -+ * licensing only applies to this file, and not this project as a -+ * whole. -+ * -+ * a) This file is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License -+ * version 2 as published by the Free Software Foundation. -+ * -+ * This file is distributed in the hope that it will be useful -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * Or, alternatively -+ * -+ * b) Permission is hereby granted, free of charge, to any person -+ * obtaining a copy of this software and associated documentation -+ * files (the "Software"), to deal in the Software without -+ * restriction, including without limitation the rights to use -+ * copy, modify, merge, publish, distribute, sublicense, and/or -+ * sell copies of the Software, and to permit persons to whom the -+ * Software is furnished to do so, subject to the following -+ * conditions: -+ * -+ * The above copyright notice and this permission notice shall be -+ * included in all copies or substantial portions of the Software. -+ * -+ * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND -+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES -+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND -+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT -+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY -+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING -+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR -+ * OTHER DEALINGS IN THE SOFTWARE. -+ */ -+/ { -+ soc { -+ internal-regs { -+ sdhci@d8000 { -+ bus-width = <4>; -+ no-1-8-v; -+ non-removable; -+ pinctrl-0 = <µsom_sdhci_pins>; -+ pinctrl-names = "default"; -+ status = "okay"; -+ wp-inverted; -+ }; -+ }; -+ }; -+}; diff --git a/target/linux/mvebu/patches-4.14/413-ARM-dts-armada388-clearfog-increase-speed-of-i2c0-to.patch b/target/linux/mvebu/patches-4.14/413-ARM-dts-armada388-clearfog-increase-speed-of-i2c0-to.patch deleted file mode 100644 index 4aedc82fe729..000000000000 --- a/target/linux/mvebu/patches-4.14/413-ARM-dts-armada388-clearfog-increase-speed-of-i2c0-to.patch +++ /dev/null @@ -1,42 +0,0 @@ -From 6e127081e669cf163a818dc04d590790e4ed9527 Mon Sep 17 00:00:00 2001 -From: Russell King -Date: Tue, 29 Nov 2016 20:06:44 +0000 -Subject: ARM: dts: armada388-clearfog: increase speed of i2c0 to 400kHz - -All the devices on I2C0 support fast mode, so increase the bus speed -to match. The Armada 388 is known to have a timing issue when in -standard mode, which we believe causes the ficticious device at 0x64 -to appear. - -Signed-off-by: Russell King ---- - arch/arm/boot/dts/armada-388-clearfog.dtsi | 7 ++----- - 1 file changed, 2 insertions(+), 5 deletions(-) - ---- a/arch/arm/boot/dts/armada-388-clearfog.dtsi -+++ b/arch/arm/boot/dts/armada-388-clearfog.dtsi -@@ -143,8 +143,7 @@ - }; - - &i2c0 { -- /* Is there anything on this? */ -- clock-frequency = <100000>; -+ clock-frequency = <400000>; - pinctrl-0 = <&i2c0_pins>; - pinctrl-names = "default"; - status = "okay"; -@@ -239,13 +238,11 @@ - }; - }; - -- /* The MCP3021 is 100kHz clock only */ -+ /* The MCP3021 supports standard and fast modes */ - mikrobus_adc: mcp3021@4c { - compatible = "microchip,mcp3021"; - reg = <0x4c>; - }; -- -- /* Also something at 0x64 */ - }; - - &i2c1 { diff --git a/target/linux/mvebu/patches-4.14/414-ARM-dts-armada388-clearfog-add-SFP-module-support.patch b/target/linux/mvebu/patches-4.14/414-ARM-dts-armada388-clearfog-add-SFP-module-support.patch deleted file mode 100644 index 52ddcb6063e9..000000000000 --- a/target/linux/mvebu/patches-4.14/414-ARM-dts-armada388-clearfog-add-SFP-module-support.patch +++ /dev/null @@ -1,81 +0,0 @@ -From 74fa68669c88f73bceff523cb764297b7d1e132b Mon Sep 17 00:00:00 2001 -From: Russell King -Date: Tue, 29 Nov 2016 10:13:44 +0000 -Subject: ARM: dts: armada388-clearfog: add SFP module support - -Add SFP module support for Clearfog using the SFP phylink support. - -Signed-off-by: Russell King ---- - arch/arm/boot/dts/armada-388-clearfog.dtsi | 44 ++++++++---------------------- - 1 file changed, 11 insertions(+), 33 deletions(-) - ---- a/arch/arm/boot/dts/armada-388-clearfog.dtsi -+++ b/arch/arm/boot/dts/armada-388-clearfog.dtsi -@@ -117,6 +117,15 @@ - }; - }; - }; -+ -+ sfp: sfp { -+ compatible = "sff,sfp"; -+ i2c-bus = <&i2c1>; -+ los-gpio = <&expander0 12 GPIO_ACTIVE_HIGH>; -+ mod-def0-gpio = <&expander0 15 GPIO_ACTIVE_LOW>; -+ tx-disable-gpio = <&expander0 14 GPIO_ACTIVE_HIGH>; -+ tx-fault-gpio = <&expander0 13 GPIO_ACTIVE_HIGH>; -+ }; - }; - - ð1 { -@@ -133,13 +142,10 @@ - bm,pool-long = <3>; - bm,pool-short = <1>; - buffer-manager = <&bm>; -+ managed = "in-band-status"; - phy-mode = "sgmii"; -+ sfp = <&sfp>; - status = "okay"; -- -- fixed-link { -- speed = <1000>; -- full-duplex; -- }; - }; - - &i2c0 { -@@ -208,34 +214,6 @@ - output-low; - line-name = "m.2 devslp"; - }; -- sfp_los { -- /* SFP loss of signal */ -- gpio-hog; -- gpios = <12 GPIO_ACTIVE_HIGH>; -- input; -- line-name = "sfp-los"; -- }; -- sfp_tx_fault { -- /* SFP laser fault */ -- gpio-hog; -- gpios = <13 GPIO_ACTIVE_HIGH>; -- input; -- line-name = "sfp-tx-fault"; -- }; -- sfp_tx_disable { -- /* SFP transmit disable */ -- gpio-hog; -- gpios = <14 GPIO_ACTIVE_HIGH>; -- output-low; -- line-name = "sfp-tx-disable"; -- }; -- sfp_mod_def0 { -- /* SFP module present */ -- gpio-hog; -- gpios = <15 GPIO_ACTIVE_LOW>; -- input; -- line-name = "sfp-mod-def0"; -- }; - }; - - /* The MCP3021 supports standard and fast modes */ diff --git a/target/linux/mvebu/patches-4.14/415-ARM-dts-armada388-clearfog-document-MPP-usage.patch b/target/linux/mvebu/patches-4.14/415-ARM-dts-armada388-clearfog-document-MPP-usage.patch deleted file mode 100644 index 0e24d08c8dd0..000000000000 --- a/target/linux/mvebu/patches-4.14/415-ARM-dts-armada388-clearfog-document-MPP-usage.patch +++ /dev/null @@ -1,124 +0,0 @@ -From 09a0122c74ec076e08512f1b00b7ccb8a450282f Mon Sep 17 00:00:00 2001 -From: Russell King -Date: Tue, 29 Nov 2016 10:15:43 +0000 -Subject: ARM: dts: armada388-clearfog: document MPP usage - -Signed-off-by: Russell King ---- - arch/arm/boot/dts/armada-388-clearfog-base.dts | 51 ++++++++++++++++++++++++++ - arch/arm/boot/dts/armada-388-clearfog.dts | 50 +++++++++++++++++++++++++ - 2 files changed, 101 insertions(+) - ---- a/arch/arm/boot/dts/armada-388-clearfog-base.dts -+++ b/arch/arm/boot/dts/armada-388-clearfog-base.dts -@@ -108,3 +108,54 @@ - marvell,function = "gpio"; - }; - }; -+ -+/* -+MPP -+18: pu gpio pca9655 int -+19: gpio phy reset -+20: pu gpio sd0 detect -+21: sd0:cmd -+22: pd gpio mikro int -+23: -+ -+24: ua1:rxd mikro rx -+25: ua1:txd mikro tx -+26: pu i2c1:sck -+27: pu i2c1:sda -+28: sd0:clk -+29: pd gpio mikro rst -+30: -+31: -+ -+32: -+33: -+34: -+35: -+36: -+37: sd0:d3 -+38: sd0:d0 -+39: sd0:d1 -+ -+40: sd0:d2 -+41: -+42: -+43: spi1:cs2 mikro cs -+44: gpio rear button sw3 -+45: ref:clk_out0 phy#0 clock -+46: ref:clk_out1 phy#1 clock -+47: -+ -+48: gpio J18 spare gpio -+49: gpio U10 I2C_IRQ(GNSS) -+50: gpio board id? -+51: -+52: -+53: -+54: gpio mikro pwm -+55: -+ -+56: pu spi1:mosi mikro mosi -+57: pd spi1:sck mikro sck -+58: spi1:miso mikro miso -+59: -+*/ ---- a/arch/arm/boot/dts/armada-388-clearfog.dts -+++ b/arch/arm/boot/dts/armada-388-clearfog.dts -@@ -290,3 +290,53 @@ - */ - pinctrl-0 = <&spi1_pins &clearfog_spi1_cs_pins &mikro_spi_pins>; - }; -+/* -++#define A38x_CUSTOMER_BOARD_1_MPP16_23 0x00400011 -+MPP18: gpio ? (pca9655 int?) -+MPP19: gpio ? (clkreq?) -+MPP20: gpio ? (sd0 detect) -+MPP21: sd0:cmd x sd0 -+MPP22: gpio x mikro int -+MPP23: gpio x switch irq -++#define A38x_CUSTOMER_BOARD_1_MPP24_31 0x22043333 -+MPP24: ua1:rxd x mikro rx -+MPP25: ua1:txd x mikro tx -+MPP26: i2c1:sck x mikro sck -+MPP27: i2c1:sda x mikro sda -+MPP28: sd0:clk x sd0 -+MPP29: gpio x mikro rst -+MPP30: ge1:txd2 ? (config) -+MPP31: ge1:txd3 ? (config) -++#define A38x_CUSTOMER_BOARD_1_MPP32_39 0x44400002 -+MPP32: ge1:txctl ? (unused) -+MPP33: gpio ? (pic_com0) -+MPP34: gpio x rear button (pic_com1) -+MPP35: gpio ? (pic_com2) -+MPP36: gpio ? (unused) -+MPP37: sd0:d3 x sd0 -+MPP38: sd0:d0 x sd0 -+MPP39: sd0:d1 x sd0 -++#define A38x_CUSTOMER_BOARD_1_MPP40_47 0x41144004 -+MPP40: sd0:d2 x sd0 -+MPP41: gpio x switch reset -+MPP42: gpio ? sw1-1 -+MPP43: spi1:cs2 x mikro cs -+MPP44: sata3:prsnt ? (unused) -+MPP45: ref:clk_out0 ? -+MPP46: ref:clk_out1 x switch clk -+MPP47: 4 ? (unused) -++#define A38x_CUSTOMER_BOARD_1_MPP48_55 0x40333333 -+MPP48: tdm:pclk -+MPP49: tdm:fsync -+MPP50: tdm:drx -+MPP51: tdm:dtx -+MPP52: tdm:int -+MPP53: tdm:rst -+MPP54: gpio ? (pwm) -+MPP55: spi1:cs1 x slic -++#define A38x_CUSTOMER_BOARD_1_MPP56_63 0x00004444 -+MPP56: spi1:mosi x mikro mosi -+MPP57: spi1:sck x mikro sck -+MPP58: spi1:miso x mikro miso -+MPP59: spi1:cs0 x w25q32 -+*/ diff --git a/target/linux/mvebu/patches-4.14/420-rtc-armada38x-add-support-for-trimming-the-RTC.patch b/target/linux/mvebu/patches-4.14/420-rtc-armada38x-add-support-for-trimming-the-RTC.patch deleted file mode 100644 index 2974a6976036..000000000000 --- a/target/linux/mvebu/patches-4.14/420-rtc-armada38x-add-support-for-trimming-the-RTC.patch +++ /dev/null @@ -1,143 +0,0 @@ -commit f94ffbc2c2a4128c4412bb483d0807722dfb682b -Author: Russell King -Date: Fri Sep 29 11:23:31 2017 +0100 - - rtc: armada38x: add support for trimming the RTC - - Add support for trimming the RTC using the offset mechanism. This RTC - supports two modes: low update mode and high update mode. Low update - mode has finer precision than high update mode, so we use the low mode - where possible. - - Signed-off-by: Russell King - Signed-off-by: Alexandre Belloni - ---- a/drivers/rtc/rtc-armada38x.c -+++ b/drivers/rtc/rtc-armada38x.c -@@ -28,6 +28,8 @@ - #define RTC_IRQ_AL_EN BIT(0) - #define RTC_IRQ_FREQ_EN BIT(1) - #define RTC_IRQ_FREQ_1HZ BIT(2) -+#define RTC_CCR 0x18 -+#define RTC_CCR_MODE BIT(15) - - #define RTC_TIME 0xC - #define RTC_ALARM1 0x10 -@@ -343,18 +345,117 @@ static irqreturn_t armada38x_rtc_alarm_i - return IRQ_HANDLED; - } - -+/* -+ * The information given in the Armada 388 functional spec is complex. -+ * They give two different formulas for calculating the offset value, -+ * but when considering "Offset" as an 8-bit signed integer, they both -+ * reduce down to (we shall rename "Offset" as "val" here): -+ * -+ * val = (f_ideal / f_measured - 1) / resolution where f_ideal = 32768 -+ * -+ * Converting to time, f = 1/t: -+ * val = (t_measured / t_ideal - 1) / resolution where t_ideal = 1/32768 -+ * -+ * => t_measured / t_ideal = val * resolution + 1 -+ * -+ * "offset" in the RTC interface is defined as: -+ * t = t0 * (1 + offset * 1e-9) -+ * where t is the desired period, t0 is the measured period with a zero -+ * offset, which is t_measured above. With t0 = t_measured and t = t_ideal, -+ * offset = (t_ideal / t_measured - 1) / 1e-9 -+ * -+ * => t_ideal / t_measured = offset * 1e-9 + 1 -+ * -+ * so: -+ * -+ * offset * 1e-9 + 1 = 1 / (val * resolution + 1) -+ * -+ * We want "resolution" to be an integer, so resolution = R * 1e-9, giving -+ * offset = 1e18 / (val * R + 1e9) - 1e9 -+ * val = (1e18 / (offset + 1e9) - 1e9) / R -+ * with a common transformation: -+ * f(x) = 1e18 / (x + 1e9) - 1e9 -+ * offset = f(val * R) -+ * val = f(offset) / R -+ * -+ * Armada 38x supports two modes, fine mode (954ppb) and coarse mode (3815ppb). -+ */ -+static long armada38x_ppb_convert(long ppb) -+{ -+ long div = ppb + 1000000000L; -+ -+ return div_s64(1000000000000000000LL + div / 2, div) - 1000000000L; -+} -+ -+static int armada38x_rtc_read_offset(struct device *dev, long *offset) -+{ -+ struct armada38x_rtc *rtc = dev_get_drvdata(dev); -+ unsigned long ccr, flags; -+ long ppb_cor; -+ -+ spin_lock_irqsave(&rtc->lock, flags); -+ ccr = rtc->data->read_rtc_reg(rtc, RTC_CCR); -+ spin_unlock_irqrestore(&rtc->lock, flags); -+ -+ ppb_cor = (ccr & RTC_CCR_MODE ? 3815 : 954) * (s8)ccr; -+ /* ppb_cor + 1000000000L can never be zero */ -+ *offset = armada38x_ppb_convert(ppb_cor); -+ -+ return 0; -+} -+ -+static int armada38x_rtc_set_offset(struct device *dev, long offset) -+{ -+ struct armada38x_rtc *rtc = dev_get_drvdata(dev); -+ unsigned long ccr = 0; -+ long ppb_cor, off; -+ -+ /* -+ * The maximum ppb_cor is -128 * 3815 .. 127 * 3815, but we -+ * need to clamp the input. This equates to -484270 .. 488558. -+ * Not only is this to stop out of range "off" but also to -+ * avoid the division by zero in armada38x_ppb_convert(). -+ */ -+ offset = clamp(offset, -484270L, 488558L); -+ -+ ppb_cor = armada38x_ppb_convert(offset); -+ -+ /* -+ * Use low update mode where possible, which gives a better -+ * resolution of correction. -+ */ -+ off = DIV_ROUND_CLOSEST(ppb_cor, 954); -+ if (off > 127 || off < -128) { -+ ccr = RTC_CCR_MODE; -+ off = DIV_ROUND_CLOSEST(ppb_cor, 3815); -+ } -+ -+ /* -+ * Armada 388 requires a bit pattern in bits 14..8 depending on -+ * the sign bit: { 0, ~S, S, S, S, S, S } -+ */ -+ ccr |= (off & 0x3fff) ^ 0x2000; -+ rtc_delayed_write(ccr, rtc, RTC_CCR); -+ -+ return 0; -+} -+ - static const struct rtc_class_ops armada38x_rtc_ops = { - .read_time = armada38x_rtc_read_time, - .set_time = armada38x_rtc_set_time, - .read_alarm = armada38x_rtc_read_alarm, - .set_alarm = armada38x_rtc_set_alarm, - .alarm_irq_enable = armada38x_rtc_alarm_irq_enable, -+ .read_offset = armada38x_rtc_read_offset, -+ .set_offset = armada38x_rtc_set_offset, - }; - - static const struct rtc_class_ops armada38x_rtc_ops_noirq = { - .read_time = armada38x_rtc_read_time, - .set_time = armada38x_rtc_set_time, - .read_alarm = armada38x_rtc_read_alarm, -+ .read_offset = armada38x_rtc_read_offset, -+ .set_offset = armada38x_rtc_set_offset, - }; - - static const struct armada38x_rtc_data armada38x_data = { diff --git a/target/linux/mvebu/patches-4.14/421-rtc-armada38x-reset-after-rtc-power-loss.patch b/target/linux/mvebu/patches-4.14/421-rtc-armada38x-reset-after-rtc-power-loss.patch deleted file mode 100644 index 885e3d7c5e90..000000000000 --- a/target/linux/mvebu/patches-4.14/421-rtc-armada38x-reset-after-rtc-power-loss.patch +++ /dev/null @@ -1,73 +0,0 @@ -From 1a990fefb641398fb580a0ea0be99b0ff27cbb9b Mon Sep 17 00:00:00 2001 -From: Baruch Siach -Date: Thu, 21 Jun 2018 20:40:23 +0300 -Subject: [PATCH] rtc: armada38x: reset after rtc power loss - -When the RTC block looses power it needs a reset sequence to make it -usable again. Otherwise, writes to the time register have no effect. - -This reset sequence combines information from the mvebu_rtc driver in -the Marvell provided U-Boot, and the SolidRun provided U-Boot repo. - -Tested on the Armada 388 based SolidRun Clearfog Base. - -Signed-off-by: Baruch Siach -Acked-by: Gregory CLEMENT -Signed-off-by: Alexandre Belloni ---- - drivers/rtc/rtc-armada38x.c | 23 +++++++++++++++++++++++ - 1 file changed, 23 insertions(+) - ---- a/drivers/rtc/rtc-armada38x.c -+++ b/drivers/rtc/rtc-armada38x.c -@@ -30,6 +30,8 @@ - #define RTC_IRQ_FREQ_1HZ BIT(2) - #define RTC_CCR 0x18 - #define RTC_CCR_MODE BIT(15) -+#define RTC_CONF_TEST 0x1C -+#define RTC_NOMINAL_TIMING BIT(13) - - #define RTC_TIME 0xC - #define RTC_ALARM1 0x10 -@@ -75,6 +77,7 @@ struct armada38x_rtc { - void __iomem *regs_soc; - spinlock_t lock; - int irq; -+ bool initialized; - struct value_to_freq *val_to_freq; - struct armada38x_rtc_data *data; - }; -@@ -226,6 +229,23 @@ static int armada38x_rtc_read_time(struc - return 0; - } - -+static void armada38x_rtc_reset(struct armada38x_rtc *rtc) -+{ -+ u32 reg; -+ -+ reg = rtc->data->read_rtc_reg(rtc, RTC_CONF_TEST); -+ /* If bits [7:0] are non-zero, assume RTC was uninitialized */ -+ if (reg & 0xff) { -+ rtc_delayed_write(0, rtc, RTC_CONF_TEST); -+ msleep(500); /* Oscillator startup time */ -+ rtc_delayed_write(0, rtc, RTC_TIME); -+ rtc_delayed_write(SOC_RTC_ALARM1 | SOC_RTC_ALARM2, rtc, -+ RTC_STATUS); -+ rtc_delayed_write(RTC_NOMINAL_TIMING, rtc, RTC_CCR); -+ } -+ rtc->initialized = true; -+} -+ - static int armada38x_rtc_set_time(struct device *dev, struct rtc_time *tm) - { - struct armada38x_rtc *rtc = dev_get_drvdata(dev); -@@ -237,6 +257,9 @@ static int armada38x_rtc_set_time(struct - if (ret) - goto out; - -+ if (!rtc->initialized) -+ armada38x_rtc_reset(rtc); -+ - spin_lock_irqsave(&rtc->lock, flags); - rtc_delayed_write(time, rtc, RTC_TIME); - spin_unlock_irqrestore(&rtc->lock, flags); diff --git a/target/linux/mvebu/patches-4.14/423-ARM-dts-armada-385-linksys-Disable-internal-RTC.patch b/target/linux/mvebu/patches-4.14/423-ARM-dts-armada-385-linksys-Disable-internal-RTC.patch deleted file mode 100644 index 040d6590b552..000000000000 --- a/target/linux/mvebu/patches-4.14/423-ARM-dts-armada-385-linksys-Disable-internal-RTC.patch +++ /dev/null @@ -1,28 +0,0 @@ -From e1cac198fea08c31ec204bed84c279ab05d20389 Mon Sep 17 00:00:00 2001 -From: Hauke Mehrtens -Date: Sat, 17 Mar 2018 15:22:25 +0100 -Subject: ARM: dts: armada-385-linksys: Disable internal RTC - -The internal RTC does not work correctly on these Linksys boards based -on Marvell SoCs. For me it only shows Wed Dec 31 23:59:59 1969 and for -others it is off by 3 minutes in 10 minutes running, this was reported -by multiple users. On the Linksys Mamba device the device tree comment -says that no crystal is connected to the internal RTC, this is probably -also true for the other devices. - -Signed-off-by: Hauke Mehrtens ---- - arch/arm/boot/dts/armada-385-linksys.dtsi | 5 +++++ - 1 file changed, 5 insertions(+) - ---- a/arch/arm/boot/dts/armada-385-linksys.dtsi -+++ b/arch/arm/boot/dts/armada-385-linksys.dtsi -@@ -304,3 +304,8 @@ - status = "okay"; - usb-phy = <&usb3_1_phy>; - }; -+ -+&rtc { -+ /* No crystal connected to the internal RTC */ -+ status = "disabled"; -+}; diff --git a/target/linux/mvebu/patches-4.14/450-reprobe_sfp_phy.patch b/target/linux/mvebu/patches-4.14/450-reprobe_sfp_phy.patch deleted file mode 100644 index b874d8265a79..000000000000 --- a/target/linux/mvebu/patches-4.14/450-reprobe_sfp_phy.patch +++ /dev/null @@ -1,94 +0,0 @@ -From 28baa5e2635285b178326b301f534ed95c65dd01 Mon Sep 17 00:00:00 2001 -From: Jonas Gorski -Date: Thu, 29 Sep 2016 11:44:39 +0200 -Subject: [PATCH] sfp: retry phy probe if unsuccessful - -Some phys seem to take longer than 50 ms to come out of reset, so retry -until we find a phy. - -Signed-off-by: Jonas Gorski ---- - drivers/net/phy/sfp.c | 38 +++++++++++++++++++++++++------------- - 1 file changed, 25 insertions(+), 13 deletions(-) - ---- a/drivers/net/phy/sfp.c -+++ b/drivers/net/phy/sfp.c -@@ -506,7 +506,7 @@ static void sfp_sm_phy_detach(struct sfp - sfp->mod_phy = NULL; - } - --static void sfp_sm_probe_phy(struct sfp *sfp) -+static int sfp_sm_probe_phy(struct sfp *sfp) - { - struct phy_device *phy; - int err; -@@ -516,11 +516,11 @@ static void sfp_sm_probe_phy(struct sfp - phy = mdiobus_scan(sfp->i2c_mii, SFP_PHY_ADDR); - if (phy == ERR_PTR(-ENODEV)) { - dev_info(sfp->dev, "no PHY detected\n"); -- return; -+ return -EAGAIN; - } - if (IS_ERR(phy)) { - dev_err(sfp->dev, "mdiobus scan returned %ld\n", PTR_ERR(phy)); -- return; -+ return PTR_ERR(phy); - } - - err = sfp_add_phy(sfp->sfp_bus, phy); -@@ -528,11 +528,13 @@ static void sfp_sm_probe_phy(struct sfp - phy_device_remove(phy); - phy_device_free(phy); - dev_err(sfp->dev, "sfp_add_phy failed: %d\n", err); -- return; -+ return err; - } - - sfp->mod_phy = phy; - phy_start(phy); -+ -+ return 0; - } - - static void sfp_sm_link_up(struct sfp *sfp) -@@ -578,14 +580,9 @@ static void sfp_sm_fault(struct sfp *sfp - - static void sfp_sm_mod_init(struct sfp *sfp) - { -- sfp_module_tx_enable(sfp); -+ int ret = 0; - -- /* Wait t_init before indicating that the link is up, provided the -- * current state indicates no TX_FAULT. If TX_FAULT clears before -- * this time, that's fine too. -- */ -- sfp_sm_next(sfp, SFP_S_INIT, T_INIT_JIFFIES); -- sfp->sm_retries = 5; -+ sfp_module_tx_enable(sfp); - - /* Setting the serdes link mode is guesswork: there's no - * field in the EEPROM which indicates what mode should -@@ -599,7 +596,22 @@ static void sfp_sm_mod_init(struct sfp * - if (sfp->id.base.e1000_base_t || - sfp->id.base.e100_base_lx || - sfp->id.base.e100_base_fx) -- sfp_sm_probe_phy(sfp); -+ ret = sfp_sm_probe_phy(sfp); -+ -+ if (!ret) { -+ /* Wait t_init before indicating that the link is up, provided -+ * the current state indicates no TX_FAULT. If TX_FAULT clears -+ * this time, that's fine too. -+ */ -+ sfp_sm_next(sfp, SFP_S_INIT, T_INIT_JIFFIES); -+ sfp->sm_retries = 5; -+ return; -+ } -+ -+ if (ret == -EAGAIN) -+ sfp_sm_set_timer(sfp, T_PROBE_RETRY); -+ else -+ sfp_sm_next(sfp, SFP_S_TX_DISABLE, 0); - } - - static int sfp_sm_mod_probe(struct sfp *sfp) diff --git a/target/linux/mvebu/patches-4.14/501-spi-a3700-Change-SPI-mode-before-asserting-chip-sele.patch b/target/linux/mvebu/patches-4.14/501-spi-a3700-Change-SPI-mode-before-asserting-chip-sele.patch deleted file mode 100644 index 3ac709118834..000000000000 --- a/target/linux/mvebu/patches-4.14/501-spi-a3700-Change-SPI-mode-before-asserting-chip-sele.patch +++ /dev/null @@ -1,70 +0,0 @@ -From dd7aa8d4b53b3484ba31ba56f3ff1be7deb38530 Mon Sep 17 00:00:00 2001 -From: Maxime Chevallier -Date: Tue, 10 Oct 2017 10:43:18 +0200 -Subject: spi: a3700: Change SPI mode before asserting chip-select - -The spi device mode should be configured in the controller before the -chip-select is asserted, so that a clock polarity configuration change -is not interpreted as a clock tick by the device. - -This patch moves the mode setting to the 'prepare_message' function -instead of the 'transfer_one' function. - -By doing so, this patch also removes redundant code in -a3700_spi_clock_set. - -This was tested on EspressoBin board, with spidev. - -Signed-off-by: Maxime Chevallier -Signed-off-by: Mark Brown ---- - drivers/spi/spi-armada-3700.c | 17 ++++------------- - 1 file changed, 4 insertions(+), 13 deletions(-) - ---- a/drivers/spi/spi-armada-3700.c -+++ b/drivers/spi/spi-armada-3700.c -@@ -214,7 +214,7 @@ static void a3700_spi_mode_set(struct a3 - } - - static void a3700_spi_clock_set(struct a3700_spi *a3700_spi, -- unsigned int speed_hz, u16 mode) -+ unsigned int speed_hz) - { - u32 val; - u32 prescale; -@@ -239,17 +239,6 @@ static void a3700_spi_clock_set(struct a - val |= A3700_SPI_CLK_CAPT_EDGE; - spireg_write(a3700_spi, A3700_SPI_IF_TIME_REG, val); - } -- -- val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); -- val &= ~(A3700_SPI_CLK_POL | A3700_SPI_CLK_PHA); -- -- if (mode & SPI_CPOL) -- val |= A3700_SPI_CLK_POL; -- -- if (mode & SPI_CPHA) -- val |= A3700_SPI_CLK_PHA; -- -- spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); - } - - static void a3700_spi_bytelen_set(struct a3700_spi *a3700_spi, unsigned int len) -@@ -431,7 +420,7 @@ static void a3700_spi_transfer_setup(str - - a3700_spi = spi_master_get_devdata(spi->master); - -- a3700_spi_clock_set(a3700_spi, xfer->speed_hz, spi->mode); -+ a3700_spi_clock_set(a3700_spi, xfer->speed_hz); - - byte_len = xfer->bits_per_word >> 3; - -@@ -592,6 +581,8 @@ static int a3700_spi_prepare_message(str - - a3700_spi_bytelen_set(a3700_spi, 4); - -+ a3700_spi_mode_set(a3700_spi, spi->mode); -+ - return 0; - } - diff --git a/target/linux/mvebu/patches-4.14/502-arm64-dts-marvell-armada-37xx-add-UART-clock.patch b/target/linux/mvebu/patches-4.14/502-arm64-dts-marvell-armada-37xx-add-UART-clock.patch deleted file mode 100644 index 47e0751c5f53..000000000000 --- a/target/linux/mvebu/patches-4.14/502-arm64-dts-marvell-armada-37xx-add-UART-clock.patch +++ /dev/null @@ -1,27 +0,0 @@ -From 2ff0d0b5bb397c3dc5c9b97bd0f20948f0b77740 Mon Sep 17 00:00:00 2001 -From: Miquel Raynal -Date: Fri, 13 Oct 2017 11:01:57 +0200 -Subject: arm64: dts: marvell: armada-37xx: add UART clock - -Add the missing clock property to armada-3700 UART node. - -This clock will be used to derive the prescaler value to comply with -the requested baudrate. - -Signed-off-by: Miquel Raynal -Acked-by: Gregory CLEMENT -Signed-off-by: Gregory CLEMENT ---- - arch/arm64/boot/dts/marvell/armada-37xx.dtsi | 1 + - 1 file changed, 1 insertion(+) - ---- a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi -+++ b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi -@@ -135,6 +135,7 @@ - uart0: serial@12000 { - compatible = "marvell,armada-3700-uart"; - reg = <0x12000 0x200>; -+ clocks = <&xtalclk>; - interrupts = ; - status = "disabled"; - }; diff --git a/target/linux/mvebu/patches-4.14/503-clk-mvebu-armada-37xx-periph-cosmetic-changes.patch b/target/linux/mvebu/patches-4.14/503-clk-mvebu-armada-37xx-periph-cosmetic-changes.patch deleted file mode 100644 index 7343e01d19ad..000000000000 --- a/target/linux/mvebu/patches-4.14/503-clk-mvebu-armada-37xx-periph-cosmetic-changes.patch +++ /dev/null @@ -1,78 +0,0 @@ -From adf4e289dd7f801c3fe12e0e6b491e11e548cd3d Mon Sep 17 00:00:00 2001 -From: Gregory CLEMENT -Date: Thu, 30 Nov 2017 14:40:27 +0100 -Subject: clk: mvebu: armada-37xx-periph: cosmetic changes - -This patches fixes few cosmetic issues such as alignment, blank lines -and required space. - -Signed-off-by: Gregory CLEMENT -Signed-off-by: Stephen Boyd ---- - drivers/clk/mvebu/armada-37xx-periph.c | 17 +++++++++-------- - 1 file changed, 9 insertions(+), 8 deletions(-) - ---- a/drivers/clk/mvebu/armada-37xx-periph.c -+++ b/drivers/clk/mvebu/armada-37xx-periph.c -@@ -79,6 +79,7 @@ static const struct clk_div_table clk_ta - { .val = 1, .div = 4, }, - { .val = 0, .div = 0, }, /* last entry */ - }; -+ - static const struct clk_ops clk_double_div_ops; - - #define PERIPH_GATE(_name, _bit) \ -@@ -217,7 +218,7 @@ PERIPH_CLK_FULL(counter, 23, 20, DIV_SEL - PERIPH_CLK_FULL_DD(eip97, 24, 24, DIV_SEL2, DIV_SEL2, 22, 19); - PERIPH_CLK_MUX_DIV(cpu, 22, DIV_SEL0, 28, clk_table6); - --static struct clk_periph_data data_nb[] ={ -+static struct clk_periph_data data_nb[] = { - REF_CLK_FULL_DD(mmc), - REF_CLK_FULL_DD(sata_host), - REF_CLK_FULL_DD(sec_at), -@@ -281,7 +282,7 @@ static unsigned int get_div(void __iomem - } - - static unsigned long clk_double_div_recalc_rate(struct clk_hw *hw, -- unsigned long parent_rate) -+ unsigned long parent_rate) - { - struct clk_double_div *double_div = to_clk_double_div(hw); - unsigned int div; -@@ -303,6 +304,7 @@ static const struct of_device_id armada_ - .data = data_sb, }, - { } - }; -+ - static int armada_3700_add_composite_clk(const struct clk_periph_data *data, - void __iomem *reg, spinlock_t *lock, - struct device *dev, struct clk_hw **hw) -@@ -355,9 +357,9 @@ static int armada_3700_add_composite_clk - } - - *hw = clk_hw_register_composite(dev, data->name, data->parent_names, -- data->num_parents, mux_hw, -- mux_ops, rate_hw, rate_ops, -- gate_hw, gate_ops, CLK_IGNORE_UNUSED); -+ data->num_parents, mux_hw, -+ mux_ops, rate_hw, rate_ops, -+ gate_hw, gate_ops, CLK_IGNORE_UNUSED); - - if (IS_ERR(*hw)) - return PTR_ERR(*hw); -@@ -406,12 +408,11 @@ static int armada_3700_periph_clock_prob - if (armada_3700_add_composite_clk(&data[i], reg, - &driver_data->lock, dev, hw)) - dev_err(dev, "Can't register periph clock %s\n", -- data[i].name); -- -+ data[i].name); - } - - ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, -- driver_data->hw_data); -+ driver_data->hw_data); - if (ret) { - for (i = 0; i < num_periph; i++) - clk_hw_unregister(driver_data->hw_data->hws[i]); diff --git a/target/linux/mvebu/patches-4.14/504-clk-mvebu-armada-37xx-periph-prepare-cpu-clk-to-be-u.patch b/target/linux/mvebu/patches-4.14/504-clk-mvebu-armada-37xx-periph-prepare-cpu-clk-to-be-u.patch deleted file mode 100644 index f9dec9f2ee0f..000000000000 --- a/target/linux/mvebu/patches-4.14/504-clk-mvebu-armada-37xx-periph-prepare-cpu-clk-to-be-u.patch +++ /dev/null @@ -1,178 +0,0 @@ -From 9818a7a4fd10f72537cdf2a5ec3402f2c245ea24 Mon Sep 17 00:00:00 2001 -From: Gregory CLEMENT -Date: Thu, 30 Nov 2017 14:40:28 +0100 -Subject: clk: mvebu: armada-37xx-periph: prepare cpu clk to be - used with DVFS - -When DVFS will be enabled then the cpu clk will use a different set of -register at run time. That means that we won't be able to use the common -callback and need to use our own ones. - -This patch prepares this change by switching on our own set of callbacks -without modifying the behavior of the clocks. - -Signed-off-by: Gregory CLEMENT -Signed-off-by: Stephen Boyd ---- - drivers/clk/mvebu/armada-37xx-periph.c | 82 ++++++++++++++++++++++++++++++---- - 1 file changed, 73 insertions(+), 9 deletions(-) - ---- a/drivers/clk/mvebu/armada-37xx-periph.c -+++ b/drivers/clk/mvebu/armada-37xx-periph.c -@@ -46,7 +46,17 @@ struct clk_double_div { - u8 shift2; - }; - -+struct clk_pm_cpu { -+ struct clk_hw hw; -+ void __iomem *reg_mux; -+ u8 shift_mux; -+ u32 mask_mux; -+ void __iomem *reg_div; -+ u8 shift_div; -+}; -+ - #define to_clk_double_div(_hw) container_of(_hw, struct clk_double_div, hw) -+#define to_clk_pm_cpu(_hw) container_of(_hw, struct clk_pm_cpu, hw) - - struct clk_periph_data { - const char *name; -@@ -55,6 +65,7 @@ struct clk_periph_data { - struct clk_hw *mux_hw; - struct clk_hw *rate_hw; - struct clk_hw *gate_hw; -+ struct clk_hw *muxrate_hw; - bool is_double_div; - }; - -@@ -81,6 +92,7 @@ static const struct clk_div_table clk_ta - }; - - static const struct clk_ops clk_double_div_ops; -+static const struct clk_ops clk_pm_cpu_ops; - - #define PERIPH_GATE(_name, _bit) \ - struct clk_gate gate_##_name = { \ -@@ -122,6 +134,18 @@ struct clk_divider rate_##_name = { \ - } \ - }; - -+#define PERIPH_PM_CPU(_name, _shift1, _reg, _shift2) \ -+struct clk_pm_cpu muxrate_##_name = { \ -+ .reg_mux = (void *)TBG_SEL, \ -+ .mask_mux = 3, \ -+ .shift_mux = _shift1, \ -+ .reg_div = (void *)_reg, \ -+ .shift_div = _shift2, \ -+ .hw.init = &(struct clk_init_data){ \ -+ .ops = &clk_pm_cpu_ops, \ -+ } \ -+}; -+ - #define PERIPH_CLK_FULL_DD(_name, _bit, _shift, _reg1, _reg2, _shift1, _shift2)\ - static PERIPH_GATE(_name, _bit); \ - static PERIPH_MUX(_name, _shift); \ -@@ -136,10 +160,6 @@ static PERIPH_DIV(_name, _reg, _shift1, - static PERIPH_GATE(_name, _bit); \ - static PERIPH_DIV(_name, _reg, _shift, _table); - --#define PERIPH_CLK_MUX_DIV(_name, _shift, _reg, _shift_div, _table) \ --static PERIPH_MUX(_name, _shift); \ --static PERIPH_DIV(_name, _reg, _shift_div, _table); -- - #define PERIPH_CLK_MUX_DD(_name, _shift, _reg1, _reg2, _shift1, _shift2)\ - static PERIPH_MUX(_name, _shift); \ - static PERIPH_DOUBLEDIV(_name, _reg1, _reg2, _shift1, _shift2); -@@ -180,13 +200,12 @@ static PERIPH_DOUBLEDIV(_name, _reg1, _r - .rate_hw = &rate_##_name.hw, \ - } - --#define REF_CLK_MUX_DIV(_name) \ -+#define REF_CLK_PM_CPU(_name) \ - { .name = #_name, \ - .parent_names = (const char *[]){ "TBG-A-P", \ - "TBG-B-P", "TBG-A-S", "TBG-B-S"}, \ - .num_parents = 4, \ -- .mux_hw = &mux_##_name.hw, \ -- .rate_hw = &rate_##_name.hw, \ -+ .muxrate_hw = &muxrate_##_name.hw, \ - } - - #define REF_CLK_MUX_DD(_name) \ -@@ -216,7 +235,7 @@ PERIPH_CLK_FULL_DD(ddr_fclk, 21, 16, DIV - PERIPH_CLK_FULL(trace, 22, 18, DIV_SEL0, 20, clk_table6); - PERIPH_CLK_FULL(counter, 23, 20, DIV_SEL0, 23, clk_table6); - PERIPH_CLK_FULL_DD(eip97, 24, 24, DIV_SEL2, DIV_SEL2, 22, 19); --PERIPH_CLK_MUX_DIV(cpu, 22, DIV_SEL0, 28, clk_table6); -+static PERIPH_PM_CPU(cpu, 22, DIV_SEL0, 28); - - static struct clk_periph_data data_nb[] = { - REF_CLK_FULL_DD(mmc), -@@ -235,7 +254,7 @@ static struct clk_periph_data data_nb[] - REF_CLK_FULL(trace), - REF_CLK_FULL(counter), - REF_CLK_FULL_DD(eip97), -- REF_CLK_MUX_DIV(cpu), -+ REF_CLK_PM_CPU(cpu), - { }, - }; - -@@ -297,6 +316,37 @@ static const struct clk_ops clk_double_d - .recalc_rate = clk_double_div_recalc_rate, - }; - -+static u8 clk_pm_cpu_get_parent(struct clk_hw *hw) -+{ -+ struct clk_pm_cpu *pm_cpu = to_clk_pm_cpu(hw); -+ int num_parents = clk_hw_get_num_parents(hw); -+ u32 val; -+ -+ val = readl(pm_cpu->reg_mux) >> pm_cpu->shift_mux; -+ val &= pm_cpu->mask_mux; -+ -+ if (val >= num_parents) -+ return -EINVAL; -+ -+ return val; -+} -+ -+static unsigned long clk_pm_cpu_recalc_rate(struct clk_hw *hw, -+ unsigned long parent_rate) -+{ -+ struct clk_pm_cpu *pm_cpu = to_clk_pm_cpu(hw); -+ unsigned int div; -+ -+ div = get_div(pm_cpu->reg_div, pm_cpu->shift_div); -+ -+ return DIV_ROUND_UP_ULL((u64)parent_rate, div); -+} -+ -+static const struct clk_ops clk_pm_cpu_ops = { -+ .get_parent = clk_pm_cpu_get_parent, -+ .recalc_rate = clk_pm_cpu_recalc_rate, -+}; -+ - static const struct of_device_id armada_3700_periph_clock_of_match[] = { - { .compatible = "marvell,armada-3700-periph-clock-nb", - .data = data_nb, }, -@@ -356,6 +406,20 @@ static int armada_3700_add_composite_clk - } - } - -+ if (data->muxrate_hw) { -+ struct clk_pm_cpu *pmcpu_clk; -+ struct clk_hw *muxrate_hw = data->muxrate_hw; -+ -+ pmcpu_clk = to_clk_pm_cpu(muxrate_hw); -+ pmcpu_clk->reg_mux = reg + (u64)pmcpu_clk->reg_mux; -+ pmcpu_clk->reg_div = reg + (u64)pmcpu_clk->reg_div; -+ -+ mux_hw = muxrate_hw; -+ rate_hw = muxrate_hw; -+ mux_ops = muxrate_hw->init->ops; -+ rate_ops = muxrate_hw->init->ops; -+ } -+ - *hw = clk_hw_register_composite(dev, data->name, data->parent_names, - data->num_parents, mux_hw, - mux_ops, rate_hw, rate_ops, diff --git a/target/linux/mvebu/patches-4.14/505-clk-mvebu-armada-37xx-periph-add-DVFS-support-for-cp.patch b/target/linux/mvebu/patches-4.14/505-clk-mvebu-armada-37xx-periph-add-DVFS-support-for-cp.patch deleted file mode 100644 index 2065e788afe3..000000000000 --- a/target/linux/mvebu/patches-4.14/505-clk-mvebu-armada-37xx-periph-add-DVFS-support-for-cp.patch +++ /dev/null @@ -1,315 +0,0 @@ -From 2089dc33ea0e3917465929d4020fbff3d6dbf7f4 Mon Sep 17 00:00:00 2001 -From: Gregory CLEMENT -Date: Thu, 30 Nov 2017 14:40:29 +0100 -Subject: clk: mvebu: armada-37xx-periph: add DVFS support for cpu clocks - -When DVFS is enabled the CPU clock setting is done using an other set of -registers. - -These Power Management registers are exposed through a syscon as they -will also be used by other drivers such as the cpufreq. - -This patch add the possibility to modify the CPU frequency using the -associate load level matching the target frequency. Then all the -frequency switch is handle by the hardware. - -Signed-off-by: Gregory CLEMENT -[sboyd@codeaurora.org: Grow a local variable for regmap pointer -to keep lines shorter] -Signed-off-by: Stephen Boyd ---- - drivers/clk/mvebu/armada-37xx-periph.c | 221 ++++++++++++++++++++++++++++++++- - 1 file changed, 217 insertions(+), 4 deletions(-) - ---- a/drivers/clk/mvebu/armada-37xx-periph.c -+++ b/drivers/clk/mvebu/armada-37xx-periph.c -@@ -21,9 +21,11 @@ - */ - - #include -+#include - #include - #include - #include -+#include - #include - - #define TBG_SEL 0x0 -@@ -33,6 +35,26 @@ - #define CLK_SEL 0x10 - #define CLK_DIS 0x14 - -+#define LOAD_LEVEL_NR 4 -+ -+#define ARMADA_37XX_NB_L0L1 0x18 -+#define ARMADA_37XX_NB_L2L3 0x1C -+#define ARMADA_37XX_NB_TBG_DIV_OFF 13 -+#define ARMADA_37XX_NB_TBG_DIV_MASK 0x7 -+#define ARMADA_37XX_NB_CLK_SEL_OFF 11 -+#define ARMADA_37XX_NB_CLK_SEL_MASK 0x1 -+#define ARMADA_37XX_NB_TBG_SEL_OFF 9 -+#define ARMADA_37XX_NB_TBG_SEL_MASK 0x3 -+#define ARMADA_37XX_NB_CONFIG_SHIFT 16 -+#define ARMADA_37XX_NB_DYN_MOD 0x24 -+#define ARMADA_37XX_NB_DFS_EN 31 -+#define ARMADA_37XX_NB_CPU_LOAD 0x30 -+#define ARMADA_37XX_NB_CPU_LOAD_MASK 0x3 -+#define ARMADA_37XX_DVFS_LOAD_0 0 -+#define ARMADA_37XX_DVFS_LOAD_1 1 -+#define ARMADA_37XX_DVFS_LOAD_2 2 -+#define ARMADA_37XX_DVFS_LOAD_3 3 -+ - struct clk_periph_driver_data { - struct clk_hw_onecell_data *hw_data; - spinlock_t lock; -@@ -53,6 +75,7 @@ struct clk_pm_cpu { - u32 mask_mux; - void __iomem *reg_div; - u8 shift_div; -+ struct regmap *nb_pm_base; - }; - - #define to_clk_double_div(_hw) container_of(_hw, struct clk_double_div, hw) -@@ -316,14 +339,94 @@ static const struct clk_ops clk_double_d - .recalc_rate = clk_double_div_recalc_rate, - }; - -+static void armada_3700_pm_dvfs_update_regs(unsigned int load_level, -+ unsigned int *reg, -+ unsigned int *offset) -+{ -+ if (load_level <= ARMADA_37XX_DVFS_LOAD_1) -+ *reg = ARMADA_37XX_NB_L0L1; -+ else -+ *reg = ARMADA_37XX_NB_L2L3; -+ -+ if (load_level == ARMADA_37XX_DVFS_LOAD_0 || -+ load_level == ARMADA_37XX_DVFS_LOAD_2) -+ *offset += ARMADA_37XX_NB_CONFIG_SHIFT; -+} -+ -+static bool armada_3700_pm_dvfs_is_enabled(struct regmap *base) -+{ -+ unsigned int val, reg = ARMADA_37XX_NB_DYN_MOD; -+ -+ if (IS_ERR(base)) -+ return false; -+ -+ regmap_read(base, reg, &val); -+ -+ return !!(val & BIT(ARMADA_37XX_NB_DFS_EN)); -+} -+ -+static unsigned int armada_3700_pm_dvfs_get_cpu_div(struct regmap *base) -+{ -+ unsigned int reg = ARMADA_37XX_NB_CPU_LOAD; -+ unsigned int offset = ARMADA_37XX_NB_TBG_DIV_OFF; -+ unsigned int load_level, div; -+ -+ /* -+ * This function is always called after the function -+ * armada_3700_pm_dvfs_is_enabled, so no need to check again -+ * if the base is valid. -+ */ -+ regmap_read(base, reg, &load_level); -+ -+ /* -+ * The register and the offset inside this register accessed to -+ * read the current divider depend on the load level -+ */ -+ load_level &= ARMADA_37XX_NB_CPU_LOAD_MASK; -+ armada_3700_pm_dvfs_update_regs(load_level, ®, &offset); -+ -+ regmap_read(base, reg, &div); -+ -+ return (div >> offset) & ARMADA_37XX_NB_TBG_DIV_MASK; -+} -+ -+static unsigned int armada_3700_pm_dvfs_get_cpu_parent(struct regmap *base) -+{ -+ unsigned int reg = ARMADA_37XX_NB_CPU_LOAD; -+ unsigned int offset = ARMADA_37XX_NB_TBG_SEL_OFF; -+ unsigned int load_level, sel; -+ -+ /* -+ * This function is always called after the function -+ * armada_3700_pm_dvfs_is_enabled, so no need to check again -+ * if the base is valid -+ */ -+ regmap_read(base, reg, &load_level); -+ -+ /* -+ * The register and the offset inside this register accessed to -+ * read the current divider depend on the load level -+ */ -+ load_level &= ARMADA_37XX_NB_CPU_LOAD_MASK; -+ armada_3700_pm_dvfs_update_regs(load_level, ®, &offset); -+ -+ regmap_read(base, reg, &sel); -+ -+ return (sel >> offset) & ARMADA_37XX_NB_TBG_SEL_MASK; -+} -+ - static u8 clk_pm_cpu_get_parent(struct clk_hw *hw) - { - struct clk_pm_cpu *pm_cpu = to_clk_pm_cpu(hw); - int num_parents = clk_hw_get_num_parents(hw); - u32 val; - -- val = readl(pm_cpu->reg_mux) >> pm_cpu->shift_mux; -- val &= pm_cpu->mask_mux; -+ if (armada_3700_pm_dvfs_is_enabled(pm_cpu->nb_pm_base)) { -+ val = armada_3700_pm_dvfs_get_cpu_parent(pm_cpu->nb_pm_base); -+ } else { -+ val = readl(pm_cpu->reg_mux) >> pm_cpu->shift_mux; -+ val &= pm_cpu->mask_mux; -+ } - - if (val >= num_parents) - return -EINVAL; -@@ -331,19 +434,124 @@ static u8 clk_pm_cpu_get_parent(struct c - return val; - } - -+static int clk_pm_cpu_set_parent(struct clk_hw *hw, u8 index) -+{ -+ struct clk_pm_cpu *pm_cpu = to_clk_pm_cpu(hw); -+ struct regmap *base = pm_cpu->nb_pm_base; -+ int load_level; -+ -+ /* -+ * We set the clock parent only if the DVFS is available but -+ * not enabled. -+ */ -+ if (IS_ERR(base) || armada_3700_pm_dvfs_is_enabled(base)) -+ return -EINVAL; -+ -+ /* Set the parent clock for all the load level */ -+ for (load_level = 0; load_level < LOAD_LEVEL_NR; load_level++) { -+ unsigned int reg, mask, val, -+ offset = ARMADA_37XX_NB_TBG_SEL_OFF; -+ -+ armada_3700_pm_dvfs_update_regs(load_level, ®, &offset); -+ -+ val = index << offset; -+ mask = ARMADA_37XX_NB_TBG_SEL_MASK << offset; -+ regmap_update_bits(base, reg, mask, val); -+ } -+ return 0; -+} -+ - static unsigned long clk_pm_cpu_recalc_rate(struct clk_hw *hw, - unsigned long parent_rate) - { - struct clk_pm_cpu *pm_cpu = to_clk_pm_cpu(hw); - unsigned int div; - -- div = get_div(pm_cpu->reg_div, pm_cpu->shift_div); -- -+ if (armada_3700_pm_dvfs_is_enabled(pm_cpu->nb_pm_base)) -+ div = armada_3700_pm_dvfs_get_cpu_div(pm_cpu->nb_pm_base); -+ else -+ div = get_div(pm_cpu->reg_div, pm_cpu->shift_div); - return DIV_ROUND_UP_ULL((u64)parent_rate, div); - } - -+static long clk_pm_cpu_round_rate(struct clk_hw *hw, unsigned long rate, -+ unsigned long *parent_rate) -+{ -+ struct clk_pm_cpu *pm_cpu = to_clk_pm_cpu(hw); -+ struct regmap *base = pm_cpu->nb_pm_base; -+ unsigned int div = *parent_rate / rate; -+ unsigned int load_level; -+ /* only available when DVFS is enabled */ -+ if (!armada_3700_pm_dvfs_is_enabled(base)) -+ return -EINVAL; -+ -+ for (load_level = 0; load_level < LOAD_LEVEL_NR; load_level++) { -+ unsigned int reg, val, offset = ARMADA_37XX_NB_TBG_DIV_OFF; -+ -+ armada_3700_pm_dvfs_update_regs(load_level, ®, &offset); -+ -+ regmap_read(base, reg, &val); -+ -+ val >>= offset; -+ val &= ARMADA_37XX_NB_TBG_DIV_MASK; -+ if (val == div) -+ /* -+ * We found a load level matching the target -+ * divider, switch to this load level and -+ * return. -+ */ -+ return *parent_rate / div; -+ } -+ -+ /* We didn't find any valid divider */ -+ return -EINVAL; -+} -+ -+static int clk_pm_cpu_set_rate(struct clk_hw *hw, unsigned long rate, -+ unsigned long parent_rate) -+{ -+ struct clk_pm_cpu *pm_cpu = to_clk_pm_cpu(hw); -+ struct regmap *base = pm_cpu->nb_pm_base; -+ unsigned int div = parent_rate / rate; -+ unsigned int load_level; -+ -+ /* only available when DVFS is enabled */ -+ if (!armada_3700_pm_dvfs_is_enabled(base)) -+ return -EINVAL; -+ -+ for (load_level = 0; load_level < LOAD_LEVEL_NR; load_level++) { -+ unsigned int reg, mask, val, -+ offset = ARMADA_37XX_NB_TBG_DIV_OFF; -+ -+ armada_3700_pm_dvfs_update_regs(load_level, ®, &offset); -+ -+ regmap_read(base, reg, &val); -+ val >>= offset; -+ val &= ARMADA_37XX_NB_TBG_DIV_MASK; -+ -+ if (val == div) { -+ /* -+ * We found a load level matching the target -+ * divider, switch to this load level and -+ * return. -+ */ -+ reg = ARMADA_37XX_NB_CPU_LOAD; -+ mask = ARMADA_37XX_NB_CPU_LOAD_MASK; -+ regmap_update_bits(base, reg, mask, load_level); -+ -+ return rate; -+ } -+ } -+ -+ /* We didn't find any valid divider */ -+ return -EINVAL; -+} -+ - static const struct clk_ops clk_pm_cpu_ops = { - .get_parent = clk_pm_cpu_get_parent, -+ .set_parent = clk_pm_cpu_set_parent, -+ .round_rate = clk_pm_cpu_round_rate, -+ .set_rate = clk_pm_cpu_set_rate, - .recalc_rate = clk_pm_cpu_recalc_rate, - }; - -@@ -409,6 +617,7 @@ static int armada_3700_add_composite_clk - if (data->muxrate_hw) { - struct clk_pm_cpu *pmcpu_clk; - struct clk_hw *muxrate_hw = data->muxrate_hw; -+ struct regmap *map; - - pmcpu_clk = to_clk_pm_cpu(muxrate_hw); - pmcpu_clk->reg_mux = reg + (u64)pmcpu_clk->reg_mux; -@@ -418,6 +627,10 @@ static int armada_3700_add_composite_clk - rate_hw = muxrate_hw; - mux_ops = muxrate_hw->init->ops; - rate_ops = muxrate_hw->init->ops; -+ -+ map = syscon_regmap_lookup_by_compatible( -+ "marvell,armada-3700-nb-pm"); -+ pmcpu_clk->nb_pm_base = map; - } - - *hw = clk_hw_register_composite(dev, data->name, data->parent_names, diff --git a/target/linux/mvebu/patches-4.14/506-cpufreq-Add-DVFS-support-for-Armada-37xx.patch b/target/linux/mvebu/patches-4.14/506-cpufreq-Add-DVFS-support-for-Armada-37xx.patch deleted file mode 100644 index 11562c582b4a..000000000000 --- a/target/linux/mvebu/patches-4.14/506-cpufreq-Add-DVFS-support-for-Armada-37xx.patch +++ /dev/null @@ -1,297 +0,0 @@ -From 92ce45fb875d7c3e021cc454482fe0687ff54f29 Mon Sep 17 00:00:00 2001 -From: Gregory CLEMENT -Date: Thu, 14 Dec 2017 16:00:05 +0100 -Subject: cpufreq: Add DVFS support for Armada 37xx - -This patch adds DVFS support for the Armada 37xx SoCs - -There are up to four CPU frequency loads for Armada 37xx controlled by -the hardware. - -This driver associates the CPU load level to a frequency, then the -hardware will switch while selecting a load level. - -The hardware also can associate a voltage for each level (AVS support) -but it is not yet supported - -Tested-by: Andre Heider -Acked-by: Viresh Kumar -Signed-off-by: Gregory CLEMENT -Signed-off-by: Rafael J. Wysocki ---- - drivers/cpufreq/Kconfig.arm | 7 + - drivers/cpufreq/Makefile | 1 + - drivers/cpufreq/armada-37xx-cpufreq.c | 241 ++++++++++++++++++++++++++++++++++ - 3 files changed, 249 insertions(+) - create mode 100644 drivers/cpufreq/armada-37xx-cpufreq.c - ---- a/drivers/cpufreq/Kconfig.arm -+++ b/drivers/cpufreq/Kconfig.arm -@@ -2,6 +2,13 @@ - # ARM CPU Frequency scaling drivers - # - -+config ARM_ARMADA_37XX_CPUFREQ -+ tristate "Armada 37xx CPUFreq support" -+ depends on ARCH_MVEBU -+ help -+ This adds the CPUFreq driver support for Marvell Armada 37xx SoCs. -+ The Armada 37xx PMU supports 4 frequency and VDD levels. -+ - # big LITTLE core layer and glue drivers - config ARM_BIG_LITTLE_CPUFREQ - tristate "Generic ARM big LITTLE CPUfreq driver" ---- a/drivers/cpufreq/Makefile -+++ b/drivers/cpufreq/Makefile -@@ -52,6 +52,7 @@ obj-$(CONFIG_ARM_BIG_LITTLE_CPUFREQ) += - # LITTLE drivers, so that it is probed last. - obj-$(CONFIG_ARM_DT_BL_CPUFREQ) += arm_big_little_dt.o - -+obj-$(CONFIG_ARM_ARMADA_37XX_CPUFREQ) += armada-37xx-cpufreq.o - obj-$(CONFIG_ARM_BRCMSTB_AVS_CPUFREQ) += brcmstb-avs-cpufreq.o - obj-$(CONFIG_ARCH_DAVINCI) += davinci-cpufreq.o - obj-$(CONFIG_ARM_EXYNOS5440_CPUFREQ) += exynos5440-cpufreq.o ---- /dev/null -+++ b/drivers/cpufreq/armada-37xx-cpufreq.c -@@ -0,0 +1,241 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * CPU frequency scaling support for Armada 37xx platform. -+ * -+ * Copyright (C) 2017 Marvell -+ * -+ * Gregory CLEMENT -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+/* Power management in North Bridge register set */ -+#define ARMADA_37XX_NB_L0L1 0x18 -+#define ARMADA_37XX_NB_L2L3 0x1C -+#define ARMADA_37XX_NB_TBG_DIV_OFF 13 -+#define ARMADA_37XX_NB_TBG_DIV_MASK 0x7 -+#define ARMADA_37XX_NB_CLK_SEL_OFF 11 -+#define ARMADA_37XX_NB_CLK_SEL_MASK 0x1 -+#define ARMADA_37XX_NB_CLK_SEL_TBG 0x1 -+#define ARMADA_37XX_NB_TBG_SEL_OFF 9 -+#define ARMADA_37XX_NB_TBG_SEL_MASK 0x3 -+#define ARMADA_37XX_NB_VDD_SEL_OFF 6 -+#define ARMADA_37XX_NB_VDD_SEL_MASK 0x3 -+#define ARMADA_37XX_NB_CONFIG_SHIFT 16 -+#define ARMADA_37XX_NB_DYN_MOD 0x24 -+#define ARMADA_37XX_NB_CLK_SEL_EN BIT(26) -+#define ARMADA_37XX_NB_TBG_EN BIT(28) -+#define ARMADA_37XX_NB_DIV_EN BIT(29) -+#define ARMADA_37XX_NB_VDD_EN BIT(30) -+#define ARMADA_37XX_NB_DFS_EN BIT(31) -+#define ARMADA_37XX_NB_CPU_LOAD 0x30 -+#define ARMADA_37XX_NB_CPU_LOAD_MASK 0x3 -+#define ARMADA_37XX_DVFS_LOAD_0 0 -+#define ARMADA_37XX_DVFS_LOAD_1 1 -+#define ARMADA_37XX_DVFS_LOAD_2 2 -+#define ARMADA_37XX_DVFS_LOAD_3 3 -+ -+/* -+ * On Armada 37xx the Power management manages 4 level of CPU load, -+ * each level can be associated with a CPU clock source, a CPU -+ * divider, a VDD level, etc... -+ */ -+#define LOAD_LEVEL_NR 4 -+ -+struct armada_37xx_dvfs { -+ u32 cpu_freq_max; -+ u8 divider[LOAD_LEVEL_NR]; -+}; -+ -+static struct armada_37xx_dvfs armada_37xx_dvfs[] = { -+ {.cpu_freq_max = 1200*1000*1000, .divider = {1, 2, 4, 6} }, -+ {.cpu_freq_max = 1000*1000*1000, .divider = {1, 2, 4, 5} }, -+ {.cpu_freq_max = 800*1000*1000, .divider = {1, 2, 3, 4} }, -+ {.cpu_freq_max = 600*1000*1000, .divider = {2, 4, 5, 6} }, -+}; -+ -+static struct armada_37xx_dvfs *armada_37xx_cpu_freq_info_get(u32 freq) -+{ -+ int i; -+ -+ for (i = 0; i < ARRAY_SIZE(armada_37xx_dvfs); i++) { -+ if (freq == armada_37xx_dvfs[i].cpu_freq_max) -+ return &armada_37xx_dvfs[i]; -+ } -+ -+ pr_err("Unsupported CPU frequency %d MHz\n", freq/1000000); -+ return NULL; -+} -+ -+/* -+ * Setup the four level managed by the hardware. Once the four level -+ * will be configured then the DVFS will be enabled. -+ */ -+static void __init armada37xx_cpufreq_dvfs_setup(struct regmap *base, -+ struct clk *clk, u8 *divider) -+{ -+ int load_lvl; -+ struct clk *parent; -+ -+ for (load_lvl = 0; load_lvl < LOAD_LEVEL_NR; load_lvl++) { -+ unsigned int reg, mask, val, offset = 0; -+ -+ if (load_lvl <= ARMADA_37XX_DVFS_LOAD_1) -+ reg = ARMADA_37XX_NB_L0L1; -+ else -+ reg = ARMADA_37XX_NB_L2L3; -+ -+ if (load_lvl == ARMADA_37XX_DVFS_LOAD_0 || -+ load_lvl == ARMADA_37XX_DVFS_LOAD_2) -+ offset += ARMADA_37XX_NB_CONFIG_SHIFT; -+ -+ /* Set cpu clock source, for all the level we use TBG */ -+ val = ARMADA_37XX_NB_CLK_SEL_TBG << ARMADA_37XX_NB_CLK_SEL_OFF; -+ mask = (ARMADA_37XX_NB_CLK_SEL_MASK -+ << ARMADA_37XX_NB_CLK_SEL_OFF); -+ -+ /* -+ * Set cpu divider based on the pre-computed array in -+ * order to have balanced step. -+ */ -+ val |= divider[load_lvl] << ARMADA_37XX_NB_TBG_DIV_OFF; -+ mask |= (ARMADA_37XX_NB_TBG_DIV_MASK -+ << ARMADA_37XX_NB_TBG_DIV_OFF); -+ -+ /* Set VDD divider which is actually the load level. */ -+ val |= load_lvl << ARMADA_37XX_NB_VDD_SEL_OFF; -+ mask |= (ARMADA_37XX_NB_VDD_SEL_MASK -+ << ARMADA_37XX_NB_VDD_SEL_OFF); -+ -+ val <<= offset; -+ mask <<= offset; -+ -+ regmap_update_bits(base, reg, mask, val); -+ } -+ -+ /* -+ * Set cpu clock source, for all the level we keep the same -+ * clock source that the one already configured. For this one -+ * we need to use the clock framework -+ */ -+ parent = clk_get_parent(clk); -+ clk_set_parent(clk, parent); -+} -+ -+static void __init armada37xx_cpufreq_disable_dvfs(struct regmap *base) -+{ -+ unsigned int reg = ARMADA_37XX_NB_DYN_MOD, -+ mask = ARMADA_37XX_NB_DFS_EN; -+ -+ regmap_update_bits(base, reg, mask, 0); -+} -+ -+static void __init armada37xx_cpufreq_enable_dvfs(struct regmap *base) -+{ -+ unsigned int val, reg = ARMADA_37XX_NB_CPU_LOAD, -+ mask = ARMADA_37XX_NB_CPU_LOAD_MASK; -+ -+ /* Start with the highest load (0) */ -+ val = ARMADA_37XX_DVFS_LOAD_0; -+ regmap_update_bits(base, reg, mask, val); -+ -+ /* Now enable DVFS for the CPUs */ -+ reg = ARMADA_37XX_NB_DYN_MOD; -+ mask = ARMADA_37XX_NB_CLK_SEL_EN | ARMADA_37XX_NB_TBG_EN | -+ ARMADA_37XX_NB_DIV_EN | ARMADA_37XX_NB_VDD_EN | -+ ARMADA_37XX_NB_DFS_EN; -+ -+ regmap_update_bits(base, reg, mask, mask); -+} -+ -+static int __init armada37xx_cpufreq_driver_init(void) -+{ -+ struct armada_37xx_dvfs *dvfs; -+ struct platform_device *pdev; -+ unsigned int cur_frequency; -+ struct regmap *nb_pm_base; -+ struct device *cpu_dev; -+ int load_lvl, ret; -+ struct clk *clk; -+ -+ nb_pm_base = -+ syscon_regmap_lookup_by_compatible("marvell,armada-3700-nb-pm"); -+ -+ if (IS_ERR(nb_pm_base)) -+ return -ENODEV; -+ -+ /* Before doing any configuration on the DVFS first, disable it */ -+ armada37xx_cpufreq_disable_dvfs(nb_pm_base); -+ -+ /* -+ * On CPU 0 register the operating points supported (which are -+ * the nominal CPU frequency and full integer divisions of -+ * it). -+ */ -+ cpu_dev = get_cpu_device(0); -+ if (!cpu_dev) { -+ dev_err(cpu_dev, "Cannot get CPU\n"); -+ return -ENODEV; -+ } -+ -+ clk = clk_get(cpu_dev, 0); -+ if (IS_ERR(clk)) { -+ dev_err(cpu_dev, "Cannot get clock for CPU0\n"); -+ return PTR_ERR(clk); -+ } -+ -+ /* Get nominal (current) CPU frequency */ -+ cur_frequency = clk_get_rate(clk); -+ if (!cur_frequency) { -+ dev_err(cpu_dev, "Failed to get clock rate for CPU\n"); -+ return -EINVAL; -+ } -+ -+ dvfs = armada_37xx_cpu_freq_info_get(cur_frequency); -+ if (!dvfs) -+ return -EINVAL; -+ -+ armada37xx_cpufreq_dvfs_setup(nb_pm_base, clk, dvfs->divider); -+ -+ for (load_lvl = ARMADA_37XX_DVFS_LOAD_0; load_lvl < LOAD_LEVEL_NR; -+ load_lvl++) { -+ unsigned long freq = cur_frequency / dvfs->divider[load_lvl]; -+ -+ ret = dev_pm_opp_add(cpu_dev, freq, 0); -+ if (ret) { -+ /* clean-up the already added opp before leaving */ -+ while (load_lvl-- > ARMADA_37XX_DVFS_LOAD_0) { -+ freq = cur_frequency / dvfs->divider[load_lvl]; -+ dev_pm_opp_remove(cpu_dev, freq); -+ } -+ return ret; -+ } -+ } -+ -+ /* Now that everything is setup, enable the DVFS at hardware level */ -+ armada37xx_cpufreq_enable_dvfs(nb_pm_base); -+ -+ pdev = platform_device_register_simple("cpufreq-dt", -1, NULL, 0); -+ -+ return PTR_ERR_OR_ZERO(pdev); -+} -+/* late_initcall, to guarantee the driver is loaded after A37xx clock driver */ -+late_initcall(armada37xx_cpufreq_driver_init); -+ -+MODULE_AUTHOR("Gregory CLEMENT "); -+MODULE_DESCRIPTION("Armada 37xx cpufreq driver"); -+MODULE_LICENSE("GPL"); diff --git a/target/linux/mvebu/patches-4.14/507-arm64-dts-marvell-armada-37xx-add-nodes-allowing-cpu.patch b/target/linux/mvebu/patches-4.14/507-arm64-dts-marvell-armada-37xx-add-nodes-allowing-cpu.patch deleted file mode 100644 index dd3727c554ce..000000000000 --- a/target/linux/mvebu/patches-4.14/507-arm64-dts-marvell-armada-37xx-add-nodes-allowing-cpu.patch +++ /dev/null @@ -1,48 +0,0 @@ -From e8d66e7927b2a15310df0eb44a67d120ea147a59 Mon Sep 17 00:00:00 2001 -From: Gregory CLEMENT -Date: Thu, 14 Dec 2017 16:00:06 +0100 -Subject: arm64: dts: marvell: armada-37xx: add nodes allowing cpufreq - support - -In order to be able to use cpu freq, we need to associate a clock to each -CPU and to expose the power management registers. - -Signed-off-by: Gregory CLEMENT ---- - arch/arm64/boot/dts/marvell/armada-372x.dtsi | 1 + - arch/arm64/boot/dts/marvell/armada-37xx.dtsi | 7 +++++++ - 2 files changed, 8 insertions(+) - ---- a/arch/arm64/boot/dts/marvell/armada-372x.dtsi -+++ b/arch/arm64/boot/dts/marvell/armada-372x.dtsi -@@ -56,6 +56,7 @@ - device_type = "cpu"; - compatible = "arm,cortex-a53","arm,armv8"; - reg = <0x1>; -+ clocks = <&nb_periph_clk 16>; - enable-method = "psci"; - }; - }; ---- a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi -+++ b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi -@@ -64,6 +64,7 @@ - device_type = "cpu"; - compatible = "arm,cortex-a53", "arm,armv8"; - reg = <0>; -+ clocks = <&nb_periph_clk 16>; - enable-method = "psci"; - }; - }; -@@ -219,6 +220,12 @@ - }; - }; - -+ nb_pm: syscon@14000 { -+ compatible = "marvell,armada-3700-nb-pm", -+ "syscon"; -+ reg = <0x14000 0x60>; -+ }; -+ - pinctrl_sb: pinctrl@18800 { - compatible = "marvell,armada3710-sb-pinctrl", - "syscon", "simple-mfd"; diff --git a/target/linux/mvebu/patches-4.14/508-arm64-dts-armada-3720-espressobin-wire-up-spi-flash.patch b/target/linux/mvebu/patches-4.14/508-arm64-dts-armada-3720-espressobin-wire-up-spi-flash.patch deleted file mode 100644 index 840897473fb2..000000000000 --- a/target/linux/mvebu/patches-4.14/508-arm64-dts-armada-3720-espressobin-wire-up-spi-flash.patch +++ /dev/null @@ -1,56 +0,0 @@ -From bffed3d4abcd32ba6d492a9bd7ebe81dc92eaa9a Mon Sep 17 00:00:00 2001 -From: Ellie Reeves -Date: Sun, 25 Mar 2018 21:57:36 +0200 -Subject: [PATCH] arm64: dts: armada-3720-espressobin: wire up spi flash -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -This is the storage the machine boots from by default. The partitioning -is taken from the U-Boot that is shipped with the board. There is some -more space on the flash that isn't used. - -Tested-by: Gregory CLEMENT -Signed-off-by: Ellie Reeves -Signed-off-by: Uwe Kleine-König -Signed-off-by: Gregory CLEMENT ---- - .../dts/marvell/armada-3720-espressobin.dts | 27 +++++++++++++++++++ - 1 file changed, 27 insertions(+) - ---- a/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts -+++ b/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts -@@ -96,6 +96,33 @@ - status = "okay"; - }; - -+&spi0 { -+ status = "okay"; -+ -+ flash@0 { -+ reg = <0>; -+ compatible = "winbond,w25q32dw", "jedec,spi-flash"; -+ spi-max-frequency = <104000000>; -+ m25p,fast-read; -+ -+ partitions { -+ compatible = "fixed-partitions"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ -+ partition@0 { -+ label = "uboot"; -+ reg = <0 0x180000>; -+ }; -+ -+ partition@180000 { -+ label = "ubootenv"; -+ reg = <0x180000 0x10000>; -+ }; -+ }; -+ }; -+}; -+ - /* Exported on the micro USB connector J5 through an FTDI */ - &uart0 { - status = "okay"; diff --git a/target/linux/mvebu/patches-4.14/509-cpufreq-armada-37xx-Fix-clock-leak.patch b/target/linux/mvebu/patches-4.14/509-cpufreq-armada-37xx-Fix-clock-leak.patch deleted file mode 100644 index 7479c6db217c..000000000000 --- a/target/linux/mvebu/patches-4.14/509-cpufreq-armada-37xx-Fix-clock-leak.patch +++ /dev/null @@ -1,35 +0,0 @@ -From bbcc328561040292f7d6796954d478e4a2335e6f Mon Sep 17 00:00:00 2001 -From: Gregory CLEMENT -Date: Wed, 4 Apr 2018 16:44:44 +0200 -Subject: [PATCH] cpufreq: armada-37xx: Fix clock leak - -There was no clk_put() balancing the clk_get(). This commit fixes it. - -Fixes: 92ce45fb875d (cpufreq: Add DVFS support for Armada 37xx) -Cc: 4.16+ # 4.16+ -Reported-by: Thomas Petazzoni -Signed-off-by: Gregory CLEMENT -Acked-by: Viresh Kumar -Signed-off-by: Rafael J. Wysocki ---- - drivers/cpufreq/armada-37xx-cpufreq.c | 2 ++ - 1 file changed, 2 insertions(+) - ---- a/drivers/cpufreq/armada-37xx-cpufreq.c -+++ b/drivers/cpufreq/armada-37xx-cpufreq.c -@@ -202,6 +202,7 @@ static int __init armada37xx_cpufreq_dri - cur_frequency = clk_get_rate(clk); - if (!cur_frequency) { - dev_err(cpu_dev, "Failed to get clock rate for CPU\n"); -+ clk_put(clk); - return -EINVAL; - } - -@@ -210,6 +211,7 @@ static int __init armada37xx_cpufreq_dri - return -EINVAL; - - armada37xx_cpufreq_dvfs_setup(nb_pm_base, clk, dvfs->divider); -+ clk_put(clk); - - for (load_lvl = ARMADA_37XX_DVFS_LOAD_0; load_lvl < LOAD_LEVEL_NR; - load_lvl++) { diff --git a/target/linux/mvebu/patches-4.14/510-clk-mvebu-armada-37xx-periph-Fix-switching-CPU-rate-.patch b/target/linux/mvebu/patches-4.14/510-clk-mvebu-armada-37xx-periph-Fix-switching-CPU-rate-.patch deleted file mode 100644 index 42bfef7b7ea1..000000000000 --- a/target/linux/mvebu/patches-4.14/510-clk-mvebu-armada-37xx-periph-Fix-switching-CPU-rate-.patch +++ /dev/null @@ -1,92 +0,0 @@ -From 61c40f35f5cd6f67ccbd7319a1722eb78c815989 Mon Sep 17 00:00:00 2001 -From: Gregory CLEMENT -Date: Tue, 19 Jun 2018 14:34:45 +0200 -Subject: [PATCH] clk: mvebu: armada-37xx-periph: Fix switching CPU rate from - 300Mhz to 1.2GHz - -Switching the CPU from the L2 or L3 frequencies (300 and 200 Mhz -respectively) to L0 frequency (1.2 Ghz) requires a significant amount -of time to let VDD stabilize to the appropriate voltage. This amount of -time is large enough that it cannot be covered by the hardware -countdown register. Due to this, the CPU might start operating at L0 -before the voltage is stabilized, leading to CPU stalls. - -To work around this problem, we prevent switching directly from the -L2/L3 frequencies to the L0 frequency, and instead switch to the L1 -frequency in-between. The sequence therefore becomes: - -1. First switch from L2/L3(200/300MHz) to L1(600MHZ) -2. Sleep 20ms for stabling VDD voltage -3. Then switch from L1(600MHZ) to L0(1200Mhz). - -It is based on the work done by Ken Ma - -Cc: stable@vger.kernel.org -Fixes: 2089dc33ea0e ("clk: mvebu: armada-37xx-periph: add DVFS support for cpu clocks") -Signed-off-by: Gregory CLEMENT -Signed-off-by: Stephen Boyd ---- - drivers/clk/mvebu/armada-37xx-periph.c | 38 ++++++++++++++++++++++++++ - 1 file changed, 38 insertions(+) - ---- a/drivers/clk/mvebu/armada-37xx-periph.c -+++ b/drivers/clk/mvebu/armada-37xx-periph.c -@@ -35,6 +35,7 @@ - #define CLK_SEL 0x10 - #define CLK_DIS 0x14 - -+#define ARMADA_37XX_DVFS_LOAD_1 1 - #define LOAD_LEVEL_NR 4 - - #define ARMADA_37XX_NB_L0L1 0x18 -@@ -507,6 +508,40 @@ static long clk_pm_cpu_round_rate(struct - return -EINVAL; - } - -+/* -+ * Switching the CPU from the L2 or L3 frequencies (300 and 200 Mhz -+ * respectively) to L0 frequency (1.2 Ghz) requires a significant -+ * amount of time to let VDD stabilize to the appropriate -+ * voltage. This amount of time is large enough that it cannot be -+ * covered by the hardware countdown register. Due to this, the CPU -+ * might start operating at L0 before the voltage is stabilized, -+ * leading to CPU stalls. -+ * -+ * To work around this problem, we prevent switching directly from the -+ * L2/L3 frequencies to the L0 frequency, and instead switch to the L1 -+ * frequency in-between. The sequence therefore becomes: -+ * 1. First switch from L2/L3(200/300MHz) to L1(600MHZ) -+ * 2. Sleep 20ms for stabling VDD voltage -+ * 3. Then switch from L1(600MHZ) to L0(1200Mhz). -+ */ -+static void clk_pm_cpu_set_rate_wa(unsigned long rate, struct regmap *base) -+{ -+ unsigned int cur_level; -+ -+ if (rate != 1200 * 1000 * 1000) -+ return; -+ -+ regmap_read(base, ARMADA_37XX_NB_CPU_LOAD, &cur_level); -+ cur_level &= ARMADA_37XX_NB_CPU_LOAD_MASK; -+ if (cur_level <= ARMADA_37XX_DVFS_LOAD_1) -+ return; -+ -+ regmap_update_bits(base, ARMADA_37XX_NB_CPU_LOAD, -+ ARMADA_37XX_NB_CPU_LOAD_MASK, -+ ARMADA_37XX_DVFS_LOAD_1); -+ msleep(20); -+} -+ - static int clk_pm_cpu_set_rate(struct clk_hw *hw, unsigned long rate, - unsigned long parent_rate) - { -@@ -537,6 +572,9 @@ static int clk_pm_cpu_set_rate(struct cl - */ - reg = ARMADA_37XX_NB_CPU_LOAD; - mask = ARMADA_37XX_NB_CPU_LOAD_MASK; -+ -+ clk_pm_cpu_set_rate_wa(rate, base); -+ - regmap_update_bits(base, reg, mask, load_level); - - return rate; diff --git a/target/linux/mvebu/patches-4.14/511-clk-mvebu-armada-37xx-periph-Fix-wrong-return-value-.patch b/target/linux/mvebu/patches-4.14/511-clk-mvebu-armada-37xx-periph-Fix-wrong-return-value-.patch deleted file mode 100644 index 389a13a2b493..000000000000 --- a/target/linux/mvebu/patches-4.14/511-clk-mvebu-armada-37xx-periph-Fix-wrong-return-value-.patch +++ /dev/null @@ -1,33 +0,0 @@ -From 616bf80d381da13fbb392ebff06f46f946e3ee84 Mon Sep 17 00:00:00 2001 -From: Gregory CLEMENT -Date: Fri, 13 Jul 2018 12:27:26 +0200 -Subject: [PATCH] clk: mvebu: armada-37xx-periph: Fix wrong return value in - get_parent - -The return value of the get_parent operation is a u8, whereas a -EINVAL -was returned. This wrong value was return if the value was bigger that -the number of parent but this case was already handled by the core. - -So we can just remove this chunk of code to fix the issue. - -Reported-by: Dan Carpenter -Fixes: 9818a7a4fd10 ("clk: mvebu: armada-37xx-periph: prepare cpu clk to -be used with DVFS") -Signed-off-by: Gregory CLEMENT -Signed-off-by: Stephen Boyd ---- - drivers/clk/mvebu/armada-37xx-periph.c | 3 --- - 1 file changed, 3 deletions(-) - ---- a/drivers/clk/mvebu/armada-37xx-periph.c -+++ b/drivers/clk/mvebu/armada-37xx-periph.c -@@ -429,9 +429,6 @@ static u8 clk_pm_cpu_get_parent(struct c - val &= pm_cpu->mask_mux; - } - -- if (val >= num_parents) -- return -EINVAL; -- - return val; - } - diff --git a/target/linux/mvebu/patches-4.14/512-clk-mvebu-armada-37xx-periph-Remove-unused-var-num_p.patch b/target/linux/mvebu/patches-4.14/512-clk-mvebu-armada-37xx-periph-Remove-unused-var-num_p.patch deleted file mode 100644 index 874f982bd7a3..000000000000 --- a/target/linux/mvebu/patches-4.14/512-clk-mvebu-armada-37xx-periph-Remove-unused-var-num_p.patch +++ /dev/null @@ -1,33 +0,0 @@ -From 8927c27b32703e28041ae19bf25ea53461be83a1 Mon Sep 17 00:00:00 2001 -From: Anders Roxell -Date: Fri, 27 Jul 2018 00:27:21 +0200 -Subject: [PATCH] clk: mvebu: armada-37xx-periph: Remove unused var num_parents -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -When building armada-37xx-periph, num_parents isn't used in function -clk_pm_cpu_get_parent: -drivers/clk/mvebu/armada-37xx-periph.c: In function ‘clk_pm_cpu_get_parent’: -drivers/clk/mvebu/armada-37xx-periph.c:419:6: warning: unused variable ‘num_parents’ [-Wunused-variable] - int num_parents = clk_hw_get_num_parents(hw); - ^~~~~~~~~~~ -Remove the declaration of num_parents to dispose the warning. - -Fixes: 616bf80d381d ("clk: mvebu: armada-37xx-periph: Fix wrong return value in get_parent") -Signed-off-by: Anders Roxell -Signed-off-by: Stephen Boyd ---- - drivers/clk/mvebu/armada-37xx-periph.c | 1 - - 1 file changed, 1 deletion(-) - ---- a/drivers/clk/mvebu/armada-37xx-periph.c -+++ b/drivers/clk/mvebu/armada-37xx-periph.c -@@ -419,7 +419,6 @@ static unsigned int armada_3700_pm_dvfs_ - static u8 clk_pm_cpu_get_parent(struct clk_hw *hw) - { - struct clk_pm_cpu *pm_cpu = to_clk_pm_cpu(hw); -- int num_parents = clk_hw_get_num_parents(hw); - u32 val; - - if (armada_3700_pm_dvfs_is_enabled(pm_cpu->nb_pm_base)) { diff --git a/target/linux/mvebu/patches-4.14/513-arm64-dts-marvell-armada37xx-Add-emmc-sdio-pinctrl-d.patch b/target/linux/mvebu/patches-4.14/513-arm64-dts-marvell-armada37xx-Add-emmc-sdio-pinctrl-d.patch deleted file mode 100644 index 19702a61ed5f..000000000000 --- a/target/linux/mvebu/patches-4.14/513-arm64-dts-marvell-armada37xx-Add-emmc-sdio-pinctrl-d.patch +++ /dev/null @@ -1,40 +0,0 @@ -From eefe328439642101774f0f5c4ea0dc6ba1cfb687 Mon Sep 17 00:00:00 2001 -From: Ding Tao -Date: Fri, 26 Oct 2018 11:50:27 +0000 -Subject: [PATCH] arm64: dts: marvell: armada37xx: Add emmc/sdio pinctrl - definition - -Add emmc/sdio pinctrl definition for marvell armada37xx SoCs. - -Signed-off-by: Ding Tao -Signed-off-by: Gregory CLEMENT ---- - arch/arm64/boot/dts/marvell/armada-37xx.dtsi | 10 ++++++++++ - 1 file changed, 10 insertions(+) - ---- a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi -+++ b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi -@@ -218,6 +218,11 @@ - groups = "uart2"; - function = "uart"; - }; -+ -+ mmc_pins: mmc-pins { -+ groups = "emmc_nb"; -+ function = "emmc"; -+ }; - }; - - nb_pm: syscon@14000 { -@@ -247,6 +252,11 @@ - function = "mii"; - }; - -+ sdio_pins: sdio-pins { -+ groups = "sdio_sb"; -+ function = "sdio"; -+ }; -+ - }; - - eth0: ethernet@30000 { diff --git a/target/linux/mvebu/patches-4.14/514-arm64-dts-marvell-armada-37xx-Enable-emmc-on-espress.patch b/target/linux/mvebu/patches-4.14/514-arm64-dts-marvell-armada-37xx-Enable-emmc-on-espress.patch deleted file mode 100644 index 26d090f050b2..000000000000 --- a/target/linux/mvebu/patches-4.14/514-arm64-dts-marvell-armada-37xx-Enable-emmc-on-espress.patch +++ /dev/null @@ -1,49 +0,0 @@ -From 43ebc7c1b3ed8198b9acf3019eca16e722f7331c Mon Sep 17 00:00:00 2001 -From: Ding Tao -Date: Fri, 26 Oct 2018 11:50:28 +0000 -Subject: [PATCH] arm64: dts: marvell: armada-37xx: Enable emmc on espressobin - -The ESPRESSObin board has a emmc interface available on U11: declare it -and let the bootloader enable it if the emmc is present. - -[gregory.clement@bootlin.com: disable the emmc by default] -Signed-off-by: Ding Tao -Signed-off-by: Gregory CLEMENT ---- - .../dts/marvell/armada-3720-espressobin.dts | 22 +++++++++++++++++++ - 1 file changed, 22 insertions(+) - ---- a/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts -+++ b/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts -@@ -93,9 +93,31 @@ - cd-gpios = <&gpionb 3 GPIO_ACTIVE_LOW>; - marvell,pad-type = "sd"; - vqmmc-supply = <&vcc_sd_reg1>; -+ -+ pinctrl-names = "default"; -+ pinctrl-0 = <&sdio_pins>; - status = "okay"; - }; - -+/* U11 */ -+&sdhci0 { -+ non-removable; -+ bus-width = <8>; -+ mmc-ddr-1_8v; -+ mmc-hs400-1_8v; -+ marvell,xenon-emmc; -+ marvell,xenon-tun-count = <9>; -+ marvell,pad-type = "fixed-1-8v"; -+ -+ pinctrl-names = "default"; -+ pinctrl-0 = <&mmc_pins>; -+/* -+ * This eMMC is not populated on all boards, so disable it by -+ * default and let the bootloader enable it, if it is present -+ */ -+ status = "disabled"; -+}; -+ - &spi0 { - status = "okay"; - diff --git a/target/linux/mvebu/patches-4.14/520-arm64-dts-marvell-armada37xx-Add-eth0-alias.patch b/target/linux/mvebu/patches-4.14/520-arm64-dts-marvell-armada37xx-Add-eth0-alias.patch deleted file mode 100644 index 206caf2fcef0..000000000000 --- a/target/linux/mvebu/patches-4.14/520-arm64-dts-marvell-armada37xx-Add-eth0-alias.patch +++ /dev/null @@ -1,20 +0,0 @@ -From be893f672e340b56ca60f2f6c32fdd713a5852f5 Mon Sep 17 00:00:00 2001 -From: Kevin Mihelich -Date: Tue, 4 Jul 2017 19:25:28 -0600 -Subject: arm64: dts: marvell: armada37xx: Add eth0 alias - -Signed-off-by: Kevin Mihelich ---- - arch/arm64/boot/dts/marvell/armada-37xx.dtsi | 1 + - 1 file changed, 1 insertion(+) - ---- a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi -+++ b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi -@@ -54,6 +54,7 @@ - #size-cells = <2>; - - aliases { -+ ethernet0 = ð0; - serial0 = &uart0; - }; - diff --git a/target/linux/mvebu/patches-4.14/521-arm64-dts-armada-3720-espressobin-correct-spi-node.patch b/target/linux/mvebu/patches-4.14/521-arm64-dts-armada-3720-espressobin-correct-spi-node.patch deleted file mode 100644 index fc7cb2af1ee7..000000000000 --- a/target/linux/mvebu/patches-4.14/521-arm64-dts-armada-3720-espressobin-correct-spi-node.patch +++ /dev/null @@ -1,58 +0,0 @@ -From 3217cdfe8a3eae76fafbebbe407be5985a7fd4c2 Mon Sep 17 00:00:00 2001 -From: Tomasz Maciej Nowak -Date: Mon, 31 Dec 2018 14:18:50 +0100 -Subject: [PATCH] arm64: dts: armada-3720-espressobin: correct spi node - -The manufacturer of this board, ships it with various SPI NOR chips and -increments U-Boot bootloader version along the time. There is no way to -tell which is placed on the board since no revision bump takes place. -This creates two issues. - -The first, cosmetic. Since the SPI chip may differ, there's message on -boot stating that kernel expected w25q32dw and found different one. To -correct this, remove optional device-specific compatible string. Being -here lets replace bogus "spi-flash" string with proper one. - -The second is linked to partitions layout, it changed after commit [1] -in Marvells downstream U-Boot fork, shifting environment location to the -end of boot device. Since the new boards can have U-Boot with this -change it can lead to improper results writing or reading from these -partitions. We can't tell if users will update bootloader to recent -version, so let's drop current layout. - -1. https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/81e7251252aefe1a6b829ed05f3586320cb45372 - -Signed-off-by: Tomasz Maciej Nowak ---- - .../dts/marvell/armada-3720-espressobin.dts | 18 +----------------- - 1 file changed, 1 insertion(+), 17 deletions(-) - ---- a/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts -+++ b/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts -@@ -123,25 +123,9 @@ - - flash@0 { - reg = <0>; -- compatible = "winbond,w25q32dw", "jedec,spi-flash"; -+ compatible = "jedec,spi-nor"; - spi-max-frequency = <104000000>; - m25p,fast-read; -- -- partitions { -- compatible = "fixed-partitions"; -- #address-cells = <1>; -- #size-cells = <1>; -- -- partition@0 { -- label = "uboot"; -- reg = <0 0x180000>; -- }; -- -- partition@180000 { -- label = "ubootenv"; -- reg = <0x180000 0x10000>; -- }; -- }; - }; - }; - diff --git a/target/linux/mvebu/patches-4.14/522-arm64-dts-marvell-armada-3720-espressobin-add-ports-.patch b/target/linux/mvebu/patches-4.14/522-arm64-dts-marvell-armada-3720-espressobin-add-ports-.patch deleted file mode 100644 index d0103bba1967..000000000000 --- a/target/linux/mvebu/patches-4.14/522-arm64-dts-marvell-armada-3720-espressobin-add-ports-.patch +++ /dev/null @@ -1,26 +0,0 @@ -From 6ea9a1ee9367fb35acff1c08a0dc4213ff4687a0 Mon Sep 17 00:00:00 2001 -From: Tomasz Maciej Nowak -Date: Tue, 9 Apr 2019 15:53:42 +0200 -Subject: [PATCH] arm64: dts: marvell: armada-3720-espressobin: add ports - phandle - -Instead of referencing the whole mdio node, add ports phandle to adjust -port labels in dts for different hardware iterations of ESPRESSObin -boards. - -Signed-off-by: Tomasz Maciej Nowak ---- - arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts -+++ b/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts -@@ -153,7 +153,7 @@ - - dsa,member = <0 0>; - -- ports { -+ ports: ports { - #address-cells = <1>; - #size-cells = <0>; - diff --git a/target/linux/mvebu/patches-4.14/524-PCI-aardvark-set-host-and-device-to-the-same-MAX-payload-size.patch b/target/linux/mvebu/patches-4.14/524-PCI-aardvark-set-host-and-device-to-the-same-MAX-payload-size.patch deleted file mode 100644 index 74e78d3b54ab..000000000000 --- a/target/linux/mvebu/patches-4.14/524-PCI-aardvark-set-host-and-device-to-the-same-MAX-payload-size.patch +++ /dev/null @@ -1,138 +0,0 @@ -From patchwork Thu Sep 28 12:58:34 2017 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -Subject: [v2, - 3/7] PCI: aardvark: set host and device to the same MAX payload size -X-Patchwork-Submitter: Thomas Petazzoni -X-Patchwork-Id: 819587 -Message-Id: <20170928125838.11887-4-thomas.petazzoni@free-electrons.com> -To: Bjorn Helgaas , linux-pci@vger.kernel.org -Cc: Jason Cooper , Andrew Lunn , - Sebastian Hesselbarth , Gregory Clement - , - Nadav Haklai , Hanna Hawa , - Yehuda Yitschak , - linux-arm-kernel@lists.infradead.org, Antoine Tenart - , =?utf-8?q?Miqu=C3=A8l_Raynal?= - , Victor Gu , - Thomas Petazzoni -Date: Thu, 28 Sep 2017 14:58:34 +0200 -From: Thomas Petazzoni -List-Id: - -From: Victor Gu - -Since the Aardvark does not implement a PCIe root bus, the Linux PCIe -subsystem will not align the MAX payload size between the host and the -device. This patch ensures that the host and device have the same MAX -payload size, fixing a number of problems with various PCIe devices. - -This is part of fixing bug -https://bugzilla.kernel.org/show_bug.cgi?id=196339, this commit was -reported as the user to be important to get a Intel 7260 mini-PCIe -WiFi card working. - -Fixes: Fixes: 8c39d710363c1 ("PCI: aardvark: Add Aardvark PCI host controller driver") -Signed-off-by: Victor Gu -Reviewed-by: Evan Wang -Reviewed-by: Nadav Haklai -[Thomas: tweak commit log.] -Signed-off-by: Thomas Petazzoni ---- - drivers/pci/host/pci-aardvark.c | 60 ++++++++++++++++++++++++++++++++++++++++- - 1 file changed, 59 insertions(+), 1 deletion(-) - ---- a/drivers/pci/host/pci-aardvark.c -+++ b/drivers/pci/host/pci-aardvark.c -@@ -30,9 +30,11 @@ - #define PCIE_CORE_DEV_CTRL_STATS_REG 0xc8 - #define PCIE_CORE_DEV_CTRL_STATS_RELAX_ORDER_DISABLE (0 << 4) - #define PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ_SHIFT 5 -+#define PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ 0x2 - #define PCIE_CORE_DEV_CTRL_STATS_SNOOP_DISABLE (0 << 11) - #define PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SIZE_SHIFT 12 - #define PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SZ 0x2 -+#define PCIE_CORE_MPS_UNIT_BYTE 128 - #define PCIE_CORE_LINK_CTRL_STAT_REG 0xd0 - #define PCIE_CORE_LINK_L0S_ENTRY BIT(0) - #define PCIE_CORE_LINK_TRAINING BIT(5) -@@ -297,7 +299,8 @@ static void advk_pcie_setup_hw(struct ad - - /* Set PCIe Device Control and Status 1 PF0 register */ - reg = PCIE_CORE_DEV_CTRL_STATS_RELAX_ORDER_DISABLE | -- (7 << PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ_SHIFT) | -+ (PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ << -+ PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ_SHIFT) | - PCIE_CORE_DEV_CTRL_STATS_SNOOP_DISABLE | - (PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SZ << - PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SIZE_SHIFT); -@@ -886,6 +889,58 @@ out_release_res: - return err; - } - -+static int advk_pcie_find_smpss(struct pci_dev *dev, void *data) -+{ -+ u8 *smpss = data; -+ -+ if (!dev) -+ return 0; -+ -+ if (!pci_is_pcie(dev)) -+ return 0; -+ -+ if (*smpss > dev->pcie_mpss) -+ *smpss = dev->pcie_mpss; -+ -+ return 0; -+} -+ -+static int advk_pcie_bus_configure_mps(struct pci_dev *dev, void *data) -+{ -+ int mps; -+ -+ if (!dev) -+ return 0; -+ -+ if (!pci_is_pcie(dev)) -+ return 0; -+ -+ mps = PCIE_CORE_MPS_UNIT_BYTE << *(u8 *)data; -+ pcie_set_mps(dev, mps); -+ -+ return 0; -+} -+ -+static void advk_pcie_configure_mps(struct pci_bus *bus, struct advk_pcie *pcie) -+{ -+ u8 smpss = PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ; -+ u32 reg; -+ -+ /* Find the minimal supported MAX payload size */ -+ advk_pcie_find_smpss(bus->self, &smpss); -+ pci_walk_bus(bus, advk_pcie_find_smpss, &smpss); -+ -+ /* Configure RC MAX payload size */ -+ reg = advk_readl(pcie, PCIE_CORE_DEV_CTRL_STATS_REG); -+ reg &= ~PCI_EXP_DEVCTL_PAYLOAD; -+ reg |= smpss << PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ_SHIFT; -+ advk_writel(pcie, reg, PCIE_CORE_DEV_CTRL_STATS_REG); -+ -+ /* Configure device MAX payload size */ -+ advk_pcie_bus_configure_mps(bus->self, &smpss); -+ pci_walk_bus(bus, advk_pcie_bus_configure_mps, &smpss); -+} -+ - static int advk_pcie_probe(struct platform_device *pdev) - { - struct device *dev = &pdev->dev; -@@ -960,6 +1015,9 @@ static int advk_pcie_probe(struct platfo - list_for_each_entry(child, &bus->children, node) - pcie_bus_configure_settings(child); - -+ /* Configure the MAX pay load size */ -+ advk_pcie_configure_mps(bus, pcie); -+ - pci_bus_add_devices(bus); - return 0; - } diff --git a/target/linux/mvebu/patches-4.14/526-PCI-aardvark-disable-LOS-state-by-default.patch b/target/linux/mvebu/patches-4.14/526-PCI-aardvark-disable-LOS-state-by-default.patch deleted file mode 100644 index 0ee4af4e8dbd..000000000000 --- a/target/linux/mvebu/patches-4.14/526-PCI-aardvark-disable-LOS-state-by-default.patch +++ /dev/null @@ -1,55 +0,0 @@ -From patchwork Thu Sep 28 12:58:36 2017 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -Subject: [v2,5/7] PCI: aardvark: disable LOS state by default -X-Patchwork-Submitter: Thomas Petazzoni -X-Patchwork-Id: 819590 -Message-Id: <20170928125838.11887-6-thomas.petazzoni@free-electrons.com> -To: Bjorn Helgaas , linux-pci@vger.kernel.org -Cc: Jason Cooper , Andrew Lunn , - Sebastian Hesselbarth , Gregory Clement - , - Nadav Haklai , Hanna Hawa , - Yehuda Yitschak , - linux-arm-kernel@lists.infradead.org, Antoine Tenart - , =?utf-8?q?Miqu=C3=A8l_Raynal?= - , Victor Gu , - Thomas Petazzoni -Date: Thu, 28 Sep 2017 14:58:36 +0200 -From: Thomas Petazzoni -List-Id: - -From: Victor Gu - -Some PCIe devices do not support LOS, and will cause timeouts if the -root complex forces the LOS state. This patch disables the LOS state -by default. - -This is part of fixing bug -https://bugzilla.kernel.org/show_bug.cgi?id=196339, this commit was -reported as the user to be important to get a Intel 7260 mini-PCIe -WiFi card working. - -Fixes: 8c39d710363c1 ("PCI: aardvark: Add Aardvark PCI host controller driver") -Signed-off-by: Victor Gu -Reviewed-by: Evan Wang -Reviewed-by: Nadav Haklai -[Thomas: tweak commit log.] -Signed-off-by: Thomas Petazzoni ---- - drivers/pci/host/pci-aardvark.c | 3 +-- - 1 file changed, 1 insertion(+), 2 deletions(-) - ---- a/drivers/pci/host/pci-aardvark.c -+++ b/drivers/pci/host/pci-aardvark.c -@@ -368,8 +368,7 @@ static void advk_pcie_setup_hw(struct ad - - advk_pcie_wait_for_link(pcie); - -- reg = PCIE_CORE_LINK_L0S_ENTRY | -- (1 << PCIE_CORE_LINK_WIDTH_SHIFT); -+ reg = (1 << PCIE_CORE_LINK_WIDTH_SHIFT); - advk_writel(pcie, reg, PCIE_CORE_LINK_CTRL_STAT_REG); - - reg = advk_readl(pcie, PCIE_CORE_CMD_STATUS_REG); diff --git a/target/linux/mvebu/patches-4.14/527-PCI-aardvark-allow-to-specify-link-capability.patch b/target/linux/mvebu/patches-4.14/527-PCI-aardvark-allow-to-specify-link-capability.patch deleted file mode 100644 index fb57f4112a4f..000000000000 --- a/target/linux/mvebu/patches-4.14/527-PCI-aardvark-allow-to-specify-link-capability.patch +++ /dev/null @@ -1,43 +0,0 @@ -From f70b629e488cc3f2a325ac35476f4f7ae502c5d0 Mon Sep 17 00:00:00 2001 -From: Tomasz Maciej Nowak -Date: Thu, 14 Jun 2018 14:24:40 +0200 -Subject: [PATCH 1/2] PCI: aardvark: allow to specify link capability - -Use DT of_pci_get_max_link_speed() facility to allow specifying link -capability. If none or unspecified value is given it falls back to gen2, -which is default for Armada 3700 SoC. - -Signed-off-by: Tomasz Maciej Nowak ---- - drivers/pci/host/pci-aardvark.c | 11 +++++++++-- - 1 file changed, 9 insertions(+), 2 deletions(-) - ---- a/drivers/pci/host/pci-aardvark.c -+++ b/drivers/pci/host/pci-aardvark.c -@@ -272,6 +272,8 @@ static void advk_pcie_set_ob_win(struct - - static void advk_pcie_setup_hw(struct advk_pcie *pcie) - { -+ struct device *dev = &pcie->pdev->dev; -+ struct device_node *node = dev->of_node; - u32 reg; - int i; - -@@ -311,10 +313,15 @@ static void advk_pcie_setup_hw(struct ad - PCIE_CORE_CTRL2_TD_ENABLE; - advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG); - -- /* Set GEN2 */ -+ /* Set GEN */ - reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG); - reg &= ~PCIE_GEN_SEL_MSK; -- reg |= SPEED_GEN_2; -+ if (of_pci_get_max_link_speed(node) == 1) -+ reg |= SPEED_GEN_1; -+ else if (of_pci_get_max_link_speed(node) == 3) -+ reg |= SPEED_GEN_3; -+ else -+ reg |= SPEED_GEN_2; - advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG); - - /* Set lane X1 */ diff --git a/target/linux/mvebu/patches-4.14/528-arm64-dts-armada-3720-espressobin-set-max-link-to-ge.patch b/target/linux/mvebu/patches-4.14/528-arm64-dts-armada-3720-espressobin-set-max-link-to-ge.patch deleted file mode 100644 index 5ff9b472682c..000000000000 --- a/target/linux/mvebu/patches-4.14/528-arm64-dts-armada-3720-espressobin-set-max-link-to-ge.patch +++ /dev/null @@ -1,73 +0,0 @@ -From 33f8fdcedb01680427328d710594facef7a0092c Mon Sep 17 00:00:00 2001 -From: Tomasz Maciej Nowak -Date: Thu, 14 Jun 2018 14:40:26 +0200 -Subject: [PATCH 2/2] arm64: dts: armada-3720-espressobin: set max link to gen1 - -Since the beginning there's been an issue with initializing the Atheros -based MiniPCIe wireless cards. Here's an example of kerenel log: - - OF: PCI: host bridge /soc/pcie@d0070000 ranges: - OF: PCI: MEM 0xe8000000..0xe8ffffff -> 0xe8000000 - OF: PCI: IO 0xe9000000..0xe900ffff -> 0xe9000000 - advk-pcie d0070000.pcie: link up - advk-pcie d0070000.pcie: PCI host bridge to bus 0000:00 - pci_bus 0000:00: root bus resource [bus 00-ff] - pci_bus 0000:00: root bus resource [mem0xe8000000-0xe8ffffff] - pci_bus 0000:00: root bus resource [io 0x0000-0xffff](bus address [0xe9000000-0xe900ffff]) - pci 0000:00:00.0: BAR 0: assigned [mem0xe8000000-0xe801ffff 64bit] - pci 0000:00:00.0: BAR 6: assigned [mem0xe8020000-0xe802ffff pref] - [...] - advk-pcie d0070000.pcie: Posted PIO Response Status: CA,0xe00 @ 0x3c - advk-pcie d0070000.pcie: Posted PIO Response Status: CA,0xe00 @ 0x44 - advk-pcie d0070000.pcie: Posted PIO Response Status: CA,0xe00 @ 0x4 - ath9k 0000:00:00.0: enabling device (0000 -> 0002) - advk-pcie d0070000.pcie: Posted PIO Response Status: CA,0xe00 @ 0x3c - advk-pcie d0070000.pcie: Posted PIO Response Status: CA,0xe00 @ 0xc - advk-pcie d0070000.pcie: Posted PIO Response Status: CA,0xe00 @ 0x4 - advk-pcie d0070000.pcie: Posted PIO Response Status: CA,0xe00 @ 0x40 - ath9k 0000:00:00.0: request_irq failed - advk-pcie d0070000.pcie: Posted PIO Response Status: CA,0xe00 @ 0x4 - ath9k: probe of 0000:00:00.0 failed with error -22 - -The same happens for ath5k cards, while ath10k card didn't appear at -all (not detected): - - OF: PCI: host bridge /soc/pcie@d0070000 ranges: - OF: PCI: MEM 0xe8000000..0xe8ffffff -> 0xe8000000 - OF: PCI: IO 0xe9000000..0xe900ffff -> 0xe9000000 - advk-pcie d0070000.pcie: link never came up - advk-pcie d0070000.pcie: PCI host bridge to bus 0000:00 - pci_bus 0000:00: root bus resource [bus 00-ff] - pci_bus 0000:00: root bus resource [mem0xe8000000-0xe8ffffff] - pci_bus 0000:00: root bus resource [io 0x0000-0xffff](bus address [0xe9000000-0xe900ffff]) - advk-pcie d0070000.pcie: config read/write timed out - -Following the issue on esppressobin.net forum [1] the workaround seems -to be limiting the speed of PCIe bridge to 1st generation. This fixed -the initialisation of all tested Atheros wireless cards. -The patch in the forum thread swaped registers which would limit speed -for all Armada 3700 based boards. The approach in this patch, in -conjunction with "PCI: aardvark: allow to specify link capability" patch -is less invasive, it only touches the affected board. - -For the record, the iwlwifi and mt76 cards were not affected by this -issue. - -1. http://espressobin.net/forums/topic/which-pcie-wlan-cards-are-supported - -Signed-off-by: Tomasz Maciej Nowak ---- - arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts | 2 ++ - 1 file changed, 2 insertions(+) - ---- a/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts -+++ b/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts -@@ -79,6 +79,8 @@ - /* J9 */ - &pcie0 { - status = "okay"; -+ -+ max-link-speed = <1>; - }; - - /* J6 */ From patchwork Sun Mar 1 12:12:38 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Hauke Mehrtens X-Patchwork-Id: 1247285 X-Patchwork-Delegate: hauke@hauke-m.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; 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Sun, 01 Mar 2020 12:13:13 +0000 Received: from smtp2.mailbox.org (smtp2.mailbox.org [80.241.60.241]) (using TLSv1.2 with cipher ECDHE-RSA-CHACHA20-POLY1305 (256/256 bits)) (No client certificate requested) by mout-p-102.mailbox.org (Postfix) with ESMTPS id 48VhxM0LPDzKmZ0; Sun, 1 Mar 2020 13:12:55 +0100 (CET) X-Virus-Scanned: amavisd-new at heinlein-support.de Received: from smtp2.mailbox.org ([80.241.60.241]) by spamfilter06.heinlein-hosting.de (spamfilter06.heinlein-hosting.de [80.241.56.125]) (amavisd-new, port 10030) with ESMTP id V0_jbWFmEHJe; Sun, 1 Mar 2020 13:12:52 +0100 (CET) From: Hauke Mehrtens To: openwrt-devel@lists.openwrt.org Date: Sun, 1 Mar 2020 13:12:38 +0100 Message-Id: <20200301121241.5545-10-hauke@hauke-m.de> In-Reply-To: <20200301121241.5545-1-hauke@hauke-m.de> References: <20200301121241.5545-1-hauke@hauke-m.de> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200301_041302_738608_19781A39 X-CRM114-Status: GOOD ( 14.88 ) X-Spam-Score: 0.1 (/) X-Spam-Report: SpamAssassin version 3.4.3 on bombadil.infradead.org summary: Content analysis details: (0.1 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at https://www.dnswl.org/, low trust [80.241.56.152 listed in list.dnswl.org] 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.0 SPF_PASS SPF: sender matches SPF record 0.8 UPPERCASE_50_75 message body is 50-75% uppercase Subject: [OpenWrt-Devel] [PATCH 09/12] octeon: Remove kernel 4.14 support X-BeenThere: openwrt-devel@lists.openwrt.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: hauke@hauke-m.de Sender: "openwrt-devel" Errors-To: openwrt-devel-bounces+incoming=patchwork.ozlabs.org@lists.openwrt.org This target was switched to kernel 4.19 more than 6 months ago in commit f342ffd300da ("treewide: kernel: bump some targets to 4.19") and now with kernel 5.4 support being added it gets harder to support kernel 4.14 in addition to kernel 4.19 and 5.4. Signed-off-by: Hauke Mehrtens --- target/linux/octeon/config-4.14 | 304 ------------------ .../100-ubnt_edgerouter2_support.patch | 31 -- .../110-er200-ethernet_probe_order.patch | 34 -- .../patches-4.14/160-cmdline-hack.patch | 47 --- .../octeon/patches-4.14/170-cisco-hack.patch | 31 -- 5 files changed, 447 deletions(-) delete mode 100644 target/linux/octeon/config-4.14 delete mode 100644 target/linux/octeon/patches-4.14/100-ubnt_edgerouter2_support.patch delete mode 100644 target/linux/octeon/patches-4.14/110-er200-ethernet_probe_order.patch delete mode 100644 target/linux/octeon/patches-4.14/160-cmdline-hack.patch delete mode 100644 target/linux/octeon/patches-4.14/170-cisco-hack.patch diff --git a/target/linux/octeon/config-4.14 b/target/linux/octeon/config-4.14 deleted file mode 100644 index e2b926f8fc3d..000000000000 --- a/target/linux/octeon/config-4.14 +++ /dev/null @@ -1,304 +0,0 @@ -CONFIG_64BIT=y -CONFIG_ARCH_BINFMT_ELF_STATE=y -CONFIG_ARCH_CLOCKSOURCE_DATA=y -CONFIG_ARCH_DISCARD_MEMBLOCK=y -CONFIG_ARCH_DMA_ADDR_T_64BIT=y -CONFIG_ARCH_HAS_ELF_RANDOMIZE=y -# CONFIG_ARCH_HAS_GCOV_PROFILE_ALL is not set -# CONFIG_ARCH_HAS_SG_CHAIN is not set -# CONFIG_ARCH_HAS_STRICT_KERNEL_RWX is not set -# CONFIG_ARCH_HAS_STRICT_MODULE_RWX is not set -CONFIG_ARCH_HIBERNATION_POSSIBLE=y -CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y -CONFIG_ARCH_MIGHT_HAVE_PC_SERIO=y -CONFIG_ARCH_MMAP_RND_BITS=12 -CONFIG_ARCH_MMAP_RND_BITS_MAX=18 -CONFIG_ARCH_MMAP_RND_BITS_MIN=12 -CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=15 -# CONFIG_ARCH_OPTIONAL_KERNEL_RWX is not set -# CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT is not set -CONFIG_ARCH_PHYS_ADDR_T_64BIT=y -CONFIG_ARCH_SPARSEMEM_ENABLE=y -CONFIG_ARCH_SUPPORTS_UPROBES=y -CONFIG_ARCH_SUSPEND_POSSIBLE=y -CONFIG_ARCH_USE_BUILTIN_BSWAP=y -CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y -CONFIG_ARCH_USE_QUEUED_RWLOCKS=y -CONFIG_ARCH_USE_QUEUED_SPINLOCKS=y -CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y -CONFIG_BLK_DEV_LOOP=y -CONFIG_BLK_DEV_SD=y -CONFIG_BLK_MQ_PCI=y -CONFIG_BLK_SCSI_REQUEST=y -# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set -CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0 -CONFIG_BUILTIN_DTB=y -CONFIG_CAVIUM_CN63XXP1=y -CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE=2 -CONFIG_CAVIUM_OCTEON_LOCK_L2=y -CONFIG_CAVIUM_OCTEON_LOCK_L2_EXCEPTION=y -CONFIG_CAVIUM_OCTEON_LOCK_L2_INTERRUPT=y -CONFIG_CAVIUM_OCTEON_LOCK_L2_LOW_LEVEL_INTERRUPT=y -CONFIG_CAVIUM_OCTEON_LOCK_L2_MEMCPY=y -CONFIG_CAVIUM_OCTEON_LOCK_L2_TLB=y -CONFIG_CAVIUM_OCTEON_SOC=y -CONFIG_CEVT_R4K=y -CONFIG_CLONE_BACKWARDS=y -CONFIG_CPU_BIG_ENDIAN=y -CONFIG_CPU_CAVIUM_OCTEON=y -CONFIG_CPU_GENERIC_DUMP_TLB=y -CONFIG_CPU_HAS_PREFETCH=y -CONFIG_CPU_HAS_RIXI=y -CONFIG_CPU_HAS_SYNC=y -# CONFIG_CPU_LITTLE_ENDIAN is not set -CONFIG_CPU_MIPSR2=y -CONFIG_CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS=y -CONFIG_CPU_R4K_FPU=y -CONFIG_CPU_RMAP=y -CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y -CONFIG_CPU_SUPPORTS_HIGHMEM=y -CONFIG_CPU_SUPPORTS_HUGEPAGES=y -CONFIG_CRAMFS=y -CONFIG_CRASH_CORE=y -CONFIG_CRC16=y -CONFIG_CRYPTO_AEAD=y -CONFIG_CRYPTO_AEAD2=y -CONFIG_CRYPTO_CRC32=y -CONFIG_CRYPTO_CRC32C=y -CONFIG_CRYPTO_HASH=y -CONFIG_CRYPTO_HASH2=y -CONFIG_CRYPTO_MANAGER=y -CONFIG_CRYPTO_MANAGER2=y -# CONFIG_CRYPTO_MD5_OCTEON is not set -CONFIG_CRYPTO_NULL2=y -CONFIG_CRYPTO_RNG2=y -# CONFIG_CRYPTO_SHA1_OCTEON is not set -# CONFIG_CRYPTO_SHA256_OCTEON is not set -# CONFIG_CRYPTO_SHA512_OCTEON is not set -CONFIG_CRYPTO_WORKQUEUE=y -CONFIG_DEBUG_INFO=y -CONFIG_DEBUG_SPINLOCK=y -CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=120 -CONFIG_DETECT_HUNG_TASK=y -CONFIG_DMA_COHERENT=y -CONFIG_DNOTIFY=y -CONFIG_DTC=y -CONFIG_EARLY_PRINTK=y -CONFIG_EDAC_ATOMIC_SCRUB=y -CONFIG_EDAC_SUPPORT=y -CONFIG_ENABLE_MUST_CHECK=y -CONFIG_EXT4_FS=y -# CONFIG_F2FS_CHECK_FS is not set -CONFIG_F2FS_FS=y -# CONFIG_F2FS_FS_SECURITY is not set -CONFIG_F2FS_FS_XATTR=y -CONFIG_F2FS_STAT_FS=y -CONFIG_FAT_FS=y -CONFIG_FIXED_PHY=y -CONFIG_FRAME_WARN=2048 -CONFIG_FS_MBCACHE=y -CONFIG_GENERIC_CLOCKEVENTS=y -CONFIG_GENERIC_CMOS_UPDATE=y -CONFIG_GENERIC_CPU_AUTOPROBE=y -CONFIG_GENERIC_IO=y -CONFIG_GENERIC_IRQ_SHOW=y -CONFIG_GENERIC_PCI_IOMAP=y -CONFIG_GENERIC_SMP_IDLE_THREAD=y -CONFIG_GENERIC_TIME_VSYSCALL=y -CONFIG_GPIOLIB=y -CONFIG_GPIO_OCTEON=y -CONFIG_GPIO_SYSFS=y -# CONFIG_GRO_CELLS is not set -CONFIG_HANDLE_DOMAIN_IRQ=y -CONFIG_HARDWARE_WATCHPOINTS=y -CONFIG_HAS_DMA=y -CONFIG_HAS_IOMEM=y -CONFIG_HAS_IOPORT_MAP=y -CONFIG_HAVE_64BIT_ALIGNED_ACCESS=y -# CONFIG_HAVE_ARCH_BITREVERSE is not set -CONFIG_HAVE_ARCH_COMPILER_H=y -CONFIG_HAVE_ARCH_JUMP_LABEL=y -CONFIG_HAVE_ARCH_KGDB=y -CONFIG_HAVE_ARCH_SECCOMP_FILTER=y -CONFIG_HAVE_ARCH_TRACEHOOK=y -CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE=y -# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set -CONFIG_HAVE_CC_STACKPROTECTOR=y -CONFIG_HAVE_CONTEXT_TRACKING=y -CONFIG_HAVE_COPY_THREAD_TLS=y -CONFIG_HAVE_C_RECORDMCOUNT=y -CONFIG_HAVE_DEBUG_KMEMLEAK=y -CONFIG_HAVE_DEBUG_STACKOVERFLOW=y -CONFIG_HAVE_DMA_API_DEBUG=y -CONFIG_HAVE_DMA_CONTIGUOUS=y -CONFIG_HAVE_DYNAMIC_FTRACE=y -CONFIG_HAVE_EBPF_JIT=y -CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y -CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y -CONFIG_HAVE_FUNCTION_TRACER=y -CONFIG_HAVE_GENERIC_DMA_COHERENT=y -CONFIG_HAVE_IDE=y -CONFIG_HAVE_IRQ_EXIT_ON_IRQ_STACK=y -CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y -CONFIG_HAVE_KVM=y -CONFIG_HAVE_LATENCYTOP_SUPPORT=y -CONFIG_HAVE_MEMBLOCK=y -CONFIG_HAVE_MEMBLOCK_NODE_MAP=y -CONFIG_HAVE_MEMORY_PRESENT=y -CONFIG_HAVE_MOD_ARCH_SPECIFIC=y -CONFIG_HAVE_NET_DSA=y -CONFIG_HAVE_OPROFILE=y -CONFIG_HAVE_PERF_EVENTS=y -CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y -CONFIG_HAVE_SYSCALL_TRACEPOINTS=y -CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y -CONFIG_HOLES_IN_ZONE=y -# CONFIG_HUGETLBFS is not set -CONFIG_HW_HAS_PCI=y -CONFIG_HW_RANDOM=y -CONFIG_HW_RANDOM_OCTEON=y -CONFIG_HZ=250 -# CONFIG_HZ_100 is not set -CONFIG_HZ_250=y -CONFIG_HZ_PERIODIC=y -CONFIG_IMAGE_CMDLINE_HACK=y -CONFIG_INITRAMFS_SOURCE="" -CONFIG_IOMMU_HELPER=y -CONFIG_IRQCHIP=y -CONFIG_IRQ_DOMAIN=y -CONFIG_IRQ_FORCED_THREADING=y -CONFIG_IRQ_WORK=y -CONFIG_JBD2=y -CONFIG_KALLSYMS=y -CONFIG_KEXEC=y -CONFIG_KEXEC_CORE=y -CONFIG_LIBFDT=y -CONFIG_MDIO_BUS=y -CONFIG_MDIO_CAVIUM=y -CONFIG_MDIO_DEVICE=y -CONFIG_MDIO_OCTEON=y -CONFIG_MIGRATION=y -CONFIG_MIPS=y -# CONFIG_MIPS32_N32 is not set -# CONFIG_MIPS32_O32 is not set -CONFIG_MIPS_ASID_BITS=8 -CONFIG_MIPS_ASID_SHIFT=0 -# CONFIG_MIPS_CLOCK_VSYSCALL is not set -# CONFIG_MIPS_CMDLINE_DTB_EXTEND is not set -CONFIG_MIPS_CMDLINE_FROM_BOOTLOADER=y -# CONFIG_MIPS_CMDLINE_FROM_DTB is not set -CONFIG_MIPS_EBPF_JIT=y -# CONFIG_MIPS_ELF_APPENDED_DTB is not set -# CONFIG_MIPS_HUGE_TLB_SUPPORT is not set -CONFIG_MIPS_L1_CACHE_SHIFT=7 -CONFIG_MIPS_L1_CACHE_SHIFT_7=y -# CONFIG_MIPS_MACHINE is not set -# CONFIG_MIPS_NO_APPENDED_DTB is not set -CONFIG_MIPS_PGD_C0_CONTEXT=y -CONFIG_MIPS_RAW_APPENDED_DTB=y -CONFIG_MIPS_SPRAM=y -# CONFIG_MIPS_VA_BITS_48 is not set -CONFIG_MMC=y -CONFIG_MMC_BLOCK=y -CONFIG_MMC_CAVIUM_OCTEON=y -# CONFIG_MMC_TIFM_SD is not set -CONFIG_MODULES_USE_ELF_REL=y -CONFIG_MODULES_USE_ELF_RELA=y -# CONFIG_MTD_CFI_INTELEXT is not set -CONFIG_MTD_CMDLINE_PARTS=y -CONFIG_MTD_PHYSMAP=y -CONFIG_NEED_SG_DMA_LENGTH=y -CONFIG_NET_FLOW_LIMIT=y -CONFIG_NLS=y -CONFIG_NLS_CODEPAGE_437=y -CONFIG_NLS_ISO8859_1=y -CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y -# CONFIG_NO_IOPORT_MAP is not set -CONFIG_NR_CPUS=16 -CONFIG_NR_CPUS_DEFAULT_16=y -CONFIG_OCTEON_ETHERNET=y -# CONFIG_OCTEON_ILM is not set -CONFIG_OCTEON_MGMT_ETHERNET=y -CONFIG_OCTEON_USB=y -CONFIG_OCTEON_WDT=y -CONFIG_OF=y -CONFIG_OF_ADDRESS=y -CONFIG_OF_ADDRESS_PCI=y -CONFIG_OF_EARLY_FLATTREE=y -CONFIG_OF_FLATTREE=y -CONFIG_OF_GPIO=y -CONFIG_OF_IRQ=y -CONFIG_OF_MDIO=y -CONFIG_OF_NET=y -CONFIG_OF_PCI=y -CONFIG_OF_PCI_IRQ=y -CONFIG_PADATA=y -# CONFIG_PARTITION_ADVANCED is not set -CONFIG_PCI=y -CONFIG_PCI_BUS_ADDR_T_64BIT=y -CONFIG_PCI_DOMAINS=y -CONFIG_PCI_DRIVERS_LEGACY=y -CONFIG_PERF_USE_VMALLOC=y -CONFIG_PGTABLE_LEVELS=3 -CONFIG_PHYLIB=y -CONFIG_PHYS_ADDR_T_64BIT=y -CONFIG_POSIX_MQUEUE=y -CONFIG_POSIX_MQUEUE_SYSCTL=y -CONFIG_QUEUED_RWLOCKS=y -CONFIG_QUEUED_SPINLOCKS=y -CONFIG_RCU_NEED_SEGCBLIST=y -CONFIG_RCU_STALL_COMMON=y -CONFIG_RELAY=y -CONFIG_RFS_ACCEL=y -CONFIG_RPS=y -CONFIG_SCHED_DEBUG=y -# CONFIG_SCHED_INFO is not set -CONFIG_SCSI=y -CONFIG_SECCOMP=y -CONFIG_SECCOMP_FILTER=y -CONFIG_SERIAL_8250_DW=y -# CONFIG_SERIAL_8250_FSL is not set -CONFIG_SG_POOL=y -CONFIG_SMP=y -CONFIG_SPARSEMEM=y -CONFIG_SPARSEMEM_STATIC=y -CONFIG_SRCU=y -CONFIG_SWIOTLB=y -CONFIG_SWPHY=y -CONFIG_SYSCTL_EXCEPTION_TRACE=y -CONFIG_SYSFS_DEPRECATED=y -CONFIG_SYSFS_DEPRECATED_V2=y -CONFIG_SYS_HAS_CPU_CAVIUM_OCTEON=y -CONFIG_SYS_HAS_EARLY_PRINTK=y -CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y -CONFIG_SYS_SUPPORTS_ARBIT_HZ=y -CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y -CONFIG_SYS_SUPPORTS_HOTPLUG_CPU=y -CONFIG_SYS_SUPPORTS_HUGETLBFS=y -CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y -CONFIG_SYS_SUPPORTS_RELOCATABLE=y -CONFIG_SYS_SUPPORTS_SMP=y -CONFIG_TICK_CPU_ACCOUNTING=y -CONFIG_TREE_RCU=y -CONFIG_TREE_SRCU=y -CONFIG_UNINLINE_SPIN_UNLOCK=y -CONFIG_USB=y -CONFIG_USB_COMMON=y -CONFIG_USB_EHCI_BIG_ENDIAN_MMIO=y -CONFIG_USB_EHCI_HCD=y -CONFIG_USB_EHCI_HCD_PLATFORM=y -CONFIG_USB_OCTEON_EHCI=y -CONFIG_USB_OCTEON_OHCI=y -CONFIG_USB_OHCI_BIG_ENDIAN_MMIO=y -CONFIG_USB_OHCI_HCD=y -CONFIG_USB_OHCI_HCD_PLATFORM=y -CONFIG_USB_STORAGE=y -CONFIG_USB_SUPPORT=y -CONFIG_USE_OF=y -CONFIG_VFAT_FS=y -CONFIG_VM_EVENT_COUNTERS=y -CONFIG_WATCHDOG_CORE=y -CONFIG_WEAK_ORDERING=y -CONFIG_XPS=y -CONFIG_ZLIB_INFLATE=y -CONFIG_ZONE_DMA32=y diff --git a/target/linux/octeon/patches-4.14/100-ubnt_edgerouter2_support.patch b/target/linux/octeon/patches-4.14/100-ubnt_edgerouter2_support.patch deleted file mode 100644 index 991eb56ce2d8..000000000000 --- a/target/linux/octeon/patches-4.14/100-ubnt_edgerouter2_support.patch +++ /dev/null @@ -1,31 +0,0 @@ ---- a/arch/mips/include/asm/octeon/cvmx-bootinfo.h -+++ b/arch/mips/include/asm/octeon/cvmx-bootinfo.h -@@ -295,6 +295,8 @@ enum cvmx_board_types_enum { - */ - CVMX_BOARD_TYPE_CUST_PRIVATE_MIN = 20001, - CVMX_BOARD_TYPE_UBNT_E100 = 20002, -+ CVMX_BOARD_TYPE_UBNT_E200 = 20003, -+ CVMX_BOARD_TYPE_UBNT_E220 = 20005, - CVMX_BOARD_TYPE_CUST_DSR1000N = 20006, - CVMX_BOARD_TYPE_KONTRON_S1901 = 21901, - CVMX_BOARD_TYPE_CUST_PRIVATE_MAX = 30000, -@@ -396,6 +398,8 @@ static inline const char *cvmx_board_typ - /* Customer private range */ - ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_PRIVATE_MIN) - ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_UBNT_E100) -+ ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_UBNT_E200) -+ ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_UBNT_E220) - ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_DSR1000N) - ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_KONTRON_S1901) - ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_PRIVATE_MAX) ---- a/arch/mips/cavium-octeon/executive/cvmx-helper-board.c -+++ b/arch/mips/cavium-octeon/executive/cvmx-helper-board.c -@@ -173,6 +173,8 @@ int cvmx_helper_board_get_mii_address(in - return 7 - ipd_port; - else - return -1; -+ case CVMX_BOARD_TYPE_UBNT_E200: -+ return -1; - case CVMX_BOARD_TYPE_KONTRON_S1901: - if (ipd_port == CVMX_HELPER_BOARD_MGMT_IPD_PORT) - return 1; diff --git a/target/linux/octeon/patches-4.14/110-er200-ethernet_probe_order.patch b/target/linux/octeon/patches-4.14/110-er200-ethernet_probe_order.patch deleted file mode 100644 index 6b1eaf92a2b0..000000000000 --- a/target/linux/octeon/patches-4.14/110-er200-ethernet_probe_order.patch +++ /dev/null @@ -1,34 +0,0 @@ ---- a/drivers/staging/octeon/ethernet.c -+++ b/drivers/staging/octeon/ethernet.c -@@ -673,6 +673,7 @@ static int cvm_oct_probe(struct platform - int interface; - int fau = FAU_NUM_PACKET_BUFFERS_TO_FREE; - int qos; -+ int i; - struct device_node *pip; - int mtu_overhead = ETH_HLEN + ETH_FCS_LEN; - -@@ -796,13 +797,19 @@ static int cvm_oct_probe(struct platform - } - - num_interfaces = cvmx_helper_get_number_of_interfaces(); -- for (interface = 0; interface < num_interfaces; interface++) { -- cvmx_helper_interface_mode_t imode = -- cvmx_helper_interface_get_mode(interface); -- int num_ports = cvmx_helper_ports_on_interface(interface); -+ for (i = 0; i < num_interfaces; i++) { -+ cvmx_helper_interface_mode_t imode; -+ int interface; -+ int num_ports; - int port; - int port_index; - -+ interface = i; -+ if (cvmx_sysinfo_get()->board_type == CVMX_BOARD_TYPE_UBNT_E200) -+ interface = num_interfaces - (i + 1); -+ -+ num_ports = cvmx_helper_ports_on_interface(interface); -+ imode = cvmx_helper_interface_get_mode(interface); - for (port_index = 0, - port = cvmx_helper_get_ipd_port(interface, 0); - port < cvmx_helper_get_ipd_port(interface, num_ports); diff --git a/target/linux/octeon/patches-4.14/160-cmdline-hack.patch b/target/linux/octeon/patches-4.14/160-cmdline-hack.patch deleted file mode 100644 index e902e853e820..000000000000 --- a/target/linux/octeon/patches-4.14/160-cmdline-hack.patch +++ /dev/null @@ -1,47 +0,0 @@ ---- a/arch/mips/cavium-octeon/setup.c -+++ b/arch/mips/cavium-octeon/setup.c -@@ -650,6 +650,35 @@ void octeon_user_io_init(void) - write_c0_derraddr1(0); - } - -+#ifdef CONFIG_IMAGE_CMDLINE_HACK -+extern char __image_cmdline[]; -+ -+static int __init octeon_use_image_cmdline(void) -+{ -+ char *p = __image_cmdline; -+ int replace = 0; -+ -+ if (*p == '-') { -+ replace = 1; -+ p++; -+ } -+ -+ if (*p == '\0') -+ return 0; -+ -+ if (replace) { -+ strlcpy(arcs_cmdline, p, sizeof(arcs_cmdline)); -+ } else { -+ strlcat(arcs_cmdline, " ", sizeof(arcs_cmdline)); -+ strlcat(arcs_cmdline, p, sizeof(arcs_cmdline)); -+ } -+ -+ return 1; -+} -+#else -+static inline int octeon_use_image_cmdline(void) { return 0; } -+#endif -+ - /** - * Early entry point for arch setup - */ -@@ -894,6 +923,8 @@ void __init prom_init(void) - } - } - -+ octeon_use_image_cmdline(); -+ - if (strstr(arcs_cmdline, "console=") == NULL) { - if (octeon_uart == 1) - strcat(arcs_cmdline, " console=ttyS1,115200"); diff --git a/target/linux/octeon/patches-4.14/170-cisco-hack.patch b/target/linux/octeon/patches-4.14/170-cisco-hack.patch deleted file mode 100644 index 72774209dc35..000000000000 --- a/target/linux/octeon/patches-4.14/170-cisco-hack.patch +++ /dev/null @@ -1,31 +0,0 @@ -From patchwork Wed Jun 8 13:49:26 2016 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 8bit -Subject: [LEDE-DEV] cavium: Ignore MEM boot param when too small -From: =?utf-8?q?Micha=C5=82_Osowiecki?= -X-Patchwork-Id: 632273 -Message-Id: <57582266.8020105@gmail.com> -To: lede-dev@lists.infradead.org -Date: Wed, 8 Jun 2016 15:49:26 +0200 - -Cisco RV0XX u-boot sets MEM=2048 as boot param. We assume that at least -4MB (mem_alloc_size) of ram is needed to run linux on cavium boards, so -if mem < 4M - ignore it and set default value - - -Signed-off-by: MichaÅ‚ Osowiecki - ---- a/arch/mips/cavium-octeon/setup.c -+++ b/arch/mips/cavium-octeon/setup.c -@@ -1018,6 +1018,10 @@ void __init plat_mem_setup(void) - if (mem_alloc_size > max_memory) - mem_alloc_size = max_memory; - -+ /* Ignore bootarg MEM <= 4MB - cisco uses a b0rked uboot env on their products */ -+ if (max_memory <= mem_alloc_size) -+ max_memory = 512ull << 20; -+ - /* Crashkernel ignores bootmem list. It relies on mem=X@Y option */ - #ifdef CONFIG_CRASH_DUMP - add_memory_region(reserve_low_mem, max_memory, BOOT_MEM_RAM); From patchwork Sun Mar 1 12:12:39 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Hauke Mehrtens X-Patchwork-Id: 1247286 X-Patchwork-Delegate: hauke@hauke-m.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.openwrt.org (client-ip=2607:7c80:54:e::133; helo=bombadil.infradead.org; envelope-from=openwrt-devel-bounces+incoming=patchwork.ozlabs.org@lists.openwrt.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=hauke-m.de Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=lists.infradead.org header.i=@lists.infradead.org header.a=rsa-sha256 header.s=bombadil.20170209 header.b=irl2RPdr; dkim-atps=neutral Received: from bombadil.infradead.org (bombadil.infradead.org [IPv6:2607:7c80:54:e::133]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 48Vj015kXYz9sQt for ; Sun, 1 Mar 2020 23:15:13 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Subject:MIME-Version:References: In-Reply-To:Message-Id:Date:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=puU+iw4FBEVaqwrWqSzWRegEyqfMaggJh+E1KVSc2wA=; b=irl2RPdrjGj50D ivSbUo6IxwNAc2rYqct8nADPQehb4lDdBjOtTVONPMc6wWf+i/iu6TbqYcd+TcBis3oE7Gh4bzGtC CHcUCX62eeGxEks9CaAPH8s3qTRT26+4/9r1kGKlb7BWLu54oB6Kqt45N1sDh4EeTRsYdP89JV17G 8jEW2OgS0AU7uribfqTJpi15Z6GG7W94c9/BgJmc2C9XDih+HMPbMfCyvdp8D6w1ExyEHAYFLHAeI YTPMXdXGGkkF0HxA/tB6OHUG5kVnmTFFMDiihr+9+Mcmx5nYOtWgZDpZHnffLTxi16/Z4SBiXENqc s/YgFx4jWrteJ8QSlW9A==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1j8NUu-0000LR-VU; Sun, 01 Mar 2020 12:15:05 +0000 Received: from mout-p-102.mailbox.org ([2001:67c:2050::465:102]) by bombadil.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1j8NSu-0006kV-M0 for openwrt-devel@lists.openwrt.org; Sun, 01 Mar 2020 12:13:13 +0000 Received: from smtp2.mailbox.org (smtp2.mailbox.org [80.241.60.241]) (using TLSv1.2 with cipher ECDHE-RSA-CHACHA20-POLY1305 (256/256 bits)) (No client certificate requested) by mout-p-102.mailbox.org (Postfix) with ESMTPS id 48VhxR0nRhzKmXw; Sun, 1 Mar 2020 13:12:59 +0100 (CET) X-Virus-Scanned: amavisd-new at heinlein-support.de Received: from smtp2.mailbox.org ([80.241.60.241]) by spamfilter06.heinlein-hosting.de (spamfilter06.heinlein-hosting.de [80.241.56.125]) (amavisd-new, port 10030) with ESMTP id T9FAyfzhT5lN; Sun, 1 Mar 2020 13:12:53 +0100 (CET) From: Hauke Mehrtens To: openwrt-devel@lists.openwrt.org Date: Sun, 1 Mar 2020 13:12:39 +0100 Message-Id: <20200301121241.5545-11-hauke@hauke-m.de> In-Reply-To: <20200301121241.5545-1-hauke@hauke-m.de> References: <20200301121241.5545-1-hauke@hauke-m.de> MIME-Version: 1.0 X-Spam-Note: CRM114 run bypassed due to message size (119965 bytes) X-Spam-Score: 0.0 (/) X-Spam-Report: SpamAssassin version 3.4.3 on bombadil.infradead.org summary: Content analysis details: (0.0 points) pts rule name description ---- ---------------------- -------------------------------------------------- 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.0 SPF_PASS SPF: sender matches SPF record Subject: [OpenWrt-Devel] [PATCH 10/12] sunxi: Remove kernel 4.14 support X-BeenThere: openwrt-devel@lists.openwrt.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: hauke@hauke-m.de Sender: "openwrt-devel" Errors-To: openwrt-devel-bounces+incoming=patchwork.ozlabs.org@lists.openwrt.org This target was switched to kernel 4.19 more than 6 months ago in commit f342ffd300da ("treewide: kernel: bump some targets to 4.19") and now with kernel 5.4 support being added it gets harder to support kernel 4.14 in addition to kernel 4.19 and 5.4. Signed-off-by: Hauke Mehrtens --- target/linux/sunxi/config-4.14 | 601 ------------------ target/linux/sunxi/cortexa53/config-4.14 | 102 --- target/linux/sunxi/cortexa7/config-4.14 | 10 - target/linux/sunxi/cortexa8/config-4.14 | 21 - ...dwmac-mdio-MDIOs-are-automatically-r.patch | 33 - ...-sun8i-Handle-integrated-external-MD.patch | 506 --------------- ...stmmac-sun8i-Restore-the-compatibles.patch | 35 - ...-sun8i-fix-allwinner-leds-active-low.patch | 29 - ...ts-sunxi-Restore-EMAC-changes-boards.patch | 292 --------- ...dts-sunxi-h3-h5-Restore-EMAC-changes.patch | 54 -- ...-h5-represent-the-mdio-switch-used-b.patch | 59 -- ...s-allwinner-A64-Restore-EMAC-changes.patch | 184 ------ ...ner-add-snps-dwmac-mdio-compatible-t.patch | 28 - ...ts-allwinner-H5-Restore-EMAC-changes.patch | 120 ---- ...a64-add-Ethernet-PHY-regulator-for-s.patch | 51 -- ...arch_counter_get_cntpct-to-read-the-.patch | 118 ---- ...arm64-dts-allwinner-a64-Add-watchdog.patch | 47 -- ...s-sun8i-add-support-for-Orange-Pi-R1.patch | 105 --- ...i-support-for-nanopi-neo-plus2-board.patch | 242 ------- ...80-arm64-allwinner-a64-add-SPI-nodes.patch | 78 --- ...ner-sun50i-a64-Add-spi-flash-node-fo.patch | 36 -- ...ers-arch_timer-Workaround-for-Allwin.patch | 244 ------- ...nner-a64-Enable-A64-timer-workaround.patch | 26 - ...n8i-fix-USB-Ethernet-of-Orange-Pi-R1.patch | 48 -- ...s-sun8i-activate-SPI-on-Orange-Pi-R1.patch | 29 - .../220-ARM-dts-orange-pi-zero-plus.patch | 185 ------ ...angepi_pc2_usb_otg_to_host_key_power.patch | 20 - ...un7i-Add-BCM53125-switch-nodes-to-th.patch | 88 --- ...a64-sopine-Add-Sopine-flash-partitio.patch | 46 -- 29 files changed, 3437 deletions(-) delete mode 100644 target/linux/sunxi/config-4.14 delete mode 100644 target/linux/sunxi/cortexa53/config-4.14 delete mode 100644 target/linux/sunxi/cortexa7/config-4.14 delete mode 100644 target/linux/sunxi/cortexa8/config-4.14 delete mode 100644 target/linux/sunxi/patches-4.14/001-net-stmmac-snps-dwmac-mdio-MDIOs-are-automatically-r.patch delete mode 100644 target/linux/sunxi/patches-4.14/002-net-stmmac-dwmac-sun8i-Handle-integrated-external-MD.patch delete mode 100644 target/linux/sunxi/patches-4.14/003-net-stmmac-sun8i-Restore-the-compatibles.patch delete mode 100644 target/linux/sunxi/patches-4.14/004-net-stmmac-dwmac-sun8i-fix-allwinner-leds-active-low.patch delete mode 100644 target/linux/sunxi/patches-4.14/020-ARM-dts-sunxi-Restore-EMAC-changes-boards.patch delete mode 100644 target/linux/sunxi/patches-4.14/021-arm-dts-sunxi-h3-h5-Restore-EMAC-changes.patch delete mode 100644 target/linux/sunxi/patches-4.14/022-ARM-dts-sunxi-h3-h5-represent-the-mdio-switch-used-b.patch delete mode 100644 target/linux/sunxi/patches-4.14/025-arm64-dts-allwinner-A64-Restore-EMAC-changes.patch delete mode 100644 target/linux/sunxi/patches-4.14/026-arm64-dts-allwinner-add-snps-dwmac-mdio-compatible-t.patch delete mode 100644 target/linux/sunxi/patches-4.14/027-arm64-dts-allwinner-H5-Restore-EMAC-changes.patch delete mode 100644 target/linux/sunxi/patches-4.14/030-arm64-allwinner-a64-add-Ethernet-PHY-regulator-for-s.patch delete mode 100644 target/linux/sunxi/patches-4.14/031-arm64-Implement-arch_counter_get_cntpct-to-read-the-.patch delete mode 100644 target/linux/sunxi/patches-4.14/040-arm64-dts-allwinner-a64-Add-watchdog.patch delete mode 100644 target/linux/sunxi/patches-4.14/060-ARM-dts-sun8i-add-support-for-Orange-Pi-R1.patch delete mode 100644 target/linux/sunxi/patches-4.14/061-arm-dts-sun50i-support-for-nanopi-neo-plus2-board.patch delete mode 100644 target/linux/sunxi/patches-4.14/080-arm64-allwinner-a64-add-SPI-nodes.patch delete mode 100644 target/linux/sunxi/patches-4.14/081-arm64-dts-allwinner-sun50i-a64-Add-spi-flash-node-fo.patch delete mode 100644 target/linux/sunxi/patches-4.14/100-clocksource-drivers-arch_timer-Workaround-for-Allwin.patch delete mode 100644 target/linux/sunxi/patches-4.14/101-arm64-dts-allwinner-a64-Enable-A64-timer-workaround.patch delete mode 100644 target/linux/sunxi/patches-4.14/201-ARM-dts-sun8i-fix-USB-Ethernet-of-Orange-Pi-R1.patch delete mode 100644 target/linux/sunxi/patches-4.14/202-ARM-dts-sun8i-activate-SPI-on-Orange-Pi-R1.patch delete mode 100644 target/linux/sunxi/patches-4.14/220-ARM-dts-orange-pi-zero-plus.patch delete mode 100644 target/linux/sunxi/patches-4.14/301-orangepi_pc2_usb_otg_to_host_key_power.patch delete mode 100644 target/linux/sunxi/patches-4.14/310-Revert-ARM-dts-sun7i-Add-BCM53125-switch-nodes-to-th.patch delete mode 100644 target/linux/sunxi/patches-4.14/400-arm64-allwinner-a64-sopine-Add-Sopine-flash-partitio.patch diff --git a/target/linux/sunxi/config-4.14 b/target/linux/sunxi/config-4.14 deleted file mode 100644 index 6e19f1599b99..000000000000 --- a/target/linux/sunxi/config-4.14 +++ /dev/null @@ -1,601 +0,0 @@ -# CONFIG_AHCI_SUNXI is not set -CONFIG_ALIGNMENT_TRAP=y -# CONFIG_ARCH_AXXIA is not set -CONFIG_ARCH_CLOCKSOURCE_DATA=y -CONFIG_ARCH_HAS_DEBUG_VIRTUAL=y -CONFIG_ARCH_HAS_ELF_RANDOMIZE=y -CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y -CONFIG_ARCH_HAS_RESET_CONTROLLER=y -CONFIG_ARCH_HAS_SET_MEMORY=y -CONFIG_ARCH_HAS_SG_CHAIN=y -CONFIG_ARCH_HAS_STRICT_KERNEL_RWX=y -CONFIG_ARCH_HAS_STRICT_MODULE_RWX=y -CONFIG_ARCH_HAS_TICK_BROADCAST=y -CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y -CONFIG_ARCH_HIBERNATION_POSSIBLE=y -CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y -CONFIG_ARCH_MULTIPLATFORM=y -# CONFIG_ARCH_MULTI_CPU_AUTO is not set -CONFIG_ARCH_MULTI_V6_V7=y -CONFIG_ARCH_MULTI_V7=y -CONFIG_ARCH_NR_GPIO=416 -CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y -CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y -CONFIG_ARCH_PHYS_ADDR_T_64BIT=y -# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set -# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set -CONFIG_ARCH_SUNXI=y -CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y -CONFIG_ARCH_SUPPORTS_BIG_ENDIAN=y -CONFIG_ARCH_SUPPORTS_UPROBES=y -CONFIG_ARCH_SUSPEND_POSSIBLE=y -CONFIG_ARCH_USE_BUILTIN_BSWAP=y -CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y -CONFIG_ARCH_WANT_GENERAL_HUGETLB=y -CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y -CONFIG_ARM=y -CONFIG_ARM_APPENDED_DTB=y -CONFIG_ARM_ARCH_TIMER=y -CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y -CONFIG_ARM_ATAG_DTB_COMPAT=y -# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set -CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y -CONFIG_ARM_CPU_SUSPEND=y -CONFIG_ARM_ERRATA_643719=y -CONFIG_ARM_GIC=y -CONFIG_ARM_HAS_SG_CHAIN=y -CONFIG_ARM_HEAVY_MB=y -CONFIG_ARM_L1_CACHE_SHIFT=6 -CONFIG_ARM_L1_CACHE_SHIFT_6=y -CONFIG_ARM_LPAE=y -CONFIG_ARM_PATCH_IDIV=y -CONFIG_ARM_PATCH_PHYS_VIRT=y -CONFIG_ARM_PMU=y -CONFIG_ARM_PSCI=y -CONFIG_ARM_PSCI_FW=y -CONFIG_ARM_THUMB=y -# CONFIG_ARM_THUMBEE is not set -CONFIG_ARM_UNWIND=y -CONFIG_ARM_VIRT_EXT=y -CONFIG_ATA=y -CONFIG_ATAGS=y -# CONFIG_ATA_SFF is not set -CONFIG_AUTO_ZRELADDR=y -CONFIG_AXP20X_POWER=y -CONFIG_BACKLIGHT_CLASS_DEVICE=y -CONFIG_BACKLIGHT_LCD_SUPPORT=y -CONFIG_BACKLIGHT_PWM=y -CONFIG_BLK_DEV_LOOP=y -CONFIG_BLK_DEV_SD=y -CONFIG_BLK_SCSI_REQUEST=y -CONFIG_BOUNCE=y -CONFIG_CACHE_L2X0=y -CONFIG_CAN=y -CONFIG_CLKDEV_LOOKUP=y -CONFIG_CLKSRC_MMIO=y -CONFIG_CLONE_BACKWARDS=y -CONFIG_COMMON_CLK=y -CONFIG_CONFIGFS_FS=y -CONFIG_CONNECTOR=y -CONFIG_CONSOLE_TRANSLATIONS=y -CONFIG_COREDUMP=y -CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y -CONFIG_CPUFREQ_DT=y -CONFIG_CPUFREQ_DT_PLATDEV=y -CONFIG_CPU_32v6K=y -CONFIG_CPU_32v7=y -CONFIG_CPU_ABRT_EV7=y -# CONFIG_CPU_BIG_ENDIAN is not set -# CONFIG_CPU_BPREDICT_DISABLE is not set -CONFIG_CPU_CACHE_V7=y -CONFIG_CPU_CACHE_VIPT=y -CONFIG_CPU_COPY_V6=y -CONFIG_CPU_CP15=y -CONFIG_CPU_CP15_MMU=y -CONFIG_CPU_FREQ=y -CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y -CONFIG_CPU_FREQ_GOV_ATTR_SET=y -CONFIG_CPU_FREQ_GOV_COMMON=y -CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y -CONFIG_CPU_FREQ_GOV_ONDEMAND=y -CONFIG_CPU_FREQ_GOV_PERFORMANCE=y -CONFIG_CPU_FREQ_GOV_POWERSAVE=y -CONFIG_CPU_FREQ_GOV_USERSPACE=y -CONFIG_CPU_FREQ_STAT=y -CONFIG_CPU_HAS_ASID=y -# CONFIG_CPU_HOTPLUG_STATE_CONTROL is not set -# CONFIG_CPU_ICACHE_DISABLE is not set -CONFIG_CPU_PABRT_V7=y -CONFIG_CPU_PM=y -CONFIG_CPU_RMAP=y -CONFIG_CPU_SPECTRE=y -CONFIG_CPU_THERMAL=y -CONFIG_CPU_THUMB_CAPABLE=y -CONFIG_CPU_TLB_V7=y -CONFIG_CPU_V7=y -CONFIG_CRC16=y -CONFIG_CRC_T10DIF=y -CONFIG_CRYPTO_AEAD=y -CONFIG_CRYPTO_AEAD2=y -CONFIG_CRYPTO_CRC32=y -CONFIG_CRYPTO_CRC32C=y -CONFIG_CRYPTO_CRCT10DIF=y -CONFIG_CRYPTO_DES=y -CONFIG_CRYPTO_DEV_SUN4I_SS=y -CONFIG_CRYPTO_DEV_SUN4I_SS_PRNG=y -CONFIG_CRYPTO_HASH=y -CONFIG_CRYPTO_HASH2=y -CONFIG_CRYPTO_HW=y -CONFIG_CRYPTO_MANAGER=y -CONFIG_CRYPTO_MANAGER2=y -CONFIG_CRYPTO_MD5=y -CONFIG_CRYPTO_NULL2=y -CONFIG_CRYPTO_RNG=y -CONFIG_CRYPTO_RNG2=y -CONFIG_CRYPTO_SHA1=y -CONFIG_CRYPTO_WORKQUEUE=y -CONFIG_DCACHE_WORD_ACCESS=y -CONFIG_DEBUG_BUGVERBOSE=y -CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" -CONFIG_DEBUG_MEMORY_INIT=y -# CONFIG_DEBUG_UART_8250 is not set -# CONFIG_DEBUG_USER is not set -CONFIG_DEFAULT_CFQ=y -# CONFIG_DEFAULT_DEADLINE is not set -CONFIG_DEFAULT_IOSCHED="cfq" -CONFIG_DMADEVICES=y -CONFIG_DMA_ENGINE=y -CONFIG_DMA_OF=y -CONFIG_DMA_SUN4I=y -CONFIG_DMA_SUN6I=y -CONFIG_DMA_VIRTUAL_CHANNELS=y -CONFIG_DNOTIFY=y -CONFIG_DTC=y -CONFIG_DUMMY_CONSOLE=y -# CONFIG_DWMAC_DWC_QOS_ETH is not set -CONFIG_DWMAC_GENERIC=y -# CONFIG_DWMAC_SUN8I is not set -CONFIG_DWMAC_SUNXI=y -CONFIG_DYNAMIC_DEBUG=y -CONFIG_EDAC_ATOMIC_SCRUB=y -CONFIG_EDAC_SUPPORT=y -CONFIG_ELF_CORE=y -CONFIG_ENABLE_MUST_CHECK=y -# CONFIG_ENABLE_WARN_DEPRECATED is not set -CONFIG_EXT4_FS=y -CONFIG_EXTCON=y -# CONFIG_F2FS_CHECK_FS is not set -CONFIG_F2FS_FS=y -# CONFIG_F2FS_FS_SECURITY is not set -CONFIG_F2FS_FS_XATTR=y -CONFIG_F2FS_STAT_FS=y -CONFIG_FAT_FS=y -CONFIG_FB=y -CONFIG_FB_CFB_COPYAREA=y -CONFIG_FB_CFB_FILLRECT=y -CONFIG_FB_CFB_IMAGEBLIT=y -CONFIG_FB_CMDLINE=y -CONFIG_FB_FOREIGN_ENDIAN=y -CONFIG_FB_LITTLE_ENDIAN=y -CONFIG_FB_MODE_HELPERS=y -# CONFIG_FB_PROVIDE_GET_FB_UNMAPPED_AREA is not set -CONFIG_FB_SIMPLE=y -CONFIG_FB_TILEBLITTING=y -CONFIG_FIXED_PHY=y -CONFIG_FIX_EARLYCON_MEM=y -# CONFIG_FONTS is not set -CONFIG_FONT_8x16=y -CONFIG_FONT_8x8=y -CONFIG_FONT_SUPPORT=y -CONFIG_FRAMEBUFFER_CONSOLE=y -CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y -CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y -CONFIG_FRAME_WARN=2048 -CONFIG_FREEZER=y -CONFIG_FS_MBCACHE=y -CONFIG_FS_POSIX_ACL=y -CONFIG_GENERIC_ALLOCATOR=y -CONFIG_GENERIC_ARCH_TOPOLOGY=y -CONFIG_GENERIC_BUG=y -CONFIG_GENERIC_CLOCKEVENTS=y -CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y -CONFIG_GENERIC_CPU_AUTOPROBE=y -CONFIG_GENERIC_EARLY_IOREMAP=y -CONFIG_GENERIC_IDLE_POLL_SETUP=y -CONFIG_GENERIC_IO=y -CONFIG_GENERIC_IRQ_CHIP=y -CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y -CONFIG_GENERIC_IRQ_SHOW=y -CONFIG_GENERIC_IRQ_SHOW_LEVEL=y -CONFIG_GENERIC_PCI_IOMAP=y -CONFIG_GENERIC_PHY=y -CONFIG_GENERIC_PINCONF=y -CONFIG_GENERIC_SCHED_CLOCK=y -CONFIG_GENERIC_SMP_IDLE_THREAD=y -CONFIG_GENERIC_STRNCPY_FROM_USER=y -CONFIG_GENERIC_STRNLEN_USER=y -CONFIG_GENERIC_TIME_VSYSCALL=y -CONFIG_GLOB=y -CONFIG_GPIOLIB=y -CONFIG_GPIO_AXP209=y -CONFIG_GPIO_SYSFS=y -# CONFIG_GRO_CELLS is not set -CONFIG_HANDLE_DOMAIN_IRQ=y -CONFIG_HARDEN_BRANCH_PREDICTOR=y -CONFIG_HARDIRQS_SW_RESEND=y -CONFIG_HAS_DMA=y -CONFIG_HAS_IOMEM=y -CONFIG_HAS_IOPORT_MAP=y -# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set -CONFIG_HAVE_ARCH_AUDITSYSCALL=y -CONFIG_HAVE_ARCH_BITREVERSE=y -CONFIG_HAVE_ARCH_JUMP_LABEL=y -CONFIG_HAVE_ARCH_KGDB=y -CONFIG_HAVE_ARCH_PFN_VALID=y -CONFIG_HAVE_ARCH_SECCOMP_FILTER=y -CONFIG_HAVE_ARCH_TRACEHOOK=y -CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE=y -CONFIG_HAVE_ARM_ARCH_TIMER=y -CONFIG_HAVE_ARM_SMCCC=y -# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set -CONFIG_HAVE_CC_STACKPROTECTOR=y -CONFIG_HAVE_CLK=y -CONFIG_HAVE_CLK_PREPARE=y -CONFIG_HAVE_CONTEXT_TRACKING=y -CONFIG_HAVE_C_RECORDMCOUNT=y -CONFIG_HAVE_DEBUG_KMEMLEAK=y -CONFIG_HAVE_DMA_API_DEBUG=y -CONFIG_HAVE_DMA_CONTIGUOUS=y -CONFIG_HAVE_DYNAMIC_FTRACE=y -CONFIG_HAVE_DYNAMIC_FTRACE_WITH_REGS=y -CONFIG_HAVE_EBPF_JIT=y -CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y -CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y -CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y -CONFIG_HAVE_FUNCTION_TRACER=y -CONFIG_HAVE_GENERIC_DMA_COHERENT=y -CONFIG_HAVE_GENERIC_GUP=y -CONFIG_HAVE_HW_BREAKPOINT=y -CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y -CONFIG_HAVE_KVM_ARCH_TLB_FLUSH_ALL=y -CONFIG_HAVE_KVM_CPU_RELAX_INTERCEPT=y -CONFIG_HAVE_KVM_EVENTFD=y -CONFIG_HAVE_KVM_IRQCHIP=y -CONFIG_HAVE_KVM_IRQFD=y -CONFIG_HAVE_KVM_IRQ_ROUTING=y -CONFIG_HAVE_KVM_MSI=y -CONFIG_HAVE_MEMBLOCK=y -CONFIG_HAVE_MOD_ARCH_SPECIFIC=y -CONFIG_HAVE_NET_DSA=y -CONFIG_HAVE_OPROFILE=y -CONFIG_HAVE_OPTPROBES=y -CONFIG_HAVE_PERF_EVENTS=y -CONFIG_HAVE_PERF_REGS=y -CONFIG_HAVE_PERF_USER_STACK_DUMP=y -CONFIG_HAVE_PROC_CPU=y -CONFIG_HAVE_RCU_TABLE_FREE=y -CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y -CONFIG_HAVE_SMP=y -CONFIG_HAVE_SYSCALL_TRACEPOINTS=y -CONFIG_HAVE_UID16=y -CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y -CONFIG_HIGHMEM=y -CONFIG_HIGHPTE=y -CONFIG_HOTPLUG_CPU=y -# CONFIG_HUGETLBFS is not set -CONFIG_HWMON=y -CONFIG_HW_CONSOLE=y -CONFIG_HW_RANDOM=y -CONFIG_HW_RANDOM_TIMERIOMEM=y -CONFIG_HZ_FIXED=0 -CONFIG_I2C=y -CONFIG_I2C_BOARDINFO=y -CONFIG_I2C_CHARDEV=y -CONFIG_I2C_COMPAT=y -CONFIG_I2C_HELPER_AUTO=y -CONFIG_I2C_MV64XXX=y -CONFIG_I2C_SUN6I_P2WI=y -CONFIG_IIO=y -# CONFIG_IIO_BUFFER is not set -# CONFIG_IIO_TRIGGER is not set -CONFIG_INITRAMFS_SOURCE="" -CONFIG_INPUT=y -CONFIG_INPUT_AXP20X_PEK=y -CONFIG_INPUT_KEYBOARD=y -CONFIG_INPUT_MOUSEDEV=y -CONFIG_INPUT_MOUSEDEV_PSAUX=y -CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 -CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 -CONFIG_INPUT_TOUCHSCREEN=y -CONFIG_IOMMU_HELPER=y -CONFIG_IOSCHED_CFQ=y -CONFIG_IRQCHIP=y -CONFIG_IRQ_DOMAIN=y -CONFIG_IRQ_DOMAIN_HIERARCHY=y -CONFIG_IRQ_FORCED_THREADING=y -CONFIG_IRQ_WORK=y -CONFIG_JBD2=y -CONFIG_KALLSYMS=y -# CONFIG_KERNEL_MODE_NEON is not set -CONFIG_KEYBOARD_SUN4I_LRADC=y -CONFIG_KSM=y -CONFIG_KVM=y -CONFIG_KVM_ARM_HOST=y -CONFIG_KVM_GENERIC_DIRTYLOG_READ_PROTECT=y -CONFIG_KVM_MMIO=y -CONFIG_KVM_VFIO=y -CONFIG_LCD_CLASS_DEVICE=y -CONFIG_LCD_PLATFORM=y -CONFIG_LEDS_GPIO=y -CONFIG_LIBFDT=y -CONFIG_LOCK_SPIN_ON_OWNER=y -CONFIG_LOGO=y -CONFIG_LOGO_LINUX_CLUT224=y -CONFIG_LOGO_LINUX_MONO=y -CONFIG_LOGO_LINUX_VGA16=y -CONFIG_MACH_SUN4I=y -CONFIG_MACH_SUN5I=y -CONFIG_MACH_SUN6I=y -CONFIG_MACH_SUN7I=y -CONFIG_MACH_SUN8I=y -CONFIG_MACH_SUN9I=y -CONFIG_MAGIC_SYSRQ=y -CONFIG_MDIO_BUS=y -CONFIG_MDIO_DEVICE=y -CONFIG_MDIO_SUN4I=y -CONFIG_MEDIA_SUPPORT=y -# CONFIG_MFD_AC100 is not set -CONFIG_MFD_AXP20X=y -CONFIG_MFD_AXP20X_I2C=y -CONFIG_MFD_AXP20X_RSB=y -CONFIG_MFD_CORE=y -CONFIG_MFD_SUN6I_PRCM=y -CONFIG_MFD_SYSCON=y -CONFIG_MIGHT_HAVE_CACHE_L2X0=y -CONFIG_MIGHT_HAVE_PCI=y -CONFIG_MIGRATION=y -CONFIG_MMC=y -CONFIG_MMC_BLOCK=y -CONFIG_MMC_SUNXI=y -CONFIG_MMU_NOTIFIER=y -CONFIG_MODULES_TREE_LOOKUP=y -CONFIG_MODULES_USE_ELF_REL=y -CONFIG_MTD=y -CONFIG_MTD_SPLIT_SUPPORT=y -CONFIG_MTD_SPLIT_FIT_FW=y -CONFIG_MTD_OF_PARTS=y -CONFIG_MTD_JEDECPROBE=y -# CONFIG_MTD_IMPA7 is not set -CONFIG_MTD_M25P80=y -CONFIG_MTD_SPI_NOR=y -CONFIG_MULTI_IRQ_HANDLER=y -CONFIG_MUTEX_SPIN_ON_OWNER=y -CONFIG_NEED_DMA_MAP_STATE=y -CONFIG_NEON=y -CONFIG_NET_FLOW_LIMIT=y -CONFIG_NET_PTP_CLASSIFY=y -CONFIG_NET_VENDOR_ALLWINNER=y -CONFIG_NLS=y -CONFIG_NLS_CODEPAGE_437=y -CONFIG_NLS_ISO8859_1=y -CONFIG_NO_BOOTMEM=y -CONFIG_NO_HZ=y -CONFIG_NO_HZ_COMMON=y -CONFIG_NO_HZ_IDLE=y -CONFIG_NR_CPUS=8 -CONFIG_NVMEM=y -CONFIG_NVMEM_SUNXI_SID=y -CONFIG_OF=y -CONFIG_OF_ADDRESS=y -CONFIG_OF_EARLY_FLATTREE=y -CONFIG_OF_FLATTREE=y -CONFIG_OF_GPIO=y -CONFIG_OF_IRQ=y -CONFIG_OF_MDIO=y -CONFIG_OF_NET=y -CONFIG_OF_RESERVED_MEM=y -CONFIG_OLD_SIGACTION=y -CONFIG_OLD_SIGSUSPEND3=y -CONFIG_OUTER_CACHE=y -CONFIG_OUTER_CACHE_SYNC=y -CONFIG_PADATA=y -CONFIG_PAGE_OFFSET=0xC0000000 -# CONFIG_PARTITION_ADVANCED is not set -# CONFIG_PCI_DOMAINS_GENERIC is not set -# CONFIG_PCI_SYSCALL is not set -CONFIG_PERF_EVENTS=y -CONFIG_PERF_USE_VMALLOC=y -CONFIG_PGTABLE_LEVELS=3 -CONFIG_PHYLIB=y -CONFIG_PHYS_ADDR_T_64BIT=y -CONFIG_PHY_SUN4I_USB=y -CONFIG_PHY_SUN9I_USB=y -CONFIG_PINCTRL=y -# CONFIG_PINCTRL_SINGLE is not set -CONFIG_PINCTRL_SUN4I_A10=y -# CONFIG_PINCTRL_SUN50I_A64 is not set -# CONFIG_PINCTRL_SUN50I_A64_R is not set -# CONFIG_PINCTRL_SUN50I_H5 is not set -CONFIG_PINCTRL_SUN5I=y -CONFIG_PINCTRL_SUN6I_A31=y -CONFIG_PINCTRL_SUN6I_A31_R=y -CONFIG_PINCTRL_SUN8I_A23=y -CONFIG_PINCTRL_SUN8I_A23_R=y -CONFIG_PINCTRL_SUN8I_A33=y -CONFIG_PINCTRL_SUN8I_A83T=y -CONFIG_PINCTRL_SUN8I_A83T_R=y -CONFIG_PINCTRL_SUN8I_H3=y -CONFIG_PINCTRL_SUN8I_H3_R=y -CONFIG_PINCTRL_SUN8I_V3S=y -CONFIG_PINCTRL_SUN9I_A80=y -CONFIG_PINCTRL_SUN9I_A80_R=y -CONFIG_PINCTRL_SUNXI=y -# CONFIG_PL310_ERRATA_588369 is not set -# CONFIG_PL310_ERRATA_727915 is not set -# CONFIG_PL310_ERRATA_753970 is not set -# CONFIG_PL310_ERRATA_769419 is not set -CONFIG_PM=y -CONFIG_PM_CLK=y -# CONFIG_PM_DEBUG is not set -CONFIG_PM_OPP=y -CONFIG_PM_SLEEP=y -CONFIG_PM_SLEEP_SMP=y -CONFIG_POWER_RESET=y -CONFIG_POWER_SUPPLY=y -CONFIG_PPS=y -CONFIG_PREEMPT=y -CONFIG_PREEMPT_COUNT=y -# CONFIG_PREEMPT_NONE is not set -CONFIG_PREEMPT_NOTIFIERS=y -CONFIG_PREEMPT_RCU=y -CONFIG_PRINTK_TIME=y -CONFIG_PROC_EVENTS=y -CONFIG_PROC_PAGE_MONITOR=y -CONFIG_PTP_1588_CLOCK=y -CONFIG_PWM=y -CONFIG_PWM_SUN4I=y -CONFIG_PWM_SYSFS=y -CONFIG_RATIONAL=y -# CONFIG_RCU_BOOST is not set -CONFIG_RCU_NEED_SEGCBLIST=y -CONFIG_RCU_STALL_COMMON=y -CONFIG_REGMAP=y -CONFIG_REGMAP_I2C=y -CONFIG_REGMAP_IRQ=y -CONFIG_REGMAP_MMIO=y -CONFIG_REGMAP_SPI=y -CONFIG_REGULATOR=y -CONFIG_REGULATOR_AXP20X=y -CONFIG_REGULATOR_FIXED_VOLTAGE=y -CONFIG_REGULATOR_GPIO=y -CONFIG_RELAY=y -CONFIG_RESET_CONTROLLER=y -CONFIG_RESET_SUNXI=y -CONFIG_RFS_ACCEL=y -CONFIG_RPS=y -CONFIG_RWSEM_SPIN_ON_OWNER=y -CONFIG_RWSEM_XCHGADD_ALGORITHM=y -CONFIG_SATA_PMP=y -# CONFIG_SCHED_INFO is not set -CONFIG_SCSI=y -CONFIG_SDIO_UART=y -CONFIG_SECURITYFS=y -CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y -CONFIG_SERIAL_8250_DW=y -CONFIG_SERIAL_8250_FSL=y -CONFIG_SERIAL_8250_NR_UARTS=8 -CONFIG_SERIAL_8250_RUNTIME_UARTS=8 -CONFIG_SERIAL_OF_PLATFORM=y -CONFIG_SERIO=y -CONFIG_SERIO_SERPORT=y -CONFIG_SG_POOL=y -CONFIG_SMP=y -CONFIG_SMP_ON_UP=y -CONFIG_SND=y -CONFIG_SND_COMPRESS_OFFLOAD=y -CONFIG_SND_JACK=y -CONFIG_SND_JACK_INPUT_DEV=y -CONFIG_SND_PCM=y -CONFIG_SND_SOC=y -CONFIG_SND_SOC_I2C_AND_SPI=y -# CONFIG_SND_SUN4I_I2S is not set -# CONFIG_SND_SUN4I_SPDIF is not set -# CONFIG_SND_SUN8I_CODEC is not set -# CONFIG_SND_SUN8I_CODEC_ANALOG is not set -CONFIG_SOUND=y -CONFIG_SOUND_OSS_CORE=y -# CONFIG_SOUND_OSS_CORE_PRECLAIM is not set -CONFIG_SPARSE_IRQ=y -CONFIG_SPI=y -CONFIG_SPI_MASTER=y -CONFIG_SPI_SUN4I=y -CONFIG_SPI_SUN6I=y -CONFIG_SRCU=y -CONFIG_STMMAC_ETH=y -CONFIG_STMMAC_PLATFORM=y -CONFIG_SUN4I_A10_CCU=y -# CONFIG_SUN4I_EMAC is not set -CONFIG_SUN4I_TIMER=y -CONFIG_SUN5I_CCU=y -CONFIG_SUN5I_HSTIMER=y -CONFIG_SUN6I_A31_CCU=y -CONFIG_SUN8I_A23_CCU=y -CONFIG_SUN8I_A33_CCU=y -CONFIG_SUN8I_A83T_CCU=y -CONFIG_SUN8I_DE2_CCU=y -CONFIG_SUN8I_H3_CCU=y -CONFIG_SUN8I_R40_CCU=y -CONFIG_SUN8I_R_CCU=y -CONFIG_SUN8I_V3S_CCU=y -CONFIG_SUN9I_A80_CCU=y -CONFIG_SUNXI_CCU=y -CONFIG_SUNXI_RSB=y -CONFIG_SUNXI_SRAM=y -CONFIG_SUNXI_WATCHDOG=y -CONFIG_SUSPEND=y -CONFIG_SUSPEND_FREEZER=y -CONFIG_SWCONFIG=y -CONFIG_SWCONFIG_B53=y -# CONFIG_SWCONFIG_B53_MMAP_DRIVER is not set -CONFIG_SWCONFIG_B53_PHY_DRIVER=y -CONFIG_SWCONFIG_B53_PHY_FIXUP=y -# CONFIG_SWCONFIG_B53_SRAB_DRIVER is not set -CONFIG_SWIOTLB=y -CONFIG_SWPHY=y -CONFIG_SWP_EMULATE=y -CONFIG_SYSFS_SYSCALL=y -CONFIG_SYS_SUPPORTS_APM_EMULATION=y -CONFIG_SYS_SUPPORTS_HUGETLBFS=y -CONFIG_TASKS_RCU=y -CONFIG_THERMAL=y -CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y -CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0 -CONFIG_THERMAL_GOV_STEP_WISE=y -CONFIG_THERMAL_HWMON=y -CONFIG_THERMAL_OF=y -# CONFIG_THUMB2_KERNEL is not set -CONFIG_TICK_CPU_ACCOUNTING=y -CONFIG_TIMER_OF=y -CONFIG_TIMER_PROBE=y -CONFIG_TMPFS_POSIX_ACL=y -CONFIG_TOUCHSCREEN_PROPERTIES=y -CONFIG_TOUCHSCREEN_SUN4I=y -CONFIG_TREE_SRCU=y -CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" -CONFIG_UNINLINE_SPIN_UNLOCK=y -CONFIG_USB=y -CONFIG_USB_ANNOUNCE_NEW_DEVICES=y -CONFIG_USB_COMMON=y -CONFIG_USB_DWC2=y -CONFIG_USB_DWC2_HOST=y -# CONFIG_USB_DWC2_TRACK_MISSED_SOFS is not set -CONFIG_USB_EHCI_HCD=y -CONFIG_USB_EHCI_HCD_PLATFORM=y -CONFIG_USB_GADGET=y -CONFIG_USB_NET_DRIVERS=y -CONFIG_USB_OHCI_HCD=y -CONFIG_USB_OHCI_HCD_PLATFORM=y -CONFIG_USB_STORAGE=y -CONFIG_USB_SUPPORT=y -CONFIG_USERIO=y -CONFIG_USE_OF=y -CONFIG_VDSO=y -CONFIG_VECTORS_BASE=0xffff0000 -CONFIG_VFAT_FS=y -CONFIG_VFP=y -CONFIG_VFPv3=y -CONFIG_VHOST=y -CONFIG_VHOST_NET=y -CONFIG_VIRTUALIZATION=y -CONFIG_VM_EVENT_COUNTERS=y -CONFIG_VT=y -CONFIG_VT_CONSOLE=y -CONFIG_VT_CONSOLE_SLEEP=y -CONFIG_VT_HW_CONSOLE_BINDING=y -CONFIG_WATCHDOG_CORE=y -# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set -CONFIG_XPS=y -CONFIG_XZ_DEC_ARM=y -CONFIG_XZ_DEC_BCJ=y -CONFIG_ZBOOT_ROM_BSS=0 -CONFIG_ZBOOT_ROM_TEXT=0 diff --git a/target/linux/sunxi/cortexa53/config-4.14 b/target/linux/sunxi/cortexa53/config-4.14 deleted file mode 100644 index 1ba379ea6509..000000000000 --- a/target/linux/sunxi/cortexa53/config-4.14 +++ /dev/null @@ -1,102 +0,0 @@ -CONFIG_64BIT=y -CONFIG_ARCH_DMA_ADDR_T_64BIT=y -CONFIG_ARCH_HAS_CACHE_LINE_SIZE=y -CONFIG_ARCH_HAS_FORTIFY_SOURCE=y -CONFIG_ARCH_HAS_HOLES_MEMORYMODEL=y -CONFIG_ARCH_HAS_KCOV=y -CONFIG_ARCH_MMAP_RND_BITS=18 -CONFIG_ARCH_MMAP_RND_BITS_MAX=24 -CONFIG_ARCH_MMAP_RND_BITS_MIN=18 -CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11 -# CONFIG_ARCH_OPTIONAL_KERNEL_RWX is not set -# CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT is not set -CONFIG_ARCH_PROC_KCORE_TEXT=y -CONFIG_ARCH_SELECT_MEMORY_MODEL=y -CONFIG_ARCH_SPARSEMEM_DEFAULT=y -CONFIG_ARCH_SPARSEMEM_ENABLE=y -CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y -CONFIG_ARCH_SUPPORTS_MEMORY_FAILURE=y -CONFIG_ARCH_SUPPORTS_NUMA_BALANCING=y -CONFIG_ARCH_WANT_COMPAT_IPC_PARSE_VERSION=y -CONFIG_ARCH_WANT_FRAME_POINTERS=y -CONFIG_ARCH_WANT_HUGE_PMD_SHARE=y -CONFIG_ARM64=y -# CONFIG_ARM64_16K_PAGES is not set -CONFIG_ARM64_4K_PAGES=y -# CONFIG_ARM64_64K_PAGES is not set -CONFIG_ARM64_CONT_SHIFT=4 -# CONFIG_ARM64_CRYPTO is not set -# CONFIG_ARM64_HW_AFDBM is not set -# CONFIG_ARM64_LSE_ATOMICS is not set -CONFIG_ARM64_PAGE_SHIFT=12 -# CONFIG_ARM64_PAN is not set -# CONFIG_ARM64_PMEM is not set -# CONFIG_ARM64_PTDUMP_CORE is not set -# CONFIG_ARM64_PTDUMP_DEBUGFS is not set -# CONFIG_ARM64_RANDOMIZE_TEXT_OFFSET is not set -CONFIG_ARM64_SSBD=y -# CONFIG_ARM64_UAO is not set -CONFIG_ARM64_VA_BITS=39 -CONFIG_ARM64_VA_BITS_39=y -# CONFIG_ARM64_VA_BITS_48 is not set -# CONFIG_ARM64_VHE is not set -CONFIG_ARM_AMBA=y -CONFIG_ARM_GIC_V3=y -# CONFIG_ARM_SP805_WATCHDOG is not set -CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y -CONFIG_DWMAC_SUN8I=y -CONFIG_FRAME_POINTER=y -CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y -CONFIG_GENERIC_CSUM=y -CONFIG_GENERIC_IRQ_MIGRATION=y -CONFIG_HAVE_ALIGNED_STRUCT_PAGE=y -CONFIG_HAVE_ARCH_HUGE_VMAP=y -CONFIG_HAVE_ARCH_KASAN=y -CONFIG_HAVE_ARCH_VMAP_STACK=y -CONFIG_HAVE_CMPXCHG_DOUBLE=y -CONFIG_HAVE_CMPXCHG_LOCAL=y -CONFIG_HAVE_DEBUG_BUGVERBOSE=y -CONFIG_HAVE_MEMORY_PRESENT=y -CONFIG_HAVE_PATA_PLATFORM=y -CONFIG_HOLES_IN_ZONE=y -CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000 -CONFIG_KERNEL_MODE_NEON=y -CONFIG_KVM_ARM_PMU=y -CONFIG_MDIO_BUS_MUX=y -CONFIG_MODULES_USE_ELF_RELA=y -CONFIG_NEED_SG_DMA_LENGTH=y -CONFIG_NO_IOPORT_MAP=y -# CONFIG_NUMA is not set -CONFIG_PARTITION_PERCPU=y -# CONFIG_PCI_DOMAINS is not set -# CONFIG_PINCTRL_SUN4I_A10 is not set -CONFIG_PINCTRL_SUN50I_A64=y -CONFIG_PINCTRL_SUN50I_A64_R=y -CONFIG_PINCTRL_SUN50I_H5=y -# CONFIG_PINCTRL_SUN5I is not set -# CONFIG_PINCTRL_SUN6I_A31 is not set -# CONFIG_PINCTRL_SUN6I_A31_R is not set -# CONFIG_PINCTRL_SUN8I_A23 is not set -# CONFIG_PINCTRL_SUN8I_A23_R is not set -# CONFIG_PINCTRL_SUN8I_A33 is not set -# CONFIG_PINCTRL_SUN8I_A83T is not set -# CONFIG_PINCTRL_SUN8I_A83T_R is not set -# CONFIG_PINCTRL_SUN8I_H3 is not set -# CONFIG_PINCTRL_SUN8I_V3S is not set -# CONFIG_PINCTRL_SUN9I_A80 is not set -# CONFIG_PINCTRL_SUN9I_A80_R is not set -# CONFIG_RANDOMIZE_BASE is not set -CONFIG_REALTEK_PHY=y -# CONFIG_SERIAL_AMBA_PL011 is not set -CONFIG_SOUND_OSS_CORE_PRECLAIM=y -CONFIG_SPARSEMEM=y -CONFIG_SPARSEMEM_EXTREME=y -CONFIG_SPARSEMEM_MANUAL=y -CONFIG_SPARSEMEM_VMEMMAP=y -CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y -CONFIG_SUN50I_A64_CCU=y -CONFIG_SUN50I_ERRATUM_UNKNOWN1=y -CONFIG_SYSCTL_EXCEPTION_TRACE=y -CONFIG_THREAD_INFO_IN_TASK=y -CONFIG_UNMAP_KERNEL_AT_EL0=y -CONFIG_VMAP_STACK=y diff --git a/target/linux/sunxi/cortexa7/config-4.14 b/target/linux/sunxi/cortexa7/config-4.14 deleted file mode 100644 index f0b6a7a86111..000000000000 --- a/target/linux/sunxi/cortexa7/config-4.14 +++ /dev/null @@ -1,10 +0,0 @@ -CONFIG_DWMAC_SUN8I=y -CONFIG_HARDEN_BRANCH_PREDICTOR=y -# CONFIG_MACH_SUN4I is not set -# CONFIG_MACH_SUN5I is not set -# CONFIG_PINCTRL_GR8 is not set -CONFIG_PINCTRL_SUN4I_A10=y -# CONFIG_PINCTRL_SUN5I_A10S is not set -# CONFIG_PINCTRL_SUN5I_A13 is not set -CONFIG_MDIO_BUS_MUX=y -# CONFIG_PINCTRL_SUN5I is not set diff --git a/target/linux/sunxi/cortexa8/config-4.14 b/target/linux/sunxi/cortexa8/config-4.14 deleted file mode 100644 index 6cbb4417f656..000000000000 --- a/target/linux/sunxi/cortexa8/config-4.14 +++ /dev/null @@ -1,21 +0,0 @@ -# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set -# CONFIG_ARM_ERRATA_643719 is not set -# CONFIG_ARM_LPAE is not set -# CONFIG_MACH_SUN6I is not set -# CONFIG_MACH_SUN7I is not set -# CONFIG_MACH_SUN8I is not set -# CONFIG_MACH_SUN9I is not set -CONFIG_PGTABLE_LEVELS=2 -# CONFIG_PHYS_ADDR_T_64BIT is not set -# CONFIG_PINCTRL_SUN6I_A31 is not set -# CONFIG_PINCTRL_SUN6I_A31_R is not set -# CONFIG_PINCTRL_SUN8I_A23 is not set -# CONFIG_PINCTRL_SUN8I_A23_R is not set -# CONFIG_PINCTRL_SUN8I_A33 is not set -# CONFIG_PINCTRL_SUN8I_A83T is not set -# CONFIG_PINCTRL_SUN8I_A83T_R is not set -# CONFIG_PINCTRL_SUN8I_H3 is not set -# CONFIG_PINCTRL_SUN8I_H3_R is not set -# CONFIG_PINCTRL_SUN8I_V3S is not set -# CONFIG_PINCTRL_SUN9I_A80 is not set -# CONFIG_PINCTRL_SUN9I_A80_R is not set diff --git a/target/linux/sunxi/patches-4.14/001-net-stmmac-snps-dwmac-mdio-MDIOs-are-automatically-r.patch b/target/linux/sunxi/patches-4.14/001-net-stmmac-snps-dwmac-mdio-MDIOs-are-automatically-r.patch deleted file mode 100644 index 838b234717e0..000000000000 --- a/target/linux/sunxi/patches-4.14/001-net-stmmac-snps-dwmac-mdio-MDIOs-are-automatically-r.patch +++ /dev/null @@ -1,33 +0,0 @@ -From b5beecb580376cd8d959eb990abece6a748a3ce3 Mon Sep 17 00:00:00 2001 -From: Corentin Labbe -Date: Tue, 24 Oct 2017 19:57:12 +0200 -Subject: [PATCH] net: stmmac: snps, dwmac-mdio MDIOs are automatically - registered - -stmmac bindings docs said that its mdio node must have -compatible = "snps,dwmac-mdio"; -Since dwmac-sun8i does not have any good reasons to not doing it, all -their MDIO node must have it. - -Since these compatible is automatically registered, dwmac-sun8i compatible -does not need to be in need_mdio_ids. - -Signed-off-by: Corentin Labbe -Signed-off-by: David S. Miller ---- - drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c | 4 ---- - 1 file changed, 4 deletions(-) - ---- a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c -+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c -@@ -317,10 +317,6 @@ static int stmmac_dt_phy(struct plat_stm - bool mdio = true; - static const struct of_device_id need_mdio_ids[] = { - { .compatible = "snps,dwc-qos-ethernet-4.10" }, -- { .compatible = "allwinner,sun8i-a83t-emac" }, -- { .compatible = "allwinner,sun8i-h3-emac" }, -- { .compatible = "allwinner,sun8i-v3s-emac" }, -- { .compatible = "allwinner,sun50i-a64-emac" }, - {}, - }; - diff --git a/target/linux/sunxi/patches-4.14/002-net-stmmac-dwmac-sun8i-Handle-integrated-external-MD.patch b/target/linux/sunxi/patches-4.14/002-net-stmmac-dwmac-sun8i-Handle-integrated-external-MD.patch deleted file mode 100644 index 9f7f89c7e201..000000000000 --- a/target/linux/sunxi/patches-4.14/002-net-stmmac-dwmac-sun8i-Handle-integrated-external-MD.patch +++ /dev/null @@ -1,506 +0,0 @@ -From 634db83b82658f4641d8026e340c6027cf74a6bb Mon Sep 17 00:00:00 2001 -From: Corentin Labbe -Date: Tue, 24 Oct 2017 19:57:13 +0200 -Subject: [PATCH] net: stmmac: dwmac-sun8i: Handle integrated/external MDIOs - -The Allwinner H3 SoC have two distinct MDIO bus, only one could be -active at the same time. -The selection of the active MDIO bus are done via some bits in the EMAC -register of the system controller. - -This patch implement this MDIO switch via a custom MDIO-mux. - -Signed-off-by: Corentin Labbe -Reviewed-by: Andrew Lunn -Signed-off-by: David S. Miller ---- - drivers/net/ethernet/stmicro/stmmac/Kconfig | 1 + - drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 353 ++++++++++++++-------- - 2 files changed, 224 insertions(+), 130 deletions(-) - ---- a/drivers/net/ethernet/stmicro/stmmac/Kconfig -+++ b/drivers/net/ethernet/stmicro/stmmac/Kconfig -@@ -159,6 +159,7 @@ config DWMAC_SUN8I - tristate "Allwinner sun8i GMAC support" - default ARCH_SUNXI - depends on OF && (ARCH_SUNXI || COMPILE_TEST) -+ select MDIO_BUS_MUX - ---help--- - Support for Allwinner H3 A83T A64 EMAC ethernet controllers. - ---- a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c -+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c -@@ -17,6 +17,7 @@ - #include - #include - #include -+#include - #include - #include - #include -@@ -41,14 +42,14 @@ - * This value is used for disabling properly EMAC - * and used as a good starting value in case of the - * boot process(uboot) leave some stuff. -- * @internal_phy: Does the MAC embed an internal PHY -+ * @soc_has_internal_phy: Does the MAC embed an internal PHY - * @support_mii: Does the MAC handle MII - * @support_rmii: Does the MAC handle RMII - * @support_rgmii: Does the MAC handle RGMII - */ - struct emac_variant { - u32 default_syscon_value; -- int internal_phy; -+ bool soc_has_internal_phy; - bool support_mii; - bool support_rmii; - bool support_rgmii; -@@ -61,7 +62,8 @@ struct emac_variant { - * @rst_ephy: reference to the optional EPHY reset for the internal PHY - * @variant: reference to the current board variant - * @regmap: regmap for using the syscon -- * @use_internal_phy: Does the current PHY choice imply using the internal PHY -+ * @internal_phy_powered: Does the internal PHY is enabled -+ * @mux_handle: Internal pointer used by mdio-mux lib - */ - struct sunxi_priv_data { - struct clk *tx_clk; -@@ -70,12 +72,13 @@ struct sunxi_priv_data { - struct reset_control *rst_ephy; - const struct emac_variant *variant; - struct regmap *regmap; -- bool use_internal_phy; -+ bool internal_phy_powered; -+ void *mux_handle; - }; - - static const struct emac_variant emac_variant_h3 = { - .default_syscon_value = 0x58000, -- .internal_phy = PHY_INTERFACE_MODE_MII, -+ .soc_has_internal_phy = true, - .support_mii = true, - .support_rmii = true, - .support_rgmii = true -@@ -83,20 +86,20 @@ static const struct emac_variant emac_va - - static const struct emac_variant emac_variant_v3s = { - .default_syscon_value = 0x38000, -- .internal_phy = PHY_INTERFACE_MODE_MII, -+ .soc_has_internal_phy = true, - .support_mii = true - }; - - static const struct emac_variant emac_variant_a83t = { - .default_syscon_value = 0, -- .internal_phy = 0, -+ .soc_has_internal_phy = false, - .support_mii = true, - .support_rgmii = true - }; - - static const struct emac_variant emac_variant_a64 = { - .default_syscon_value = 0, -- .internal_phy = 0, -+ .soc_has_internal_phy = false, - .support_mii = true, - .support_rmii = true, - .support_rgmii = true -@@ -195,6 +198,9 @@ static const struct emac_variant emac_va - #define H3_EPHY_LED_POL BIT(17) /* 1: active low, 0: active high */ - #define H3_EPHY_SHUTDOWN BIT(16) /* 1: shutdown, 0: power up */ - #define H3_EPHY_SELECT BIT(15) /* 1: internal PHY, 0: external PHY */ -+#define H3_EPHY_MUX_MASK (H3_EPHY_SHUTDOWN | H3_EPHY_SELECT) -+#define DWMAC_SUN8I_MDIO_MUX_INTERNAL_ID 1 -+#define DWMAC_SUN8I_MDIO_MUX_EXTERNAL_ID 2 - - /* H3/A64 specific bits */ - #define SYSCON_RMII_EN BIT(13) /* 1: enable RMII (overrides EPIT) */ -@@ -635,6 +641,159 @@ static int sun8i_dwmac_reset(struct stmm - return 0; - } - -+/* Search in mdio-mux node for internal PHY node and get its clk/reset */ -+static int get_ephy_nodes(struct stmmac_priv *priv) -+{ -+ struct sunxi_priv_data *gmac = priv->plat->bsp_priv; -+ struct device_node *mdio_mux, *iphynode; -+ struct device_node *mdio_internal; -+ int ret; -+ -+ mdio_mux = of_get_child_by_name(priv->device->of_node, "mdio-mux"); -+ if (!mdio_mux) { -+ dev_err(priv->device, "Cannot get mdio-mux node\n"); -+ return -ENODEV; -+ } -+ -+ mdio_internal = of_find_compatible_node(mdio_mux, NULL, -+ "allwinner,sun8i-h3-mdio-internal"); -+ if (!mdio_internal) { -+ dev_err(priv->device, "Cannot get internal_mdio node\n"); -+ return -ENODEV; -+ } -+ -+ /* Seek for internal PHY */ -+ for_each_child_of_node(mdio_internal, iphynode) { -+ gmac->ephy_clk = of_clk_get(iphynode, 0); -+ if (IS_ERR(gmac->ephy_clk)) -+ continue; -+ gmac->rst_ephy = of_reset_control_get_exclusive(iphynode, NULL); -+ if (IS_ERR(gmac->rst_ephy)) { -+ ret = PTR_ERR(gmac->rst_ephy); -+ if (ret == -EPROBE_DEFER) -+ return ret; -+ continue; -+ } -+ dev_info(priv->device, "Found internal PHY node\n"); -+ return 0; -+ } -+ return -ENODEV; -+} -+ -+static int sun8i_dwmac_power_internal_phy(struct stmmac_priv *priv) -+{ -+ struct sunxi_priv_data *gmac = priv->plat->bsp_priv; -+ int ret; -+ -+ if (gmac->internal_phy_powered) { -+ dev_warn(priv->device, "Internal PHY already powered\n"); -+ return 0; -+ } -+ -+ dev_info(priv->device, "Powering internal PHY\n"); -+ ret = clk_prepare_enable(gmac->ephy_clk); -+ if (ret) { -+ dev_err(priv->device, "Cannot enable internal PHY\n"); -+ return ret; -+ } -+ -+ /* Make sure the EPHY is properly reseted, as U-Boot may leave -+ * it at deasserted state, and thus it may fail to reset EMAC. -+ */ -+ reset_control_assert(gmac->rst_ephy); -+ -+ ret = reset_control_deassert(gmac->rst_ephy); -+ if (ret) { -+ dev_err(priv->device, "Cannot deassert internal phy\n"); -+ clk_disable_unprepare(gmac->ephy_clk); -+ return ret; -+ } -+ -+ gmac->internal_phy_powered = true; -+ -+ return 0; -+} -+ -+static int sun8i_dwmac_unpower_internal_phy(struct sunxi_priv_data *gmac) -+{ -+ if (!gmac->internal_phy_powered) -+ return 0; -+ -+ clk_disable_unprepare(gmac->ephy_clk); -+ reset_control_assert(gmac->rst_ephy); -+ gmac->internal_phy_powered = false; -+ return 0; -+} -+ -+/* MDIO multiplexing switch function -+ * This function is called by the mdio-mux layer when it thinks the mdio bus -+ * multiplexer needs to switch. -+ * 'current_child' is the current value of the mux register -+ * 'desired_child' is the value of the 'reg' property of the target child MDIO -+ * node. -+ * The first time this function is called, current_child == -1. -+ * If current_child == desired_child, then the mux is already set to the -+ * correct bus. -+ */ -+static int mdio_mux_syscon_switch_fn(int current_child, int desired_child, -+ void *data) -+{ -+ struct stmmac_priv *priv = data; -+ struct sunxi_priv_data *gmac = priv->plat->bsp_priv; -+ u32 reg, val; -+ int ret = 0; -+ bool need_power_ephy = false; -+ -+ if (current_child ^ desired_child) { -+ regmap_read(gmac->regmap, SYSCON_EMAC_REG, ®); -+ switch (desired_child) { -+ case DWMAC_SUN8I_MDIO_MUX_INTERNAL_ID: -+ dev_info(priv->device, "Switch mux to internal PHY"); -+ val = (reg & ~H3_EPHY_MUX_MASK) | H3_EPHY_SELECT; -+ -+ need_power_ephy = true; -+ break; -+ case DWMAC_SUN8I_MDIO_MUX_EXTERNAL_ID: -+ dev_info(priv->device, "Switch mux to external PHY"); -+ val = (reg & ~H3_EPHY_MUX_MASK) | H3_EPHY_SHUTDOWN; -+ need_power_ephy = false; -+ break; -+ default: -+ dev_err(priv->device, "Invalid child ID %x\n", -+ desired_child); -+ return -EINVAL; -+ } -+ regmap_write(gmac->regmap, SYSCON_EMAC_REG, val); -+ if (need_power_ephy) { -+ ret = sun8i_dwmac_power_internal_phy(priv); -+ if (ret) -+ return ret; -+ } else { -+ sun8i_dwmac_unpower_internal_phy(gmac); -+ } -+ /* After changing syscon value, the MAC need reset or it will -+ * use the last value (and so the last PHY set). -+ */ -+ ret = sun8i_dwmac_reset(priv); -+ } -+ return ret; -+} -+ -+static int sun8i_dwmac_register_mdio_mux(struct stmmac_priv *priv) -+{ -+ int ret; -+ struct device_node *mdio_mux; -+ struct sunxi_priv_data *gmac = priv->plat->bsp_priv; -+ -+ mdio_mux = of_get_child_by_name(priv->device->of_node, "mdio-mux"); -+ if (!mdio_mux) -+ return -ENODEV; -+ -+ ret = mdio_mux_init(priv->device, mdio_mux, mdio_mux_syscon_switch_fn, -+ &gmac->mux_handle, priv, priv->mii); -+ return ret; -+} -+ - static int sun8i_dwmac_set_syscon(struct stmmac_priv *priv) - { - struct sunxi_priv_data *gmac = priv->plat->bsp_priv; -@@ -649,35 +808,25 @@ static int sun8i_dwmac_set_syscon(struct - "Current syscon value is not the default %x (expect %x)\n", - val, reg); - -- if (gmac->variant->internal_phy) { -- if (!gmac->use_internal_phy) { -- /* switch to external PHY interface */ -- reg &= ~H3_EPHY_SELECT; -- } else { -- reg |= H3_EPHY_SELECT; -- reg &= ~H3_EPHY_SHUTDOWN; -- dev_dbg(priv->device, "Select internal_phy %x\n", reg); -- -- if (of_property_read_bool(priv->plat->phy_node, -- "allwinner,leds-active-low")) -- reg |= H3_EPHY_LED_POL; -- else -- reg &= ~H3_EPHY_LED_POL; -- -- /* Force EPHY xtal frequency to 24MHz. */ -- reg |= H3_EPHY_CLK_SEL; -- -- ret = of_mdio_parse_addr(priv->device, -- priv->plat->phy_node); -- if (ret < 0) { -- dev_err(priv->device, "Could not parse MDIO addr\n"); -- return ret; -- } -- /* of_mdio_parse_addr returns a valid (0 ~ 31) PHY -- * address. No need to mask it again. -- */ -- reg |= ret << H3_EPHY_ADDR_SHIFT; -+ if (gmac->variant->soc_has_internal_phy) { -+ if (of_property_read_bool(priv->plat->phy_node, -+ "allwinner,leds-active-low")) -+ reg |= H3_EPHY_LED_POL; -+ else -+ reg &= ~H3_EPHY_LED_POL; -+ -+ /* Force EPHY xtal frequency to 24MHz. */ -+ reg |= H3_EPHY_CLK_SEL; -+ -+ ret = of_mdio_parse_addr(priv->device, priv->plat->phy_node); -+ if (ret < 0) { -+ dev_err(priv->device, "Could not parse MDIO addr\n"); -+ return ret; - } -+ /* of_mdio_parse_addr returns a valid (0 ~ 31) PHY -+ * address. No need to mask it again. -+ */ -+ reg |= 1 << H3_EPHY_ADDR_SHIFT; - } - - if (!of_property_read_u32(node, "allwinner,tx-delay-ps", &val)) { -@@ -750,81 +899,21 @@ static void sun8i_dwmac_unset_syscon(str - regmap_write(gmac->regmap, SYSCON_EMAC_REG, reg); - } - --static int sun8i_dwmac_power_internal_phy(struct stmmac_priv *priv) -+static void sun8i_dwmac_exit(struct platform_device *pdev, void *priv) - { -- struct sunxi_priv_data *gmac = priv->plat->bsp_priv; -- int ret; -- -- if (!gmac->use_internal_phy) -- return 0; -+ struct sunxi_priv_data *gmac = priv; - -- ret = clk_prepare_enable(gmac->ephy_clk); -- if (ret) { -- dev_err(priv->device, "Cannot enable ephy\n"); -- return ret; -+ if (gmac->variant->soc_has_internal_phy) { -+ /* sun8i_dwmac_exit could be called with mdiomux uninit */ -+ if (gmac->mux_handle) -+ mdio_mux_uninit(gmac->mux_handle); -+ if (gmac->internal_phy_powered) -+ sun8i_dwmac_unpower_internal_phy(gmac); - } - -- /* Make sure the EPHY is properly reseted, as U-Boot may leave -- * it at deasserted state, and thus it may fail to reset EMAC. -- */ -- reset_control_assert(gmac->rst_ephy); -- -- ret = reset_control_deassert(gmac->rst_ephy); -- if (ret) { -- dev_err(priv->device, "Cannot deassert ephy\n"); -- clk_disable_unprepare(gmac->ephy_clk); -- return ret; -- } -- -- return 0; --} -- --static int sun8i_dwmac_unpower_internal_phy(struct sunxi_priv_data *gmac) --{ -- if (!gmac->use_internal_phy) -- return 0; -- -- clk_disable_unprepare(gmac->ephy_clk); -- reset_control_assert(gmac->rst_ephy); -- return 0; --} -- --/* sun8i_power_phy() - Activate the PHY: -- * In case of error, no need to call sun8i_unpower_phy(), -- * it will be called anyway by sun8i_dwmac_exit() -- */ --static int sun8i_power_phy(struct stmmac_priv *priv) --{ -- int ret; -- -- ret = sun8i_dwmac_power_internal_phy(priv); -- if (ret) -- return ret; -- -- ret = sun8i_dwmac_set_syscon(priv); -- if (ret) -- return ret; -- -- /* After changing syscon value, the MAC need reset or it will use -- * the last value (and so the last PHY set. -- */ -- ret = sun8i_dwmac_reset(priv); -- if (ret) -- return ret; -- return 0; --} -- --static void sun8i_unpower_phy(struct sunxi_priv_data *gmac) --{ - sun8i_dwmac_unset_syscon(gmac); -- sun8i_dwmac_unpower_internal_phy(gmac); --} -- --static void sun8i_dwmac_exit(struct platform_device *pdev, void *priv) --{ -- struct sunxi_priv_data *gmac = priv; - -- sun8i_unpower_phy(gmac); -+ reset_control_put(gmac->rst_ephy); - - clk_disable_unprepare(gmac->tx_clk); - -@@ -853,7 +942,7 @@ static struct mac_device_info *sun8i_dwm - if (!mac) - return NULL; - -- ret = sun8i_power_phy(priv); -+ ret = sun8i_dwmac_set_syscon(priv); - if (ret) - return NULL; - -@@ -895,6 +984,8 @@ static int sun8i_dwmac_probe(struct plat - struct sunxi_priv_data *gmac; - struct device *dev = &pdev->dev; - int ret; -+ struct stmmac_priv *priv; -+ struct net_device *ndev; - - ret = stmmac_get_platform_resources(pdev, &stmmac_res); - if (ret) -@@ -938,29 +1029,6 @@ static int sun8i_dwmac_probe(struct plat - } - - plat_dat->interface = of_get_phy_mode(dev->of_node); -- if (plat_dat->interface == gmac->variant->internal_phy) { -- dev_info(&pdev->dev, "Will use internal PHY\n"); -- gmac->use_internal_phy = true; -- gmac->ephy_clk = of_clk_get(plat_dat->phy_node, 0); -- if (IS_ERR(gmac->ephy_clk)) { -- ret = PTR_ERR(gmac->ephy_clk); -- dev_err(&pdev->dev, "Cannot get EPHY clock: %d\n", ret); -- return -EINVAL; -- } -- -- gmac->rst_ephy = of_reset_control_get(plat_dat->phy_node, NULL); -- if (IS_ERR(gmac->rst_ephy)) { -- ret = PTR_ERR(gmac->rst_ephy); -- if (ret == -EPROBE_DEFER) -- return ret; -- dev_err(&pdev->dev, "No EPHY reset control found %d\n", -- ret); -- return -EINVAL; -- } -- } else { -- dev_info(&pdev->dev, "Will use external PHY\n"); -- gmac->use_internal_phy = false; -- } - - /* platform data specifying hardware features and callbacks. - * hardware features were copied from Allwinner drivers. -@@ -979,9 +1047,34 @@ static int sun8i_dwmac_probe(struct plat - - ret = stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res); - if (ret) -- sun8i_dwmac_exit(pdev, plat_dat->bsp_priv); -+ goto dwmac_exit; -+ -+ ndev = dev_get_drvdata(&pdev->dev); -+ priv = netdev_priv(ndev); -+ /* The mux must be registered after parent MDIO -+ * so after stmmac_dvr_probe() -+ */ -+ if (gmac->variant->soc_has_internal_phy) { -+ ret = get_ephy_nodes(priv); -+ if (ret) -+ goto dwmac_exit; -+ ret = sun8i_dwmac_register_mdio_mux(priv); -+ if (ret) { -+ dev_err(&pdev->dev, "Failed to register mux\n"); -+ goto dwmac_mux; -+ } -+ } else { -+ ret = sun8i_dwmac_reset(priv); -+ if (ret) -+ goto dwmac_exit; -+ } - - return ret; -+dwmac_mux: -+ sun8i_dwmac_unset_syscon(gmac); -+dwmac_exit: -+ sun8i_dwmac_exit(pdev, plat_dat->bsp_priv); -+return ret; - } - - static const struct of_device_id sun8i_dwmac_match[] = { diff --git a/target/linux/sunxi/patches-4.14/003-net-stmmac-sun8i-Restore-the-compatibles.patch b/target/linux/sunxi/patches-4.14/003-net-stmmac-sun8i-Restore-the-compatibles.patch deleted file mode 100644 index 0e8d808b4224..000000000000 --- a/target/linux/sunxi/patches-4.14/003-net-stmmac-sun8i-Restore-the-compatibles.patch +++ /dev/null @@ -1,35 +0,0 @@ -From a8ff8ccb45d37efa64476958fc5e9a8d9716b23b Mon Sep 17 00:00:00 2001 -From: Corentin Labbe -Date: Tue, 24 Oct 2017 19:57:14 +0200 -Subject: [PATCH] net: stmmac: sun8i: Restore the compatibles - -The original dwmac-sun8i DT bindings have some issue on how to handle -integrated PHY and was reverted in last RC of 4.13. -But now we have a solution so we need to get back that was reverted. - -This patch restore compatibles about dwmac-sun8i -This reverts commit ad4540cc5aa3 ("net: stmmac: sun8i: Remove the compatibles") - -Signed-off-by: Corentin Labbe -Signed-off-by: David S. Miller ---- - drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 8 ++++++++ - 1 file changed, 8 insertions(+) - ---- a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c -+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c -@@ -1078,6 +1078,14 @@ return ret; - } - - static const struct of_device_id sun8i_dwmac_match[] = { -+ { .compatible = "allwinner,sun8i-h3-emac", -+ .data = &emac_variant_h3 }, -+ { .compatible = "allwinner,sun8i-v3s-emac", -+ .data = &emac_variant_v3s }, -+ { .compatible = "allwinner,sun8i-a83t-emac", -+ .data = &emac_variant_a83t }, -+ { .compatible = "allwinner,sun50i-a64-emac", -+ .data = &emac_variant_a64 }, - { } - }; - MODULE_DEVICE_TABLE(of, sun8i_dwmac_match); diff --git a/target/linux/sunxi/patches-4.14/004-net-stmmac-dwmac-sun8i-fix-allwinner-leds-active-low.patch b/target/linux/sunxi/patches-4.14/004-net-stmmac-dwmac-sun8i-fix-allwinner-leds-active-low.patch deleted file mode 100644 index 1bd5e16c1642..000000000000 --- a/target/linux/sunxi/patches-4.14/004-net-stmmac-dwmac-sun8i-fix-allwinner-leds-active-low.patch +++ /dev/null @@ -1,29 +0,0 @@ -From 1c08ac0c4bd8e9d66c4dde29bc496c3b430dd028 Mon Sep 17 00:00:00 2001 -From: Corentin Labbe -Date: Tue, 28 Nov 2017 17:48:22 +0100 -Subject: net: stmmac: dwmac-sun8i: fix allwinner,leds-active-low handling - -The driver expect "allwinner,leds-active-low" to be in PHY node, but -the binding doc expect it to be in MAC node. - -Since all board DT use it also in MAC node, the driver need to search -allwinner,leds-active-low in MAC node. - -Signed-off-by: Corentin Labbe -Signed-off-by: David S. Miller ---- - drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 3 +-- - 1 file changed, 1 insertion(+), 2 deletions(-) - ---- a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c -+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c -@@ -809,8 +809,7 @@ static int sun8i_dwmac_set_syscon(struct - val, reg); - - if (gmac->variant->soc_has_internal_phy) { -- if (of_property_read_bool(priv->plat->phy_node, -- "allwinner,leds-active-low")) -+ if (of_property_read_bool(node, "allwinner,leds-active-low")) - reg |= H3_EPHY_LED_POL; - else - reg &= ~H3_EPHY_LED_POL; diff --git a/target/linux/sunxi/patches-4.14/020-ARM-dts-sunxi-Restore-EMAC-changes-boards.patch b/target/linux/sunxi/patches-4.14/020-ARM-dts-sunxi-Restore-EMAC-changes-boards.patch deleted file mode 100644 index b89278d5d30c..000000000000 --- a/target/linux/sunxi/patches-4.14/020-ARM-dts-sunxi-Restore-EMAC-changes-boards.patch +++ /dev/null @@ -1,292 +0,0 @@ -From 4904337fe34fa7fc529d6f4d9ee8b96fe7db310a Mon Sep 17 00:00:00 2001 -From: Corentin Labbe -Date: Tue, 31 Oct 2017 09:19:12 +0100 -Subject: [PATCH] ARM: dts: sunxi: Restore EMAC changes (boards) - -The original dwmac-sun8i DT bindings have some issue on how to handle -integrated PHY and was reverted in last RC of 4.13. -But now we have a solution so we need to get back that was reverted. - -This patch restore all boards DT about dwmac-sun8i -This reverts partially commit fe45174b72ae ("arm: dts: sunxi: Revert EMAC changes") - -Signed-off-by: Corentin Labbe -Acked-by: Florian Fainelli -Signed-off-by: Maxime Ripard ---- - arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts | 9 +++++++ - arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts | 19 +++++++++++++++ - arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts | 29 +++++++++++++++++++++++ - arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts | 7 ++++++ - arch/arm/boot/dts/sun8i-h3-orangepi-2.dts | 8 +++++++ - arch/arm/boot/dts/sun8i-h3-orangepi-one.dts | 8 +++++++ - arch/arm/boot/dts/sun8i-h3-orangepi-pc-plus.dts | 5 ++++ - arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts | 8 +++++++ - arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts | 22 +++++++++++++++++ - arch/arm/boot/dts/sun8i-h3-orangepi-plus2e.dts | 16 +++++++++++++ - 10 files changed, 131 insertions(+) - ---- a/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts -+++ b/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts -@@ -56,6 +56,8 @@ - - aliases { - serial0 = &uart0; -+ /* ethernet0 is the H3 emac, defined in sun8i-h3.dtsi */ -+ ethernet0 = &emac; - ethernet1 = &xr819; - }; - -@@ -102,6 +104,13 @@ - status = "okay"; - }; - -+&emac { -+ phy-handle = <&int_mii_phy>; -+ phy-mode = "mii"; -+ allwinner,leds-active-low; -+ status = "okay"; -+}; -+ - &mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>; ---- a/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts -+++ b/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts -@@ -52,6 +52,7 @@ - compatible = "sinovoip,bpi-m2-plus", "allwinner,sun8i-h3"; - - aliases { -+ ethernet0 = &emac; - serial0 = &uart0; - serial1 = &uart1; - }; -@@ -114,6 +115,24 @@ - status = "okay"; - }; - -+&emac { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&emac_rgmii_pins>; -+ phy-supply = <®_gmac_3v3>; -+ phy-handle = <&ext_rgmii_phy>; -+ phy-mode = "rgmii"; -+ -+ allwinner,leds-active-low; -+ status = "okay"; -+}; -+ -+&external_mdio { -+ ext_rgmii_phy: ethernet-phy@1 { -+ compatible = "ethernet-phy-ieee802.3-c22"; -+ reg = <0>; -+ }; -+}; -+ - &ir { - pinctrl-names = "default"; - pinctrl-0 = <&ir_pins_a>; ---- a/arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts -+++ b/arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts -@@ -45,6 +45,16 @@ - / { - model = "FriendlyArm NanoPi M1 Plus"; - compatible = "friendlyarm,nanopi-m1-plus", "allwinner,sun8i-h3"; -+ -+ reg_gmac_3v3: gmac-3v3 { -+ compatible = "regulator-fixed"; -+ regulator-name = "gmac-3v3"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ startup-delay-us = <100000>; -+ enable-active-high; -+ gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>; -+ }; - }; - - &ehci1 { -@@ -55,6 +65,25 @@ - status = "okay"; - }; - -+&emac { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&emac_rgmii_pins>; -+ phy-supply = <®_gmac_3v3>; -+ phy-handle = <&ext_rgmii_phy>; -+ phy-mode = "rgmii"; -+ -+ allwinner,leds-active-low; -+ -+ status = "okay"; -+}; -+ -+&external_mdio { -+ ext_rgmii_phy: ethernet-phy@1 { -+ compatible = "ethernet-phy-ieee802.3-c22"; -+ reg = <7>; -+ }; -+}; -+ - &ohci1 { - status = "okay"; - }; ---- a/arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts -+++ b/arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts -@@ -46,3 +46,10 @@ - model = "FriendlyARM NanoPi NEO"; - compatible = "friendlyarm,nanopi-neo", "allwinner,sun8i-h3"; - }; -+ -+&emac { -+ phy-handle = <&int_mii_phy>; -+ phy-mode = "mii"; -+ allwinner,leds-active-low; -+ status = "okay"; -+}; ---- a/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts -+++ b/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts -@@ -54,6 +54,7 @@ - aliases { - serial0 = &uart0; - /* ethernet0 is the H3 emac, defined in sun8i-h3.dtsi */ -+ ethernet0 = &emac; - ethernet1 = &rtl8189; - }; - -@@ -117,6 +118,13 @@ - status = "okay"; - }; - -+&emac { -+ phy-handle = <&int_mii_phy>; -+ phy-mode = "mii"; -+ allwinner,leds-active-low; -+ status = "okay"; -+}; -+ - &ir { - pinctrl-names = "default"; - pinctrl-0 = <&ir_pins_a>; ---- a/arch/arm/boot/dts/sun8i-h3-orangepi-one.dts -+++ b/arch/arm/boot/dts/sun8i-h3-orangepi-one.dts -@@ -52,6 +52,7 @@ - compatible = "xunlong,orangepi-one", "allwinner,sun8i-h3"; - - aliases { -+ ethernet0 = &emac; - serial0 = &uart0; - }; - -@@ -97,6 +98,13 @@ - status = "okay"; - }; - -+&emac { -+ phy-handle = <&int_mii_phy>; -+ phy-mode = "mii"; -+ allwinner,leds-active-low; -+ status = "okay"; -+}; -+ - &mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>; ---- a/arch/arm/boot/dts/sun8i-h3-orangepi-pc-plus.dts -+++ b/arch/arm/boot/dts/sun8i-h3-orangepi-pc-plus.dts -@@ -53,6 +53,11 @@ - }; - }; - -+&emac { -+ /* LEDs changed to active high on the plus */ -+ /delete-property/ allwinner,leds-active-low; -+}; -+ - &mmc1 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins_a>; ---- a/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts -+++ b/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts -@@ -52,6 +52,7 @@ - compatible = "xunlong,orangepi-pc", "allwinner,sun8i-h3"; - - aliases { -+ ethernet0 = &emac; - serial0 = &uart0; - }; - -@@ -113,6 +114,13 @@ - status = "okay"; - }; - -+&emac { -+ phy-handle = <&int_mii_phy>; -+ phy-mode = "mii"; -+ allwinner,leds-active-low; -+ status = "okay"; -+}; -+ - &ir { - pinctrl-names = "default"; - pinctrl-0 = <&ir_pins_a>; ---- a/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts -+++ b/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts -@@ -47,6 +47,10 @@ - model = "Xunlong Orange Pi Plus / Plus 2"; - compatible = "xunlong,orangepi-plus", "allwinner,sun8i-h3"; - -+ aliases { -+ ethernet0 = &emac; -+ }; -+ - reg_gmac_3v3: gmac-3v3 { - compatible = "regulator-fixed"; - regulator-name = "gmac-3v3"; -@@ -74,6 +78,24 @@ - status = "okay"; - }; - -+&emac { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&emac_rgmii_pins>; -+ phy-supply = <®_gmac_3v3>; -+ phy-handle = <&ext_rgmii_phy>; -+ phy-mode = "rgmii"; -+ -+ allwinner,leds-active-low; -+ status = "okay"; -+}; -+ -+&external_mdio { -+ ext_rgmii_phy: ethernet-phy@1 { -+ compatible = "ethernet-phy-ieee802.3-c22"; -+ reg = <0>; -+ }; -+}; -+ - &mmc2 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_8bit_pins>; ---- a/arch/arm/boot/dts/sun8i-h3-orangepi-plus2e.dts -+++ b/arch/arm/boot/dts/sun8i-h3-orangepi-plus2e.dts -@@ -61,3 +61,19 @@ - gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>; /* PD6 */ - }; - }; -+ -+&emac { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&emac_rgmii_pins>; -+ phy-supply = <®_gmac_3v3>; -+ phy-handle = <&ext_rgmii_phy>; -+ phy-mode = "rgmii"; -+ status = "okay"; -+}; -+ -+&external_mdio { -+ ext_rgmii_phy: ethernet-phy@1 { -+ compatible = "ethernet-phy-ieee802.3-c22"; -+ reg = <1>; -+ }; -+}; diff --git a/target/linux/sunxi/patches-4.14/021-arm-dts-sunxi-h3-h5-Restore-EMAC-changes.patch b/target/linux/sunxi/patches-4.14/021-arm-dts-sunxi-h3-h5-Restore-EMAC-changes.patch deleted file mode 100644 index 9e7319b4c88f..000000000000 --- a/target/linux/sunxi/patches-4.14/021-arm-dts-sunxi-h3-h5-Restore-EMAC-changes.patch +++ /dev/null @@ -1,54 +0,0 @@ -From 4b236a0fe51259ccde06aed046fe20bfe6e25dce Mon Sep 17 00:00:00 2001 -From: Corentin Labbe -Date: Tue, 31 Oct 2017 09:19:10 +0100 -Subject: [PATCH] arm: dts: sunxi: h3/h5: Restore EMAC changes - -The original dwmac-sun8i DT bindings have some issue on how to handle -integrated PHY and was reverted in last RC of 4.13. -But now we have a solution so we need to get back that was reverted. - -This patch restore sunxi-h3-h5.dtsi -This reverts partially commit fe45174b72ae ("arm: dts: sunxi: Revert EMAC changes") - -Signed-off-by: Corentin Labbe -Acked-by: Florian Fainelli -Signed-off-by: Maxime Ripard ---- - arch/arm/boot/dts/sunxi-h3-h5.dtsi | 26 ++++++++++++++++++++++++++ - 1 file changed, 26 insertions(+) - ---- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi -+++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi -@@ -391,6 +391,32 @@ - clocks = <&osc24M>; - }; - -+ emac: ethernet@1c30000 { -+ compatible = "allwinner,sun8i-h3-emac"; -+ syscon = <&syscon>; -+ reg = <0x01c30000 0x10000>; -+ interrupts = ; -+ interrupt-names = "macirq"; -+ resets = <&ccu RST_BUS_EMAC>; -+ reset-names = "stmmaceth"; -+ clocks = <&ccu CLK_BUS_EMAC>; -+ clock-names = "stmmaceth"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "disabled"; -+ -+ mdio: mdio { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ int_mii_phy: ethernet-phy@1 { -+ compatible = "ethernet-phy-ieee802.3-c22"; -+ reg = <1>; -+ clocks = <&ccu CLK_BUS_EPHY>; -+ resets = <&ccu RST_BUS_EPHY>; -+ }; -+ }; -+ }; -+ - spi0: spi@01c68000 { - compatible = "allwinner,sun8i-h3-spi"; - reg = <0x01c68000 0x1000>; diff --git a/target/linux/sunxi/patches-4.14/022-ARM-dts-sunxi-h3-h5-represent-the-mdio-switch-used-b.patch b/target/linux/sunxi/patches-4.14/022-ARM-dts-sunxi-h3-h5-represent-the-mdio-switch-used-b.patch deleted file mode 100644 index 2db4f1360920..000000000000 --- a/target/linux/sunxi/patches-4.14/022-ARM-dts-sunxi-h3-h5-represent-the-mdio-switch-used-b.patch +++ /dev/null @@ -1,59 +0,0 @@ -From 776245ae02f63ba2b94596b892c597676e190e78 Mon Sep 17 00:00:00 2001 -From: Corentin Labbe -Date: Tue, 31 Oct 2017 09:19:11 +0100 -Subject: [PATCH] ARM: dts: sunxi: h3/h5: represent the mdio switch used by - sun8i-h3-emac - -Since dwmac-sun8i could use either an integrated PHY or an external PHY -(which could be at same MDIO address), we need to represent this selection -by a MDIO switch. - -Signed-off-by: Corentin Labbe -Acked-by: Florian Fainelli -Reviewed-by: Andrew Lunn -Signed-off-by: Maxime Ripard ---- - arch/arm/boot/dts/sunxi-h3-h5.dtsi | 31 +++++++++++++++++++++++++++---- - 1 file changed, 27 insertions(+), 4 deletions(-) - ---- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi -+++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi -@@ -408,11 +408,34 @@ - mdio: mdio { - #address-cells = <1>; - #size-cells = <0>; -- int_mii_phy: ethernet-phy@1 { -- compatible = "ethernet-phy-ieee802.3-c22"; -+ compatible = "snps,dwmac-mdio"; -+ }; -+ -+ mdio-mux { -+ compatible = "allwinner,sun8i-h3-mdio-mux"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ mdio-parent-bus = <&mdio>; -+ /* Only one MDIO is usable at the time */ -+ internal_mdio: mdio@1 { -+ compatible = "allwinner,sun8i-h3-mdio-internal"; - reg = <1>; -- clocks = <&ccu CLK_BUS_EPHY>; -- resets = <&ccu RST_BUS_EPHY>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ int_mii_phy: ethernet-phy@1 { -+ compatible = "ethernet-phy-ieee802.3-c22"; -+ reg = <1>; -+ clocks = <&ccu CLK_BUS_EPHY>; -+ resets = <&ccu RST_BUS_EPHY>; -+ }; -+ }; -+ -+ external_mdio: mdio@2 { -+ reg = <2>; -+ #address-cells = <1>; -+ #size-cells = <0>; - }; - }; - }; diff --git a/target/linux/sunxi/patches-4.14/025-arm64-dts-allwinner-A64-Restore-EMAC-changes.patch b/target/linux/sunxi/patches-4.14/025-arm64-dts-allwinner-A64-Restore-EMAC-changes.patch deleted file mode 100644 index 23c3ec27edd3..000000000000 --- a/target/linux/sunxi/patches-4.14/025-arm64-dts-allwinner-A64-Restore-EMAC-changes.patch +++ /dev/null @@ -1,184 +0,0 @@ -From 94f442886711c6c4f4383a1c5a6994a788ba05d8 Mon Sep 17 00:00:00 2001 -From: Corentin Labbe -Date: Tue, 31 Oct 2017 09:19:13 +0100 -Subject: [PATCH] arm64: dts: allwinner: A64: Restore EMAC changes - -The original dwmac-sun8i DT bindings have some issue on how to handle -integrated PHY and was reverted in last RC of 4.13. -But now we have a solution so we need to get back that was reverted. - -This patch restore arm64 DT about dwmac-sun8i for A64 -This reverts commit 87e1f5e8bb4b ("arm64: dts: allwinner: Revert EMAC changes") - -Signed-off-by: Corentin Labbe -Acked-by: Florian Fainelli -Signed-off-by: Maxime Ripard ---- - .../boot/dts/allwinner/sun50i-a64-bananapi-m64.dts | 16 ++++++++++++++++ - .../boot/dts/allwinner/sun50i-a64-pine64-plus.dts | 15 +++++++++++++++ - arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts | 17 +++++++++++++++++ - .../dts/allwinner/sun50i-a64-sopine-baseboard.dts | 16 ++++++++++++++++ - arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 20 ++++++++++++++++++++ - 5 files changed, 84 insertions(+) - ---- a/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts -+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts -@@ -51,6 +51,7 @@ - compatible = "sinovoip,bananapi-m64", "allwinner,sun50i-a64"; - - aliases { -+ ethernet0 = &emac; - serial0 = &uart0; - serial1 = &uart1; - }; -@@ -69,6 +70,14 @@ - status = "okay"; - }; - -+&emac { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&rgmii_pins>; -+ phy-mode = "rgmii"; -+ phy-handle = <&ext_rgmii_phy>; -+ status = "okay"; -+}; -+ - &i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins>; -@@ -79,6 +88,13 @@ - bias-pull-up; - }; - -+&mdio { -+ ext_rgmii_phy: ethernet-phy@1 { -+ compatible = "ethernet-phy-ieee802.3-c22"; -+ reg = <1>; -+ }; -+}; -+ - &mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins>; ---- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts -+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts -@@ -48,3 +48,18 @@ - - /* TODO: Camera, touchscreen, etc. */ - }; -+ -+&emac { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&rgmii_pins>; -+ phy-mode = "rgmii"; -+ phy-handle = <&ext_rgmii_phy>; -+ status = "okay"; -+}; -+ -+&mdio { -+ ext_rgmii_phy: ethernet-phy@1 { -+ compatible = "ethernet-phy-ieee802.3-c22"; -+ reg = <1>; -+ }; -+}; ---- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts -+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts -@@ -51,6 +51,7 @@ - compatible = "pine64,pine64", "allwinner,sun50i-a64"; - - aliases { -+ ethernet0 = &emac; - serial0 = &uart0; - serial1 = &uart1; - serial2 = &uart2; -@@ -71,6 +72,15 @@ - status = "okay"; - }; - -+&emac { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&rmii_pins>; -+ phy-mode = "rmii"; -+ phy-handle = <&ext_rmii_phy1>; -+ status = "okay"; -+ -+}; -+ - &i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins>; -@@ -81,6 +91,13 @@ - bias-pull-up; - }; - -+&mdio { -+ ext_rmii_phy1: ethernet-phy@1 { -+ compatible = "ethernet-phy-ieee802.3-c22"; -+ reg = <1>; -+ }; -+}; -+ - &mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins>; ---- a/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts -+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts -@@ -53,6 +53,7 @@ - "allwinner,sun50i-a64"; - - aliases { -+ ethernet0 = &emac; - serial0 = &uart0; - }; - -@@ -76,6 +77,21 @@ - status = "okay"; - }; - -+&emac { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&rgmii_pins>; -+ phy-mode = "rgmii"; -+ phy-handle = <&ext_rgmii_phy>; -+ status = "okay"; -+}; -+ -+&mdio { -+ ext_rgmii_phy: ethernet-phy@1 { -+ compatible = "ethernet-phy-ieee802.3-c22"; -+ reg = <1>; -+ }; -+}; -+ - &mmc2 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_pins>; ---- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi -+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi -@@ -450,6 +450,26 @@ - #size-cells = <0>; - }; - -+ emac: ethernet@1c30000 { -+ compatible = "allwinner,sun50i-a64-emac"; -+ syscon = <&syscon>; -+ reg = <0x01c30000 0x10000>; -+ interrupts = ; -+ interrupt-names = "macirq"; -+ resets = <&ccu RST_BUS_EMAC>; -+ reset-names = "stmmaceth"; -+ clocks = <&ccu CLK_BUS_EMAC>; -+ clock-names = "stmmaceth"; -+ status = "disabled"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ mdio: mdio { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ }; -+ }; -+ - gic: interrupt-controller@1c81000 { - compatible = "arm,gic-400"; - reg = <0x01c81000 0x1000>, diff --git a/target/linux/sunxi/patches-4.14/026-arm64-dts-allwinner-add-snps-dwmac-mdio-compatible-t.patch b/target/linux/sunxi/patches-4.14/026-arm64-dts-allwinner-add-snps-dwmac-mdio-compatible-t.patch deleted file mode 100644 index ee4731d0dcdb..000000000000 --- a/target/linux/sunxi/patches-4.14/026-arm64-dts-allwinner-add-snps-dwmac-mdio-compatible-t.patch +++ /dev/null @@ -1,28 +0,0 @@ -From 16416084e06e1ebff51a9e7721a8cc4ccc186f28 Mon Sep 17 00:00:00 2001 -From: Corentin Labbe -Date: Tue, 31 Oct 2017 09:19:15 +0100 -Subject: [PATCH] arm64: dts: allwinner: add snps,dwmac-mdio compatible to - emac/mdio - -stmmac bindings docs said that its mdio node must have -compatible = "snps,dwmac-mdio"; -Since dwmac-sun8i does not have any good reasons to not doing it, all -their MDIO node must have it. - -Signed-off-by: Corentin Labbe -Acked-by: Florian Fainelli -Signed-off-by: Maxime Ripard ---- - arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 1 + - 1 file changed, 1 insertion(+) - ---- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi -+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi -@@ -465,6 +465,7 @@ - #size-cells = <0>; - - mdio: mdio { -+ compatible = "snps,dwmac-mdio"; - #address-cells = <1>; - #size-cells = <0>; - }; diff --git a/target/linux/sunxi/patches-4.14/027-arm64-dts-allwinner-H5-Restore-EMAC-changes.patch b/target/linux/sunxi/patches-4.14/027-arm64-dts-allwinner-H5-Restore-EMAC-changes.patch deleted file mode 100644 index b2c9d75ad772..000000000000 --- a/target/linux/sunxi/patches-4.14/027-arm64-dts-allwinner-H5-Restore-EMAC-changes.patch +++ /dev/null @@ -1,120 +0,0 @@ -From 44a94c7ef989317de81e3e7f84385be2bf1b5fe2 Mon Sep 17 00:00:00 2001 -From: Corentin Labbe -Date: Tue, 31 Oct 2017 09:19:14 +0100 -Subject: [PATCH] arm64: dts: allwinner: H5: Restore EMAC changes - -The original dwmac-sun8i DT bindings have some issue on how to handle -integrated PHY and was reverted in last RC of 4.13. -But now we have a solution so we need to get back that was reverted. - -This patch restore arm64 DT about dwmac-sun8i for H5 -This reverts a part of commit 87e1f5e8bb4b ("arm64: dts: allwinner: Revert EMAC changes") - -Signed-off-by: Corentin Labbe -Acked-by: Florian Fainelli -Signed-off-by: Maxime Ripard ---- - arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo2.dts | 17 +++++++++++++++++ - .../arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts | 17 +++++++++++++++++ - .../boot/dts/allwinner/sun50i-h5-orangepi-prime.dts | 17 +++++++++++++++++ - 3 files changed, 51 insertions(+) - ---- a/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo2.dts -+++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo2.dts -@@ -50,6 +50,7 @@ - compatible = "friendlyarm,nanopi-neo2", "allwinner,sun50i-h5"; - - aliases { -+ ethernet0 = &emac; - serial0 = &uart0; - }; - -@@ -108,6 +109,22 @@ - status = "okay"; - }; - -+&emac { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&emac_rgmii_pins>; -+ phy-supply = <®_gmac_3v3>; -+ phy-handle = <&ext_rgmii_phy>; -+ phy-mode = "rgmii"; -+ status = "okay"; -+}; -+ -+&external_mdio { -+ ext_rgmii_phy: ethernet-phy@7 { -+ compatible = "ethernet-phy-ieee802.3-c22"; -+ reg = <7>; -+ }; -+}; -+ - &mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>; ---- a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts -+++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts -@@ -59,6 +59,7 @@ - }; - - aliases { -+ ethernet0 = &emac; - serial0 = &uart0; - }; - -@@ -136,6 +137,22 @@ - status = "okay"; - }; - -+&emac { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&emac_rgmii_pins>; -+ phy-supply = <®_gmac_3v3>; -+ phy-handle = <&ext_rgmii_phy>; -+ phy-mode = "rgmii"; -+ status = "okay"; -+}; -+ -+&external_mdio { -+ ext_rgmii_phy: ethernet-phy@1 { -+ compatible = "ethernet-phy-ieee802.3-c22"; -+ reg = <1>; -+ }; -+}; -+ - &ir { - pinctrl-names = "default"; - pinctrl-0 = <&ir_pins_a>; ---- a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-prime.dts -+++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-prime.dts -@@ -54,6 +54,7 @@ - compatible = "xunlong,orangepi-prime", "allwinner,sun50i-h5"; - - aliases { -+ ethernet0 = &emac; - serial0 = &uart0; - }; - -@@ -143,6 +144,22 @@ - status = "okay"; - }; - -+&emac { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&emac_rgmii_pins>; -+ phy-supply = <®_gmac_3v3>; -+ phy-handle = <&ext_rgmii_phy>; -+ phy-mode = "rgmii"; -+ status = "okay"; -+}; -+ -+&external_mdio { -+ ext_rgmii_phy: ethernet-phy@1 { -+ compatible = "ethernet-phy-ieee802.3-c22"; -+ reg = <1>; -+ }; -+}; -+ - &ir { - pinctrl-names = "default"; - pinctrl-0 = <&ir_pins_a>; diff --git a/target/linux/sunxi/patches-4.14/030-arm64-allwinner-a64-add-Ethernet-PHY-regulator-for-s.patch b/target/linux/sunxi/patches-4.14/030-arm64-allwinner-a64-add-Ethernet-PHY-regulator-for-s.patch deleted file mode 100644 index 295fff2e7447..000000000000 --- a/target/linux/sunxi/patches-4.14/030-arm64-allwinner-a64-add-Ethernet-PHY-regulator-for-s.patch +++ /dev/null @@ -1,51 +0,0 @@ -From bdfe4cebea11476d278b1b98dd0f7cdac8269d62 Mon Sep 17 00:00:00 2001 -From: Icenowy Zheng -Date: Fri, 10 Nov 2017 17:26:54 +0800 -Subject: [PATCH] arm64: allwinner: a64: add Ethernet PHY regulator for several - boards - -On several A64 boards the Ethernet PHY is powered by the DC1SW regulator -on the AXP803 PMIC. - -Add phy-handle property to these boards' emac node. - -Signed-off-by: Icenowy Zheng -Acked-by: Corentin LABBE -Tested-by: Corentin LABBE -Signed-off-by: Maxime Ripard ---- - arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts | 1 + - arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts | 1 + - arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts | 1 + - 3 files changed, 3 insertions(+) - ---- a/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts -+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts -@@ -75,6 +75,7 @@ - pinctrl-0 = <&rgmii_pins>; - phy-mode = "rgmii"; - phy-handle = <&ext_rgmii_phy>; -+ phy-supply = <®_dc1sw>; - status = "okay"; - }; - ---- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts -+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts -@@ -77,6 +77,7 @@ - pinctrl-0 = <&rmii_pins>; - phy-mode = "rmii"; - phy-handle = <&ext_rmii_phy1>; -+ phy-supply = <®_dc1sw>; - status = "okay"; - - }; ---- a/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts -+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts -@@ -82,6 +82,7 @@ - pinctrl-0 = <&rgmii_pins>; - phy-mode = "rgmii"; - phy-handle = <&ext_rgmii_phy>; -+ phy-supply = <®_dc1sw>; - status = "okay"; - }; - diff --git a/target/linux/sunxi/patches-4.14/031-arm64-Implement-arch_counter_get_cntpct-to-read-the-.patch b/target/linux/sunxi/patches-4.14/031-arm64-Implement-arch_counter_get_cntpct-to-read-the-.patch deleted file mode 100644 index 60f0cb6c9b90..000000000000 --- a/target/linux/sunxi/patches-4.14/031-arm64-Implement-arch_counter_get_cntpct-to-read-the-.patch +++ /dev/null @@ -1,118 +0,0 @@ -From f2e600c149fda3453344f89c7e9353fe278ebd32 Mon Sep 17 00:00:00 2001 -From: Christoffer Dall -Date: Wed, 18 Oct 2017 13:06:25 +0200 -Subject: [PATCH] arm64: Implement arch_counter_get_cntpct to read the physical - counter - -As we are about to use the physical counter on arm64 systems that have -KVM support, implement arch_counter_get_cntpct() and the associated -errata workaround functionality for stable timer reads. - -Cc: Will Deacon -Cc: Mark Rutland -Acked-by: Catalin Marinas -Acked-by: Marc Zyngier -Signed-off-by: Christoffer Dall ---- - arch/arm64/include/asm/arch_timer.h | 8 +++----- - drivers/clocksource/arm_arch_timer.c | 23 +++++++++++++++++++++++ - 2 files changed, 26 insertions(+), 5 deletions(-) - ---- a/arch/arm64/include/asm/arch_timer.h -+++ b/arch/arm64/include/asm/arch_timer.h -@@ -52,6 +52,7 @@ struct arch_timer_erratum_workaround { - const char *desc; - u32 (*read_cntp_tval_el0)(void); - u32 (*read_cntv_tval_el0)(void); -+ u64 (*read_cntpct_el0)(void); - u64 (*read_cntvct_el0)(void); - int (*set_next_event_phys)(unsigned long, struct clock_event_device *); - int (*set_next_event_virt)(unsigned long, struct clock_event_device *); -@@ -148,11 +149,8 @@ static inline void arch_timer_set_cntkct - - static inline u64 arch_counter_get_cntpct(void) - { -- /* -- * AArch64 kernel and user space mandate the use of CNTVCT. -- */ -- BUG(); -- return 0; -+ isb(); -+ return arch_timer_reg_read_stable(cntpct_el0); - } - - static inline u64 arch_counter_get_cntvct(void) ---- a/drivers/clocksource/arm_arch_timer.c -+++ b/drivers/clocksource/arm_arch_timer.c -@@ -217,6 +217,11 @@ static u32 notrace fsl_a008585_read_cntv - return __fsl_a008585_read_reg(cntv_tval_el0); - } - -+static u64 notrace fsl_a008585_read_cntpct_el0(void) -+{ -+ return __fsl_a008585_read_reg(cntpct_el0); -+} -+ - static u64 notrace fsl_a008585_read_cntvct_el0(void) - { - return __fsl_a008585_read_reg(cntvct_el0); -@@ -258,6 +263,11 @@ static u32 notrace hisi_161010101_read_c - return __hisi_161010101_read_reg(cntv_tval_el0); - } - -+static u64 notrace hisi_161010101_read_cntpct_el0(void) -+{ -+ return __hisi_161010101_read_reg(cntpct_el0); -+} -+ - static u64 notrace hisi_161010101_read_cntvct_el0(void) - { - return __hisi_161010101_read_reg(cntvct_el0); -@@ -288,6 +298,15 @@ static struct ate_acpi_oem_info hisi_161 - #endif - - #ifdef CONFIG_ARM64_ERRATUM_858921 -+static u64 notrace arm64_858921_read_cntpct_el0(void) -+{ -+ u64 old, new; -+ -+ old = read_sysreg(cntpct_el0); -+ new = read_sysreg(cntpct_el0); -+ return (((old ^ new) >> 32) & 1) ? old : new; -+} -+ - static u64 notrace arm64_858921_read_cntvct_el0(void) - { - u64 old, new; -@@ -346,6 +365,7 @@ static const struct arch_timer_erratum_w - .desc = "Freescale erratum a005858", - .read_cntp_tval_el0 = fsl_a008585_read_cntp_tval_el0, - .read_cntv_tval_el0 = fsl_a008585_read_cntv_tval_el0, -+ .read_cntpct_el0 = fsl_a008585_read_cntpct_el0, - .read_cntvct_el0 = fsl_a008585_read_cntvct_el0, - .set_next_event_phys = erratum_set_next_event_tval_phys, - .set_next_event_virt = erratum_set_next_event_tval_virt, -@@ -358,6 +378,7 @@ static const struct arch_timer_erratum_w - .desc = "HiSilicon erratum 161010101", - .read_cntp_tval_el0 = hisi_161010101_read_cntp_tval_el0, - .read_cntv_tval_el0 = hisi_161010101_read_cntv_tval_el0, -+ .read_cntpct_el0 = hisi_161010101_read_cntpct_el0, - .read_cntvct_el0 = hisi_161010101_read_cntvct_el0, - .set_next_event_phys = erratum_set_next_event_tval_phys, - .set_next_event_virt = erratum_set_next_event_tval_virt, -@@ -368,6 +389,7 @@ static const struct arch_timer_erratum_w - .desc = "HiSilicon erratum 161010101", - .read_cntp_tval_el0 = hisi_161010101_read_cntp_tval_el0, - .read_cntv_tval_el0 = hisi_161010101_read_cntv_tval_el0, -+ .read_cntpct_el0 = hisi_161010101_read_cntpct_el0, - .read_cntvct_el0 = hisi_161010101_read_cntvct_el0, - .set_next_event_phys = erratum_set_next_event_tval_phys, - .set_next_event_virt = erratum_set_next_event_tval_virt, -@@ -378,6 +400,7 @@ static const struct arch_timer_erratum_w - .match_type = ate_match_local_cap_id, - .id = (void *)ARM64_WORKAROUND_858921, - .desc = "ARM erratum 858921", -+ .read_cntpct_el0 = arm64_858921_read_cntpct_el0, - .read_cntvct_el0 = arm64_858921_read_cntvct_el0, - }, - #endif diff --git a/target/linux/sunxi/patches-4.14/040-arm64-dts-allwinner-a64-Add-watchdog.patch b/target/linux/sunxi/patches-4.14/040-arm64-dts-allwinner-a64-Add-watchdog.patch deleted file mode 100644 index 90c72f950830..000000000000 --- a/target/linux/sunxi/patches-4.14/040-arm64-dts-allwinner-a64-Add-watchdog.patch +++ /dev/null @@ -1,47 +0,0 @@ -From d41850437c364ef7aba9bc25c1c701699d0240e0 Mon Sep 17 00:00:00 2001 -From: Harald Geyer -Date: Thu, 15 Mar 2018 16:25:07 +0000 -Subject: [PATCH] arm64: dts: allwinner: a64: Add watchdog - -Add a watchdog node for the A64, automatically enabled on all boards. -Since the device is compatible with an existing driver, we only reserve -a new compatible string to be used together with the fall back. -Tested on Olimex Teres-I. - -Signed-off-by: Harald Geyer -Signed-off-by: Maxime Ripard ---- - Documentation/devicetree/bindings/watchdog/sunxi-wdt.txt | 6 ++++-- - arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 7 +++++++ - 2 files changed, 11 insertions(+), 2 deletions(-) - ---- a/Documentation/devicetree/bindings/watchdog/sunxi-wdt.txt -+++ b/Documentation/devicetree/bindings/watchdog/sunxi-wdt.txt -@@ -2,8 +2,10 @@ Allwinner SoCs Watchdog timer - - Required properties: - --- compatible : should be either "allwinner,sun4i-a10-wdt" or -- "allwinner,sun6i-a31-wdt" -+- compatible : should be one of -+ "allwinner,sun4i-a10-wdt" -+ "allwinner,sun6i-a31-wdt" -+ "allwinner,sun50i-a64-wdt","allwinner,sun6i-a31-wdt" - - reg : Specifies base physical address and size of the registers. - - Example: ---- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi -+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi -@@ -538,5 +538,12 @@ - #address-cells = <1>; - #size-cells = <0>; - }; -+ -+ wdt0: watchdog@1c20ca0 { -+ compatible = "allwinner,sun50i-a64-wdt", -+ "allwinner,sun6i-a31-wdt"; -+ reg = <0x01c20ca0 0x20>; -+ interrupts = ; -+ }; - }; - }; diff --git a/target/linux/sunxi/patches-4.14/060-ARM-dts-sun8i-add-support-for-Orange-Pi-R1.patch b/target/linux/sunxi/patches-4.14/060-ARM-dts-sun8i-add-support-for-Orange-Pi-R1.patch deleted file mode 100644 index e9d448792c73..000000000000 --- a/target/linux/sunxi/patches-4.14/060-ARM-dts-sun8i-add-support-for-Orange-Pi-R1.patch +++ /dev/null @@ -1,105 +0,0 @@ -From 74942cd5dfe4ac4fd982fe58118bc69346a2bd18 Mon Sep 17 00:00:00 2001 -From: Icenowy Zheng -Date: Sun, 12 Nov 2017 20:41:29 +0800 -Subject: [PATCH] ARM: dts: sun8i: add support for Orange Pi R1 - -Orange Pi R1 is a board design based on Orange Pi Zero, with XR819 Wi-Fi -chip replaced by RTL8189ETV Wi-Fi module and the USB Type-A jack -replaced by an onboard USB RTL8152B USB-Ethernet adapter. - -Add support for it. - -Signed-off-by: Icenowy Zheng -Signed-off-by: Maxime Ripard ---- - arch/arm/boot/dts/Makefile | 1 + - arch/arm/boot/dts/sun8i-h2-plus-orangepi-r1.dts | 73 +++++++++++++++++++++++++ - 2 files changed, 74 insertions(+) - create mode 100644 arch/arm/boot/dts/sun8i-h2-plus-orangepi-r1.dts - ---- a/arch/arm/boot/dts/Makefile -+++ b/arch/arm/boot/dts/Makefile -@@ -916,6 +916,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \ - sun8i-a83t-allwinner-h8homlet-v2.dtb \ - sun8i-a83t-bananapi-m3.dtb \ - sun8i-a83t-cubietruck-plus.dtb \ -+ sun8i-h2-plus-orangepi-r1.dtb \ - sun8i-h2-plus-orangepi-zero.dtb \ - sun8i-h3-bananapi-m2-plus.dtb \ - sun8i-h3-beelink-x2.dtb \ ---- /dev/null -+++ b/arch/arm/boot/dts/sun8i-h2-plus-orangepi-r1.dts -@@ -0,0 +1,73 @@ -+/* -+ * Copyright (C) 2017 Icenowy Zheng -+ * -+ * This file is dual-licensed: you can use it either under the terms -+ * of the GPL or the X11 license, at your option. Note that this dual -+ * licensing only applies to this file, and not this project as a -+ * whole. -+ * -+ * a) This file is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License as -+ * published by the Free Software Foundation; either version 2 of the -+ * License, or (at your option) any later version. -+ * -+ * This file is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * Or, alternatively, -+ * -+ * b) Permission is hereby granted, free of charge, to any person -+ * obtaining a copy of this software and associated documentation -+ * files (the "Software"), to deal in the Software without -+ * restriction, including without limitation the rights to use, -+ * copy, modify, merge, publish, distribute, sublicense, and/or -+ * sell copies of the Software, and to permit persons to whom the -+ * Software is furnished to do so, subject to the following -+ * conditions: -+ * -+ * The above copyright notice and this permission notice shall be -+ * included in all copies or substantial portions of the Software. -+ * -+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES -+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND -+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT -+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, -+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING -+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR -+ * OTHER DEALINGS IN THE SOFTWARE. -+ */ -+ -+/* Orange Pi R1 is based on Orange Pi Zero design */ -+#include "sun8i-h2-plus-orangepi-zero.dts" -+ -+/ { -+ model = "Xunlong Orange Pi R1"; -+ compatible = "xunlong,orangepi-r1", "allwinner,sun8i-h2-plus"; -+ -+ /delete-node/ reg_vcc_wifi; -+ -+ aliases { -+ ethernet1 = &rtl8189etv; -+ }; -+}; -+ -+&ohci1 { -+ /* -+ * RTL8152B USB-Ethernet adapter is connected to USB1, -+ * and it's a USB 2.0 device. So the OHCI1 controller -+ * can be left disabled. -+ */ -+ status = "disabled"; -+}; -+ -+&mmc1 { -+ vmmc-supply = <®_vcc3v3>; -+ vqmmc-supply = <®_vcc3v3>; -+ -+ rtl8189etv: sdio_wifi@1 { -+ reg = <1>; -+ }; -+}; diff --git a/target/linux/sunxi/patches-4.14/061-arm-dts-sun50i-support-for-nanopi-neo-plus2-board.patch b/target/linux/sunxi/patches-4.14/061-arm-dts-sun50i-support-for-nanopi-neo-plus2-board.patch deleted file mode 100644 index 9c0e64a9023c..000000000000 --- a/target/linux/sunxi/patches-4.14/061-arm-dts-sun50i-support-for-nanopi-neo-plus2-board.patch +++ /dev/null @@ -1,242 +0,0 @@ -From 54cc3330c2334a0cea8cafc105a29c5d67f9fd32 Mon Sep 17 00:00:00 2001 -From: Antony Antony -Date: Fri, 2 Mar 2018 10:50:48 +0100 -Subject: [PATCH] arm64: allwinner: h5: add NanoPi NEO Plus2 DT support - -Add initial DT for NanoPi NEO Plus2 by FriendlyARM -- Allwinner quad core H5 Cortex A53 with an ARM Mali-450MP GPU -- 1 GB DDR3 RAM -- 8GB eMMC flash (Samsung KLM8G1WEPD-B031) -- micro SD card slot -- Gigabit Ethernet (external RTL8211E-VB-CG chip) -- 802.11 b/g/n WiFi, Bluetooth 4.0 (Ampak AP6212A module) -- 2x USB 2.0 host ports & 2x USB via headers - -Kernel 4.15 commit d7341305863b -Kernel 4.16 commit 27d7f9297027 - -Signed-off-by: Antony Antony - ---- a/arch/arm64/boot/dts/allwinner/Makefile -+++ b/arch/arm64/boot/dts/allwinner/Makefile -@@ -9,6 +9,7 @@ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-or - dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-orangepi-prime.dtb - dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-orangepi-zero-plus2.dtb - dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-nanopi-neo2.dtb -+dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-nanopi-neo-plus2.dtb - - always := $(dtb-y) - subdir-y := $(dts-dirs) ---- /dev/null -+++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo-plus2.dts -@@ -0,0 +1,210 @@ -+/* -+ * Copyright (C) 2017 Antony Antony -+ * Copyright (C) 2016 ARM Ltd. -+ * -+ * This file is dual-licensed: you can use it either under the terms -+ * of the GPL or the X11 license, at your option. Note that this dual -+ * licensing only applies to this file, and not this project as a -+ * whole. -+ * -+ * a) This file is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License as -+ * published by the Free Software Foundation; either version 2 of the -+ * License, or (at your option) any later version. -+ * -+ * This file is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * Or, alternatively, -+ * -+ * b) Permission is hereby granted, free of charge, to any person -+ * obtaining a copy of this software and associated documentation -+ * files (the "Software"), to deal in the Software without -+ * restriction, including without limitation the rights to use, -+ * copy, modify, merge, publish, distribute, sublicense, and/or -+ * sell copies of the Software, and to permit persons to whom the -+ * Software is furnished to do so, subject to the following -+ * conditions: -+ * -+ * The above copyright notice and this permission notice shall be -+ * included in all copies or substantial portions of the Software. -+ * -+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES -+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND -+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT -+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, -+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING -+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR -+ * OTHER DEALINGS IN THE SOFTWARE. -+ */ -+ -+/dts-v1/; -+#include "sun50i-h5.dtsi" -+ -+#include -+#include -+#include -+ -+/ { -+ model = "FriendlyARM NanoPi NEO Plus2"; -+ compatible = "friendlyarm,nanopi-neo-plus2", "allwinner,sun50i-h5"; -+ -+ aliases { -+ ethernet0 = &emac; -+ serial0 = &uart0; -+ }; -+ -+ chosen { -+ stdout-path = "serial0:115200n8"; -+ }; -+ -+ leds { -+ compatible = "gpio-leds"; -+ -+ pwr { -+ label = "nanopi:green:pwr"; -+ gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; -+ default-state = "on"; -+ }; -+ -+ status { -+ label = "nanopi:red:status"; -+ gpios = <&pio 0 20 GPIO_ACTIVE_HIGH>; -+ }; -+ }; -+ -+ reg_gmac_3v3: gmac-3v3 { -+ compatible = "regulator-fixed"; -+ pinctrl-names = "default"; -+ regulator-name = "gmac-3v3"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ startup-delay-us = <100000>; -+ enable-active-high; -+ gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>; -+ }; -+ -+ reg_vcc3v3: vcc3v3 { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc3v3"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ }; -+ -+ vdd_cpux: gpio-regulator { -+ compatible = "regulator-gpio"; -+ pinctrl-names = "default"; -+ regulator-name = "vdd-cpux"; -+ regulator-type = "voltage"; -+ regulator-boot-on; -+ regulator-always-on; -+ regulator-min-microvolt = <1100000>; -+ regulator-max-microvolt = <1300000>; -+ regulator-ramp-delay = <50>; /* 4ms */ -+ gpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; -+ gpios-states = <0x1>; -+ states = <1100000 0x0 -+ 1300000 0x1>; -+ }; -+ -+ wifi_pwrseq: wifi_pwrseq { -+ compatible = "mmc-pwrseq-simple"; -+ pinctrl-names = "default"; -+ reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */ -+ post-power-on-delay-ms = <200>; -+ }; -+}; -+ -+&codec { -+ allwinner,audio-routing = -+ "Line Out", "LINEOUT", -+ "MIC1", "Mic", -+ "Mic", "MBIAS"; -+ status = "okay"; -+}; -+ -+&ehci0 { -+ status = "okay"; -+}; -+ -+&ehci3 { -+ status = "okay"; -+}; -+ -+&emac { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&emac_rgmii_pins>; -+ phy-supply = <®_gmac_3v3>; -+ phy-handle = <&ext_rgmii_phy>; -+ phy-mode = "rgmii"; -+ status = "okay"; -+}; -+ -+&external_mdio { -+ ext_rgmii_phy: ethernet-phy@7 { -+ compatible = "ethernet-phy-ieee802.3-c22"; -+ reg = <7>; -+ }; -+}; -+ -+&mmc0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>; -+ vmmc-supply = <®_vcc3v3>; -+ bus-width = <4>; -+ cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ -+ status = "okay"; -+}; -+ -+&mmc1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&mmc1_pins_a>; -+ vmmc-supply = <®_vcc3v3>; -+ vqmmc-supply = <®_vcc3v3>; -+ mmc-pwrseq = <&wifi_pwrseq>; -+ bus-width = <4>; -+ non-removable; -+ status = "okay"; -+ -+ brcmf: wifi@1 { -+ reg = <1>; -+ compatible = "brcm,bcm4329-fmac"; -+ }; -+}; -+ -+&mmc2 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&mmc2_8bit_pins>; -+ vmmc-supply = <®_vcc3v3>; -+ bus-width = <8>; -+ non-removable; -+ cap-mmc-hw-reset; -+ status = "okay"; -+}; -+ -+&ohci0 { -+ status = "okay"; -+}; -+ -+&ohci3 { -+ status = "okay"; -+}; -+ -+&uart0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&uart0_pins_a>; -+ status = "okay"; -+}; -+ -+&usb_otg { -+ dr_mode = "host"; -+ status = "okay"; -+}; -+ -+&usbphy { -+ /* USB Type-A ports' VBUS is always on */ -+ status = "okay"; -+}; diff --git a/target/linux/sunxi/patches-4.14/080-arm64-allwinner-a64-add-SPI-nodes.patch b/target/linux/sunxi/patches-4.14/080-arm64-allwinner-a64-add-SPI-nodes.patch deleted file mode 100644 index 1e40f99d04e2..000000000000 --- a/target/linux/sunxi/patches-4.14/080-arm64-allwinner-a64-add-SPI-nodes.patch +++ /dev/null @@ -1,78 +0,0 @@ -From b518bb159032aac33503fd4cf98706dc84cc1266 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Stefan=20Br=C3=BCns?= -Date: Thu, 31 Aug 2017 01:06:37 +0200 -Subject: [PATCH] arm64: allwinner: a64: add SPI nodes -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -The A64 SPI controllers are register compatible to the h3/h5 SPI -controllers. - -The A64 has two SPI controllers, each with a single chip select. -The handles for the DMA channels (23/24 for SPI0/SPI1) are omitted, -as the A64 DMA support is currently missing. - -Signed-off-by: Stefan Brüns -Signed-off-by: Maxime Ripard ---- - arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 41 +++++++++++++++++++ - 1 file changed, 41 insertions(+) - ---- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi -+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi -@@ -326,6 +326,16 @@ - drive-strength = <40>; - }; - -+ spi0_pins: spi0 { -+ pins = "PC0", "PC1", "PC2", "PC3"; -+ function = "spi0"; -+ }; -+ -+ spi1_pins: spi1 { -+ pins = "PD0", "PD1", "PD2", "PD3"; -+ function = "spi1"; -+ }; -+ - uart0_pins_a: uart0@0 { - pins = "PB8", "PB9"; - function = "uart0"; -@@ -471,6 +481,37 @@ - }; - }; - -+ -+ spi0: spi@01c68000 { -+ compatible = "allwinner,sun8i-h3-spi"; -+ reg = <0x01c68000 0x1000>; -+ interrupts = ; -+ clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>; -+ clock-names = "ahb", "mod"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&spi0_pins>; -+ resets = <&ccu RST_BUS_SPI0>; -+ status = "disabled"; -+ num-cs = <1>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ }; -+ -+ spi1: spi@01c69000 { -+ compatible = "allwinner,sun8i-h3-spi"; -+ reg = <0x01c69000 0x1000>; -+ interrupts = ; -+ clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>; -+ clock-names = "ahb", "mod"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&spi1_pins>; -+ resets = <&ccu RST_BUS_SPI1>; -+ status = "disabled"; -+ num-cs = <1>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ }; -+ - gic: interrupt-controller@1c81000 { - compatible = "arm,gic-400"; - reg = <0x01c81000 0x1000>, diff --git a/target/linux/sunxi/patches-4.14/081-arm64-dts-allwinner-sun50i-a64-Add-spi-flash-node-fo.patch b/target/linux/sunxi/patches-4.14/081-arm64-dts-allwinner-sun50i-a64-Add-spi-flash-node-fo.patch deleted file mode 100644 index 3a6e1c3bfa2f..000000000000 --- a/target/linux/sunxi/patches-4.14/081-arm64-dts-allwinner-sun50i-a64-Add-spi-flash-node-fo.patch +++ /dev/null @@ -1,36 +0,0 @@ -From 4661c3afefe900ff7b5004aca0a2c927cfa37f3b Mon Sep 17 00:00:00 2001 -From: Emmanuel Vadot -Date: Mon, 21 May 2018 13:54:13 +0200 -Subject: [PATCH] arm64: dts: allwinner: sun50i: a64: Add spi flash node for - sopine - -The Sopine and Pine64-LTS have a winbond w25q128 spi flash on spi0. -Add a node for it. - -Signed-off-by: Emmanuel Vadot -Signed-off-by: Maxime Ripard ---- - arch/arm64/boot/dts/allwinner/sun50i-a64-sopine.dtsi | 12 ++++++++++++ - 1 file changed, 12 insertions(+) - ---- a/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine.dtsi -+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine.dtsi -@@ -75,6 +75,18 @@ - }; - }; - -+&spi0 { -+ status = "okay"; -+ -+ flash@0 { -+ #address-cells = <1>; -+ #size-cells = <1>; -+ compatible = "jedec,spi-nor"; -+ reg = <0>; -+ spi-max-frequency = <40000000>; -+ }; -+}; -+ - #include "axp803.dtsi" - - ®_aldo2 { diff --git a/target/linux/sunxi/patches-4.14/100-clocksource-drivers-arch_timer-Workaround-for-Allwin.patch b/target/linux/sunxi/patches-4.14/100-clocksource-drivers-arch_timer-Workaround-for-Allwin.patch deleted file mode 100644 index 6da300312fc7..000000000000 --- a/target/linux/sunxi/patches-4.14/100-clocksource-drivers-arch_timer-Workaround-for-Allwin.patch +++ /dev/null @@ -1,244 +0,0 @@ -From 7cd6dca3600d8d71328950216688ecd00015d1ce Mon Sep 17 00:00:00 2001 -From: Samuel Holland -Date: Sat, 12 Jan 2019 20:17:18 -0600 -Subject: [PATCH] clocksource/drivers/arch_timer: Workaround for Allwinner A64 - timer instability -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -The Allwinner A64 SoC is known[1] to have an unstable architectural -timer, which manifests itself most obviously in the time jumping forward -a multiple of 95 years[2][3]. This coincides with 2^56 cycles at a -timer frequency of 24 MHz, implying that the time went slightly backward -(and this was interpreted by the kernel as it jumping forward and -wrapping around past the epoch). - -Investigation revealed instability in the low bits of CNTVCT at the -point a high bit rolls over. This leads to power-of-two cycle forward -and backward jumps. (Testing shows that forward jumps are about twice as -likely as backward jumps.) Since the counter value returns to normal -after an indeterminate read, each "jump" really consists of both a -forward and backward jump from the software perspective. - -Unless the kernel is trapping CNTVCT reads, a userspace program is able -to read the register in a loop faster than it changes. A test program -running on all 4 CPU cores that reported jumps larger than 100 ms was -run for 13.6 hours and reported the following: - - Count | Event --------+--------------------------- - 9940 | jumped backward 699ms - 268 | jumped backward 1398ms - 1 | jumped backward 2097ms - 16020 | jumped forward 175ms - 6443 | jumped forward 699ms - 2976 | jumped forward 1398ms - 9 | jumped forward 356516ms - 9 | jumped forward 357215ms - 4 | jumped forward 714430ms - 1 | jumped forward 3578440ms - -This works out to a jump larger than 100 ms about every 5.5 seconds on -each CPU core. - -The largest jump (almost an hour!) was the following sequence of reads: - 0x0000007fffffffff → 0x00000093feffffff → 0x0000008000000000 - -Note that the middle bits don't necessarily all read as all zeroes or -all ones during the anomalous behavior; however the low 10 bits checked -by the function in this patch have never been observed with any other -value. - -Also note that smaller jumps are much more common, with backward jumps -of 2048 (2^11) cycles observed over 400 times per second on each core. -(Of course, this is partially explained by lower bits rolling over more -frequently.) Any one of these could have caused the 95 year time skip. - -Similar anomalies were observed while reading CNTPCT (after patching the -kernel to allow reads from userspace). However, the CNTPCT jumps are -much less frequent, and only small jumps were observed. The same program -as before (except now reading CNTPCT) observed after 72 hours: - - Count | Event --------+--------------------------- - 17 | jumped backward 699ms - 52 | jumped forward 175ms - 2831 | jumped forward 699ms - 5 | jumped forward 1398ms - -Further investigation showed that the instability in CNTPCT/CNTVCT also -affected the respective timer's TVAL register. The following values were -observed immediately after writing CNVT_TVAL to 0x10000000: - - CNTVCT | CNTV_TVAL | CNTV_CVAL | CNTV_TVAL Error ---------------------+------------+--------------------+----------------- - 0x000000d4a2d8bfff | 0x10003fff | 0x000000d4b2d8bfff | +0x00004000 - 0x000000d4a2d94000 | 0x0fffffff | 0x000000d4b2d97fff | -0x00004000 - 0x000000d4a2d97fff | 0x10003fff | 0x000000d4b2d97fff | +0x00004000 - 0x000000d4a2d9c000 | 0x0fffffff | 0x000000d4b2d9ffff | -0x00004000 - -The pattern of errors in CNTV_TVAL seemed to depend on exactly which -value was written to it. For example, after writing 0x10101010: - - CNTVCT | CNTV_TVAL | CNTV_CVAL | CNTV_TVAL Error ---------------------+------------+--------------------+----------------- - 0x000001ac3effffff | 0x1110100f | 0x000001ac4f10100f | +0x1000000 - 0x000001ac40000000 | 0x1010100f | 0x000001ac5110100f | -0x1000000 - 0x000001ac58ffffff | 0x1110100f | 0x000001ac6910100f | +0x1000000 - 0x000001ac66000000 | 0x1010100f | 0x000001ac7710100f | -0x1000000 - 0x000001ac6affffff | 0x1110100f | 0x000001ac7b10100f | +0x1000000 - 0x000001ac6e000000 | 0x1010100f | 0x000001ac7f10100f | -0x1000000 - -I was also twice able to reproduce the issue covered by Allwinner's -workaround[4], that writing to TVAL sometimes fails, and both CVAL and -TVAL are left with entirely bogus values. One was the following values: - - CNTVCT | CNTV_TVAL | CNTV_CVAL ---------------------+------------+-------------------------------------- - 0x000000d4a2d6014c | 0x8fbd5721 | 0x000000d132935fff (615s in the past) -Reviewed-by: Marc Zyngier - -======================================================================== - -Because the CPU can read the CNTPCT/CNTVCT registers faster than they -change, performing two reads of the register and comparing the high bits -(like other workarounds) is not a workable solution. And because the -timer can jump both forward and backward, no pair of reads can -distinguish a good value from a bad one. The only way to guarantee a -good value from consecutive reads would be to read _three_ times, and -take the middle value only if the three values are 1) each unique and -2) increasing. This takes at minimum 3 counter cycles (125 ns), or more -if an anomaly is detected. - -However, since there is a distinct pattern to the bad values, we can -optimize the common case (1022/1024 of the time) to a single read by -simply ignoring values that match the error pattern. This still takes no -more than 3 cycles in the worst case, and requires much less code. As an -additional safety check, we still limit the loop iteration to the number -of max-frequency (1.2 GHz) CPU cycles in three 24 MHz counter periods. - -For the TVAL registers, the simple solution is to not use them. Instead, -read or write the CVAL and calculate the TVAL value in software. - -Although the manufacturer is aware of at least part of the erratum[4], -there is no official name for it. For now, use the kernel-internal name -"UNKNOWN1". - -[1]: https://github.com/armbian/build/commit/a08cd6fe7ae9 -[2]: https://forum.armbian.com/topic/3458-a64-datetime-clock-issue/ -[3]: https://irclog.whitequark.org/linux-sunxi/2018-01-26 -[4]: https://github.com/Allwinner-Homlet/H6-BSP4.9-linux/blob/master/drivers/clocksource/arm_arch_timer.c#L272 - -Acked-by: Maxime Ripard -Tested-by: Andre Przywara -Signed-off-by: Samuel Holland -Cc: stable@vger.kernel.org -Signed-off-by: Daniel Lezcano ---- - Documentation/arm64/silicon-errata.txt | 2 + - drivers/clocksource/Kconfig | 10 +++++ - drivers/clocksource/arm_arch_timer.c | 55 ++++++++++++++++++++++++++ - 3 files changed, 67 insertions(+) - ---- a/Documentation/arm64/silicon-errata.txt -+++ b/Documentation/arm64/silicon-errata.txt -@@ -44,6 +44,8 @@ stable kernels. - - | Implementor | Component | Erratum ID | Kconfig | - +----------------+-----------------+-----------------+-----------------------------+ -+| Allwinner | A64/R18 | UNKNOWN1 | SUN50I_ERRATUM_UNKNOWN1 | -+| | | | | - | ARM | Cortex-A53 | #826319 | ARM64_ERRATUM_826319 | - | ARM | Cortex-A53 | #827319 | ARM64_ERRATUM_827319 | - | ARM | Cortex-A53 | #824069 | ARM64_ERRATUM_824069 | ---- a/drivers/clocksource/Kconfig -+++ b/drivers/clocksource/Kconfig -@@ -374,6 +374,16 @@ config ARM64_ERRATUM_858921 - The workaround will be dynamically enabled when an affected - core is detected. - -+config SUN50I_ERRATUM_UNKNOWN1 -+ bool "Workaround for Allwinner A64 erratum UNKNOWN1" -+ default y -+ depends on ARM_ARCH_TIMER && ARM64 && ARCH_SUNXI -+ select ARM_ARCH_TIMER_OOL_WORKAROUND -+ help -+ This option enables a workaround for instability in the timer on -+ the Allwinner A64 SoC. The workaround will only be active if the -+ allwinner,erratum-unknown1 property is found in the timer node. -+ - config ARM_GLOBAL_TIMER - bool "Support for the ARM global timer" if COMPILE_TEST - select TIMER_OF if OF ---- a/drivers/clocksource/arm_arch_timer.c -+++ b/drivers/clocksource/arm_arch_timer.c -@@ -317,6 +317,48 @@ static u64 notrace arm64_858921_read_cnt - } - #endif - -+#ifdef CONFIG_SUN50I_ERRATUM_UNKNOWN1 -+/* -+ * The low bits of the counter registers are indeterminate while bit 10 or -+ * greater is rolling over. Since the counter value can jump both backward -+ * (7ff -> 000 -> 800) and forward (7ff -> fff -> 800), ignore register values -+ * with all ones or all zeros in the low bits. Bound the loop by the maximum -+ * number of CPU cycles in 3 consecutive 24 MHz counter periods. -+ */ -+#define __sun50i_a64_read_reg(reg) ({ \ -+ u64 _val; \ -+ int _retries = 150; \ -+ \ -+ do { \ -+ _val = read_sysreg(reg); \ -+ _retries--; \ -+ } while (((_val + 1) & GENMASK(9, 0)) <= 1 && _retries); \ -+ \ -+ WARN_ON_ONCE(!_retries); \ -+ _val; \ -+}) -+ -+static u64 notrace sun50i_a64_read_cntpct_el0(void) -+{ -+ return __sun50i_a64_read_reg(cntpct_el0); -+} -+ -+static u64 notrace sun50i_a64_read_cntvct_el0(void) -+{ -+ return __sun50i_a64_read_reg(cntvct_el0); -+} -+ -+static u32 notrace sun50i_a64_read_cntp_tval_el0(void) -+{ -+ return read_sysreg(cntp_cval_el0) - sun50i_a64_read_cntpct_el0(); -+} -+ -+static u32 notrace sun50i_a64_read_cntv_tval_el0(void) -+{ -+ return read_sysreg(cntv_cval_el0) - sun50i_a64_read_cntvct_el0(); -+} -+#endif -+ - #ifdef CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND - DEFINE_PER_CPU(const struct arch_timer_erratum_workaround *, - timer_unstable_counter_workaround); -@@ -404,6 +446,19 @@ static const struct arch_timer_erratum_w - .read_cntvct_el0 = arm64_858921_read_cntvct_el0, - }, - #endif -+#ifdef CONFIG_SUN50I_ERRATUM_UNKNOWN1 -+ { -+ .match_type = ate_match_dt, -+ .id = "allwinner,erratum-unknown1", -+ .desc = "Allwinner erratum UNKNOWN1", -+ .read_cntp_tval_el0 = sun50i_a64_read_cntp_tval_el0, -+ .read_cntv_tval_el0 = sun50i_a64_read_cntv_tval_el0, -+ .read_cntpct_el0 = sun50i_a64_read_cntpct_el0, -+ .read_cntvct_el0 = sun50i_a64_read_cntvct_el0, -+ .set_next_event_phys = erratum_set_next_event_tval_phys, -+ .set_next_event_virt = erratum_set_next_event_tval_virt, -+ }, -+#endif - }; - - typedef bool (*ate_match_fn_t)(const struct arch_timer_erratum_workaround *, diff --git a/target/linux/sunxi/patches-4.14/101-arm64-dts-allwinner-a64-Enable-A64-timer-workaround.patch b/target/linux/sunxi/patches-4.14/101-arm64-dts-allwinner-a64-Enable-A64-timer-workaround.patch deleted file mode 100644 index 5bfd33b944ac..000000000000 --- a/target/linux/sunxi/patches-4.14/101-arm64-dts-allwinner-a64-Enable-A64-timer-workaround.patch +++ /dev/null @@ -1,26 +0,0 @@ -From 55ec26d6a4241363fa94f15377ebd8f1116fbfd7 Mon Sep 17 00:00:00 2001 -From: Samuel Holland -Date: Sat, 12 Jan 2019 20:17:19 -0600 -Subject: [PATCH] arm64: dts: allwinner: a64: Enable A64 timer workaround - -As instability in the architectural timer has been observed on multiple -devices using this SoC, inluding the Pine64 and the Orange Pi Win, -enable the workaround in the SoC's device tree. - -Acked-by: Maxime Ripard -Signed-off-by: Samuel Holland -Signed-off-by: Chen-Yu Tsai ---- - arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 1 + - 1 file changed, 1 insertion(+) - ---- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi -+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi -@@ -114,6 +114,7 @@ - - timer { - compatible = "arm,armv8-timer"; -+ allwinner,erratum-unknown1; - interrupts = , - -Date: Thu, 28 Dec 2017 21:01:56 +0800 -Subject: [PATCH] ARM: dts: sun8i: fix USB Ethernet of Orange Pi R1 - -Orange Pi R1 uses a Realtek RTL8152B USB Ethernet chip, which is easily -seen on the board but not show in the schematics. A regulator for the -power of the RTL8152B chip is hidden, which uses the same pin with the -Wi-Fi regulator on the original Orange Pi Zero. - -Add this regulator back to the device tree, and bind it to USB1. - -Signed-off-by: Icenowy Zheng ---- - arch/arm/boot/dts/sun8i-h2-plus-orangepi-r1.dts | 18 ++++++++++++++++++ - 1 file changed, 18 insertions(+) - ---- a/arch/arm/boot/dts/sun8i-h2-plus-orangepi-r1.dts -+++ b/arch/arm/boot/dts/sun8i-h2-plus-orangepi-r1.dts -@@ -49,6 +49,20 @@ - - /delete-node/ reg_vcc_wifi; - -+ /* -+ * Ths pin of this regulator is the same with the Wi-Fi extra -+ * regulator on the original Zero. However it's used for USB -+ * Ethernet rather than the Wi-Fi now. -+ */ -+ reg_vcc_usb_eth: reg-vcc-usb-ethernet { -+ compatible = "regulator-fixed"; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ regulator-name = "vcc-usb-ethernet"; -+ enable-active-high; -+ gpio = <&pio 0 20 GPIO_ACTIVE_HIGH>; -+ }; -+ - aliases { - ethernet1 = &rtl8189etv; - }; -@@ -71,3 +85,7 @@ - reg = <1>; - }; - }; -+ -+&usbphy { -+ usb1_vbus-supply = <®_vcc_usb_eth>; -+}; diff --git a/target/linux/sunxi/patches-4.14/202-ARM-dts-sun8i-activate-SPI-on-Orange-Pi-R1.patch b/target/linux/sunxi/patches-4.14/202-ARM-dts-sun8i-activate-SPI-on-Orange-Pi-R1.patch deleted file mode 100644 index 3f03c1163c3d..000000000000 --- a/target/linux/sunxi/patches-4.14/202-ARM-dts-sun8i-activate-SPI-on-Orange-Pi-R1.patch +++ /dev/null @@ -1,29 +0,0 @@ -From 4a36ec1f82db3fa34d766dec5062b4de06b50f7f Mon Sep 17 00:00:00 2001 -From: Hauke Mehrtens -Date: Thu, 28 Dec 2017 14:11:36 +0100 -Subject: [PATCH] ARM: dts: sun8i: activate SPI on Orange Pi R1 - -This board has a SPI flash, activate it also in device tree by default. - -Signed-off-by: Hauke Mehrtens ---- - arch/arm/boot/dts/sun8i-h2-plus-orangepi-r1.dts | 4 ++++ - 1 file changed, 4 insertions(+) - ---- a/arch/arm/boot/dts/sun8i-h2-plus-orangepi-r1.dts -+++ b/arch/arm/boot/dts/sun8i-h2-plus-orangepi-r1.dts -@@ -68,6 +68,14 @@ - }; - }; - -+&spi0 { -+ status = "okay"; -+ -+ flash@0 { -+ compatible = "mxicy,mx25l12805d", "jedec,spi-nor"; -+ }; -+}; -+ - &ohci1 { - /* - * RTL8152B USB-Ethernet adapter is connected to USB1, diff --git a/target/linux/sunxi/patches-4.14/220-ARM-dts-orange-pi-zero-plus.patch b/target/linux/sunxi/patches-4.14/220-ARM-dts-orange-pi-zero-plus.patch deleted file mode 100644 index 2eedb915ddbd..000000000000 --- a/target/linux/sunxi/patches-4.14/220-ARM-dts-orange-pi-zero-plus.patch +++ /dev/null @@ -1,185 +0,0 @@ -From 0e2da1a792a21e3933e17727920ed3c35a3ba57a Mon Sep 17 00:00:00 2001 -From: Hauke Mehrtens -Date: Sun, 11 Mar 2018 15:13:30 +0100 -Subject: [PATCH] arm64: allwinner: H5: Add Xunlong Orange Pi Zero Plus - -The Xunlong Orange Pi Zero Plus is single board computer. -- H5 Quad-core 64-bit Cortex-A53 -- 512MB DDR3 -- microSD slot -- Debug TTL UART -- 1000M/100M/10M Ethernet RJ45 -- Realtek RTL8189FTV -- Spi flash (2MB) -- One USB 2.0 HOST, One USB 2.0 OTG - -This is based on a patch from armbian: -https://github.com/armbian/build/blob/master/patch/kernel/sunxi-next/sunxi-add-orangepi-zero-plus.patch - -Signed-off-by: Hauke Mehrtens ---- - arch/arm64/boot/dts/allwinner/Makefile | 1 + - .../dts/allwinner/sun50i-h5-orangepi-zero-plus.dts | 147 +++++++++++++++++++++ - 2 files changed, 148 insertions(+) - create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-zero-plus.dts - ---- a/arch/arm64/boot/dts/allwinner/Makefile -+++ b/arch/arm64/boot/dts/allwinner/Makefile -@@ -7,6 +7,7 @@ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-p - dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-sopine-baseboard.dtb - dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-orangepi-pc2.dtb - dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-orangepi-prime.dtb -+dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-orangepi-zero-plus.dtb - dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-orangepi-zero-plus2.dtb - dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-nanopi-neo2.dtb - dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-nanopi-neo-plus2.dtb ---- /dev/null -+++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-zero-plus.dts -@@ -0,0 +1,147 @@ -+/* -+ * Copyright (C) 2016 ARM Ltd. -+ * Copyright (C) 2018 Hauke Mehrtens -+ * -+ * SPDX-License-Identifier: (GPL-2.0+ OR X11) -+ */ -+ -+/dts-v1/; -+#include "sun50i-h5.dtsi" -+ -+#include -+#include -+#include -+ -+/ { -+ model = "Xunlong Orange Pi Zero Plus"; -+ compatible = "xunlong,orangepi-zero-plus", "allwinner,sun50i-h5"; -+ -+ reg_vcc3v3: vcc3v3 { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc3v3"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ }; -+ -+ aliases { -+ ethernet0 = &emac; -+ ethernet1 = &rtl8189ftv; -+ serial0 = &uart0; -+ }; -+ -+ chosen { -+ stdout-path = "serial0:115200n8"; -+ }; -+ -+ leds { -+ compatible = "gpio-leds"; -+ -+ pwr { -+ label = "orangepi:green:pwr"; -+ gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; /* PA10 */ -+ default-state = "on"; -+ }; -+ -+ status { -+ label = "orangepi:red:status"; -+ gpios = <&pio 0 17 GPIO_ACTIVE_HIGH>; /* PA17 */ -+ }; -+ }; -+ -+ reg_gmac_3v3: gmac-3v3 { -+ compatible = "regulator-fixed"; -+ regulator-name = "gmac-3v3"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ startup-delay-us = <100000>; -+ enable-active-high; -+ gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>; /* PD6 */ -+ }; -+}; -+ -+&ehci0 { -+ status = "okay"; -+}; -+ -+&ehci1 { -+ status = "okay"; -+}; -+ -+&emac { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&emac_rgmii_pins>; -+ phy-supply = <®_gmac_3v3>; -+ phy-handle = <&ext_rgmii_phy>; -+ phy-mode = "rgmii"; -+ status = "okay"; -+}; -+ -+&external_mdio { -+ ext_rgmii_phy: ethernet-phy@1 { -+ compatible = "ethernet-phy-ieee802.3-c22"; -+ reg = <1>; -+ }; -+}; -+ -+&mmc0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&mmc0_pins_a>; -+ vmmc-supply = <®_vcc3v3>; -+ bus-width = <4>; -+ cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ -+ status = "okay"; -+}; -+ -+&mmc1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&mmc1_pins_a>; -+ vmmc-supply = <®_vcc3v3>; -+ bus-width = <4>; -+ non-removable; -+ status = "okay"; -+ -+ /* -+ * Explicitly define the sdio device, so that we can add an ethernet -+ * alias for it (which e.g. makes u-boot set a mac-address). -+ */ -+ rtl8189ftv: sdio_wifi@1 { -+ reg = <1>; -+ }; -+}; -+ -+&spi0 { -+ status = "okay"; -+ -+ flash@0 { -+ #address-cells = <1>; -+ #size-cells = <1>; -+ compatible = "mxicy,mx25l1606e", "winbond,w25q128"; -+ reg = <0>; -+ spi-max-frequency = <40000000>; -+ }; -+}; -+ -+&ohci0 { -+ status = "okay"; -+}; -+ -+&ohci1 { -+ status = "okay"; -+}; -+ -+&uart0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&uart0_pins_a>; -+ status = "okay"; -+}; -+ -+&usb_otg { -+ dr_mode = "peripheral"; -+ status = "okay"; -+}; -+ -+&usbphy { -+ /* USB Type-A ports' VBUS is always on */ -+ usb0_id_det-gpios = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */ -+ status = "okay"; -+}; diff --git a/target/linux/sunxi/patches-4.14/301-orangepi_pc2_usb_otg_to_host_key_power.patch b/target/linux/sunxi/patches-4.14/301-orangepi_pc2_usb_otg_to_host_key_power.patch deleted file mode 100644 index d8693374d2ef..000000000000 --- a/target/linux/sunxi/patches-4.14/301-orangepi_pc2_usb_otg_to_host_key_power.patch +++ /dev/null @@ -1,20 +0,0 @@ ---- a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts -+++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts -@@ -87,7 +87,7 @@ - - sw4 { - label = "sw4"; -- linux,code = ; -+ linux,code = ; - gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; - }; - }; -@@ -203,7 +203,7 @@ - }; - - &usb_otg { -- dr_mode = "otg"; -+ dr_mode = "host"; - status = "okay"; - }; - diff --git a/target/linux/sunxi/patches-4.14/310-Revert-ARM-dts-sun7i-Add-BCM53125-switch-nodes-to-th.patch b/target/linux/sunxi/patches-4.14/310-Revert-ARM-dts-sun7i-Add-BCM53125-switch-nodes-to-th.patch deleted file mode 100644 index 3f8a3418a998..000000000000 --- a/target/linux/sunxi/patches-4.14/310-Revert-ARM-dts-sun7i-Add-BCM53125-switch-nodes-to-th.patch +++ /dev/null @@ -1,88 +0,0 @@ -From 49cd9ea6dc8d68eb519ccd9f31c9730dec8a181a Mon Sep 17 00:00:00 2001 -From: Hauke Mehrtens -Date: Thu, 8 Mar 2018 22:14:50 +0100 -Subject: [PATCH] Revert "ARM: dts: sun7i: Add BCM53125 switch nodes to the - lamobo-r1 board" - -This reverts the changes needed for the upstream b53 DSA switch driver -to use the OpenWrt b43 swconfig switch driver. - -This reverts commit 0cdefd5b5485ee6eb3512a75739d09a4090176ed. -This reverts commit d7b9eaff5f0ca00726336b4c0c3c29decf30412a. ---- - arch/arm/boot/dts/sun7i-a20-lamobo-r1.dts | 60 ++----------------------------- - 1 file changed, 3 insertions(+), 57 deletions(-) - ---- a/arch/arm/boot/dts/sun7i-a20-lamobo-r1.dts -+++ b/arch/arm/boot/dts/sun7i-a20-lamobo-r1.dts -@@ -109,67 +109,13 @@ - &gmac { - pinctrl-names = "default"; - pinctrl-0 = <&gmac_pins_rgmii_a>; -+ phy = <&phy1>; - phy-mode = "rgmii"; - phy-supply = <®_gmac_3v3>; - status = "okay"; - -- fixed-link { -- speed = <1000>; -- full-duplex; -- }; -- -- mdio { -- compatible = "snps,dwmac-mdio"; -- #address-cells = <1>; -- #size-cells = <0>; -- -- switch: ethernet-switch@1e { -- compatible = "brcm,bcm53125"; -- reg = <30>; -- #address-cells = <1>; -- #size-cells = <0>; -- -- ports { -- #address-cells = <1>; -- #size-cells = <0>; -- -- port0: port@0 { -- reg = <0>; -- label = "lan2"; -- }; -- -- port1: port@1 { -- reg = <1>; -- label = "lan3"; -- }; -- -- port2: port@2 { -- reg = <2>; -- label = "lan4"; -- }; -- -- port3: port@3 { -- reg = <3>; -- label = "wan"; -- }; -- -- port4: port@4 { -- reg = <4>; -- label = "lan1"; -- }; -- -- port8: port@8 { -- reg = <8>; -- label = "cpu"; -- ethernet = <&gmac>; -- phy-mode = "rgmii-txid"; -- fixed-link { -- speed = <1000>; -- full-duplex; -- }; -- }; -- }; -- }; -+ phy1: ethernet-phy@1 { -+ reg = <1>; - }; - }; - diff --git a/target/linux/sunxi/patches-4.14/400-arm64-allwinner-a64-sopine-Add-Sopine-flash-partitio.patch b/target/linux/sunxi/patches-4.14/400-arm64-allwinner-a64-sopine-Add-Sopine-flash-partitio.patch deleted file mode 100644 index 0d8ec4cec0e2..000000000000 --- a/target/linux/sunxi/patches-4.14/400-arm64-allwinner-a64-sopine-Add-Sopine-flash-partitio.patch +++ /dev/null @@ -1,46 +0,0 @@ -From 7d87d3dafc4b1ea5659eb71ee6c5fd5308490d1f Mon Sep 17 00:00:00 2001 -From: Oskari Lemmela -Date: Mon, 31 Dec 2018 07:44:49 +0200 -Subject: [PATCH] arm64: allwinner: a64-sopine: Add Sopine flash partitions. - -First 896kB to u-boot. Enough space for SPL, u-boot and ATF. -Next 128kB to u-boot environment and rest to firmware. - -Firmware partition is compatible FIT image dynamic splitting. - -Signed-off-by: Oskari Lemmela ---- - .../boot/dts/allwinner/sun50i-a64-sopine.dtsi | 22 +++++++++++++++++++ - 1 file changed, 22 insertions(+) - ---- a/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine.dtsi -+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine.dtsi -@@ -84,6 +84,28 @@ - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <40000000>; -+ -+ partitions { -+ compatible = "fixed-partitions"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ -+ partition@0 { -+ label = "u-boot"; -+ reg = <0x000000 0x0E0000>; -+ }; -+ -+ partition@e0000 { -+ label = "u-boot-env"; -+ reg = <0x0E0000 0x020000>; -+ }; -+ -+ partition@100000 { -+ compatible = "denx,fit"; -+ label = "firmware"; -+ reg = <0x100000 0xF00000>; -+ }; -+ }; - }; - }; - From patchwork Sun Mar 1 12:12:40 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hauke Mehrtens X-Patchwork-Id: 1247290 X-Patchwork-Delegate: hauke@hauke-m.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; 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Sun, 01 Mar 2020 12:19:16 +0000 Received: from smtp2.mailbox.org (smtp2.mailbox.org [IPv6:2001:67c:2050:105:465:1:2:0]) (using TLSv1.2 with cipher ECDHE-RSA-CHACHA20-POLY1305 (256/256 bits)) (No client certificate requested) by mout-p-103.mailbox.org (Postfix) with ESMTPS id 48VhxQ4VH4zKmf8; Sun, 1 Mar 2020 13:12:58 +0100 (CET) X-Virus-Scanned: amavisd-new at heinlein-support.de Received: from smtp2.mailbox.org ([80.241.60.241]) by spamfilter04.heinlein-hosting.de (spamfilter04.heinlein-hosting.de [80.241.56.122]) (amavisd-new, port 10030) with ESMTP id kH3FXvCz9jWO; Sun, 1 Mar 2020 13:12:53 +0100 (CET) From: Hauke Mehrtens To: openwrt-devel@lists.openwrt.org Date: Sun, 1 Mar 2020 13:12:40 +0100 Message-Id: <20200301121241.5545-12-hauke@hauke-m.de> In-Reply-To: <20200301121241.5545-1-hauke@hauke-m.de> References: <20200301121241.5545-1-hauke@hauke-m.de> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200301_041914_166583_F5EC6838 X-CRM114-Status: GOOD ( 10.78 ) X-Spam-Score: 0.8 (/) X-Spam-Report: SpamAssassin version 3.4.3 on bombadil.infradead.org summary: Content analysis details: (0.8 points) pts rule name description ---- ---------------------- -------------------------------------------------- 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.0 SPF_PASS SPF: sender matches SPF record 0.8 UPPERCASE_50_75 message body is 50-75% uppercase Subject: [OpenWrt-Devel] [PATCH 11/12] tegra: Remove kernel 4.14 support X-BeenThere: openwrt-devel@lists.openwrt.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: hauke@hauke-m.de Sender: "openwrt-devel" Errors-To: openwrt-devel-bounces+incoming=patchwork.ozlabs.org@lists.openwrt.org This target was switched to kernel 4.19 more than 6 months ago in commit f342ffd300da ("treewide: kernel: bump some targets to 4.19") and now with kernel 5.4 support being added it gets harder to support kernel 4.14 in addition to kernel 4.19 and 5.4. Signed-off-by: Hauke Mehrtens --- target/linux/tegra/config-4.14 | 558 ------------------ ...interrupts-due-to-tegra2-silicon-bug.patch | 77 --- ...enable-front-panel-leds-in-TrimSlice.patch | 46 -- 3 files changed, 681 deletions(-) delete mode 100644 target/linux/tegra/config-4.14 delete mode 100644 target/linux/tegra/patches-4.14/100-serial8250-on-tegra-hsuart-recover-from-spurious-interrupts-due-to-tegra2-silicon-bug.patch delete mode 100644 target/linux/tegra/patches-4.14/101-ARM-dtc-tegra-enable-front-panel-leds-in-TrimSlice.patch diff --git a/target/linux/tegra/config-4.14 b/target/linux/tegra/config-4.14 deleted file mode 100644 index 42547da301ea..000000000000 --- a/target/linux/tegra/config-4.14 +++ /dev/null @@ -1,558 +0,0 @@ -CONFIG_AC97_BUS=y -# CONFIG_AHCI_TEGRA is not set -CONFIG_ALIGNMENT_TRAP=y -CONFIG_ARCH_CLOCKSOURCE_DATA=y -CONFIG_ARCH_HAS_DEBUG_VIRTUAL=y -CONFIG_ARCH_HAS_ELF_RANDOMIZE=y -CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y -CONFIG_ARCH_HAS_RESET_CONTROLLER=y -CONFIG_ARCH_HAS_SET_MEMORY=y -CONFIG_ARCH_HAS_SG_CHAIN=y -CONFIG_ARCH_HAS_STRICT_KERNEL_RWX=y -CONFIG_ARCH_HAS_STRICT_MODULE_RWX=y -CONFIG_ARCH_HAS_TICK_BROADCAST=y -CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y -CONFIG_ARCH_HIBERNATION_POSSIBLE=y -CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y -CONFIG_ARCH_MULTIPLATFORM=y -# CONFIG_ARCH_MULTI_CPU_AUTO is not set -CONFIG_ARCH_MULTI_V6_V7=y -CONFIG_ARCH_MULTI_V7=y -CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED=y -CONFIG_ARCH_NR_GPIO=1024 -CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y -CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y -# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set -# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set -CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y -CONFIG_ARCH_SUPPORTS_FIRMWARE=y -CONFIG_ARCH_SUPPORTS_TRUSTED_FOUNDATIONS=y -CONFIG_ARCH_SUPPORTS_UPROBES=y -CONFIG_ARCH_SUSPEND_POSSIBLE=y -CONFIG_ARCH_TEGRA=y -# CONFIG_ARCH_TEGRA_114_SOC is not set -# CONFIG_ARCH_TEGRA_124_SOC is not set -CONFIG_ARCH_TEGRA_2x_SOC=y -# CONFIG_ARCH_TEGRA_3x_SOC is not set -CONFIG_ARCH_USE_BUILTIN_BSWAP=y -CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y -CONFIG_ARCH_WANT_GENERAL_HUGETLB=y -CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y -CONFIG_ARM=y -CONFIG_ARM_AMBA=y -CONFIG_ARM_ARCH_TIMER=y -CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y -CONFIG_ARM_CPU_SUSPEND=y -CONFIG_ARM_CRYPTO=y -CONFIG_ARM_ERRATA_720789=y -CONFIG_ARM_ERRATA_754327=y -CONFIG_ARM_ERRATA_764369=y -CONFIG_ARM_GIC=y -CONFIG_ARM_HAS_SG_CHAIN=y -CONFIG_ARM_HEAVY_MB=y -CONFIG_ARM_L1_CACHE_SHIFT=6 -CONFIG_ARM_L1_CACHE_SHIFT_6=y -# CONFIG_ARM_LPAE is not set -CONFIG_ARM_PATCH_IDIV=y -CONFIG_ARM_PATCH_PHYS_VIRT=y -# CONFIG_ARM_PL172_MPMC is not set -# CONFIG_ARM_SMMU is not set -# CONFIG_ARM_SP805_WATCHDOG is not set -CONFIG_ARM_TEGRA20_CPUFREQ=y -CONFIG_ARM_THUMB=y -CONFIG_ARM_THUMBEE=y -CONFIG_ARM_VIRT_EXT=y -CONFIG_ASN1=y -CONFIG_ATA=y -CONFIG_ATAGS=y -CONFIG_AUTO_ZRELADDR=y -CONFIG_BLK_DEV_BSG=y -CONFIG_BLK_DEV_LOOP=y -CONFIG_BLK_MQ_PCI=y -CONFIG_BLK_SCSI_REQUEST=y -CONFIG_BOUNCE=y -CONFIG_CACHE_L2X0=y -CONFIG_CLKDEV_LOOKUP=y -CONFIG_CLKSRC_MMIO=y -CONFIG_CLONE_BACKWARDS=y -CONFIG_CLZ_TAB=y -CONFIG_CMA=y -CONFIG_CMA_ALIGNMENT=8 -CONFIG_CMA_AREAS=7 -# CONFIG_CMA_DEBUG is not set -# CONFIG_CMA_DEBUGFS is not set -CONFIG_CMA_SIZE_MBYTES=16 -# CONFIG_CMA_SIZE_SEL_MAX is not set -CONFIG_CMA_SIZE_SEL_MBYTES=y -# CONFIG_CMA_SIZE_SEL_MIN is not set -# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set -CONFIG_COMMON_CLK=y -# CONFIG_CPUFREQ_DT is not set -CONFIG_CPU_32v6K=y -CONFIG_CPU_32v7=y -CONFIG_CPU_ABRT_EV7=y -# CONFIG_CPU_BPREDICT_DISABLE is not set -CONFIG_CPU_CACHE_V7=y -CONFIG_CPU_CACHE_VIPT=y -CONFIG_CPU_COPY_V6=y -CONFIG_CPU_CP15=y -CONFIG_CPU_CP15_MMU=y -CONFIG_CPU_FREQ=y -CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y -# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set -CONFIG_CPU_FREQ_GOV_ATTR_SET=y -CONFIG_CPU_FREQ_GOV_COMMON=y -CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y -CONFIG_CPU_FREQ_GOV_ONDEMAND=y -CONFIG_CPU_FREQ_GOV_PERFORMANCE=y -CONFIG_CPU_FREQ_GOV_POWERSAVE=y -CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y -CONFIG_CPU_FREQ_GOV_USERSPACE=y -# CONFIG_CPU_FREQ_STAT is not set -CONFIG_CPU_HAS_ASID=y -# CONFIG_CPU_HOTPLUG_STATE_CONTROL is not set -# CONFIG_CPU_ICACHE_DISABLE is not set -CONFIG_CPU_IDLE=y -CONFIG_CPU_IDLE_GOV_LADDER=y -CONFIG_CPU_PABRT_V7=y -CONFIG_CPU_PM=y -CONFIG_CPU_RMAP=y -CONFIG_CPU_SPECTRE=y -CONFIG_CPU_THUMB_CAPABLE=y -CONFIG_CPU_TLB_V7=y -CONFIG_CPU_V7=y -CONFIG_CRC16=y -# CONFIG_CRC32_SARWATE is not set -CONFIG_CRC32_SLICEBY8=y -CONFIG_CROSS_MEMORY_ATTACH=y -CONFIG_CRYPTO_ACOMP2=y -CONFIG_CRYPTO_AEAD=y -CONFIG_CRYPTO_AEAD2=y -CONFIG_CRYPTO_AES_ARM=y -CONFIG_CRYPTO_AKCIPHER=y -CONFIG_CRYPTO_AKCIPHER2=y -CONFIG_CRYPTO_CRC32=y -CONFIG_CRYPTO_CRC32C=y -CONFIG_CRYPTO_CRYPTD=y -CONFIG_CRYPTO_DEFLATE=y -CONFIG_CRYPTO_DRBG=y -CONFIG_CRYPTO_DRBG_HMAC=y -CONFIG_CRYPTO_DRBG_MENU=y -CONFIG_CRYPTO_ECHAINIV=y -CONFIG_CRYPTO_HASH=y -CONFIG_CRYPTO_HASH2=y -CONFIG_CRYPTO_HMAC=y -CONFIG_CRYPTO_JITTERENTROPY=y -CONFIG_CRYPTO_LZ4=y -CONFIG_CRYPTO_LZ4HC=y -CONFIG_CRYPTO_LZO=y -CONFIG_CRYPTO_MANAGER=y -CONFIG_CRYPTO_MANAGER2=y -CONFIG_CRYPTO_NULL=y -CONFIG_CRYPTO_NULL2=y -CONFIG_CRYPTO_RNG=y -CONFIG_CRYPTO_RNG2=y -CONFIG_CRYPTO_RNG_DEFAULT=y -CONFIG_CRYPTO_RSA=y -CONFIG_CRYPTO_SEQIV=y -CONFIG_CRYPTO_SHA1=y -CONFIG_CRYPTO_SHA1_ARM=y -CONFIG_CRYPTO_SHA256=y -CONFIG_CRYPTO_SHA256_ARM=y -CONFIG_CRYPTO_SHA512_ARM=y -CONFIG_CRYPTO_TWOFISH=y -CONFIG_CRYPTO_TWOFISH_COMMON=y -CONFIG_CRYPTO_WORKQUEUE=y -CONFIG_DCACHE_WORD_ACCESS=y -CONFIG_DEBUG_ALIGN_RODATA=y -CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" -# CONFIG_DEBUG_UART_8250 is not set -# CONFIG_DEBUG_USER is not set -# CONFIG_DEVPORT is not set -CONFIG_DMADEVICES=y -CONFIG_DMA_CMA=y -CONFIG_DMA_ENGINE=y -CONFIG_DMA_OF=y -CONFIG_DMA_SHARED_BUFFER=y -CONFIG_DNOTIFY=y -CONFIG_DRM=y -CONFIG_DRM_BRIDGE=y -CONFIG_DRM_FBDEV_EMULATION=y -CONFIG_DRM_FBDEV_OVERALLOC=100 -CONFIG_DRM_KMS_FB_HELPER=y -CONFIG_DRM_KMS_HELPER=y -CONFIG_DRM_MIPI_DSI=y -CONFIG_DRM_PANEL=y -CONFIG_DRM_PANEL_BRIDGE=y -CONFIG_DRM_TEGRA=y -# CONFIG_DRM_TEGRA_DEBUG is not set -# CONFIG_DRM_TEGRA_STAGING is not set -CONFIG_DTC=y -CONFIG_EDAC_ATOMIC_SCRUB=y -CONFIG_EDAC_SUPPORT=y -CONFIG_ENABLE_MUST_CHECK=y -CONFIG_EXT4_FS=y -CONFIG_EXTCON=y -# CONFIG_F2FS_CHECK_FS is not set -CONFIG_F2FS_FS=y -# CONFIG_F2FS_FS_SECURITY is not set -CONFIG_F2FS_FS_XATTR=y -CONFIG_F2FS_STAT_FS=y -CONFIG_FB=y -CONFIG_FB_CFB_COPYAREA=y -CONFIG_FB_CFB_FILLRECT=y -CONFIG_FB_CFB_IMAGEBLIT=y -CONFIG_FB_CMDLINE=y -CONFIG_FB_DEFERRED_IO=y -# CONFIG_FB_PROVIDE_GET_FB_UNMAPPED_AREA is not set -CONFIG_FB_SYS_COPYAREA=y -CONFIG_FB_SYS_FILLRECT=y -CONFIG_FB_SYS_FOPS=y -CONFIG_FB_SYS_IMAGEBLIT=y -CONFIG_FIX_EARLYCON_MEM=y -CONFIG_FRAME_POINTER=y -CONFIG_FREEZER=y -CONFIG_FS_MBCACHE=y -CONFIG_GENERIC_ALLOCATOR=y -CONFIG_GENERIC_ARCH_TOPOLOGY=y -CONFIG_GENERIC_BUG=y -CONFIG_GENERIC_CLOCKEVENTS=y -CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y -CONFIG_GENERIC_CPU_AUTOPROBE=y -CONFIG_GENERIC_EARLY_IOREMAP=y -CONFIG_GENERIC_IDLE_POLL_SETUP=y -CONFIG_GENERIC_IO=y -CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y -CONFIG_GENERIC_IRQ_MIGRATION=y -CONFIG_GENERIC_IRQ_SHOW=y -CONFIG_GENERIC_IRQ_SHOW_LEVEL=y -CONFIG_GENERIC_MSI_IRQ=y -CONFIG_GENERIC_MSI_IRQ_DOMAIN=y -CONFIG_GENERIC_PCI_IOMAP=y -CONFIG_GENERIC_PHY=y -CONFIG_GENERIC_PINCONF=y -CONFIG_GENERIC_PINCTRL_GROUPS=y -CONFIG_GENERIC_PINMUX_FUNCTIONS=y -CONFIG_GENERIC_SCHED_CLOCK=y -CONFIG_GENERIC_SMP_IDLE_THREAD=y -CONFIG_GENERIC_STRNCPY_FROM_USER=y -CONFIG_GENERIC_STRNLEN_USER=y -CONFIG_GENERIC_TIME_VSYSCALL=y -CONFIG_GLOB=y -CONFIG_GPIOLIB=y -CONFIG_GPIO_SYSFS=y -CONFIG_GPIO_TEGRA=y -# CONFIG_GRO_CELLS is not set -CONFIG_HANDLE_DOMAIN_IRQ=y -CONFIG_HARDEN_BRANCH_PREDICTOR=y -CONFIG_HARDIRQS_SW_RESEND=y -CONFIG_HAS_DMA=y -CONFIG_HAS_IOMEM=y -CONFIG_HAS_IOPORT_MAP=y -# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set -CONFIG_HAVE_ARCH_AUDITSYSCALL=y -CONFIG_HAVE_ARCH_BITREVERSE=y -CONFIG_HAVE_ARCH_JUMP_LABEL=y -CONFIG_HAVE_ARCH_KGDB=y -CONFIG_HAVE_ARCH_PFN_VALID=y -CONFIG_HAVE_ARCH_SECCOMP_FILTER=y -CONFIG_HAVE_ARCH_TRACEHOOK=y -CONFIG_HAVE_ARM_ARCH_TIMER=y -CONFIG_HAVE_ARM_SCU=y -CONFIG_HAVE_ARM_SMCCC=y -CONFIG_HAVE_ARM_TWD=y -# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set -CONFIG_HAVE_CC_STACKPROTECTOR=y -CONFIG_HAVE_CLK=y -CONFIG_HAVE_CLK_PREPARE=y -CONFIG_HAVE_CONTEXT_TRACKING=y -CONFIG_HAVE_C_RECORDMCOUNT=y -CONFIG_HAVE_DEBUG_KMEMLEAK=y -CONFIG_HAVE_DMA_API_DEBUG=y -CONFIG_HAVE_DMA_CONTIGUOUS=y -CONFIG_HAVE_DYNAMIC_FTRACE=y -CONFIG_HAVE_DYNAMIC_FTRACE_WITH_REGS=y -CONFIG_HAVE_EBPF_JIT=y -CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y -CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y -CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y -CONFIG_HAVE_FUNCTION_TRACER=y -CONFIG_HAVE_GENERIC_DMA_COHERENT=y -CONFIG_HAVE_IDE=y -CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y -CONFIG_HAVE_MEMBLOCK=y -CONFIG_HAVE_MOD_ARCH_SPECIFIC=y -CONFIG_HAVE_NET_DSA=y -CONFIG_HAVE_OPROFILE=y -CONFIG_HAVE_OPTPROBES=y -CONFIG_HAVE_PERF_EVENTS=y -CONFIG_HAVE_PERF_REGS=y -CONFIG_HAVE_PERF_USER_STACK_DUMP=y -CONFIG_HAVE_PROC_CPU=y -CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y -CONFIG_HAVE_SMP=y -CONFIG_HAVE_SYSCALL_TRACEPOINTS=y -CONFIG_HAVE_UID16=y -CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y -CONFIG_HDMI=y -CONFIG_HID=y -CONFIG_HIDRAW=y -CONFIG_HID_GENERIC=y -CONFIG_HIGHMEM=y -CONFIG_HIGHPTE=y -CONFIG_HOTPLUG_CPU=y -CONFIG_HWMON=y -CONFIG_HZ_FIXED=0 -CONFIG_HZ_PERIODIC=y -CONFIG_I2C=y -CONFIG_I2C_ALGOBIT=y -CONFIG_I2C_BOARDINFO=y -CONFIG_I2C_COMPAT=y -CONFIG_I2C_TEGRA=y -CONFIG_INITRAMFS_SOURCE="" -CONFIG_INPUT=y -CONFIG_INPUT_KEYBOARD=y -CONFIG_IOMMU_API=y -CONFIG_IOMMU_HELPER=y -CONFIG_IOMMU_IOVA=y -# CONFIG_IOMMU_IO_PGTABLE_ARMV7S is not set -# CONFIG_IOMMU_IO_PGTABLE_LPAE is not set -CONFIG_IOMMU_SUPPORT=y -CONFIG_IRQCHIP=y -CONFIG_IRQ_DOMAIN=y -CONFIG_IRQ_DOMAIN_HIERARCHY=y -CONFIG_IRQ_FORCED_THREADING=y -CONFIG_IRQ_WORK=y -CONFIG_JBD2=y -CONFIG_KEYBOARD_ATKBD=y -CONFIG_LIBFDT=y -CONFIG_LOCK_SPIN_ON_OWNER=y -CONFIG_LZ4HC_COMPRESS=y -CONFIG_LZ4_COMPRESS=y -CONFIG_LZ4_DECOMPRESS=y -CONFIG_LZO_COMPRESS=y -CONFIG_LZO_DECOMPRESS=y -# CONFIG_MDIO_BUS is not set -CONFIG_MEMORY=y -CONFIG_MEMORY_ISOLATION=y -# CONFIG_MFD_NVEC is not set -CONFIG_MIGHT_HAVE_CACHE_L2X0=y -CONFIG_MIGHT_HAVE_PCI=y -CONFIG_MIGRATION=y -CONFIG_MMC=y -CONFIG_MMC_BLOCK=y -CONFIG_MMC_SDHCI=y -CONFIG_MMC_SDHCI_IO_ACCESSORS=y -# CONFIG_MMC_SDHCI_PCI is not set -CONFIG_MMC_SDHCI_PLTFM=y -CONFIG_MMC_SDHCI_TEGRA=y -# CONFIG_MMC_TIFM_SD is not set -CONFIG_MODULES_USE_ELF_REL=y -CONFIG_MPILIB=y -CONFIG_MTD_M25P80=y -CONFIG_MTD_SPI_NOR=y -CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y -CONFIG_MULTI_IRQ_HANDLER=y -CONFIG_MUTEX_SPIN_ON_OWNER=y -CONFIG_NEED_DMA_MAP_STATE=y -# CONFIG_NEON is not set -CONFIG_NET_FLOW_LIMIT=y -CONFIG_NLS=y -CONFIG_NO_BOOTMEM=y -CONFIG_NR_CPUS=4 -CONFIG_NVMEM=y -CONFIG_OF=y -CONFIG_OF_ADDRESS=y -CONFIG_OF_ADDRESS_PCI=y -CONFIG_OF_EARLY_FLATTREE=y -CONFIG_OF_FLATTREE=y -CONFIG_OF_GPIO=y -CONFIG_OF_IOMMU=y -CONFIG_OF_IRQ=y -CONFIG_OF_NET=y -CONFIG_OF_PCI=y -CONFIG_OF_PCI_IRQ=y -CONFIG_OF_RESERVED_MEM=y -CONFIG_OLD_SIGACTION=y -CONFIG_OLD_SIGSUSPEND3=y -CONFIG_OUTER_CACHE=y -CONFIG_OUTER_CACHE_SYNC=y -CONFIG_PADATA=y -CONFIG_PAGE_OFFSET=0xC0000000 -CONFIG_PCI=y -CONFIG_PCIEAER=y -CONFIG_PCIEASPM=y -# CONFIG_PCIEASPM_DEBUG is not set -CONFIG_PCIEASPM_DEFAULT=y -# CONFIG_PCIEASPM_PERFORMANCE is not set -# CONFIG_PCIEASPM_POWERSAVE is not set -# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set -CONFIG_PCIEPORTBUS=y -CONFIG_PCIE_PME=y -CONFIG_PCI_DOMAINS=y -CONFIG_PCI_DOMAINS_GENERIC=y -CONFIG_PCI_MSI=y -CONFIG_PCI_MSI_IRQ_DOMAIN=y -CONFIG_PCI_TEGRA=y -CONFIG_PERF_USE_VMALLOC=y -CONFIG_PGTABLE_LEVELS=2 -CONFIG_PHY_TEGRA_XUSB=y -CONFIG_PINCTRL=y -CONFIG_PINCTRL_TEGRA=y -CONFIG_PINCTRL_TEGRA20=y -CONFIG_PINCTRL_TEGRA_XUSB=y -# CONFIG_PL310_ERRATA_588369 is not set -CONFIG_PL310_ERRATA_727915=y -# CONFIG_PL310_ERRATA_753970 is not set -CONFIG_PL310_ERRATA_769419=y -CONFIG_PM=y -CONFIG_PM_CLK=y -# CONFIG_PM_DEBUG is not set -CONFIG_PM_OPP=y -CONFIG_PM_SLEEP=y -CONFIG_PM_SLEEP_SMP=y -CONFIG_POWER_RESET=y -CONFIG_POWER_RESET_GPIO=y -CONFIG_POWER_SUPPLY=y -CONFIG_PROC_PAGE_MONITOR=y -CONFIG_PWM=y -CONFIG_PWM_SYSFS=y -CONFIG_PWM_TEGRA=y -CONFIG_RAS=y -CONFIG_RATIONAL=y -CONFIG_RCU_CPU_STALL_TIMEOUT=21 -# CONFIG_RCU_EXPERT is not set -CONFIG_RCU_NEED_SEGCBLIST=y -CONFIG_RCU_STALL_COMMON=y -CONFIG_REGMAP=y -CONFIG_REGMAP_I2C=y -CONFIG_REGMAP_MMIO=y -CONFIG_REGMAP_SPI=y -CONFIG_REGULATOR=y -CONFIG_REGULATOR_FIXED_VOLTAGE=y -CONFIG_REGULATOR_GPIO=y -CONFIG_RESET_CONTROLLER=y -CONFIG_RFS_ACCEL=y -CONFIG_RPS=y -CONFIG_RTC_CLASS=y -# CONFIG_RTC_DRV_CMOS is not set -CONFIG_RTC_DRV_TEGRA=y -CONFIG_RTC_I2C_AND_SPI=y -CONFIG_RTC_NVMEM=y -CONFIG_RWSEM_SPIN_ON_OWNER=y -CONFIG_RWSEM_XCHGADD_ALGORITHM=y -# CONFIG_SCHED_INFO is not set -CONFIG_SCSI=y -# CONFIG_SCSI_LOWLEVEL is not set -# CONFIG_SCSI_PROC_FS is not set -CONFIG_SERIAL_8250_FSL=y -# CONFIG_SERIAL_AMBA_PL011 is not set -CONFIG_SERIAL_OF_PLATFORM=y -CONFIG_SERIAL_TEGRA=y -CONFIG_SERIO=y -CONFIG_SERIO_LIBPS2=y -CONFIG_SG_POOL=y -CONFIG_SMP=y -CONFIG_SMP_ON_UP=y -CONFIG_SND=y -# CONFIG_SND_COMPRESS_OFFLOAD is not set -CONFIG_SND_DMAENGINE_PCM=y -# CONFIG_SND_DRIVERS is not set -# CONFIG_SND_HDA_TEGRA is not set -CONFIG_SND_JACK=y -CONFIG_SND_JACK_INPUT_DEV=y -# CONFIG_SND_PCI is not set -CONFIG_SND_PCM=y -# CONFIG_SND_PROC_FS is not set -CONFIG_SND_SIMPLE_CARD=y -CONFIG_SND_SIMPLE_CARD_UTILS=y -CONFIG_SND_SOC=y -CONFIG_SND_SOC_AC97_BUS=y -CONFIG_SND_SOC_GENERIC_DMAENGINE_PCM=y -CONFIG_SND_SOC_I2C_AND_SPI=y -CONFIG_SND_SOC_TEGRA=y -CONFIG_SND_SOC_TEGRA20_AC97=y -CONFIG_SND_SOC_TEGRA20_DAS=y -CONFIG_SND_SOC_TEGRA20_I2S=y -CONFIG_SND_SOC_TEGRA20_SPDIF=y -# CONFIG_SND_SOC_TEGRA30_AHUB is not set -# CONFIG_SND_SOC_TEGRA30_I2S is not set -# CONFIG_SND_SOC_TEGRA_ALC5632 is not set -# CONFIG_SND_SOC_TEGRA_MAX98090 is not set -# CONFIG_SND_SOC_TEGRA_RT5640 is not set -# CONFIG_SND_SOC_TEGRA_RT5677 is not set -# CONFIG_SND_SOC_TEGRA_SGTL5000 is not set -CONFIG_SND_SOC_TEGRA_TRIMSLICE=y -# CONFIG_SND_SOC_TEGRA_WM8753 is not set -# CONFIG_SND_SOC_TEGRA_WM8903 is not set -# CONFIG_SND_SOC_TEGRA_WM9712 is not set -CONFIG_SND_SOC_TLV320AIC23=y -CONFIG_SND_SOC_TLV320AIC23_I2C=y -# CONFIG_SND_USB is not set -CONFIG_SOC_BUS=y -CONFIG_SOC_TEGRA_FLOWCTRL=y -CONFIG_SOC_TEGRA_FUSE=y -CONFIG_SOC_TEGRA_PMC=y -CONFIG_SOUND=y -CONFIG_SOUND_OSS_CORE=y -CONFIG_SOUND_OSS_CORE_PRECLAIM=y -CONFIG_SPARSE_IRQ=y -CONFIG_SPI=y -CONFIG_SPI_MASTER=y -# CONFIG_SPI_TEGRA114 is not set -CONFIG_SPI_TEGRA20_SFLASH=y -CONFIG_SPI_TEGRA20_SLINK=y -CONFIG_SRCU=y -CONFIG_SUSPEND=y -CONFIG_SUSPEND_FREEZER=y -CONFIG_SWIOTLB=y -CONFIG_SWP_EMULATE=y -CONFIG_SYNC_FILE=y -CONFIG_SYS_SUPPORTS_APM_EMULATION=y -CONFIG_TEGRA20_APB_DMA=y -CONFIG_TEGRA20_MC=y -CONFIG_TEGRA_AHB=y -CONFIG_TEGRA_GMI=y -CONFIG_TEGRA_HOST1X=y -CONFIG_TEGRA_HOST1X_FIREWALL=y -CONFIG_TEGRA_IOMMU_GART=y -# CONFIG_TEGRA_IOMMU_SMMU is not set -# CONFIG_TEGRA_IVC is not set -CONFIG_TEGRA_MC=y -CONFIG_TEGRA_TIMER=y -CONFIG_TEGRA_WATCHDOG=y -# CONFIG_THUMB2_KERNEL is not set -CONFIG_TICK_CPU_ACCOUNTING=y -CONFIG_TIMER_OF=y -CONFIG_TIMER_PROBE=y -CONFIG_TREE_RCU=y -CONFIG_TREE_SRCU=y -CONFIG_TRUSTED_FOUNDATIONS=y -CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" -CONFIG_USB=y -CONFIG_USB_COMMON=y -CONFIG_USB_EHCI_HCD=y -# CONFIG_USB_EHCI_HCD_PLATFORM is not set -CONFIG_USB_EHCI_TEGRA=y -CONFIG_USB_HID=y -CONFIG_USB_HIDDEV=y -CONFIG_USB_PHY=y -CONFIG_USB_SUPPORT=y -CONFIG_USB_ULPI=y -CONFIG_USB_ULPI_VIEWPORT=y -# CONFIG_USERIO is not set -CONFIG_USE_OF=y -CONFIG_VDSO=y -CONFIG_VECTORS_BASE=0xffff0000 -# CONFIG_VFIO is not set -CONFIG_VFP=y -CONFIG_VFPv3=y -CONFIG_WATCHDOG_CORE=y -CONFIG_XPS=y -CONFIG_XZ_DEC_ARM=y -CONFIG_XZ_DEC_ARMTHUMB=y -CONFIG_XZ_DEC_BCJ=y -CONFIG_ZBOOT_ROM_BSS=0 -CONFIG_ZBOOT_ROM_TEXT=0 -CONFIG_ZLIB_DEFLATE=y -CONFIG_ZLIB_INFLATE=y diff --git a/target/linux/tegra/patches-4.14/100-serial8250-on-tegra-hsuart-recover-from-spurious-interrupts-due-to-tegra2-silicon-bug.patch b/target/linux/tegra/patches-4.14/100-serial8250-on-tegra-hsuart-recover-from-spurious-interrupts-due-to-tegra2-silicon-bug.patch deleted file mode 100644 index cfbc5d9c4f89..000000000000 --- a/target/linux/tegra/patches-4.14/100-serial8250-on-tegra-hsuart-recover-from-spurious-interrupts-due-to-tegra2-silicon-bug.patch +++ /dev/null @@ -1,77 +0,0 @@ -From patchwork Fri Jul 13 11:32:42 2018 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -Subject: serial8250 on tegra hsuart: recover from spurious interrupts due to - tegra2 silicon bug -X-Patchwork-Submitter: "David R. Piegdon" -X-Patchwork-Id: 943440 -Message-Id: <4676ea34-69ce-5422-1ded-94218b89f7d9@p23q.org> -To: linux-tegra@vger.kernel.org -Date: Fri, 13 Jul 2018 11:32:42 +0000 -From: "David R. Piegdon" -List-Id: - -Hi, -a while back I sent a few mails regarding spurious interrupts in the -UARTA (hsuart) block of the Tegra2 SoC, when using the 8250 driver for -it instead of the hsuart driver. After going down a pretty deep -debugging/testing hole, I think I found a patch that fixes the issue. So -far testing in a reboot-cycle suggests that the error frequency dropped -from >3% of all reboots to at least <0.05% of all reboots. Tests -continue to run over the weekend. - -The patch below already is a second iteration; the first did not reset -the MCR or contain the lines below '// clear interrupts'. This resulted -in no more spurious interrupts, but in a few % of spurious interrupts -that were recovered the UART block did not receive any characters any -more. So further resetting was required to fully reacquire operational -state of the UART block. - -I'd love any comments/suggestions on this! - -Cheers, - -David - ---- a/drivers/tty/serial/8250/8250_core.c -+++ b/drivers/tty/serial/8250/8250_core.c -@@ -140,6 +140,38 @@ static irqreturn_t serial8250_interrupt( - "serial8250: too much work for irq%d\n", irq); - break; - } -+ -+#ifdef CONFIG_ARCH_TEGRA_2x_SOC -+ if (!handled && (port->type == PORT_TEGRA)) { -+ /* -+ * Fix Tegra 2 CPU silicon bug where sometimes -+ * "TX holding register empty" interrupts result in a -+ * bad (metastable?) state in Tegras HSUART IP core. -+ * Only way to recover seems to be to reset all -+ * interrupts as well as the TX queue and the MCR. -+ * But we don't want to loose any outgoing characters, -+ * so only do it if the RX and TX queues are empty. -+ */ -+ unsigned char lsr = port->serial_in(port, UART_LSR); -+ const unsigned char fifo_empty_mask = -+ (UART_LSR_TEMT | UART_LSR_THRE); -+ if (((lsr & (UART_LSR_DR | fifo_empty_mask)) == -+ fifo_empty_mask)) { -+ port->serial_out(port, UART_IER, 0); -+ port->serial_out(port, UART_MCR, 0); -+ serial8250_clear_and_reinit_fifos(up); -+ port->serial_out(port, UART_MCR, up->mcr); -+ port->serial_out(port, UART_IER, up->ier); -+ // clear interrupts -+ serial_port_in(port, UART_LSR); -+ serial_port_in(port, UART_RX); -+ serial_port_in(port, UART_IIR); -+ serial_port_in(port, UART_MSR); -+ up->lsr_saved_flags = 0; -+ up->msr_saved_flags = 0; -+ } -+ } -+#endif - } while (l != end); - - spin_unlock(&i->lock); diff --git a/target/linux/tegra/patches-4.14/101-ARM-dtc-tegra-enable-front-panel-leds-in-TrimSlice.patch b/target/linux/tegra/patches-4.14/101-ARM-dtc-tegra-enable-front-panel-leds-in-TrimSlice.patch deleted file mode 100644 index ae48e8d8627b..000000000000 --- a/target/linux/tegra/patches-4.14/101-ARM-dtc-tegra-enable-front-panel-leds-in-TrimSlice.patch +++ /dev/null @@ -1,46 +0,0 @@ ---- a/arch/arm/boot/dts/tegra20-trimslice.dts -+++ b/arch/arm/boot/dts/tegra20-trimslice.dts -@@ -200,16 +200,17 @@ - conf_ata { - nvidia,pins = "ata", "atc", "atd", "ate", - "crtp", "dap2", "dap3", "dap4", "dta", -- "dtb", "dtc", "dtd", "dte", "gmb", -- "gme", "i2cp", "pta", "slxc", "slxd", -- "spdi", "spdo", "uda"; -+ "dtb", "dtc", "dtd", "gmb", "gme", -+ "i2cp", "pta", "slxc", "slxd", "spdi", -+ "spdo", "uda"; - nvidia,pull = ; - nvidia,tristate = ; - }; - conf_atb { - nvidia,pins = "atb", "cdev1", "cdev2", "dap1", -- "gma", "gmc", "gmd", "gpu", "gpu7", -- "gpv", "sdio1", "slxa", "slxk", "uac"; -+ "dte", "gma", "gmc", "gmd", "gpu", -+ "gpu7", "gpv", "sdio1", "slxa", "slxk", -+ "uac"; - nvidia,pull = ; - nvidia,tristate = ; - }; -@@ -402,6 +403,20 @@ - }; - }; - -+ gpio-leds { -+ compatible = "gpio-leds"; -+ -+ ds2 { -+ label = "trimslice:green:right"; -+ gpios = <&gpio TEGRA_GPIO(D, 2) GPIO_ACTIVE_LOW>; -+ }; -+ -+ ds3 { -+ label = "trimslice:green:left"; -+ gpios = <&gpio TEGRA_GPIO(BB, 5) GPIO_ACTIVE_LOW>; -+ }; -+ }; -+ - poweroff { - compatible = "gpio-poweroff"; - gpios = <&gpio TEGRA_GPIO(X, 7) GPIO_ACTIVE_LOW>; From patchwork Sun Mar 1 12:12:41 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hauke Mehrtens X-Patchwork-Id: 1247289 X-Patchwork-Delegate: hauke@hauke-m.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; 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Sun, 01 Mar 2020 12:13:24 +0000 Received: from smtp2.mailbox.org (smtp2.mailbox.org [IPv6:2001:67c:2050:105:465:1:2:0]) (using TLSv1.2 with cipher ECDHE-RSA-CHACHA20-POLY1305 (256/256 bits)) (No client certificate requested) by mout-p-201.mailbox.org (Postfix) with ESMTPS id 48VhxQ08SfzQlCW; Sun, 1 Mar 2020 13:12:58 +0100 (CET) X-Virus-Scanned: amavisd-new at heinlein-support.de Received: from smtp2.mailbox.org ([80.241.60.241]) by spamfilter02.heinlein-hosting.de (spamfilter02.heinlein-hosting.de [80.241.56.116]) (amavisd-new, port 10030) with ESMTP id vauuRvqbCnwj; Sun, 1 Mar 2020 13:12:54 +0100 (CET) From: Hauke Mehrtens To: openwrt-devel@lists.openwrt.org Date: Sun, 1 Mar 2020 13:12:41 +0100 Message-Id: <20200301121241.5545-13-hauke@hauke-m.de> In-Reply-To: <20200301121241.5545-1-hauke@hauke-m.de> References: <20200301121241.5545-1-hauke@hauke-m.de> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200301_041315_692254_272FB212 X-CRM114-Status: GOOD ( 11.44 ) X-Spam-Score: 0.5 (/) X-Spam-Report: SpamAssassin version 3.4.3 on bombadil.infradead.org summary: Content analysis details: (0.5 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at https://www.dnswl.org/, low trust [80.241.56.171 listed in list.dnswl.org] 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.0 SPF_PASS SPF: sender matches SPF record 1.2 UPPERCASE_75_100 message body is 75-100% uppercase Subject: [OpenWrt-Devel] [PATCH 12/12] x86: Remove kernel 4.14 support X-BeenThere: openwrt-devel@lists.openwrt.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: hauke@hauke-m.de Sender: "openwrt-devel" Errors-To: openwrt-devel-bounces+incoming=patchwork.ozlabs.org@lists.openwrt.org This target was switched to kernel 4.19 more than 6 months ago in commit f342ffd300da ("treewide: kernel: bump some targets to 4.19") and now with kernel 5.4 support being added it gets harder to support kernel 4.14 in addition to kernel 4.19 and 5.4. Signed-off-by: Hauke Mehrtens --- target/linux/x86/64/config-4.14 | 487 ---------------- target/linux/x86/config-4.14 | 528 ------------------ target/linux/x86/generic/config-4.14 | 429 -------------- target/linux/x86/geode/config-4.14 | 145 ----- target/linux/x86/legacy/config-4.14 | 215 ------- .../patches-4.14/011-tune_lzma_options.patch | 22 - .../100-fix_cs5535_clockevt.patch | 12 - .../200-pcengines-apu2-reboot.patch | 19 - ...0-hwmon-w83627ehf-dont-claim-nct677x.patch | 30 - 9 files changed, 1887 deletions(-) delete mode 100644 target/linux/x86/64/config-4.14 delete mode 100644 target/linux/x86/config-4.14 delete mode 100644 target/linux/x86/generic/config-4.14 delete mode 100644 target/linux/x86/geode/config-4.14 delete mode 100644 target/linux/x86/legacy/config-4.14 delete mode 100644 target/linux/x86/patches-4.14/011-tune_lzma_options.patch delete mode 100644 target/linux/x86/patches-4.14/100-fix_cs5535_clockevt.patch delete mode 100644 target/linux/x86/patches-4.14/200-pcengines-apu2-reboot.patch delete mode 100644 target/linux/x86/patches-4.14/800-hwmon-w83627ehf-dont-claim-nct677x.patch diff --git a/target/linux/x86/64/config-4.14 b/target/linux/x86/64/config-4.14 deleted file mode 100644 index b9777c0f72dd..000000000000 --- a/target/linux/x86/64/config-4.14 +++ /dev/null @@ -1,487 +0,0 @@ -CONFIG_64BIT=y -CONFIG_ACPI=y -CONFIG_ACPI_AC=y -CONFIG_ACPI_BATTERY=y -# CONFIG_ACPI_BGRT is not set -CONFIG_ACPI_BUTTON=y -# CONFIG_ACPI_CMPC is not set -CONFIG_ACPI_CONTAINER=y -CONFIG_ACPI_CPPC_LIB=y -CONFIG_ACPI_CPU_FREQ_PSS=y -# CONFIG_ACPI_CUSTOM_DSDT is not set -# CONFIG_ACPI_DEBUG is not set -# CONFIG_ACPI_DEBUGGER is not set -# CONFIG_ACPI_DOCK is not set -# CONFIG_ACPI_EC_DEBUGFS is not set -CONFIG_ACPI_FAN=y -CONFIG_ACPI_HOTPLUG_CPU=y -CONFIG_ACPI_HOTPLUG_IOAPIC=y -# CONFIG_ACPI_I2C_OPREGION is not set -CONFIG_ACPI_LEGACY_TABLES_LOOKUP=y -# CONFIG_ACPI_PCI_SLOT is not set -CONFIG_ACPI_PROCESSOR=y -# CONFIG_ACPI_PROCESSOR_AGGREGATOR is not set -CONFIG_ACPI_PROCESSOR_CSTATE=y -CONFIG_ACPI_PROCESSOR_IDLE=y -# CONFIG_ACPI_PROCFS_POWER is not set -CONFIG_ACPI_REV_OVERRIDE_POSSIBLE=y -# CONFIG_ACPI_SBS is not set -CONFIG_ACPI_SYSTEM_POWER_STATES_SUPPORT=y -CONFIG_ACPI_THERMAL=y -CONFIG_ACPI_VIDEO=y -# CONFIG_ACPI_WMI is not set -CONFIG_AGP=y -# CONFIG_AGP_ALI is not set -# CONFIG_AGP_AMD is not set -# CONFIG_AGP_AMD64 is not set -# CONFIG_AGP_ATI is not set -# CONFIG_AGP_EFFICEON is not set -CONFIG_AGP_INTEL=y -# CONFIG_AGP_NVIDIA is not set -# CONFIG_AGP_SIS is not set -# CONFIG_AGP_SWORKS is not set -# CONFIG_AGP_VIA is not set -# CONFIG_APM is not set -CONFIG_ARCH_DEFCONFIG="arch/x86/configs/x86_64_defconfig" -CONFIG_ARCH_HAS_ACPI_TABLE_UPGRADE=y -CONFIG_ARCH_HAS_ADD_PAGES=y -CONFIG_ARCH_HAS_KCOV=y -CONFIG_ARCH_HAS_PMEM_API=y -CONFIG_ARCH_HAS_UACCESS_FLUSHCACHE=y -CONFIG_ARCH_HAS_ZONE_DEVICE=y -CONFIG_ARCH_MIGHT_HAVE_ACPI_PDC=y -CONFIG_ARCH_MMAP_RND_BITS=28 -CONFIG_ARCH_MMAP_RND_BITS_MAX=32 -CONFIG_ARCH_MMAP_RND_BITS_MIN=28 -CONFIG_ARCH_SPARSEMEM_DEFAULT=y -CONFIG_ARCH_SUPPORTS_INT128=y -CONFIG_ARCH_SUPPORTS_NUMA_BALANCING=y -CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y -CONFIG_ARCH_WANTS_THP_SWAP=y -CONFIG_AUDIT_ARCH=y -CONFIG_BACKLIGHT_CLASS_DEVICE=y -CONFIG_BACKLIGHT_GENERIC=y -CONFIG_BACKLIGHT_LCD_SUPPORT=y -CONFIG_BALLOON_COMPACTION=y -CONFIG_BLK_DEV_INTEGRITY=y -CONFIG_BLK_DEV_NVME=y -CONFIG_BLK_MQ_VIRTIO=y -# CONFIG_BOOTPARAM_HOTPLUG_CPU0 is not set -CONFIG_CALGARY_IOMMU=y -CONFIG_CALGARY_IOMMU_ENABLED_BY_DEFAULT=y -CONFIG_CONNECTOR=y -# CONFIG_CPU_HOTPLUG_STATE_CONTROL is not set -CONFIG_CPU_RMAP=y -CONFIG_CRC_T10DIF=y -CONFIG_CRYPTO_AEAD=y -CONFIG_CRYPTO_AEAD2=y -CONFIG_CRYPTO_AES_NI_INTEL=y -CONFIG_CRYPTO_AES_X86_64=y -# CONFIG_CRYPTO_BLOWFISH_X86_64 is not set -# CONFIG_CRYPTO_CAMELLIA_AESNI_AVX2_X86_64 is not set -# CONFIG_CRYPTO_CAMELLIA_AESNI_AVX_X86_64 is not set -# CONFIG_CRYPTO_CAMELLIA_X86_64 is not set -# CONFIG_CRYPTO_CAST5_AVX_X86_64 is not set -# CONFIG_CRYPTO_CAST6_AVX_X86_64 is not set -# CONFIG_CRYPTO_CHACHA20_X86_64 is not set -CONFIG_CRYPTO_CRCT10DIF=y -# CONFIG_CRYPTO_CRCT10DIF_PCLMUL is not set -CONFIG_CRYPTO_CRYPTD=y -# CONFIG_CRYPTO_DES3_EDE_X86_64 is not set -CONFIG_CRYPTO_ECB=y -CONFIG_CRYPTO_GF128MUL=y -CONFIG_CRYPTO_GLUE_HELPER_X86=y -CONFIG_CRYPTO_LRW=y -CONFIG_CRYPTO_MANAGER=y -CONFIG_CRYPTO_MANAGER2=y -CONFIG_CRYPTO_NULL2=y -# CONFIG_CRYPTO_POLY1305_X86_64 is not set -# CONFIG_CRYPTO_SERPENT_AVX2_X86_64 is not set -# CONFIG_CRYPTO_SERPENT_AVX_X86_64 is not set -# CONFIG_CRYPTO_SERPENT_SSE2_X86_64 is not set -# CONFIG_CRYPTO_SHA1_MB is not set -# CONFIG_CRYPTO_SHA1_SSSE3 is not set -# CONFIG_CRYPTO_SHA256_MB is not set -# CONFIG_CRYPTO_SHA256_SSSE3 is not set -# CONFIG_CRYPTO_SHA512_MB is not set -# CONFIG_CRYPTO_SHA512_SSSE3 is not set -CONFIG_CRYPTO_SIMD=y -# CONFIG_CRYPTO_SKEIN is not set -# CONFIG_CRYPTO_TWOFISH_AVX_X86_64 is not set -# CONFIG_CRYPTO_TWOFISH_X86_64 is not set -# CONFIG_CRYPTO_TWOFISH_X86_64_3WAY is not set -CONFIG_CRYPTO_XTS=y -# CONFIG_DEBUG_HOTPLUG_CPU0 is not set -# CONFIG_DPTF_POWER is not set -CONFIG_DRM=y -# CONFIG_DRM_AMDGPU is not set -# CONFIG_DRM_AMDGPU_CIK is not set -# CONFIG_DRM_AMDGPU_GART_DEBUGFS is not set -# CONFIG_DRM_AMDGPU_SI is not set -# CONFIG_DRM_AMDGPU_USERPTR is not set -# CONFIG_DRM_AMD_ACP is not set -CONFIG_DRM_BOCHS=y -CONFIG_DRM_BRIDGE=y -CONFIG_DRM_FBDEV_EMULATION=y -CONFIG_DRM_FBDEV_OVERALLOC=100 -# CONFIG_DRM_GMA500 is not set -CONFIG_DRM_I915=y -# CONFIG_DRM_I915_ALPHA_SUPPORT is not set -CONFIG_DRM_I915_CAPTURE_ERROR=y -CONFIG_DRM_I915_COMPRESS_ERROR=y -# CONFIG_DRM_I915_DEBUG is not set -# CONFIG_DRM_I915_DEBUG_VBLANK_EVADE is not set -CONFIG_DRM_I915_GVT=y -# CONFIG_DRM_I915_LOW_LEVEL_TRACEPOINTS is not set -# CONFIG_DRM_I915_SELFTEST is not set -# CONFIG_DRM_I915_SW_FENCE_CHECK_DAG is not set -# CONFIG_DRM_I915_SW_FENCE_DEBUG_OBJECTS is not set -CONFIG_DRM_I915_USERPTR=y -# CONFIG_DRM_I915_WERROR is not set -CONFIG_DRM_KMS_FB_HELPER=y -CONFIG_DRM_KMS_HELPER=y -CONFIG_DRM_MIPI_DSI=y -CONFIG_DRM_PANEL=y -CONFIG_DRM_PANEL_BRIDGE=y -# CONFIG_DRM_RADEON is not set -# CONFIG_DRM_RADEON_USERPTR is not set -CONFIG_DRM_TTM=y -CONFIG_DRM_VIRTIO_GPU=y -# CONFIG_DRM_VMWGFX is not set -CONFIG_EARLY_PRINTK_EFI=y -# CONFIG_EBC_C384_WDT is not set -CONFIG_EFI=y -CONFIG_EFIVAR_FS=m -# CONFIG_EFI_CAPSULE_LOADER is not set -# CONFIG_EFI_DEV_PATH_PARSER is not set -CONFIG_EFI_ESRT=y -# CONFIG_EFI_FAKE_MEMMAP is not set -# CONFIG_EFI_MIXED is not set -# CONFIG_EFI_PGT_DUMP is not set -CONFIG_EFI_RUNTIME_MAP=y -CONFIG_EFI_RUNTIME_WRAPPERS=y -CONFIG_EFI_STUB=y -# CONFIG_EFI_TEST is not set -# CONFIG_EFI_VARS is not set -CONFIG_FB=y -CONFIG_FB_CFB_COPYAREA=y -CONFIG_FB_CFB_FILLRECT=y -CONFIG_FB_CFB_IMAGEBLIT=y -CONFIG_FB_CMDLINE=y -CONFIG_FB_DEFERRED_IO=y -CONFIG_FB_EFI=y -CONFIG_FB_HYPERV=y -# CONFIG_FB_I810 is not set -CONFIG_FB_MODE_HELPERS=y -# CONFIG_FB_PROVIDE_GET_FB_UNMAPPED_AREA is not set -CONFIG_FB_SIMPLE=y -CONFIG_FB_SYS_COPYAREA=y -CONFIG_FB_SYS_FILLRECT=y -CONFIG_FB_SYS_FOPS=y -CONFIG_FB_SYS_IMAGEBLIT=y -CONFIG_FB_TILEBLITTING=y -# CONFIG_FB_VESA is not set -# CONFIG_FONTS is not set -CONFIG_FONT_8x16=y -CONFIG_FONT_8x8=y -CONFIG_FONT_SUPPORT=y -CONFIG_FRAMEBUFFER_CONSOLE=y -CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y -# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set -CONFIG_FREEZER=y -CONFIG_GART_IOMMU=y -CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y -CONFIG_GENERIC_CPU=y -CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y -CONFIG_GENERIC_IRQ_MIGRATION=y -CONFIG_GENERIC_PENDING_IRQ=y -CONFIG_GPIOLIB=y -CONFIG_GPIOLIB_IRQCHIP=y -CONFIG_GPIO_ACPI=y -CONFIG_GPIO_ICH=y -CONFIG_GPIO_IT87=y -CONFIG_GPIO_LYNXPOINT=y -CONFIG_GPIO_SCH=y -CONFIG_GPIO_SYSFS=y -CONFIG_HARDLOCKUP_CHECK_TIMESTAMP=y -CONFIG_HAVE_ACPI_APEI=y -CONFIG_HAVE_ACPI_APEI_NMI=y -CONFIG_HDMI=y -# CONFIG_HAVE_AOUT is not set -CONFIG_HAVE_ARCH_KASAN=y -CONFIG_HAVE_ARCH_SOFT_DIRTY=y -CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE_PUD=y -CONFIG_HAVE_ARCH_VMAP_STACK=y -CONFIG_HAVE_CONTEXT_TRACKING=y -CONFIG_HAVE_EBPF_JIT=y -CONFIG_HAVE_FENTRY=y -# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set -CONFIG_HAVE_IRQ_EXIT_ON_IRQ_STACK=y -CONFIG_HAVE_LIVEPATCH=y -CONFIG_HAVE_MEMORY_PRESENT=y -CONFIG_HAVE_RELIABLE_STACKTRACE=y -CONFIG_HAVE_STACK_VALIDATION=y -CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y -CONFIG_HIBERNATE_CALLBACKS=y -CONFIG_HID_BATTERY_STRENGTH=y -CONFIG_HID_GENERIC=y -CONFIG_HID_HYPERV_MOUSE=y -CONFIG_HOTPLUG_CPU=y -CONFIG_HOTPLUG_PCI=y -CONFIG_HOTPLUG_PCI_ACPI=y -# CONFIG_HOTPLUG_PCI_ACPI_IBM is not set -# CONFIG_HOTPLUG_PCI_CPCI is not set -# CONFIG_HOTPLUG_PCI_PCIE is not set -# CONFIG_HOTPLUG_PCI_SHPC is not set -CONFIG_HOTPLUG_SMT=y -CONFIG_HPET=y -CONFIG_HPET_MMAP=y -# CONFIG_HP_ACCEL is not set -CONFIG_HVC_DRIVER=y -CONFIG_HVC_IRQ=y -CONFIG_HVC_XEN=y -CONFIG_HVC_XEN_FRONTEND=y -CONFIG_HWMON=y -CONFIG_HWMON_VID=y -CONFIG_HW_RANDOM_AMD=y -CONFIG_HW_RANDOM_INTEL=y -CONFIG_HW_RANDOM_VIRTIO=y -CONFIG_HYPERV=y -CONFIG_HYPERVISOR_GUEST=y -CONFIG_HYPERV_BALLOON=y -CONFIG_HYPERV_KEYBOARD=y -CONFIG_HYPERV_NET=y -CONFIG_HYPERV_STORAGE=y -CONFIG_HYPERV_TSCPAGE=y -CONFIG_HYPERV_UTILS=y -# CONFIG_HYPERV_VSOCKETS is not set -CONFIG_I2C=y -CONFIG_I2C_BOARDINFO=y -# CONFIG_IA32_EMULATION is not set -CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000 -CONFIG_INPUT_XEN_KBDDEV_FRONTEND=y -CONFIG_INTEL_GTT=y -CONFIG_INTEL_IDLE=y -# CONFIG_INTEL_INT0002_VGPIO is not set -# CONFIG_INTEL_IPS is not set -# CONFIG_INTEL_MENLOW is not set -# CONFIG_INTEL_MIC_BUS is not set -CONFIG_INTEL_PCH_THERMAL=y -# CONFIG_INTEL_PMC_IPC is not set -CONFIG_INTEL_SOC_DTS_IOSF_CORE=y -CONFIG_INTEL_SOC_DTS_THERMAL=y -# CONFIG_INTEL_TURBO_MAX_3 is not set -# CONFIG_IOMMU_DEBUG is not set -CONFIG_IOSF_MBI=y -# CONFIG_IOSF_MBI_DEBUG is not set -# CONFIG_ISCSI_IBFT is not set -# CONFIG_ISCSI_IBFT_FIND is not set -CONFIG_KALLSYMS_ABSOLUTE_PERCPU=y -# CONFIG_KVM_DEBUG_FS is not set -CONFIG_KVM_GUEST=y -# CONFIG_LCD_CLASS_DEVICE is not set -CONFIG_LEDS_GPIO=y -# CONFIG_LEGACY_VSYSCALL_EMULATE is not set -# CONFIG_LEGACY_VSYSCALL_NATIVE is not set -CONFIG_LEGACY_VSYSCALL_NONE=y -CONFIG_LOCK_SPIN_ON_OWNER=y -CONFIG_LPC_ICH=y -CONFIG_LPC_SCH=y -CONFIG_MAILBOX=y -# CONFIG_MAXSMP is not set -CONFIG_MEMORY_BALLOON=y -# CONFIG_MEMORY_HOTPLUG is not set -CONFIG_MFD_CORE=y -# CONFIG_MFD_INTEL_LPSS_ACPI is not set -CONFIG_MMC=y -CONFIG_MMC_BLOCK=y -CONFIG_MMC_RICOH_MMC=y -CONFIG_MMC_SDHCI=y -CONFIG_MMC_SDHCI_PCI=y -# CONFIG_MMC_SDHCI_PLTFM is not set -# CONFIG_MMC_TIFM_SD is not set -# CONFIG_MMC_WBSD is not set -CONFIG_MMU_NOTIFIER=y -CONFIG_MODULES_USE_ELF_RELA=y -# CONFIG_MPSC is not set -CONFIG_MUTEX_SPIN_ON_OWNER=y -CONFIG_NET_FLOW_LIMIT=y -CONFIG_NR_CPUS=8 -# CONFIG_NUMA is not set -CONFIG_OUTPUT_FORMAT="elf64-x86-64" -CONFIG_PADATA=y -CONFIG_PAGE_TABLE_ISOLATION=y -CONFIG_PARAVIRT=y -CONFIG_PARAVIRT_CLOCK=y -# CONFIG_PARAVIRT_DEBUG is not set -CONFIG_PARAVIRT_SPINLOCKS=y -CONFIG_PATA_AMD=y -CONFIG_PATA_ATIIXP=y -CONFIG_PATA_MPIIX=y -CONFIG_PATA_OLDPIIX=y -CONFIG_PATA_PLATFORM=y -CONFIG_PATA_VIA=y -CONFIG_PCC=y -CONFIG_PCIEAER=y -CONFIG_PCIEPORTBUS=y -CONFIG_PCIE_PME=y -CONFIG_PCI_HYPERV=y -# CONFIG_PCI_MMCONFIG is not set -CONFIG_PCI_XEN=y -CONFIG_PGTABLE_LEVELS=4 -CONFIG_PHYSICAL_ALIGN=0x1000000 -CONFIG_PINCTRL=y -# CONFIG_PINCTRL_BAYTRAIL is not set -# CONFIG_PINCTRL_BROXTON is not set -# CONFIG_PINCTRL_CANNONLAKE is not set -# CONFIG_PINCTRL_CHERRYVIEW is not set -# CONFIG_PINCTRL_DENVERTON is not set -# CONFIG_PINCTRL_GEMINILAKE is not set -# CONFIG_PINCTRL_LEWISBURG is not set -# CONFIG_PINCTRL_SUNRISEPOINT is not set -CONFIG_PM=y -# CONFIG_PMIC_OPREGION is not set -CONFIG_PM_CLK=y -# CONFIG_PM_DEBUG is not set -CONFIG_PM_SLEEP=y -CONFIG_PM_SLEEP_SMP=y -CONFIG_PNP=y -CONFIG_PNPACPI=y -CONFIG_PNP_DEBUG_MESSAGES=y -CONFIG_PROC_EVENTS=y -# CONFIG_PVPANIC is not set -CONFIG_QUEUED_RWLOCKS=y -CONFIG_QUEUED_SPINLOCKS=y -# CONFIG_RANDOMIZE_BASE is not set -CONFIG_RAS=y -CONFIG_RCU_NEED_SEGCBLIST=y -CONFIG_RCU_STALL_COMMON=y -CONFIG_REGMAP=y -CONFIG_REGMAP_I2C=y -CONFIG_RELOCATABLE=y -CONFIG_RESET_ATTACK_MITIGATION=y -CONFIG_RFS_ACCEL=y -CONFIG_RPS=y -CONFIG_RTC_I2C_AND_SPI=y -CONFIG_RWSEM_SPIN_ON_OWNER=y -# CONFIG_SAMSUNG_Q10 is not set -CONFIG_SATA_AHCI=y -CONFIG_SCHED_MC=y -CONFIG_SCHED_MC_PRIO=y -CONFIG_SCHED_SMT=y -# CONFIG_SCIF_BUS is not set -CONFIG_SCSI_VIRTIO=y -CONFIG_SENSORS_CORETEMP=y -CONFIG_SENSORS_FAM15H_POWER=y -CONFIG_SENSORS_I5500=y -CONFIG_SENSORS_K10TEMP=y -CONFIG_SENSORS_K8TEMP=y -CONFIG_SENSORS_VIA_CPUTEMP=y -CONFIG_SERIAL_8250_PNP=y -CONFIG_SMP=y -CONFIG_SPARSEMEM=y -CONFIG_SPARSEMEM_ALLOC_MEM_MAP_TOGETHER=y -CONFIG_SPARSEMEM_EXTREME=y -CONFIG_SPARSEMEM_MANUAL=y -# CONFIG_SPARSEMEM_VMEMMAP is not set -CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y -CONFIG_STACK_VALIDATION=y -# CONFIG_SURFACE_PRO3_BUTTON is not set -CONFIG_SWIOTLB_XEN=y -CONFIG_SYS_HYPERVISOR=y -CONFIG_THERMAL_GOV_USER_SPACE=y -CONFIG_THERMAL_HWMON=y -CONFIG_THERMAL_WRITABLE_TRIPS=y -# CONFIG_TOSHIBA_BT_RFKILL is not set -CONFIG_TREE_RCU=y -CONFIG_TREE_SRCU=y -CONFIG_UCS2_STRING=y -# CONFIG_UNISYSSPAR is not set -# CONFIG_UNWINDER_ORC is not set -CONFIG_USB_STORAGE=y -CONFIG_VGACON_SOFT_SCROLLBACK=y -# CONFIG_VGACON_SOFT_SCROLLBACK_PERSISTENT_ENABLE_BY_DEFAULT is not set -CONFIG_VGACON_SOFT_SCROLLBACK_SIZE=64 -CONFIG_VIRTIO=y -CONFIG_VIRTIO_BALLOON=y -CONFIG_VIRTIO_BLK=y -CONFIG_VIRTIO_CONSOLE=y -CONFIG_VIRTIO_MMIO=y -# CONFIG_VIRTIO_MMIO_CMDLINE_DEVICES is not set -CONFIG_VIRTIO_NET=y -CONFIG_VIRTIO_PCI=y -CONFIG_VIRTIO_PCI_LEGACY=y -# CONFIG_VIRTIO_VSOCKETS is not set -CONFIG_VIRT_DRIVERS=y -CONFIG_VMAP_STACK=y -# CONFIG_VMD is not set -CONFIG_VMWARE_BALLOON=y -CONFIG_VMWARE_PVSCSI=y -CONFIG_VMWARE_VMCI=y -CONFIG_VMWARE_VMCI_VSOCKETS=y -CONFIG_VMXNET3=y -CONFIG_VSOCKETS=y -CONFIG_VT_CONSOLE_SLEEP=y -CONFIG_WATCHDOG_CORE=y -# CONFIG_X86_5LEVEL is not set -CONFIG_X86_64=y -CONFIG_X86_64_SMP=y -CONFIG_X86_ACPI_CPUFREQ=y -# CONFIG_X86_ACPI_CPUFREQ_CPB is not set -CONFIG_X86_AMD_FREQ_SENSITIVITY=y -# CONFIG_X86_AMD_PLATFORM_DEVICE is not set -CONFIG_X86_CMOV=y -CONFIG_X86_CPUID=y -CONFIG_X86_DEBUGCTLMSR=y -CONFIG_X86_DEV_DMA_OPS=y -CONFIG_X86_DIRECT_GBPAGES=y -CONFIG_X86_INTEL_LPSS=y -# CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS is not set -# CONFIG_X86_INTEL_MPX is not set -CONFIG_X86_INTEL_PSTATE=y -CONFIG_X86_MINIMUM_CPU_FAMILY=64 -# CONFIG_X86_PCC_CPUFREQ is not set -CONFIG_X86_PKG_TEMP_THERMAL=y -# CONFIG_X86_PMEM_LEGACY is not set -CONFIG_X86_PM_TIMER=y -# CONFIG_X86_POWERNOW_K8 is not set -# CONFIG_X86_VSYSCALL_EMULATION is not set -CONFIG_X86_X2APIC=y -# CONFIG_X86_X32 is not set -CONFIG_XEN=y -CONFIG_XENFS=y -CONFIG_XEN_512GB=y -CONFIG_XEN_ACPI=y -CONFIG_XEN_ACPI_PROCESSOR=y -CONFIG_XEN_AUTO_XLATE=y -# CONFIG_XEN_BACKEND is not set -CONFIG_XEN_BALLOON=y -CONFIG_XEN_BLKDEV_FRONTEND=y -CONFIG_XEN_COMPAT_XENFS=y -CONFIG_XEN_DEBUG_FS=y -CONFIG_XEN_DEV_EVTCHN=y -CONFIG_XEN_DOM0=y -CONFIG_XEN_EFI=y -CONFIG_XEN_FBDEV_FRONTEND=y -CONFIG_XEN_GNTDEV=y -CONFIG_XEN_GRANT_DEV_ALLOC=y -CONFIG_XEN_HAVE_PVMMU=y -CONFIG_XEN_HAVE_VPMU=y -# CONFIG_XEN_MCE_LOG is not set -CONFIG_XEN_NETDEV_FRONTEND=y -CONFIG_XEN_PCIDEV_FRONTEND=y -CONFIG_XEN_PRIVCMD=y -CONFIG_XEN_PV=y -CONFIG_XEN_PVH=y -CONFIG_XEN_PVHVM=y -CONFIG_XEN_PVHVM_SMP=y -CONFIG_XEN_PV_SMP=y -CONFIG_XEN_SAVE_RESTORE=y -CONFIG_XEN_SCRUB_PAGES=y -CONFIG_XEN_SCSI_FRONTEND=y -CONFIG_XEN_SYMS=y -CONFIG_XEN_SYS_HYPERVISOR=y -CONFIG_XEN_WDT=y -CONFIG_XEN_XENBUS_FRONTEND=y -CONFIG_XPS=y -CONFIG_ZONE_DMA32=y diff --git a/target/linux/x86/config-4.14 b/target/linux/x86/config-4.14 deleted file mode 100644 index 8d358aacaceb..000000000000 --- a/target/linux/x86/config-4.14 +++ /dev/null @@ -1,528 +0,0 @@ -# CONFIG_60XX_WDT is not set -# CONFIG_64BIT is not set -# CONFIG_ACPI is not set -# CONFIG_ACQUIRE_WDT is not set -# CONFIG_ADVANTECH_WDT is not set -# CONFIG_ALIM1535_WDT is not set -# CONFIG_ALIX is not set -CONFIG_AMD_NB=y -CONFIG_ARCH_CLOCKSOURCE_DATA=y -CONFIG_ARCH_DEFCONFIG="arch/x86/configs/i386_defconfig" -CONFIG_ARCH_DISCARD_MEMBLOCK=y -CONFIG_ARCH_DMA_ADDR_T_64BIT=y -CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y -CONFIG_ARCH_ENABLE_SPLIT_PMD_PTLOCK=y -CONFIG_ARCH_HAS_CACHE_LINE_SIZE=y -CONFIG_ARCH_HAS_CPU_RELAX=y -CONFIG_ARCH_HAS_DEBUG_VIRTUAL=y -CONFIG_ARCH_HAS_ELF_RANDOMIZE=y -CONFIG_ARCH_HAS_FAST_MULTIPLIER=y -CONFIG_ARCH_HAS_FORTIFY_SOURCE=y -CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y -CONFIG_ARCH_HAS_MEM_ENCRYPT=y -CONFIG_ARCH_HAS_REFCOUNT=y -CONFIG_ARCH_HAS_SET_MEMORY=y -CONFIG_ARCH_HAS_SG_CHAIN=y -CONFIG_ARCH_HAS_STRICT_KERNEL_RWX=y -CONFIG_ARCH_HAS_STRICT_MODULE_RWX=y -CONFIG_ARCH_HAVE_NMI_SAFE_CMPXCHG=y -CONFIG_ARCH_HIBERNATION_POSSIBLE=y -CONFIG_ARCH_MAY_HAVE_PC_FDC=y -CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y -CONFIG_ARCH_MIGHT_HAVE_PC_SERIO=y -# CONFIG_ARCH_OPTIONAL_KERNEL_RWX is not set -# CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT is not set -CONFIG_ARCH_PHYS_ADDR_T_64BIT=y -CONFIG_ARCH_RANDOM=y -CONFIG_ARCH_SELECT_MEMORY_MODEL=y -CONFIG_ARCH_SPARSEMEM_ENABLE=y -CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y -CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y -CONFIG_ARCH_SUPPORTS_DEFERRED_STRUCT_PAGE_INIT=y -CONFIG_ARCH_SUPPORTS_MEMORY_FAILURE=y -CONFIG_ARCH_SUPPORTS_UPROBES=y -CONFIG_ARCH_SUSPEND_POSSIBLE=y -CONFIG_ARCH_USES_PG_UNCACHED=y -CONFIG_ARCH_USE_BUILTIN_BSWAP=y -CONFIG_ARCH_USE_QUEUED_RWLOCKS=y -CONFIG_ARCH_USE_QUEUED_SPINLOCKS=y -CONFIG_ARCH_WANTS_DYNAMIC_TASK_STRUCT=y -CONFIG_ARCH_WANT_BATCHED_UNMAP_TLB_FLUSH=y -CONFIG_ARCH_WANT_GENERAL_HUGETLB=y -CONFIG_ARCH_WANT_HUGE_PMD_SHARE=y -CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y -CONFIG_ATA=y -CONFIG_ATA_GENERIC=y -CONFIG_ATA_PIIX=y -CONFIG_BLK_DEV_LOOP=y -CONFIG_BLK_DEV_SD=y -CONFIG_BLK_MQ_PCI=y -CONFIG_BLK_SCSI_REQUEST=y -CONFIG_BOUNCE=y -CONFIG_BTT=y -CONFIG_CLKBLD_I8253=y -CONFIG_CLKDEV_LOOKUP=y -CONFIG_CLKEVT_I8253=y -CONFIG_CLKSRC_I8253=y -CONFIG_CLOCKSOURCE_VALIDATE_LAST_CYCLE=y -CONFIG_CLOCKSOURCE_WATCHDOG=y -CONFIG_CLONE_BACKWARDS=y -CONFIG_COMMON_CLK=y -CONFIG_COMPAT_32=y -# CONFIG_COMPAT_VDSO is not set -CONFIG_CONSOLE_TRANSLATIONS=y -# CONFIG_CPU5_WDT is not set -CONFIG_CPU_FREQ=y -CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y -# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set -CONFIG_CPU_FREQ_GOV_ATTR_SET=y -CONFIG_CPU_FREQ_GOV_COMMON=y -# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set -CONFIG_CPU_FREQ_GOV_ONDEMAND=y -CONFIG_CPU_FREQ_GOV_PERFORMANCE=y -# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set -# CONFIG_CPU_FREQ_GOV_USERSPACE is not set -CONFIG_CPU_FREQ_STAT=y -CONFIG_CPU_IDLE=y -CONFIG_CPU_IDLE_GOV_LADDER=y -CONFIG_CPU_SUP_AMD=y -CONFIG_CPU_SUP_CENTAUR=y -CONFIG_CPU_SUP_CYRIX_32=y -CONFIG_CPU_SUP_INTEL=y -CONFIG_CPU_SUP_TRANSMETA_32=y -CONFIG_CPU_SUP_UMC_32=y -# CONFIG_CRASHLOG is not set -CONFIG_CRASH_CORE=y -CONFIG_CRC16=y -CONFIG_CRYPTO_AES_586=y -CONFIG_CRYPTO_CRC32=y -CONFIG_CRYPTO_CRC32C=y -# CONFIG_CRYPTO_CRC32_PCLMUL is not set -CONFIG_CRYPTO_HASH=y -CONFIG_CRYPTO_HASH2=y -CONFIG_CRYPTO_RNG2=y -# CONFIG_CRYPTO_SERPENT_SSE2_586 is not set -CONFIG_CRYPTO_WORKQUEUE=y -# CONFIG_CX_ECAT is not set -CONFIG_DCACHE_WORD_ACCESS=y -# CONFIG_DCDBAS is not set -# CONFIG_DEBUG_BOOT_PARAMS is not set -# CONFIG_DEBUG_ENTRY is not set -CONFIG_DEBUG_MEMORY_INIT=y -# CONFIG_DEBUG_NMI_SELFTEST is not set -# CONFIG_DEBUG_TLBFLUSH is not set -CONFIG_DECOMPRESS_BZIP2=y -CONFIG_DECOMPRESS_GZIP=y -CONFIG_DEFAULT_IO_DELAY_TYPE=0 -# CONFIG_DELL_RBU is not set -CONFIG_DMI=y -CONFIG_DMIID=y -CONFIG_DMI_SCAN_MACHINE_NON_EFI_FALLBACK=y -CONFIG_DMI_SYSFS=y -CONFIG_DNOTIFY=y -CONFIG_DUMMY_CONSOLE=y -CONFIG_EARLY_PRINTK=y -# CONFIG_EARLY_PRINTK_DBGP is not set -CONFIG_EDAC_ATOMIC_SCRUB=y -CONFIG_EDAC_SUPPORT=y -# CONFIG_EDD is not set -# CONFIG_EUROTECH_WDT is not set -CONFIG_EXT4_FS=y -# CONFIG_F2FS_CHECK_FS is not set -CONFIG_F2FS_FS=y -# CONFIG_F2FS_FS_SECURITY is not set -CONFIG_F2FS_FS_XATTR=y -CONFIG_F2FS_STAT_FS=y -# CONFIG_F71808E_WDT is not set -CONFIG_FIRMWARE_IN_KERNEL=y -CONFIG_FIRMWARE_MEMMAP=y -CONFIG_FIX_EARLYCON_MEM=y -CONFIG_FRAME_POINTER=y -CONFIG_FS_MBCACHE=y -CONFIG_FUSION=y -# CONFIG_FUSION_CTL is not set -# CONFIG_FUSION_LOGGING is not set -CONFIG_FUSION_MAX_SGE=128 -CONFIG_FUSION_SPI=y -CONFIG_GENERIC_ALLOCATOR=y -CONFIG_GENERIC_BUG=y -CONFIG_GENERIC_CLOCKEVENTS=y -CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y -CONFIG_GENERIC_CLOCKEVENTS_MIN_ADJUST=y -CONFIG_GENERIC_CMOS_UPDATE=y -CONFIG_GENERIC_CPU_AUTOPROBE=y -CONFIG_GENERIC_CPU_VULNERABILITIES=y -CONFIG_GENERIC_EARLY_IOREMAP=y -CONFIG_GENERIC_FIND_FIRST_BIT=y -CONFIG_GENERIC_IO=y -CONFIG_GENERIC_IOMAP=y -CONFIG_GENERIC_IRQ_SHOW=y -CONFIG_GENERIC_ISA_DMA=y -CONFIG_GENERIC_MSI_IRQ=y -CONFIG_GENERIC_MSI_IRQ_DOMAIN=y -CONFIG_GENERIC_PCI_IOMAP=y -CONFIG_GENERIC_SMP_IDLE_THREAD=y -CONFIG_GENERIC_STRNCPY_FROM_USER=y -CONFIG_GENERIC_STRNLEN_USER=y -CONFIG_GENERIC_TIME_VSYSCALL=y -# CONFIG_GEOS is not set -CONFIG_GLOB=y -# CONFIG_GRO_CELLS is not set -# CONFIG_HANGCHECK_TIMER is not set -CONFIG_HAS_DMA=y -CONFIG_HAS_IOMEM=y -CONFIG_HAS_IOPORT_MAP=y -# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set -CONFIG_HAVE_ALIGNED_STRUCT_PAGE=y -CONFIG_HAVE_AOUT=y -CONFIG_HAVE_ARCH_AUDITSYSCALL=y -# CONFIG_HAVE_ARCH_BITREVERSE is not set -CONFIG_HAVE_ARCH_HUGE_VMAP=y -CONFIG_HAVE_ARCH_JUMP_LABEL=y -CONFIG_HAVE_ARCH_KGDB=y -CONFIG_HAVE_ARCH_SECCOMP_FILTER=y -CONFIG_HAVE_ARCH_TRACEHOOK=y -CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE=y -CONFIG_HAVE_ATOMIC_IOMAP=y -# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set -CONFIG_HAVE_CC_STACKPROTECTOR=y -CONFIG_HAVE_CLK=y -CONFIG_HAVE_CLK_PREPARE=y -CONFIG_HAVE_CMPXCHG_DOUBLE=y -CONFIG_HAVE_CMPXCHG_LOCAL=y -CONFIG_HAVE_COPY_THREAD_TLS=y -CONFIG_HAVE_C_RECORDMCOUNT=y -CONFIG_HAVE_DEBUG_KMEMLEAK=y -CONFIG_HAVE_DEBUG_STACKOVERFLOW=y -CONFIG_HAVE_DMA_API_DEBUG=y -CONFIG_HAVE_DMA_CONTIGUOUS=y -CONFIG_HAVE_DYNAMIC_FTRACE=y -CONFIG_HAVE_DYNAMIC_FTRACE_WITH_REGS=y -CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y -CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y -CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y -CONFIG_HAVE_FUNCTION_TRACER=y -CONFIG_HAVE_GENERIC_DMA_COHERENT=y -CONFIG_HAVE_GENERIC_GUP=y -CONFIG_HAVE_HARDLOCKUP_DETECTOR_PERF=y -CONFIG_HAVE_HW_BREAKPOINT=y -CONFIG_HAVE_IDE=y -CONFIG_HAVE_IOREMAP_PROT=y -CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y -CONFIG_HAVE_KPROBES_ON_FTRACE=y -CONFIG_HAVE_KVM=y -CONFIG_HAVE_MEMBLOCK=y -CONFIG_HAVE_MEMBLOCK_NODE_MAP=y -CONFIG_HAVE_MIXED_BREAKPOINTS_REGS=y -CONFIG_HAVE_MMIOTRACE_SUPPORT=y -CONFIG_HAVE_MOD_ARCH_SPECIFIC=y -CONFIG_HAVE_NET_DSA=y -CONFIG_HAVE_OPROFILE=y -CONFIG_HAVE_OPTPROBES=y -CONFIG_HAVE_PCSPKR_PLATFORM=y -CONFIG_HAVE_PERF_EVENTS=y -CONFIG_HAVE_PERF_EVENTS_NMI=y -CONFIG_HAVE_PERF_REGS=y -CONFIG_HAVE_PERF_USER_STACK_DUMP=y -CONFIG_HAVE_RCU_TABLE_FREE=y -CONFIG_HAVE_RCU_TABLE_INVALIDATE=y -CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y -CONFIG_HAVE_SETUP_PER_CPU_AREA=y -CONFIG_HAVE_SYSCALL_TRACEPOINTS=y -CONFIG_HAVE_UID16=y -CONFIG_HAVE_UNSTABLE_SCHED_CLOCK=y -CONFIG_HAVE_USER_RETURN_NOTIFIER=y -CONFIG_HID=y -CONFIG_HIGHMEM=y -# CONFIG_HIGHMEM4G is not set -CONFIG_HIGHMEM64G=y -# CONFIG_HIGHPTE is not set -CONFIG_HPET_EMULATE_RTC=y -CONFIG_HPET_TIMER=y -# CONFIG_HP_WATCHDOG is not set -CONFIG_HT_IRQ=y -# CONFIG_HUGETLBFS is not set -CONFIG_HW_CONSOLE=y -CONFIG_HW_RANDOM=y -CONFIG_HW_RANDOM_GEODE=y -CONFIG_HW_RANDOM_VIA=y -# CONFIG_HYPERVISOR_GUEST is not set -CONFIG_HZ_PERIODIC=y -CONFIG_I8253_LOCK=y -# CONFIG_I8K is not set -# CONFIG_IB700_WDT is not set -# CONFIG_IBMASR is not set -# CONFIG_IBM_RTL is not set -# CONFIG_IE6XX_WDT is not set -CONFIG_ILLEGAL_POINTER_VALUE=0 -CONFIG_INITRAMFS_SOURCE="" -CONFIG_INPUT=y -CONFIG_INPUT_KEYBOARD=y -CONFIG_INSTRUCTION_DECODER=y -# CONFIG_INTEL_PCH_THERMAL is not set -# CONFIG_INTEL_POWERCLAMP is not set -# CONFIG_INTEL_RDT is not set -# CONFIG_INTEL_SOC_DTS_THERMAL is not set -CONFIG_IOMMU_HELPER=y -# CONFIG_IOMMU_STRESS is not set -# CONFIG_IOSF_MBI is not set -CONFIG_IO_DELAY_0X80=y -# CONFIG_IO_DELAY_0XED is not set -# CONFIG_IO_DELAY_NONE is not set -CONFIG_IO_DELAY_TYPE_0X80=0 -CONFIG_IO_DELAY_TYPE_0XED=1 -CONFIG_IO_DELAY_TYPE_NONE=3 -CONFIG_IO_DELAY_TYPE_UDELAY=2 -# CONFIG_IO_DELAY_UDELAY is not set -CONFIG_IRQ_DOMAIN=y -CONFIG_IRQ_DOMAIN_HIERARCHY=y -CONFIG_IRQ_FORCED_THREADING=y -CONFIG_IRQ_WORK=y -# CONFIG_ISA is not set -CONFIG_ISA_DMA_API=y -# CONFIG_IT8712F_WDT is not set -# CONFIG_IT87_WDT is not set -# CONFIG_ITCO_WDT is not set -CONFIG_JBD2=y -CONFIG_KALLSYMS=y -CONFIG_KEXEC=y -CONFIG_KEXEC_CORE=y -CONFIG_KEYBOARD_ATKBD=y -# CONFIG_LEDS_CLEVO_MAIL is not set -CONFIG_LIBNVDIMM=y -# CONFIG_M486 is not set -# CONFIG_M586 is not set -CONFIG_M586MMX=y -# CONFIG_M586TSC is not set -# CONFIG_M686 is not set -# CONFIG_MACHZ_WDT is not set -# CONFIG_MATOM is not set -# CONFIG_MCORE2 is not set -# CONFIG_MCRUSOE is not set -# CONFIG_MCYRIXIII is not set -# CONFIG_MDIO_BUS is not set -# CONFIG_MEFFICEON is not set -# CONFIG_MELAN is not set -# CONFIG_MFD_INTEL_LPSS_PCI is not set -# CONFIG_MGEODEGX1 is not set -# CONFIG_MGEODE_LX is not set -CONFIG_MICROCODE=y -CONFIG_MICROCODE_AMD=y -CONFIG_MICROCODE_INTEL=y -CONFIG_MICROCODE_OLD_INTERFACE=y -CONFIG_MIGRATION=y -# CONFIG_MK6 is not set -# CONFIG_MK7 is not set -# CONFIG_MK8 is not set -# CONFIG_MODIFY_LDT_SYSCALL is not set -CONFIG_MODULES_TREE_LOOKUP=y -CONFIG_MODULES_USE_ELF_REL=y -# CONFIG_MPENTIUM4 is not set -# CONFIG_MPENTIUMII is not set -# CONFIG_MPENTIUMIII is not set -# CONFIG_MPENTIUMM is not set -# CONFIG_MTD is not set -CONFIG_MTRR=y -# CONFIG_MTRR_SANITIZER is not set -# CONFIG_MVIAC3_2 is not set -# CONFIG_MVIAC7 is not set -# CONFIG_MWINCHIP3D is not set -# CONFIG_MWINCHIPC6 is not set -CONFIG_NAMESPACES=y -CONFIG_ND_BLK=y -CONFIG_ND_BTT=y -CONFIG_ND_CLAIM=y -CONFIG_NEED_DMA_MAP_STATE=y -CONFIG_NEED_PER_CPU_EMBED_FIRST_CHUNK=y -CONFIG_NEED_PER_CPU_KM=y -CONFIG_NEED_PER_CPU_PAGE_FIRST_CHUNK=y -CONFIG_NEED_SG_DMA_LENGTH=y -# CONFIG_NET5501 is not set -# CONFIG_NET_NS is not set -CONFIG_NLS=y -# CONFIG_NOHIGHMEM is not set -CONFIG_NO_BOOTMEM=y -CONFIG_NR_CPUS=1 -# CONFIG_NSC_GPIO is not set -CONFIG_NVRAM=y -# CONFIG_OF is not set -CONFIG_OLD_SIGACTION=y -CONFIG_OLD_SIGSUSPEND3=y -CONFIG_OPROFILE_NMI_TIMER=y -CONFIG_OUTPUT_FORMAT="elf32-i386" -CONFIG_PAGE_OFFSET=0xC0000000 -CONFIG_PC104=y -# CONFIG_PC8736x_GPIO is not set -# CONFIG_PC87413_WDT is not set -CONFIG_PCI=y -CONFIG_PCI_BIOS=y -CONFIG_PCI_BUS_ADDR_T_64BIT=y -CONFIG_PCI_DIRECT=y -CONFIG_PCI_DOMAINS=y -CONFIG_PCI_GOANY=y -# CONFIG_PCI_GOBIOS is not set -# CONFIG_PCI_GODIRECT is not set -# CONFIG_PCI_GOMMCONFIG is not set -CONFIG_PCI_IOV=y -CONFIG_PCI_LABEL=y -CONFIG_PCI_LOCKLESS_CONFIG=y -CONFIG_PCI_MSI=y -CONFIG_PCI_MSI_IRQ_DOMAIN=y -CONFIG_PCSPKR_PLATFORM=y -CONFIG_PERF_EVENTS=y -CONFIG_PERF_EVENTS_INTEL_CSTATE=y -CONFIG_PERF_EVENTS_INTEL_RAPL=y -CONFIG_PERF_EVENTS_INTEL_UNCORE=y -CONFIG_PGTABLE_LEVELS=3 -CONFIG_PHYSICAL_ALIGN=0x100000 -CONFIG_PHYSICAL_START=0x1000000 -CONFIG_PHYS_ADDR_T_64BIT=y -CONFIG_PMC_ATOM=y -CONFIG_POWER_SUPPLY=y -# CONFIG_PROCESSOR_SELECT is not set -CONFIG_PROC_PAGE_MONITOR=y -# CONFIG_PROVIDE_OHCI1394_DMA_INIT is not set -# CONFIG_PUNIT_ATOM_DEBUG is not set -CONFIG_RATIONAL=y -# CONFIG_RCU_NEED_SEGCBLIST is not set -# CONFIG_RCU_STALL_COMMON is not set -CONFIG_RD_BZIP2=y -CONFIG_RD_GZIP=y -CONFIG_RETPOLINE=y -CONFIG_RTC_CLASS=y -CONFIG_RTC_MC146818_LIB=y -CONFIG_RWSEM_XCHGADD_ALGORITHM=y -# CONFIG_SBC7240_WDT is not set -# CONFIG_SBC8360_WDT is not set -# CONFIG_SBC_EPX_C3_WATCHDOG is not set -# CONFIG_SC1200_WDT is not set -# CONFIG_SCHED_INFO is not set -CONFIG_SCSI=y -CONFIG_SCSI_SPI_ATTRS=y -CONFIG_SCx200=y -CONFIG_SCx200HR_TIMER=y -# CONFIG_SCx200_GPIO is not set -# CONFIG_SCx200_WDT is not set -# CONFIG_SERIAL_8250_FSL is not set -CONFIG_SERIAL_8250_PCI=y -CONFIG_SERIO=y -CONFIG_SERIO_I8042=y -CONFIG_SERIO_LIBPS2=y -CONFIG_SERIO_SERPORT=y -CONFIG_SG_POOL=y -# CONFIG_SMSC37B787_WDT is not set -# CONFIG_SMSC_SCH311X_WDT is not set -CONFIG_SPARSEMEM_STATIC=y -CONFIG_SPARSE_IRQ=y -CONFIG_SRCU=y -CONFIG_SWIOTLB=y -CONFIG_SYSCTL_EXCEPTION_TRACE=y -# CONFIG_TELCLOCK is not set -CONFIG_THERMAL=y -CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y -CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0 -CONFIG_THERMAL_GOV_STEP_WISE=y -CONFIG_THREAD_INFO_IN_TASK=y -CONFIG_TICK_CPU_ACCOUNTING=y -CONFIG_TINY_SRCU=y -# CONFIG_TOSHIBA is not set -CONFIG_UNWINDER_FRAME_POINTER=y -# CONFIG_UNWINDER_GUESS is not set -CONFIG_UP_LATE_INIT=y -CONFIG_USB=y -CONFIG_USB_COMMON=y -CONFIG_USB_EHCI_HCD=y -# CONFIG_USB_EHCI_HCD_PLATFORM is not set -CONFIG_USB_EHCI_PCI=y -CONFIG_USB_HID=y -CONFIG_USB_HIDDEV=y -CONFIG_USB_OHCI_HCD=y -CONFIG_USB_OHCI_HCD_PCI=y -# CONFIG_USB_OHCI_HCD_PLATFORM is not set -CONFIG_USB_PCI=y -CONFIG_USB_SUPPORT=y -CONFIG_USB_UHCI_HCD=y -CONFIG_USB_XHCI_HCD=y -CONFIG_USB_XHCI_PCI=y -# CONFIG_USB_XHCI_PLATFORM is not set -# CONFIG_USERIO is not set -# CONFIG_USER_NS is not set -CONFIG_USER_STACKTRACE_SUPPORT=y -# CONFIG_VGACON_SOFT_SCROLLBACK is not set -CONFIG_VGA_CONSOLE=y -# CONFIG_VIA_WDT is not set -# CONFIG_VM86 is not set -# CONFIG_VMWARE_VMCI is not set -CONFIG_VM_EVENT_COUNTERS=y -CONFIG_VT=y -CONFIG_VT_CONSOLE=y -CONFIG_VT_HW_CONSOLE_BINDING=y -# CONFIG_WAFER_WDT is not set -CONFIG_X86=y -CONFIG_X86_32=y -# CONFIG_X86_32_IRIS is not set -CONFIG_X86_32_LAZY_GS=y -CONFIG_X86_ALIGNMENT_16=y -# CONFIG_X86_ANCIENT_MCE is not set -# CONFIG_X86_CHECK_BIOS_CORRUPTION is not set -CONFIG_X86_CMPXCHG64=y -# CONFIG_X86_CPUFREQ_NFORCE2 is not set -# CONFIG_X86_CPUID is not set -# CONFIG_X86_DEBUG_FPU is not set -# CONFIG_X86_DECODER_SELFTEST is not set -# CONFIG_X86_EXTENDED_PLATFORM is not set -CONFIG_X86_F00F_BUG=y -CONFIG_X86_FAST_FEATURE_TESTS=y -CONFIG_X86_FEATURE_NAMES=y -CONFIG_X86_GENERIC=y -# CONFIG_X86_GX_SUSPMOD is not set -# CONFIG_X86_INTEL_MPX is not set -# CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS is not set -# CONFIG_X86_INTEL_PSTATE is not set -CONFIG_X86_INTEL_TSX_MODE_OFF=y -# CONFIG_X86_INTEL_TSX_MODE_ON is not set -# CONFIG_X86_INTEL_TSX_MODE_AUTO is not set -CONFIG_X86_INTEL_USERCOPY=y -CONFIG_X86_INTERNODE_CACHE_SHIFT=6 -CONFIG_X86_IO_APIC=y -CONFIG_X86_L1_CACHE_SHIFT=6 -# CONFIG_X86_LEGACY_VM86 is not set -CONFIG_X86_LOCAL_APIC=y -# CONFIG_X86_LONGRUN is not set -CONFIG_X86_MCE=y -# CONFIG_X86_MCELOG_LEGACY is not set -CONFIG_X86_MCE_AMD=y -# CONFIG_X86_MCE_INJECT is not set -CONFIG_X86_MCE_INTEL=y -CONFIG_X86_MCE_THRESHOLD=y -CONFIG_X86_MINIMUM_CPU_FAMILY=5 -CONFIG_X86_MPPARSE=y -CONFIG_X86_MSR=y -# CONFIG_X86_P4_CLOCKMOD is not set -CONFIG_X86_PAE=y -CONFIG_X86_PAT=y -CONFIG_X86_PLATFORM_DEVICES=y -CONFIG_X86_PMEM_LEGACY=y -CONFIG_X86_PMEM_LEGACY_DEVICE=y -# CONFIG_X86_POWERNOW_K6 is not set -# CONFIG_X86_POWERNOW_K7 is not set -CONFIG_X86_PPRO_FENCE=y -# CONFIG_X86_PTDUMP is not set -# CONFIG_X86_PTDUMP_CORE is not set -# CONFIG_X86_REBOOTFIXUPS is not set -CONFIG_X86_REROUTE_FOR_BROKEN_BOOT_IRQS=y -CONFIG_X86_RESERVE_LOW=64 -CONFIG_X86_SMAP=y -# CONFIG_X86_SPEEDSTEP_CENTRINO is not set -# CONFIG_X86_SPEEDSTEP_ICH is not set -# CONFIG_X86_SPEEDSTEP_LIB is not set -# CONFIG_X86_SPEEDSTEP_SMI is not set -CONFIG_X86_SUPPORTS_MEMORY_FAILURE=y -CONFIG_X86_THERMAL_VECTOR=y -CONFIG_X86_TSC=y -CONFIG_X86_UP_APIC=y -CONFIG_X86_UP_IOAPIC=y -CONFIG_X86_VERBOSE_BOOTUP=y -CONFIG_XZ_DEC_BCJ=y -CONFIG_XZ_DEC_X86=y -CONFIG_ZLIB_INFLATE=y diff --git a/target/linux/x86/generic/config-4.14 b/target/linux/x86/generic/config-4.14 deleted file mode 100644 index 1e31e117dd0f..000000000000 --- a/target/linux/x86/generic/config-4.14 +++ /dev/null @@ -1,429 +0,0 @@ -# CONFIG_3C515 is not set -CONFIG_ACPI=y -CONFIG_ACPI_AC=y -CONFIG_ACPI_BATTERY=y -# CONFIG_ACPI_BGRT is not set -CONFIG_ACPI_BUTTON=y -# CONFIG_ACPI_CMPC is not set -CONFIG_ACPI_CONTAINER=y -CONFIG_ACPI_CPU_FREQ_PSS=y -# CONFIG_ACPI_CUSTOM_DSDT is not set -# CONFIG_ACPI_DEBUG is not set -# CONFIG_ACPI_DEBUGGER is not set -# CONFIG_ACPI_DOCK is not set -# CONFIG_ACPI_EC_DEBUGFS is not set -# CONFIG_ACPI_FAN is not set -CONFIG_ACPI_HOTPLUG_CPU=y -CONFIG_ACPI_HOTPLUG_IOAPIC=y -# CONFIG_ACPI_I2C_OPREGION is not set -CONFIG_ACPI_LEGACY_TABLES_LOOKUP=y -# CONFIG_ACPI_PCI_SLOT is not set -CONFIG_ACPI_PROCESSOR=y -# CONFIG_ACPI_PROCESSOR_AGGREGATOR is not set -CONFIG_ACPI_PROCESSOR_CSTATE=y -CONFIG_ACPI_PROCESSOR_IDLE=y -# CONFIG_ACPI_PROCFS_POWER is not set -CONFIG_ACPI_REV_OVERRIDE_POSSIBLE=y -# CONFIG_ACPI_SBS is not set -CONFIG_ACPI_SYSTEM_POWER_STATES_SUPPORT=y -CONFIG_ACPI_THERMAL=y -CONFIG_ACPI_VIDEO=y -# CONFIG_ACPI_WMI is not set -CONFIG_AGP=y -# CONFIG_AGP_ALI is not set -# CONFIG_AGP_AMD is not set -# CONFIG_AGP_AMD64 is not set -# CONFIG_AGP_ATI is not set -# CONFIG_AGP_EFFICEON is not set -CONFIG_AGP_INTEL=y -# CONFIG_AGP_NVIDIA is not set -# CONFIG_AGP_SIS is not set -# CONFIG_AGP_SWORKS is not set -# CONFIG_AGP_VIA is not set -# CONFIG_APM is not set -CONFIG_ARCH_HAS_ACPI_TABLE_UPGRADE=y -CONFIG_ARCH_MIGHT_HAVE_ACPI_PDC=y -CONFIG_BACKLIGHT_CLASS_DEVICE=y -CONFIG_BACKLIGHT_GENERIC=y -CONFIG_BACKLIGHT_LCD_SUPPORT=y -CONFIG_BALLOON_COMPACTION=y -CONFIG_BLK_DEV_SR=y -# CONFIG_BLK_DEV_SR_VENDOR is not set -CONFIG_BLK_MQ_VIRTIO=y -# CONFIG_BOOTPARAM_HOTPLUG_CPU0 is not set -CONFIG_CONNECTOR=y -# CONFIG_CPU_HOTPLUG_STATE_CONTROL is not set -CONFIG_CPU_IDLE_GOV_MENU=y -CONFIG_CPU_RMAP=y -CONFIG_CRYPTO_AEAD=y -CONFIG_CRYPTO_AEAD2=y -CONFIG_CRYPTO_MANAGER=y -CONFIG_CRYPTO_MANAGER2=y -CONFIG_CRYPTO_NULL2=y -# CONFIG_DEBUG_HOTPLUG_CPU0 is not set -CONFIG_DMA_SHARED_BUFFER=y -# CONFIG_DPTF_POWER is not set -CONFIG_DRM=y -# CONFIG_DRM_AMDGPU is not set -# CONFIG_DRM_AMDGPU_CIK is not set -# CONFIG_DRM_AMDGPU_GART_DEBUGFS is not set -# CONFIG_DRM_AMDGPU_SI is not set -# CONFIG_DRM_AMDGPU_USERPTR is not set -# CONFIG_DRM_AMD_ACP is not set -CONFIG_DRM_BOCHS=y -CONFIG_DRM_BRIDGE=y -CONFIG_DRM_FBDEV_EMULATION=y -CONFIG_DRM_FBDEV_OVERALLOC=100 -# CONFIG_DRM_GMA500 is not set -CONFIG_DRM_I915=y -# CONFIG_DRM_I915_ALPHA_SUPPORT is not set -CONFIG_DRM_I915_CAPTURE_ERROR=y -CONFIG_DRM_I915_COMPRESS_ERROR=y -# CONFIG_DRM_I915_DEBUG is not set -# CONFIG_DRM_I915_DEBUG_VBLANK_EVADE is not set -# CONFIG_DRM_I915_LOW_LEVEL_TRACEPOINTS is not set -# CONFIG_DRM_I915_SELFTEST is not set -# CONFIG_DRM_I915_SW_FENCE_CHECK_DAG is not set -# CONFIG_DRM_I915_SW_FENCE_DEBUG_OBJECTS is not set -CONFIG_DRM_I915_USERPTR=y -# CONFIG_DRM_I915_WERROR is not set -CONFIG_DRM_KMS_FB_HELPER=y -CONFIG_DRM_KMS_HELPER=y -CONFIG_DRM_MIPI_DSI=y -CONFIG_DRM_PANEL=y -CONFIG_DRM_PANEL_BRIDGE=y -# CONFIG_DRM_RADEON is not set -# CONFIG_DRM_RADEON_USERPTR is not set -CONFIG_DRM_TTM=y -CONFIG_DRM_VIRTIO_GPU=y -# CONFIG_DRM_VMWGFX is not set -CONFIG_EARLY_PRINTK_EFI=y -# CONFIG_EBC_C384_WDT is not set -CONFIG_EFI=y -CONFIG_EFIVAR_FS=m -# CONFIG_EFI_BOOTLOADER_CONTROL is not set -# CONFIG_EFI_CAPSULE_LOADER is not set -# CONFIG_EFI_CAPSULE_QUIRK_QUARK_CSH is not set -# CONFIG_EFI_DEV_PATH_PARSER is not set -CONFIG_EFI_ESRT=y -# CONFIG_EFI_FAKE_MEMMAP is not set -# CONFIG_EFI_PGT_DUMP is not set -CONFIG_EFI_RUNTIME_MAP=y -CONFIG_EFI_RUNTIME_WRAPPERS=y -CONFIG_EFI_STUB=y -# CONFIG_EFI_TEST is not set -CONFIG_EFI_VARS=y -# CONFIG_EISA is not set -# CONFIG_EL3 is not set -CONFIG_FB=y -CONFIG_FB_CFB_COPYAREA=y -CONFIG_FB_CFB_FILLRECT=y -CONFIG_FB_CFB_IMAGEBLIT=y -CONFIG_FB_CMDLINE=y -CONFIG_FB_DEFERRED_IO=y -CONFIG_FB_EFI=y -CONFIG_FB_HYPERV=y -# CONFIG_FB_I810 is not set -# CONFIG_FB_PROVIDE_GET_FB_UNMAPPED_AREA is not set -CONFIG_FB_SYS_COPYAREA=y -CONFIG_FB_SYS_FILLRECT=y -CONFIG_FB_SYS_FOPS=y -CONFIG_FB_SYS_IMAGEBLIT=y -# CONFIG_FB_VESA is not set -# CONFIG_FONTS is not set -CONFIG_FONT_8x16=y -CONFIG_FONT_8x8=y -CONFIG_FONT_SUPPORT=y -CONFIG_FRAMEBUFFER_CONSOLE=y -CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y -# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set -CONFIG_FREEZER=y -CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y -CONFIG_GENERIC_IRQ_MIGRATION=y -CONFIG_GENERIC_PENDING_IRQ=y -CONFIG_GENERIC_PINCONF=y -CONFIG_GPIOLIB=y -CONFIG_GPIOLIB_IRQCHIP=y -# CONFIG_GPIO_104_DIO_48E is not set -# CONFIG_GPIO_104_IDIO_16 is not set -# CONFIG_GPIO_104_IDI_48 is not set -CONFIG_GPIO_ACPI=y -CONFIG_HAVE_ACPI_APEI=y -CONFIG_HAVE_ACPI_APEI_NMI=y -CONFIG_HAVE_KVM_CPU_RELAX_INTERCEPT=y -CONFIG_HAVE_KVM_EVENTFD=y -CONFIG_HAVE_KVM_IRQCHIP=y -CONFIG_HAVE_KVM_IRQFD=y -CONFIG_HAVE_KVM_IRQ_BYPASS=y -CONFIG_HAVE_KVM_IRQ_ROUTING=y -CONFIG_HAVE_KVM_MSI=y -CONFIG_HDMI=y -CONFIG_HIBERNATE_CALLBACKS=y -CONFIG_HID_BATTERY_STRENGTH=y -CONFIG_HID_GENERIC=y -CONFIG_HID_HYPERV_MOUSE=y -CONFIG_HOTPLUG_CPU=y -CONFIG_HOTPLUG_PCI=y -CONFIG_HOTPLUG_PCI_ACPI=y -# CONFIG_HOTPLUG_PCI_ACPI_IBM is not set -# CONFIG_HOTPLUG_PCI_COMPAQ is not set -# CONFIG_HOTPLUG_PCI_CPCI is not set -# CONFIG_HOTPLUG_PCI_IBM is not set -CONFIG_HOTPLUG_PCI_PCIE=y -# CONFIG_HOTPLUG_PCI_SHPC is not set -CONFIG_HOTPLUG_SMT=y -CONFIG_HPET=y -CONFIG_HPET_MMAP=y -# CONFIG_HP_ACCEL is not set -CONFIG_HVC_DRIVER=y -CONFIG_HVC_IRQ=y -CONFIG_HVC_XEN=y -CONFIG_HVC_XEN_FRONTEND=y -CONFIG_HWMON=y -CONFIG_HWMON_VID=y -CONFIG_HW_RANDOM_VIRTIO=y -CONFIG_HYPERV=y -CONFIG_HYPERVISOR_GUEST=y -CONFIG_HYPERV_BALLOON=y -CONFIG_HYPERV_KEYBOARD=y -CONFIG_HYPERV_NET=y -CONFIG_HYPERV_STORAGE=y -CONFIG_HYPERV_UTILS=y -CONFIG_I2C=y -CONFIG_I2C_ALGOBIT=y -CONFIG_I2C_BOARDINFO=y -CONFIG_INPUT_MOUSE=y -CONFIG_INPUT_MOUSEDEV=y -CONFIG_INPUT_MOUSEDEV_PSAUX=y -CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 -CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 -CONFIG_INPUT_XEN_KBDDEV_FRONTEND=y -CONFIG_INTEL_GTT=y -CONFIG_INTEL_IDLE=y -# CONFIG_INTEL_INT0002_VGPIO is not set -# CONFIG_INTEL_IPS is not set -# CONFIG_INTEL_MENLOW is not set -CONFIG_INTEL_PCH_THERMAL=y -# CONFIG_INTEL_PMC_IPC is not set -CONFIG_INTEL_SOC_DTS_IOSF_CORE=y -CONFIG_INTEL_SOC_DTS_THERMAL=y -CONFIG_INTERVAL_TREE=y -CONFIG_IOSF_MBI=y -# CONFIG_IOSF_MBI_DEBUG is not set -CONFIG_IRQ_BYPASS_MANAGER=y -CONFIG_ISA=y -CONFIG_ISAPNP=y -CONFIG_ISA_BUS_API=y -# CONFIG_ISCSI_IBFT is not set -# CONFIG_ISCSI_IBFT_FIND is not set -CONFIG_ISO9660_FS=y -# CONFIG_JOLIET is not set -CONFIG_KVM=y -CONFIG_KVM_AMD=y -CONFIG_KVM_ASYNC_PF=y -# CONFIG_KVM_DEBUG_FS is not set -CONFIG_KVM_GENERIC_DIRTYLOG_READ_PROTECT=y -CONFIG_KVM_GUEST=y -CONFIG_KVM_INTEL=y -CONFIG_KVM_MMIO=y -CONFIG_KVM_VFIO=y -# CONFIG_LANCE is not set -# CONFIG_LCD_CLASS_DEVICE is not set -CONFIG_LOCK_SPIN_ON_OWNER=y -# CONFIG_M586MMX is not set -# CONFIG_MDA_CONSOLE is not set -CONFIG_MEMORY_BALLOON=y -CONFIG_MFD_CORE=y -CONFIG_MFD_INTEL_LPSS=y -CONFIG_MFD_INTEL_LPSS_ACPI=y -# CONFIG_MIXCOMWD is not set -CONFIG_MMC=y -CONFIG_MMC_BLOCK=y -CONFIG_MMC_RICOH_MMC=y -CONFIG_MMC_SDHCI=y -CONFIG_MMC_SDHCI_PCI=y -# CONFIG_MMC_SDHCI_PLTFM is not set -# CONFIG_MMC_TIFM_SD is not set -# CONFIG_MMC_WBSD is not set -CONFIG_MMU_NOTIFIER=y -# CONFIG_MOUSE_BCM5974 is not set -# CONFIG_MOUSE_CYAPA is not set -CONFIG_MOUSE_PS2=y -CONFIG_MOUSE_PS2_ALPS=y -# CONFIG_MOUSE_PS2_BYD is not set -# CONFIG_MOUSE_PS2_CYPRESS is not set -# CONFIG_MOUSE_PS2_ELANTECH is not set -CONFIG_MOUSE_PS2_LIFEBOOK=y -CONFIG_MOUSE_PS2_LOGIPS2PP=y -CONFIG_MOUSE_PS2_SMBUS=y -CONFIG_MOUSE_PS2_SYNAPTICS=y -CONFIG_MOUSE_PS2_SYNAPTICS_SMBUS=y -# CONFIG_MOUSE_PS2_TOUCHKIT is not set -CONFIG_MOUSE_PS2_TRACKPOINT=y -# CONFIG_MOUSE_PS2_VMMOUSE is not set -# CONFIG_MOUSE_SERIAL is not set -# CONFIG_MOUSE_VSXXXAA is not set -CONFIG_MPENTIUM4=y -CONFIG_MUTEX_SPIN_ON_OWNER=y -CONFIG_NET_FLOW_LIMIT=y -CONFIG_NO_HZ=y -CONFIG_NR_CPUS=4 -CONFIG_PADATA=y -CONFIG_PARAVIRT=y -CONFIG_PARAVIRT_CLOCK=y -# CONFIG_PARAVIRT_DEBUG is not set -CONFIG_PARAVIRT_SPINLOCKS=y -CONFIG_PATA_AMD=y -CONFIG_PATA_ATIIXP=y -CONFIG_PATA_MPIIX=y -CONFIG_PATA_OLDPIIX=y -CONFIG_PATA_PLATFORM=y -CONFIG_PATA_SC1200=y -CONFIG_PATA_VIA=y -CONFIG_PCIEAER=y -CONFIG_PCIEPORTBUS=y -CONFIG_PCIE_PME=y -CONFIG_PCI_MMCONFIG=y -CONFIG_PCI_XEN=y -# CONFIG_PCWATCHDOG is not set -CONFIG_PINCTRL=y -CONFIG_PINCTRL_BAYTRAIL=y -CONFIG_PINCTRL_BROXTON=y -CONFIG_PINCTRL_CANNONLAKE=y -CONFIG_PINCTRL_CHERRYVIEW=y -CONFIG_PINCTRL_DENVERTON=y -CONFIG_PINCTRL_GEMINILAKE=y -CONFIG_PINCTRL_INTEL=y -# CONFIG_PINCTRL_LEWISBURG is not set -CONFIG_PINCTRL_SUNRISEPOINT=y -CONFIG_PM=y -# CONFIG_PMIC_OPREGION is not set -CONFIG_PM_CLK=y -# CONFIG_PM_DEBUG is not set -CONFIG_PM_SLEEP=y -CONFIG_PM_SLEEP_SMP=y -CONFIG_PNP=y -CONFIG_PNPACPI=y -# CONFIG_PNPBIOS is not set -CONFIG_PNP_DEBUG_MESSAGES=y -CONFIG_PREEMPT_NOTIFIERS=y -CONFIG_PROC_EVENTS=y -# CONFIG_PVPANIC is not set -CONFIG_QUEUED_RWLOCKS=y -CONFIG_QUEUED_SPINLOCKS=y -# CONFIG_RANDOMIZE_BASE is not set -CONFIG_RAS=y -CONFIG_RCU_NEED_SEGCBLIST=y -CONFIG_RCU_STALL_COMMON=y -CONFIG_REGMAP=y -CONFIG_REGMAP_I2C=y -CONFIG_RELAY=y -CONFIG_RELOCATABLE=y -CONFIG_RESET_ATTACK_MITIGATION=y -CONFIG_RFS_ACCEL=y -CONFIG_RPS=y -CONFIG_RTC_I2C_AND_SPI=y -CONFIG_RWSEM_SPIN_ON_OWNER=y -# CONFIG_SAMSUNG_Q10 is not set -CONFIG_SATA_AHCI=y -CONFIG_SATA_VIA=y -CONFIG_SCHED_INFO=y -CONFIG_SCHED_SMT=y -CONFIG_SCSI_VIRTIO=y -CONFIG_SENSORS_CORETEMP=y -CONFIG_SENSORS_FAM15H_POWER=y -CONFIG_SENSORS_I5500=y -CONFIG_SENSORS_K10TEMP=y -CONFIG_SENSORS_K8TEMP=y -CONFIG_SENSORS_VIA_CPUTEMP=y -CONFIG_SERIAL_8250_PNP=y -CONFIG_SMP=y -# CONFIG_SURFACE_PRO3_BUTTON is not set -CONFIG_SWIOTLB_XEN=y -CONFIG_SYNC_FILE=y -CONFIG_SYS_HYPERVISOR=y -CONFIG_TASKSTATS=y -CONFIG_TASK_DELAY_ACCT=y -CONFIG_THERMAL_GOV_USER_SPACE=y -CONFIG_THERMAL_HWMON=y -CONFIG_THERMAL_WRITABLE_TRIPS=y -# CONFIG_TOSHIBA_BT_RFKILL is not set -CONFIG_TREE_RCU=y -CONFIG_TREE_SRCU=y -CONFIG_UCS2_STRING=y -CONFIG_USB_STORAGE=y -CONFIG_USER_RETURN_NOTIFIER=y -CONFIG_VGACON_SOFT_SCROLLBACK=y -# CONFIG_VGACON_SOFT_SCROLLBACK_PERSISTENT_ENABLE_BY_DEFAULT is not set -CONFIG_VGACON_SOFT_SCROLLBACK_SIZE=64 -CONFIG_VHOST=y -CONFIG_VHOST_NET=y -CONFIG_VIRTIO=y -CONFIG_VIRTIO_BALLOON=y -CONFIG_VIRTIO_BLK=y -CONFIG_VIRTIO_CONSOLE=y -CONFIG_VIRTIO_INPUT=y -CONFIG_VIRTIO_MMIO=y -# CONFIG_VIRTIO_MMIO_CMDLINE_DEVICES is not set -CONFIG_VIRTIO_NET=y -CONFIG_VIRTIO_PCI=y -CONFIG_VIRTIO_PCI_LEGACY=y -CONFIG_VIRTUALIZATION=y -CONFIG_VT_CONSOLE_SLEEP=y -# CONFIG_WDT is not set -CONFIG_X86_32_SMP=y -CONFIG_X86_ACPI_CPUFREQ=y -# CONFIG_X86_ACPI_CPUFREQ_CPB is not set -CONFIG_X86_AMD_FREQ_SENSITIVITY=y -# CONFIG_X86_AMD_PLATFORM_DEVICE is not set -# CONFIG_X86_BIGSMP is not set -CONFIG_X86_CMOV=y -CONFIG_X86_CPUID=y -CONFIG_X86_DEBUGCTLMSR=y -# CONFIG_X86_E_POWERSAVER is not set -CONFIG_X86_INTEL_LPSS=y -CONFIG_X86_INTEL_PSTATE=y -CONFIG_X86_INTERNODE_CACHE_SHIFT=7 -CONFIG_X86_L1_CACHE_SHIFT=7 -# CONFIG_X86_LONGHAUL is not set -CONFIG_X86_NEED_RELOCS=y -# CONFIG_X86_PCC_CPUFREQ is not set -CONFIG_X86_PKG_TEMP_THERMAL=y -# CONFIG_X86_PMEM_LEGACY is not set -CONFIG_X86_PM_TIMER=y -# CONFIG_X86_POWERNOW_K8 is not set -CONFIG_X86_USE_PPRO_CHECKSUM=y -CONFIG_XEN=y -CONFIG_XENFS=y -CONFIG_XEN_ACPI=y -CONFIG_XEN_ACPI_PROCESSOR=y -CONFIG_XEN_AUTO_XLATE=y -# CONFIG_XEN_BACKEND is not set -CONFIG_XEN_BALLOON=y -CONFIG_XEN_BLKDEV_FRONTEND=y -CONFIG_XEN_COMPAT_XENFS=y -CONFIG_XEN_DEBUG_FS=y -CONFIG_XEN_DEV_EVTCHN=y -CONFIG_XEN_DOM0=y -CONFIG_XEN_FBDEV_FRONTEND=y -CONFIG_XEN_GNTDEV=y -CONFIG_XEN_GRANT_DEV_ALLOC=y -CONFIG_XEN_HAVE_PVMMU=y -CONFIG_XEN_HAVE_VPMU=y -CONFIG_XEN_NETDEV_FRONTEND=y -CONFIG_XEN_PCIDEV_FRONTEND=y -CONFIG_XEN_PRIVCMD=y -CONFIG_XEN_PV=y -CONFIG_XEN_PVH=y -CONFIG_XEN_PVHVM=y -CONFIG_XEN_PVHVM_SMP=y -CONFIG_XEN_PV_SMP=y -CONFIG_XEN_SAVE_RESTORE=y -CONFIG_XEN_SCRUB_PAGES=y -CONFIG_XEN_SCSI_FRONTEND=y -CONFIG_XEN_SYMS=y -CONFIG_XEN_SYS_HYPERVISOR=y -CONFIG_XEN_WDT=y -CONFIG_XEN_XENBUS_FRONTEND=y -CONFIG_XPS=y -CONFIG_ZLIB_DEFLATE=y diff --git a/target/linux/x86/geode/config-4.14 b/target/linux/x86/geode/config-4.14 deleted file mode 100644 index 796aba7cd2fb..000000000000 --- a/target/linux/x86/geode/config-4.14 +++ /dev/null @@ -1,145 +0,0 @@ -# CONFIG_3C515 is not set -CONFIG_8139CP=y -CONFIG_8139TOO=y -CONFIG_8139TOO_8129=y -CONFIG_8139TOO_PIO=y -# CONFIG_8139TOO_TUNE_TWISTER is not set -# CONFIG_8139_OLD_RX_RESET is not set -CONFIG_ACPI=y -CONFIG_ACPI_AC=y -# CONFIG_ACPI_BATTERY is not set -# CONFIG_ACPI_CMPC is not set -# CONFIG_ACPI_CONTAINER is not set -CONFIG_ACPI_CPU_FREQ_PSS=y -# CONFIG_ACPI_CUSTOM_DSDT is not set -# CONFIG_ACPI_DEBUG is not set -# CONFIG_ACPI_DEBUGGER is not set -# CONFIG_ACPI_DOCK is not set -# CONFIG_ACPI_EC_DEBUGFS is not set -CONFIG_ACPI_FAN=y -CONFIG_ACPI_HOTPLUG_IOAPIC=y -CONFIG_ACPI_I2C_OPREGION=y -CONFIG_ACPI_LEGACY_TABLES_LOOKUP=y -# CONFIG_ACPI_PCI_SLOT is not set -CONFIG_ACPI_PROCESSOR=y -# CONFIG_ACPI_PROCESSOR_AGGREGATOR is not set -CONFIG_ACPI_PROCESSOR_CSTATE=y -CONFIG_ACPI_PROCESSOR_IDLE=y -# CONFIG_ACPI_PROCFS_POWER is not set -CONFIG_ACPI_REV_OVERRIDE_POSSIBLE=y -# CONFIG_ACPI_SBS is not set -CONFIG_ACPI_SYSTEM_POWER_STATES_SUPPORT=y -CONFIG_ACPI_THERMAL=y -# CONFIG_ACPI_WMI is not set -CONFIG_ALIX=y -CONFIG_ARCH_HAS_ACPI_TABLE_UPGRADE=y -CONFIG_ARCH_MIGHT_HAVE_ACPI_PDC=y -# CONFIG_ATA_PIIX is not set -CONFIG_CS5535_CLOCK_EVENT_SRC=y -CONFIG_CS5535_MFGPT=y -CONFIG_CS5535_MFGPT_DEFAULT_IRQ=7 -# CONFIG_DPTF_POWER is not set -# CONFIG_EBC_C384_WDT is not set -# CONFIG_EFI_DEV_PATH_PARSER is not set -# CONFIG_EISA is not set -# CONFIG_EL3 is not set -CONFIG_GEODE_WDT=y -CONFIG_GEOS=y -CONFIG_GPIOLIB=y -# CONFIG_GPIO_104_DIO_48E is not set -# CONFIG_GPIO_104_IDIO_16 is not set -# CONFIG_GPIO_104_IDI_48 is not set -CONFIG_GPIO_ACPI=y -CONFIG_GPIO_CS5535=y -CONFIG_GPIO_SYSFS=y -CONFIG_HAVE_ACPI_APEI=y -CONFIG_HAVE_ACPI_APEI_NMI=y -CONFIG_HIGHMEM4G=y -# CONFIG_HIGHMEM64G is not set -# CONFIG_HPET is not set -# CONFIG_HP_ACCEL is not set -CONFIG_HWMON=y -CONFIG_I2C=y -CONFIG_I2C_ALGOBIT=y -CONFIG_I2C_ALGOPCA=y -CONFIG_I2C_ALGOPCF=y -CONFIG_I2C_BOARDINFO=y -# CONFIG_INTEL_INT0002_VGPIO is not set -# CONFIG_INTEL_IPS is not set -# CONFIG_INTEL_MENLOW is not set -# CONFIG_INTEL_PMC_IPC is not set -CONFIG_IOSF_MBI=y -# CONFIG_IOSF_MBI_DEBUG is not set -CONFIG_ISA=y -# CONFIG_ISAPNP is not set -CONFIG_ISA_BUS_API=y -# CONFIG_ISCSI_IBFT is not set -# CONFIG_ISCSI_IBFT_FIND is not set -# CONFIG_LANCE is not set -CONFIG_LEDS_GPIO=y -# CONFIG_M586MMX is not set -# CONFIG_MDA_CONSOLE is not set -CONFIG_MFD_CORE=y -CONFIG_MFD_CS5535=y -# CONFIG_MFD_INTEL_LPSS_ACPI is not set -CONFIG_MGEODEGX1=y -# CONFIG_MIXCOMWD is not set -CONFIG_NATSEMI=y -CONFIG_NET5501=y -CONFIG_NSC_GPIO=y -# CONFIG_OLPC is not set -CONFIG_PATA_CS5520=y -CONFIG_PATA_CS5530=y -CONFIG_PATA_CS5535=y -CONFIG_PATA_CS5536=y -CONFIG_PATA_SC1200=y -CONFIG_PC8736x_GPIO=y -CONFIG_PCI_MMCONFIG=y -# CONFIG_PCWATCHDOG is not set -CONFIG_PGTABLE_LEVELS=2 -# CONFIG_PHYS_ADDR_T_64BIT is not set -CONFIG_PINCTRL=y -# CONFIG_PINCTRL_BAYTRAIL is not set -# CONFIG_PINCTRL_BROXTON is not set -# CONFIG_PINCTRL_CANNONLAKE is not set -# CONFIG_PINCTRL_CHERRYVIEW is not set -# CONFIG_PINCTRL_DENVERTON is not set -# CONFIG_PINCTRL_GEMINILAKE is not set -# CONFIG_PINCTRL_LEWISBURG is not set -# CONFIG_PINCTRL_SUNRISEPOINT is not set -# CONFIG_PMIC_OPREGION is not set -CONFIG_PNP=y -CONFIG_PNPACPI=y -# CONFIG_PNPBIOS is not set -CONFIG_PNP_DEBUG_MESSAGES=y -# CONFIG_PVPANIC is not set -CONFIG_REGMAP=y -CONFIG_REGMAP_I2C=y -CONFIG_RTC_I2C_AND_SPI=y -# CONFIG_SAMSUNG_Q10 is not set -CONFIG_SC1200_WDT=y -CONFIG_SCx200_ACB=y -CONFIG_SCx200_WDT=y -CONFIG_SENSORS_LM90=y -CONFIG_SERIAL_8250_PNP=y -# CONFIG_SURFACE_PRO3_BUTTON is not set -# CONFIG_TOSHIBA_BT_RFKILL is not set -# CONFIG_USB_UHCI_HCD is not set -CONFIG_VGACON_SOFT_SCROLLBACK=y -# CONFIG_VGACON_SOFT_SCROLLBACK_PERSISTENT_ENABLE_BY_DEFAULT is not set -CONFIG_VGACON_SOFT_SCROLLBACK_SIZE=64 -CONFIG_VIA_RHINE=y -CONFIG_VIA_RHINE_MMIO=y -# CONFIG_WDT is not set -# CONFIG_X86_ACPI_CPUFREQ is not set -# CONFIG_X86_AMD_PLATFORM_DEVICE is not set -CONFIG_X86_CPUID=y -CONFIG_X86_DEBUGCTLMSR=y -# CONFIG_X86_E_POWERSAVER is not set -CONFIG_X86_INTEL_LPSS=y -# CONFIG_X86_LONGHAUL is not set -# CONFIG_X86_MCE is not set -CONFIG_X86_MINIMUM_CPU_FAMILY=4 -# CONFIG_X86_PCC_CPUFREQ is not set -CONFIG_X86_PM_TIMER=y -CONFIG_X86_REBOOTFIXUPS=y diff --git a/target/linux/x86/legacy/config-4.14 b/target/linux/x86/legacy/config-4.14 deleted file mode 100644 index 6fa2d083ab3e..000000000000 --- a/target/linux/x86/legacy/config-4.14 +++ /dev/null @@ -1,215 +0,0 @@ -# CONFIG_3C515 is not set -CONFIG_ACPI=y -CONFIG_ACPI_AC=y -CONFIG_ACPI_BATTERY=y -CONFIG_ACPI_BUTTON=y -# CONFIG_ACPI_CMPC is not set -# CONFIG_ACPI_CONTAINER is not set -CONFIG_ACPI_CPU_FREQ_PSS=y -# CONFIG_ACPI_CUSTOM_DSDT is not set -# CONFIG_ACPI_DEBUG is not set -# CONFIG_ACPI_DEBUGGER is not set -# CONFIG_ACPI_DOCK is not set -# CONFIG_ACPI_EC_DEBUGFS is not set -# CONFIG_ACPI_FAN is not set -CONFIG_ACPI_HOTPLUG_IOAPIC=y -# CONFIG_ACPI_I2C_OPREGION is not set -CONFIG_ACPI_LEGACY_TABLES_LOOKUP=y -# CONFIG_ACPI_PCI_SLOT is not set -CONFIG_ACPI_PROCESSOR=y -# CONFIG_ACPI_PROCESSOR_AGGREGATOR is not set -CONFIG_ACPI_PROCESSOR_CSTATE=y -CONFIG_ACPI_PROCESSOR_IDLE=y -# CONFIG_ACPI_PROCFS_POWER is not set -CONFIG_ACPI_REV_OVERRIDE_POSSIBLE=y -# CONFIG_ACPI_SBS is not set -CONFIG_ACPI_SYSTEM_POWER_STATES_SUPPORT=y -CONFIG_ACPI_THERMAL=y -CONFIG_ACPI_VIDEO=y -# CONFIG_ACPI_WMI is not set -CONFIG_AGP=y -# CONFIG_AGP_ALI is not set -# CONFIG_AGP_AMD is not set -# CONFIG_AGP_AMD64 is not set -# CONFIG_AGP_ATI is not set -# CONFIG_AGP_EFFICEON is not set -CONFIG_AGP_INTEL=y -# CONFIG_AGP_NVIDIA is not set -# CONFIG_AGP_SIS is not set -# CONFIG_AGP_SWORKS is not set -# CONFIG_AGP_VIA is not set -CONFIG_ARCH_HAS_ACPI_TABLE_UPGRADE=y -CONFIG_ARCH_MIGHT_HAVE_ACPI_PDC=y -CONFIG_BACKLIGHT_CLASS_DEVICE=y -CONFIG_BACKLIGHT_GENERIC=y -CONFIG_BACKLIGHT_LCD_SUPPORT=y -CONFIG_BLK_DEV_SR=y -# CONFIG_BLK_DEV_SR_VENDOR is not set -CONFIG_CPU_IDLE_GOV_MENU=y -CONFIG_DMA_SHARED_BUFFER=y -# CONFIG_DPTF_POWER is not set -CONFIG_DRM=y -CONFIG_DRM_AMDGPU=y -# CONFIG_DRM_AMDGPU_CIK is not set -# CONFIG_DRM_AMDGPU_GART_DEBUGFS is not set -# CONFIG_DRM_AMDGPU_SI is not set -# CONFIG_DRM_AMDGPU_USERPTR is not set -# CONFIG_DRM_AMD_ACP is not set -CONFIG_DRM_BOCHS=y -CONFIG_DRM_BRIDGE=y -CONFIG_DRM_FBDEV_EMULATION=y -CONFIG_DRM_FBDEV_OVERALLOC=100 -# CONFIG_DRM_GMA500 is not set -CONFIG_DRM_I915=y -# CONFIG_DRM_I915_ALPHA_SUPPORT is not set -CONFIG_DRM_I915_CAPTURE_ERROR=y -CONFIG_DRM_I915_COMPRESS_ERROR=y -# CONFIG_DRM_I915_DEBUG is not set -# CONFIG_DRM_I915_DEBUG_VBLANK_EVADE is not set -# CONFIG_DRM_I915_LOW_LEVEL_TRACEPOINTS is not set -# CONFIG_DRM_I915_SELFTEST is not set -# CONFIG_DRM_I915_SW_FENCE_CHECK_DAG is not set -# CONFIG_DRM_I915_SW_FENCE_DEBUG_OBJECTS is not set -CONFIG_DRM_I915_USERPTR=y -# CONFIG_DRM_I915_WERROR is not set -CONFIG_DRM_KMS_FB_HELPER=y -CONFIG_DRM_KMS_HELPER=y -CONFIG_DRM_MIPI_DSI=y -CONFIG_DRM_PANEL=y -CONFIG_DRM_PANEL_BRIDGE=y -CONFIG_DRM_RADEON=y -# CONFIG_DRM_RADEON_USERPTR is not set -CONFIG_DRM_TTM=y -# CONFIG_DRM_VMWGFX is not set -# CONFIG_EBC_C384_WDT is not set -# CONFIG_EFI_DEV_PATH_PARSER is not set -# CONFIG_EISA is not set -# CONFIG_EL3 is not set -CONFIG_FB=y -CONFIG_FB_CFB_COPYAREA=y -CONFIG_FB_CFB_FILLRECT=y -CONFIG_FB_CFB_IMAGEBLIT=y -CONFIG_FB_CMDLINE=y -CONFIG_FB_DEFERRED_IO=y -# CONFIG_FB_I810 is not set -# CONFIG_FB_PROVIDE_GET_FB_UNMAPPED_AREA is not set -CONFIG_FB_SYS_COPYAREA=y -CONFIG_FB_SYS_FILLRECT=y -CONFIG_FB_SYS_FOPS=y -CONFIG_FB_SYS_IMAGEBLIT=y -# CONFIG_FB_VESA is not set -# CONFIG_FONTS is not set -CONFIG_FONT_8x16=y -CONFIG_FONT_8x8=y -CONFIG_FONT_SUPPORT=y -CONFIG_FRAMEBUFFER_CONSOLE=y -CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y -# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set -CONFIG_HAVE_ACPI_APEI=y -CONFIG_HAVE_ACPI_APEI_NMI=y -CONFIG_HDMI=y -CONFIG_HID_BATTERY_STRENGTH=y -# CONFIG_HIGHMEM64G is not set -CONFIG_HPET=y -CONFIG_HPET_MMAP=y -# CONFIG_HP_ACCEL is not set -CONFIG_HWMON=y -CONFIG_I2C=y -CONFIG_I2C_ALGOBIT=y -CONFIG_I2C_BOARDINFO=y -CONFIG_INPUT_MOUSE=y -CONFIG_INPUT_MOUSEDEV=y -CONFIG_INPUT_MOUSEDEV_PSAUX=y -CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 -CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 -CONFIG_INTEL_GTT=y -CONFIG_INTEL_IDLE=y -# CONFIG_INTEL_IPS is not set -# CONFIG_INTEL_MENLOW is not set -# CONFIG_INTEL_PMC_IPC is not set -CONFIG_INTERVAL_TREE=y -CONFIG_IOSF_MBI=y -# CONFIG_IOSF_MBI_DEBUG is not set -CONFIG_ISA=y -CONFIG_ISAPNP=y -CONFIG_ISA_BUS_API=y -# CONFIG_ISCSI_IBFT is not set -# CONFIG_ISCSI_IBFT_FIND is not set -CONFIG_ISO9660_FS=y -# CONFIG_JOLIET is not set -# CONFIG_LANCE is not set -# CONFIG_LCD_CLASS_DEVICE is not set -# CONFIG_MDA_CONSOLE is not set -CONFIG_MFD_CORE=y -CONFIG_MFD_INTEL_LPSS=y -CONFIG_MFD_INTEL_LPSS_ACPI=y -# CONFIG_MIXCOMWD is not set -CONFIG_MMU_NOTIFIER=y -# CONFIG_MOUSE_BCM5974 is not set -# CONFIG_MOUSE_CYAPA is not set -CONFIG_MOUSE_PS2=y -CONFIG_MOUSE_PS2_ALPS=y -# CONFIG_MOUSE_PS2_BYD is not set -# CONFIG_MOUSE_PS2_CYPRESS is not set -# CONFIG_MOUSE_PS2_ELANTECH is not set -CONFIG_MOUSE_PS2_LIFEBOOK=y -CONFIG_MOUSE_PS2_LOGIPS2PP=y -CONFIG_MOUSE_PS2_SMBUS=y -CONFIG_MOUSE_PS2_SYNAPTICS=y -CONFIG_MOUSE_PS2_SYNAPTICS_SMBUS=y -# CONFIG_MOUSE_PS2_TOUCHKIT is not set -CONFIG_MOUSE_PS2_TRACKPOINT=y -# CONFIG_MOUSE_SERIAL is not set -# CONFIG_MOUSE_VSXXXAA is not set -CONFIG_NOHIGHMEM=y -CONFIG_NO_HZ=y -# CONFIG_OLPC is not set -CONFIG_PATA_AMD=y -CONFIG_PATA_ATIIXP=y -CONFIG_PATA_LEGACY=y -CONFIG_PATA_MPIIX=y -CONFIG_PATA_OLDPIIX=y -CONFIG_PATA_PLATFORM=y -CONFIG_PATA_SC1200=y -CONFIG_PATA_VIA=y -CONFIG_PCIEAER=y -CONFIG_PCIEPORTBUS=y -CONFIG_PCI_MMCONFIG=y -# CONFIG_PCWATCHDOG is not set -CONFIG_PGTABLE_LEVELS=2 -# CONFIG_PHYS_ADDR_T_64BIT is not set -# CONFIG_PMIC_OPREGION is not set -CONFIG_PNP=y -CONFIG_PNPACPI=y -# CONFIG_PNPBIOS is not set -CONFIG_PNP_DEBUG_MESSAGES=y -# CONFIG_PVPANIC is not set -CONFIG_RAS=y -CONFIG_REGMAP=y -CONFIG_REGMAP_I2C=y -CONFIG_RELAY=y -CONFIG_RTC_I2C_AND_SPI=y -# CONFIG_SAMSUNG_Q10 is not set -CONFIG_SATA_AHCI=y -CONFIG_SERIAL_8250_PNP=y -# CONFIG_SURFACE_PRO3_BUTTON is not set -CONFIG_SYNC_FILE=y -# CONFIG_TOSHIBA_BT_RFKILL is not set -CONFIG_USB_STORAGE=y -CONFIG_VGACON_SOFT_SCROLLBACK=y -# CONFIG_VGACON_SOFT_SCROLLBACK_PERSISTENT_ENABLE_BY_DEFAULT is not set -CONFIG_VGACON_SOFT_SCROLLBACK_SIZE=64 -# CONFIG_WDT is not set -CONFIG_X86_ACPI_CPUFREQ=y -# CONFIG_X86_ACPI_CPUFREQ_CPB is not set -# CONFIG_X86_AMD_FREQ_SENSITIVITY is not set -# CONFIG_X86_AMD_PLATFORM_DEVICE is not set -# CONFIG_X86_E_POWERSAVER is not set -# CONFIG_X86_INTEL_LPSS is not set -# CONFIG_X86_LONGHAUL is not set -CONFIG_X86_MINIMUM_CPU_FAMILY=4 -# CONFIG_X86_PAE is not set -# CONFIG_X86_PCC_CPUFREQ is not set -CONFIG_X86_PM_TIMER=y -# CONFIG_X86_POWERNOW_K8 is not set -CONFIG_ZLIB_DEFLATE=y diff --git a/target/linux/x86/patches-4.14/011-tune_lzma_options.patch b/target/linux/x86/patches-4.14/011-tune_lzma_options.patch deleted file mode 100644 index daed310a1336..000000000000 --- a/target/linux/x86/patches-4.14/011-tune_lzma_options.patch +++ /dev/null @@ -1,22 +0,0 @@ ---- a/scripts/Makefile.lib -+++ b/scripts/Makefile.lib -@@ -348,7 +348,7 @@ cmd_bzip2 = (cat $(filter-out FORCE,$^) - - quiet_cmd_lzma = LZMA $@ - cmd_lzma = (cat $(filter-out FORCE,$^) | \ -- lzma e -d20 -lc1 -lp2 -pb2 -eos -si -so && $(call size_append, $(filter-out FORCE,$^))) > $@ || \ -+ lzma e -lc8 -eos -si -so && $(call size_append, $(filter-out FORCE,$^))) > $@ || \ - (rm -f $@ ; false) - - quiet_cmd_lzo = LZO $@ ---- a/arch/x86/include/asm/boot.h -+++ b/arch/x86/include/asm/boot.h -@@ -24,7 +24,7 @@ - # error "Invalid value for CONFIG_PHYSICAL_ALIGN" - #endif - --#ifdef CONFIG_KERNEL_BZIP2 -+#if defined(CONFIG_KERNEL_BZIP2) || defined(CONFIG_KERNEL_LZMA) - # define BOOT_HEAP_SIZE 0x400000 - #else /* !CONFIG_KERNEL_BZIP2 */ - # define BOOT_HEAP_SIZE 0x10000 diff --git a/target/linux/x86/patches-4.14/100-fix_cs5535_clockevt.patch b/target/linux/x86/patches-4.14/100-fix_cs5535_clockevt.patch deleted file mode 100644 index c3a7fce9ceb1..000000000000 --- a/target/linux/x86/patches-4.14/100-fix_cs5535_clockevt.patch +++ /dev/null @@ -1,12 +0,0 @@ ---- a/drivers/clocksource/cs5535-clockevt.c -+++ b/drivers/clocksource/cs5535-clockevt.c -@@ -130,7 +130,8 @@ static irqreturn_t mfgpt_tick(int irq, v - cs5535_mfgpt_write(cs5535_event_clock, MFGPT_REG_SETUP, - MFGPT_SETUP_CNTEN | MFGPT_SETUP_CMP2); - -- cs5535_clockevent.event_handler(&cs5535_clockevent); -+ if (cs5535_clockevent.event_handler) -+ cs5535_clockevent.event_handler(&cs5535_clockevent); - return IRQ_HANDLED; - } - diff --git a/target/linux/x86/patches-4.14/200-pcengines-apu2-reboot.patch b/target/linux/x86/patches-4.14/200-pcengines-apu2-reboot.patch deleted file mode 100644 index 1426140183d1..000000000000 --- a/target/linux/x86/patches-4.14/200-pcengines-apu2-reboot.patch +++ /dev/null @@ -1,19 +0,0 @@ ---- a/arch/x86/kernel/reboot.c -+++ b/arch/x86/kernel/reboot.c -@@ -469,6 +469,16 @@ static const struct dmi_system_id reboot - }, - }, - -+ /* PC Engines */ -+ { /* Handle problems with rebooting on PC Engines apu2 */ -+ .callback = set_pci_reboot, -+ .ident = "PC Engines apu2", -+ .matches = { -+ DMI_MATCH(DMI_BOARD_VENDOR, "PC Engines"), -+ DMI_MATCH(DMI_BOARD_NAME, "apu2"), -+ }, -+ }, -+ - /* Sony */ - { /* Handle problems with rebooting on Sony VGN-Z540N */ - .callback = set_bios_reboot, diff --git a/target/linux/x86/patches-4.14/800-hwmon-w83627ehf-dont-claim-nct677x.patch b/target/linux/x86/patches-4.14/800-hwmon-w83627ehf-dont-claim-nct677x.patch deleted file mode 100644 index ef2e1333e781..000000000000 --- a/target/linux/x86/patches-4.14/800-hwmon-w83627ehf-dont-claim-nct677x.patch +++ /dev/null @@ -1,30 +0,0 @@ ---- a/drivers/hwmon/w83627ehf.c -+++ b/drivers/hwmon/w83627ehf.c -@@ -2717,8 +2717,8 @@ static int __init w83627ehf_find(int sio - static const char sio_name_W83627UHG[] __initconst = "W83627UHG"; - static const char sio_name_W83667HG[] __initconst = "W83667HG"; - static const char sio_name_W83667HG_B[] __initconst = "W83667HG-B"; -- static const char sio_name_NCT6775[] __initconst = "NCT6775F"; -- static const char sio_name_NCT6776[] __initconst = "NCT6776F"; -+/* static const char sio_name_NCT6775[] __initconst = "NCT6775F"; -+ static const char sio_name_NCT6776[] __initconst = "NCT6776F"; */ - - u16 val; - const char *sio_name; -@@ -2762,14 +2762,14 @@ static int __init w83627ehf_find(int sio - sio_data->kind = w83667hg_b; - sio_name = sio_name_W83667HG_B; - break; -- case SIO_NCT6775_ID: -+/* case SIO_NCT6775_ID: - sio_data->kind = nct6775; - sio_name = sio_name_NCT6775; - break; - case SIO_NCT6776_ID: - sio_data->kind = nct6776; - sio_name = sio_name_NCT6776; -- break; -+ break; */ - default: - if (val != 0xffff) - pr_debug("unsupported chip ID: 0x%04x\n", val);