From patchwork Fri Feb 21 19:35:28 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robin Murphy X-Patchwork-Id: 1242319 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=arm.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 48PMBM1Ct3z9sRN for ; Sat, 22 Feb 2020 06:35:39 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726683AbgBUTfi (ORCPT ); Fri, 21 Feb 2020 14:35:38 -0500 Received: from foss.arm.com ([217.140.110.172]:46646 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726160AbgBUTfh (ORCPT ); Fri, 21 Feb 2020 14:35:37 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 788B531B; Fri, 21 Feb 2020 11:35:37 -0800 (PST) Received: from e121345-lin.cambridge.arm.com (e121345-lin.cambridge.arm.com [10.1.196.37]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id AC3313F6CF; Fri, 21 Feb 2020 11:35:36 -0800 (PST) From: Robin Murphy To: will@kernel.org, catalin.marinas@arm.com, mark.rutland@arm.com Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 1/5] dt-bindings: ARM: Add recent Cortex/Neoverse CPUs Date: Fri, 21 Feb 2020 19:35:28 +0000 Message-Id: <79ef74956befe089d7994ad24ab25132e95e9ac9.1582312530.git.robin.murphy@arm.com> X-Mailer: git-send-email 2.23.0.dirty In-Reply-To: References: MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The CPU group has been busy since we last updated these bindings... Add definitions for all the new Cortex-A and Neoverse cores now available. Signed-off-by: Robin Murphy --- v2: no change, just resending for completeness Documentation/devicetree/bindings/arm/cpus.yaml | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/cpus.yaml b/Documentation/devicetree/bindings/arm/cpus.yaml index 7a9c3ce2dbef..41e22b5320da 100644 --- a/Documentation/devicetree/bindings/arm/cpus.yaml +++ b/Documentation/devicetree/bindings/arm/cpus.yaml @@ -123,11 +123,18 @@ properties: - arm,cortex-a12 - arm,cortex-a15 - arm,cortex-a17 + - arm,cortex-a32 + - arm,cortex-a34 + - arm,cortex-a35 - arm,cortex-a53 - arm,cortex-a55 - arm,cortex-a57 + - arm,cortex-a65 - arm,cortex-a72 - arm,cortex-a73 + - arm,cortex-a75 + - arm,cortex-a76 + - arm,cortex-a77 - arm,cortex-m0 - arm,cortex-m0+ - arm,cortex-m1 @@ -136,6 +143,8 @@ properties: - arm,cortex-r4 - arm,cortex-r5 - arm,cortex-r7 + - arm,neoverse-e1 + - arm,neoverse-n1 - brcm,brahma-b15 - brcm,brahma-b53 - brcm,vulcan From patchwork Fri Feb 21 19:35:29 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robin Murphy X-Patchwork-Id: 1242320 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=arm.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 48PMBN19STz9sRJ for ; Sat, 22 Feb 2020 06:35:40 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726707AbgBUTfj (ORCPT ); Fri, 21 Feb 2020 14:35:39 -0500 Received: from foss.arm.com ([217.140.110.172]:46650 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726160AbgBUTfi (ORCPT ); Fri, 21 Feb 2020 14:35:38 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 800A8FEC; Fri, 21 Feb 2020 11:35:38 -0800 (PST) Received: from e121345-lin.cambridge.arm.com (e121345-lin.cambridge.arm.com [10.1.196.37]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id ADCEE3F6CF; Fri, 21 Feb 2020 11:35:37 -0800 (PST) From: Robin Murphy To: will@kernel.org, catalin.marinas@arm.com, mark.rutland@arm.com Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 2/5] dt-bindings: ARM: Add recent Cortex/Neoverse PMUs Date: Fri, 21 Feb 2020 19:35:29 +0000 Message-Id: <3954ca0b86641e5e6a1935886df6658b9305ec4a.1582312530.git.robin.murphy@arm.com> X-Mailer: git-send-email 2.23.0.dirty In-Reply-To: References: MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add new PMU definitions to correspond with the CPU bindings. Signed-off-by: Robin Murphy --- v2: no change, just resending for completeness Documentation/devicetree/bindings/arm/pmu.yaml | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/pmu.yaml b/Documentation/devicetree/bindings/arm/pmu.yaml index 52ae094ce330..cc52195d0e9e 100644 --- a/Documentation/devicetree/bindings/arm/pmu.yaml +++ b/Documentation/devicetree/bindings/arm/pmu.yaml @@ -21,11 +21,20 @@ properties: - enum: - apm,potenza-pmu - arm,armv8-pmuv3 + - arm,neoverse-n1-pmu + - arm,neoverse-e1-pmu + - arm,cortex-a77-pmu + - arm,cortex-a76-pmu + - arm,cortex-a75-pmu - arm,cortex-a73-pmu - arm,cortex-a72-pmu + - arm,cortex-a65-pmu - arm,cortex-a57-pmu + - arm,cortex-a55-pmu - arm,cortex-a53-pmu - arm,cortex-a35-pmu + - arm,cortex-a34-pmu + - arm,cortex-a32-pmu - arm,cortex-a17-pmu - arm,cortex-a15-pmu - arm,cortex-a12-pmu From patchwork Fri Feb 21 19:35:30 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robin Murphy X-Patchwork-Id: 1242321 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=arm.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 48PMBP0wWPz9sRY for ; Sat, 22 Feb 2020 06:35:41 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726725AbgBUTfk (ORCPT ); Fri, 21 Feb 2020 14:35:40 -0500 Received: from foss.arm.com ([217.140.110.172]:46660 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726160AbgBUTfj (ORCPT ); Fri, 21 Feb 2020 14:35:39 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 7F289101E; Fri, 21 Feb 2020 11:35:39 -0800 (PST) Received: from e121345-lin.cambridge.arm.com (e121345-lin.cambridge.arm.com [10.1.196.37]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id B57D83F6CF; Fri, 21 Feb 2020 11:35:38 -0800 (PST) From: Robin Murphy To: will@kernel.org, catalin.marinas@arm.com, mark.rutland@arm.com Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 3/5] dt-bindings: ARM: Clean up PMU compatible list Date: Fri, 21 Feb 2020 19:35:30 +0000 Message-Id: <397df7accd295d2f743830591facbd2fb99208af.1582312530.git.robin.murphy@arm.com> X-Mailer: git-send-email 2.23.0.dirty In-Reply-To: References: MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The "alpha by vendor, reverse-alpha by model" sorting of compatibles that we seem to have ended up with is decidedly odd. Make it less so. Also copy the comment from the generic "arm,armv8" CPU binding to help clarify that the "arm,armv8-pmuv3" binding is rather intended to be a counterpart to that, for describing implementations without a specific microarchitecture like the AEMv8 software model. Signed-off-by: Robin Murphy --- v3: new - can be squashed or reordered with #2/5 if desired .../devicetree/bindings/arm/pmu.yaml | 50 +++++++++---------- 1 file changed, 25 insertions(+), 25 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/pmu.yaml b/Documentation/devicetree/bindings/arm/pmu.yaml index cc52195d0e9e..97df36d301c9 100644 --- a/Documentation/devicetree/bindings/arm/pmu.yaml +++ b/Documentation/devicetree/bindings/arm/pmu.yaml @@ -20,36 +20,36 @@ properties: items: - enum: - apm,potenza-pmu - - arm,armv8-pmuv3 - - arm,neoverse-n1-pmu - - arm,neoverse-e1-pmu - - arm,cortex-a77-pmu - - arm,cortex-a76-pmu - - arm,cortex-a75-pmu - - arm,cortex-a73-pmu - - arm,cortex-a72-pmu - - arm,cortex-a65-pmu - - arm,cortex-a57-pmu - - arm,cortex-a55-pmu - - arm,cortex-a53-pmu - - arm,cortex-a35-pmu - - arm,cortex-a34-pmu - - arm,cortex-a32-pmu - - arm,cortex-a17-pmu - - arm,cortex-a15-pmu - - arm,cortex-a12-pmu - - arm,cortex-a9-pmu - - arm,cortex-a8-pmu - - arm,cortex-a7-pmu - - arm,cortex-a5-pmu - - arm,arm11mpcore-pmu - - arm,arm1176-pmu + - arm,armv8-pmuv3 # Only for s/w models - arm,arm1136-pmu + - arm,arm1176-pmu + - arm,arm11mpcore-pmu + - arm,cortex-a5-pmu + - arm,cortex-a7-pmu + - arm,cortex-a8-pmu + - arm,cortex-a9-pmu + - arm,cortex-a12-pmu + - arm,cortex-a15-pmu + - arm,cortex-a17-pmu + - arm,cortex-a32-pmu + - arm,cortex-a34-pmu + - arm,cortex-a35-pmu + - arm,cortex-a53-pmu + - arm,cortex-a55-pmu + - arm,cortex-a57-pmu + - arm,cortex-a65-pmu + - arm,cortex-a72-pmu + - arm,cortex-a73-pmu + - arm,cortex-a75-pmu + - arm,cortex-a76-pmu + - arm,cortex-a77-pmu + - arm,neoverse-e1-pmu + - arm,neoverse-n1-pmu - brcm,vulcan-pmu - cavium,thunder-pmu + - qcom,krait-pmu - qcom,scorpion-pmu - qcom,scorpion-mp-pmu - - qcom,krait-pmu interrupts: # Don't know how many CPUs, so no constraints to specify