From patchwork Mon Feb 17 14:44:11 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vladimir Oltean X-Patchwork-Id: 1239288 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: patchwork-incoming-netdev@ozlabs.org Delivered-To: patchwork-incoming-netdev@ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=netdev-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=pOC8mE/7; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 48LmwC0vVlz9sRN for ; Tue, 18 Feb 2020 01:44:27 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729217AbgBQOoX (ORCPT ); Mon, 17 Feb 2020 09:44:23 -0500 Received: from mail-wm1-f66.google.com ([209.85.128.66]:40757 "EHLO mail-wm1-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728798AbgBQOoW (ORCPT ); Mon, 17 Feb 2020 09:44:22 -0500 Received: by mail-wm1-f66.google.com with SMTP id t14so18738010wmi.5; Mon, 17 Feb 2020 06:44:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=fYOm0c6Wq8+JdA+av6JaNbF89Lpk98DTtPwQkUkGoO0=; b=pOC8mE/7xlzVJZkKjxtN7wWpmPHu/f/tJkKakRwbXKQlFLQ/LkwWMRI+cAWKaYM0u/ xAhFFvs9hBUfOXgmaaP5Gti97ui9q/JduIYiShIhlLPDoCkatKdse57ReBrmrykk4n5C eXZQ0b/PvY4A77hX8QmvKIrMV5+BWNhJRTAcDbBHpAj13zb/xtSW3L9IKg3ATinWMUxr 4ZA9bOvWQ/feXPgfSGtpl8N0z1+fEnowlW/XRUc2SLBzbq5q6Czmgm2/wr6qdHZGqmAO nJBwUThNeesyQLiQnVE03NY6I6VWFGzyPkEF1rvubWlkfUAbWDSBgZitS9khw6aDldgj H0XA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=fYOm0c6Wq8+JdA+av6JaNbF89Lpk98DTtPwQkUkGoO0=; b=rtLee9pzu44JCOBD/4PC8vhXjWOjXs3zvf1zI3+MbGzqm9wJ0f4ycv3s9FwdPMNRmZ Pg0SF17Qo50oj6Spj7VIw+sT97ljAIILHLb0KoQEn1W18PWawh1Bpd9e/ci/Qxmt/GVo TFsZ0POlzuMJT0bq3k9mSjAex3FaSccvmLzOsipXA2vw4upYtD84Oe8KJuvfudT+Zjg1 1PTRSyetVOZDeLHU9mp8d29bifrETOTpVeC/HNLGW3HVt1aDqK+5LX/p+jSbzV8Yigo+ Kywo9BvGXrhaAIB66P1tFAX1WKKldv7UWVmCa38EwOTK8uoHhcB2fBLF2d0o1Dy1E5pW AmcQ== X-Gm-Message-State: APjAAAX7glUnia8vjFItugYcpbSciGvnamtS1lahEu602CYrC9gl0ehW dSE5m9LcAoPAYgbPeEyNvw4= X-Google-Smtp-Source: APXvYqxDuXJIQFYMIV1ZOU+5DG84y1Tpxf4v+9gyIdkVcVh8HzM47zm8T8IQfTHwnu+kW/RN7QZxww== X-Received: by 2002:a1c:960c:: with SMTP id y12mr22462178wmd.9.1581950660618; Mon, 17 Feb 2020 06:44:20 -0800 (PST) Received: from localhost.localdomain ([79.115.60.40]) by smtp.gmail.com with ESMTPSA id j5sm1381699wrb.33.2020.02.17.06.44.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 Feb 2020 06:44:20 -0800 (PST) From: Vladimir Oltean To: shawnguo@kernel.org, robh+dt@kernel.org, mark.rutland@arm.com, devicetree@vger.kernel.org Cc: andrew@lunn.ch, vivien.didelot@gmail.com, f.fainelli@gmail.com, davem@davemloft.net, netdev@vger.kernel.org, linux-kernel@vger.kernel.org, Vladimir Oltean Subject: [PATCH devicetree 1/4] arm64: dts: fsl: ls1028a: delete extraneous #interrupt-cells for ENETC RCIE Date: Mon, 17 Feb 2020 16:44:11 +0200 Message-Id: <20200217144414.409-2-olteanv@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200217144414.409-1-olteanv@gmail.com> References: <20200217144414.409-1-olteanv@gmail.com> Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org From: Vladimir Oltean This specifier overrides the interrupt specifier with 3 cells from gic (/interrupt-controller@6000000), but in fact ENETC is not an interrupt controller, so the property is bogus. Interrupts used by the children of the ENETC RCIE must use the full 3-cell specifier required by the GIC. Fixes: 927d7f857542 ("arm64: dts: fsl: ls1028a: Add PCI IERC node and ENETC endpoints") Signed-off-by: Vladimir Oltean --- arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi index 0bf375ec959b..dfead691e509 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi @@ -683,7 +683,6 @@ reg = <0x01 0xf0000000 0x0 0x100000>; #address-cells = <3>; #size-cells = <2>; - #interrupt-cells = <1>; msi-parent = <&its>; device_type = "pci"; bus-range = <0x0 0x0>; From patchwork Mon Feb 17 14:44:12 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vladimir Oltean X-Patchwork-Id: 1239289 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: patchwork-incoming-netdev@ozlabs.org Delivered-To: patchwork-incoming-netdev@ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=netdev-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=YU5jZu9s; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 48LmwC4XXWz9sRf for ; Tue, 18 Feb 2020 01:44:27 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729247AbgBQOo0 (ORCPT ); Mon, 17 Feb 2020 09:44:26 -0500 Received: from mail-wr1-f65.google.com ([209.85.221.65]:34102 "EHLO mail-wr1-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728104AbgBQOoY (ORCPT ); Mon, 17 Feb 2020 09:44:24 -0500 Received: by mail-wr1-f65.google.com with SMTP id n10so18101178wrm.1; Mon, 17 Feb 2020 06:44:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=L4M/ibBBRdcqDYZGaD9/OlVhGEQv3shq3kw51JTm0KM=; b=YU5jZu9svKTVWPQ+6ocBvta8tqZbBcXdz9ulODnNhS76nfcXd386TRBmc34EKZIiMW zYpfNzMmRuD1tHimyBeO9U18ptBsSlTw+9ZuCra9UVnirkEKpKqisfyGoN7fcR3w0MZg 2W0pkD/sJbOpx5of2shxyHlVfz1B9A6eID5pgZFIlnMtZUWG1JLrOwiELUaw8hsRrgPp eLPiJCP3NqVYP5V4Pzd3tUkGuEK0IV84jfJX9TkQHATs+Gukh5Nn/wQMcWDJSWB1P+8T o14mmXfRvShTatkJnvi8g7n01Lm5zGmSAEOzWy571SvnJzvWZw1ZaouW9UQK6xH91cw7 ym1Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=L4M/ibBBRdcqDYZGaD9/OlVhGEQv3shq3kw51JTm0KM=; b=NmIvpWd13G7JWw5lJdrWvcheNZPLMjmNMp74BHjOAlGmZAa8qHT8YOmylCsIMM6/LV 5b4iLKEahKHCSx/y6F8qV6dSMxqpy75Jm9PiYxlsMQw9VqLVfq5oVRdevPnI1z+Z4ZqV 5gxsEYiVHBVpseqhoQehf6Ga05mbTEI31o35M3KOziOkXCIAg/qCY88r5WmPpfhrLEwX /p05CEHxAOqhs270u1kM7UgeFI6QgF1V5Ed7RY93ViuPLH7rqGVCmVFRlLJCKuU18Sn4 qTQL+2cGAvNor8XSMz9gBJlM3pel0VN14BB/InvEvRdyl+gdos2skJsCLPeHwg4cEoEU zt1g== X-Gm-Message-State: APjAAAUUSxxiyMgG/inpEiIMxvurzMZ7tl1N4Tps0/3Io6oYmxTcHhsn s1NtIOIfF8ey55iGBD5quVg= X-Google-Smtp-Source: APXvYqypIBVkDqVgdwGHtEStvxGHrdKhi7scsYwoccRe8yz3FX4uCVK5kVhTORUNKP/zA62yk/DG5Q== X-Received: by 2002:a5d:6452:: with SMTP id d18mr22102588wrw.303.1581950662118; Mon, 17 Feb 2020 06:44:22 -0800 (PST) Received: from localhost.localdomain ([79.115.60.40]) by smtp.gmail.com with ESMTPSA id j5sm1381699wrb.33.2020.02.17.06.44.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 Feb 2020 06:44:21 -0800 (PST) From: Vladimir Oltean To: shawnguo@kernel.org, robh+dt@kernel.org, mark.rutland@arm.com, devicetree@vger.kernel.org Cc: andrew@lunn.ch, vivien.didelot@gmail.com, f.fainelli@gmail.com, davem@davemloft.net, netdev@vger.kernel.org, linux-kernel@vger.kernel.org, Vladimir Oltean Subject: [PATCH devicetree 2/4] dt-bindings: net: dsa: ocelot: document the vsc9959 core Date: Mon, 17 Feb 2020 16:44:12 +0200 Message-Id: <20200217144414.409-3-olteanv@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200217144414.409-1-olteanv@gmail.com> References: <20200217144414.409-1-olteanv@gmail.com> Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org From: Vladimir Oltean This patch adds the required documentation for the embedded L2 switch inside the NXP LS1028A chip. I've submitted it in the legacy format instead of yaml schema, because DSA itself has not yet been converted to yaml, and this driver defines no custom bindings. Signed-off-by: Vladimir Oltean --- .../devicetree/bindings/net/dsa/ocelot.txt | 97 +++++++++++++++++++ 1 file changed, 97 insertions(+) create mode 100644 Documentation/devicetree/bindings/net/dsa/ocelot.txt diff --git a/Documentation/devicetree/bindings/net/dsa/ocelot.txt b/Documentation/devicetree/bindings/net/dsa/ocelot.txt new file mode 100644 index 000000000000..6afd677c6ac0 --- /dev/null +++ b/Documentation/devicetree/bindings/net/dsa/ocelot.txt @@ -0,0 +1,97 @@ +Microchip Ocelot switch driver family +===================================== + +Felix +----- + +The VSC9959 core is currently the only switch supported by the driver, and is +found in the NXP LS1028A. It is a PCI device, part of the larger ENETC root +complex. As a result, the ethernet-switch node is a sub-node of the PCIe root +complex node and its "reg" property conforms to the parent node bindings: + +* reg: Specifies PCIe Device Number and Function Number of the endpoint device, + in this case for the Ethernet L2Switch it is PF5 (of device 0, bus 0). + +It does not require a "compatible" string. + +The interrupt line is used to signal availability of PTP TX timestamps and for +TSN frame preemption. + +For the external switch ports, depending on board configuration, "phy-mode" and +"phy-handle" are populated by board specific device tree instances. Ports 4 and +5 are fixed as internal ports in the NXP LS1028A instantiation. + +Any port can be disabled, but the CPU port should be kept enabled. + +The CPU port property ("ethernet"), which is assigned by default to the 2.5Gbps +port@4, can be moved to the 1Gbps port@5, depending on the specific use case. +DSA tagging is supported on a single port at a time. + +For the rest of the device tree binding definitions, which are standard DSA and +PCI, refer to the following documents: + +Documentation/devicetree/bindings/net/dsa/dsa.txt +Documentation/devicetree/bindings/pci/pci.txt + +Example: + +&soc { + pcie@1f0000000 { /* Integrated Endpoint Root Complex */ + ethernet-switch@0,5 { + reg = <0x000500 0 0 0 0>; + /* IEP INT_B */ + interrupts = ; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + /* External ports */ + port@0 { + reg = <0>; + label = "swp0"; + }; + + port@1 { + reg = <1>; + label = "swp1"; + }; + + port@2 { + reg = <2>; + label = "swp2"; + }; + + port@3 { + reg = <3>; + label = "swp3"; + }; + + /* Internal CPU port */ + port@4 { + reg = <4>; + ethernet = <&enetc_port2>; + phy-mode = "gmii"; + + fixed-link { + speed = <2500>; + full-duplex; + }; + }; + + /* Internal non-CPU port */ + port@5 { + reg = <5>; + phy-mode = "gmii"; + status = "disabled"; + + fixed-link { + speed = <1000>; + full-duplex; + pause; + }; + }; + }; + }; + }; +}; From patchwork Mon Feb 17 14:44:13 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vladimir Oltean X-Patchwork-Id: 1239292 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: patchwork-incoming-netdev@ozlabs.org Delivered-To: patchwork-incoming-netdev@ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=netdev-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; 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Mon, 17 Feb 2020 06:44:22 -0800 (PST) From: Vladimir Oltean To: shawnguo@kernel.org, robh+dt@kernel.org, mark.rutland@arm.com, devicetree@vger.kernel.org Cc: andrew@lunn.ch, vivien.didelot@gmail.com, f.fainelli@gmail.com, davem@davemloft.net, netdev@vger.kernel.org, linux-kernel@vger.kernel.org, Claudiu Manoil Subject: [PATCH devicetree 3/4] arm64: dts: fsl: ls1028a: add node for Felix switch Date: Mon, 17 Feb 2020 16:44:13 +0200 Message-Id: <20200217144414.409-4-olteanv@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200217144414.409-1-olteanv@gmail.com> References: <20200217144414.409-1-olteanv@gmail.com> Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org From: Claudiu Manoil Add the switch device node, available on PF5, so that the switch port sub-nodes (net devices) can be linked to corresponding board specific phy nodes (external ports) or have their link mode defined (internal ports). The switch device features 6 ports, 4 with external links and 2 internally facing to the LS1028A SoC and connected via fixed links to 2 internal ENETC Ethernet controller ports. Add the corresponding ENETC host port device nodes, mapped to PF2 and PF6 PCIe functions. Since the switch only supports tagging on one CPU port, only one port pair (swp4, eno2) is enabled by default and the other, lower speed, port pair is disabled to prevent the PCI core from probing them. If enabled, swp5 will be a fixed-link slave port. DSA tagging can also be moved from the swp4-eno2 2.5G port pair to the 1G swp5-eno3 pair by changing the ethernet = <&enetc_port2> phandle to <&enetc_port3> and moving it under port5, but in that case enetc_port2 should not be disabled, because it is the hardware owner of the Felix PCS and disabling its memory would result in access faults in the Felix DSA driver. All ports are disabled by default, except one CPU port. The switch's INTB interrupt line signals: - PTP timestamp ready in timestamp FIFO - TSN Frame Preemption And don't forget to enable the 4MB BAR4 in the root complex ECAM space, where the switch registers are mapped. Signed-off-by: Claudiu Manoil Signed-off-by: Alex Marginean Signed-off-by: Yangbo Lu Signed-off-by: Vladimir Oltean --- .../arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 84 ++++++++++++++++++- 1 file changed, 83 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi index dfead691e509..b35679dbcaa7 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi @@ -700,7 +700,9 @@ /* PF1: VF0-1 BAR0 - non-prefetchable memory */ 0x82000000 0x0 0x00000000 0x1 0xf8210000 0x0 0x020000 /* PF1: VF0-1 BAR2 - prefetchable memory */ - 0xc2000000 0x0 0x00000000 0x1 0xf8230000 0x0 0x020000>; + 0xc2000000 0x0 0x00000000 0x1 0xf8230000 0x0 0x020000 + /* BAR4 (PF5) - non-prefetchable memory */ + 0x82000000 0x0 0x00000000 0x1 0xfc000000 0x0 0x400000>; enetc_port0: ethernet@0,0 { compatible = "fsl,enetc"; @@ -710,6 +712,18 @@ compatible = "fsl,enetc"; reg = <0x000100 0 0 0 0>; }; + + enetc_port2: ethernet@0,2 { + compatible = "fsl,enetc"; + reg = <0x000200 0 0 0 0>; + phy-mode = "gmii"; + + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + enetc_mdio_pf3: mdio@0,3 { compatible = "fsl,enetc-mdio"; reg = <0x000300 0 0 0 0>; @@ -722,6 +736,74 @@ clocks = <&clockgen 4 0>; little-endian; }; + + ethernet-switch@0,5 { + reg = <0x000500 0 0 0 0>; + /* IEP INT_B */ + interrupts = ; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + /* external ports */ + mscc_felix_port0: port@0 { + reg = <0>; + status = "disabled"; + }; + + mscc_felix_port1: port@1 { + reg = <1>; + status = "disabled"; + }; + + mscc_felix_port2: port@2 { + reg = <2>; + status = "disabled"; + }; + + mscc_felix_port3: port@3 { + reg = <3>; + status = "disabled"; + }; + + /* Internal port with DSA tagging */ + mscc_felix_port4: port@4 { + reg = <4>; + phy-mode = "gmii"; + ethernet = <&enetc_port2>; + + fixed-link { + speed = <2500>; + full-duplex; + }; + }; + + /* Internal port without DSA tagging */ + mscc_felix_port5: port@5 { + reg = <5>; + phy-mode = "gmii"; + status = "disabled"; + + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + }; + }; + + enetc_port3: ethernet@0,6 { + compatible = "fsl,enetc"; + reg = <0x000600 0 0 0 0>; + status = "disabled"; + phy-mode = "gmii"; + + fixed-link { + speed = <1000>; + full-duplex; + }; + }; }; }; From patchwork Mon Feb 17 14:44:14 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vladimir Oltean X-Patchwork-Id: 1239290 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: patchwork-incoming-netdev@ozlabs.org Delivered-To: patchwork-incoming-netdev@ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=netdev-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; 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Mon, 17 Feb 2020 06:44:24 -0800 (PST) From: Vladimir Oltean To: shawnguo@kernel.org, robh+dt@kernel.org, mark.rutland@arm.com, devicetree@vger.kernel.org Cc: andrew@lunn.ch, vivien.didelot@gmail.com, f.fainelli@gmail.com, davem@davemloft.net, netdev@vger.kernel.org, linux-kernel@vger.kernel.org, Claudiu Manoil Subject: [PATCH devicetree 4/4] arm64: dts: fsl: ls1028a: enable switch PHYs on RDB Date: Mon, 17 Feb 2020 16:44:14 +0200 Message-Id: <20200217144414.409-5-olteanv@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200217144414.409-1-olteanv@gmail.com> References: <20200217144414.409-1-olteanv@gmail.com> Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org From: Claudiu Manoil Link the switch PHY nodes to the central MDIO controller PCIe endpoint node on LS1028A (implemented as PF3) so that PHYs are accessible via MDIO. Enable SGMII AN on the Felix PCS by telling PHYLINK that the VSC8514 quad PHY is capable of in-band-status. The PHYs are used in poll mode due to an issue with the interrupt line on current revisions of the LS1028A-RDB board. Signed-off-by: Claudiu Manoil Signed-off-by: Alex Marginean Signed-off-by: Vladimir Oltean Reviewed-by: Andrew Lunn --- .../boot/dts/freescale/fsl-ls1028a-rdb.dts | 51 +++++++++++++++++++ 1 file changed, 51 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts index afb55653850d..9353c00e46a7 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts @@ -194,6 +194,57 @@ status = "disabled"; }; +&enetc_mdio_pf3 { + /* VSC8514 QSGMII quad PHY */ + qsgmii_phy0: ethernet-phy@10 { + reg = <0x10>; + }; + + qsgmii_phy1: ethernet-phy@11 { + reg = <0x11>; + }; + + qsgmii_phy2: ethernet-phy@12 { + reg = <0x12>; + }; + + qsgmii_phy3: ethernet-phy@13 { + reg = <0x13>; + }; +}; + +&mscc_felix_port0 { + status = "okay"; + label = "swp0"; + managed = "in-band-status"; + phy-handle = <&qsgmii_phy0>; + phy-mode = "qsgmii"; +}; + +&mscc_felix_port1 { + status = "okay"; + label = "swp1"; + managed = "in-band-status"; + phy-handle = <&qsgmii_phy1>; + phy-mode = "qsgmii"; +}; + +&mscc_felix_port2 { + status = "okay"; + label = "swp2"; + managed = "in-band-status"; + phy-handle = <&qsgmii_phy2>; + phy-mode = "qsgmii"; +}; + +&mscc_felix_port3 { + status = "okay"; + label = "swp3"; + managed = "in-band-status"; + phy-handle = <&qsgmii_phy3>; + phy-mode = "qsgmii"; +}; + &sai4 { status = "okay"; };